Merge branch 'lt-3.2-imx5' into topic/lt-3.2-imx6-uglytopic/lt-3.2-imx6-ugly

* lt-3.2-imx5: (124 commits)
  SAUCE: fix the missing header of <linux/module.h>
  SAUCE: fix the removal of mxc_register_device()
  SAUCE: mx53_loco: fix gpio_to_irq() being non-constant
  SAUCE: fix building errors after rebased to v3.2
  LINARO: Add lt-mx5_defconfig
  ARM i.MX5: fix system_rev if not set by atag or DT
  ENGR00162701 mxc_vout: fix potential deadlock of fb_blank
  ENGR00162666 mxc_vout: v4l2 playback blocking issue
  ENGR00162665 ipuv3 fb: fix non-interleave format wrong color issue
  ENGR00162664 mxc_vout: modify pp bypass condition
  ENGR00162663 ipuv3 fb: add vertical flip support
  ENGR00162475 ipuv3 fb: fix camera preview failure
  ENGR00162360 mxc_vout: fix STREAMOFF and G_CROP issues
  ENGR00162358 ipuv3 fb: only check pos when fb is unblank
  ENGR00162354 ipuv3 device: correct kthread operation for split task
  SAUCE: mx53: add mxc_lcdif support
  SAUCE: add arm-pmu device
  SAUCE: remove unnecessary suspend/resume functions from mxc_spdif
  ENGR00162218 mxc_vout: put set position function before set var
  ENGR00162208 ipuv3 device: fix jitter issue of split mode
  ...

297 files changed, 336274 insertions, 316 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b259c7c644e..0d9bfb600e9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1700,6 +1700,7 @@ config FORCE_MAX_ZONEORDER
 	int "Maximum zone order" if ARCH_SHMOBILE
 	range 11 64 if ARCH_SHMOBILE
 	default "9" if SA1111
+	default "14" if ARCH_MX5
 	default "11"
 	help
 	  The kernel memory allocator divides physically contiguous memory
diff --git a/arch/arm/configs/lt-mx5_defconfig b/arch/arm/configs/lt-mx5_defconfig
new file mode 100644
index 00000000000..cb080218092
--- /dev/null
+++ b/arch/arm/configs/lt-mx5_defconfig
@@ -0,0 +1,2323 @@
+#
+# Common config options automatically generated by splitconfig.pl
+#
+# CONFIG_ABX500_CORE is not set
+CONFIG_AC97_BUS=y
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ADFS_FS is not set
+CONFIG_AEABI=y
+# CONFIG_AFFS_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_AIO=y
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_AMIGA_PARTITION is not set
+CONFIG_ANON_INODES=y
+# CONFIG_APDS9802ALS is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_EXYNOS4 is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_H720X is not set
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MX1 is not set
+# CONFIG_ARCH_MX2 is not set
+# CONFIG_ARCH_MX25 is not set
+# CONFIG_ARCH_MX3 is not set
+CONFIG_ARCH_MX5=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_MXC_AUDMUX_V2=y
+CONFIG_ARCH_MXC_IOMUX_V3=y
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PRIMA2 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_REALVIEW is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VT8500 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_ZYNQ is not set
+CONFIG_ARM=y
+# CONFIG_ARM_APPENDED_DTB is not set
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+# CONFIG_ARM_KPROBES_TEST is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_ARPD is not set
+# CONFIG_ASYNC_TX_DMA is not set
+CONFIG_AT76C50X_USB=m
+CONFIG_ATA=y
+CONFIG_ATAGS_PROC=y
+# CONFIG_ATALK is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_ATA_BMDMA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_ATA_SFF=y
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_ATH9K is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+# CONFIG_ATM is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+CONFIG_AUDIT=y
+CONFIG_AUDIT_GENERIC=y
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_AUXDISPLAY is not set
+CONFIG_AVERAGE=y
+# CONFIG_AX88796 is not set
+CONFIG_B43=m
+CONFIG_B43LEGACY=m
+CONFIG_B43LEGACY_DEBUG=y
+CONFIG_B43LEGACY_DMA=y
+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
+# CONFIG_B43LEGACY_DMA_MODE is not set
+CONFIG_B43LEGACY_HWRNG=y
+CONFIG_B43LEGACY_LEDS=y
+CONFIG_B43LEGACY_PIO=y
+# CONFIG_B43LEGACY_PIO_MODE is not set
+# CONFIG_B43_DEBUG is not set
+CONFIG_B43_HWRNG=y
+CONFIG_B43_LEDS=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PIO=y
+# CONFIG_B43_SDIO is not set
+CONFIG_B43_SSB=y
+# CONFIG_B44 is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_DA9052=m
+CONFIG_BACKLIGHT_GENERIC=m
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+CONFIG_BASE_FULL=y
+CONFIG_BASE_SMALL=0
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_DA9052 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_BCMA is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_BINARY_PRINTF=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=m
+CONFIG_BITREVERSE=y
+# CONFIG_BLK_CGROUP is not set
+CONFIG_BLK_DEV=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_BLK_DEV_DRBD is not set
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_RBD is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_BLOCK=y
+# CONFIG_BMP085 is not set
+# CONFIG_BONDING is not set
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_BOOT_PRINTK_DELAY is not set
+CONFIG_BOUNCE=y
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_BRIDGE is not set
+# CONFIG_BROADCOM_PHY is not set
+CONFIG_BROKEN_ON_SMP=y
+# CONFIG_BSD_DISKLABEL is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_BT=m
+CONFIG_BTRFS_FS=y
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+CONFIG_BT_HCIBCM203X=m
+# CONFIG_BT_HCIBFUSB is not set
+CONFIG_BT_HCIBPA10X=m
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIUART=m
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_L2CAP is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_SCO is not set
+CONFIG_BUG=y
+# CONFIG_C2PORT is not set
+# CONFIG_CAIF is not set
+# CONFIG_CAN is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CEPH_LIB is not set
+CONFIG_CFG80211=m
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_PERF is not set
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CIFS is not set
+# CONFIG_CLEANCACHE is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_DEBUG=y
+CONFIG_CMDLINE=""
+# CONFIG_CODA_FS is not set
+CONFIG_COMPACTION=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_POLL=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+# CONFIG_CORDIC is not set
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUSETS=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_IMX=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRAMFS=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+# CONFIG_CRC8 is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_COMPILE=""
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_BLOWFISH=m
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CCM is not set
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_DES is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+# CONFIG_CRYPTO_HMAC is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCBC is not set
+CONFIG_CRYPTO_PCOMP2=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_SERPENT=m
+# CONFIG_CRYPTO_SHA1 is not set
+CONFIG_CRYPTO_SHA256=m
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_VMAC is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_DA9052_GPIO_ENABLE=y
+CONFIG_DA9052_WATCHDOG=m
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_DCB is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_HIGHMEM is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_LOCKDEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_DEBUG_LOCK_ALLOC=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DECNET is not set
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_SECURITY="apparmor"
+CONFIG_DEFAULT_SECURITY_APPARMOR=y
+# CONFIG_DEFAULT_SECURITY_DAC is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_DM9000 is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+# CONFIG_DMATEST is not set
+# CONFIG_DMA_API_DEBUG is not set
+CONFIG_DMA_ENGINE=y
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_DEBUG is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DNET is not set
+CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
+# CONFIG_DRAGONRISE_FF is not set
+# CONFIG_DRM is not set
+# CONFIG_DS1682 is not set
+CONFIG_DTC=y
+# CONFIG_DUMMY is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_DVB_CORE is not set
+# CONFIG_DW_DMAC is not set
+# CONFIG_DW_WATCHDOG is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+CONFIG_DYNAMIC_FTRACE=y
+# CONFIG_ECONET is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_EFS_FS is not set
+CONFIG_ELF_CORE=y
+# CONFIG_EMBEDDED is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_EPOLL=y
+# CONFIG_EQUALIZER is not set
+# CONFIG_ETHOC is not set
+CONFIG_EVENTFD=y
+CONFIG_EVENT_POWER_TRACING_DEPRECATED=y
+CONFIG_EVENT_TRACING=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXPERT=y
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_EZX_PCAP is not set
+# CONFIG_FANOTIFY is not set
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_FAT_FS=y
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_FB=y
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_METRONOME is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_MXC=y
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_SII902X=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+CONFIG_FB_MXC_TVOUT_TVE=y
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_TILEBLITTING is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+CONFIG_FEC=y
+# CONFIG_FHANDLE is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FIQ=y
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FIRMWARE_IN_KERNEL=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_FLATMEM=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_FPE_NWFPE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=1024
+CONFIG_FREEZER=y
+# CONFIG_FSCACHE is not set
+CONFIG_FSNOTIFY=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_FTGMAC100 is not set
+# CONFIG_FTL is not set
+# CONFIG_FTMAC100 is not set
+CONFIG_FTRACE=y
+CONFIG_FTRACE_MCOUNT_RECORD=y
+# CONFIG_FTRACE_STARTUP_TEST is not set
+CONFIG_FUNCTION_GRAPH_TRACER=y
+# CONFIG_FUNCTION_PROFILER is not set
+CONFIG_FUNCTION_TRACER=y
+# CONFIG_FUSE_FS is not set
+CONFIG_FUTEX=y
+CONFIG_FW_LOADER=y
+# CONFIG_GAMEPORT is not set
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_GENERIC_ACL=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_TRACER=y
+# CONFIG_GFS2_FS is not set
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_ADP5588 is not set
+CONFIG_GPIO_GENERIC=y
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+CONFIG_GPIO_MXC=y
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+CONFIG_GPIO_SYSFS=y
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_AOUT=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_PWM=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SCHED_CLOCK=y
+CONFIG_HAVE_SPARSE_IRQ=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+CONFIG_HID_A4TECH=y
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
+# CONFIG_HID_EMS_FF is not set
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GREENASIA=y
+CONFIG_HID_GYRATION=y
+# CONFIG_HID_HOLTEK is not set
+CONFIG_HID_KENSINGTON=y
+# CONFIG_HID_KEYTOUCH is not set
+CONFIG_HID_KYE=y
+# CONFIG_HID_LCPOWER is not set
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_MULTITOUCH is not set
+CONFIG_HID_NTRIG=y
+# CONFIG_HID_ORTEK is not set
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PID is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_HID_SONY=y
+# CONFIG_HID_SPEEDLINK is not set
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_TWINHAN=y
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+CONFIG_HID_ZEROPLUS=y
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_HMC6352 is not set
+# CONFIG_HOSTAP is not set
+CONFIG_HOTPLUG=y
+# CONFIG_HPFS_FS is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_HVC_DCC is not set
+CONFIG_HWMON=m
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_HWMON_VID is not set
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_HZ=100
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_IDE is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IMA is not set
+CONFIG_IMX2_WDT=y
+CONFIG_IMX_HAVE_PLATFORM_AHCI=y
+CONFIG_IMX_HAVE_PLATFORM_FEC=y
+CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS=y
+CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_IIM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SRTC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_TVE=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
+CONFIG_IMX_HAVE_PLATFORM_LDB=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_GPU=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_NAND=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
+CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
+CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
+CONFIG_IMX_SDMA=y
+CONFIG_INET=y
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET_AH is not set
+CONFIG_INET_DIAG=y
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INFTL is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_INPUT=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_CMA3000 is not set
+CONFIG_INPUT_DA9052_ONKEY=m
+# CONFIG_INPUT_EVBUG is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+CONFIG_INPUT_JOYDEV=y
+# CONFIG_INPUT_JOYSTICK is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MMA8450=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_PCF8574 is not set
+CONFIG_INPUT_POLLDEV=m
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_YEALINK is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPX is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_MROUTE is not set
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_IP_SCTP is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IRDA is not set
+# CONFIG_IRQSOFF_TRACER is not set
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISDN is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+CONFIG_ISO9660_FS=m
+# CONFIG_IWM is not set
+# CONFIG_IWMC3200TOP is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFS_FS is not set
+CONFIG_JOLIET=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_KEXEC=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+CONFIG_KEYBOARD_IMX=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+CONFIG_KGDB=y
+# CONFIG_KGDB_KDB is not set
+CONFIG_KGDB_SERIAL_CONSOLE=y
+# CONFIG_KGDB_TESTS is not set
+CONFIG_KPROBES=y
+CONFIG_KPROBES_SANITY_TEST=y
+CONFIG_KPROBE_EVENT=y
+CONFIG_KRETPROBES=y
+# CONFIG_KS8842 is not set
+CONFIG_KS8851=y
+CONFIG_KS8851_MLL=y
+# CONFIG_KSM is not set
+CONFIG_KTIME_SCALAR=y
+# CONFIG_L2TP is not set
+# CONFIG_LAPB is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_LBDAF=y
+# CONFIG_LCD_AMS369FG06 is not set
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_LEDS_BD2802 is not set
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_DA9052=m
+# CONFIG_LEDS_DAC124S085 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_REGISTER=y
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_LIBCRC32C=y
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_MESH is not set
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_LKDTM is not set
+# CONFIG_LLC2 is not set
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKDEP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_LOCKD_V4=y
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_LOGFS is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIWII_FF is not set
+# CONFIG_LOGO is not set
+CONFIG_LOG_BUF_SHIFT=18
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_LSM_MMAP_MIN_ADDR=0
+# CONFIG_LXT_PHY is not set
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAC80211=m
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_HWSIM=m
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MACH_EUKREA_CPUIMX51=y
+CONFIG_MACH_EUKREA_CPUIMX51SD=y
+CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD=y
+CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD=y
+CONFIG_MACH_MX51_3DS=y
+CONFIG_MACH_MX51_BABBAGE=y
+CONFIG_MACH_MX51_EFIKAMX=y
+CONFIG_MACH_MX51_EFIKASB=y
+CONFIG_MACH_MX53_ARD=y
+CONFIG_MACH_MX53_EVK=y
+CONFIG_MACH_MX53_LOCO=y
+CONFIG_MACH_MX53_SMD=y
+# CONFIG_MACVLAN is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+CONFIG_MD=y
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MEDIA_ATTACH is not set
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_TUNER_CUSTOMISE=y
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_ASIC3 is not set
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MICREL_PHY is not set
+CONFIG_MIGRATION=y
+CONFIG_MII=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_MMC_BLOCK_MINORS=8
+# CONFIG_MMC_CLKGATE is not set
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_DW is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_TEST is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_VUB300 is not set
+CONFIG_MMU=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_GPIO is not set
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_AR7_PARTS is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_M25P80 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_MXC is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_OOPS=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PHYSMAP_OF is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SWAP is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MX51_EFIKA_COMMON=y
+CONFIG_MXC_AMD_GPU=m
+CONFIG_MXC_DEBUG_BOARD=y
+CONFIG_MXC_IIM=y
+CONFIG_MXC_IPU=y
+CONFIG_MXC_IPU_V3=y
+CONFIG_MXC_IPU_V3EX=y
+# CONFIG_MXC_IRQ_PRIOR is not set
+CONFIG_MXC_PWM=y
+CONFIG_MXC_TZIC=y
+CONFIG_MXC_VPU=y
+# CONFIG_MXC_VPU_DEBUG is not set
+CONFIG_NAMESPACES=y
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_NCP_FS is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NEON=y
+CONFIG_NET=y
+# CONFIG_NETCONSOLE is not set
+CONFIG_NETDEVICES=y
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_XTABLES is not set
+CONFIG_NETLABEL=y
+# CONFIG_NETPOLL is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NET_9P is not set
+# CONFIG_NET_DMA is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_NET_DSA is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_NET_IPIP is not set
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_NS is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_TCPPROBE is not set
+CONFIG_NEW_LEDS=y
+# CONFIG_NFC is not set
+# CONFIG_NFSD is not set
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+# CONFIG_NFTL is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_NF_DEFRAG_IPV6 is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_NL80211_TESTMODE is not set
+CONFIG_NLATTR=y
+CONFIG_NLS=y
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+CONFIG_NOP_TRACER=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ=y
+# CONFIG_NTFS_FS is not set
+# CONFIG_N_GSM is not set
+CONFIG_OABI_COMPAT=y
+# CONFIG_OC_ETM is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_SPI=y
+CONFIG_OLD_MCOUNT=y
+# CONFIG_OMFS_FS is not set
+CONFIG_OPROFILE=y
+# CONFIG_OSF_PARTITION is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_LEDS=y
+CONFIG_P54_SPI=m
+# CONFIG_P54_SPI_DEFAULT_EEPROM is not set
+CONFIG_P54_USB=m
+CONFIG_PACKET=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PAGE_OFFSET=0x80000000
+# CONFIG_PANTHERLORD_FF is not set
+# CONFIG_PARPORT is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_PATA_ARASAN_CF is not set
+# CONFIG_PATA_IMX is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PCCARD is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+# CONFIG_PHONE is not set
+# CONFIG_PHONET is not set
+CONFIG_PHYLIB=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+# CONFIG_PID_NS is not set
+# CONFIG_PLAT_SPEAR is not set
+CONFIG_PM=y
+# CONFIG_PMBUS is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_DA9052 is not set
+# CONFIG_PMIC_DA9053AA is not set
+CONFIG_PMIC_DA9053Bx=y
+CONFIG_PMIC_DIALOG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_SLEEP=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PPP is not set
+# CONFIG_PPS is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_PRINTK=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PROC_DEVICETREE is not set
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_FS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_VMCORE=y
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+CONFIG_PROFILING=y
+CONFIG_PROVE_LOCKING=y
+# CONFIG_PROVE_RCU is not set
+# CONFIG_PSTORE is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_R3964 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_RATIONAL=y
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_RCU_BOOST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_VERBOSE=y
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_RDS is not set
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+# CONFIG_REALTEK_PHY is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_DA9052=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+CONFIG_REGULATOR_TPS65023=y
+CONFIG_REGULATOR_TPS6507X=y
+# CONFIG_REGULATOR_TPS6524X is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REISERFS_FS is not set
+CONFIG_RELAY=y
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_RFKILL is not set
+# CONFIG_RFKILL_REGULATOR is not set
+CONFIG_RING_BUFFER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_ROOT_NFS=y
+CONFIG_RT2500USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00=m
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_LEDS=y
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT73USB=m
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DEBUG is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_DA9052=m
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+CONFIG_RTC_DRV_MXC_V2=y
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_MXC=y
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+CONFIG_RTL8192CU=m
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_RTL8192DE is not set
+CONFIG_RTL8192SE=m
+CONFIG_RTLWIFI=m
+CONFIG_RT_MUTEXES=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_SAMPLES is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_PMP is not set
+CONFIG_SCHEDSTATS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHED_TRACER is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_SCSI_MOD=y
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_SCSI_PROC_FS=y
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_TGT is not set
+CONFIG_SCSI_WAIT_SCAN=m
+CONFIG_SDIO_UART=y
+CONFIG_SECCOMP=y
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_APPARMOR=y
+CONFIG_SECURITY_APPARMOR_BOOTPARAM_VALUE=1
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY_NETWORK=y
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+CONFIG_SECURITY_PATH=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+# CONFIG_SECURITY_SELINUX_DISABLE is not set
+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
+CONFIG_SECURITY_SMACK=y
+# CONFIG_SECURITY_TOMOYO is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_DA9052 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_IFX6X60 is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+CONFIG_SERIO=y
+# CONFIG_SERIO_ALTERA_PS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_RAW is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SGI_PARTITION is not set
+CONFIG_SHMEM=y
+CONFIG_SIGNALFD=y
+CONFIG_SLAB=y
+CONFIG_SLABINFO=y
+# CONFIG_SLIP is not set
+# CONFIG_SLOB is not set
+# CONFIG_SLUB is not set
+# CONFIG_SMARTJOYPLUS_FF is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_SM_FTL is not set
+CONFIG_SND=y
+# CONFIG_SND_ALOOP is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_DEBUG=y
+# CONFIG_SND_DEBUG_VERBOSE is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_HWDEP=m
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_JACK=y
+CONFIG_SND_MIXER_OSS=m
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_MTPAV is not set
+CONFIG_SND_MXC_SOC_FIQ=y
+CONFIG_SND_MXC_SOC_MX2=y
+CONFIG_SND_MXC_SOC_SPDIF_DAI=y
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_PCM_XRUN_DEBUG is not set
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_CACHE_LZO=y
+CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_MXC_SPDIF=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_SND_SOC_TLV320AIC23=y
+CONFIG_SND_SPI=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_UA101 is not set
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SOC_CAMERA is not set
+CONFIG_SOC_IMX51=y
+CONFIG_SOC_IMX53=y
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_SPARSE_IRQ is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+CONFIG_SPI=y
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_DEBUG is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_IMX=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_XILINX is not set
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+# CONFIG_SQUASHFS is not set
+CONFIG_SSB=m
+CONFIG_SSB_BLOCKIO=y
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB_SDIOHOST is not set
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSFDC is not set
+CONFIG_STACKTRACE=y
+CONFIG_STACKTRACE_SUPPORT=y
+# CONFIG_STACK_TRACER is not set
+# CONFIG_STAGING is not set
+CONFIG_STANDALONE=y
+# CONFIG_STE10XP is not set
+# CONFIG_STMMAC_ETH is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUN_PARTITION is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWAP=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSCTL=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_SYSFS=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_TARGET_CORE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_TIMB_DMA is not set
+CONFIG_TIMERFD=y
+CONFIG_TIMER_STATS=y
+# CONFIG_TINY_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_TIPC is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_TI_ST is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+CONFIG_TOUCHSCREEN_ADS7846=m
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+CONFIG_TOUCHSCREEN_DA9052=m
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+CONFIG_TRACEPOINTS=y
+CONFIG_TRACE_IRQFLAGS=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_TRACE_SINK is not set
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_TREE_PREEMPT_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_TUN is not set
+# CONFIG_TWL4030_CORE is not set
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+# CONFIG_UBIFS_FS_DEBUG is not set
+CONFIG_UBIFS_FS_LZO=y
+# CONFIG_UBIFS_FS_XATTR is not set
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_UDF_FS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_UFS_FS is not set
+CONFIG_UID16=y
+CONFIG_UIO=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_UNIX=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_USB=y
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_ADUTUX is not set
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_ARC=m
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_AUDIO=m
+CONFIG_USB_BELKIN=y
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_CATC is not set
+CONFIG_USB_CDC_COMPOSITE=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_DEBUG=y
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DUMMY_HCD is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_EHCI_ARC=y
+CONFIG_USB_EHCI_ARC_OTG=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_EMI62 is not set
+CONFIG_USB_EPSON2888=y
+# CONFIG_USB_ET61X251 is not set
+CONFIG_USB_ETH=m
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_FSL_USB2 is not set
+# CONFIG_USB_FTDI_ELAN is not set
+CONFIG_USB_FUNCTIONFS=m
+# CONFIG_USB_FUNCTIONFS_ETH is not set
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+# CONFIG_USB_FUNCTIONFS_RNDIS is not set
+# CONFIG_USB_FUSB300 is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_GADGET_ARC=m
+CONFIG_USB_GADGET_DEBUG=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_GSPCA is not set
+# CONFIG_USB_G_DBGP is not set
+CONFIG_USB_G_HID=m
+CONFIG_USB_G_MULTI=m
+# CONFIG_USB_G_MULTI_CDC is not set
+CONFIG_USB_G_MULTI_RNDIS=y
+CONFIG_USB_G_NCM=m
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_G_WEBCAM is not set
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_KC2190=y
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_LEGOTOWER is not set
+CONFIG_USB_LIBUSUAL=y
+# CONFIG_USB_M66592 is not set
+CONFIG_USB_MASS_STORAGE=m
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_MON=y
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_NET2272 is not set
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_NCM=y
+CONFIG_USB_NET_CDC_SUBSET=y
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_GL620A is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_MCS7830 is not set
+CONFIG_USB_NET_NET1080=y
+# CONFIG_USB_NET_PLUSB is not set
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_USB_NET_SMSC75XX is not set
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_NET_ZAURUS=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_R8A66597 is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STATIC_IRAM is not set
+# CONFIG_USB_STKWEBCAM is not set
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+CONFIG_USB_TEST=y
+# CONFIG_USB_TMC is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_ULPI is not set
+CONFIG_USB_USBNET=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_VL600 is not set
+CONFIG_USB_WDM=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USER_NS is not set
+CONFIG_USE_OF=y
+CONFIG_UTMI_MXC=y
+# CONFIG_UTS_NS is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_VETH is not set
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEOBUF_GEN=y
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_AK881X is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_CX2341X is not set
+# CONFIG_VIDEO_CX25840 is not set
+CONFIG_VIDEO_DEV=y
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_M52790 is not set
+CONFIG_VIDEO_MEDIA=y
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+CONFIG_VIDEO_MXC_OUTPUT=y
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_SAA6588 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_TIMBERDALE is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_USBVISION is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+# CONFIG_VIDEO_VPX3220 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_VXFS_FS is not set
+CONFIG_W1=y
+CONFIG_W1_CON=y
+# CONFIG_W1_MASTER_DS1WM is not set
+# CONFIG_W1_MASTER_DS2482 is not set
+# CONFIG_W1_MASTER_DS2490 is not set
+# CONFIG_W1_MASTER_GPIO is not set
+CONFIG_W1_MASTER_MXC=y
+# CONFIG_W1_SLAVE_BQ27000 is not set
+# CONFIG_W1_SLAVE_DS2408 is not set
+# CONFIG_W1_SLAVE_DS2423 is not set
+# CONFIG_W1_SLAVE_DS2431 is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+# CONFIG_W1_SLAVE_DS2760 is not set
+# CONFIG_W1_SLAVE_DS2780 is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_WAN is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_CORE is not set
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PRIV=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+# CONFIG_WIMAX is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_WL1251=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL12XX=m
+CONFIG_WL12XX_HT=y
+CONFIG_WL12XX_MENU=m
+CONFIG_WL12XX_PLATFORM_DATA=y
+CONFIG_WL12XX_SDIO=m
+CONFIG_WL12XX_SDIO_TEST=m
+CONFIG_WL12XX_SPI=m
+CONFIG_WLAN=y
+# CONFIG_X25 is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_USER=y
+# CONFIG_XFS_FS is not set
+# CONFIG_XIP_KERNEL is not set
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_ZISOFS=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index af0c212e3c7..da99de76ae0 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -31,6 +31,11 @@ config	SOC_IMX51
 	select ARCH_MXC_AUDMUX_V2
 	select ARCH_HAS_CPUFREQ
 	select ARCH_MX51
+	select IMX_HAVE_PLATFORM_IMX_IIM
+	select IMX_HAVE_PLATFORM_IMX_IPUV3
+	select IMX_HAVE_PLATFORM_IMX_TVE
+	select IMX_HAVE_PLATFORM_IMX_VPU
+	select IMX_HAVE_PLATFORM_IMX_SPDIF
 
 config	SOC_IMX53
 	bool
@@ -38,7 +43,15 @@ config	SOC_IMX53
 	select ARM_L1_CACHE_SHIFT_6
 	select MXC_TZIC
 	select ARCH_MXC_IOMUX_V3
+	select ARCH_MXC_AUDMUX_V2
+	select ARCH_HAS_CPUFREQ
 	select ARCH_MX53
+	select IMX_HAVE_PLATFORM_IMX_IIM
+	select IMX_HAVE_PLATFORM_IMX_IPUV3
+	select IMX_HAVE_PLATFORM_IMX_TVE
+	select IMX_HAVE_PLATFORM_LDB
+	select IMX_HAVE_PLATFORM_IMX_VPU
+	select IMX_HAVE_PLATFORM_IMX_SPDIF
 
 #comment "i.MX50 machines:"
 
@@ -221,10 +234,14 @@ config MACH_MX53_LOCO
 	select SOC_IMX53
 	select IMX_HAVE_PLATFORM_IMX2_WDT
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_SRTC
 	select IMX_HAVE_PLATFORM_IMX_UART
+	select IMX_HAVE_PLATFORM_MXC_GPU
+	select IMX_HAVE_PLATFORM_MXC_PWM
 	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
 	select IMX_HAVE_PLATFORM_GPIO_KEYS
 	select LEDS_GPIO_REGISTER
+	select IMX_HAVE_PLATFORM_IMX_SSI
 	help
 	  Include support for MX53 LOCO platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0fc60807fa2..5411507ce16 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,15 +3,19 @@
 #
 
 # Object file lists.
-obj-y   := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o
+obj-y   := cpu.o mm.o devices.o ehci.o system.o bus_freq.o sdram_autogating.o \
+	   suspend.o
+obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
+obj-$(CONFIG_SOC_IMX51)	+= clock.o
+obj-$(CONFIG_SOC_IMX53)	+= clock.o
 
 obj-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
+obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o cpu_op-mx53.o
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
 obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
 obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
-obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
+obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o mx53_loco_pmic_da9053.o
 obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
@@ -24,3 +28,4 @@ obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
 
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
+obj-$(CONFIG_USB_SUPPORT)	+= usb_h1.o usb_dr.o
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 237bdecd933..458fe9c9b64 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -23,10 +23,15 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
+#include <linux/fsl_devices.h>
+#include <linux/ipu.h>
+#include <linux/pwm_backlight.h>
+#include <linux/memblock.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx53.h>
+#include <mach/ipu-v3.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -34,8 +39,11 @@
 
 #include "crm_regs.h"
 #include "devices-imx53.h"
+#include "devices.h"
+#include "usb.h"
 
 #define MX53_LOCO_POWER			IMX_GPIO_NR(1, 8)
+#define LOCO_HEADPHONE_DET		IMX_GPIO_NR(2, 5)
 #define MX53_LOCO_UI1			IMX_GPIO_NR(2, 14)
 #define MX53_LOCO_UI2			IMX_GPIO_NR(2, 15)
 #define LOCO_FEC_PHY_RST		IMX_GPIO_NR(7, 6)
@@ -44,6 +52,14 @@
 #define LOCO_SD3_WP			IMX_GPIO_NR(3, 12)
 #define LOCO_SD1_CD			IMX_GPIO_NR(3, 13)
 #define LOCO_ACCEL_EN			IMX_GPIO_NR(6, 14)
+#define LOCO_DISP0_PWR			IMX_GPIO_NR(3, 24)
+#define LOCO_DISP0_DET_INT		IMX_GPIO_NR(3, 31)
+#define LOCO_DISP0_RESET		IMX_GPIO_NR(5, 0)
+
+extern void __iomem *ccm_base;
+extern void __iomem *imx_otg_base;
+
+#define LOCO_USBH1_VBUS			IMX_GPIO_NR(7, 8)
 
 static iomux_v3_cfg_t mx53_loco_pads[] = {
 	/* FEC */
@@ -227,6 +243,52 @@ static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
 	.wp_type = ESDHC_WP_GPIO,
 };
 
+static struct mxc_audio_platform_data loco_audio_data;
+
+static int loco_sgtl5000_init(void)
+{
+	struct clk *ssi_ext1;
+	int rate;
+
+	ssi_ext1 = clk_get(NULL, "ssi_ext1_clk");
+	if (IS_ERR(ssi_ext1))
+		return -1;
+
+	rate = clk_round_rate(ssi_ext1, 24000000);
+	if (rate < 8000000 || rate > 27000000) {
+			pr_err("Error: SGTL5000 mclk freq %d out of range!\n",
+				   rate);
+			clk_put(ssi_ext1);
+			return -1;
+	}
+
+	loco_audio_data.sysclk = rate;
+	clk_set_rate(ssi_ext1, rate);
+	clk_enable(ssi_ext1);
+
+	return 0;
+}
+
+static struct imx_ssi_platform_data loco_ssi_pdata = {
+	.flags = IMX_SSI_DMA | IMX_SSI_SYN,
+};
+
+static struct mxc_audio_platform_data loco_audio_data = {
+	.ssi_num = 1,
+	.src_port = 2,
+	.ext_port = 5,
+	.init = loco_sgtl5000_init,
+	.hp_gpio = LOCO_HEADPHONE_DET,
+	.hp_active_low = 1,
+};
+
+static struct platform_device loco_audio_device = {
+	.name = "imx-sgtl5000",
+	.dev = {
+		.platform_data	= &loco_audio_data,
+	}
+};
+
 static inline void mx53_loco_fec_reset(void)
 {
 	int ret;
@@ -246,10 +308,80 @@ static const struct fec_platform_data mx53_loco_fec_data __initconst = {
 	.phy = PHY_INTERFACE_MODE_RMII,
 };
 
+static void sii902x_hdmi_reset(void)
+{
+	gpio_set_value(LOCO_DISP0_RESET, 0);
+	msleep(10);
+	gpio_set_value(LOCO_DISP0_RESET, 1);
+	msleep(10);
+}
+
+static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = {
+	.ipu_id = 0,
+	.disp_id = 0,
+	.reset = sii902x_hdmi_reset,
+};
+
 static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
 	.bitrate = 100000,
 };
 
+static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
+	{
+		.type = "mma8450",
+		.addr = 0x1C,
+	},
+};
+
+static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
+	[0] = {
+		.type	= "sgtl5000",
+		.addr	= 0x0a,
+	},
+	[1] = {
+		.type	= "sii902x",
+		.addr	= 0x39,
+		.platform_data = &sii902x_hdmi_data,
+	},
+};
+
+static struct fsl_mxc_lcd_platform_data lcdif_data = {
+	.ipu_id = 0,
+	.disp_id = 0,
+	.default_ifmt = IPU_PIX_FMT_RGB565,
+};
+
+static struct fsl_mxc_ldb_platform_data ldb_data = {
+	.ipu_id = 0,
+	.disp_id = 0,
+	.ext_ref = 1,
+	.mode = LDB_SIN0,
+};
+
+static struct fsl_mxc_tve_platform_data tve_data = {
+	.dac_reg = "DA9052_LDO7",
+};
+
+static struct ipuv3_fb_platform_data loco_fb_data[] = {
+	{ /*fb0*/
+	.disp_dev = "hdmi",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB24,
+	.mode_str = "1920x1080M@60",
+	.default_bpp = 16,
+	.int_clk = false,
+	}, {
+	.disp_dev = "vga",
+	.interface_pix_fmt = IPU_PIX_FMT_GBR24,
+	.mode_str = "VGA-XGA",
+	.default_bpp = 16,
+	.int_clk = false,
+	},
+};
+
+static struct imx_ipuv3_platform_data ipu_data = {
+	.rev = 3,
+};
+
 static const struct gpio_led mx53loco_leds[] __initconst = {
 	{
 		.name			= "green",
@@ -275,12 +407,137 @@ static struct i2c_board_info mx53loco_i2c_devices[] = {
 	},
 };
 
-static void __init mx53_loco_board_init(void)
+static struct mxc_gpu_platform_data gpu_data __initdata = {
+	.reserved_mem_size	= SZ_64M,
+};
+
+static void mxc_iim_enable_fuse(void)
+{
+	u32 reg;
+	if (!ccm_base)
+		return;
+	/* enable fuse blown */
+	reg = readl(ccm_base + 0x64);
+	reg |= 0x10;
+	writel(reg, ccm_base + 0x64);
+}
+
+static void mxc_iim_disable_fuse(void)
+{
+	u32 reg;
+	if (!ccm_base)
+		return;
+	/* enable fuse blown */
+	reg = readl(ccm_base + 0x64);
+	reg &= ~0x10;
+	writel(reg, ccm_base + 0x64);
+}
+
+static struct mxc_iim_platform_data iim_data = {
+	.bank_start = MXC_IIM_MX53_BANK_START_ADDR,
+	.bank_end   = MXC_IIM_MX53_BANK_END_ADDR,
+	.enable_fuse = mxc_iim_enable_fuse,
+	.disable_fuse = mxc_iim_disable_fuse,
+};
+
+static void loco_suspend_enter(void)
+{
+	/* da9053 suspend preparation */
+}
+
+static void loco_suspend_exit(void)
+{
+	/*clear the EMPGC0/1 bits */
+	__raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
+	__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
+	/* da9053 resmue resore */
+}
+
+static struct mxc_pm_platform_data loco_pm_data = {
+        .suspend_enter = loco_suspend_enter,
+        .suspend_exit = loco_suspend_exit,
+};
+
+extern int __init mx53_loco_init_da9052(void);
+extern void da9053_power_off(void);
+
+static struct platform_pwm_backlight_data loco_pwm_backlight_data = {
+	.pwm_id = 1,
+	.max_brightness = 255,
+	.dft_brightness = 128,
+	.pwm_period_ns = 50000,
+};
+
+static void mx53_loco_usbh1_vbus(bool on)
+{
+        if (on)
+                gpio_set_value(LOCO_USBH1_VBUS, 1);
+        else
+                gpio_set_value(LOCO_USBH1_VBUS, 0);
+}
+
+static void __init mx53_loco_io_init(void)
 {
 	int ret;
 	imx53_soc_init();
 	imx53_qsb_common_init();
 
+	mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
+					ARRAY_SIZE(mx53_loco_pads));
+
+	/* Sii902x HDMI controller */
+	ret = gpio_request(LOCO_DISP0_RESET, "disp0-reset");
+	if (ret) {
+		printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_RESET: %d\n", ret);
+		return;
+	}
+	gpio_direction_output(LOCO_DISP0_RESET, 0);
+
+	ret = gpio_request(LOCO_DISP0_DET_INT, "disp0-detect");
+	if (ret) {
+		printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_DET_INT: %d\n", ret);
+		return;
+	}
+	gpio_direction_input(LOCO_DISP0_DET_INT);
+
+	/* enable disp0 power */
+	ret = gpio_request(LOCO_DISP0_PWR, "disp0-power-en");
+	if (ret) {
+		printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_PWR: %d\n", ret);
+		return;
+	}
+	gpio_direction_output(LOCO_DISP0_PWR, 1);
+}
+
+static struct mxc_spdif_platform_data mxc_spdif_data = {
+	.spdif_tx = 1,
+	.spdif_rx = 0,
+	.spdif_clk_44100 = -1,	/* No source for 44.1K */
+	/* Source from CCM spdif_clk (24M) for 48k and 32k
+	 * It's not accurate: for 48Khz it is actually 46875Hz (2.3% off)
+	 */
+	.spdif_clk_48000 = 1,
+	.spdif_clkid = 0,
+	.spdif_clk = NULL,	/* spdif bus clk */
+};
+
+static void __init mx53_loco_board_init(void)
+{
+	int i, ret;
+
+	mx53_loco_io_init();
+
+	imx53_add_ipuv3(0, &ipu_data);
+
+	for (i = 0; i < ARRAY_SIZE(loco_fb_data); i++)
+		imx53_add_ipuv3fb(i, &loco_fb_data[i]);
+
+	imx53_add_vpu();
+	imx53_add_lcdif(&lcdif_data);
+	imx53_add_ldb(&ldb_data);
+	imx53_add_tve(&tve_data);
+	imx53_add_v4l2_output(0);
+
 	imx53_add_imx_uart(0, NULL);
 	mx53_loco_fec_reset();
 	imx53_add_fec(&mx53_loco_fec_data);
@@ -294,11 +551,62 @@ static void __init mx53_loco_board_init(void)
 				ARRAY_SIZE(mx53loco_i2c_devices));
 	imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
 	imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
+	i2c_register_board_info(0, mxc_i2c0_board_info,
+				ARRAY_SIZE(mxc_i2c0_board_info));
+
+	mxc_i2c1_board_info[1].irq = gpio_to_irq(LOCO_DISP0_DET_INT);
+
+	i2c_register_board_info(1, mxc_i2c1_board_info,
+				ARRAY_SIZE(mxc_i2c1_board_info));
+
 	imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
 	imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
+	platform_device_register(&loco_audio_device);
+	imx53_add_imx_ssi(1, &loco_ssi_pdata);
+	imx53_add_srtc();
 	imx_add_gpio_keys(&loco_button_data);
 	gpio_led_register_device(-1, &mx53loco_leds_data);
 	imx53_add_ahci_imx();
+	irq_set_irq_wake(gpio_to_irq(MX53_LOCO_POWER), 1);
+	imx53_add_iim(&iim_data);
+
+	i2c_register_board_info(0, mxc_i2c0_board_info,
+				ARRAY_SIZE(mxc_i2c0_board_info));
+
+	mxc_pm_device.dev.platform_data = &loco_pm_data;
+	platform_device_register(&mxc_pm_device);
+	mx53_loco_init_da9052();
+	pm_power_off = da9053_power_off;
+
+	imx53_add_mxc_pwm(1);
+	imx53_add_mxc_pwm_backlight(0, &loco_pwm_backlight_data);
+
+	mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
+	clk_put(mxc_spdif_data.spdif_core_clk);
+
+	imx53_add_spdif(&mxc_spdif_data);
+	imx53_add_spdif_dai();
+	imx53_add_spdif_audio_device();
+
+	/*GPU*/
+	if (mx53_revision() >= IMX_CHIP_REVISION_2_0)
+		gpu_data.z160_revision = 1;
+	else
+		gpu_data.z160_revision = 0;
+	imx53_add_mxc_gpu(&gpu_data);
+
+        /* USB */
+	imx_otg_base = MX53_IO_ADDRESS(MX53_OTG_BASE_ADDR);
+	/* usb host1 vbus */
+        ret = gpio_request(LOCO_USBH1_VBUS, "usbh1-vbus");
+        if (ret) {
+                printk(KERN_ERR"failed to get GPIO LOCO_USBH1_VBUS: %d\n", ret);
+                return;
+        }
+        gpio_direction_output(LOCO_USBH1_VBUS, 0);
+        mx5_set_host1_vbus_func(mx53_loco_usbh1_vbus);
+        mx5_usbh1_init();
+	mx5_usb_dr_init();
 }
 
 static void __init mx53_loco_timer_init(void)
@@ -310,6 +618,18 @@ static struct sys_timer mx53_loco_timer = {
 	.init	= mx53_loco_timer_init,
 };
 
+static void __init mx53_loco_reserve(void)
+{
+	phys_addr_t phys;
+
+	if (gpu_data.reserved_mem_size) {
+		phys = memblock_alloc(gpu_data.reserved_mem_size, SZ_4K);
+		memblock_free(phys, gpu_data.reserved_mem_size);
+		memblock_remove(phys, gpu_data.reserved_mem_size);
+		gpu_data.reserved_mem_base = phys;
+	}
+}
+
 MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
 	.map_io = mx53_map_io,
 	.init_early = imx53_init_early,
@@ -317,4 +637,5 @@ MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
 	.handle_irq = imx53_handle_irq,
 	.timer = &mx53_loco_timer,
 	.init_machine = mx53_loco_board_init,
+	.reserve = mx53_loco_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c
new file mode 100644
index 00000000000..c2cbbd02d52
--- /dev/null
+++ b/arch/arm/mach-mx5/bus_freq.c
@@ -0,0 +1,1065 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file bus_freq.c
+ *
+ * @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module
+ * and DVFS CORE module.
+ *
+ * The APIs are for setting bus frequency to low or high.
+ *
+ * @ingroup PM
+ */
+#include <linux/module.h>
+#include <asm/io.h>
+#include <linux/sched.h>
+#include <linux/proc_fs.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mutex.h>
+#include <mach/iram.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include <mach/mxc_dvfs.h>
+#include <mach/sdram_autogating.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <asm/cacheflush.h>
+#include <asm/tlb.h>
+#include "crm_regs.h"
+
+#define LP_LOW_VOLTAGE		1050000
+#define LP_NORMAL_VOLTAGE		1250000
+#define LP_APM_CLK   			24000000
+#define NAND_LP_APM_CLK			12000000
+#define AXI_A_NORMAL_CLK		166250000
+#define AXI_A_CLK_NORMAL_DIV		4
+#define AXI_B_CLK_NORMAL_DIV		5
+#define AHB_CLK_NORMAL_DIV		AXI_B_CLK_NORMAL_DIV
+#define EMI_SLOW_CLK_NORMAL_DIV		AXI_B_CLK_NORMAL_DIV
+#define NFC_CLK_NORMAL_DIV      	4
+#define SPIN_DELAY	1000000 /* in nanoseconds */
+#define DDR_TYPE_DDR3		0x0
+#define DDR_TYPE_DDR2		0x1
+
+DEFINE_SPINLOCK(ddr_freq_lock);
+
+unsigned long lp_normal_rate;
+unsigned long lp_med_rate;
+unsigned long ddr_normal_rate;
+unsigned long ddr_med_rate;
+unsigned long ddr_low_rate;
+static int cur_ddr_rate;
+static unsigned char mx53_ddr_type;
+
+static struct clk *ddr_clk;
+static struct clk *pll1_sw_clk;
+static struct clk *pll1;
+static struct clk *pll2;
+static struct clk *pll3;
+static struct clk *pll4;
+static struct clk *main_bus_clk;
+static struct clk *axi_a_clk;
+static struct clk *axi_b_clk;
+static struct clk *cpu_clk;
+static struct clk *ddr_hf_clk;
+static struct clk *ahb_clk;
+static struct clk *ddr_clk;
+static struct clk *periph_apm_clk;
+static struct clk *lp_apm;
+static struct clk *gpc_dvfs_clk;
+static struct clk *emi_garb_clk;
+static void __iomem *pll1_base;
+static void __iomem *pll4_base;
+
+struct regulator *pll_regulator;
+
+struct regulator *lp_regulator;
+int low_bus_freq_mode;
+int high_bus_freq_mode;
+int med_bus_freq_mode;
+
+int bus_freq_scaling_initialized;
+char *gp_reg_id;
+char *lp_reg_id;
+
+static struct cpu_op *cpu_op_tbl;
+static struct device *busfreq_dev;
+static int busfreq_suspended;
+static int cpu_podf;
+/* True if bus_frequency is scaled not using DVFS-PER */
+int bus_freq_scaling_is_active;
+
+int cpu_op_nr;
+int lp_high_freq;
+int lp_med_freq;
+
+static int lp_voltage;
+struct workqueue_struct *voltage_wq;
+static struct work_struct voltage_change_handler;
+struct completion voltage_change_cmpl;
+
+void enter_lpapm_mode_mx50(void);
+void enter_lpapm_mode_mx51(void);
+void enter_lpapm_mode_mx53(void);
+void exit_lpapm_mode_mx50(int high_bus_freq);
+void exit_lpapm_mode_mx51(void);
+void exit_lpapm_mode_mx53(void);
+int low_freq_bus_used(void);
+void set_ddr_freq(int ddr_freq);
+
+extern int dvfs_core_is_active;
+extern struct cpu_op *(*get_cpu_op)(int *op);
+extern void __iomem *ccm_base;
+extern void __iomem *databahn_base;
+extern int update_ddr_freq(int ddr_rate);
+extern unsigned int mx50_ddr_type;
+
+
+struct dvfs_wp dvfs_core_setpoint[] = {
+						{33, 8, 33, 10, 10, 0x08},
+						{26, 0, 33, 20, 10, 0x08},
+						{28, 8, 33, 20, 30, 0x08},
+						{29, 0, 33, 20, 10, 0x08},};
+
+static DEFINE_SPINLOCK(voltage_lock);
+struct mutex bus_freq_mutex;
+
+struct timeval start_time;
+struct timeval end_time;
+
+static void voltage_work_handler(struct work_struct *work)
+{
+	if (lp_regulator != NULL) {
+		u32 ret = 0;
+		ret = regulator_set_voltage(lp_regulator,
+					lp_voltage, lp_voltage);
+		udelay(400);
+		if (ret < 0) {
+			printk(KERN_ERR "COULD NOT SET LP VOLTAGE!!!!!!\n");
+			return;
+		}
+	}
+	complete_all(&voltage_change_cmpl);
+}
+
+int set_low_bus_freq(void)
+{
+	if (busfreq_suspended)
+		return 0;
+	if (bus_freq_scaling_initialized) {
+		/* can not enter low bus freq, when cpu is in higher freq
+		 * or only have one working point */
+		if ((clk_get_rate(cpu_clk) >
+				cpu_op_tbl[cpu_op_nr - 1].cpu_rate)
+			|| (cpu_op_nr == 1)) {
+			return 0;
+		}
+
+		mutex_lock(&bus_freq_mutex);
+
+		stop_dvfs_per();
+
+		stop_sdram_autogating();
+
+		if (cpu_is_mx50())
+			enter_lpapm_mode_mx50();
+		else if (cpu_is_mx51())
+			enter_lpapm_mode_mx51();
+		else
+			enter_lpapm_mode_mx53();
+		mutex_unlock(&bus_freq_mutex);
+	}
+	return 0;
+}
+
+void enter_lpapm_mode_mx50()
+{
+	u32 reg;
+	unsigned long flags;
+	spin_lock_irqsave(&ddr_freq_lock, flags);
+
+	set_ddr_freq(LP_APM_CLK);
+	/* Set the parent of main_bus_clk to be PLL3 */
+	clk_set_parent(main_bus_clk, pll3);
+
+	/* Set the AHB dividers to be 2.
+	 * Set the dividers so that clock rates
+	 * are not greater than current clock rate.
+	 */
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+			| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+			| MXC_CCM_CBCDR_AHB_PODF_MASK
+			| MX50_CCM_CBCDR_WEIM_PODF_MASK);
+	reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+			| 1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+			| 1 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+			| 0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCDR);
+	while (__raw_readl(MXC_CCM_CDHIPR) & 0x0F)
+		udelay(10);
+
+	low_bus_freq_mode = 1;
+	high_bus_freq_mode = 0;
+	med_bus_freq_mode = 0;
+
+	/* Set the source of main_bus_clk to be lp-apm. */
+	clk_set_parent(main_bus_clk, lp_apm);
+
+	/* Set the AHB dividers to be 1. */
+	/* Set the dividers to be  1, so the clock rates
+	 * are at 24Mhz
+	 */
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+			| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+			| MXC_CCM_CBCDR_AHB_PODF_MASK
+			| MX50_CCM_CBCDR_WEIM_PODF_MASK);
+	reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+			| 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+			| 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+			| 0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCDR);
+	while (__raw_readl(MXC_CCM_CDHIPR) & 0x0F)
+		udelay(10);
+
+	spin_unlock_irqrestore(&ddr_freq_lock, flags);
+
+	spin_lock_irqsave(&voltage_lock, flags);
+	lp_voltage = LP_LOW_VOLTAGE;
+	INIT_COMPLETION(voltage_change_cmpl);
+	queue_work(voltage_wq, &voltage_change_handler);
+	spin_unlock_irqrestore(&voltage_lock, flags);
+
+	if (clk_get_usecount(pll1_sw_clk) == 1) {
+		/* Relock PLL1 to 160MHz. */
+		clk_set_parent(pll1_sw_clk, pll2);
+		/* Set the divider to ARM_PODF to 3. */
+		__raw_writel(0x02, MXC_CCM_CACRR);
+
+		clk_set_rate(pll1, 160000000);
+		clk_set_parent(pll1_sw_clk, pll1);
+		/* Set the divider to ARM_PODF to 1. */
+		__raw_writel(0x0, MXC_CCM_CACRR);
+	}
+
+	udelay(100);
+}
+
+void enter_lpapm_mode_mx51()
+{
+	u32 reg;
+	/* Set PLL3 to 133Mhz if no-one is using it. */
+	if (clk_get_usecount(pll3) == 0) {
+		u32 pll3_rate = clk_get_rate(pll3);
+
+		clk_enable(pll3);
+		clk_set_rate(pll3, clk_round_rate(pll3, 133000000));
+
+		/*Change the DDR freq to 133Mhz. */
+		clk_set_rate(ddr_hf_clk,
+		     clk_round_rate(ddr_hf_clk, ddr_low_rate));
+
+		/* Set the parent of Periph_apm_clk to be PLL3 */
+		clk_set_parent(periph_apm_clk, pll3);
+		clk_set_parent(main_bus_clk, periph_apm_clk);
+
+		/* Set the dividers to be  1, so the clock rates
+		  * are at 133MHz.
+		  */
+		reg = __raw_readl(MXC_CCM_CBCDR);
+		reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+				| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+				| MXC_CCM_CBCDR_AHB_PODF_MASK
+				| MXC_CCM_CBCDR_EMI_PODF_MASK
+				| MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+		reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+				| 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+				| 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+				| 0 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
+				| 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+		__raw_writel(reg, MXC_CCM_CBCDR);
+
+		clk_enable(emi_garb_clk);
+		while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
+			udelay(10);
+		clk_disable(emi_garb_clk);
+
+		low_bus_freq_mode = 1;
+		high_bus_freq_mode = 0;
+		med_bus_freq_mode = 0;
+
+		/* Set the source of Periph_APM_Clock to be lp-apm. */
+		clk_set_parent(periph_apm_clk, lp_apm);
+
+		/* Set PLL3 back to original rate. */
+		clk_set_rate(pll3, clk_round_rate(pll3, pll3_rate));
+		clk_disable(pll3);
+	}
+}
+
+void enter_lpapm_mode_mx53()
+{
+	u32 reg;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+
+	/* TBD: Reduce DDR frequency for DDR2 */
+	/* if (mx53_ddr_type == DDR_TYPE_DDR2) {
+	} */
+
+	/* move cpu clk to pll2, 400 / 3 = 133Mhz for cpu  */
+    /* Change the source of pll1_sw_clk to be the step_clk */
+    reg = __raw_readl(MXC_CCM_CCSR);
+    reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+    __raw_writel(reg, MXC_CCM_CCSR);
+
+	cpu_podf = __raw_readl(MXC_CCM_CACRR);
+	reg = __raw_readl(MXC_CCM_CDHIPR);
+	if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) == 0)
+		__raw_writel(0x2, MXC_CCM_CACRR);
+	else
+		printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n");
+	clk_set_parent(pll1_sw_clk, pll2);
+
+	/* ahb = pll2/8, axi_b = pll2/8, axi_a = pll2/1*/
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+		| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+		| MXC_CCM_CBCDR_AHB_PODF_MASK);
+	reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+		| 7 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+		| 7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) &
+			(MXC_CCM_CDHIPR_AXI_A_PODF_BUSY |
+			 MXC_CCM_CDHIPR_AXI_B_PODF_BUSY |
+			 MXC_CCM_CDHIPR_AHB_PODF_BUSY)) {
+			getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec
+			       > SPIN_DELAY)
+			panic("low bus freq set rate error\n");
+	}
+
+	/* keep this infront of propagating */
+	low_bus_freq_mode = 1;
+	high_bus_freq_mode = 0;
+	med_bus_freq_mode = 0;
+
+	if (clk_get_usecount(pll1) == 0) {
+		reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+		reg &= ~MXC_PLL_DP_CTL_UPEN;
+		__raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
+	}
+	if (clk_get_usecount(pll4) == 0) {
+		reg = __raw_readl(pll4_base + MXC_PLL_DP_CTL);
+		reg &= ~MXC_PLL_DP_CTL_UPEN;
+		__raw_writel(reg, pll4_base + MXC_PLL_DP_CTL);
+	}
+}
+
+int set_high_bus_freq(int high_bus_freq)
+{
+	u32 reg;
+	if (bus_freq_scaling_initialized) {
+		mutex_lock(&bus_freq_mutex);
+		/*
+		 * If the CPU freq is 800MHz, set the bus to the high
+		 * setpoint (133MHz) and DDR to 200MHz.
+		 */
+		if ((clk_get_rate(cpu_clk) >
+				cpu_op_tbl[cpu_op_nr - 1].cpu_rate)
+				|| lp_high_freq)
+			high_bus_freq = 1;
+
+		stop_sdram_autogating();
+
+		if (low_bus_freq_mode) {
+			/* Relock PLL3 to 133MHz */
+			if (cpu_is_mx50())
+				exit_lpapm_mode_mx50(high_bus_freq);
+			else if (cpu_is_mx51())
+				exit_lpapm_mode_mx51();
+			else
+				exit_lpapm_mode_mx53();
+			start_dvfs_per();
+		}
+		if (bus_freq_scaling_is_active) {
+			if (!high_bus_freq_mode && high_bus_freq) {
+				if (cpu_is_mx50()) {
+					if (med_bus_freq_mode) {
+						/* Increase SYS_CLK */
+						reg = __raw_readl(MXC_CCM_CLK_SYS);
+						reg &= ~MXC_CCM_CLK_SYS_DIV_PLL_MASK;
+						reg |= 4 << MXC_CCM_CLK_SYS_DIV_PLL_OFFSET;
+						__raw_writel(reg, MXC_CCM_CLK_SYS);
+
+						/* Set the dividers to the default dividers */
+						reg = __raw_readl(MXC_CCM_CBCDR);
+						reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+							| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+							| MXC_CCM_CBCDR_AHB_PODF_MASK
+							| MX50_CCM_CBCDR_WEIM_PODF_MASK);
+						reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+							|1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+							|2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+							|0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+						__raw_writel(reg, MXC_CCM_CBCDR);
+
+						while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+							udelay(10);
+					}
+				} else {
+					clk_set_rate(ahb_clk,
+						clk_round_rate(ahb_clk,
+							lp_normal_rate));
+					clk_set_rate(ddr_hf_clk,
+						clk_round_rate(ddr_hf_clk,
+							ddr_normal_rate));
+				}
+				/* Set to the high setpoint. */
+				high_bus_freq_mode = 1;
+				low_bus_freq_mode = 0;
+				med_bus_freq_mode = 0;
+			} else if (!med_bus_freq_mode && !high_bus_freq) {
+				if (cpu_is_mx50()) {
+					/* Set the dividers to the medium setpoint dividers */
+					reg = __raw_readl(MXC_CCM_CBCDR);
+					reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+						| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+						| MXC_CCM_CBCDR_AHB_PODF_MASK
+						| MX50_CCM_CBCDR_WEIM_PODF_MASK);
+					reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+						|3 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+						|5 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+						|0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+					__raw_writel(reg, MXC_CCM_CBCDR);
+
+					while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+						udelay(10);
+					/* Reduce SYS_CLK */
+					reg = __raw_readl(MXC_CCM_CLK_SYS);
+					reg &= ~MXC_CCM_CLK_SYS_DIV_PLL_MASK;
+					reg |= 8 << MXC_CCM_CLK_SYS_DIV_PLL_OFFSET;
+					__raw_writel(reg, MXC_CCM_CLK_SYS);
+				} else {
+					if (cpu_is_mx51())
+						clk_set_rate(ddr_hf_clk,
+							clk_round_rate(
+							ddr_hf_clk,
+							ddr_low_rate));
+					clk_set_rate(ahb_clk,
+					clk_round_rate(
+						ahb_clk, lp_med_rate));
+				}
+				/* Set to the medium setpoint. */
+				high_bus_freq_mode = 0;
+				low_bus_freq_mode = 0;
+				med_bus_freq_mode = 1;
+			}
+			if (cpu_is_mx50()) {
+				if (med_bus_freq_mode &&
+					(cur_ddr_rate != ddr_med_rate))
+					set_ddr_freq(ddr_med_rate);
+				if (high_bus_freq_mode &&
+					(cur_ddr_rate != ddr_normal_rate))
+					set_ddr_freq(ddr_normal_rate);
+			}
+		}
+		start_sdram_autogating();
+		mutex_unlock(&bus_freq_mutex);
+	}
+	return 0;
+}
+
+void exit_lpapm_mode_mx50(int high_bus_freq)
+{
+	u32 reg;
+	unsigned long flags;
+
+	if (clk_get_usecount(pll1_sw_clk) == 1) {
+		/* Relock PLL1 to 800MHz. */
+		clk_set_parent(pll1_sw_clk, pll2);
+		/* Set the divider to ARM_PODF to 3, cpu is at 160MHz. */
+		__raw_writel(0x02, MXC_CCM_CACRR);
+
+		clk_set_rate(pll1, 800000000);
+		clk_set_parent(pll1_sw_clk, pll1);
+		/* Set the divider to ARM_PODF to 5. */
+		__raw_writel(0x4, MXC_CCM_CACRR);
+	}
+
+	if (!completion_done(&voltage_change_cmpl))
+		wait_for_completion_interruptible(&voltage_change_cmpl);
+	spin_lock_irqsave(&voltage_lock, flags);
+	if (lp_voltage != LP_NORMAL_VOLTAGE) {
+		INIT_COMPLETION(voltage_change_cmpl);
+		lp_voltage = LP_NORMAL_VOLTAGE;
+		if (!queue_work(voltage_wq, &voltage_change_handler))
+			printk(KERN_ERR "WORK_NOT_ADDED\n");
+		spin_unlock_irqrestore(&voltage_lock, flags);
+		wait_for_completion_interruptible(&voltage_change_cmpl);
+	} else {
+		spin_unlock_irqrestore(&voltage_lock, flags);
+		if (!completion_done(&voltage_change_cmpl))
+			wait_for_completion_interruptible(&voltage_change_cmpl);
+	}
+
+	spin_lock_irqsave(&ddr_freq_lock, flags);
+	if (!low_bus_freq_mode) {
+		spin_unlock_irqrestore(&ddr_freq_lock, flags);
+		return;
+	}
+
+	/* Temporarily set the dividers when the source is PLL3.
+	 * No clock rate is above 133MHz.
+	 */
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+		| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+		| MXC_CCM_CBCDR_AHB_PODF_MASK
+		| MX50_CCM_CBCDR_WEIM_PODF_MASK);
+	reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+		|1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+		|1 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+		|0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+		udelay(10);
+
+	clk_set_parent(main_bus_clk, pll3);
+
+	if (bus_freq_scaling_is_active && !high_bus_freq) {
+		/* Set the dividers to the medium setpoint dividers */
+		reg = __raw_readl(MXC_CCM_CBCDR);
+		reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+			| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+			| MXC_CCM_CBCDR_AHB_PODF_MASK
+			| MX50_CCM_CBCDR_WEIM_PODF_MASK);
+		reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+			|3 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+			|5 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+			|0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+		__raw_writel(reg, MXC_CCM_CBCDR);
+
+		while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+			udelay(10);
+
+		/*Set the main_bus_clk parent to be PLL2. */
+		clk_set_parent(main_bus_clk, pll2);
+
+		/* Set to the medium setpoint. */
+		high_bus_freq_mode = 0;
+		low_bus_freq_mode = 0;
+		med_bus_freq_mode = 1;
+		set_ddr_freq(ddr_med_rate);
+	} else {
+		/* Set the dividers to the default dividers */
+		reg = __raw_readl(MXC_CCM_CBCDR);
+		reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+			| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+			| MXC_CCM_CBCDR_AHB_PODF_MASK
+			| MX50_CCM_CBCDR_WEIM_PODF_MASK);
+		reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+			|1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+			|2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+			|0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+		__raw_writel(reg, MXC_CCM_CBCDR);
+
+		while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+			udelay(10);
+
+		/*Set the main_bus_clk parent to be PLL2. */
+		clk_set_parent(main_bus_clk, pll2);
+
+		/* Set to the high setpoint. */
+		high_bus_freq_mode = 1;
+		low_bus_freq_mode = 0;
+		med_bus_freq_mode = 0;
+		set_ddr_freq(ddr_normal_rate);
+	}
+
+	spin_unlock_irqrestore(&ddr_freq_lock, flags);
+
+	udelay(100);
+}
+
+void exit_lpapm_mode_mx51()
+{
+	u32 reg;
+
+	/* Temporarily Set the dividers  is PLL3.
+	 * No clock rate is above 133MHz.
+	 */
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+		| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+		| MXC_CCM_CBCDR_AHB_PODF_MASK
+		| MXC_CCM_CBCDR_EMI_PODF_MASK
+		| MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+	reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+		| 1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+		| 1 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+		| 1 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
+		| 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	clk_enable(emi_garb_clk);
+	while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
+		udelay(10);
+	clk_disable(emi_garb_clk);
+
+	clk_set_parent(periph_apm_clk, pll3);
+
+	/* Set the dividers to the default dividers */
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+		| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+		| MXC_CCM_CBCDR_AHB_PODF_MASK
+		| MXC_CCM_CBCDR_EMI_PODF_MASK
+		| MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+	reg |= (3 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+		| 4 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+		| 4 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+		| 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
+		| 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	clk_enable(emi_garb_clk);
+	while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
+		udelay(10);
+
+	low_bus_freq_mode = 0;
+	high_bus_freq_mode = 1;
+	clk_disable(emi_garb_clk);
+
+	/*Set the main_bus_clk parent to be PLL2. */
+	clk_set_parent(main_bus_clk, pll2);
+
+	/*Change the DDR freq to 200MHz*/
+	clk_set_rate(ddr_hf_clk,
+	    clk_round_rate(ddr_hf_clk, ddr_normal_rate));
+}
+
+void exit_lpapm_mode_mx53()
+{
+	u32 reg;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+
+
+	/* move cpu clk to pll1 */
+	reg = __raw_readl(MXC_CCM_CDHIPR);
+	if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) != 0)
+		__raw_writel(cpu_podf & 0x7,
+				MXC_CCM_CACRR);
+	else
+		printk(KERN_DEBUG
+			"ARM_PODF still in busy!!!!\n");
+
+	clk_set_parent(pll1_sw_clk, pll1);
+
+
+	/* ahb = 400/3, axi_b = 400/2, axi_a = 400*/
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+		| MXC_CCM_CBCDR_AXI_B_PODF_MASK
+		| MXC_CCM_CBCDR_AHB_PODF_MASK);
+	reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+		| 1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+		| 2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) &
+		(MXC_CCM_CDHIPR_AXI_A_PODF_BUSY |
+		 MXC_CCM_CDHIPR_AXI_B_PODF_BUSY |
+		 MXC_CCM_CDHIPR_AHB_PODF_BUSY)) {
+			getnstimeofday(&curtime);
+		if (curtime.tv_nsec
+			- nstimeofday.tv_nsec
+			> SPIN_DELAY)
+			panic("bus freq error\n");
+	}
+
+	/* keep this infront of propagating */
+	low_bus_freq_mode = 0;
+	high_bus_freq_mode = 1;
+	med_bus_freq_mode = 0;
+
+	/* TBD: Restore DDR frequency for DDR2 */
+	/* if (mx53_ddr_type == DDR_TYPE_DDR2) {
+	} */
+}
+
+void set_ddr_freq(int ddr_rate)
+{
+	unsigned long flags;
+	unsigned int ret = 0;
+
+	spin_lock_irqsave(&ddr_freq_lock, flags);
+
+	if (cpu_is_mx50())
+		ret = update_ddr_freq(ddr_rate);
+
+	spin_unlock_irqrestore(&ddr_freq_lock, flags);
+	if (!ret)
+		cur_ddr_rate = ddr_rate;
+	udelay(100);
+}
+
+int low_freq_bus_used(void)
+{
+	if ((lp_high_freq == 0)
+	    && (lp_med_freq == 0))
+		return 1;
+	else
+		return 0;
+}
+
+void setup_pll(void)
+{
+}
+
+static ssize_t bus_freq_scaling_enable_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	if (bus_freq_scaling_is_active)
+		return sprintf(buf, "Bus frequency scaling is enabled\n");
+	else
+		return sprintf(buf, "Bus frequency scaling is disabled\n");
+}
+
+static ssize_t bus_freq_scaling_enable_store(struct device *dev,
+				 struct device_attribute *attr,
+				 const char *buf, size_t size)
+{
+	u32 reg;
+
+	if (strncmp(buf, "1", 1) == 0) {
+		if (dvfs_per_active()) {
+			printk(KERN_INFO "bus frequency scaling cannot be\
+				 enabled when DVFS-PER is active\n");
+			return size;
+		}
+		if (!cpu_is_mx50()) {
+			/* Initialize DVFS-PODF to 0. */
+			reg = __raw_readl(MXC_CCM_CDCR);
+			reg &= ~MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK;
+			__raw_writel(reg, MXC_CCM_CDCR);
+			clk_set_parent(main_bus_clk, pll2);
+		}
+		bus_freq_scaling_is_active = 1;
+		set_high_bus_freq(0);
+	} else if (strncmp(buf, "0", 1) == 0) {
+		if (bus_freq_scaling_is_active)
+			set_high_bus_freq(1);
+		bus_freq_scaling_is_active = 0;
+	}
+
+	return size;
+}
+
+static int busfreq_suspend(struct platform_device *pdev, pm_message_t message)
+{
+	if (low_bus_freq_mode)
+		set_high_bus_freq(1);
+	busfreq_suspended = 1;
+	return 0;
+}
+
+static int busfreq_resume(struct platform_device *pdev)
+{
+	busfreq_suspended = 0;
+	return  0;
+}
+
+static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show,
+			bus_freq_scaling_enable_store);
+
+/*!
+ * This is the probe routine for the bus frequency driver.
+ *
+ * @param   pdev   The platform device structure
+ *
+ * @return         The function returns 0 on success
+ *
+ */
+static int __devinit busfreq_probe(struct platform_device *pdev)
+{
+	int err = 0;
+	unsigned long pll2_rate, pll1_rate;
+	struct mxc_bus_freq_platform_data *p_bus_freq_data;
+
+	p_bus_freq_data = pdev->dev.platform_data;
+	gp_reg_id = p_bus_freq_data->gp_reg_id;
+	lp_reg_id = p_bus_freq_data->lp_reg_id;
+
+	if (cpu_is_mx51()) {
+		pll1_base = MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR);
+	} else if (cpu_is_mx53()) {
+		pll1_base = MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR);
+		pll4_base = MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR);
+	} else if (cpu_is_mx50()) {
+		pll1_base = MX50_IO_ADDRESS(MX50_PLL1_BASE_ADDR);
+	}
+
+	busfreq_dev = &pdev->dev;
+
+	main_bus_clk = clk_get(NULL, "main_bus_clk");
+	if (IS_ERR(main_bus_clk)) {
+		printk(KERN_DEBUG "%s: failed to get main_bus_clk\n",
+		       __func__);
+		return PTR_ERR(main_bus_clk);
+	}
+
+	pll1_sw_clk = clk_get(NULL, "pll1_sw_clk");
+	if (IS_ERR(pll1_sw_clk)) {
+		printk(KERN_DEBUG "%s: failed to get pll1_sw_clk\n", __func__);
+		return PTR_ERR(pll1_sw_clk);
+	}
+
+	pll1 = clk_get(NULL, "pll1_main_clk");
+	if (IS_ERR(pll1)) {
+		printk(KERN_DEBUG "%s: failed to get pll1\n", __func__);
+		return PTR_ERR(pll1);
+	}
+
+	pll2 = clk_get(NULL, "pll2");
+	if (IS_ERR(pll2)) {
+		printk(KERN_DEBUG "%s: failed to get pll2\n", __func__);
+		return PTR_ERR(pll2);
+	}
+
+	pll3 = clk_get(NULL, "pll3");
+	if (IS_ERR(pll3)) {
+		printk(KERN_DEBUG "%s: failed to get pll3\n", __func__);
+		return PTR_ERR(pll3);
+	}
+
+	if (cpu_is_mx53()) {
+		pll4 = clk_get(NULL, "pll4");
+		if (IS_ERR(pll4)) {
+			printk(KERN_DEBUG "%s: failed to get pll4\n", __func__);
+			return PTR_ERR(pll4);
+		}
+	}
+
+	axi_a_clk = clk_get(NULL, "axi_a_clk");
+	if (IS_ERR(axi_a_clk)) {
+		printk(KERN_DEBUG "%s: failed to get axi_a_clk\n",
+		       __func__);
+		return PTR_ERR(axi_a_clk);
+	}
+
+	axi_b_clk = clk_get(NULL, "axi_b_clk");
+	if (IS_ERR(axi_b_clk)) {
+		printk(KERN_DEBUG "%s: failed to get axi_b_clk\n",
+		       __func__);
+		return PTR_ERR(axi_b_clk);
+	}
+
+	ddr_clk = clk_get(NULL, "ddr_clk");
+	if (IS_ERR(ddr_clk)) {
+		printk(KERN_DEBUG "%s: failed to get ddr_clk\n",
+		       __func__);
+		return PTR_ERR(ddr_clk);
+	}
+
+	ddr_hf_clk = clk_get_parent(ddr_clk);
+
+	if (IS_ERR(ddr_hf_clk)) {
+		printk(KERN_DEBUG "%s: failed to get ddr_hf_clk\n",
+		       __func__);
+		return PTR_ERR(ddr_hf_clk);
+	}
+
+	ahb_clk = clk_get(NULL, "ahb_clk");
+	if (IS_ERR(ahb_clk)) {
+		printk(KERN_DEBUG "%s: failed to get ahb_clk\n",
+		       __func__);
+		return PTR_ERR(ahb_clk);
+	}
+
+	cpu_clk = clk_get(NULL, "cpu_clk");
+	if (IS_ERR(cpu_clk)) {
+		printk(KERN_DEBUG "%s: failed to get cpu_clk\n",
+		       __func__);
+		return PTR_ERR(cpu_clk);
+	}
+
+	if (cpu_is_mx51())
+		emi_garb_clk = clk_get(NULL, "emi_intr_clk.1");
+	else if (cpu_is_mx53())
+		emi_garb_clk = clk_get(NULL, "emi_intr_clk.1");
+	else
+		emi_garb_clk = clk_get(NULL, "ocram_clk");
+	if (IS_ERR(emi_garb_clk)) {
+		printk(KERN_DEBUG "%s: failed to get emi_garb_clk\n",
+		       __func__);
+		return PTR_ERR(emi_garb_clk);
+	}
+
+	if (cpu_is_mx51()  || cpu_is_mx53()) {
+		periph_apm_clk = clk_get(NULL, "periph_apm_clk");
+		if (IS_ERR(periph_apm_clk)) {
+			printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n",
+			       __func__);
+			return PTR_ERR(periph_apm_clk);
+		}
+	}
+
+	lp_apm = clk_get(NULL, "lp_apm");
+	if (IS_ERR(lp_apm)) {
+		printk(KERN_DEBUG "%s: failed to get lp_apm\n",
+		       __func__);
+		return PTR_ERR(lp_apm);
+	}
+
+	gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
+	if (IS_ERR(gpc_dvfs_clk)) {
+		printk(KERN_DEBUG "%s: failed to get gpc_dvfs_clk\n", __func__);
+		return PTR_ERR(gpc_dvfs_clk);
+	}
+
+	err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
+	if (err) {
+		printk(KERN_ERR
+		       "Unable to register sysdev entry for BUSFREQ");
+		return err;
+	}
+
+	pll1_rate = clk_get_rate(pll1_sw_clk);
+	pll2_rate = clk_get_rate(pll2);
+
+	if (pll2_rate == 665000000) {
+		/* for mx51 */
+		lp_normal_rate = pll2_rate / 5;
+		lp_med_rate = pll2_rate / 8;
+		ddr_normal_rate = pll1_rate / 4; /* 200M */
+		ddr_low_rate = pll1_rate / 6; /* 133M */
+	} else if (pll2_rate == 600000000) {
+		/* for mx53 evk rev.A */
+		lp_normal_rate = pll2_rate / 5;
+		lp_med_rate = pll2_rate / 8;
+		ddr_normal_rate = pll2_rate / 2;
+		ddr_low_rate = pll2_rate / 2;
+	} else if (pll2_rate == 400000000) {
+		if (cpu_is_mx50()) {
+			lp_normal_rate = pll2_rate / 3;
+			ddr_normal_rate = clk_get_rate(ddr_clk);
+			lp_med_rate = pll2_rate / 6;
+			ddr_low_rate = LP_APM_CLK;
+			if (mx50_ddr_type == MX50_LPDDR2)
+				ddr_med_rate = pll2_rate / 3;
+			else
+				/* mDDR @ 133Mhz currently does not work */
+				ddr_med_rate = ddr_normal_rate;
+		}
+	}
+
+	/* for mx53 */
+	if (cpu_is_mx53()) {
+		/* set DDR type */
+		if (machine_is_mx53_evk() || machine_is_mx53_ard())
+			mx53_ddr_type = DDR_TYPE_DDR2;
+		else
+			mx53_ddr_type = DDR_TYPE_DDR3;
+		if (mx53_ddr_type == DDR_TYPE_DDR2) {
+			/* DDR2 */
+			lp_normal_rate = pll2_rate / 3;
+			lp_med_rate = pll2_rate / 5;
+			ddr_normal_rate = pll2_rate / 1;
+			ddr_low_rate = pll2_rate / 3;
+		} else {
+			/* DDR3: DDR3 frequency can not be lower than 300MHZ */
+			lp_normal_rate = pll2_rate / 3;
+			lp_med_rate = pll2_rate / 5;
+			ddr_normal_rate = pll2_rate / 1;
+			ddr_low_rate = pll2_rate / 1;
+		}
+	}
+
+	if (cpu_is_mx50()) {
+		cur_ddr_rate = ddr_normal_rate;
+
+		lp_regulator = regulator_get(NULL, lp_reg_id);
+		if (IS_ERR(lp_regulator)) {
+			printk(KERN_DEBUG
+			"%s: failed to get lp regulator\n", __func__);
+			return PTR_ERR(lp_regulator);
+		}
+		voltage_wq = create_workqueue("voltage_change");
+		INIT_WORK(&voltage_change_handler, voltage_work_handler);
+
+		init_completion(&voltage_change_cmpl);
+	}
+	cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+	low_bus_freq_mode = 0;
+	high_bus_freq_mode = 1;
+	med_bus_freq_mode = 0;
+	bus_freq_scaling_is_active = 0;
+	bus_freq_scaling_initialized = 1;
+
+	mutex_init(&bus_freq_mutex);
+	return 0;
+}
+
+static struct platform_driver busfreq_driver = {
+	.driver = {
+		   .name = "busfreq",
+		},
+	.probe = busfreq_probe,
+	.suspend = busfreq_suspend,
+	.resume = busfreq_resume,
+};
+
+/*!
+ * Initialise the busfreq_driver.
+ *
+ * @return  The function always returns 0.
+ */
+
+static int __init busfreq_init(void)
+{
+	if (platform_driver_register(&busfreq_driver) != 0) {
+		printk(KERN_ERR "busfreq_driver register failed\n");
+		return -ENODEV;
+	}
+
+	printk(KERN_INFO "Bus freq driver module loaded\n");
+	return 0;
+}
+
+static void __exit busfreq_cleanup(void)
+{
+	sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
+
+	/* Unregister the device structure */
+	platform_driver_unregister(&busfreq_driver);
+	bus_freq_scaling_initialized = 0;
+}
+
+module_init(busfreq_init);
+module_exit(busfreq_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("BusFreq driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
new file mode 100644
index 00000000000..4cbc05bbdc6
--- /dev/null
+++ b/arch/arm/mach-mx5/clock.c
@@ -0,0 +1,5250 @@
+/*
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/hrtimer.h>
+#include <linux/mm.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <asm/div64.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+#include <mach/mxc_dvfs.h>
+#include <mach/sdram_autogating.h>
+
+#include "crm_regs.h"
+#include "cpu_op-mx51.h"
+#include "cpu_op-mx53.h"
+
+/* External clock values passed-in by the board code */
+static unsigned long external_high_reference, external_low_reference;
+static unsigned long oscillator_reference, ckih2_reference;
+
+static struct clk dummy_clk;
+static struct clk pll1_main_clk;
+static struct clk pll1_sw_clk;
+static struct clk pll2_sw_clk;
+static struct clk pll3_sw_clk;
+static struct clk pll4_sw_clk;
+static struct clk lp_apm_clk;
+static struct clk tve_clk;
+static struct clk emi_fast_clk;
+static struct clk emi_slow_clk;
+static struct clk emi_intr_clk[];
+static struct clk ddr_clk;
+static struct clk ipu_clk[];
+static struct clk ldb_di_clk[];
+static struct clk axi_a_clk;
+static struct clk axi_b_clk;
+static struct clk ddr_hf_clk;
+static struct clk mipi_hsp_clk;
+static struct clk gpu3d_clk;
+static struct clk gpu2d_clk;
+static struct clk vpu_clk[];
+static int cpu_curr_op;
+static struct cpu_op *cpu_op_tbl;
+
+static void __iomem *pll1_base;
+static void __iomem *pll2_base;
+static void __iomem *pll3_base;
+static void __iomem *pll4_base;
+
+extern int cpu_op_nr;
+extern int lp_high_freq;
+extern int lp_med_freq;
+static int max_axi_a_clk;
+static int max_axi_b_clk;
+static int max_ahb_clk;
+static int max_emi_slow_clk;
+extern int dvfs_core_is_active;
+
+#define SPIN_DELAY	1000000 /* in nanoseconds */
+#define MAX_AXI_A_CLK_MX51 	166250000
+#define MAX_AXI_A_CLK_MX53 	400000000
+#define MAX_AXI_B_CLK_MX51 	133000000
+#define MAX_AXI_B_CLK_MX53 	200000000
+#define MAX_AHB_CLK_MX51	133000000
+#define MAX_EMI_SLOW_CLK_MX51	133000000
+#define MAX_AHB_CLK_MX53	133333333
+#define MAX_EMI_SLOW_CLK_MX53	133333333
+#define MAX_DDR_HF_RATE		200000000
+/* To keep compatible with some NAND flash, limit
+ * max NAND clk to 34MHZ. The user can modify it for
+ * dedicate NAND flash */
+#define MAX_NFC_CLK		34000000
+
+#define UART1_DMA_ENABLE	0
+#define UART2_DMA_ENABLE	0
+#define UART3_DMA_ENABLE	0
+#define UART4_DMA_ENABLE	0
+#define UART5_DMA_ENABLE	0
+
+#ifdef CONFIG_CLK_DEBUG
+#define __INIT_CLK_DEBUG(n)	.name = #n,
+#else
+#define __INIT_CLK_DEBUG(n)
+#endif
+
+extern int mxc_jtag_enabled;
+extern int uart_at_24;
+extern int cpufreq_trig_needed;
+extern int low_bus_freq_mode;
+
+static int cpu_clk_set_op(int op);
+extern struct cpu_op *(*get_cpu_op)(int *op);
+extern void (*set_num_cpu_op)(int num);
+
+static struct clk esdhc3_clk[];
+
+static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
+{
+	u32 min_pre, temp_pre, old_err, err;
+
+	if (div >= 512) {
+		*pre = 8;
+		*post = 64;
+	} else if (div >= 8) {
+		min_pre = (div - 1) / 64 + 1;
+		old_err = 8;
+		for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+			err = div % temp_pre;
+			if (err == 0) {
+				*pre = temp_pre;
+				break;
+			}
+			err = temp_pre - err;
+			if (err < old_err) {
+				old_err = err;
+				*pre = temp_pre;
+			}
+		}
+		*post = (div + *pre - 1) / *pre;
+	} else if (div < 8) {
+		*pre = div;
+		*post = 1;
+	}
+}
+
+static int _clk_enable(struct clk *clk)
+{
+	u32 reg;
+	reg = __raw_readl(clk->enable_reg);
+	reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
+	__raw_writel(reg, clk->enable_reg);
+
+	if (clk->flags & AHB_HIGH_SET_POINT)
+		lp_high_freq++;
+	else if (clk->flags & AHB_MED_SET_POINT)
+		lp_med_freq++;
+
+	return 0;
+}
+
+static int _clk_enable_inrun(struct clk *clk)
+{
+	u32 reg;
+
+	reg = __raw_readl(clk->enable_reg);
+	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+	reg |= 1 << clk->enable_shift;
+	__raw_writel(reg, clk->enable_reg);
+	return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+	u32 reg;
+	reg = __raw_readl(clk->enable_reg);
+	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+	__raw_writel(reg, clk->enable_reg);
+
+	if (clk->flags & AHB_HIGH_SET_POINT)
+		lp_high_freq--;
+	else if (clk->flags & AHB_MED_SET_POINT)
+		lp_med_freq--;
+}
+
+static void _clk_disable_inwait(struct clk *clk)
+{
+	u32 reg;
+	reg = __raw_readl(clk->enable_reg);
+	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+	reg |= 1 << clk->enable_shift;
+	__raw_writel(reg, clk->enable_reg);
+}
+
+/*
+ * For the 4-to-1 muxed input clock
+ */
+static inline u32 _get_mux(struct clk *parent, struct clk *m0,
+			   struct clk *m1, struct clk *m2, struct clk *m3)
+{
+	if (parent == m0)
+		return 0;
+	else if (parent == m1)
+		return 1;
+	else if (parent == m2)
+		return 2;
+	else if (parent == m3)
+		return 3;
+	else
+		BUG();
+
+	return 0;
+}
+
+/*
+ * For the ddr muxed input clock
+ */
+static inline u32 _get_mux_ddr(struct clk *parent, struct clk *m0,
+			   struct clk *m1, struct clk *m2, struct clk *m3, struct clk *m4)
+{
+	if (parent == m0)
+		return 0;
+	else if (parent == m1)
+		return 1;
+	else if (parent == m2)
+		return 2;
+	else if (parent == m3)
+		return 3;
+	else if (parent == m4)
+		return 4;
+	else
+		BUG();
+
+	return 0;
+}
+
+static inline void __iomem *_get_pll_base(struct clk *pll)
+{
+	if (pll == &pll1_main_clk)
+		return pll1_base;
+	else if (pll == &pll2_sw_clk)
+		return pll2_base;
+	else if (pll == &pll3_sw_clk)
+		return pll3_base;
+	else if (pll == &pll4_sw_clk)
+		return pll4_base;
+	else
+		BUG();
+
+	return NULL;
+}
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+	return external_high_reference;
+}
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+	return external_low_reference;
+}
+
+static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
+{
+	return oscillator_reference;
+}
+
+static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
+{
+	return ckih2_reference;
+}
+
+/* External high frequency clock */
+static struct clk ckih_clk = {
+	__INIT_CLK_DEBUG(ckih_clk)
+	.get_rate = get_high_reference_clock_rate,
+};
+
+static struct clk ckih2_clk = {
+	__INIT_CLK_DEBUG(ckih2_clk)
+	.get_rate = get_ckih2_reference_clock_rate,
+};
+
+static struct clk osc_clk = {
+	__INIT_CLK_DEBUG(osc_clk)
+	.get_rate = get_oscillator_reference_clock_rate,
+};
+
+/* External low frequency (32kHz) clock */
+static struct clk ckil_clk = {
+	__INIT_CLK_DEBUG(ckil_clk)
+	.get_rate = get_low_reference_clock_rate,
+};
+
+static unsigned long _fpm_get_rate(struct clk *clk)
+{
+	u32 rate = ckil_clk.get_rate(&ckil_clk) * 512;
+	if ((__raw_readl(MXC_CCM_CCR) & MXC_CCM_CCR_FPM_MULT_MASK) != 0)
+		rate *= 2;
+	return rate;
+}
+
+static int _fpm_enable(struct clk *clk)
+{
+	u32 reg = __raw_readl(MXC_CCM_CCR);
+	reg |= MXC_CCM_CCR_FPM_EN;
+	__raw_writel(reg, MXC_CCM_CCR);
+	return 0;
+}
+
+static void _fpm_disable(struct clk *clk)
+{
+	u32 reg = __raw_readl(MXC_CCM_CCR);
+	reg &= ~MXC_CCM_CCR_FPM_EN;
+	__raw_writel(reg, MXC_CCM_CCR);
+}
+
+static struct clk fpm_clk = {
+	__INIT_CLK_DEBUG(fpm_clk)
+	.parent = &ckil_clk,
+	.get_rate = _fpm_get_rate,
+	.enable = _fpm_enable,
+	.disable = _fpm_disable,
+};
+
+static unsigned long _fpm_div2_get_rate(struct clk *clk)
+{
+	return  clk_get_rate(clk->parent) / 2;
+}
+
+static struct clk fpm_div2_clk = {
+	__INIT_CLK_DEBUG(fpm_div2_clk)
+	.parent = &fpm_clk,
+	.get_rate = _fpm_div2_get_rate,
+};
+
+static unsigned long _clk_pll_get_rate(struct clk *clk)
+{
+	long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+	unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
+	void __iomem *pllbase;
+	s64 temp;
+
+	pllbase = _get_pll_base(clk);
+
+	dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+	pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+	dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
+
+	if (pll_hfsm == 0) {
+		dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+		dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+		dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+	} else {
+		dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+		dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+		dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+	}
+	pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+	mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
+	mfi = (mfi <= 5) ? 5 : mfi;
+	mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+	mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
+	/* Sign extend to 32-bits */
+	if (mfn >= 0x04000000) {
+		mfn |= 0xFC000000;
+		mfn_abs = -mfn;
+	}
+
+	ref_clk = 2 * clk_get_rate(clk->parent);
+	if (dbl != 0)
+		ref_clk *= 2;
+
+	ref_clk /= (pdf + 1);
+	temp = (u64) ref_clk * mfn_abs;
+	do_div(temp, mfd + 1);
+	if (mfn < 0)
+		temp = -temp;
+	temp = (ref_clk * mfi) + temp;
+
+	return temp;
+}
+
+static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, reg1;
+	void __iomem *pllbase;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+
+	long mfi, pdf, mfn, mfd = 999999;
+	s64 temp64;
+	unsigned long quad_parent_rate;
+	unsigned long pll_hfsm, dp_ctl;
+
+	pllbase = _get_pll_base(clk);
+
+	quad_parent_rate = 4 * clk_get_rate(clk->parent);
+	pdf = mfi = -1;
+	while (++pdf < 16 && mfi < 5)
+		mfi = rate * (pdf+1) / quad_parent_rate;
+	if (mfi > 15)
+		return -1;
+	pdf--;
+
+	temp64 = rate*(pdf+1) - quad_parent_rate*mfi;
+	do_div(temp64, quad_parent_rate/1000000);
+	mfn = (long)temp64;
+
+	dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+	/* use dpdck0_2 */
+	__raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
+	pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+	if (pll_hfsm == 0) {
+		reg = mfi<<4 | pdf;
+		__raw_writel(reg, pllbase + MXC_PLL_DP_OP);
+		__raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
+		__raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
+	} else {
+		reg = mfi<<4 | pdf;
+		__raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
+		__raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
+		__raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
+	}
+	/* If auto restart is disabled, restart the PLL and
+	  * wait for it to lock.
+	  */
+	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+	if (reg & MXC_PLL_DP_CTL_UPEN) {
+		reg = __raw_readl(pllbase + MXC_PLL_DP_CONFIG);
+		if (!(reg & MXC_PLL_DP_CONFIG_AREN)) {
+			reg1 = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+			reg1 |= MXC_PLL_DP_CTL_RST;
+			__raw_writel(reg1, pllbase + MXC_PLL_DP_CTL);
+		}
+		/* Wait for lock */
+		getnstimeofday(&nstimeofday);
+		while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL)
+					& MXC_PLL_DP_CTL_LRF)) {
+			getnstimeofday(&curtime);
+			if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+				panic("pll_set_rate: pll relock failed\n");
+		}
+	}
+	return 0;
+}
+
+static int _clk_pll_enable(struct clk *clk)
+{
+	u32 reg;
+	void __iomem *pllbase;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+
+	pllbase = _get_pll_base(clk);
+	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+
+	if (reg & MXC_PLL_DP_CTL_UPEN)
+		return 0;
+
+	reg |=  MXC_PLL_DP_CTL_UPEN;
+	__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+
+	/* Wait for lock */
+	getnstimeofday(&nstimeofday);
+	while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+			panic("pll relock failed\n");
+	}
+	return 0;
+}
+
+static void _clk_pll_disable(struct clk *clk)
+{
+	u32 reg;
+	void __iomem *pllbase;
+
+	pllbase = _get_pll_base(clk);
+	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
+	__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+}
+
+static struct clk pll1_main_clk = {
+	__INIT_CLK_DEBUG(pll1_main_clk)
+	.parent = &osc_clk,
+	.get_rate = _clk_pll_get_rate,
+	.enable = _clk_pll_enable,
+	.disable = _clk_pll_disable,
+};
+
+static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CCSR);
+
+	if (parent == &pll1_main_clk) {
+		reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+		__raw_writel(reg, MXC_CCM_CCSR);
+		/* Set the step_clk parent to be lp_apm, to save power. */
+		mux = _get_mux(&lp_apm_clk, &lp_apm_clk, NULL, &pll2_sw_clk,
+			       &pll3_sw_clk);
+		reg = __raw_readl(MXC_CCM_CCSR);
+		reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |
+		    (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET);
+	} else {
+		if (parent == &lp_apm_clk) {
+			reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+			reg = __raw_readl(MXC_CCM_CCSR);
+			mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk,
+				       &pll3_sw_clk);
+			reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |
+			    (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET);
+		} else {
+			mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk,
+				       &pll3_sw_clk);
+			reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |
+			    (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET);
+			__raw_writel(reg, MXC_CCM_CCSR);
+			reg = __raw_readl(MXC_CCM_CCSR);
+			reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+
+		}
+	}
+	__raw_writel(reg, MXC_CCM_CCSR);
+
+	return 0;
+}
+
+static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
+{
+	u32 reg, div;
+	div = 1;
+	reg = __raw_readl(MXC_CCM_CCSR);
+
+	if (clk->parent == &pll2_sw_clk) {
+		div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
+		       MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
+	} else if (clk->parent == &pll3_sw_clk) {
+		div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
+		       MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
+	}
+	return clk_get_rate(clk->parent) / div;
+}
+
+/* pll1 switch clock */
+static struct clk pll1_sw_clk = {
+	__INIT_CLK_DEBUG(pll1_sw_clk)
+	.parent = &pll1_main_clk,
+	.set_parent = _clk_pll1_sw_set_parent,
+	.get_rate = _clk_pll1_sw_get_rate,
+};
+
+static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CCSR);
+
+	if (parent == &pll2_sw_clk) {
+		reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
+	} else {
+		reg = (reg & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL);
+		reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
+	}
+	__raw_writel(reg, MXC_CCM_CCSR);
+	return 0;
+}
+
+/* same as pll2_main_clk. These two clocks should always be the same */
+static struct clk pll2_sw_clk = {
+	__INIT_CLK_DEBUG(pll2_sw_clk)
+	.parent = &osc_clk,
+	.get_rate = _clk_pll_get_rate,
+	.enable = _clk_pll_enable,
+	.disable = _clk_pll_disable,
+	.set_rate = _clk_pll_set_rate,
+	.set_parent = _clk_pll2_sw_set_parent,
+};
+
+/* same as pll3_main_clk. These two clocks should always be the same */
+static struct clk pll3_sw_clk = {
+	__INIT_CLK_DEBUG(pll3_sw_clk)
+	.parent = &osc_clk,
+	.set_rate = _clk_pll_set_rate,
+	.get_rate = _clk_pll_get_rate,
+	.enable = _clk_pll_enable,
+	.disable = _clk_pll_disable,
+};
+
+/* same as pll4_main_clk. These two clocks should always be the same */
+static struct clk pll4_sw_clk = {
+	__INIT_CLK_DEBUG(pll4_sw_clk)
+	.parent = &osc_clk,
+	.set_rate = _clk_pll_set_rate,
+	.get_rate = _clk_pll_get_rate,
+	.enable = _clk_pll_enable,
+	.disable = _clk_pll_disable,
+};
+
+static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+
+	if (parent == &osc_clk)
+		reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
+	else if (parent == &fpm_clk)
+		reg = __raw_readl(MXC_CCM_CCSR) | MXC_CCM_CCSR_LP_APM_SEL;
+	else
+		return -EINVAL;
+
+	__raw_writel(reg, MXC_CCM_CCSR);
+
+	return 0;
+}
+
+static struct clk lp_apm_clk = {
+	__INIT_CLK_DEBUG(lp_apm_clk)
+	.parent = &osc_clk,
+	.set_parent = _clk_lp_apm_set_parent,
+};
+
+static unsigned long _clk_arm_get_rate(struct clk *clk)
+{
+	u32 cacrr, div;
+
+	cacrr = __raw_readl(MXC_CCM_CACRR);
+	div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
+	return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 i;
+	for (i = 0; i < cpu_op_nr; i++) {
+		if (rate == cpu_op_tbl[i].cpu_rate)
+			break;
+	}
+	if (i >= cpu_op_nr)
+		return -EINVAL;
+	cpu_clk_set_op(i);
+
+	return 0;
+}
+
+static unsigned long _clk_cpu_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 i;
+	u32 op;
+
+	for (i = 0; i < cpu_op_nr; i++) {
+		if (rate == cpu_op_tbl[i].cpu_rate)
+			break;
+	}
+
+	if (i > cpu_op_nr)
+		op = 0;
+
+	return cpu_op_tbl[op].cpu_rate;
+}
+
+
+static struct clk cpu_clk = {
+	__INIT_CLK_DEBUG(cpu_clk)
+	.parent = &pll1_sw_clk,
+	.get_rate = _clk_arm_get_rate,
+	.set_rate = _clk_cpu_set_rate,
+	.round_rate = _clk_cpu_round_rate,
+};
+
+static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
+
+	reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CBCMR);
+
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) &
+			MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+			panic("pll _clk_periph_apm_set_parent failed\n");
+	}
+	return 0;
+}
+
+static struct clk periph_apm_clk = {
+	__INIT_CLK_DEBUG(periph_apm_clk)
+	.parent = &pll1_sw_clk,
+	.set_parent = _clk_periph_apm_set_parent,
+};
+
+/* TODO: Need to sync with GPC to determine if DVFS is in place so that
+ * the DVFS_PODF divider can be applied in CDCR register.
+ */
+static unsigned long _clk_main_bus_get_rate(struct clk *clk)
+{
+	u32 div = 0;
+
+	if (dvfs_per_divider_active() || low_bus_freq_mode)
+		div  = (__raw_readl(MXC_CCM_CDCR) & 0x3);
+	return clk_get_rate(clk->parent) / (div + 1);
+}
+
+static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.enable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.enable(&emi_slow_clk);
+
+	if (parent == &pll2_sw_clk) {
+		reg = __raw_readl(MXC_CCM_CBCDR) &
+		    ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+	} else if (parent == &periph_apm_clk) {
+		reg = __raw_readl(MXC_CCM_CBCDR) | MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+	} else {
+		return -EINVAL;
+	}
+	__raw_writel(reg, MXC_CCM_CBCDR);
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.disable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.disable(&emi_slow_clk);
+
+	return 0;
+}
+
+static struct clk main_bus_clk = {
+	__INIT_CLK_DEBUG(main_bus_clk)
+	.parent = &pll2_sw_clk,
+	.set_parent = _clk_main_bus_set_parent,
+	.get_rate = _clk_main_bus_get_rate,
+};
+
+static unsigned long _clk_axi_a_get_rate(struct clk *clk)
+{
+	u32 reg, div;
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	div = ((reg & MXC_CCM_CBCDR_AXI_A_PODF_MASK) >>
+	       MXC_CCM_CBCDR_AXI_A_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || (div > 8))
+		return -EINVAL;
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.enable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.enable(&emi_slow_clk);
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+			panic("pll _clk_axi_a_set_rate failed\n");
+	}
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.disable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.disable(&emi_slow_clk);
+
+	return 0;
+}
+
+static unsigned long _clk_axi_a_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	/* Make sure rate is not greater than the maximum value for the clock.
+	 * Also prevent a div of 0.
+	 */
+	if (div == 0)
+		div++;
+	if (parent_rate / div > max_axi_a_clk)
+		div++;
+
+	if (div > 8)
+		div = 8;
+
+	return parent_rate / div;
+}
+
+
+static struct clk axi_a_clk = {
+	__INIT_CLK_DEBUG(axi_a_clk)
+	.parent = &main_bus_clk,
+	.get_rate = _clk_axi_a_get_rate,
+	.set_rate = _clk_axi_a_set_rate,
+	.round_rate = _clk_axi_a_round_rate,
+};
+
+static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
+{
+	u32 reg, div;
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
+	       MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long _clk_ddr_hf_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	/* Make sure rate is not greater than the maximum value for the clock.
+	 * Also prevent a div of 0.
+	 */
+	if (div == 0)
+		div++;
+	if (parent_rate / div > MAX_DDR_HF_RATE)
+		div++;
+
+	if (div > 8)
+		div = 8;
+
+	return parent_rate / div;
+}
+
+static int _clk_ddr_hf_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || (div > 8))
+		return -EINVAL;
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.enable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.enable(&emi_slow_clk);
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~MXC_CCM_CBCDR_DDR_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_DDR_PODF_BUSY) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+			panic("clk_ddr_hf_set_rate failed\n");
+	}
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.disable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.disable(&emi_slow_clk);
+
+	return 0;
+}
+
+static struct clk ddr_hf_clk = {
+	__INIT_CLK_DEBUG(ddr_hf_clk)
+	.parent = &pll1_sw_clk,
+	.get_rate = _clk_ddr_hf_get_rate,
+	.round_rate = _clk_ddr_hf_round_rate,
+	.set_rate = _clk_ddr_hf_set_rate,
+};
+
+static unsigned long _clk_axi_b_get_rate(struct clk *clk)
+{
+	u32 reg, div;
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	div = ((reg & MXC_CCM_CBCDR_AXI_B_PODF_MASK) >>
+	       MXC_CCM_CBCDR_AXI_B_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || (div > 8))
+		return -EINVAL;
+
+	emi_fast_clk.enable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.enable(&emi_slow_clk);
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+			panic("_clk_axi_b_set_rate failed\n");
+	}
+
+	emi_fast_clk.disable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.disable(&emi_slow_clk);
+
+	return 0;
+}
+
+static unsigned long _clk_axi_b_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	/* Make sure rate is not greater than the maximum value for the clock.
+	 * Also prevent a div of 0.
+	 */
+	if (div == 0)
+		div++;
+	if (parent_rate / div > max_axi_b_clk)
+		div++;
+
+	if (div > 8)
+		div = 8;
+
+	return parent_rate / div;
+}
+
+
+static struct clk axi_b_clk = {
+	__INIT_CLK_DEBUG(axi_b_clk)
+	.parent = &main_bus_clk,
+	.get_rate = _clk_axi_b_get_rate,
+	.set_rate = _clk_axi_b_set_rate,
+	.round_rate = _clk_axi_b_round_rate,
+};
+
+static unsigned long _clk_ahb_get_rate(struct clk *clk)
+{
+	u32 reg, div;
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+	       MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent) / div;
+}
+
+
+static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || (div > 8))
+		return -EINVAL;
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.enable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.enable(&emi_slow_clk);
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) {
+		getnstimeofday(&curtime);
+		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+			panic("_clk_ahb_set_rate failed\n");
+	}
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.disable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.disable(&emi_slow_clk);
+
+	return 0;
+}
+
+static unsigned long _clk_ahb_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	/* Make sure rate is not greater than the maximum value for the clock.
+	 * Also prevent a div of 0.
+	 */
+	if (div == 0)
+		div++;
+	if (parent_rate / div > max_ahb_clk)
+		div++;
+
+	if (div > 8)
+		div = 8;
+
+	return parent_rate / div;
+}
+
+
+static struct clk ahb_clk = {
+	__INIT_CLK_DEBUG(ahb_clk)
+	.parent = &main_bus_clk,
+	.get_rate = _clk_ahb_get_rate,
+	.set_rate = _clk_ahb_set_rate,
+	.round_rate = _clk_ahb_round_rate,
+};
+
+static int _clk_max_enable(struct clk *clk)
+{
+	u32 reg;
+
+	_clk_enable(clk);
+
+	/* Handshake with MAX when LPM is entered. */
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	if (cpu_is_mx51())
+		reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51;
+	else
+		reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+
+	return 0;
+}
+
+
+static void _clk_max_disable(struct clk *clk)
+{
+	u32 reg;
+
+	_clk_disable_inwait(clk);
+
+	/* No Handshake with MAX when LPM is entered as its disabled. */
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	if (cpu_is_mx51())
+		reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51;
+	else
+		reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+
+static struct clk ahb_max_clk = {
+	__INIT_CLK_DEBUG(ahb_max_clk)
+	.parent = &ahb_clk,
+	.enable_reg = MXC_CCM_CCGR0,
+	.enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+	.enable = _clk_max_enable,
+	.disable = _clk_max_disable,
+};
+
+static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.enable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.enable(&emi_slow_clk);
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	if (parent == &ahb_clk) {
+		reg |= MXC_CCM_CBCDR_EMI_CLK_SEL;
+	} else if (parent == &main_bus_clk) {
+		reg &= ~MXC_CCM_CBCDR_EMI_CLK_SEL;
+	} else {
+		BUG();
+	}
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.disable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.disable(&emi_slow_clk);
+
+	return 0;
+}
+
+static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
+{
+	u32 reg, div;
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
+	       MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || (div > 8))
+		return -EINVAL;
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.enable(&emi_fast_clk);
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CBCDR);
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY) {
+		getnstimeofday(&curtime);
+		if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
+			panic("_clk_emi_slow_set_rate failed\n");
+	}
+
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.disable(&emi_fast_clk);
+
+	return 0;
+}
+
+static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
+					      unsigned long rate)
+{
+	u32 div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	/* Make sure rate is not greater than the maximum value for the clock.
+	 * Also prevent a div of 0.
+	 */
+	if (div == 0)
+		div++;
+	if (parent_rate / div > max_emi_slow_clk)
+		div++;
+
+	if (div > 8)
+		div = 8;
+
+	return parent_rate / div;
+}
+
+
+static struct clk emi_slow_clk = {
+	__INIT_CLK_DEBUG(emi_slow_clk)
+	.parent = &main_bus_clk,
+	.set_parent = _clk_emi_slow_set_parent,
+	.get_rate = _clk_emi_slow_get_rate,
+	.set_rate = _clk_emi_slow_set_rate,
+	.round_rate = _clk_emi_slow_round_rate,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+	.disable = _clk_disable_inwait,
+};
+
+static struct clk ahbmux1_clk = {
+	__INIT_CLK_DEBUG(ahbmux1_clk)
+	.id = 0,
+	.parent = &ahb_clk,
+	.secondary = &ahb_max_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR0,
+	.enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+	.disable = _clk_disable_inwait,
+};
+
+static struct clk ahbmux2_clk = {
+	__INIT_CLK_DEBUG(ahbmux2_clk)
+	.id = 0,
+	.parent = &ahb_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR0,
+	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+	.disable = _clk_disable_inwait,
+};
+
+
+static struct clk emi_fast_clk = {
+	__INIT_CLK_DEBUG(emi_fast_clk)
+	.parent = &ddr_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+	.disable = _clk_disable_inwait,
+};
+
+static struct clk emi_intr_clk[] = {
+	{
+	__INIT_CLK_DEBUG(emi_intr_clk_0)
+	.id = 0,
+	.parent = &ahb_clk,
+	.secondary = &ahbmux2_clk,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable_inwait,
+	},
+	{
+	/* On MX51 - this clock is name emi_garb_clk, and controls the
+	 * access of ARM to GARB.
+	 */
+	__INIT_CLK_DEBUG(emi_intr_clk_1)
+	.id = 1,
+	.parent = &ahb_clk,
+	.secondary = &ahbmux2_clk,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable_inwait,
+	}
+};
+
+static unsigned long _clk_ipg_get_rate(struct clk *clk)
+{
+	u32 reg, div;
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+	       MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk ipg_clk = {
+	__INIT_CLK_DEBUG(ipg_clk)
+	.parent = &ahb_clk,
+	.get_rate = _clk_ipg_get_rate,
+};
+
+static unsigned long _clk_ipg_per_get_rate(struct clk *clk)
+{
+	u32 reg, prediv1, prediv2, podf;
+
+	if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
+		/* the main_bus_clk is the one before the DVFS engine */
+		reg = __raw_readl(MXC_CCM_CBCDR);
+		prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
+			   MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
+		prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
+			   MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
+		podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
+			MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
+		return clk_get_rate(clk->parent) / (prediv1 * prediv2 * podf);
+	} else if (clk->parent == &ipg_clk) {
+		return clk_get_rate(&ipg_clk);
+	}
+	BUG();
+	return 0;
+}
+
+static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CBCMR);
+	mux = _get_mux(parent, &main_bus_clk, &lp_apm_clk, &ipg_clk, NULL);
+	if (mux == 2) {
+		reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
+	} else {
+		reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
+		if (mux == 0)
+			reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
+		else
+			reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
+	}
+	__raw_writel(reg, MXC_CCM_CBCMR);
+
+	return 0;
+}
+
+static struct clk ipg_perclk = {
+	__INIT_CLK_DEBUG(ipg_perclk)
+	.parent = &lp_apm_clk,
+	.get_rate = _clk_ipg_per_get_rate,
+	.set_parent = _clk_ipg_per_set_parent,
+};
+
+static int _clk_ipmux_enable(struct clk *clk)
+{
+	u32 reg;
+	reg = __raw_readl(clk->enable_reg);
+	reg |= 1  << clk->enable_shift;
+	__raw_writel(reg, clk->enable_reg);
+
+	return 0;
+}
+
+static void _clk_ipmux_disable(struct clk *clk)
+{
+	u32 reg;
+	reg = __raw_readl(clk->enable_reg);
+	reg &= ~(0x1 << clk->enable_shift);
+	__raw_writel(reg, clk->enable_reg);
+}
+
+static struct clk ipumux1_clk = {
+	__INIT_CLK_DEBUG(ipumux1_clk)
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGR5_CG6_1_OFFSET,
+	.enable = _clk_ipmux_enable,
+	.disable = _clk_ipmux_disable,
+};
+
+static struct clk ipumux2_clk = {
+	__INIT_CLK_DEBUG(ipumux2_clk)
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGR5_CG6_2_OFFSET,
+	.enable = _clk_ipmux_enable,
+	.disable = _clk_ipmux_disable,
+};
+
+static int _clk_ocram_enable(struct clk *clk)
+{
+	return 0;
+}
+
+static void _clk_ocram_disable(struct clk *clk)
+{
+}
+
+static struct clk ocram_clk = {
+	__INIT_CLK_DEBUG(ocram_clk)
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+	.enable = _clk_ocram_enable,
+	.disable = _clk_ocram_disable,
+};
+
+
+static struct clk aips_tz1_clk = {
+	__INIT_CLK_DEBUG(aips_tz1_clk)
+	.parent = &ahb_clk,
+	.secondary = &ahb_max_clk,
+	.enable_reg = MXC_CCM_CCGR0,
+	.enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable_inwait,
+};
+
+static struct clk aips_tz2_clk = {
+	__INIT_CLK_DEBUG(aips_tz2_clk)
+	.parent = &ahb_clk,
+	.secondary = &ahb_max_clk,
+	.enable_reg = MXC_CCM_CCGR0,
+	.enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable_inwait,
+};
+
+static struct clk gpc_dvfs_clk = {
+	__INIT_CLK_DEBUG(gpc_dvfs_clk)
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+};
+
+static int _clk_sdma_enable(struct clk *clk)
+{
+	u32 reg;
+
+	_clk_enable(clk);
+
+	/* Handshake with SDMA when LPM is entered. */
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	if (cpu_is_mx51())
+		reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51;
+	else
+		reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+
+	return 0;
+}
+
+static void _clk_sdma_disable(struct clk *clk)
+{
+	u32 reg;
+
+	_clk_disable(clk);
+	/* No handshake with SDMA as its not enabled. */
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	if (cpu_is_mx51())
+		reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51;
+	else
+		reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+
+static struct clk sdma_clk[] = {
+	{
+	 __INIT_CLK_DEBUG(sdma_clk)
+	 .parent = &ahb_clk,
+	 .enable_reg = MXC_CCM_CCGR4,
+	 .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	 .enable = _clk_sdma_enable,
+	 .disable = _clk_sdma_disable,
+	 },
+	{
+	 .parent = &ipg_clk,
+#ifdef CONFIG_SDMA_IRAM
+	 .secondary = &emi_intr_clk[0],
+#endif
+	 },
+};
+
+static int _clk_ipu_enable(struct clk *clk)
+{
+	u32 reg;
+
+	_clk_enable(clk);
+	/* Handshake with IPU when certain clock rates are changed. */
+	reg = __raw_readl(MXC_CCM_CCDR);
+	if (cpu_is_mx51())
+		reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
+	else
+		reg &= ~MXC_CCM_CCDR_IPU_HS_MX53_MASK;
+	__raw_writel(reg, MXC_CCM_CCDR);
+
+	/* Handshake with IPU when LPM is entered as its enabled. */
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+
+	start_sdram_autogating();
+
+	return 0;
+}
+
+static void _clk_ipu_disable(struct clk *clk)
+{
+	u32 reg;
+
+	if (sdram_autogating_active())
+		stop_sdram_autogating();
+
+	_clk_disable(clk);
+
+	/* No handshake with IPU whe dividers are changed
+	 * as its not enabled. */
+	reg = __raw_readl(MXC_CCM_CCDR);
+	if (cpu_is_mx51())
+		reg |= MXC_CCM_CCDR_IPU_HS_MASK;
+	else
+		reg |= MXC_CCM_CCDR_IPU_HS_MX53_MASK;
+	__raw_writel(reg, MXC_CCM_CCDR);
+
+	/* No handshake with IPU when LPM is entered as its not enabled. */
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static int _clk_ipu_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+	reg = __raw_readl(MXC_CCM_CBCMR);
+	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &ahb_clk,
+		       &emi_slow_clk);
+	reg = (reg & ~MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK) |
+	    (mux << MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCMR);
+
+	return 0;
+}
+
+
+static struct clk ipu_clk[] = {
+	{
+	 __INIT_CLK_DEBUG(ipu_clk)
+	.parent = &ahb_clk,
+	.secondary = &ipu_clk[1],
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+	.enable = _clk_ipu_enable,
+	.disable = _clk_ipu_disable,
+	.set_parent = _clk_ipu_set_parent,
+	 .flags = CPU_FREQ_TRIG_UPDATE | AHB_MED_SET_POINT,
+	},
+	{
+	 __INIT_CLK_DEBUG(ipu_clk_1)
+	 .parent = &emi_fast_clk,
+	 .secondary = &ahbmux1_clk,
+	}
+};
+
+static int _clk_ipu_di_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+	reg &= ~MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id);
+	if (parent == &pll3_sw_clk)
+		;
+	else if (parent == &osc_clk)
+		reg |= 1 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+	else if (parent == &ckih_clk)
+		reg |= 2 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+	else if ((parent == &pll4_sw_clk) && (clk->id == 0)) {
+		if (cpu_is_mx51())
+			return -EINVAL;
+		reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+	} else if ((parent == &tve_clk) && (clk->id == 1))
+		reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+	else if ((parent == &ldb_di_clk[clk->id]) && cpu_is_mx53())
+		reg |= 5 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+	else		/* Assume any other clock is external clock pin */
+		reg |= 4 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static int priv_div;
+static unsigned long _clk_ipu_di_get_rate(struct clk *clk)
+{
+	u32 reg, mux;
+	u32 div = 1;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+	mux = (reg & MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id)) >>
+		MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+	if (mux == 0) {
+		reg = __raw_readl(MXC_CCM_CDCDR) &
+		    MXC_CCM_CDCDR_DI1_CLK_PRED_MASK;
+		div = (reg >> MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET) + 1;
+	} else if ((mux == 3) && (clk->id == 1)) {
+		if (priv_div)
+			div = priv_div;
+	} else if ((mux == 3) && (clk->id == 0)) {
+		reg = __raw_readl(MXC_CCM_CDCDR) &
+			MXC_CCM_CDCDR_DI_PLL4_PODF_MASK;
+		div = (reg >> MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET) + 1;
+	}
+	return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || (div > 8))
+		return -EINVAL;
+
+	if ((clk->parent == &pll4_sw_clk) && (clk->id == 0)) {
+		reg = __raw_readl(MXC_CCM_CDCDR);
+		reg &= ~MXC_CCM_CDCDR_DI_PLL4_PODF_MASK;
+		reg |= (div - 1) << MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET;
+		__raw_writel(reg, MXC_CCM_CDCDR);
+	} else if (clk->parent == &pll3_sw_clk) {
+		reg = __raw_readl(MXC_CCM_CDCDR);
+		reg &= ~MXC_CCM_CDCDR_DI1_CLK_PRED_MASK;
+		reg |= (div - 1) << MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET;
+		__raw_writel(reg, MXC_CCM_CDCDR);
+	} else if (((clk->parent == &tve_clk) && (clk->id == 1)) ||
+		((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53())) {
+		priv_div = div;
+		return 0;
+	} else
+		return -EINVAL;
+
+	return 0;
+}
+
+static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
+					    unsigned long rate)
+{
+	u32 div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	if ((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53())
+		return parent_rate;
+	else {
+		div = (parent_rate + rate/2) / rate;
+		if (div > 8)
+			div = 8;
+		else if (div == 0)
+			div++;
+		return parent_rate / div;
+	}
+}
+
+static struct clk ipu_di_clk[] = {
+	{
+	 __INIT_CLK_DEBUG(ipu_di_clk_0)
+	.id = 0,
+	.parent = &pll3_sw_clk,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+	.get_rate = _clk_ipu_di_get_rate,
+	.set_parent = _clk_ipu_di_set_parent,
+	.round_rate = _clk_ipu_di_round_rate,
+	.set_rate = _clk_ipu_di_set_rate,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	},
+	{
+	 __INIT_CLK_DEBUG(ipu_di_clk_1)
+	.id = 1,
+	.parent = &pll3_sw_clk,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+	.get_rate = _clk_ipu_di_get_rate,
+	.set_parent = _clk_ipu_di_set_parent,
+	.round_rate = _clk_ipu_di_round_rate,
+	.set_rate = _clk_ipu_di_set_rate,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	},
+};
+
+static int _clk_ldb_di_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+
+	if ((parent == &pll3_sw_clk)) {
+		if (clk->id == 0)
+			reg &= ~(MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL);
+		else
+			reg &= ~(MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL);
+	} else if ((parent == &pll4_sw_clk)) {
+		if (clk->id == 0)
+			reg |= MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL;
+		else
+			reg |= MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL;
+	} else {
+		BUG();
+	}
+
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+	return 0;
+}
+
+static unsigned long _clk_ldb_di_get_rate(struct clk *clk)
+{
+	u32 div;
+
+	if (clk->id == 0)
+		div = __raw_readl(MXC_CCM_CSCMR2) &
+			MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	else
+		div = __raw_readl(MXC_CCM_CSCMR2) &
+			MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+
+	if (div)
+		return clk_get_rate(clk->parent) / 7;
+
+	return (2 * clk_get_rate(clk->parent)) / 7;
+}
+
+static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	if (rate * 7 <= parent_rate + parent_rate/20)
+		return parent_rate / 7;
+	else
+		return 2 * parent_rate / 7;
+}
+
+static int _clk_ldb_di_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div = 0;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	if (rate * 7 <= parent_rate + parent_rate/20) {
+		div = 7;
+		rate = parent_rate / 7;
+	} else
+		rate = 2 * parent_rate / 7;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+	if (div == 7)
+		reg |= (clk->id ? MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV :
+			MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+	else
+		reg &= ~(clk->id ? MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV :
+			MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static int _clk_ldb_di_enable(struct clk *clk)
+{
+	_clk_enable(clk);
+	ipu_di_clk[clk->id].set_parent(&ipu_di_clk[clk->id], clk);
+	ipu_di_clk[clk->id].parent = clk;
+	ipu_di_clk[clk->id].enable(&ipu_di_clk[clk->id]);
+	ipu_di_clk[clk->id].usecount++;
+	return 0;
+}
+
+static void _clk_ldb_di_disable(struct clk *clk)
+{
+	_clk_disable(clk);
+	ipu_di_clk[clk->id].disable(&ipu_di_clk[clk->id]);
+	ipu_di_clk[clk->id].usecount--;
+}
+
+static struct clk ldb_di_clk[] = {
+	{
+	 __INIT_CLK_DEBUG(ldb_di_clk_0)
+	.id = 0,
+	.parent = &pll4_sw_clk,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+	.get_rate = _clk_ldb_di_get_rate,
+	.set_parent = _clk_ldb_di_set_parent,
+	.round_rate = _clk_ldb_di_round_rate,
+	.set_rate = _clk_ldb_di_set_rate,
+	.enable = _clk_ldb_di_enable,
+	.disable = _clk_ldb_di_disable,
+	.flags = AHB_MED_SET_POINT,
+	},
+	{
+	 __INIT_CLK_DEBUG(ldb_di_clk_1)
+	.id = 1,
+	.parent = &pll4_sw_clk,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	.get_rate = _clk_ldb_di_get_rate,
+	.set_parent = _clk_ldb_di_set_parent,
+	.round_rate = _clk_ldb_di_round_rate,
+	.set_rate = _clk_ldb_di_set_rate,
+	.enable = _clk_ldb_di_enable,
+	.disable = _clk_ldb_di_disable,
+	.flags = AHB_MED_SET_POINT,
+	},
+};
+
+static int _clk_csi0_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL);
+	reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK) |
+		    (mux << MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET);
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static unsigned long _clk_csi0_get_rate(struct clk *clk)
+{
+	u32 reg, pred, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR4);
+	pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK) >>
+			MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK) >>
+			MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent)/(pred * podf);
+}
+
+static unsigned long _clk_csi0_round_rate(struct clk *clk, unsigned long rate)
+{
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+	u32 div = parent_rate / rate;
+	if (parent_rate % rate)
+		div++;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	return parent_rate / (pre * post);
+}
+
+static int _clk_csi0_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg;
+	u32 div;
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if ((parent_rate / div) != rate)
+		return -EINVAL;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	/* Set CSI clock divider */
+	reg = __raw_readl(MXC_CCM_CSCDR4) &
+	    ~(MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK |
+		MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK);
+	reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET;
+	reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR4);
+
+	return 0;
+}
+
+static struct clk csi0_clk = {
+	.parent = &pll3_sw_clk,
+	.set_parent = _clk_csi0_set_parent,
+	.get_rate = _clk_csi0_get_rate,
+	.round_rate = _clk_csi0_round_rate,
+	.set_rate = _clk_csi0_set_rate,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+	.disable = _clk_disable,
+};
+
+static int _clk_csi1_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL);
+	reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK) |
+		    (mux << MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET);
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static unsigned long _clk_csi1_get_rate(struct clk *clk)
+{
+	u32 reg, pred, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR4);
+	pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK) >>
+			MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK) >>
+			MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent)/(pred * podf) ;
+}
+
+static unsigned long _clk_csi1_round_rate(struct clk *clk, unsigned long rate)
+{
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+	u32 div = parent_rate / rate;
+	if (parent_rate % rate)
+		div++;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	return parent_rate / (pre * post);
+}
+
+static int _clk_csi1_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg;
+	u32 div;
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if ((parent_rate / div) != rate)
+		return -EINVAL;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	/* Set CSI clock divider */
+	reg = __raw_readl(MXC_CCM_CSCDR4) &
+	    ~(MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK |
+		MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK);
+	reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET;
+	reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR4);
+
+	return 0;
+}
+
+static struct clk csi1_clk = {
+	__INIT_CLK_DEBUG(csi1_clk)
+	.parent = &pll3_sw_clk,
+	.set_parent = _clk_csi1_set_parent,
+	.get_rate = _clk_csi1_get_rate,
+	.round_rate = _clk_csi1_round_rate,
+	.set_rate = _clk_csi1_set_rate,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+	.disable = _clk_disable,
+};
+
+
+static int _clk_hsc_enable(struct clk *clk)
+{
+	u32 reg;
+
+	_clk_enable(clk);
+	/* Handshake with IPU when certain clock rates are changed. */
+	reg = __raw_readl(MXC_CCM_CCDR);
+	reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
+	__raw_writel(reg, MXC_CCM_CCDR);
+
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+
+	return 0;
+}
+
+static void _clk_hsc_disable(struct clk *clk)
+{
+	u32 reg;
+
+	_clk_disable(clk);
+	/* No handshake with HSC as its not enabled. */
+	reg = __raw_readl(MXC_CCM_CCDR);
+	reg |= MXC_CCM_CCDR_HSC_HS_MASK;
+	__raw_writel(reg, MXC_CCM_CCDR);
+
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static struct clk mipi_esc_clk = {
+	__INIT_CLK_DEBUG(mipi_esc_clk)
+	.parent = &pll2_sw_clk,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+};
+
+static struct clk mipi_hsc2_clk = {
+	__INIT_CLK_DEBUG(mipi_hsc2_clk)
+	.parent = &pll2_sw_clk,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+	.secondary = &mipi_esc_clk,
+};
+
+static struct clk mipi_hsc1_clk = {
+	__INIT_CLK_DEBUG(mipi_hsc1_clk)
+	.parent = &pll2_sw_clk,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+	.secondary = &mipi_hsc2_clk,
+};
+
+static struct clk mipi_hsp_clk = {
+	__INIT_CLK_DEBUG(mipi_hsp_clk)
+	.parent = &ipu_clk[0],
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+	.enable = _clk_hsc_enable,
+	.disable = _clk_hsc_disable,
+	.secondary = &mipi_hsc1_clk,
+};
+
+static int _clk_tve_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CSCMR1);
+
+	if ((parent == &pll3_sw_clk) && cpu_is_mx51()) {
+		reg &= ~(MXC_CCM_CSCMR1_TVE_CLK_SEL);
+	} else if ((parent == &pll4_sw_clk) && cpu_is_mx53()) {
+		reg &= ~(MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL);
+	} else if ((parent == &osc_clk) && cpu_is_mx51()) {
+		reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL;
+		reg &= ~MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL;
+	} else if (parent == &ckih_clk) {
+		reg |= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL;
+		reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; /* Reserved on MX53 */
+	} else {
+		BUG();
+	}
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+	return 0;
+}
+
+static unsigned long _clk_tve_get_rate(struct clk *clk)
+{
+	u32 reg, div = 1;
+
+	reg = __raw_readl(MXC_CCM_CSCMR1);
+	if ((reg & (MXC_CCM_CSCMR1_TVE_CLK_SEL | MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) == 0) {
+		reg = __raw_readl(MXC_CCM_CDCDR) &
+		    MXC_CCM_CDCDR_TVE_CLK_PRED_MASK;
+		div = (reg >> MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET) + 1;
+	}
+	return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long _clk_tve_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 reg, div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	reg = __raw_readl(MXC_CCM_CSCMR1);
+	if (cpu_is_mx51() && (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL))
+		return -EINVAL;
+	if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL))
+		return -EINVAL;
+
+	div = (parent_rate + rate/2) / rate;
+	if (div > 8)
+		div = 8;
+	else if (div == 0)
+		div++;
+	return parent_rate / div;
+}
+
+static int _clk_tve_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	reg = __raw_readl(MXC_CCM_CSCMR1);
+	if (cpu_is_mx51() && (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL))
+		return -EINVAL;
+	if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL))
+		return -EINVAL;
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || (div > 8))
+		return -EINVAL;
+
+	div--;
+	reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_TVE_CLK_PRED_MASK;
+	reg |= div << MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CDCDR);
+	return 0;
+}
+
+static struct clk tve_clk = {
+	__INIT_CLK_DEBUG(tve_clk)
+	.parent = &pll3_sw_clk,
+	.set_parent = _clk_tve_set_parent,
+	.enable_reg = MXC_CCM_CCGR2,
+	.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	.get_rate = _clk_tve_get_rate,
+	.round_rate = _clk_tve_round_rate,
+	.set_rate = _clk_tve_set_rate,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+};
+
+static struct clk spba_clk = {
+	__INIT_CLK_DEBUG(spba_clk)
+	.parent = &ipg_clk,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+};
+
+static unsigned long _clk_uart_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR1);
+	prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+		  MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent)/(prediv * podf) ;
+}
+
+static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+		       &lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk uart_main_clk = {
+	__INIT_CLK_DEBUG(uart_main_clk)
+	.parent = &pll2_sw_clk,
+	.get_rate = _clk_uart_get_rate,
+	.set_parent = _clk_uart_set_parent,
+};
+
+static struct clk uart1_clk[] = {
+	{
+	__INIT_CLK_DEBUG(uart1_clk_0)
+	 .id = 0,
+	 .parent = &uart_main_clk,
+	 .secondary = &uart1_clk[1],
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+#if UART1_DMA_ENABLE
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+	 },
+	{
+	__INIT_CLK_DEBUG(uart1_clk_1)
+	 .id = 0,
+	 .parent = &ipg_clk,
+#if UART1_DMA_ENABLE
+	 .secondary = &aips_tz1_clk,
+#endif
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+};
+
+static struct clk uart2_clk[] = {
+	{
+	__INIT_CLK_DEBUG(uart2_clk_0)
+	 .id = 1,
+	 .parent = &uart_main_clk,
+	 .secondary = &uart2_clk[1],
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+#if UART2_DMA_ENABLE
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+	 },
+	{
+	__INIT_CLK_DEBUG(uart2_clk_1)
+	 .id = 1,
+	 .parent = &ipg_clk,
+#if UART2_DMA_ENABLE
+	 .secondary = &aips_tz1_clk,
+#endif
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+};
+
+static struct clk uart3_clk[] = {
+	{
+	__INIT_CLK_DEBUG(uart3_clk_0)
+	 .id = 2,
+	 .parent = &uart_main_clk,
+	 .secondary = &uart3_clk[1],
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+#if UART3_DMA_ENABLE
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+	 },
+	{
+	__INIT_CLK_DEBUG(uart3_clk_1)
+	 .id = 2,
+	 .parent = &ipg_clk,
+	 .secondary = &spba_clk,
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+};
+
+static struct clk uart4_clk[] = {
+	{
+	__INIT_CLK_DEBUG(uart4_clk_0)
+	 .id = 3,
+	 .parent = &uart_main_clk,
+	 .secondary = &uart4_clk[1],
+	 .enable_reg = MXC_CCM_CCGR7,
+	 .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+#if UART4_DMA_ENABLE
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+	 },
+	{
+	__INIT_CLK_DEBUG(uart4_clk_1)
+	 .id = 3,
+	 .parent = &ipg_clk,
+	 .secondary = &spba_clk,
+	 .enable_reg = MXC_CCM_CCGR7,
+	 .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+};
+
+static struct clk uart5_clk[] = {
+	{
+	__INIT_CLK_DEBUG(uart5_clk_0)
+	 .id = 4,
+	 .parent = &uart_main_clk,
+	 .secondary = &uart5_clk[1],
+	 .enable_reg = MXC_CCM_CCGR7,
+	 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+#if UART5_DMA_ENABLE
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+	 },
+	{
+	__INIT_CLK_DEBUG(uart5_clk_1)
+	 .id = 4,
+	 .parent = &ipg_clk,
+	 .secondary = &spba_clk,
+	 .enable_reg = MXC_CCM_CCGR7,
+	 .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+};
+
+static struct clk gpt_clk[] = {
+	{
+	__INIT_CLK_DEBUG(gpt_clki_0)
+	 .parent = &ipg_perclk,
+	 .id = 0,
+	 .enable_reg = MXC_CCM_CCGR2,
+	 .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 .secondary = &gpt_clk[1],
+	 },
+	{
+	__INIT_CLK_DEBUG(gpt_clki_1)
+	 .id = 0,
+	 .parent = &ipg_clk,
+	 .enable_reg = MXC_CCM_CCGR2,
+	 .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(gpt_clki_2)
+	 .id = 0,
+	 .parent = &ckil_clk,
+	 },
+};
+
+static struct clk pwm1_clk[] = {
+	{
+	__INIT_CLK_DEBUG(pwm1_clk_0)
+	 .parent = &ipg_perclk,
+	 .id = 0,
+	 .enable_reg = MXC_CCM_CCGR2,
+	 .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 .secondary = &pwm1_clk[1],
+	 },
+	{
+	__INIT_CLK_DEBUG(pwm1_clk_1)
+	 .id = 0,
+	 .parent = &ipg_clk,
+	 .enable_reg = MXC_CCM_CCGR2,
+	 .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+	 .enable = _clk_enable_inrun, /*Active only when ARM is running. */
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(pwm1_clk_2)
+	 .id = 0,
+	 .parent = &ckil_clk,
+	 },
+};
+
+static struct clk pwm2_clk[] = {
+	{
+	__INIT_CLK_DEBUG(pwm2_clk_0)
+	 .parent = &ipg_perclk,
+	 .id = 1,
+	 .enable_reg = MXC_CCM_CCGR2,
+	 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 .secondary = &pwm2_clk[1],
+	 },
+	{
+	__INIT_CLK_DEBUG(pwm2_clk_1)
+	 .id = 1,
+	 .parent = &ipg_clk,
+	 .enable_reg = MXC_CCM_CCGR2,
+	 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+	 .enable = _clk_enable_inrun, /*Active only when ARM is running. */
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(pwm2_clk_2)
+	 .id = 1,
+	 .parent = &ckil_clk,
+	 },
+};
+
+static struct clk i2c_clk[] = {
+	{
+	__INIT_CLK_DEBUG(i2c_clk_0)
+	 .id = 0,
+	 .parent = &ipg_perclk,
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(i2c_clk_1)
+	 .id = 1,
+	 .parent = &ipg_perclk,
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(i2c_clk_2)
+	 .id = 2,
+	 .parent = &ipg_perclk,
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+};
+
+static unsigned long _clk_hsi2c_serial_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR3);
+	prediv = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK) >>
+		  MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static struct clk hsi2c_serial_clk = {
+	__INIT_CLK_DEBUG(hsi2c_serial_clk)
+	.id = 0,
+	.parent = &pll3_sw_clk,
+	.secondary = &spba_clk,
+	.enable_reg = MXC_CCM_CCGR1,
+	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+	.get_rate = _clk_hsi2c_serial_get_rate,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+};
+
+static struct clk hsi2c_clk = {
+	__INIT_CLK_DEBUG(hsi2c_clk)
+	.id = 0,
+	.parent = &ipg_clk,
+	.enable_reg = MXC_CCM_CCGR1,
+	.enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+};
+
+static unsigned long _clk_cspi_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+	prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
+		  MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
+	if (prediv == 1)
+		BUG();
+	podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+		       &lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk cspi_main_clk = {
+	__INIT_CLK_DEBUG(cspi_main_clk)
+	.parent = &pll3_sw_clk,
+	.get_rate = _clk_cspi_get_rate,
+	.set_parent = _clk_cspi_set_parent,
+};
+
+static struct clk cspi1_clk[] = {
+	{
+	__INIT_CLK_DEBUG(cspi1_clk_0)
+	 .id = 0,
+	 .parent = &cspi_main_clk,
+	 .secondary = &cspi1_clk[1],
+	 .enable_reg = MXC_CCM_CCGR4,
+	 .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(cspi1_clk_1)
+	 .id = 0,
+	 .parent = &ipg_clk,
+	 .secondary = &spba_clk,
+	 .enable_reg = MXC_CCM_CCGR4,
+	 .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+	 .enable = _clk_enable_inrun, /*Active only when ARM is running. */
+	 .disable = _clk_disable,
+	 },
+};
+
+static struct clk cspi2_clk[] = {
+	{
+	__INIT_CLK_DEBUG(cspi2_clk_0)
+	 .id = 1,
+	 .parent = &cspi_main_clk,
+	 .secondary = &cspi2_clk[1],
+	 .enable_reg = MXC_CCM_CCGR4,
+	 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(cspi2_clk_1)
+	 .id = 1,
+	 .parent = &ipg_clk,
+	 .secondary = &aips_tz2_clk,
+	 .enable_reg = MXC_CCM_CCGR4,
+	 .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+	 .enable = _clk_enable_inrun, /*Active only when ARM is running. */
+	 .disable = _clk_disable,
+	 },
+};
+
+static struct clk cspi3_clk = {
+	__INIT_CLK_DEBUG(cspi3_clk)
+	.id = 2,
+	.parent = &ipg_clk,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	.secondary = &aips_tz2_clk,
+};
+
+static unsigned long _clk_ieee_rtc_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+	prediv = ((reg & MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK) >>
+		  MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET) + 1;
+	if (prediv == 1)
+		BUG();
+	podf = ((reg & MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_ieee_rtc_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div, pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || div > 512)
+		return -EINVAL;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+	reg &= ~(MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK |
+		 MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK);
+	reg |= (post - 1) << MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET;
+	reg |= (pre - 1) << MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR2);
+
+	return 0;
+}
+
+static unsigned long _clk_ieee_rtc_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+	u32 div = parent_rate / rate;
+
+	if (parent_rate % rate)
+		div++;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	return parent_rate / (pre * post);
+}
+
+static int _clk_ieee_rtc_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll3_sw_clk, &pll4_sw_clk,
+		       NULL, NULL);
+	reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static struct clk ieee_rtc_clk = {
+	__INIT_CLK_DEBUG(ieee_rtc_clk)
+	.id = 0,
+	.parent = &pll3_sw_clk,
+	.set_parent = _clk_ieee_rtc_set_parent,
+	.set_rate = _clk_ieee_rtc_set_rate,
+	.round_rate = _clk_ieee_rtc_round_rate,
+	.get_rate = _clk_ieee_rtc_get_rate,
+};
+
+static int _clk_ssi_lp_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &ckih_clk, &lp_apm_clk, &ckih2_clk, NULL);
+	reg = __raw_readl(MXC_CCM_CSCMR1) &
+	    ~MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk ssi_lp_apm_clk = {
+	__INIT_CLK_DEBUG(ssi_lp_apm_clk)
+	.parent = &ckih_clk,
+	.set_parent = _clk_ssi_lp_apm_set_parent,
+};
+
+static unsigned long _clk_ssi1_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CS1CDR);
+	prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) >>
+		  MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
+	if (prediv == 1)
+		BUG();
+	podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) >>
+		MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / (prediv * podf);
+}
+static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,
+		       &pll3_sw_clk, &ssi_lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk ssi1_clk[] = {
+	{
+	__INIT_CLK_DEBUG(ssi1_clk_0)
+	 .id = 0,
+	 .parent = &pll3_sw_clk,
+	 .set_parent = _clk_ssi1_set_parent,
+	 .secondary = &ssi1_clk[1],
+	 .get_rate = _clk_ssi1_get_rate,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(ssi1_clk_1)
+	 .id = 0,
+	 .parent = &ipg_clk,
+	 .secondary = &ssi1_clk[2],
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(ssi1_clk_2)
+	 .id = 0,
+	 .parent = &aips_tz2_clk,
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+	 .secondary = &emi_intr_clk[0],
+#else
+	 .secondary = &emi_fast_clk,
+#endif
+	 },
+};
+
+static unsigned long _clk_ssi2_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CS2CDR);
+	prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK) >>
+		  MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
+	if (prediv == 1)
+		BUG();
+	podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK) >>
+		MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,
+		       &pll3_sw_clk, &ssi_lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk ssi2_clk[] = {
+	{
+	__INIT_CLK_DEBUG(ssi2_clk_0)
+	 .id = 1,
+	 .parent = &pll3_sw_clk,
+	 .set_parent = _clk_ssi2_set_parent,
+	 .secondary = &ssi2_clk[1],
+	 .get_rate = _clk_ssi2_get_rate,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(ssi2_clk_1)
+	 .id = 1,
+	 .parent = &ipg_clk,
+	 .secondary = &ssi2_clk[2],
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(ssi2_clk_2)
+	 .id = 1,
+	 .parent = &spba_clk,
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+	 .secondary = &emi_intr_clk[0],
+#else
+	 .secondary = &emi_fast_clk,
+#endif
+	 },
+};
+
+static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL;
+
+	if (parent == &ssi1_clk[0])
+		reg &= ~MXC_CCM_CSCMR1_SSI3_CLK_SEL;
+	else if (parent == &ssi2_clk[0])
+		reg |= MXC_CCM_CSCMR1_SSI3_CLK_SEL;
+	else {
+		printk(KERN_ERR"Set ssi3 clock parent failed!\n");
+		printk(KERN_ERR"ssi3 only support");
+		printk(KERN_ERR"ssi1 and ssi2 as parent clock\n");
+		return -1;
+	}
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+	return 0;
+}
+
+static struct clk ssi3_clk[] = {
+	{
+	__INIT_CLK_DEBUG(ssi3_clk_0)
+	 .id = 2,
+	 .parent = &ssi1_clk[0],
+	 .set_parent = _clk_ssi3_set_parent,
+	 .secondary = &ssi3_clk[1],
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(ssi3_clk_1)
+	 .id = 2,
+	 .parent = &ipg_clk,
+	 .secondary = &ssi3_clk[2],
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(ssi3_clk_2)
+	 .id = 2,
+	 .parent = &aips_tz2_clk,
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+	 .secondary = &emi_intr_clk,
+#else
+	 .secondary = &emi_fast_clk,
+#endif
+	 },
+};
+
+static unsigned long _clk_ssi_ext1_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+	u32 div = 1;
+
+	reg = __raw_readl(MXC_CCM_CSCMR1);
+	if ((reg & MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL) == 0) {
+		reg = __raw_readl(MXC_CCM_CS1CDR);
+		prediv = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK) >>
+			  MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET) + 1;
+		podf = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK) >>
+			MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET) + 1;
+		div = prediv * podf;
+	}
+	return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_ssi_ext1_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div, pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || div > 512)
+		return -EINVAL;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	reg = __raw_readl(MXC_CCM_CS1CDR);
+	reg &= ~(MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK |
+		 MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK);
+	reg |= (post - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET;
+	reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CS1CDR);
+
+	return 0;
+}
+
+static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CSCMR1);
+	if (parent == &ssi1_clk[0]) {
+		reg |= MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL;
+	} else {
+		reg &= ~MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL;
+		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+			       &ssi_lp_apm_clk);
+		reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK) |
+		    (mux << MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET);
+	}
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static unsigned long _clk_ssi_ext1_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+	u32 div = parent_rate / rate;
+
+	if (parent_rate % rate)
+		div++;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	return parent_rate / (pre * post);
+}
+
+static struct clk ssi_ext1_clk = {
+	__INIT_CLK_DEBUG(ssi_ext1_clk)
+	.parent = &pll3_sw_clk,
+	.set_parent = _clk_ssi_ext1_set_parent,
+	.set_rate = _clk_ssi_ext1_set_rate,
+	.round_rate = _clk_ssi_ext1_round_rate,
+	.get_rate = _clk_ssi_ext1_get_rate,
+	.enable_reg = MXC_CCM_CCGR3,
+	.enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+};
+
+static unsigned long _clk_ssi_ext2_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+	u32 div = 1;
+
+	reg = __raw_readl(MXC_CCM_CSCMR1);
+	if ((reg & MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL) == 0) {
+		reg = __raw_readl(MXC_CCM_CS2CDR);
+		prediv = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK) >>
+			  MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET) + 1;
+		if (prediv == 1)
+			BUG();
+		podf = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK) >>
+			MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET) + 1;
+		div = prediv * podf;
+	}
+	return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_ssi_ext2_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CSCMR1);
+	if (parent == &ssi2_clk[0]) {
+		reg |= MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL;
+	} else {
+		reg &= ~MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL;
+		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+			       &ssi_lp_apm_clk);
+		reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK) |
+		    (mux << MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET);
+	}
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk ssi_ext2_clk = {
+	__INIT_CLK_DEBUG(ssi_ext2_clk)
+	.parent = &pll3_sw_clk,
+	.set_parent = _clk_ssi_ext2_set_parent,
+	.get_rate = _clk_ssi_ext2_get_rate,
+	.enable_reg = MXC_CCM_CCGR3,
+	.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+};
+
+static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+	if (parent ==  &pll1_sw_clk || parent ==  &pll2_sw_clk ||
+		    parent ==  &pll3_sw_clk) {
+		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+			NULL);
+		reg &= ~MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK;
+		reg |= mux << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET;
+		reg &= ~MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK;
+		reg |= 0 << MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET;
+		/* divider setting */
+	} else {
+		mux = _get_mux(parent, &ssi1_clk[0], &ssi2_clk[0], &ckih_clk,
+			&ckih2_clk);
+		reg &= ~MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK;
+		reg |= (mux + 1) << MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET;
+		/* divider setting */
+	}
+
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	/* set podf = 0 */
+	reg = __raw_readl(MXC_CCM_CS1CDR);
+	reg &= ~MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK;
+	__raw_writel(reg, MXC_CCM_CS1CDR);
+
+	return 0;
+}
+
+static unsigned long _clk_esai_get_rate(struct clk *clk)
+{
+	u32 reg, pred, podf;
+
+	reg = __raw_readl(MXC_CCM_CS1CDR);
+	if (clk->parent ==  &pll1_sw_clk || clk->parent ==  &pll2_sw_clk ||
+		    clk->parent ==  &pll3_sw_clk) {
+		pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK) >>
+			MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
+		podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK) >>
+			MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
+
+		return clk_get_rate(clk->parent) / (pred * podf);
+	} else {
+		podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK) >>
+			MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
+
+		return clk_get_rate(clk->parent) / podf;
+	}
+}
+
+static struct clk esai_clk[] = {
+	{
+	__INIT_CLK_DEBUG(esai_clk_0)
+	 .id = 0,
+	 .parent = &pll3_sw_clk,
+	 .set_parent = _clk_esai_set_parent,
+	 .get_rate = _clk_esai_get_rate,
+	 .secondary = &esai_clk[1],
+	 .enable_reg = MXC_CCM_CCGR6,
+	 .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(esai_clk_1)
+	 .id = 0,
+	 .parent = &ipg_clk,
+	 .enable_reg = MXC_CCM_CCGR6,
+	 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+};
+
+static struct clk iim_clk = {
+	__INIT_CLK_DEBUG(iim_clk)
+	.parent = &ipg_clk,
+	.secondary = &aips_tz2_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR0,
+	.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk tmax1_clk = {
+	__INIT_CLK_DEBUG(tmax1_clk)
+	 .id = 0,
+	 .parent = &ahb_clk,
+	 .secondary = &ahb_max_clk,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+	 .disable = _clk_disable,
+	 };
+
+static struct clk tmax2_clk = {
+	__INIT_CLK_DEBUG(tmax2_clk)
+	 .id = 0,
+	 .parent = &ahb_clk,
+	 .secondary = &ahb_max_clk,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+	 .disable = _clk_disable,
+};
+
+static struct clk tmax3_clk = {
+	__INIT_CLK_DEBUG(tmax3_clk)
+	 .id = 0,
+	 .parent = &ahb_clk,
+	 .secondary = &ahb_max_clk,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR1,
+	 .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+	 .disable = _clk_disable,
+};
+
+static unsigned long _clk_usboh3_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR1);
+	prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
+		  MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
+	if (prediv == 1)
+		BUG();
+	podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+		       &lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk usboh3_clk[] = {
+	{
+	__INIT_CLK_DEBUG(usboh3_clk_0)
+	 .parent = &pll3_sw_clk,
+	 .set_parent = _clk_usboh3_set_parent,
+	 .get_rate = _clk_usboh3_get_rate,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR2,
+	 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+	 .disable = _clk_disable,
+	 .secondary = &usboh3_clk[1],
+	 .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	 },
+	{
+	__INIT_CLK_DEBUG(usboh3_clk_1)
+	 .parent = &tmax2_clk,
+#if defined(CONFIG_USB_STATIC_IRAM) \
+    || defined(CONFIG_USB_STATIC_IRAM_PPH)
+	 .secondary = &emi_intr_clk[0],
+#else
+	 .secondary = &emi_fast_clk,
+#endif
+	 },
+};
+
+static struct clk usb_ahb_clk = {
+	__INIT_CLK_DEBUG(usb_ahb_clk)
+	 .parent = &ipg_clk,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR2,
+	 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+	 .disable = _clk_disable,
+};
+
+static unsigned long _clk_usb_phy_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+	u32 div = 1;
+
+	if (clk->parent == &pll3_sw_clk) {
+		reg = __raw_readl(MXC_CCM_CDCDR);
+		prediv = ((reg & MXC_CCM_CDCDR_USB_PHY_PRED_MASK) >>
+			  MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET) + 1;
+		podf = ((reg & MXC_CCM_CDCDR_USB_PHY_PODF_MASK) >>
+			MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET) + 1;
+
+		div = (prediv * podf);
+	}
+
+	return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_usb_phy_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CSCMR1);
+	if (parent == &osc_clk)
+		reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+	else if (parent == &pll3_sw_clk)
+		reg |= MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+	else
+		BUG();
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+	return 0;
+}
+
+static struct clk usb_phy_clk[] = {
+	{
+	__INIT_CLK_DEBUG(usb_phy_clk_0)
+	.id = 0,
+	.parent = &pll3_sw_clk,
+	.secondary = &tmax3_clk,
+	.set_parent = _clk_usb_phy_set_parent,
+	.get_rate = _clk_usb_phy_get_rate,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR2,
+	.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+	.disable = _clk_disable,
+	},
+	{
+	__INIT_CLK_DEBUG(usb_phy_clk_1)
+	.id = 1,
+	.parent = &pll3_sw_clk,
+	.secondary = &tmax3_clk,
+	.set_parent = _clk_usb_phy_set_parent,
+	.get_rate = _clk_usb_phy_get_rate,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+	.disable = _clk_disable,
+	}
+};
+
+static struct clk esdhc_dep_clks = {
+	__INIT_CLK_DEBUG(esdhc_dep_clks)
+	 .parent = &spba_clk,
+	 .secondary = &emi_fast_clk,
+};
+
+static unsigned long _clk_esdhc1_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR1);
+	prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK) >>
+		  MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+		       &lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CSCMR1) &
+	    ~MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+
+static int _clk_sdhc1_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg;
+	u32 div;
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if ((parent_rate / div) != rate)
+		return -EINVAL;
+
+	 __calc_pre_post_dividers(div, &pre, &post);
+
+	/* Set sdhc1 clock divider */
+	reg = __raw_readl(MXC_CCM_CSCDR1) &
+		~(MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK |
+		MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK);
+	reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET;
+	reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR1);
+
+	return 0;
+}
+
+static struct clk esdhc1_clk[] = {
+	{
+	__INIT_CLK_DEBUG(esdhc1_clk_0)
+	 .id = 0,
+	 .parent = &pll2_sw_clk,
+	 .set_parent = _clk_esdhc1_set_parent,
+	 .get_rate = _clk_esdhc1_get_rate,
+	 .set_rate = _clk_sdhc1_set_rate,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+	 .disable = _clk_disable,
+	 .secondary = &esdhc1_clk[1],
+	 },
+	{
+	__INIT_CLK_DEBUG(esdhc1_clk_1)
+	 .id = 0,
+	 .parent = &ipg_clk,
+	 .secondary = &esdhc1_clk[2],
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(esdhc1_clk_2)
+	 .id = 0,
+	 .parent = &tmax3_clk,
+	 .secondary = &esdhc_dep_clks,
+	 },
+
+};
+
+static unsigned long _clk_esdhc2_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	if (cpu_is_mx51()) {
+		reg = __raw_readl(MXC_CCM_CSCDR1);
+		prediv = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >>
+			MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET) + 1;
+		podf = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >>
+			MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET) + 1;
+
+		return clk_get_rate(clk->parent) / (prediv * podf);
+	}
+	return clk_get_rate(clk->parent);
+}
+
+static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	if (cpu_is_mx51()) {
+		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+			       &lp_apm_clk);
+		reg = __raw_readl(MXC_CCM_CSCMR1) &
+		    ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK;
+		reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET;
+	} else { /* MX53  */
+		reg = __raw_readl(MXC_CCM_CSCMR1);
+		if (parent == &esdhc1_clk[0])
+			reg &= ~MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
+		else if (parent == &esdhc3_clk[0])
+			reg |= MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
+		else
+			BUG();
+	}
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+	return 0;
+}
+
+static int _clk_esdhc2_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg;
+	u32 div;
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	if (cpu_is_mx51()) {
+		div = parent_rate / rate;
+
+		if ((parent_rate / div) != rate)
+			return -EINVAL;
+
+		 __calc_pre_post_dividers(div, &pre, &post);
+
+		/* Set sdhc1 clock divider */
+		reg = __raw_readl(MXC_CCM_CSCDR1) &
+			~(MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK |
+			MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK);
+		reg |= (post - 1) <<
+				MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET;
+		reg |= (pre - 1) <<
+				MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET;
+		__raw_writel(reg, MXC_CCM_CSCDR1);
+	}
+	return 0;
+}
+
+static struct clk esdhc2_clk[] = {
+	{
+	__INIT_CLK_DEBUG(esdhc2_clk_0)
+	 .id = 1,
+	 .parent = &pll3_sw_clk,
+	 .set_parent = _clk_esdhc2_set_parent,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+	 .disable = _clk_disable,
+	 .secondary = &esdhc2_clk[1],
+	 },
+	{
+	__INIT_CLK_DEBUG(esdhc2_clk_1)
+	 .id = 1,
+	 .parent = &ipg_clk,
+	 .secondary = &esdhc2_clk[2],
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(esdhc2_clk_2)
+	 .id = 0,
+	 .parent = &tmax2_clk,
+	 .secondary = &esdhc_dep_clks,
+	 },
+};
+
+static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	if (cpu_is_mx51()) {
+		reg = __raw_readl(MXC_CCM_CSCMR1);
+		if (parent == &esdhc1_clk[0])
+			reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51;
+		else if (parent == &esdhc2_clk[0])
+			reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51;
+		else
+			BUG();
+	} else { /* MX53 */
+		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+			       &lp_apm_clk);
+		reg = __raw_readl(MXC_CCM_CSCMR1) &
+		    ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK;
+		reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET;
+	}
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static unsigned long _clk_esdhc3_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR1);
+	prediv = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK) >>
+		  MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_sdhc3_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg;
+	u32 div;
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	if (cpu_is_mx53()) {
+		div = parent_rate / rate;
+
+		if ((parent_rate / div) != rate)
+			return -EINVAL;
+
+		__calc_pre_post_dividers(div, &pre, &post);
+
+		/* Set sdhc1 clock divider */
+		reg = __raw_readl(MXC_CCM_CSCDR1) &
+			~(MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK |
+			MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK);
+		reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET;
+		reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET;
+		 __raw_writel(reg, MXC_CCM_CSCDR1);
+	}
+	return 0;
+}
+
+
+static struct clk esdhc3_clk[] = {
+	{
+	__INIT_CLK_DEBUG(esdhc3_clk_0)
+	 .id = 2,
+	 .parent = &esdhc1_clk[0],
+	 .set_parent = _clk_esdhc3_set_parent,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+	 .disable = _clk_disable,
+	 .secondary = &esdhc3_clk[1],
+	 },
+	{
+	__INIT_CLK_DEBUG(esdhc3_clk_1)
+	 .id = 2,
+	 .parent = &ipg_clk,
+	 .secondary = &esdhc3_clk[2],
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(esdhc3_clk_2)
+	 .id = 0,
+	 .parent = &ahb_max_clk,
+	 .secondary = &esdhc_dep_clks,
+	 },
+};
+
+static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+	if (cpu_is_mx51()) {
+		reg = __raw_readl(MXC_CCM_CSCMR1);
+		if (parent == &esdhc1_clk[0])
+			reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+		else if (parent == &esdhc2_clk[0])
+			reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+		else
+			BUG();
+	} else {/*MX53 */
+		reg = __raw_readl(MXC_CCM_CSCMR1);
+		if (parent == &esdhc1_clk[0])
+			reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+		else if (parent == &esdhc3_clk[0])
+			reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+		else
+			BUG();
+	}
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk esdhc4_clk[] = {
+	{
+	__INIT_CLK_DEBUG(esdhc4_clk_0)
+	 .id = 3,
+	 .parent = &esdhc1_clk[0],
+	 .set_parent = _clk_esdhc4_set_parent,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+	 .disable = _clk_disable,
+	 .secondary = &esdhc4_clk[1],
+	 },
+	{
+	__INIT_CLK_DEBUG(esdhc4_clk_1)
+	 .id = 3,
+	 .parent = &ipg_clk,
+	 .secondary = &esdhc4_clk[2],
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+	 .disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(esdhc4_clk_2)
+	 .id = 0,
+	 .parent = &tmax3_clk,
+	 .secondary = &esdhc_dep_clks,
+	 },
+};
+
+static struct clk sata_clk = {
+	__INIT_CLK_DEBUG(sata_clk)
+	.parent = &ipg_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk ieee_1588_clk = {
+	__INIT_CLK_DEBUG(ieee_1588_clk)
+	.parent = &ipg_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR7,
+	.enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk mlb_clk[] = {
+	{
+	__INIT_CLK_DEBUG(mlb_clk_0)
+	.parent = &ipg_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR7,
+	.enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+	.disable = _clk_disable,
+	.secondary = &mlb_clk[1],
+	},
+	{
+	__INIT_CLK_DEBUG(mlb_clk_1)
+	.parent = &emi_fast_clk,
+	.secondary = &emi_intr_clk[1],
+	},
+};
+
+static int _can_root_clk_set(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &ipg_clk, &ckih_clk, &ckih2_clk, &lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static struct clk can1_clk[] = {
+	{
+	__INIT_CLK_DEBUG(can1_clk_0)
+	.id = 0,
+	.parent = &lp_apm_clk,
+	.set_parent = _can_root_clk_set,
+	.enable = _clk_enable,
+	.secondary = &can1_clk[1],
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+	.disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(can1_clk_1)
+	.id = 0,
+	.parent = &ipg_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+	.disable = _clk_disable,
+	 },
+};
+
+static struct clk can2_clk[] = {
+	{
+	__INIT_CLK_DEBUG(can2_clk_0)
+	.id = 1,
+	.parent = &lp_apm_clk,
+	.set_parent = _can_root_clk_set,
+	.enable = _clk_enable,
+	.secondary = &can2_clk[1],
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+	.disable = _clk_disable,
+	 },
+	{
+	__INIT_CLK_DEBUG(can2_clk_1)
+	.id = 1,
+	.parent = &ipg_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+	.disable = _clk_disable,
+	 },
+};
+
+static int _clk_sim_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL);
+	reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static unsigned long _clk_sim_get_rate(struct clk *clk)
+{
+	u32 reg, pred, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+	pred = ((reg & MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK) >>
+		MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent) / (pred * podf);
+}
+
+static unsigned long _clk_sim_round_rate(struct clk *clk, unsigned long rate)
+{
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+	u32 div = parent_rate / rate;
+	if (parent_rate % rate)
+		div++;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	return parent_rate / (pre * post);
+}
+
+static int _clk_sim_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg;
+	u32 div;
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if ((parent_rate / div) != rate)
+		return -EINVAL;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	/* Set SIM clock divider */
+	reg = __raw_readl(MXC_CCM_CSCDR2) &
+	    ~(MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK |
+	      MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK);
+	reg |= (post - 1) << MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET;
+	reg |= (pre - 1) << MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR2);
+
+	return 0;
+
+}
+
+static struct clk sim_clk[] = {
+	{
+	__INIT_CLK_DEBUG(sim_clk_0)
+	.parent = &pll3_sw_clk,
+	.set_parent = _clk_sim_set_parent,
+	.secondary = &sim_clk[1],
+	.get_rate = _clk_sim_get_rate,
+	.round_rate = _clk_sim_round_rate,
+	.set_rate = _clk_sim_set_rate,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+	.disable = _clk_disable,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	 },
+	{
+	__INIT_CLK_DEBUG(sim_clk_1)
+	.parent = &ipg_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+	.disable = _clk_disable,
+	 },
+};
+
+static unsigned long _clk_nfc_get_rate(struct clk *clk)
+{
+	u32 reg, div;
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
+	       MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
+	return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long _clk_nfc_round_rate(struct clk *clk,
+						unsigned long rate)
+{
+	u32 div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	/*
+	 * Compute the divider we'd have to use to reach the target rate.
+	 */
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (parent_rate / div > MAX_NFC_CLK)
+		div++;
+
+	/*
+	 * The divider for this clock is 3 bits wide, so we can't possibly
+	 * divide the parent by more than eight.
+	 */
+
+	if (div > 8)
+		return -EINVAL;
+
+	return parent_rate / div;
+
+}
+
+static int _clk_nfc_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (div == 0)
+		div++;
+	if (((parent_rate / div) != rate) || (div > 8))
+		return -EINVAL;
+
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.enable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.enable(&emi_slow_clk);
+
+
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CBCDR);
+	getnstimeofday(&nstimeofday);
+	while (__raw_readl(MXC_CCM_CDHIPR) &
+			MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
+		getnstimeofday(&curtime);
+		if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
+			panic("_clk_nfc_set_rate failed\n");
+	}
+	if (emi_fast_clk.usecount == 0)
+		emi_fast_clk.disable(&emi_fast_clk);
+	if (emi_slow_clk.usecount == 0)
+		emi_slow_clk.disable(&emi_slow_clk);
+
+	return 0;
+}
+
+static struct clk emi_enfc_clk = {
+	__INIT_CLK_DEBUG(emi_enfc_clk)
+	.parent = &emi_slow_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+	.disable = _clk_disable_inwait,
+	.get_rate = _clk_nfc_get_rate,
+	.round_rate = _clk_nfc_round_rate,
+	.set_rate = _clk_nfc_set_rate,
+};
+
+static int _clk_spdif_xtal_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &osc_clk, &ckih_clk, &ckih2_clk, NULL);
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk spdif_xtal_clk = {
+	__INIT_CLK_DEBUG(spdif_xtal_clk)
+	.parent = &osc_clk,
+	.set_parent = _clk_spdif_xtal_set_parent,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	.disable = _clk_disable,
+};
+
+static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+	reg |= MXC_CCM_CSCMR2_SPDIF0_COM;
+	if (parent != &ssi1_clk[0]) {
+		reg &= ~MXC_CCM_CSCMR2_SPDIF0_COM;
+		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+			       &spdif_xtal_clk);
+		reg = (reg & ~MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK) |
+		    (mux << MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET);
+	}
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static unsigned long _clk_spdif0_get_rate(struct clk *clk)
+{
+	u32 reg, pred, podf;
+	u32 div = 1;
+
+	if (clk->parent != &ssi1_clk[0]) {
+		reg = __raw_readl(MXC_CCM_CDCDR);
+		pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK) >>
+			MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
+		podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK) >>
+			MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
+		div = (pred * podf);
+	}
+	return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk spdif0_clk[] = {
+	{
+	__INIT_CLK_DEBUG(spdif0_clk_0)
+	.id = 0,
+	.parent = &pll3_sw_clk,
+	.set_parent = _clk_spdif0_set_parent,
+	.get_rate = _clk_spdif0_get_rate,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+	.disable = _clk_disable,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	},
+	{
+	__INIT_CLK_DEBUG(spdif0_clk_1)
+	 .id = 0,
+	 .parent = &ipg_clk,
+	 .secondary = &spba_clk,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR5,
+	 .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	 .disable = _clk_disable,
+	 },
+};
+
+static int _clk_spdif1_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+	reg |= MXC_CCM_CSCMR2_SPDIF1_COM;
+	if (parent != &ssi2_clk[0]) {
+		reg &= ~MXC_CCM_CSCMR2_SPDIF1_COM;
+		mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+			       &spdif_xtal_clk);
+		reg = (reg & ~MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK) |
+		    (mux << MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET);
+	}
+	__raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static unsigned long _clk_spdif1_get_rate(struct clk *clk)
+{
+	u32 reg, pred, podf;
+	u32 div = 1;
+
+	if (clk->parent != &ssi2_clk[0]) {
+		reg = __raw_readl(MXC_CCM_CDCDR);
+		pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK) >>
+			MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
+		podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK) >>
+			MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
+		div = (pred * podf);
+	}
+	return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk spdif1_clk[] = {
+	{
+	__INIT_CLK_DEBUG(spdif1_clk_0)
+	.id = 1,
+	.parent = &pll3_sw_clk,
+	.set_parent = _clk_spdif1_set_parent,
+	.get_rate = _clk_spdif1_get_rate,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+	.disable = _clk_disable,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	},
+	{
+	__INIT_CLK_DEBUG(spdif1_clk_1)
+	 .id = 0,
+	 .parent = &ipg_clk,
+	 .secondary = &spba_clk,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR5,
+	 .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	 .disable = _clk_disable,
+	 },
+};
+
+static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, reg2, mux;
+	struct timespec nstimeofday;
+	struct timespec curtime;
+
+	reg = __raw_readl(MXC_CCM_CBCMR);
+	reg2 = __raw_readl(MXC_CCM_CBCDR);
+	if (cpu_is_mx51()) {
+		clk->parent = &ddr_hf_clk;
+		mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, &ddr_hf_clk);
+	} else {
+		clk->parent = &axi_a_clk;
+		mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, NULL);
+	}
+	if (mux < 4) {
+		reg = (reg & ~MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) |
+		    (mux << MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET);
+		__raw_writel(reg, MXC_CCM_CBCMR);
+		if (cpu_is_mx51())
+			reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL);
+	} else {
+		reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL) |
+			(MXC_CCM_CBCDR_DDR_HF_SEL);
+	}
+	if (cpu_is_mx51()) {
+		__raw_writel(reg2, MXC_CCM_CBCDR);
+		getnstimeofday(&nstimeofday);
+		while (__raw_readl(MXC_CCM_CDHIPR) &
+			MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY){
+			getnstimeofday(&curtime);
+			if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
+				panic("_clk_ddr_set_parent failed\n");
+		}
+	}
+	return 0;
+}
+
+static struct clk ddr_clk = {
+	__INIT_CLK_DEBUG(ddr_clk)
+	.parent = &axi_b_clk,
+	.set_parent = _clk_ddr_set_parent,
+};
+
+static int _clk_arm_axi_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+	reg = __raw_readl(MXC_CCM_CBCMR);
+	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
+	reg = (reg & ~MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK) |
+	    (mux << MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCMR);
+
+	return 0;
+}
+
+static struct clk arm_axi_clk = {
+	__INIT_CLK_DEBUG(arm_axi_clk)
+	.parent = &axi_a_clk,
+	.set_parent = _clk_arm_axi_set_parent,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR0,
+	.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+	.disable = _clk_disable,
+};
+
+static int _clk_vpu_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+	reg = __raw_readl(MXC_CCM_CBCMR);
+	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
+	reg = (reg & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK) |
+	    (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCMR);
+
+	return 0;
+}
+
+static struct clk vpu_clk[] = {
+	{
+	__INIT_CLK_DEBUG(vpu_clk_0)
+	 .set_parent = _clk_vpu_set_parent,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR5,
+	 .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+	 .disable = _clk_disable,
+	 .secondary = &vpu_clk[1],
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	 },
+	{
+	__INIT_CLK_DEBUG(vpu_clk_1)
+	 .set_parent = _clk_vpu_set_parent,
+	 .enable = _clk_enable,
+	 .enable_reg = MXC_CCM_CCGR5,
+	 .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+	 .disable = _clk_disable,
+	 .secondary = &vpu_clk[2],
+	 },
+	{
+	__INIT_CLK_DEBUG(vpu_clk_2)
+	 .parent = &emi_fast_clk,
+	 }
+};
+
+static int _clk_lpsr_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	mux = _get_mux(parent, &ckil_clk, &osc_clk, NULL, NULL);
+	reg = (reg & ~MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK) |
+	    (mux << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET);
+	__raw_writel(reg, MXC_CCM_CLPCR);
+
+	return 0;
+}
+
+static struct clk lpsr_clk = {
+	__INIT_CLK_DEBUG(lpsr_clk)
+	.parent = &ckil_clk,
+	.set_parent = _clk_lpsr_set_parent,
+};
+
+static unsigned long _clk_pgc_get_rate(struct clk *clk)
+{
+	u32 reg, div;
+
+	reg = __raw_readl(MXC_CCM_CSCDR1);
+	div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >>
+	    MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET;
+	div = 1 >> div;
+	return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk pgc_clk = {
+	__INIT_CLK_DEBUG(pgc_clk)
+	.parent = &ipg_clk,
+	.get_rate = _clk_pgc_get_rate,
+};
+
+static unsigned long _clk_usb_get_rate(struct clk *clk)
+{
+	return 60000000;
+}
+
+/*usb OTG clock */
+static struct clk usb_clk = {
+	__INIT_CLK_DEBUG(usb_clk)
+	.get_rate = _clk_usb_get_rate,
+};
+
+static struct clk usb_utmi_clk = {
+	__INIT_CLK_DEBUG(usb_utmi_clk)
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CSCMR1,
+	.enable_shift = MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk rtc_clk = {
+	__INIT_CLK_DEBUG(rtc_clk)
+	.parent = &ckil_clk,
+	.secondary = &ipg_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk ata_clk = {
+	__INIT_CLK_DEBUG(ata_clk)
+	.parent = &ipg_clk,
+	.secondary = &spba_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+	.disable = _clk_disable,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+};
+
+static struct clk owire_clk = {
+	__INIT_CLK_DEBUG(owire_clk)
+	.parent = &ipg_perclk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR2,
+	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+	.disable = _clk_disable,
+};
+
+
+static struct clk fec_clk[] = {
+	{
+	__INIT_CLK_DEBUG(fec_clk_0)
+	.parent = &ipg_clk,
+	.secondary = &fec_clk[1],
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR2,
+	.enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+	.disable = _clk_disable,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	},
+	{
+	__INIT_CLK_DEBUG(fec_clk_1)
+	 .parent = &tmax2_clk,
+	 .secondary = &fec_clk[2],
+	},
+	{
+	__INIT_CLK_DEBUG(fec_clk_2)
+	 .parent = &aips_tz2_clk,
+	 .secondary = &emi_fast_clk,
+	},
+};
+
+static struct clk sahara_clk[] = {
+	{
+	__INIT_CLK_DEBUG(sahara_clk_0)
+	.parent = &ahb_clk,
+	.secondary = &sahara_clk[1],
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	},
+	{
+	__INIT_CLK_DEBUG(sahara_clk_1)
+	.parent = &tmax1_clk,
+	.secondary = &emi_fast_clk,
+	}
+};
+
+static struct clk scc_clk[] = {
+	{
+	__INIT_CLK_DEBUG(scc_clk_0)
+	.parent = &ahb_clk,
+	.secondary = &scc_clk[1],
+	.enable_reg = MXC_CCM_CCGR1,
+	.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	},
+	{
+	__INIT_CLK_DEBUG(scc_clk_1)
+	.parent = &tmax1_clk,
+	.secondary = &emi_fast_clk,
+	}
+};
+
+
+static int _clk_gpu3d_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CBCMR);
+	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
+	reg = (reg & ~MXC_CCM_CBCMR_GPU_CLK_SEL_MASK) |
+	    (mux << MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCMR);
+
+	return 0;
+}
+
+
+static struct clk garb_clk = {
+	__INIT_CLK_DEBUG(garb_clk)
+	.parent = &axi_a_clk,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk gpu3d_clk = {
+	__INIT_CLK_DEBUG(gpu3d_clk)
+	.parent = &axi_a_clk,
+	.set_parent = _clk_gpu3d_set_parent,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR5,
+	.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+	.disable = _clk_disable,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	.secondary = &garb_clk,
+};
+
+static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	reg = __raw_readl(MXC_CCM_CBCMR);
+	mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
+	reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) |
+	    (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCMR);
+
+	return 0;
+}
+
+static struct clk gpu2d_clk = {
+	__INIT_CLK_DEBUG(gpu2d_clk)
+	.parent = &axi_a_clk,
+	.set_parent = _clk_gpu2d_set_parent,
+	.enable = _clk_enable,
+	.enable_reg = MXC_CCM_CCGR6,
+	.enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+	.disable = _clk_disable,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+};
+
+static unsigned long cko1_get_rate(struct clk *clk)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CCOSR);
+	reg &= MXC_CCM_CCOSR_CKOL_DIV_MASK;
+	reg = reg >> MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
+	return clk_get_rate(clk->parent) / (reg + 1);
+}
+
+static int cko1_enable(struct clk *clk)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CCOSR);
+	reg |= MXC_CCM_CCOSR_CKOL_EN;
+	__raw_writel(reg, MXC_CCM_CCOSR);
+	return 0;
+}
+
+static void cko1_disable(struct clk *clk)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CCOSR);
+	reg &= ~MXC_CCM_CCOSR_CKOL_EN;
+	__raw_writel(reg, MXC_CCM_CCOSR);
+}
+
+static int cko1_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = (parent_rate/rate - 1) & 0x7;
+	reg = __raw_readl(MXC_CCM_CCOSR);
+	reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
+	reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
+	__raw_writel(reg, MXC_CCM_CCOSR);
+	return 0;
+}
+
+static unsigned long cko1_round_rate(struct clk *clk, unsigned long rate)
+{
+	u32 div;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	div = div < 1 ? 1 : div;
+	div = div > 8 ? 8 : div;
+	return parent_rate / div;
+}
+
+static int cko1_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 sel, reg;
+
+	if (parent == &cpu_clk)
+		sel = 0;
+	else if (parent == &pll1_sw_clk)
+		sel = 1;
+	else if (parent == &pll2_sw_clk)
+		sel = 2;
+	else if (parent == &pll3_sw_clk)
+		sel = 3;
+	else if (parent == &emi_slow_clk)
+		sel = 4;
+	else if (parent == &pll4_sw_clk)
+		sel = 5;
+	else if (parent == &emi_enfc_clk)
+		sel = 6;
+	else if (parent == &ipu_di_clk[0])
+		sel = 8;
+	else if (parent == &ahb_clk)
+		sel = 11;
+	else if (parent == &ipg_clk)
+		sel = 12;
+	else if (parent == &ipg_perclk)
+		sel = 13;
+	else if (parent == &ckil_clk)
+		sel = 14;
+	else
+		return -EINVAL;
+
+	reg = __raw_readl(MXC_CCM_CCOSR);
+	reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
+	reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CCOSR);
+	return 0;
+}
+static struct clk cko1_clk = {
+	__INIT_CLK_DEBUG(cko1_clk)
+	.get_rate = cko1_get_rate,
+	.enable = cko1_enable,
+	.disable = cko1_disable,
+	.set_rate = cko1_set_rate,
+	.round_rate = cko1_round_rate,
+	.set_parent = cko1_set_parent,
+};
+static int _clk_asrc_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+
+	reg = __raw_readl(MXC_CCM_CSCMR2);
+	if (parent == &pll4_sw_clk)
+		reg |= MXC_CCM_CSCMR2_ASRC_CLK_SEL;
+	else
+		reg &= ~MXC_CCM_CSCMR2_ASRC_CLK_SEL;
+	 __raw_writel(reg, MXC_CCM_CSCMR2);
+
+	return 0;
+}
+
+static unsigned long _clk_asrc_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+	prediv = ((reg & MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK) >>
+		MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET) + 1;
+	if (prediv == 1)
+		BUG();
+	podf = ((reg & MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET) + 1;
+
+	return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_asrc_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg;
+	u32 div;
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if ((parent_rate / div) != rate)
+		return -EINVAL;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	reg = __raw_readl(MXC_CCM_CSCDR2) &
+		~(MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK |
+		MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK);
+	reg |= (post - 1) << MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET;
+	reg |= (pre - 1) << MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR2);
+
+	return 0;
+}
+
+static unsigned long _clk_asrc_round_rate(struct clk *clk,
+			unsigned long rate)
+{
+	u32 pre, post;
+	u32 parent_rate = clk_get_rate(clk->parent);
+	u32 div = parent_rate / rate;
+
+	if (parent_rate % rate)
+		div++;
+
+	__calc_pre_post_dividers(div, &pre, &post);
+
+	return parent_rate / (pre * post);
+}
+
+static struct clk asrc_clk[] = {
+	{
+	__INIT_CLK_DEBUG(asrc_clk_0)
+	.id = 0,
+	.parent = &pll4_sw_clk,
+	.set_parent = _clk_asrc_set_parent,
+	.get_rate = _clk_asrc_get_rate,
+	.set_rate = _clk_asrc_set_rate,
+	.round_rate = _clk_asrc_round_rate,
+	.enable_reg = MXC_CCM_CCGR7,
+	.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	},
+	{
+	__INIT_CLK_DEBUG(asrc_clk_1)
+	.id = 0,
+	.parent = &ipg_clk,
+	.enable_reg = MXC_CCM_CCGR7,
+	.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+	.enable = _clk_enable,
+	.disable = _clk_disable,
+	},
+};
+
+static struct clk dummy_clk = {
+	.id = 0,
+};
+
+#define _REGISTER_CLOCK(d, n, c) \
+	{ \
+		.dev_id = d, \
+		.con_id = n, \
+		.clk = &c, \
+	}
+
+static struct clk_lookup lookups[] = {
+	_REGISTER_CLOCK(NULL, "osc", osc_clk),
+	_REGISTER_CLOCK(NULL, "ckih", ckih_clk),
+	_REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
+	_REGISTER_CLOCK(NULL, "ckil", ckil_clk),
+	_REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_main_clk),
+	_REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
+	_REGISTER_CLOCK(NULL, "pll2", pll2_sw_clk),
+	_REGISTER_CLOCK(NULL, "pll3", pll3_sw_clk),
+	_REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk),
+	_REGISTER_CLOCK(NULL, "lp_apm", lp_apm_clk),
+	_REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
+	_REGISTER_CLOCK(NULL, "periph_apm_clk", periph_apm_clk),
+	_REGISTER_CLOCK(NULL, "main_bus_clk", main_bus_clk),
+	_REGISTER_CLOCK(NULL, "axi_a_clk", axi_a_clk),
+	_REGISTER_CLOCK(NULL, "axi_b_clk", axi_b_clk),
+	_REGISTER_CLOCK(NULL, "ahb_clk", ahb_clk),
+	_REGISTER_CLOCK(NULL, "ahb_max_clk", ahb_max_clk),
+	_REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
+	_REGISTER_CLOCK(NULL, "vpu_core_clk", vpu_clk[1]),
+	_REGISTER_CLOCK(NULL, "nfc_clk", emi_enfc_clk),
+	_REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk[0]),
+	_REGISTER_CLOCK(NULL, "ipu1_clk", ipu_clk[0]),
+	_REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu_di_clk[0]),
+	_REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu_di_clk[1]),
+	_REGISTER_CLOCK(NULL, "csi_mclk1", csi0_clk),
+	_REGISTER_CLOCK(NULL, "csi_mclk2", csi1_clk),
+	_REGISTER_CLOCK(NULL, "tve_clk", tve_clk),
+	_REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk[0]),
+	_REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk[0]),
+	_REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk[0]),
+	_REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
+	_REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
+	_REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk[0]),
+	_REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk[0]),
+	_REGISTER_CLOCK(NULL, "ssi_lp_apm_clk", ssi_lp_apm_clk),
+	_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk[0]),
+	_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk[0]),
+	_REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk[0]),
+	_REGISTER_CLOCK(NULL, "ssi_ext1_clk", ssi_ext1_clk),
+	_REGISTER_CLOCK(NULL, "ssi_ext2_clk", ssi_ext2_clk),
+	_REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
+	_REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
+	_REGISTER_CLOCK(NULL, "usb_ahb_clk", usb_ahb_clk),
+	_REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy_clk[0]),
+	_REGISTER_CLOCK(NULL, "usb_utmi_clk", usb_utmi_clk),
+	_REGISTER_CLOCK(NULL, "usb_clk", usb_clk),
+	_REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
+	_REGISTER_CLOCK(NULL, "ddr_clk", ddr_clk),
+	_REGISTER_CLOCK(NULL, "emi_enfc_clk", emi_enfc_clk),
+	_REGISTER_CLOCK(NULL, "emi_fast_clk", emi_fast_clk),
+	_REGISTER_CLOCK(NULL, "emi_intr_clk.0", emi_intr_clk[0]),
+	_REGISTER_CLOCK(NULL, "emi_intr_clk.1", emi_intr_clk[1]),
+	_REGISTER_CLOCK(NULL, "spdif_xtal_clk", spdif_xtal_clk),
+	_REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
+	_REGISTER_CLOCK("mxc_vpu.0", NULL, vpu_clk[0]),
+	_REGISTER_CLOCK(NULL, "lpsr_clk", lpsr_clk),
+	_REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk),
+	_REGISTER_CLOCK("pata_fsl", NULL, ata_clk),
+	_REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk),
+	_REGISTER_CLOCK(NULL, "sahara_clk", sahara_clk[0]),
+	_REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_clk),
+	_REGISTER_CLOCK(NULL, "garb_clk", garb_clk),
+	_REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_clk),
+	_REGISTER_CLOCK("mxc_scc.0", NULL, scc_clk[0]),
+	_REGISTER_CLOCK(NULL, "cko1", cko1_clk),
+	_REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
+	_REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk),
+};
+
+static struct clk_lookup mx51_lookups[] = {
+	_REGISTER_CLOCK("mxc_i2c_hs.3", NULL, hsi2c_serial_clk),
+	_REGISTER_CLOCK("mxc_sim.0", NULL, sim_clk[0]),
+	_REGISTER_CLOCK("mxc_spdif.0", NULL, spdif1_clk[0]),
+	_REGISTER_CLOCK(NULL, "mipi_hsp_clk", mipi_hsp_clk),
+	_REGISTER_CLOCK(NULL, "ddr_hf_clk", ddr_hf_clk),
+	_REGISTER_CLOCK("imx51-ecspi.0", NULL, cspi1_clk[0]),
+	_REGISTER_CLOCK("imx51-ecspi.1", NULL, cspi2_clk[0]),
+	_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi3_clk),
+	_REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk[0]),
+	_REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk[0]),
+	_REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk[0]),
+	_REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk[0]),
+	_REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk[0]),
+	_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
+	_REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
+};
+
+static struct clk_lookup mx53_lookups[] = {
+	_REGISTER_CLOCK(NULL, "pll4", pll4_sw_clk),
+	_REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk[0]),
+	_REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk[0]),
+	_REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
+	_REGISTER_CLOCK(NULL, "usb_phy2_clk", usb_phy_clk[1]),
+	_REGISTER_CLOCK(NULL, "ocram_clk", ocram_clk),
+	_REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk),
+	_REGISTER_CLOCK(NULL, "ieee_1588_clk", ieee_1588_clk),
+	_REGISTER_CLOCK(NULL, "ieee_rtc_clk", ieee_rtc_clk),
+	_REGISTER_CLOCK("mxc_mlb.0", NULL, mlb_clk[0]),
+	_REGISTER_CLOCK("FlexCAN.0", "can_clk", can1_clk[0]),
+	_REGISTER_CLOCK("FlexCAN.1", "can_clk", can2_clk[0]),
+	_REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di_clk[0]),
+	_REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di_clk[1]),
+	_REGISTER_CLOCK(NULL, "esai_clk", esai_clk[0]),
+	_REGISTER_CLOCK(NULL, "esai_ipg_clk", esai_clk[1]),
+	_REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[1]),
+	_REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[0]),
+	_REGISTER_CLOCK("imx53-ecspi.0", NULL, cspi1_clk[0]),
+	_REGISTER_CLOCK("imx53-ecspi.1", NULL, cspi2_clk[0]),
+	_REGISTER_CLOCK("imx53-cspi.0", NULL, cspi3_clk),
+	_REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk[0]),
+	_REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_clk[0]),
+	_REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_clk[0]),
+	_REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_clk[0]),
+	_REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk[0]),
+	_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
+	_REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
+};
+
+static void clk_tree_init(void)
+{
+	u32 reg, dp_ctl;
+
+	ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
+
+	/*
+	 *Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
+	 * 8MHz, its derived from lp_apm.
+	 */
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
+	reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
+	reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
+	reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
+	__raw_writel(reg, MXC_CCM_CBCDR);
+
+	/* set pll1_main_clk parent */
+	pll1_main_clk.parent = &osc_clk;
+
+	/* set pll2_sw_clk parent */
+	pll2_sw_clk.parent = &osc_clk;
+
+	/* set pll3_clk parent */
+	pll3_sw_clk.parent = &osc_clk;
+
+	if (cpu_is_mx51()) {
+		dp_ctl = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+		if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
+			pll1_main_clk.parent = &fpm_clk;
+
+		dp_ctl = __raw_readl(pll2_base + MXC_PLL_DP_CTL);
+		if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
+			pll2_sw_clk.parent = &fpm_clk;
+
+		dp_ctl = __raw_readl(pll3_base + MXC_PLL_DP_CTL);
+		if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
+			pll3_sw_clk.parent = &fpm_clk;
+	} else {
+		/* set pll4_clk parent */
+		pll4_sw_clk.parent = &osc_clk;
+	}
+
+	/* set emi_slow_clk parent */
+	emi_slow_clk.parent = &main_bus_clk;
+	reg = __raw_readl(MXC_CCM_CBCDR);
+	if ((reg & MXC_CCM_CBCDR_EMI_CLK_SEL) != 0)
+		emi_slow_clk.parent = &ahb_clk;
+
+	/* set ipg_perclk parent */
+	ipg_perclk.parent = &lp_apm_clk;
+	reg = __raw_readl(MXC_CCM_CBCMR);
+	if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) {
+		ipg_perclk.parent = &ipg_clk;
+	} else {
+		if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0)
+			ipg_perclk.parent = &main_bus_clk;
+	}
+}
+
+
+int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)
+{
+	__iomem void *base;
+	struct clk *tclk;
+	int i = 0, j = 0, reg;
+	int op_cnt = 0;
+	u32 pll1_rate;
+
+	pll1_base = MX51_DPLL1_BASE;
+	pll2_base = MX51_DPLL2_BASE;
+	pll3_base = MX51_DPLL3_BASE;
+
+	/* Turn off all possible clocks */
+	if (mxc_jtag_enabled) {
+		__raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG1_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG2_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG3_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG4_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG8_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG9_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG12_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG13_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0);
+	} else {
+		__raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG1_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG2_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG3_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG8_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG9_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG12_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG13_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0);
+	}
+	__raw_writel(0, MXC_CCM_CCGR1);
+	__raw_writel(0, MXC_CCM_CCGR2);
+	__raw_writel(0, MXC_CCM_CCGR3);
+	__raw_writel(1 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR4);
+
+	__raw_writel(1 << MXC_CCM_CCGRx_CG2_OFFSET |
+		     1 << MXC_CCM_CCGR5_CG6_1_OFFSET |
+		     1 << MXC_CCM_CCGR5_CG6_2_OFFSET |
+		     3 << MXC_CCM_CCGRx_CG7_OFFSET |
+		     1 << MXC_CCM_CCGRx_CG8_OFFSET |
+		     3 << MXC_CCM_CCGRx_CG9_OFFSET |
+		     1 << MXC_CCM_CCGRx_CG10_OFFSET |
+		     3 << MXC_CCM_CCGRx_CG11_OFFSET, MXC_CCM_CCGR5);
+
+	__raw_writel(1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR6);
+
+	external_low_reference = ckil;
+	external_high_reference = ckih1;
+	ckih2_reference = ckih2;
+	oscillator_reference = osc;
+
+	/* Fix up clocks unique to MX51. */
+	esdhc2_clk[0].get_rate = _clk_esdhc2_get_rate;
+	esdhc2_clk[0].set_rate = _clk_esdhc2_set_rate;
+
+	clk_tree_init();
+
+	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+		clkdev_add(&lookups[i]);
+		clk_debug_register(lookups[i].clk);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) {
+		clkdev_add(&mx51_lookups[i]);
+		clk_debug_register(mx51_lookups[i].clk);
+	}
+
+	max_axi_a_clk = MAX_AXI_A_CLK_MX51;
+	max_axi_b_clk = MAX_AXI_B_CLK_MX51;
+	max_ahb_clk = MAX_AHB_CLK_MX51;
+	max_emi_slow_clk = MAX_AHB_CLK_MX51;
+
+	/* set DDR clock parent */
+	reg = 0;
+	if (mx51_revision() >= IMX_CHIP_REVISION_2_0) {
+		reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL;
+		reg >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET;
+
+		if (reg)
+			tclk = &ddr_hf_clk;
+	}
+	if (reg == 0) {
+		reg = __raw_readl(MXC_CCM_CBCMR) &
+					MXC_CCM_CBCMR_DDR_CLK_SEL_MASK;
+		reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+
+		if (reg == 0) {
+			tclk = &axi_a_clk;
+		} else if (reg == 1) {
+			tclk = &axi_b_clk;
+		} else if (reg == 2) {
+			tclk = &emi_slow_clk;
+		} else {
+			tclk = &ahb_clk;
+		}
+	}
+	clk_set_parent(&ddr_clk, tclk);
+
+	/*Setup the LPM bypass bits */
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS
+		| MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
+		| MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS
+		| MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX51
+		| MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+
+	/* Disable the handshake with HSC block as its not
+	  * initialised right now.
+	  */
+	reg = __raw_readl(MXC_CCM_CCDR);
+	reg |= MXC_CCM_CCDR_HSC_HS_MASK;
+	__raw_writel(reg, MXC_CCM_CCDR);
+
+	clk_enable(&cpu_clk);
+
+	/* Set SDHC parents to be PLL2 */
+	clk_set_parent(&esdhc1_clk[0], &pll2_sw_clk);
+	clk_set_parent(&esdhc2_clk[0], &pll2_sw_clk);
+
+	/* set SDHC root clock as 166.25MHZ*/
+	clk_set_rate(&esdhc1_clk[0], 166250000);
+	clk_set_rate(&esdhc2_clk[0], 166250000);
+
+	/* Initialise the parents to be axi_b, parents are set to
+	 * axi_a when the clocks are enabled.
+	 */
+	clk_set_parent(&vpu_clk[0], &axi_a_clk);
+	clk_set_parent(&vpu_clk[1], &axi_a_clk);
+	clk_set_parent(&gpu3d_clk, &axi_a_clk);
+	clk_set_parent(&gpu2d_clk, &axi_a_clk);
+
+	/* move cspi to 24MHz */
+	clk_set_parent(&cspi_main_clk, &lp_apm_clk);
+	clk_set_rate(&cspi_main_clk, 12000000);
+	/*move the spdif0 to spdif_xtal_ckl */
+	clk_set_parent(&spdif0_clk[0], &spdif_xtal_clk);
+	/*set the SPDIF dividers to 1 */
+	reg = __raw_readl(MXC_CCM_CDCDR);
+	reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK;
+	__raw_writel(reg, MXC_CCM_CDCDR);
+
+	/* move the spdif1 to 24MHz */
+	clk_set_parent(&spdif1_clk[0], &spdif_xtal_clk);
+	/* set the spdif1 dividers to 1 */
+	reg = __raw_readl(MXC_CCM_CDCDR);
+	reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK;
+	__raw_writel(reg, MXC_CCM_CDCDR);
+
+	/* Move SSI clocks to SSI_LP_APM clock */
+	clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk);
+
+	clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk);
+	/* set the SSI dividers to divide by 2 */
+	reg = __raw_readl(MXC_CCM_CS1CDR);
+	reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK;
+	reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CS1CDR);
+
+	clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CS2CDR);
+	reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK;
+	reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CS2CDR);
+
+	/*
+	 * SSI3 has no clock divide register,
+	 * we always set SSI3 parent clock to SSI1 and freq same to SSI1
+	 */
+	clk_set_parent(&ssi3_clk[0], &ssi1_clk[0]);
+
+	/* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */
+	clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]);
+	clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]);
+
+	/* move usb_phy_clk to 24MHz */
+	clk_set_parent(&usb_phy_clk[0], &osc_clk);
+
+	/* set usboh3_clk to pll2 */
+	clk_set_parent(&usboh3_clk[0], &pll2_sw_clk);
+	reg = __raw_readl(MXC_CCM_CSCDR1);
+	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
+	reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
+	reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR1);
+
+	mx51_cpu_op_init();
+	/* Set the current working point. */
+	cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+	/* Update the cpu working point table based on the PLL1 freq
+	 * at boot time
+	 */
+	pll1_rate = clk_get_rate(&pll1_main_clk);
+	if (pll1_rate <= cpu_op_tbl[cpu_op_nr - 1].cpu_rate)
+		op_cnt = 1;
+	else if (pll1_rate <= cpu_op_tbl[1].cpu_rate &&
+				pll1_rate > cpu_op_tbl[2].cpu_rate)
+		op_cnt = cpu_op_nr - 1;
+	else
+		op_cnt = cpu_op_nr;
+
+	cpu_op_tbl[0].cpu_rate = pll1_rate;
+
+	if (op_cnt == 1) {
+		cpu_op_tbl[0] = cpu_op_tbl[cpu_op_nr - 1];
+		memset(&cpu_op_tbl[cpu_op_nr - 1], 0, sizeof(struct cpu_op));
+		memset(&cpu_op_tbl[cpu_op_nr - 2], 0, sizeof(struct cpu_op));
+	} else if (op_cnt < cpu_op_nr) {
+		for (i = 0; i < op_cnt; i++)
+			cpu_op_tbl[i] = cpu_op_tbl[i+1];
+		memset(&cpu_op_tbl[i], 0, sizeof(struct cpu_op));
+	}
+
+	if (op_cnt < cpu_op_nr) {
+		set_num_cpu_op(op_cnt);
+		cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+	}
+
+	pll1_rate = clk_get_rate(&pll1_main_clk);
+	for (j = 0; j < cpu_op_nr; j++) {
+		if ((ddr_clk.parent == &ddr_hf_clk)) {
+			/* Change the CPU podf divider based on the boot up
+			 * pll1 rate.
+			 */
+			cpu_op_tbl[j].cpu_podf =
+				(pll1_rate / cpu_op_tbl[j].cpu_rate)
+				- 1;
+			if (pll1_rate / (cpu_op_tbl[j].cpu_podf + 1) >
+					cpu_op_tbl[j].cpu_rate) {
+				cpu_op_tbl[j].cpu_podf++;
+				cpu_op_tbl[j].cpu_rate =
+					 pll1_rate /
+					 (1000 * (cpu_op_tbl[j].cpu_podf + 1));
+				cpu_op_tbl[j].cpu_rate *= 1000;
+			}
+			if (pll1_rate / (cpu_op_tbl[j].cpu_podf + 1) <
+						cpu_op_tbl[j].cpu_rate) {
+				cpu_op_tbl[j].cpu_rate = pll1_rate;
+			}
+		}
+	cpu_op_tbl[j].pll_rate = pll1_rate;
+	}
+	/* Set the current working point. */
+	for (i = 0; i < cpu_op_nr; i++) {
+		if (clk_get_rate(&cpu_clk) == cpu_op_tbl[i].cpu_rate) {
+			cpu_curr_op = i;
+			break;
+		}
+	}
+	if (i > cpu_op_nr)
+		BUG();
+
+	clk_set_parent(&arm_axi_clk, &axi_a_clk);
+	clk_set_parent(&ipu_clk[0], &axi_b_clk);
+
+	if (uart_at_24) {
+		/* Move UART to run from lp_apm */
+		clk_set_parent(&uart_main_clk, &lp_apm_clk);
+
+		/* Set the UART dividers to divide, so the UART_CLK is 24MHz. */
+		reg = __raw_readl(MXC_CCM_CSCDR1);
+		reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
+		reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK;
+		reg |= (0 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) |
+		    (0 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
+		__raw_writel(reg, MXC_CCM_CSCDR1);
+	} else {
+		clk_set_parent(&uart_main_clk, &pll2_sw_clk);
+
+		/* Set the UART dividers to divide, so the UART_CLK is 66.5MHz. */
+		reg = __raw_readl(MXC_CCM_CSCDR1);
+		reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
+		reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK;
+		reg |= (4 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) |
+		    (1 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
+		__raw_writel(reg, MXC_CCM_CSCDR1);
+	}
+
+	clk_set_parent(&emi_slow_clk, &ahb_clk);
+	clk_set_rate(&emi_slow_clk, clk_round_rate(&emi_slow_clk, 130000000));
+
+	/* Change the NFC clock rate to be 1:4 ratio with emi clock. */
+	clk_set_rate(&emi_enfc_clk, clk_round_rate(&emi_enfc_clk,
+			(clk_get_rate(&emi_slow_clk))/4));
+
+	/* System timer */
+	mxc_timer_init(&gpt_clk[0], MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
+		MX51_INT_GPT);
+
+	return 0;
+}
+
+int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)
+{
+	__iomem void *base;
+	struct clk *tclk;
+	int i = 0, j = 0, reg;
+	u32 pll1_rate;
+
+	pll1_base = MX53_DPLL1_BASE;
+	pll2_base = MX53_DPLL2_BASE;
+	pll3_base = MX53_DPLL3_BASE;
+	pll4_base = MX53_DPLL4_BASE;
+
+	/* Turn off all possible clocks */
+	if (mxc_jtag_enabled) {
+		__raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG1_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG2_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG3_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG4_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG8_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG9_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG12_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG13_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0);
+	} else {
+		__raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG1_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG3_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG8_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG9_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG12_OFFSET |
+			      1 << MXC_CCM_CCGRx_CG13_OFFSET |
+			      3 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0);
+	}
+
+	__raw_writel(0, MXC_CCM_CCGR1);
+	__raw_writel(0, MXC_CCM_CCGR2);
+	__raw_writel(0, MXC_CCM_CCGR3);
+	__raw_writel(1 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR4);
+
+	__raw_writel(1 << MXC_CCM_CCGRx_CG2_OFFSET |
+		     1 << MXC_CCM_CCGRx_CG6_OFFSET |
+		     3 << MXC_CCM_CCGRx_CG7_OFFSET |
+		     1 << MXC_CCM_CCGRx_CG8_OFFSET |
+		     1 << MXC_CCM_CCGRx_CG9_OFFSET |
+		     3 << MXC_CCM_CCGRx_CG11_OFFSET, MXC_CCM_CCGR5);
+
+	__raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+				3 << MXC_CCM_CCGRx_CG1_OFFSET |
+				1 << MXC_CCM_CCGRx_CG4_OFFSET |
+				3 << MXC_CCM_CCGRx_CG12_OFFSET |
+				3 << MXC_CCM_CCGRx_CG13_OFFSET , MXC_CCM_CCGR6);
+
+	__raw_writel(0, MXC_CCM_CCGR7);
+
+	external_low_reference = ckil;
+	external_high_reference = ckih1;
+	ckih2_reference = ckih2;
+	oscillator_reference = osc;
+
+	usb_phy_clk[0].enable_reg = MXC_CCM_CCGR4;
+	usb_phy_clk[0].enable_shift = MXC_CCM_CCGRx_CG5_OFFSET;
+
+	ipumux1_clk.enable_reg = MXC_CCM_CCGR5;
+	ipumux1_clk.enable_shift = MXC_CCM_CCGRx_CG6_OFFSET;
+	ipumux2_clk.enable_reg = MXC_CCM_CCGR6;
+	ipumux2_clk.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET;
+
+	esdhc3_clk[0].get_rate = _clk_esdhc3_get_rate;
+	esdhc3_clk[0].set_rate = _clk_sdhc3_set_rate;
+
+	vpu_clk[2].secondary = &emi_intr_clk[0];
+
+#if defined(CONFIG_USB_STATIC_IRAM) \
+    || defined(CONFIG_USB_STATIC_IRAM_PPH)
+	usboh3_clk[1].secondary = &emi_intr_clk[1];
+#endif
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+	ssi2_clk[2].secondary = &emi_intr_clk[1];
+	ssi1_clk[2].secondary = &emi_intr_clk[1];
+#endif
+#ifdef CONFIG_SDMA_IRAM
+	sdma_clk[1].secondary = &emi_intr_clk[1];
+#endif
+
+	clk_tree_init();
+
+	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+		clkdev_add(&lookups[i]);
+		clk_debug_register(lookups[i].clk);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) {
+		clkdev_add(&mx53_lookups[i]);
+		clk_debug_register(mx53_lookups[i].clk);
+	}
+
+	clk_set_parent(&esai_clk[0], &ckih_clk);
+
+	ldb_di_clk[0].parent = ldb_di_clk[1].parent =
+	tve_clk.parent = &pll4_sw_clk;
+
+	max_axi_a_clk = MAX_AXI_A_CLK_MX53;
+	max_axi_b_clk = MAX_AXI_B_CLK_MX53;
+	max_ahb_clk = MAX_AHB_CLK_MX53;
+	max_emi_slow_clk = MAX_AHB_CLK_MX53;
+
+
+	/* set DDR clock parent */
+	reg = __raw_readl(MXC_CCM_CBCMR) &
+				MXC_CCM_CBCMR_DDR_CLK_SEL_MASK;
+	reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+	if (reg == 0) {
+		tclk = &axi_a_clk;
+	} else if (reg == 1) {
+		tclk = &axi_b_clk;
+	} else if (reg == 2) {
+		tclk = &emi_slow_clk;
+	} else {
+		tclk = &ahb_clk;
+	}
+	clk_set_parent(&ddr_clk, tclk);
+
+	clk_set_parent(&esdhc1_clk[2], &tmax2_clk);
+	clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]);
+	clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk);
+
+#if 0
+	/*Setup the LPM bypass bits */
+	reg = __raw_readl(MXC_CCM_CLPCR);
+	reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
+		| MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS
+		| MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS
+		| MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS;
+	__raw_writel(reg, MXC_CCM_CLPCR);
+#endif
+
+	clk_enable(&cpu_clk);
+
+	clk_enable(&main_bus_clk);
+
+	/* Set AXI_B_CLK to be 200MHz */
+	clk_set_rate(&axi_b_clk, 200000000);
+
+	/* Initialise the parents to be axi_b, parents are set to
+	 * axi_a when the clocks are enabled.
+	 */
+
+	clk_set_parent(&vpu_clk[0], &axi_b_clk);
+	clk_set_parent(&vpu_clk[1], &axi_b_clk);
+
+	/* move cspi to 24MHz */
+	clk_set_parent(&cspi_main_clk, &lp_apm_clk);
+	clk_set_rate(&cspi_main_clk, 12000000);
+	/*move the spdif0 to spdif_xtal_ckl */
+	clk_set_parent(&spdif0_clk[0], &spdif_xtal_clk);
+	/*set the SPDIF dividers to 1 */
+	reg = __raw_readl(MXC_CCM_CDCDR);
+	reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK;
+	__raw_writel(reg, MXC_CCM_CDCDR);
+
+	/* Move SSI clocks to SSI_LP_APM clock */
+	clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk);
+
+	clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk);
+	/* set the SSI dividers to divide by 2 */
+	reg = __raw_readl(MXC_CCM_CS1CDR);
+	reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK;
+	reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CS1CDR);
+
+	clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CS2CDR);
+	reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK;
+	reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
+	__raw_writel(reg, MXC_CCM_CS2CDR);
+
+	/* Change the SSI_EXT1_CLK to be sourced from PLL2 for camera */
+	clk_set_parent(&ssi_ext1_clk, &pll2_sw_clk);
+	clk_set_rate(&ssi_ext1_clk, 24000000);
+	clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]);
+
+	/* move usb_phy_clk to 24MHz */
+	clk_set_parent(&usb_phy_clk[0], &osc_clk);
+	clk_set_parent(&usb_phy_clk[1], &osc_clk);
+
+	/* set usboh3_clk to pll2 */
+	clk_set_parent(&usboh3_clk[0], &pll2_sw_clk);
+	reg = __raw_readl(MXC_CCM_CSCDR1);
+	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
+	reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
+	reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR1);
+
+	/* set SDHC root clock as 200MHZ*/
+	clk_set_rate(&esdhc1_clk[0], 200000000);
+	clk_set_rate(&esdhc3_clk[0], 200000000);
+
+	 /* Set the 1588 RTC input clocks as 108MHZ */
+	clk_set_parent(&ieee_rtc_clk, &pll3_sw_clk);
+	clk_set_rate(&ieee_rtc_clk, 108000000);
+
+	/* The CPU working point should be set according to part number
+	 * information. But part number information is not clear now.
+	 * So update the cpu working point table based on the PLL1 freq
+	 * at boot time
+	 */
+	pll1_rate = clk_get_rate(&pll1_main_clk);
+
+	if (pll1_rate > 1000000000)
+		mx53_set_cpu_part_number(IMX53_CEC_1_2G);
+	else if (pll1_rate > 800000000)
+		mx53_set_cpu_part_number(IMX53_CEC);
+	else
+		mx53_set_cpu_part_number(IMX53_AEC);
+
+	/* Set the current working point. */
+	cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+	for (i = 0; i < cpu_op_nr; i++) {
+		if (clk_get_rate(&cpu_clk) == cpu_op_tbl[i].cpu_rate) {
+			cpu_curr_op = i;
+			break;
+		}
+	}
+	if (i > cpu_op_nr)
+		BUG();
+
+	clk_set_parent(&arm_axi_clk, &axi_b_clk);
+	clk_set_parent(&ipu_clk[0], &axi_b_clk);
+	clk_set_parent(&gpu3d_clk, &axi_b_clk);
+	clk_set_parent(&gpu2d_clk, &axi_b_clk);
+
+	clk_set_parent(&emi_slow_clk, &ahb_clk);
+	clk_set_rate(&emi_slow_clk, clk_round_rate(&emi_slow_clk, 133333333));
+
+	clk_set_rate(&emi_enfc_clk, clk_round_rate(&emi_enfc_clk,
+			MAX_NFC_CLK));
+
+	/* set the freq of asrc_serial_clk */
+	clk_set_rate(&asrc_clk[0], clk_round_rate(&asrc_clk[0],
+			1190000));
+	clk_set_parent(&uart_main_clk, &pll2_sw_clk);
+	/* System timer */
+	mxc_timer_init(&gpt_clk[0], MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
+		MX53_INT_GPT);
+	return 0;
+}
+
+/*!
+ * Setup cpu clock based on working point.
+ * @param	op	cpu freq working point
+ * @return		0 on success or error code on failure.
+ */
+static int cpu_clk_set_op(int op)
+{
+	struct cpu_op *p;
+	u32 reg, pll_hfsm;
+	u32 stat;
+	int relock_timeout = 10;
+
+	if (op == cpu_curr_op)
+		return 0;
+
+	p = &cpu_op_tbl[op];
+
+	/*
+	 * If DDR clock is sourced from PLL1, we cannot drop PLL1 freq.
+	 * Use the ARM_PODF to change the freq of the core, leave the PLL1
+	 * freq unchanged. Meanwhile, if pll_rate is same, use the ARM_PODF
+	 * to change the freq of core
+	 */
+	if ((ddr_clk.parent == &ddr_hf_clk) ||
+		(p->pll_rate == cpu_op_tbl[cpu_curr_op].pll_rate)) {
+		reg = __raw_readl(MXC_CCM_CACRR);
+		reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
+		reg |= cpu_op_tbl[op].cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
+		__raw_writel(reg, MXC_CCM_CACRR);
+		cpu_curr_op = op;
+	} else {
+		struct timespec nstimeofday;
+		struct timespec curtime;
+
+		/* Change the ARM clock to requested frequency */
+		/* First move the ARM clock to step clock which is running
+		 * at 24MHz.
+		 */
+
+		/* Change the source of pll1_sw_clk to be the step_clk */
+		reg = __raw_readl(MXC_CCM_CCSR);
+		reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+		__raw_writel(reg, MXC_CCM_CCSR);
+
+		/* Stop the PLL */
+		reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+		reg &= ~MXC_PLL_DP_CTL_UPEN;
+		__raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
+
+		reg = __raw_readl(MXC_CCM_CACRR);
+		reg = (reg & ~MXC_CCM_CACRR_ARM_PODF_MASK)
+			| p->cpu_podf;
+		__raw_writel(reg, MXC_CCM_CACRR);
+
+		reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+		pll_hfsm = reg & MXC_PLL_DP_CTL_HFSM;
+		/* PDF and MFI */
+		reg = p->pdf | p->mfi << MXC_PLL_DP_OP_MFI_OFFSET;
+		if (pll_hfsm == 0) {
+			__raw_writel(reg, pll1_base + MXC_PLL_DP_OP);
+			__raw_writel(p->mfd, pll1_base + MXC_PLL_DP_MFD);
+			__raw_writel(p->mfn, pll1_base + MXC_PLL_DP_MFN);
+		} else {
+			__raw_writel(reg, pll1_base + MXC_PLL_DP_HFS_OP);
+			__raw_writel(p->mfd, pll1_base + MXC_PLL_DP_HFS_MFD);
+			__raw_writel(p->mfn, pll1_base + MXC_PLL_DP_HFS_MFN);
+		}
+
+		reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+		reg |= MXC_PLL_DP_CTL_UPEN;
+		/* Set the UPEN bits */
+		__raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
+		/* Forcefully restart the PLL */
+		reg |= MXC_PLL_DP_CTL_RST;
+		__raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
+
+		/* Wait for the PLL to lock */
+		do {
+			stat = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+			if (stat & MXC_PLL_DP_CTL_LRF)
+				break;
+			udelay(100);
+		} while (--relock_timeout);
+
+		reg = __raw_readl(MXC_CCM_CCSR);
+		/* Move the PLL1 back to the pll1_main_clk */
+		reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+		__raw_writel(reg, MXC_CCM_CCSR);
+
+		cpu_curr_op = op;
+	}
+
+#if defined(CONFIG_CPU_FREQ)
+	cpufreq_trig_needed = 1;
+#endif
+	return 0;
+}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 5e2e7a84386..9d2bddcee09 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -14,12 +14,32 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 #include <linux/module.h>
 #include <mach/hardware.h>
 #include <linux/io.h>
+#include <mach/iram.h>
 
 static int mx5_cpu_rev = -1;
 
+#define CORTEXA8_PLAT_AMC       0x18
+#define SRPG_NEON_PUPSCR        0x284
+#define SRPG_NEON_PDNSCR        0x288
+#define SRPG_ARM_PUPSCR         0x2A4
+#define SRPG_ARM_PDNSCR         0x2A8
+#define SRPG_EMPGC0_PUPSCR      0x2E4
+#define SRPG_EMPGC0_PDNSCR      0x2E8
+#define SRPG_EMPGC1_PUPSCR      0x304
+#define SRPG_EMPGC1_PDNSCR      0x308
+
+void __iomem *arm_plat_base;
+void __iomem *gpc_base;
+void __iomem *ccm_base;
+extern void init_ddr_settings(void);
+
+static int cpu_silicon_rev = -1;
+void (*set_num_cpu_op)(int num);
+
 #define IIM_SREV 0x24
 #define MX50_HW_ADADIG_DIGPROG	0xB0
 
@@ -111,6 +131,7 @@ int mx53_revision(void)
 	return mx5_cpu_rev;
 }
 EXPORT_SYMBOL(mx53_revision);
+#define MX50_HW_ADADIG_DIGPROG	0xB0
 
 static int get_mx50_srev(void)
 {
@@ -154,6 +175,24 @@ static int __init post_cpu_init(void)
 {
 	unsigned int reg;
 	void __iomem *base;
+	struct clk *gpcclk = clk_get(NULL, "gpc_dvfs_clk");
+
+	if (cpu_is_mx51()) {
+		ccm_base = MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR);
+		gpc_base = MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR);
+		arm_plat_base = MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR);
+		iram_init(MX51_IRAM_BASE_ADDR, MX51_IRAM_SIZE);
+	} else if (cpu_is_mx53()) {
+		ccm_base = MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR);
+		gpc_base = MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR);
+		arm_plat_base = MX53_IO_ADDRESS(MX53_ARM_BASE_ADDR);
+		iram_init(MX53_IRAM_BASE_ADDR, MX53_IRAM_SIZE);
+	} else {
+		ccm_base = MX50_IO_ADDRESS(MX50_CCM_BASE_ADDR);
+		gpc_base = MX50_IO_ADDRESS(MX50_GPC_BASE_ADDR);
+		arm_plat_base = MX50_IO_ADDRESS(MX50_ARM_BASE_ADDR);
+		iram_init(MX50_IRAM_BASE_ADDR, MX50_IRAM_SIZE);
+	}
 
 	if (cpu_is_mx51() || cpu_is_mx53()) {
 		if (cpu_is_mx51())
@@ -180,6 +219,30 @@ static int __init post_cpu_init(void)
 		reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
 		__raw_writel(reg, base + 0x50);
 	}
+	clk_enable(gpcclk);
+
+	/* Setup the number of clock cycles to wait for SRPG
+	* power up and power down requests.
+	*/
+	__raw_writel(0x010F0201, gpc_base + SRPG_ARM_PUPSCR);
+	__raw_writel(0x010F0201, gpc_base + SRPG_NEON_PUPSCR);
+	__raw_writel(0x00000008, gpc_base + SRPG_EMPGC0_PUPSCR);
+	__raw_writel(0x00000008, gpc_base + SRPG_EMPGC1_PUPSCR);
+
+	__raw_writel(0x01010101, gpc_base + SRPG_ARM_PDNSCR);
+	__raw_writel(0x01010101, gpc_base + SRPG_NEON_PDNSCR);
+	__raw_writel(0x00000018, gpc_base + SRPG_EMPGC0_PDNSCR);
+	__raw_writel(0x00000018, gpc_base + SRPG_EMPGC1_PDNSCR);
+
+	clk_disable(gpcclk);
+	clk_put(gpcclk);
+
+	/* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */
+	reg = 0x8;
+	__raw_writel(reg, arm_plat_base + CORTEXA8_PLAT_AMC);
+
+	if (cpu_is_mx50())
+		init_ddr_settings();
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-mx5/cpu_op-mx51.c
index 9d34c3d4c02..c721a47a0db 100644
--- a/arch/arm/mach-mx5/cpu_op-mx51.c
+++ b/arch/arm/mach-mx5/cpu_op-mx51.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -15,15 +15,55 @@
 #include <mach/hardware.h>
 #include <linux/kernel.h>
 
+extern struct cpu_op *(*get_cpu_op)(int *op);
+extern void (*set_num_cpu_op)(int num);
+static int num_cpu_op;
+
+/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
 static struct cpu_op mx51_cpu_op[] = {
 	{
-	.cpu_rate = 160000000,},
+	 .pll_rate = 1000000000,
+	 .cpu_rate = 1000000000,
+	 .pdf = 0,
+	 .mfi = 10,
+	 .mfd = 11,
+	 .mfn = 5,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1175000,},
+	{
+	 .pll_rate = 800000000,
+	 .cpu_rate = 800000000,
+	 .pdf = 0,
+	 .mfi = 8,
+	 .mfd = 2,
+	 .mfn = 1,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1100000,
+	},
 	{
-	.cpu_rate = 800000000,},
+	 .pll_rate = 800000000,
+	 .cpu_rate = 166250000,
+	 .cpu_podf = 4,
+	 .cpu_voltage = 850000,
+	},
 };
 
 struct cpu_op *mx51_get_cpu_op(int *op)
 {
-	*op = ARRAY_SIZE(mx51_cpu_op);
+	*op = num_cpu_op;
 	return mx51_cpu_op;
 }
+
+void mx51_set_num_cpu_op(int num)
+{
+	num_cpu_op = num;
+	return;
+}
+
+void mx51_cpu_op_init()
+{
+	get_cpu_op = mx51_get_cpu_op;
+	set_num_cpu_op = mx51_set_num_cpu_op;
+
+	num_cpu_op = ARRAY_SIZE(mx51_cpu_op);
+}
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-mx5/cpu_op-mx51.h
index 97477fecb46..03564bd3712 100644
--- a/arch/arm/mach-mx5/cpu_op-mx51.h
+++ b/arch/arm/mach-mx5/cpu_op-mx51.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -11,4 +11,5 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-extern struct cpu_op *mx51_get_cpu_op(int *op);
+struct cpu_op *mx51_get_cpu_op(int *op);
+extern void mx51_cpu_op_init(void);
diff --git a/arch/arm/mach-mx5/cpu_op-mx53.c b/arch/arm/mach-mx5/cpu_op-mx53.c
new file mode 100644
index 00000000000..a0d0700548f
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu_op-mx53.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <mach/hardware.h>
+#include "cpu_op-mx53.h"
+
+/*!
+ * @file mach-mx5/cpu_op-mx53.c
+ *
+ * @brief This file contains the information about MX53 CPU working points.
+ *
+ * @ingroup MSL_MX53
+ */
+extern struct cpu_op *(*get_cpu_op)(int *op);
+extern void (*set_num_cpu_op)(int num);
+static int num_cpu_op;
+static struct cpu_op *cpu_op_table;
+
+/* working point for auto*/
+static struct cpu_op cpu_op_aec[] = {
+	{
+	 .pll_rate = 800000000,
+	 .cpu_rate = 800000000,
+	 .pdf = 0,
+	 .mfi = 8,
+	 .mfd = 2,
+	 .mfn = 1,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1050000,},
+};
+
+/* working point for consumer 1G*/
+static struct cpu_op cpu_op_ces[] = {
+	{
+	 .pll_rate = 1000000000,
+	 .cpu_rate = 1000000000,
+	 .pdf = 0,
+	 .mfi = 10,
+	 .mfd = 11,
+	 .mfn = 5,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1200000,},
+	{
+	 .pll_rate = 800000000,
+	 .cpu_rate = 800000000,
+	 .pdf = 0,
+	 .mfi = 8,
+	 .mfd = 2,
+	 .mfn = 1,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1050000,},
+	 {
+	  .pll_rate = 800000000,
+	  .cpu_rate = 400000000,
+	  .cpu_podf = 1,
+	  .cpu_voltage = 950000,},
+	{
+	 .pll_rate = 800000000,
+	 .cpu_rate = 160000000,
+	 .cpu_podf = 4,
+	 .cpu_voltage = 900000,},
+};
+
+/* working point for consumer 1.2G*/
+static struct cpu_op cpu_op_ces_1_2g[] = {
+	{
+	 .pll_rate = 1200000000,
+	 .cpu_rate = 1200000000,
+	 .pdf = 0,
+	 .mfi = 12,
+	 .mfd = 1,
+	 .mfn = 1,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1300000,},
+	{
+	 .pll_rate = 1000000000,
+	 .cpu_rate = 1000000000,
+	 .pdf = 0,
+	 .mfi = 10,
+	 .mfd = 11,
+	 .mfn = 5,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1200000,},
+	{
+	 .pll_rate = 800000000,
+	 .cpu_rate = 800000000,
+	 .pdf = 0,
+	 .mfi = 8,
+	 .mfd = 2,
+	 .mfn = 1,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1050000,},
+	 {
+	  .pll_rate = 800000000,
+	  .cpu_rate = 400000000,
+	  .cpu_podf = 1,
+	  .cpu_voltage = 950000,},
+	{
+	 .pll_rate = 800000000,
+	 .cpu_rate = 160000000,
+	 .cpu_podf = 4,
+	 .cpu_voltage = 900000,},
+};
+
+
+struct cpu_op *mx53_get_cpu_op(int *op)
+{
+	*op = num_cpu_op;
+	return cpu_op_table;
+}
+
+void mx53_set_num_cpu_op(int num)
+{
+	num_cpu_op = num;
+	return;
+}
+
+void mx53_set_cpu_part_number(enum mx53_cpu_part_number part_num)
+{
+	get_cpu_op = mx53_get_cpu_op;
+	set_num_cpu_op = mx53_set_num_cpu_op;
+
+	switch (part_num) {
+	case IMX53_CEC_1_2G:
+		cpu_op_table = cpu_op_ces_1_2g;
+		num_cpu_op = ARRAY_SIZE(cpu_op_ces_1_2g);
+		break;
+	case IMX53_CEC:
+		cpu_op_table = cpu_op_ces;
+		num_cpu_op = ARRAY_SIZE(cpu_op_ces);
+		break;
+	case IMX53_AEC:
+	default:
+		cpu_op_table = cpu_op_aec;
+		num_cpu_op = ARRAY_SIZE(cpu_op_aec);
+		break;
+	}
+}
+
+
diff --git a/arch/arm/mach-mx5/cpu_op-mx53.h b/arch/arm/mach-mx5/cpu_op-mx53.h
new file mode 100644
index 00000000000..5bd8f4fd73c
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu_op-mx53.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX53_WP_H__
+#define  __ARCH_ARM_MACH_MX53_WP_H__
+#include <linux/types.h>
+
+/*!
+ * @file mach-mx5/cpu_op-mx53.h
+ *
+ * @brief This file contains the information about MX53 CPU working points.
+ *
+ * @ingroup MSL_MX53
+ */
+enum mx53_cpu_part_number {
+  IMX53_AEC,  /* automative and infotainment AP */
+  IMX53_CEC,  /* Consumer AP, CPU freq is up to 1G */
+  IMX53_CEC_1_2G, /* Consumer AP, CPU freq is up to 1.2GHZ */
+};
+
+void mx53_set_cpu_part_number(enum mx53_cpu_part_number part_num);
+
+#endif /*__ARCH_ARM_MACH_MX53_WP_H__ */
+
+
+
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index 5e11ba7daee..b28737fb263 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -11,19 +11,21 @@
 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
 
-#define MX51_CCM_BASE		MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
+#define MXC_CCM_BASE	MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
+
 #define MX51_DPLL1_BASE		MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
 #define MX51_DPLL2_BASE		MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
 #define MX51_DPLL3_BASE		MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
-#define MX51_CORTEXA8_BASE	MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
-#define MX51_GPC_BASE		MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
 
-/*MX53*/
-#define MX53_CCM_BASE		MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
 #define MX53_DPLL1_BASE		MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
 #define MX53_DPLL2_BASE		MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
 #define MX53_DPLL3_BASE		MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-#define MX53_DPLL4_BASE		MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+#define MX53_DPLL4_BASE		MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
+
+#define MX50_DPLL1_BASE		MX50_IO_ADDRESS(MX50_PLL1_BASE_ADDR)
+#define MX50_DPLL2_BASE		MX50_IO_ADDRESS(MX50_PLL2_BASE_ADDR)
+#define MX50_DPLL3_BASE		MX50_IO_ADDRESS(MX50_PLL3_BASE_ADDR)
+#define MX50_ANATOP_BASE		MX50_IO_ADDRESS(MX50_ANATOP_BASE_ADDR)
 
 /* PLL Register Offsets */
 #define MXC_PLL_DP_CTL			0x00
@@ -80,43 +82,108 @@
 #define MXC_PLL_DP_DESTAT_TOG_SEL	(1 << 31)
 #define MXC_PLL_DP_DESTAT_MFN		0x07FFFFFF
 
+/* Register addresses of apll and pfd*/
+#define MXC_ANADIG_FRAC0		0x10
+#define MXC_ANADIG_FRAC0_SET		0x14
+#define MXC_ANADIG_FRAC0_CLR		0x18
+#define MXC_ANADIG_FRAC1		0x20
+#define MXC_ANADIG_FRAC1_SET		0x24
+#define MXC_ANADIG_FRAC1_CLR		0x28
+#define MXC_ANADIG_MISC			0x60
+#define MXC_ANADIG_MISC_SET		0x64
+#define MXC_ANADIG_MISC_CLR		0x68
+#define MXC_ANADIG_PLLCTRL		0x70
+#define MXC_ANADIG_PLLCTRL_SET		0x74
+#define MXC_ANADIG_PLLCTRL_CLR		0x78
+
+/* apll and pfd Register Bit definitions */
+
+#define MXC_ANADIG_PFD3_CLKGATE		(1 << 31)
+#define MXC_ANADIG_PFD3_STABLE		(1 << 30)
+#define MXC_ANADIG_PFD3_FRAC_OFFSET	24
+#define MXC_ANADIG_PFD_FRAC_MASK	0x3F
+#define MXC_ANADIG_PFD2_CLKGATE		(1 << 23)
+#define MXC_ANADIG_PFD2_STABLE		(1 << 22)
+#define MXC_ANADIG_PFD2_FRAC_OFFSET	16
+#define MXC_ANADIG_PFD1_CLKGATE		(1 << 15)
+#define MXC_ANADIG_PFD1_STABLE		(1 << 14)
+#define MXC_ANADIG_PFD1_FRAC_OFFSET	8
+#define MXC_ANADIG_PFD0_CLKGATE		(1 << 7)
+#define MXC_ANADIG_PFD0_STABLE		(1 << 6)
+#define MXC_ANADIG_PFD0_FRAC_OFFSET	0
+
+#define MXC_ANADIG_PFD7_CLKGATE		(1 << 31)
+#define MXC_ANADIG_PFD7_STABLE		(1 << 30)
+#define MXC_ANADIG_PFD7_FRAC_OFFSET	24
+#define MXC_ANADIG_PFD6_CLKGATE		(1 << 23)
+#define MXC_ANADIG_PFD6_STABLE		(1 << 22)
+#define MXC_ANADIG_PFD6_FRAC_OFFSET	16
+#define MXC_ANADIG_PFD5_CLKGATE		(1 << 15)
+#define MXC_ANADIG_PFD5_STABLE		(1 << 14)
+#define MXC_ANADIG_PFD5_FRAC_OFFSET	8
+#define MXC_ANADIG_PFD4_CLKGATE		(1 << 7)
+#define MXC_ANADIG_PFD4_STABLE		(1 << 6)
+#define MXC_ANADIG_PFD4_FRAC_OFFSET	0
+
+#define MXC_ANADIG_APLL_LOCK		(1 << 31)
+#define MXC_ANADIG_APLL_FORCE_LOCK	(1 << 30)
+#define MXC_ANADIG_PFD_DIS_OFFSET	16
+#define MXC_ANADIG_PFD_DIS_MASK		0xff
+#define MXC_ANADIG_APLL_LOCK_CNT_OFFSET	0
+#define MXC_ANADIG_APLL_LOCK_CNT_MASK	0xffff
+
 /* Register addresses of CCM*/
-#define MXC_CCM_CCR		(MX51_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR		(MX51_CCM_BASE + 0x04)
-#define MXC_CCM_CSR		(MX51_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR		(MX51_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR		(MX51_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR		(MX51_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR		(MX51_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1		(MX51_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2		(MX51_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1		(MX51_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR		(MX51_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR		(MX51_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR		(MX51_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR		(MX51_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2		(MX51_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3		(MX51_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4		(MX51_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR		(MX51_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR		(MX51_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR		(MX51_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR		(MX51_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR		(MX51_CCM_BASE + 0x54)
-#define MXC_CCM_CISR		(MX51_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR		(MX51_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR		(MX51_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR		(MX51_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0		(MX51_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1		(MX51_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2		(MX51_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3		(MX51_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4		(MX51_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5		(MX51_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6		(MX51_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7		(MX51_CCM_BASE + 0x84)
-
-#define MXC_CCM_CMEOR		(MX51_CCM_BASE + 0x84)
+#define MXC_CCM_CCR		(MXC_CCM_BASE + 0x00)
+#define MXC_CCM_CCDR		(MXC_CCM_BASE + 0x04)
+#define MXC_CCM_CSR		(MXC_CCM_BASE + 0x08)
+#define MXC_CCM_CCSR		(MXC_CCM_BASE + 0x0C)
+#define MXC_CCM_CACRR		(MXC_CCM_BASE + 0x10)
+#define MXC_CCM_CBCDR		(MXC_CCM_BASE + 0x14)
+#define MXC_CCM_CBCMR		(MXC_CCM_BASE + 0x18)
+#define MXC_CCM_CSCMR1		(MXC_CCM_BASE + 0x1C)
+#define MXC_CCM_CSCMR2		(MXC_CCM_BASE + 0x20)
+#define MXC_CCM_CSCDR1		(MXC_CCM_BASE + 0x24)
+#define MXC_CCM_CS1CDR		(MXC_CCM_BASE + 0x28)
+#define MXC_CCM_CS2CDR		(MXC_CCM_BASE + 0x2C)
+#define MXC_CCM_CDCDR		(MXC_CCM_BASE + 0x30)
+#define MXC_CCM_CHSCDR		(MXC_CCM_BASE + 0x34)
+#define MXC_CCM_CSCDR2		(MXC_CCM_BASE + 0x38)
+#define MXC_CCM_CSCDR3		(MXC_CCM_BASE + 0x3C)
+#define MXC_CCM_CSCDR4		(MXC_CCM_BASE + 0x40)
+#define MXC_CCM_CWDR		(MXC_CCM_BASE + 0x44)
+#define MXC_CCM_CDHIPR		(MXC_CCM_BASE + 0x48)
+#define MXC_CCM_CDCR		(MXC_CCM_BASE + 0x4C)
+#define MXC_CCM_CTOR		(MXC_CCM_BASE + 0x50)
+#define MXC_CCM_CLPCR		(MXC_CCM_BASE + 0x54)
+#define MXC_CCM_CISR		(MXC_CCM_BASE + 0x58)
+#define MXC_CCM_CIMR		(MXC_CCM_BASE + 0x5C)
+#define MXC_CCM_CCOSR		(MXC_CCM_BASE + 0x60)
+#define MXC_CCM_CGPR		(MXC_CCM_BASE + 0x64)
+#define MXC_CCM_CCGR0		(MXC_CCM_BASE + 0x68)
+#define MXC_CCM_CCGR1		(MXC_CCM_BASE + 0x6C)
+#define MXC_CCM_CCGR2		(MXC_CCM_BASE + 0x70)
+#define MXC_CCM_CCGR3		(MXC_CCM_BASE + 0x74)
+#define MXC_CCM_CCGR4		(MXC_CCM_BASE + 0x78)
+#define MXC_CCM_CCGR5		(MXC_CCM_BASE + 0x7C)
+#define MXC_CCM_CCGR6		(MXC_CCM_BASE + 0x80)
+#define MXC_CCM_CCGR7		(MXC_CCM_BASE + 0x84)
+#define MXC_CCM_CMEOR		(MXC_CCM_BASE + 0x88)
+#define MXC_CCM_CSR2		(MXC_CCM_BASE + 0x8C)
+#define MXC_CCM_CLKSEQ_BYPASS	(MXC_CCM_BASE + 0x90)
+#define MXC_CCM_CLK_SYS		(MXC_CCM_BASE + 0x94)
+#define MXC_CCM_CLK_DDR		(MXC_CCM_BASE + 0x98)
+#define MXC_CCM_ELCDIFPIX	(MXC_CCM_BASE + 0x9C)
+#define MXC_CCM_EPDCPIX		(MXC_CCM_BASE + 0xA0)
+#define MXC_CCM_DISPLAY_AXI	(MXC_CCM_BASE + 0xA4)
+#define MXC_CCM_EPDC_AXI	(MXC_CCM_BASE + 0xA8)
+#define MXC_CCM_GPMI		(MXC_CCM_BASE + 0xAC)
+#define MXC_CCM_BCH		(MXC_CCM_BASE + 0xB0)
+#define MXC_CCM_MSHC_XMSCKI	(MXC_CCM_BASE + 0xB4)
+
+/* CCM Register Offsets. */
+#define MXC_CCM_CDCR_OFFSET		0x4C
+#define MXC_CCM_CACRR_OFFSET		0x10
+#define MXC_CCM_CDHIPR_OFFSET	0x48
 
 /* Define the bits in register CCR */
 #define MXC_CCM_CCR_COSC_EN		(1 << 12)
@@ -128,82 +195,103 @@
 #define MXC_CCM_CCR_OSCNT_MASK	(0xFF)
 
 /* Define the bits in register CCDR */
+/* MX51 */
 #define MXC_CCM_CCDR_HSC_HS_MASK	(0x1 << 18)
 #define MXC_CCM_CCDR_IPU_HS_MASK	(0x1 << 17)
 #define MXC_CCM_CCDR_EMI_HS_MASK	(0x1 << 16)
+/* MX53 */
+#define MXC_CCM_CCDR_IPU_HS_MX53_MASK	(0x1 << 21)
+#define MXC_CCM_CCDR_EMI_HS_INT2_MASK	(0x1 << 20)
+#define MXC_CCM_CCDR_EMI_HS_INT1_MASK	(0x1 << 19)
+#define MXC_CCM_CCDR_EMI_HS_SLOW_MASK	(0x1 << 18)
+#define MXC_CCM_CCDR_EMI_HS_FAST_MASK	(0x1 << 17)
+#define MXC_CCM_CCDR_EMI_HS_MASK	(0x1 << 16)
 
 /* Define the bits in register CSR */
 #define MXC_CCM_CSR_COSR_READY	(1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE	(1 << 4)
+#define MXC_CCM_CSR_LVS_VALUE		(1 << 4)
 #define MXC_CCM_CSR_CAMP2_READY	(1 << 3)
 #define MXC_CCM_CSR_CAMP1_READY	(1 << 2)
 #define MXC_CCM_CSR_FPM_READY	(1 << 1)
-#define MXC_CCM_CSR_REF_EN_B	(1 << 0)
+#define MXC_CCM_CSR_TEMP_MON_ALARM	(1 << 1)
+#define MXC_CCM_CSR_REF_EN_B		(1 << 0)
 
 /* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL		(0x1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET	(7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK	(0x3 << 7)
+#define MXC_CCM_CCSR_PLL3_PFD_EN		(0x1 << 13)
+#define MXC_CCM_CCSR_PLL2_PFD_EN		(0x1 << 12)
+#define MXC_CCM_CCSR_PLL1_PFD_EN		(0x1 << 11)
+#define MXC_CCM_CCSR_LP_APM_SEL			(0x1 << 10)
+#define MXC_CCM_CCSR_LP_APM_SE_MX51L		(0x1 << 9)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL		(1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET		(7)
+#define MXC_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
 #define MXC_CCM_CCSR_STEP_SEL_LP_APM	   0
 #define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
 #define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
 #define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
 #define MXC_CCM_CCSR_PLL2_PODF_OFFSET	(5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK	(0x3 << 5)
+#define MXC_CCM_CCSR_PLL2_PODF_MASK		(0x3 << 5)
 #define MXC_CCM_CCSR_PLL3_PODF_OFFSET	(3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK	(0x3 << 3)
+#define MXC_CCM_CCSR_PLL3_PODF_MASK		(0x3 << 3)
 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL	(1 << 2) /* 0: pll1_main_clk,
 						    1: step_clk */
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL	(1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL	(1 << 0)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL		(1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL		(1 << 0)
 
 /* Define the bits in register CACRR */
 #define MXC_CCM_CACRR_ARM_PODF_OFFSET	(0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK	(0x7)
+#define MXC_CCM_CACRR_ARM_PODF_MASK		(0x7)
 
 /* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
+#define MX50_CCM_CBCDR_WEIM_CLK_SEL		(0x1 << 27)
+#define MXC_CCM_CBCDR_EMI_CLK_SEL			(0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL			(0x1 << 25)
+#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET	(25)
+#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK	(0x3 << 25)
 #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET		(30)
-#define MXC_CCM_CBCDR_DDR_HF_SEL		(0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_HF_SEL			(0x1 << 30)
 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET		(27)
 #define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MX50_CCM_CBCDR_WEIM_PODF_OFFSET	(22)
+#define MX50_CCM_CBCDR_WEIM_PODF_MASK		(0x7 << 22)
 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		(22)
-#define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
+#define MXC_CCM_CBCDR_EMI_PODF_MASK			(0x7 << 22)
 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		(19)
 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		(16)
 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET		(13)
-#define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
+#define MXC_CCM_CBCDR_NFC_PODF_MASK			(0x7 << 13)
 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET		(10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK			(0x7 << 10)
 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET		(8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	(6)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK			(0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET		(6)
 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	(3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET		(3)
 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	(0)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET		(0)
 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK		(0x7)
 
 /* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET		(16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK		(0x3 << 16)
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET	(14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK	(0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET	(12)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK	(0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET	(10)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		(12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		(10)
 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK		(0x3 << 10)
 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET	(8)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK	(0x3 << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET	(6)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK	(0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET	(4)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		(4)
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK		(0x3 << 4)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET	(14)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK	(0x3 << 14)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL	(0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL	(0x1 << 0)
+#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_OFFSET	(2)
+#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_MASK	(0x3 << 2)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
 
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		(30)
@@ -212,103 +300,128 @@
 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		(26)
 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		(24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET			(24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK			(0x3 << 24)
 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		(22)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	(20)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL	(0x1 << 19)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK			(0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET	(20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK		(0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51		(0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL			(0x1 << 19)
 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	(16)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET	(16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK		(0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		(14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		(12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
+#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET	(21)
+#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK	(0x3 << 21)
+#define MX50_CCM_CSCMR1_ESDHC2_CLK_SEL			(0x1 << 20)
+#define MX50_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 19)
+#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET	(16)
+#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK		(0x7 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET	(16)
+#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK		(0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET			(14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK			(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET			(12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK			(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL				(0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL				(0x1 << 10)
 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		(8)
 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL				(0x1 << 7)
 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		(4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		(2)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		(0x1)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET			(4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK			(0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET			(2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK			(0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL			(0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL			(0x1)
 
 /* Define the bits in register CSCMR2 */
 #define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)		(26+n*3)
 #define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n)		(0x7 << (26+n*3))
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET		(24)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK		(0x3 << 24)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET		(22)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK		(0x3 << 22)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET	(24)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK	(0x3 << 24)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET	(22)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK	(0x3 << 22)
+/* MX51 */
 #define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET		(20)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK			(0x3 << 20)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK		(0x3 << 20)
 #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET		(18)
 #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK		(0x3 << 18)
 #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET		(16)
 #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK		(0x3 << 16)
 #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET		(14)
 #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK		(0x3 << 14)
+/* MX53 */
+#define MXC_CCM_CSCMR2_ASRC_CLK_SEL				(1<<21)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		(19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK		(0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET	(16)
+#define MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK		(0x7 << 16)
+#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET		(14)
+#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK		(0x3 << 14)
 #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET		(12)
 #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK		(0x3 << 12)
+/* MX51 */
 #define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET		(10)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK			(0x3 << 10)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK		(0x3 << 10)
 #define MXC_CCM_CSCMR2_SLIMBUS_COM			(0x1 << 9)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET		(6)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET	(6)
 #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK		(0x7 << 6)
+/* MX53 */
+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(0x1 << 11)
+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(0x1 << 10)
+#define MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL			(0x1 << 9)
+#define MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL			(0x1 << 8)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		(6)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK		(0x3 << 6)
 #define MXC_CCM_CSCMR2_SPDIF1_COM			(1 << 5)
 #define MXC_CCM_CSCMR2_SPDIF0_COM			(1 << 4)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET		(2)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET	(2)
 #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK		(0x3 << 2)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET		(0)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET	(0)
 #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK		(0x3)
 
 /* Define the bits in register CSCDR1 */
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	(22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK		(0x7 << 22)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	(19)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET	(22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK	(0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET	(19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK	(0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	(16)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		(14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	(11)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET	(22)
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK		(0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET	(19)
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET	(16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK	(0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET			(14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK			(0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET	(11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK	(0x7 << 11)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		(8)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		(6)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		(3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK			(0x7 << 3)
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		(0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		(0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK			(0x7)
 
 /* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET		(22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK		(0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET		(16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK		(0x3F << 16)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET	(25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET	(22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK	(0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET	(16)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK	(0x3F << 16)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET		(9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK	(0x7 << 9)
 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		(6)
 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		(0)
 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK		(0x3F)
 
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET		(22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK		(0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET		(16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK		(0x3F << 16)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET	(22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK	(0x7 << 22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET	(16)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK	(0x3F << 16)
 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		(6)
 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		(0)
@@ -316,50 +429,74 @@
 
 /* Define the bits in register CDCDR */
 #define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET		(28)
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK			(0x7 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET		(25)
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK		(0x7 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET	(25)
 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET		(19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET	(19)
 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x3F << 19)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET		(16)
+/* MX51 */
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET	(16)
 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		(9)
+/* MX53 */
+#define MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET		(16)
+#define MXC_CCM_CDCDR_DI_PLL4_PODF_MASK			(0x7 << 16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET	(9)
 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x3F << 9)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET		(6)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK			(0x7 << 6)
+#define MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET		(6)
+#define MXC_CCM_CDCDR_DI1_CLK_PRED_MASK		(0x7 << 6)
 #define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET		(3)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK			(0x7 << 3)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK		(0x7 << 3)
 #define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET		(0)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK			(0x7)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK		(0x7)
 
 /* Define the bits in register CHSCCDR */
+/* MX51 */
 #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET		(12)
 #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK		(0x7 << 12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET		(6)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET	(6)
 #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK		(0x3F << 6)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET		(3)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET	(3)
 #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK		(0x7 << 3)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET		(0)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET	(0)
 #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK		(0x7)
+/* MX53 */
+#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_OFFSET		(6)
+#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_MASK			(0x3 << 6)
+#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_OFFSET		(4)
+#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_MASK			(0x3 << 4)
+#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_OFFSET		(2)
+#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_MASK		(0x3 << 2)
+#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_OFFSET		(0)
+#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_MASK		(0x3)
 
 /* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET	(28)
+#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK		(0x7 << 28)
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		(25)
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		(19)
 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
+/* MX51 */
 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		(16)
 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		(9)
 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		(6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET	(6)
 #define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
 #define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		(0)
 #define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK		(0x3F)
+/* MX53 */
+#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET	(9)
+#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK		(0x3F << 9)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET		(6)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET	(0)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK		(0x3F)
 
 /* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET		(16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET	(16)
 #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK		(0x7 << 16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET		(9)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET	(9)
 #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK		(0x3F << 9)
 #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET		(6)
 #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK		(0x7 << 6)
@@ -368,13 +505,13 @@
 
 /* Define the bits in register CSCDR4 */
 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET	(16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK	(0x7 << 16)
 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET	(9)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK		(0x3F << 9)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK	(0x3F << 9)
 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET	(6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK	(0x7 << 6)
 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET	(0)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK		(0x3F)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK	(0x3F)
 
 /* Define the bits in register CDHIPR */
 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
@@ -389,59 +526,92 @@
 #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY			(1 << 0)
 
 /* Define the bits in register CDCR */
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER		(0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET	(0)
+#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ_STATUS	(0x1 << 7)
+#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ		(0x1 << 6)
+#define MX50_CCM_CDCR_SW_DVFS_EN				(0x1 << 5)
+#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER			(0x1 << 2)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET		(0)
 #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK		(0x3)
 
 /* Define the bits in register CLPCR */
+/* MX51 */
 #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS		(0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS		(0x1 << 22)
-#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS		(0x1 << 21)
-#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS		(0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS	(0x1 << 20)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX51		(0x1 << 22)
+#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51		(0x1 << 21)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51		(0x1 << 20)
+/* MX53 */
+#define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS			(0x1 << 27)
+#define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS			(0x1 << 27)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX53			(0x1 << 26)
+#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS			(0x1 << 25)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS			(0x1 << 24)
+#define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS		(0x1 << 23)
+#define MX50_CCM_CLPCR_BYPASS_RNGB_LPM_HS		(0x1 << 23)
+#define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS		(0x1 << 22)
+#define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS		(0x1 << 21)
+#define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS		(0x1 << 20)
 #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS		(0x1 << 19)
 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS		(0x1 << 18)
-#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS	(0x1 << 17)
-#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS	(0x1 << 16)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
+#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS		(0x1 << 17)
+#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS		(0x1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN			(0x1 << 11)
 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET		(9)
 #define MXC_CCM_CLPCR_STBY_COUNT_MASK		(0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY			(0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC		(0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS			(0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET	(3)
+#define MXC_CCM_CLPCR_VSTBY				(0x1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC			(0x1 << 7)
+#define MXC_CCM_CLPCR_SBYOS				(0x1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM		(0x1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET		(3)
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK		(0x3 << 3)
-#define MXC_CCM_CLPCR_LPM_OFFSET		(0)
+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY		(0x1 << 2)
+#define MXC_CCM_CLPCR_LPM_OFFSET			(0)
 #define MXC_CCM_CLPCR_LPM_MASK			(0x3)
 
 /* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED			(0x1 << 25)
-#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
+#define MXC_CCM_CISR_ARM_PODF_LOADED_MX51		(0x1 << 25)
+#define MXC_CCM_CISR_ARM_PODF_LOADED		(0x1 << 26)
+#define MXC_CCM_CISR_TEMP_MON_ALARM				(0x1 << 25)
+#define MXC_CCM_CISR_EMI_CLK_SEL_LOADED			(0x1 << 23)
+#define MXC_CCM_CISR_PER_CLK_SEL_LOADED			(0x1 << 22)
+#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED		(0x1 << 21)
 #define MXC_CCM_CISR_AHB_PODF_LOADED			(0x1 << 20)
-#define MXC_CCM_CISR_EMI_PODF_LOADED			(0x1 << 19)
+#define MXC_CCM_CISR_EMI_PODF_LOADED				(0x1 << 19)
 #define MXC_CCM_CISR_AXI_B_PODF_LOADED			(0x1 << 18)
 #define MXC_CCM_CISR_AXI_A_PODF_LOADED			(0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED			(0x1 << 16)
+#define MXC_CCM_CISR_DIVIDER_LOADED				(0x1 << 16)
 #define MXC_CCM_CISR_COSC_READY				(0x1 << 6)
-#define MXC_CCM_CISR_CKIH2_READY			(0x1 << 5)
+#define MXC_CCM_CISR_CKIH2_READY				(0x1 << 5)
 #define MXC_CCM_CISR_CKIH_READY				(0x1 << 4)
+#define MX50_CCM_CISR_CAMP1_READY			(0x1 << 4)
 #define MXC_CCM_CISR_FPM_READY				(0x1 << 3)
-#define MXC_CCM_CISR_LRF_PLL3				(0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2				(0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1				(0x1)
+#define MXC_CCM_CISR_LRF_PLL3					(0x1 << 2)
+#define MXC_CCM_CISR_LRF_PLL2					(0x1 << 1)
+#define MXC_CCM_CISR_LRF_PLL1					(0x1)
 
 /* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(0x1 << 25)
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED_MX51		(0x1 << 25)
+#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED_MX51		(0x1 << 20)
+#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED_MX51	(0x1 << 19)
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(0x1 << 26)
+#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM		(0x1 << 25)
+#define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED		(0x1 << 23)
+#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED		(0x1 << 22)
 #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
-#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED		(0x1 << 20)
-#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED		(0x1 << 19)
+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED_MX53		(0x1 << 20)
+#define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED_MX53		(0x1 << 19)
+#define MX50_CCM_CIMR_MASK_WEIM_PODF_LOADED		(0x1 << 19)
 #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED		(0x1 << 18)
 #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED		(0x1 << 17)
 #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED		(0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY			(0x1 << 5)
+/* MX51 */
+#define MXC_CCM_CIMR_MASK_COSC_READY_MX51			(0x1 << 5)
 #define MXC_CCM_CIMR_MASK_CKIH_READY			(0x1 << 4)
 #define MXC_CCM_CIMR_MASK_FPM_READY			(0x1 << 3)
+/* MX53/MX50 */
+#define MXC_CCM_CIMR_MASK_COSC_READY			(0x1 << 6)
+#define MXC_CCM_CIMR_MASK_CAMP2_READY			(0x1 << 5)
+#define MXC_CCM_CIMR_MASK_CAMP1_READY			(0x1 << 4)
+#define MXC_CCM_CIMR_MASK_LRF_PLL4			(0x1 << 3)
 #define MXC_CCM_CIMR_MASK_LRF_PLL3			(0x1 << 2)
 #define MXC_CCM_CIMR_MASK_LRF_PLL2			(0x1 << 1)
 #define MXC_CCM_CIMR_MASK_LRF_PLL1			(0x1)
@@ -459,11 +629,20 @@
 #define MXC_CCM_CCOSR_CKOL_SEL_MASK			(0xF)
 
 /* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_ARM_CLK_INPUT_SEL				(0x1 << 24)
+#define MXC_CCM_CGPR_ARM_ASYNC_REF_EN				(0x1 << 23)
 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(0x1 << 4)
 #define MXC_CCM_CGPR_FPM_SEL				(0x1 << 3)
 #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET		(0)
 #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK		(0x7)
 
+#define MX50_CCM_CCOSR_CKO1_SLOW_SEL			(0x1 << 8)
+#define MX50_CCM_CCOSR_CKO1_EN				(0x1 << 7)
+#define MX50_CCM_CCOSR_CKO1_DIV_OFFSET			(4)
+#define MX50_CCM_CCOSR_CKO1_DIV_MASK			(0x7 << 4)
+#define MX50_CCM_CCOSR_CKO1_SEL_OFFSET			(0)
+#define MX50_CCM_CCOSR_CKO1_SEL_MASK			(0xF)
+
 /* Define the bits in registers CCGRx */
 #define MXC_CCM_CCGRx_CG_MASK				0x3
 #define MXC_CCM_CCGRx_MOD_OFF				0x0
@@ -502,30 +681,120 @@
 #define MXC_CCM_CCGRx_CG1_OFFSET			2
 #define MXC_CCM_CCGRx_CG0_OFFSET			0
 
-#define MXC_DPTC_LP_BASE	(MX51_GPC_BASE + 0x80)
-#define MXC_DPTC_GP_BASE	(MX51_GPC_BASE + 0x100)
-#define MXC_DVFS_CORE_BASE	(MX51_GPC_BASE + 0x180)
-#define MXC_DPTC_PER_BASE	(MX51_GPC_BASE + 0x1C0)
-#define MXC_PGC_IPU_BASE	(MX51_GPC_BASE + 0x220)
-#define MXC_PGC_VPU_BASE	(MX51_GPC_BASE + 0x240)
-#define MXC_PGC_GPU_BASE	(MX51_GPC_BASE + 0x260)
-#define MXC_SRPG_NEON_BASE	(MX51_GPC_BASE + 0x280)
-#define MXC_SRPG_ARM_BASE	(MX51_GPC_BASE + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE	(MX51_GPC_BASE + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE	(MX51_GPC_BASE + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE	(MX51_GPC_BASE + 0x2E0)
-#define MXC_SRPG_EMI_BASE	(MX51_GPC_BASE + 0x300)
+#define MXC_CCM_CCGR5_CG6_1_OFFSET			12
+#define MXC_CCM_CCGR5_CG6_2_OFFSET			13
+
+/* Define the bits in registers CSR2  */
+#define MXC_CCM_CSR2_ELCDIF_PIX_BUSY			(0x1 << 9)
+#define MXC_CCM_CSR2_EPDC_PIX_BUSY			(0x1 << 8)
+#define MXC_CCM_CSR2_EPDC_AXI_BUSY			(0x1 << 4)
+#define MXC_CCM_CSR2_DISPLAY_AXI_BUSY			(0x1 << 3)
+
+/* Define the bits in registers CLKSEQ_BYPASS  */
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_OFFSET	14
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_MASK	(0x3 << 14)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_OFFSET	12
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_MASK	(0x3 << 12)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_OFFSET	6
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_MASK		(0x3 << 6)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_OFFSET		8
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_OFFSET	4
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_MASK	(0x3 << 4)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_OFFSET	2
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_MASK	(0x3 << 2)
+
+/* Define the bits in registers CLK_SYS */
+#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET	(30)
+#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK	(0x3 << 30)
+#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET		(28)
+#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK	(0x3 << 28)
+#define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET			(6)
+#define MXC_CCM_CLK_SYS_DIV_XTAL_MASK			(0xF << 6)
+#define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET			(0)
+#define MXC_CCM_CLK_SYS_DIV_PLL_MASK				(0x3F)
+
+/* Define the bits in registers CLK_DDR */
+#define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET	(30)
+#define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK	(0x3 << 30)
+#define MXC_CCM_CLK_DDR_DDR_PFD_SEL		(1 << 6)
+#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET	(0)
+#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK	(0x3F)
+
+/* Define the bits in register DISPLAY_AXI */
+#define MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET	(30)
+#define MXC_CCM_DISPLAY_AXI_CLKGATE_MASK	(0x3 << 30)
+#define MXC_CCM_DISPLAY_AXI_PXP_ASM_EN		(1 << 13)
+#define MXC_CCM_DISPLAY_AXI_PXP_ASM_DIV_MASK	(0x7 << 10)
+#define MXC_CCM_DISPLAY_AXI_PXP_ASM_DIV_OFFSET	10
+#define MXC_CCM_DISPLAY_AXI_DIV_OFFSET		(0)
+#define MXC_CCM_DISPLAY_AXI_DIV_MASK		(0x3F)
+
+/* Define the bits in register EPDC_AXI */
+#define MXC_CCM_EPDC_AXI_CLKGATE_OFFSET	(30)
+#define MXC_CCM_EPDC_AXI_CLKGATE_MASK	(0x3 << 30)
+#define MXC_CCM_EPDC_AXI_ASM_EN			(1 << 9)
+#define MXC_CCM_EPDC_AXI_ASM_DIV_OFFSET		(6)
+#define MXC_CCM_EPDC_AXI_ASM_DIV_MASK		(0x7 << 6)
+#define MXC_CCM_EPDC_AXI_DIV_OFFSET		(0)
+#define MXC_CCM_EPDC_AXI_DIV_MASK		(0x3F)
+
+/* Define the bits in register EPDCPIX */
+#define MXC_CCM_EPDC_PIX_CLKGATE_OFFSET		(30)
+#define MXC_CCM_EPDC_PIX_CLKGATE_MASK		(0x3 << 30)
+#define MXC_CCM_EPDC_PIX_CLK_PRED_OFFSET	(12)
+#define MXC_CCM_EPDC_PIX_CLK_PRED_MASK		(0x3 << 12)
+#define MXC_CCM_EPDC_PIX_CLK_PODF_OFFSET	(0)
+#define MXC_CCM_EPDC_PIX_CLK_PODF_MASK		(0xFFF)
+
+/* Define the bits in register ELCDIFPIX */
+#define MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET	(30)
+#define MXC_CCM_ELCDIFPIX_CLKGATE_MASK		(0x3 << 30)
+#define MXC_CCM_ELCDIFPIX_CLK_PRED_OFFSET	(12)
+#define MXC_CCM_ELCDIFPIX_CLK_PRED_MASK		(0x3 << 12)
+#define MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET	(0)
+#define MXC_CCM_ELCDIFPIX_CLK_PODF_MASK		(0xFFF)
+
+
+/* Define the bits in register GPMI */
+#define MXC_CCM_GPMI_CLKGATE_OFFSET		(30)
+#define MXC_CCM_GPMI_CLKGATE_MASK		(0x3 << 30)
+#define MXC_CCM_GPMI_CLK_DIV_OFFSET		(0)
+#define MXC_CCM_GPMI_CLK_DIV_MASK		(0x3F)
+
+/* Define the bits in register BCH */
+#define MXC_CCM_BCH_CLKGATE_OFFSET		(30)
+#define MXC_CCM_BCH_CLKGATE_MASK		(0x3 << 30)
+#define MXC_CCM_BCH_CLK_DIV_OFFSET		(0)
+#define MXC_CCM_BCH_CLK_DIV_MASK		(0x3F)
+
+#define MXC_GPC_BASE		(MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR))
+#define MXC_DPTC_LP_BASE	(MXC_GPC_BASE + 0x80)
+#define MXC_DPTC_GP_BASE	(MXC_GPC_BASE + 0x100)
+#define MXC_DVFS_CORE_BASE	(MXC_GPC_BASE + 0x180)
+#define MXC_DVFS_PER_BASE	(MXC_GPC_BASE + 0x1C4)
+#define MXC_PGC_IPU_BASE	(MXC_GPC_BASE + 0x220)
+#define MXC_PGC_VPU_BASE	(MXC_GPC_BASE + 0x240)
+#define MXC_PGC_GPU_BASE	(MXC_GPC_BASE + 0x260)
+#define MXC_SRPG_NEON_BASE	(MXC_GPC_BASE + 0x280)
+#define MXC_SRPG_ARM_BASE	(MXC_GPC_BASE + 0x2A0)
+#define MXC_SRPG_EMPGC0_BASE	(MXC_GPC_BASE + 0x2C0)
+#define MXC_SRPG_EMPGC1_BASE	(MXC_GPC_BASE + 0x2D0)
+#define MXC_SRPG_MEGAMIX_BASE	(MXC_GPC_BASE + 0x2E0)
+#define MXC_SRPG_EMI_BASE	(MXC_GPC_BASE + 0x300)
 
 /* CORTEXA8 platform */
-#define MXC_CORTEXA8_PLAT_PVID		(MX51_CORTEXA8_BASE + 0x0)
-#define MXC_CORTEXA8_PLAT_GPC		(MX51_CORTEXA8_BASE + 0x4)
-#define MXC_CORTEXA8_PLAT_PIC		(MX51_CORTEXA8_BASE + 0x8)
-#define MXC_CORTEXA8_PLAT_LPC		(MX51_CORTEXA8_BASE + 0xC)
-#define MXC_CORTEXA8_PLAT_NEON_LPC	(MX51_CORTEXA8_BASE + 0x10)
-#define MXC_CORTEXA8_PLAT_ICGC		(MX51_CORTEXA8_BASE + 0x14)
-#define MXC_CORTEXA8_PLAT_AMC		(MX51_CORTEXA8_BASE + 0x18)
-#define MXC_CORTEXA8_PLAT_NMC		(MX51_CORTEXA8_BASE + 0x20)
-#define MXC_CORTEXA8_PLAT_NMS		(MX51_CORTEXA8_BASE + 0x24)
+extern void __iomem *arm_plat_base;
+#define MXC_CORTEXA8_BASE		(arm_plat_base)
+#define MXC_CORTEXA8_PLAT_PVID		(arm_plat_base + 0x0)
+#define MXC_CORTEXA8_PLAT_GPC		(arm_plat_base + 0x4)
+#define MXC_CORTEXA8_PLAT_PIC		(arm_plat_base + 0x8)
+#define MXC_CORTEXA8_PLAT_LPC		(arm_plat_base + 0xC)
+#define MXC_CORTEXA8_PLAT_NEON_LPC	(arm_plat_base + 0x10)
+#define MXC_CORTEXA8_PLAT_ICGC		(arm_plat_base + 0x14)
+#define MXC_CORTEXA8_PLAT_AMC		(arm_plat_base + 0x18)
+#define MXC_CORTEXA8_PLAT_NMC		(arm_plat_base + 0x20)
+#define MXC_CORTEXA8_PLAT_NMS		(arm_plat_base + 0x24)
 
 /* DVFS CORE */
 #define MXC_DVFSTHRS		(MXC_DVFS_CORE_BASE + 0x00)
@@ -546,28 +815,23 @@
 #define MXC_DVFSPT2 		(MXC_DVFS_CORE_BASE + 0x3C)
 #define MXC_DVFSPT3 		(MXC_DVFS_CORE_BASE + 0x40)
 
-/* GPC */
-#define MXC_GPC_CNTR		(MX51_GPC_BASE + 0x0)
-#define MXC_GPC_PGR		(MX51_GPC_BASE + 0x4)
-#define MXC_GPC_VCR		(MX51_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU		(MX51_GPC_BASE + 0xC)
-#define MXC_GPC_NEON		(MX51_GPC_BASE + 0x10)
-#define MXC_GPC_PGR_ARMPG_OFFSET	8
-#define MXC_GPC_PGR_ARMPG_MASK		(3 << 8)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR	(MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR	(MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR	(MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR	(MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR	(MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR	(MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR		1
-#define MXC_SRPGCR_PCR		1
-#define MXC_EMPGCR_PCR		1
-#define MXC_PGSR_PSR		1
+/* DVFS PER */
+#define MXC_DVFSPER_LTR0	(MXC_DVFS_PER_BASE)
+#define MXC_DVFSPER_LTR1	(MXC_DVFS_PER_BASE + 0x04)
+#define MXC_DVFSPER_LTR2	(MXC_DVFS_PER_BASE + 0x08)
+#define MXC_DVFSPER_LTR3	(MXC_DVFS_PER_BASE + 0x0C)
+#define MXC_DVFSPER_LTBR0	(MXC_DVFS_PER_BASE + 0x10)
+#define MXC_DVFSPER_LTBR1	(MXC_DVFS_PER_BASE + 0x14)
+#define MXC_DVFSPER_PMCR0	(MXC_DVFS_PER_BASE + 0x18)
+#define MXC_DVFSPER_PMCR1	(MXC_DVFS_PER_BASE + 0x1C)
 
+/* GPC */
+#define MXC_GPC_CNTR				(MXC_GPC_BASE  + 0x0)
+#define MXC_GPC_PGR				(MXC_GPC_BASE  + 0x4)
+#define MXC_GPC_VCR				(MXC_GPC_BASE  + 0x8)
+#define MXC_GPC_CNTR_OFFSET		0x0
+#define MXC_GPC_PGR_OFFSET		0x4
+#define MXC_GPC_VCR_OFFSET		0x8
 
 #define MXC_CORTEXA8_PLAT_LPC_DSM	(1 << 0)
 #define MXC_CORTEXA8_PLAT_LPC_DBG_DSM	(1 << 1)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index af488bc0e22..b7a941aa905 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -69,3 +69,23 @@ extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
 extern const struct imx_pata_imx_data imx51_pata_imx_data;
 #define imx51_add_pata_imx() \
 	imx_add_pata_imx(&imx51_pata_imx_data)
+
+extern const struct imx_ipuv3_data imx51_ipuv3_data __initconst;
+#define imx51_add_ipuv3(id, pdata)	imx_add_ipuv3(id, &imx51_ipuv3_data, pdata)
+#define imx51_add_ipuv3fb(id, pdata)	imx_add_ipuv3_fb(id, pdata)
+
+extern const struct imx_tve_data imx51_tve_data __initconst;
+#define imx51_add_tve(pdata)	\
+	imx_add_tve(&imx51_tve_data, pdata)
+
+#define imx51_add_v4l2_output(id)	\
+	platform_device_register_resndata(NULL, "mxc_v4l2_output",\
+			id, NULL, 0, NULL, 0);
+
+extern const struct imx_spdif_data imx51_imx_spdif_data __initconst;
+#define imx51_add_spdif(pdata)	imx_add_spdif(&imx51_imx_spdif_data, pdata)
+
+extern const struct imx_spdif_dai_data imx51_spdif_dai_data __initconst;
+#define imx51_add_spdif_dai()	imx_add_spdif_dai(&imx51_spdif_dai_data)
+
+#define imx51_add_spdif_audio_device(pdata)	imx_add_spdif_audio_device()
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 6e1e5d1f8c3..8d15ee5e35c 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -29,6 +29,10 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[];
 #define imx53_add_ecspi(id, pdata)	\
 	imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
 
+extern const struct imx_mxc_gpu_data imx53_gpu_data __initconst;
+#define imx53_add_mxc_gpu(pdata) \
+	imx_add_mxc_gpu(&imx53_gpu_data, pdata)
+
 extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
 #define imx53_add_imx2_wdt(id, pdata)	\
 	imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
@@ -37,6 +41,14 @@ extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
 #define imx53_add_imx_ssi(id, pdata)	\
 	imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
 
+extern const struct imx_spdif_data imx53_imx_spdif_data __initconst;
+#define imx53_add_spdif(pdata)	imx_add_spdif(&imx53_imx_spdif_data, pdata)
+
+extern const struct imx_spdif_dai_data imx53_spdif_dai_data __initconst;
+#define imx53_add_spdif_dai()	imx_add_spdif_dai(&imx53_spdif_dai_data)
+
+#define imx53_add_spdif_audio_device(pdata)	imx_add_spdif_audio_device()
+
 extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
 #define imx53_add_imx_keypad(pdata)	\
 	imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
@@ -46,3 +58,42 @@ extern const struct imx_pata_imx_data imx53_pata_imx_data;
 	imx_add_pata_imx(&imx53_pata_imx_data)
 
 extern struct platform_device *__init imx53_add_ahci_imx(void);
+
+extern const struct imx_srtc_data imx53_imx_srtc_data __initconst;
+#define imx53_add_srtc()	\
+	imx_add_srtc(&imx53_imx_srtc_data)
+
+extern const struct imx_iim_data imx53_imx_iim_data __initconst;
+#define imx53_add_iim(pdata) \
+	imx_add_iim(&imx53_imx_iim_data, pdata)
+
+extern const struct imx_ipuv3_data imx53_ipuv3_data __initconst;
+#define imx53_add_ipuv3(id, pdata)	imx_add_ipuv3(id, &imx53_ipuv3_data, pdata)
+#define imx53_add_ipuv3fb(id, pdata)	imx_add_ipuv3_fb(id, pdata)
+
+extern const struct imx_tve_data imx53_tve_data __initconst;
+#define imx53_add_tve(pdata)	\
+	imx_add_tve(&imx53_tve_data, pdata)
+
+extern const struct imx_ldb_data imx53_ldb_data __initconst;
+#define imx53_add_ldb(pdata) \
+	imx_add_ldb(&imx53_ldb_data, pdata);
+
+extern const struct imx_mxc_pwm_data imx53_mxc_pwm_data[] __initconst;
+#define imx53_add_mxc_pwm(id)	\
+	imx_add_mxc_pwm(&imx53_mxc_pwm_data[id])
+
+#define imx53_add_lcdif(pdata)	\
+	platform_device_register_resndata(NULL, "mxc_lcdif",\
+			0, NULL, 0, pdata, sizeof(*pdata));
+
+#define imx53_add_mxc_pwm_backlight(id, pdata)			\
+	platform_device_register_resndata(NULL, "pwm-backlight",\
+			id, NULL, 0, pdata, sizeof(*pdata));
+
+#define imx53_add_v4l2_output(id)	\
+	platform_device_register_resndata(NULL, "mxc_v4l2_output",\
+			id, NULL, 0, NULL, 0);
+
+extern const struct imx_vpu_data imx53_vpu_data __initconst;
+#define imx53_add_vpu()	imx_add_vpu(&imx53_vpu_data)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
new file mode 100644
index 00000000000..d579ce49f64
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/irqs.h>
+
+static struct resource mxc_hsi2c_resources[] = {
+	{
+		.start = MX51_HSI2C_DMA_BASE_ADDR,
+		.end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = MX51_INT_HS_I2C,
+		.end = MX51_INT_HS_I2C,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device mxc_hsi2c_device = {
+	.name = "imx-i2c",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
+	.resource = mxc_hsi2c_resources
+};
+
+static u64 usb_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource usbotg_resources[] = {
+	{
+		.start = MX51_USB_OTG_BASE_ADDR,
+		.end = MX51_USB_OTG_BASE_ADDR + 0x1ff,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = MX51_INT_USB_OTG,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+/* OTG gadget device */
+struct platform_device mxc_usbdr_udc_device = {
+	.name		= "fsl-usb2-udc",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(usbotg_resources),
+	.resource	= usbotg_resources,
+	.dev		= {
+		.dma_mask		= &usb_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+struct platform_device mx53_usbdr_udc_device = {
+	.name		= "fsl-usb2-udc",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(usbotg_resources),
+	.resource	= usbotg_resources,
+	.dev		= {
+		.dma_mask		= &usb_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+struct platform_device mxc_usbdr_host_device = {
+	.name = "mxc-ehci",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(usbotg_resources),
+	.resource = usbotg_resources,
+	.dev = {
+		.dma_mask = &usb_dma_mask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+
+struct platform_device mx53_usbdr_host_device = {
+	.name = "fsl-ehci",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(usbotg_resources),
+	.resource = usbotg_resources,
+	.dev = {
+		.dma_mask = &usb_dma_mask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+
+static struct resource usbotg_wakeup_resources[] = {
+        {
+                .start = MX51_INT_USB_OTG,/* wakeup irq */
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = MX51_INT_USB_OTG,/* usb core irq */
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mx53_usbdr_wakeup_device = {
+        .name = "usb_wakeup",
+        .id   = 0,
+        .num_resources = ARRAY_SIZE(usbotg_wakeup_resources),
+        .resource = usbotg_wakeup_resources,
+};
+
+static struct resource usbotg_xcvr_resources[] = {
+	{
+		.start = MX51_USB_OTG_BASE_ADDR,
+		.end = MX51_USB_OTG_BASE_ADDR + 0x1ff,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = MX51_INT_USB_OTG,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device mx53_usbdr_otg_device = {
+	.name = "fsl-usb2-otg",
+	.id = -1,
+	.dev		= {
+		.dma_mask		= &usb_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+	.resource      = usbotg_xcvr_resources,
+	.num_resources = ARRAY_SIZE(usbotg_xcvr_resources),
+};
+
+static struct resource usbh1_resources[] = {
+	{
+		.start = MX51_USB_OTG_BASE_ADDR + 0x200,
+		.end = MX51_USB_OTG_BASE_ADDR + 0x200 + 0x1ff,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = MX51_INT_USB_HS1,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device mxc_usbh1_device = {
+	.name = "mxc-ehci",
+	.id = 1,
+	.num_resources = ARRAY_SIZE(usbh1_resources),
+	.resource = usbh1_resources,
+	.dev = {
+		.dma_mask = &usb_dma_mask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+
+struct platform_device mx53_usbh1_device = {
+        .name = "fsl-ehci",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(usbh1_resources),
+        .resource = usbh1_resources,
+        .dev = {
+                .dma_mask = &usb_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource usbh2_resources[] = {
+	{
+		.start = MX51_USB_OTG_BASE_ADDR + 0x400,
+		.end = MX51_USB_OTG_BASE_ADDR + 0x400 + 0x1ff,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = MX51_INT_USB_HS2,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device mxc_usbh2_device = {
+	.name = "mxc-ehci",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(usbh2_resources),
+	.resource = usbh2_resources,
+	.dev = {
+		.dma_mask = &usb_dma_mask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+};
+
+struct platform_device mxc_pm_device = {
+	.name = "mx5_pm",
+	.id = 0,
+};
+
+static struct resource usbh1_wakeup_resources[] = {
+        {
+                .start = MX51_INT_USB_HS1, /*wakeup irq*/
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = MX51_INT_USB_HS1,
+                .flags = IORESOURCE_IRQ,/* usb core irq */
+        },
+};
+
+struct platform_device mx53_usbh1_wakeup_device = {
+        .name = "usb_wakeup",
+        .id   = 1,
+        .num_resources = ARRAY_SIZE(usbh1_wakeup_resources),
+        .resource = usbh1_wakeup_resources,
+};
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
new file mode 100644
index 00000000000..a0de07b318f
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.h
@@ -0,0 +1,12 @@
+extern struct platform_device mxc_usbdr_host_device;
+extern struct platform_device mx53_usbdr_host_device;
+extern struct platform_device mxc_usbh1_device;
+extern struct platform_device mxc_usbh2_device;
+extern struct platform_device mx53_usbh1_device;
+extern struct platform_device mxc_usbdr_udc_device;
+extern struct platform_device mx53_usbdr_udc_device;
+extern struct platform_device mxc_hsi2c_device;
+extern struct platform_device mxc_pm_device;
+extern struct platform_device mx53_usbdr_wakeup_device;
+extern struct platform_device mx53_usbh1_wakeup_device;
+extern struct platform_device mx53_usbdr_otg_device;
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index df4a508f240..924395a90b2 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -14,7 +14,9 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 
+#include <asm/sizes.h>
 #include <asm/mach/map.h>
+#include <asm/pmu.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -92,6 +94,9 @@ void __init imx51_init_early(void)
 	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
 	pm_idle = imx5_idle;
+
+	if (!system_rev)
+		system_rev = 0x51000;
 }
 
 void __init imx53_init_early(void)
@@ -99,6 +104,10 @@ void __init imx53_init_early(void)
 	mxc_set_cpu_type(MXC_CPU_MX53);
 	mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
+	init_consistent_dma_size(SZ_128M);
+
+	if (!system_rev)
+		system_rev = 0x53000;
 }
 
 void __init mx50_init_irq(void)
@@ -130,7 +139,7 @@ static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
 };
 
 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
-	.fw_name = "sdma-imx51.bin",
+	.fw_name = "imx/sdma/sdma-imx51-to3.bin",
 	.script_addrs = &imx51_sdma_script,
 };
 
@@ -149,7 +158,7 @@ static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
 };
 
 static struct sdma_platform_data imx53_sdma_pdata __initdata = {
-	.fw_name = "sdma-imx53.bin",
+	.fw_name = "imx/sdma/sdma-imx53-to1.bin",
 	.script_addrs = &imx53_sdma_script,
 };
 
@@ -164,6 +173,21 @@ void __init imx50_soc_init(void)
 	mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
 }
 
+static struct resource mx5_pmu_resources[] = {
+	{
+		/* MX51/53 share the same IRQ number */
+		.start	= MX51_INT_PMU,
+		.flags	= IORESOURCE_IRQ,
+	}
+};
+
+static struct platform_device mx5_pmu_device = {
+	.name		= "arm-pmu",
+	.id		= ARM_PMU_DEVICE_CPU,
+	.resource	= &mx5_pmu_resources,
+	.num_resources	= 1,
+};
+
 void __init imx51_soc_init(void)
 {
 	/* i.mx51 has the i.mx31 type gpio */
@@ -174,6 +198,8 @@ void __init imx51_soc_init(void)
 
 	/* i.mx51 has the i.mx35 type sdma */
 	imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+
+	platform_device_register(&mx5_pmu_device);
 }
 
 void __init imx53_soc_init(void)
@@ -189,4 +215,6 @@ void __init imx53_soc_init(void)
 
 	/* i.mx53 has the i.mx35 type sdma */
 	imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+
+	platform_device_register(&mx5_pmu_device);
 }
diff --git a/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c b/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c
new file mode 100644
index 00000000000..75266141fea
--- /dev/null
+++ b/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+/*
+ * mx53_loco_pmic_da9053.c  --  i.MX53 LOCO driver for pmic da9053
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/pm.h>
+#include <linux/mfd/da9052/led.h>
+#include <linux/mfd/da9052/tsi.h>
+#include <mach/irqs.h>
+#include <mach/iomux-mx53.h>
+
+#define DA9052_LDO(max, min, rname, suspend_mv) \
+{\
+	.constraints = {\
+		.name		= (rname), \
+		.max_uV		= (max) * 1000,\
+		.min_uV		= (min) * 1000,\
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE\
+		|REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE,\
+		.valid_modes_mask = REGULATOR_MODE_NORMAL,\
+		.state_mem = { \
+			.uV = suspend_mv * 1000, \
+			.mode = REGULATOR_MODE_NORMAL, \
+			.enabled = (0 == suspend_mv) ? 0 : 1, \
+			.disabled = 0, \
+		}, \
+	},\
+}
+
+#ifdef CONFIG_SND_SOC_SGTL5000
+
+static struct regulator_consumer_supply sgtl5000_consumer[] = {
+	REGULATOR_SUPPLY("VDDA", NULL),
+	REGULATOR_SUPPLY("VDDIO", NULL),
+};
+
+static struct regulator_init_data sgtl5000_reg_initdata = {
+	.constraints = {
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(sgtl5000_consumer),
+	.consumer_supplies = &sgtl5000_consumer[0],
+};
+
+static struct fixed_voltage_config sgtl5000_reg_config = {
+	.supply_name		= "VDDA",
+	.microvolts		= 3200000,
+	.gpio			= -1,
+	.init_data		= &sgtl5000_reg_initdata,
+};
+
+static struct platform_device sgtl5000_reg_devices = {
+
+	.name	= "reg-fixed-voltage",
+	.id	= 1,
+	.dev	= {
+		.platform_data = &sgtl5000_reg_config,
+	},
+};
+#endif /* CONFIG_SND_SOC_SGTL5000 */
+
+/* currently the suspend_mv here takes no effects for DA9053
+preset-voltage have to be done in the latest stage during
+suspend*/
+static struct regulator_init_data da9052_regulators_init[] = {
+	DA9052_LDO(DA9052_LDO1_VOLT_UPPER,
+		DA9052_LDO1_VOLT_LOWER, "DA9052_LDO1", 1300),
+	DA9052_LDO(DA9052_LDO2_VOLT_UPPER,
+		DA9052_LDO2_VOLT_LOWER, "DA9052_LDO2", 1300),
+	DA9052_LDO(DA9052_LDO34_VOLT_UPPER,
+		DA9052_LDO34_VOLT_LOWER, "DA9052_LDO3", 3300),
+	DA9052_LDO(DA9052_LDO34_VOLT_UPPER,
+		DA9052_LDO34_VOLT_LOWER, "DA9052_LDO4", 2775),
+	DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+		DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO5", 1300),
+	DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+		DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO6", 1200),
+	DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+		DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO7", 2750),
+	DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+		DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO8", 1800),
+	DA9052_LDO(DA9052_LDO9_VOLT_UPPER,
+		DA9052_LDO9_VOLT_LOWER, "DA9052_LDO9", 2500),
+	DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+		DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO10", 1200),
+
+	/* BUCKS */
+	DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER,
+		DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_CORE", 850),
+	DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER,
+		DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_PRO", 950),
+	DA9052_LDO(DA9052_BUCK_MEM_VOLT_UPPER,
+		DA9052_BUCK_MEM_VOLT_LOWER, "DA9052_BUCK_MEM", 1500),
+	DA9052_LDO(DA9052_BUCK_PERI_VOLT_UPPER,
+		DA9052_BUCK_PERI_VOLT_LOWER, "DA9052_BUCK_PERI", 2500)
+};
+
+
+static struct da9052_tsi_platform_data da9052_tsi = {
+	.pen_up_interval = 50,
+	.tsi_delay_bit_shift = 6,
+	.tsi_skip_bit_shift = 3,
+	.num_gpio_tsi_register = 3,
+	.tsi_supply_voltage = 2500,
+	 /* This is the DA9052 LDO number used for powering the TSI */
+	.tsi_ref_source = 9,
+	.max_tsi_delay = TSI_DELAY_4SLOTS,
+	.max_tsi_skip_slot = TSI_SKIP_330SLOTS,
+};
+
+static struct da9052_led_platform_data da9052_gpio_led[] = {
+	{
+		.id = DA9052_LED_4,
+		.name = "LED_GPIO14",
+	},
+	{
+		.id = DA9052_LED_5,
+		.name = "LED_GPIO15",
+	},
+};
+
+static struct da9052_leds_platform_data da9052_gpio_leds = {
+	.num_leds = ARRAY_SIZE(da9052_gpio_led),
+	.led = da9052_gpio_led,
+};
+
+
+static void da9052_init_ssc_cache(struct da9052 *da9052)
+{
+	unsigned char cnt;
+
+	/* First initialize all registers as Non-volatile */
+	for (cnt = 0; cnt < DA9052_REG_CNT; cnt++) {
+		da9052->ssc_cache[cnt].type = NON_VOLATILE;
+		da9052->ssc_cache[cnt].status = INVALID;
+		da9052->ssc_cache[cnt].val = 0;
+	}
+
+	/* Now selectively set type for all Volatile registers */
+	/* Reg 1 - 9 */
+	da9052->ssc_cache[DA9052_STATUSA_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_STATUSB_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_STATUSC_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_STATUSD_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_EVENTA_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_EVENTB_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_EVENTC_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_EVENTD_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_FAULTLOG_REG].type = VOLATILE;
+
+	/* Reg 15 */
+	da9052->ssc_cache[DA9052_CONTROLB_REG].type = VOLATILE;
+	/* Reg - 17 */
+	da9052->ssc_cache[DA9052_CONTROLD_REG].type = VOLATILE;
+	/* Reg - 60 */
+	da9052->ssc_cache[DA9052_SUPPLY_REG].type = VOLATILE;
+	/* Reg - 62 */
+	da9052->ssc_cache[DA9052_CHGBUCK_REG].type = VOLATILE;
+
+	/* Reg 67 - 68 */
+	da9052->ssc_cache[DA9052_INPUTCONT_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_CHGTIME_REG].type = VOLATILE;
+
+	/* Reg - 70 */
+	da9052->ssc_cache[DA9052_BOOST_REG].type = VOLATILE;
+
+	/* Reg - 81 */
+	da9052->ssc_cache[DA9052_ADCMAN_REG].type = VOLATILE;
+
+	/* Reg - 83 - 85 */
+	da9052->ssc_cache[DA9052_ADCRESL_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_ADCRESH_REG].type = VOLATILE;
+	da9052->ssc_cache[DA9052_VDDRES_REG].type = VOLATILE;
+
+	/* Reg - 87 */
+	da9052->ssc_cache[DA9052_ICHGAV_REG].type = VOLATILE;
+
+	/* Reg - 90 */
+	da9052->ssc_cache[DA9052_TBATRES_REG].type = VOLATILE;
+
+	/* Reg - 95 */
+	da9052->ssc_cache[DA9052_ADCIN4RES_REG].type = VOLATILE;
+
+	/* Reg - 98 */
+	da9052->ssc_cache[DA9052_ADCIN5RES_REG].type = VOLATILE;
+
+	/* Reg - 101 */
+	da9052->ssc_cache[DA9052_ADCIN6RES_REG].type = VOLATILE;
+
+	/* Reg - 104 */
+	da9052->ssc_cache[DA9052_TJUNCRES_REG].type = VOLATILE;
+
+	/* Reg 106 - 110 */
+	da9052->ssc_cache[DA9052_TSICONTB_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_TSIXMSB_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_TSIYMSB_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_TSILSB_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_TSIZMSB_REG].type	= VOLATILE;
+
+	/* Reg 111 - 117 */
+	da9052->ssc_cache[DA9052_COUNTS_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_COUNTMI_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_COUNTH_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_COUNTD_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_COUNTMO_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_COUNTY_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_ALARMMI_REG].type	= VOLATILE;
+
+	/* Reg 122 - 125 */
+	da9052->ssc_cache[DA9052_SECONDA_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_SECONDB_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_SECONDC_REG].type	= VOLATILE;
+	da9052->ssc_cache[DA9052_SECONDD_REG].type	= VOLATILE;
+
+	/* Following addresses are not assigned to any register */
+	da9052->ssc_cache[126].type			= VOLATILE;
+	da9052->ssc_cache[127].type			= VOLATILE;
+}
+
+
+#define MX53_LOCO_DA9052_IRQ			(6*32 + 11)	/* GPIO7_11 */
+
+static int __init loco_da9052_init(struct da9052 *da9052)
+{
+	/* Configuring for DA9052 interrupt servce */
+	/* s3c_gpio_setpull(DA9052_IRQ_PIN, S3C_GPIO_PULL_UP);*/
+
+	/* Set interrupt as LOW LEVEL interrupt source */
+	irq_set_irq_type(gpio_to_irq(MX53_LOCO_DA9052_IRQ), IRQF_TRIGGER_LOW);
+
+	da9052_init_ssc_cache(da9052);
+
+#ifdef CONFIG_SND_SOC_SGTL5000
+	platform_device_register(&sgtl5000_reg_devices);
+#endif
+
+	return 0;
+}
+
+static struct da9052_platform_data __initdata da9052_plat = {
+	.init = loco_da9052_init,
+	.num_regulators = ARRAY_SIZE(da9052_regulators_init),
+	.regulators = da9052_regulators_init,
+	.led_data = &da9052_gpio_leds,
+	.tsi_data = &da9052_tsi,
+	/* .bat_data = &da9052_bat, */
+	/* .gpio_base = GPIO_BOARD_START, */
+};
+
+
+static struct i2c_board_info __initdata da9052_i2c_device = {
+	I2C_BOARD_INFO(DA9052_SSC_I2C_DEVICE_NAME, DA9052_I2C_ADDR >> 1),
+	.platform_data = &da9052_plat,
+};
+
+int __init mx53_loco_init_da9052(void)
+{
+	da9052_i2c_device.irq = gpio_to_irq(MX53_LOCO_DA9052_IRQ);
+	return i2c_register_board_info(0, &da9052_i2c_device, 1);
+}
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
index 98052fc852c..120dd9624dd 100644
--- a/arch/arm/mach-mx5/pm-imx5.c
+++ b/arch/arm/mach-mx5/pm-imx5.c
@@ -38,6 +38,8 @@ static int mx5_suspend_enter(suspend_state_t state)
 		return -EINVAL;
 	}
 
+	if (tzic_enable_wake(0) != 0)
+		return -EAGAIN;
 	if (state == PM_SUSPEND_MEM) {
 		local_flush_tlb_all();
 		flush_cache_all();
@@ -47,6 +49,10 @@ static int mx5_suspend_enter(suspend_state_t state)
 		__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
 	}
 	cpu_do_idle();
+
+	__raw_writel(0, MXC_CORTEXA8_PLAT_LPC);
+	clk_disable(gpc_dvfs_clk);
+
 	return 0;
 }
 
@@ -73,8 +79,9 @@ static int __init mx5_pm_init(void)
 		gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
 
 	if (!IS_ERR(gpc_dvfs_clk)) {
-		if (cpu_is_mx51())
+		if (cpu_is_mx51() || cpu_is_mx53()) {
 			suspend_set_ops(&mx5_suspend_ops);
+		}
 	} else
 		return -EPERM;
 
diff --git a/arch/arm/mach-mx5/pm.c b/arch/arm/mach-mx5/pm.c
new file mode 100644
index 00000000000..8d671ad2b0f
--- /dev/null
+++ b/arch/arm/mach-mx5/pm.c
@@ -0,0 +1,283 @@
+/*
+ *  Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/suspend.h>
+#include <linux/regulator/machine.h>
+#include <linux/proc_fs.h>
+#include <linux/cpufreq.h>
+#include <mach/iram.h>
+#include <linux/fsl_devices.h>
+#include <asm/mach-types.h>
+#include <asm/cacheflush.h>
+#include <asm/tlb.h>
+#include <asm/delay.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#ifdef CONFIG_ARCH_MX50
+#include <mach/iomux-mx50.h>
+#endif
+#include "crm_regs.h"
+
+#define DATABAHN_CTL_REG0	0
+#define DATABAHN_CTL_REG19	0x4c
+#define DATABAHN_CTL_REG79	0x13c
+#define DATABAHN_PHY_REG25	0x264
+#define MX53_OFFSET 0x20000000
+
+static struct cpu_op *cpu_op_tbl;
+static int cpu_op_nr;
+static struct clk *cpu_clk;
+static struct mxc_pm_platform_data *pm_data;
+
+#if defined(CONFIG_CPU_FREQ)
+static int org_freq;
+extern int set_cpu_freq(int wp);
+#endif
+
+
+static struct device *pm_dev;
+struct clk *gpc_dvfs_clk;
+extern void cpu_do_suspend_workaround(u32 sdclk_iomux_addr);
+extern void mx50_suspend(u32 databahn_addr);
+extern struct cpu_op *(*get_cpu_op)(int *wp);
+extern void __iomem *databahn_base;
+extern void da9053_suspend_cmd(void);
+extern void da9053_resume_dump(void);
+extern void pm_da9053_i2c_init(u32 base_addr);
+
+extern int iram_ready;
+void *suspend_iram_base;
+void (*suspend_in_iram)(void *sdclk_iomux_addr) = NULL;
+void __iomem *suspend_param1;
+
+#define TZIC_WAKEUP0_OFFSET            0x0E00
+#define TZIC_WAKEUP1_OFFSET            0x0E04
+#define TZIC_WAKEUP2_OFFSET            0x0E08
+#define TZIC_WAKEUP3_OFFSET            0x0E0C
+#define GPIO7_0_11_IRQ_BIT		(0x1<<11)
+
+static void mx53_smd_loco_irq_wake_fixup(void)
+{
+	void __iomem *tzic_base;
+	tzic_base = ioremap(MX53_TZIC_BASE_ADDR, SZ_4K);
+	if (NULL == tzic_base) {
+		pr_err("fail to map MX53_TZIC_BASE_ADDR\n");
+		return;
+	}
+	__raw_writel(0, tzic_base + TZIC_WAKEUP0_OFFSET);
+	__raw_writel(0, tzic_base + TZIC_WAKEUP1_OFFSET);
+	__raw_writel(0, tzic_base + TZIC_WAKEUP2_OFFSET);
+	/* only enable irq wakeup for da9053 */
+	__raw_writel(GPIO7_0_11_IRQ_BIT, tzic_base + TZIC_WAKEUP3_OFFSET);
+	iounmap(tzic_base);
+	pr_debug("only da9053 irq is wakeup-enabled\n");
+}
+
+extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
+
+static int mx5_suspend_enter(suspend_state_t state)
+{
+	if (gpc_dvfs_clk == NULL)
+		gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
+	/* gpc clock is needed for SRPG */
+	clk_enable(gpc_dvfs_clk);
+	switch (state) {
+	case PM_SUSPEND_MEM:
+		mx5_cpu_lp_set(STOP_POWER_OFF);
+		break;
+	case PM_SUSPEND_STANDBY:
+		mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (tzic_enable_wake(0) != 0)
+		return -EAGAIN;
+
+	if (state == PM_SUSPEND_MEM) {
+		local_flush_tlb_all();
+		flush_cache_all();
+
+		if (pm_data && pm_data->suspend_enter)
+			pm_data->suspend_enter();
+
+		suspend_in_iram(suspend_param1);
+
+		if (pm_data && pm_data->suspend_exit)
+			pm_data->suspend_exit();
+	} else {
+			cpu_do_idle();
+	}
+	clk_disable(gpc_dvfs_clk);
+
+	return 0;
+}
+
+
+/*
+ * Called after processes are frozen, but before we shut down devices.
+ */
+static int mx5_suspend_prepare(void)
+{
+#if defined(CONFIG_CPU_FREQ)
+#define MX53_SUSPEND_CPU_WP 1000000000
+	struct cpufreq_freqs freqs;
+	u32 suspend_wp = 0;
+	org_freq = clk_get_rate(cpu_clk);
+	/* workaround for mx53 to suspend on 400MHZ wp */
+	if (cpu_is_mx53())
+		for (suspend_wp = 0; suspend_wp < cpu_op_nr; suspend_wp++)
+			if (cpu_op_tbl[suspend_wp].cpu_rate
+				== MX53_SUSPEND_CPU_WP)
+				break;
+	if (suspend_wp == cpu_op_nr)
+		suspend_wp = 0;
+	pr_info("suspend wp cpu=%d\n", cpu_op_tbl[suspend_wp].cpu_rate);
+	freqs.old = org_freq / 1000;
+	freqs.new = cpu_op_tbl[suspend_wp].cpu_rate / 1000;
+	freqs.cpu = 0;
+	freqs.flags = 0;
+
+	if (clk_get_rate(cpu_clk) != cpu_op_tbl[suspend_wp].cpu_rate) {
+		set_cpu_freq(cpu_op_tbl[suspend_wp].cpu_rate);
+		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+	}
+#endif
+	return 0;
+}
+
+/*
+ * Called before devices are re-setup.
+ */
+static void mx5_suspend_finish(void)
+{
+#if defined(CONFIG_CPU_FREQ)
+	struct cpufreq_freqs freqs;
+
+	freqs.old = clk_get_rate(cpu_clk) / 1000;
+	freqs.new = org_freq / 1000;
+	freqs.cpu = 0;
+	freqs.flags = 0;
+
+
+	if (org_freq != clk_get_rate(cpu_clk)) {
+		set_cpu_freq(org_freq);
+		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+	}
+#endif
+}
+
+/*
+ * Called after devices are re-setup, but before processes are thawed.
+ */
+static void mx5_suspend_end(void)
+{
+}
+
+static int mx5_pm_valid(suspend_state_t state)
+{
+	return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
+}
+
+struct platform_suspend_ops mx5_suspend_ops = {
+	.valid = mx5_pm_valid,
+	.prepare = mx5_suspend_prepare,
+	.enter = mx5_suspend_enter,
+	.finish = mx5_suspend_finish,
+	.end = mx5_suspend_end,
+};
+
+static int __devinit mx5_pm_probe(struct platform_device *pdev)
+{
+	pm_dev = &pdev->dev;
+	pm_data = pdev->dev.platform_data;
+
+	return 0;
+}
+
+static struct platform_driver mx5_pm_driver = {
+	.driver = {
+		   .name = "mx5_pm",
+		   },
+	.probe = mx5_pm_probe,
+};
+
+static int __init pm_init(void)
+{
+	unsigned long iram_paddr, cpaddr;
+
+	pr_info("Static Power Management for Freescale i.MX5\n");
+	if (platform_driver_register(&mx5_pm_driver) != 0) {
+		printk(KERN_ERR "mx5_pm_driver register failed\n");
+		return -ENODEV;
+	}
+	suspend_set_ops(&mx5_suspend_ops);
+	/* Move suspend routine into iRAM */
+	cpaddr = iram_alloc(SZ_4K, &iram_paddr);
+	/* Need to remap the area here since we want the memory region
+		 to be executable. */
+	suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K,
+					  MT_HIGH_VECTORS);
+	pr_info("cpaddr = %x suspend_iram_base=%x\n", cpaddr, suspend_iram_base);
+
+	if (cpu_is_mx51() || cpu_is_mx53()) {
+		suspend_param1 = MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR + 0x4b8);
+		memcpy(cpaddr, cpu_do_suspend_workaround,
+			SZ_4K);
+	} else if (cpu_is_mx50()) {
+		/*
+		 * Need to run the suspend code from IRAM as the DDR needs
+		 * to be put into self refresh mode manually.
+		 */
+		memcpy(cpaddr, mx50_suspend, SZ_4K);
+
+		suspend_param1 = databahn_base;
+	}
+	suspend_in_iram = (void *)suspend_iram_base;
+
+	cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+
+	cpu_clk = clk_get(NULL, "cpu_clk");
+	if (IS_ERR(cpu_clk)) {
+		printk(KERN_DEBUG "%s: failed to get cpu_clk\n", __func__);
+		return PTR_ERR(cpu_clk);
+	}
+	printk(KERN_INFO "PM driver module loaded\n");
+
+	return 0;
+}
+
+
+static void __exit pm_cleanup(void)
+{
+	/* Unregister the device structure */
+	platform_driver_unregister(&mx5_pm_driver);
+}
+
+module_init(pm_init);
+module_exit(pm_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("PM driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-mx5/sdram_autogating.c b/arch/arm/mach-mx5/sdram_autogating.c
new file mode 100644
index 00000000000..f352d360a9d
--- /dev/null
+++ b/arch/arm/mach-mx5/sdram_autogating.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file sdram_autogating.c
+ *
+ * @brief Enable auto clock gating of the EMI_FAST clock using M4IF.
+ *
+ * The APIs are for enabling and disabling automatic clock gating of EMI_FAST.
+ *
+ * @ingroup PM
+ */
+#include <linux/module.h>
+#include <asm/io.h>
+#include <linux/proc_fs.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include <mach/sdram_autogating.h>
+#include "crm_regs.h"
+
+static struct device *sdram_autogating_dev;
+#define M4IF_CNTL_REG0		0x8c
+#define M4IF_CNTL_REG1		0x90
+
+/* Flag used to indicate if SDRAM M4IF autoclock gating feature is active. */
+static int sdram_autogating_is_active;
+static int sdram_autogating_paused;
+static void __iomem *m4if_base;
+
+void start_sdram_autogating(void);
+void stop_sdram_autogating(void);
+int sdram_autogating_active(void);
+
+static void enable(void)
+{
+	u32 reg;
+
+	/* Set the Fast arbitration Power saving timer */
+	reg = __raw_readl(m4if_base + M4IF_CNTL_REG1);
+	reg &= ~0xFF;
+	reg |= 0x09;
+	__raw_writel(reg, m4if_base + M4IF_CNTL_REG1);
+	/*Allow for automatic gating of the EMI internal clock.
+	 * If this is done, emi_intr CCGR bits should be set to 11.
+	 */
+	reg = __raw_readl(m4if_base + M4IF_CNTL_REG0);
+	reg &= ~0x5;
+	__raw_writel(reg, m4if_base + M4IF_CNTL_REG0);
+
+	sdram_autogating_is_active = 1;
+}
+
+static void disable(void)
+{
+	u32 reg;
+
+	reg = __raw_readl(m4if_base + M4IF_CNTL_REG0);
+	reg |= 0x4;
+	__raw_writel(reg, m4if_base + M4IF_CNTL_REG0);
+	sdram_autogating_is_active = 0;
+}
+
+int sdram_autogating_active()
+{
+	return sdram_autogating_is_active;
+}
+
+void start_sdram_autogating()
+{
+	if (cpu_is_mx50())
+		return;
+	if (sdram_autogating_paused) {
+		enable();
+		sdram_autogating_paused = 0;
+	}
+}
+
+void  stop_sdram_autogating()
+{
+	if (cpu_is_mx50())
+		return;
+
+	if (sdram_autogating_is_active) {
+		sdram_autogating_paused = 1;
+		disable();
+	}
+}
+
+static ssize_t sdram_autogating_enable_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	if (sdram_autogating_is_active)
+		return sprintf(buf,
+			"M4IF autoclock gating for EMI_FAST enabled\n");
+	else
+		return sprintf(buf,
+			"M4IF autoclock gating for EMI_FAST disabled\n");
+}
+
+static ssize_t sdram_autogating_enable_store(struct device *dev,
+				 struct device_attribute *attr,
+				 const char *buf, size_t size)
+{
+	if (strstr(buf, "1") != NULL)
+		enable();
+	else if (strstr(buf, "0") != NULL) {
+		if (sdram_autogating_is_active)
+			disable();
+	}
+	return size;
+}
+
+static DEVICE_ATTR(enable, 0644, sdram_autogating_enable_show,
+			sdram_autogating_enable_store);
+
+/*!
+ * This is the probe routine for the auto clockgating of sdram driver.
+ *
+ * @param   pdev   The platform device structure
+ *
+ * @return         The function returns 0 on success
+ *
+ */
+static int __devinit sdram_autogating_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int err = 0;
+
+	sdram_autogating_dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		return -ENOMEM;
+	}
+	m4if_base = ioremap(res->start, res->end - res->start + 1);
+
+	err = sysfs_create_file(&sdram_autogating_dev->kobj,
+							&dev_attr_enable.attr);
+	if (err) {
+		printk(KERN_ERR
+		       "Unable to register sysdev entry for sdram_autogating");
+		return err;
+	}
+
+	sdram_autogating_is_active = 0;
+
+	return 0;
+}
+
+static struct platform_driver sdram_autogating_driver = {
+	.driver = {
+		   .name = "sdram_autogating",
+		},
+	.probe = sdram_autogating_probe,
+};
+
+/*!
+ * Initialise the sdram_autogating_driver.
+ *
+ * @return  The function always returns 0.
+ */
+
+static int __init sdram_autogating_init(void)
+{
+	if (platform_driver_register(&sdram_autogating_driver) != 0) {
+		printk(KERN_ERR "sdram_autogating_driver register failed\n");
+		return -ENODEV;
+	}
+
+	printk(KERN_INFO "sdram autogating driver module loaded\n");
+	return 0;
+}
+
+static void __exit sdram_autogating_cleanup(void)
+{
+	sysfs_remove_file(&sdram_autogating_dev->kobj, &dev_attr_enable.attr);
+
+	/* Unregister the device structure */
+	platform_driver_unregister(&sdram_autogating_driver);
+}
+
+module_init(sdram_autogating_init);
+module_exit(sdram_autogating_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("sdram_autogating driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-mx5/suspend.S b/arch/arm/mach-mx5/suspend.S
new file mode 100644
index 00000000000..c7937ec94d9
--- /dev/null
+++ b/arch/arm/mach-mx5/suspend.S
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/linkage.h>
+
+#define ARM_CTRL_DCACHE  1 << 2
+#define ARM_CTRL_ICACHE  1 << 12
+#define ARM_AUXCR_L2EN   1 << 1
+
+
+/*
+ *	cpu_do_suspend_workaround()
+ *
+ *	Suspend the processor (eg, wait for interrupt).
+ *
+ *	IRQs are already disabled.
+ */
+ENTRY(cpu_do_suspend_workaround)
+    stmfd   sp!, {r4,r5,r6,r7,r9,r10,r11}     @ Save registers
+
+   mov    r6, r0                       @save iomux address
+    /* Disable L1 caches */
+    mrc     p15, 0, r0, c1, c0, 0    @ R0 = system control reg
+    bic     r0, r0, #ARM_CTRL_ICACHE @ Disable ICache
+    bic     r0, r0, #ARM_CTRL_DCACHE @ Disable DCache
+    mcr     p15, 0, r0, c1, c0, 0    @ Update system control reg
+
+    mrc     p15, 1, r0, c0, c0, 1   @ Read CLIDR
+    ands    r3, r0, #0x7000000       @ Isolate level of coherency
+    mov     r3, r3, lsr #23         @ Cache level value (naturally aligned)
+    beq     FinishedClean
+    mov     r10, #0
+Loop1Clean:
+    add     r2, r10, r10, lsr #1    @ Work out cache level
+    mov     r1, r0, lsr r2          @ R0 bottom 3 bits = Cache Type for this level
+    and     r1, r1, #7              @ Get those 3 bits alone
+    cmp     r1, #2
+    blt     SkipClean                @ No cache or only instruction cache at this level
+    mcr     p15, 2, r10, c0, c0, 0  @ Write the Cache Size selection register
+    mov     r1, #0
+    .long   0xF57FF06F              @ ISB
+    mrc     p15, 1, r1, c0, c0, 0   @ Reads current Cache Size ID register
+    and     r2, r1, #7             @ Extract the line length field
+    add     r2, r2, #4              @ Add 4 for the line length offset (log2 16 bytes)
+    ldr     r4, =0x3FF
+    ands    r4, r4, r1, lsr #3      @ R4 is the max number on the way size (right aligned)
+    clz     r5, r4                  @ R5 is the bit position of the way size increment
+    ldr     r7, =0x00007FFF
+    ands    r7, r7, r1, lsr #13     @ R7 is the max number of the index size (right aligned)
+Loop2Clean:
+    mov     r9, r4                  @ R9 working copy of the max way size (right aligned)
+Loop3Clean:
+    orr     r11, r10, r9, lsl r5    @ Factor in the way number and cache number into R11
+    orr     r11, r11, r7, lsl r2    @ Factor in the index number
+    mcr     p15, 0, r11, c7, c14, 2 @ Clean and invalidate by set/way
+    subs    r9, r9, #1              @ Decrement the way number
+    bge     Loop3Clean
+    subs    r7, r7, #1              @ Decrement the index
+    bge     Loop2Clean
+SkipClean:
+    add     r10, r10, #2            @ Increment the cache number
+    cmp     r3, r10
+    bgt     Loop1Clean
+
+FinishedClean:
+
+    /* Disable L2 cache */
+    mrc     p15, 0, r0, c1, c0, 1   @ R0 = auxiliary control reg
+    bic     r0, r0, #ARM_AUXCR_L2EN @ Disable L2 cache
+    mcr     p15, 0, r0, c1, c0, 1   @ Update aux control reg
+
+#if 0
+	/*Set the DDR drive strength to low */
+	ldr        r10, [r6]
+	and       r10, r10, #0xF1        @ clear bits 2-1
+	str        r10, [r6]
+#endif
+
+    .long     0xe320f003              @ Opcode for WFI
+
+#if 0
+	/*Set the DDR drive strength to max */
+	orr       r10, r10, #0x06        @ set bits 2-1
+	str        r10, [r6]
+#endif
+
+	ldr     r11, =0x0000fFFF
+TestLoop:
+	subs    r11,r11, #1              @ Decrement the index
+	bge     TestLoop
+
+    mov     r0, #0
+    mcr     p15, 0, r0, c7, c5, 0   @ Invalidate inst cache
+
+    /* Invalidate data caches */
+    mrc     p15, 1, r0, c0, c0, 1   @ Read CLIDR
+    ands    r3, r0, #0x7000000      @ Isolate level of coherency
+    mov     r3, r3, lsr #23         @ Cache level value (naturally aligned)
+    beq     FinishedInvalidate
+    mov     r10, #0
+Loop1Invalidate:
+    add     r2, r10, r10, lsr #1    @ Work out cache level
+    mov     r1, r0, lsr r2          @ R0 bottom 3 bits = Cache Type for this level
+    and     r1, r1, #7              @ Get those 3 bits alone
+    cmp     r1, #2
+    blt     SkipInvalidate          @ No cache or only instruction cache at this level
+    mcr     p15, 2, r10, c0, c0, 0  @ Write the Cache Size selection register
+    mov     r1, #0
+    .long   0xF57FF06F              @ ISB
+    mrc     p15, 1, r1, c0, c0, 0   @ Reads current Cache Size ID register
+    and     r2, r1, #7              @ Extract the line length field
+    add     r2, r2, #4              @ Add 4 for the line length offset (log2 16 bytes)
+    ldr     r4, =0x3FF
+    ands    r4, r4, r1, lsr #3      @ R4 is the max number on the way size (right aligned)
+    clz     r5, r4                  @ R5 is the bit position of the way size increment
+    ldr     r7, =0x00007FFF
+    ands    r7, r7, r1, lsr #13     @ R7 is the max number of the index size (right aligned)
+Loop2Invalidate:
+    mov     r9, r4                  @ R9 working copy of the max way size (right aligned)
+Loop3Invalidate:
+    orr     r11, r10, r9, lsl r5    @ Factor in the way number and cache number into R11
+    orr     r11, r11, r7, lsl r2    @ Factor in the index number
+    mcr     p15, 0, r11, c7, c6, 2  @ Invalidate by set/way
+    subs    r9, r9, #1              @ Decrement the way number
+    bge     Loop3Invalidate
+    subs    r7, r7, #1              @ Decrement the index
+    bge     Loop2Invalidate
+SkipInvalidate:
+    add     r10, r10, #2            @ Increment the cache number
+    cmp     r3, r10
+    bgt     Loop1Invalidate
+
+FinishedInvalidate:
+
+    /* Enable L2 cache */
+    mrc     p15, 0, r0, c1, c0, 1   @ R0 = auxiliary control reg
+    orr     r0, r0, #ARM_AUXCR_L2EN @ Enable L2 cache
+    mcr     p15, 0, r0, c1, c0, 1   @ Update aux control reg
+
+    /* Enable L1 caches */
+    mrc     p15, 0, r0, c1, c0, 0    @ R0 = system control reg
+    orr     r0, r0, #ARM_CTRL_ICACHE @ Enable ICache
+    orr     r0, r0, #ARM_CTRL_DCACHE @ Enable DCache
+    mcr     p15, 0, r0, c1, c0, 0    @ Update system control reg
+
+    /* Restore registers */
+    ldmfd sp!, {r4,r5,r6,r7,r9,r10,r11}
+    mov		pc, lr
+
+	.type	cpu_do_suspend, #object
+ENTRY(cpu_do_suspend)
+	.word	cpu_do_suspend_workaround
+	.size	cpu_do_suspend_workaround, . - cpu_do_suspend_workaround
diff --git a/arch/arm/mach-mx5/usb.h b/arch/arm/mach-mx5/usb.h
new file mode 100644
index 00000000000..c059f7409e6
--- /dev/null
+++ b/arch/arm/mach-mx5/usb.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <mach/common.h>
+#include "devices.h"
+
+extern int usbotg_init(struct platform_device *pdev);
+extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
+extern struct platform_device *host_pdev_register(struct resource *res,
+		  int n_res, struct fsl_usb2_platform_data *config);
+
+extern int fsl_usb_host_init(struct platform_device *pdev);
+extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata);
+extern int gpio_usbotg_utmi_active(void);
+extern void gpio_usbotg_utmi_inactive(void);
+
+extern void __init mx5_usb_dr_init(void);
+extern void __init mx5_usbh1_init(void);
+extern void __init mx5_usbh2_init(void);
+
+typedef void (*driver_vbus_func)(bool);
+extern void mx5_set_host1_vbus_func(driver_vbus_func);
+extern void mx5_set_otghost_vbus_func(driver_vbus_func);
+/*
+ * Used to set pdata->operating_mode before registering the platform_device.
+ * If OTG is configured, the controller operates in OTG mode,
+ * otherwise it's either host or device.
+ */
+#ifdef CONFIG_USB_OTG
+#define DR_UDC_MODE	FSL_USB2_DR_OTG
+#define DR_HOST_MODE	FSL_USB2_DR_OTG
+#else
+#define DR_UDC_MODE	FSL_USB2_DR_DEVICE
+#define DR_HOST_MODE	FSL_USB2_DR_HOST
+#endif
+
+extern void __iomem *imx_otg_base;
diff --git a/arch/arm/mach-mx5/usb_dr.c b/arch/arm/mach-mx5/usb_dr.c
new file mode 100755
index 00000000000..ae4df535d1e
--- /dev/null
+++ b/arch/arm/mach-mx5/usb_dr.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#define DEBUG 1
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <mach/arc_otg.h>
+#include <mach/hardware.h>
+#include <linux/delay.h>
+#include "usb.h"
+static int usbotg_init_ext(struct platform_device *pdev);
+static void usbotg_uninit_ext(struct platform_device *pdev);
+static void usbotg_clock_gate(bool on);
+
+static struct clk *usb_phy1_clk;
+static struct clk *usb_oh3_clk;
+static struct clk *usb_ahb_clk;
+static void usbotg_wakeup_event_clear(void);
+extern int clk_get_usecount(struct clk *clk);
+
+/* Beginning of Common operation for DR port */
+
+/*
+ * platform data structs
+ * 	- Which one to use is determined by CONFIG options in usb.h
+ * 	- operating_mode plugged at run time
+ */
+static struct fsl_usb2_platform_data dr_utmi_config = {
+	.name              = "DR",
+	.init              = usbotg_init_ext,
+	.exit              = usbotg_uninit_ext,
+	.phy_mode          = FSL_USB2_PHY_UTMI_WIDE,
+	.power_budget      = 500,		/* 500 mA max power */
+	.usb_clock_for_pm  = usbotg_clock_gate,
+	.transceiver       = "utmi",
+};
+
+/* Platform data for wakeup operation */
+static struct fsl_usb2_wakeup_platform_data dr_wakeup_config = {
+	.name = "DR wakeup",
+	.usb_clock_for_pm  = usbotg_clock_gate,
+	.usb_wakeup_exhandle = usbotg_wakeup_event_clear,
+};
+/* Notes: configure USB clock*/
+static int usbotg_init_ext(struct platform_device *pdev)
+{
+	struct clk *usb_clk;
+
+	/* the usb_ahb_clk will be enabled in usb_otg_init */
+	usb_ahb_clk = clk_get(NULL, "usb_ahb_clk");
+
+	usb_clk = clk_get(NULL, "usboh3_clk");
+	clk_enable(usb_clk);
+	usb_oh3_clk = usb_clk;
+
+	usb_clk = clk_get(NULL, "usb_phy1_clk");
+	clk_enable(usb_clk);
+	usb_phy1_clk = usb_clk;
+
+	return usbotg_init(pdev);
+}
+
+static void usbotg_uninit_ext(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	clk_disable(usb_phy1_clk);
+	clk_put(usb_phy1_clk);
+
+	clk_disable(usb_oh3_clk);
+	clk_put(usb_oh3_clk);
+
+	/* usb_ahb_clk will be disabled at usb_common.c */
+	usbotg_uninit(pdata);
+	clk_put(usb_ahb_clk);
+}
+
+/* Below two macros are used at otg mode to indicate usb mode*/
+#define ENABLED_BY_HOST   (0x1 << 0)
+#define ENABLED_BY_DEVICE (0x1 << 1)
+static u32 wakeup_irq_enable_src; /* only useful at otg mode */
+static void __wakeup_irq_enable(bool on, int source)
+ {
+	/* otg host and device share the OWIE bit, only when host and device
+	 * all enable the wakeup irq, we can enable the OWIE bit
+	 */
+	if (on) {
+#ifdef CONFIG_USB_OTG
+		wakeup_irq_enable_src |= source;
+		if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
+			USBCTRL |= UCTRL_OWIE;
+			USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2;
+		}
+#else
+		USBCTRL |= UCTRL_OWIE;
+		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2;
+#endif
+	} else {
+		USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2;
+		USBCTRL &= ~UCTRL_OWIE;
+		wakeup_irq_enable_src &= ~source;
+		/* The interrupt must be disabled for at least 3 clock
+		 * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
+		udelay(100);
+	}
+}
+
+static u32 low_power_enable_src; /* only useful at otg mode */
+static void __phy_lowpower_suspend(bool enable, int source)
+{
+	if (enable) {
+		low_power_enable_src |= source;
+#ifdef CONFIG_USB_OTG
+		if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
+			pr_debug("phy lowpower enabled\n");
+			UOG_PORTSC1 |= PORTSC_PHCD;
+		}
+#else
+		UOG_PORTSC1 |= PORTSC_PHCD;
+#endif
+	} else {
+		pr_debug("phy lowpower disable\n");
+		UOG_PORTSC1 &= ~PORTSC_PHCD;
+		low_power_enable_src &= ~source;
+	}
+}
+
+static void usbotg_clock_gate(bool on)
+{
+	pr_debug("%s: on is %d\n", __func__, on);
+	if (on) {
+		clk_enable(usb_ahb_clk);
+		clk_enable(usb_oh3_clk);
+		clk_enable(usb_phy1_clk);
+	} else {
+		clk_disable(usb_phy1_clk);
+		clk_disable(usb_oh3_clk);
+		clk_disable(usb_ahb_clk);
+	}
+	pr_debug("usb_ahb_ref_count:%d, usb_phy_clk1_ref_count:%d\n", clk_get_usecount(usb_ahb_clk), clk_get_usecount(usb_phy1_clk));
+}
+
+void mx5_set_otghost_vbus_func(driver_vbus_func driver_vbus)
+{
+	dr_utmi_config.platform_driver_vbus = driver_vbus;
+}
+
+/* The wakeup operation for DR port, it will clear the wakeup irq status
+ * and re-enable the wakeup
+ */
+static void usbotg_wakeup_event_clear(void)
+{
+	int wakeup_req = USBCTRL & UCTRL_OWIR;
+
+	if (wakeup_req != 0) {
+		printk(KERN_INFO "Unknown wakeup.(OTGSC 0x%x)\n", UOG_OTGSC);
+		/* Disable OWIE to clear OWIR, wait 3 clock
+		 * cycles of standly clock(32KHz)
+		 */
+		USBCTRL &= ~UCTRL_OWIE;
+		udelay(100);
+		USBCTRL |= UCTRL_OWIE;
+	}
+}
+/* End of Common operation for DR port */
+
+
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+extern void fsl_usb_recover_hcd(struct platform_device *pdev);
+/* Beginning of host related operation for DR port */
+static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+	__wakeup_irq_enable(enable, ENABLED_BY_HOST);
+	/* host only care the ID change wakeup event */
+	if (enable) {
+		pr_debug("host wakeup enable\n");
+		USBCTRL_HOST2 |= UCTRL_H2OIDWK_EN;
+	} else {
+		pr_debug("host wakeup disable\n");
+		USBCTRL_HOST2 &= ~UCTRL_H2OIDWK_EN;
+		/* The interrupt must be disabled for at least 3 clock
+		 * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
+		udelay(100);
+	}
+}
+
+static void _host_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+	__phy_lowpower_suspend(enable, ENABLED_BY_HOST);
+}
+
+static enum usb_wakeup_event _is_host_wakeup(struct fsl_usb2_platform_data *pdata)
+{
+	int wakeup_req = USBCTRL & UCTRL_OWIR;
+	int otgsc = UOG_OTGSC;
+
+	/* if ID change sts, it is a host wakeup event */
+	if (wakeup_req && (otgsc & OTGSC_IS_USB_ID)) {
+		printk(KERN_INFO "otg host ID wakeup\n");
+		/* if host ID wakeup, we must clear the b session change sts */
+		UOG_OTGSC = otgsc & (~OTGSC_IS_USB_ID);
+		return WAKEUP_EVENT_ID;
+	}
+	if (wakeup_req && (!(otgsc & OTGSC_STS_USB_ID))) {
+		printk(KERN_INFO "otg host Remote wakeup\n");
+		return WAKEUP_EVENT_DPDM;
+	}
+
+	return WAKEUP_EVENT_INVALID;
+}
+
+static void host_wakeup_handler(struct fsl_usb2_platform_data *pdata)
+{
+	_host_wakeup_enable(pdata, false);
+	_host_phy_lowpower_suspend(pdata, false);
+	fsl_usb_recover_hcd(&mxc_usbdr_host_device);
+}
+/* End of host related operation for DR port */
+#endif /* CONFIG_USB_EHCI_ARC_OTG */
+
+
+#ifdef CONFIG_USB_GADGET_ARC
+/* Beginning of device related operation for DR port */
+static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+	__wakeup_irq_enable(enable, ENABLED_BY_DEVICE);
+	/* if udc is not used by any gadget, we can not enable the vbus wakeup */
+	if (!pdata->port_enables) {
+		USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN;
+		return;
+	}
+	if (enable) {
+		pr_debug("device wakeup enable\n");
+		USBCTRL_HOST2 |= UCTRL_H2OVBWK_EN;
+	} else {
+		pr_debug("device wakeup disable\n");
+		USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN;
+	}
+}
+
+static void _device_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+	__phy_lowpower_suspend(enable, ENABLED_BY_DEVICE);
+}
+
+static enum usb_wakeup_event _is_device_wakeup(struct fsl_usb2_platform_data *pdata)
+{
+	int wakeup_req = USBCTRL & UCTRL_OWIR;
+	u32 otgsc = 0;
+
+	otgsc = UOG_OTGSC;
+	if (wakeup_req  &&
+		(otgsc & OTGSC_STS_USB_ID) &&
+		(otgsc & OTGSC_IS_B_SESSION_VALID)) {
+		printk(KERN_INFO "otg udc wakeup\n");
+		return WAKEUP_EVENT_VBUS;
+	}
+	return WAKEUP_EVENT_INVALID;
+
+}
+
+static void device_wakeup_handler(struct fsl_usb2_platform_data *pdata)
+{
+	_device_wakeup_enable(pdata, false);
+	_device_phy_lowpower_suspend(pdata, false);
+}
+
+/* end of device related operation for DR port */
+#endif /* CONFIG_USB_GADGET_ARC */
+
+#define MX53_OFFSET	0x20000000
+
+void __init mx5_usb_dr_init(void)
+{
+	int ret = 0;
+#ifdef CONFIG_USB_OTG
+	if (cpu_is_mx53() || cpu_is_mx50()) {
+		mx53_usbdr_otg_device.resource[0].start	-= MX53_OFFSET;
+		mx53_usbdr_otg_device.resource[0].end	-= MX53_OFFSET;
+	}
+	/* wake_up_enalbe is useless, just for usb_register_remote_wakeup execution*/
+	dr_utmi_config.wake_up_enable = _device_wakeup_enable;
+	dr_utmi_config.operating_mode = FSL_USB2_DR_OTG;
+	dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
+	ret |= platform_device_add_data(&mx53_usbdr_otg_device, &dr_utmi_config, sizeof(dr_utmi_config));
+	ret |= platform_device_register(&mx53_usbdr_otg_device);
+	dr_wakeup_config.usb_pdata[0] = mx53_usbdr_otg_device.dev.platform_data;
+#endif
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+	if (cpu_is_mx53() || cpu_is_mx50()) {
+		mx53_usbdr_host_device.resource[0].start	-= MX53_OFFSET;
+		mx53_usbdr_host_device.resource[0].end	-= MX53_OFFSET;
+	}
+	dr_utmi_config.operating_mode = DR_HOST_MODE;
+	dr_utmi_config.wake_up_enable = _host_wakeup_enable;
+	dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend;
+	dr_utmi_config.is_wakeup_event = _is_host_wakeup;
+	dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
+	dr_utmi_config.wakeup_handler = host_wakeup_handler;
+	ret |= platform_device_add_data(&mx53_usbdr_host_device, &dr_utmi_config, sizeof(dr_utmi_config));
+	ret |= platform_device_register(&mx53_usbdr_host_device);
+	dr_wakeup_config.usb_pdata[1] = mx53_usbdr_host_device.dev.platform_data;
+#endif
+#ifdef CONFIG_USB_GADGET_ARC
+	if (cpu_is_mx53() || cpu_is_mx50()) {
+		mx53_usbdr_udc_device.resource[0].start	-= MX53_OFFSET;
+		mx53_usbdr_udc_device.resource[0].end	-= MX53_OFFSET;
+	}
+	dr_utmi_config.operating_mode = DR_UDC_MODE;
+	dr_utmi_config.wake_up_enable = _device_wakeup_enable;
+	dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend;
+	dr_utmi_config.is_wakeup_event = _is_device_wakeup;
+	dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
+	dr_utmi_config.wakeup_handler = device_wakeup_handler;
+	ret |= platform_device_add_data(&mx53_usbdr_udc_device, &dr_utmi_config, sizeof(dr_utmi_config));
+	ret |= platform_device_register(&mx53_usbdr_udc_device);
+	dr_wakeup_config.usb_pdata[2] = mx53_usbdr_udc_device.dev.platform_data;
+#endif
+	mx53_usbdr_wakeup_device.dev.platform_data = &dr_wakeup_config;
+	ret |= platform_device_register(&mx53_usbdr_wakeup_device);
+	if (ret)
+		printk(KERN_ERR "%s(%d): error occures while init usb dr \n", __func__, __LINE__);
+}
diff --git a/arch/arm/mach-mx5/usb_h1.c b/arch/arm/mach-mx5/usb_h1.c
new file mode 100644
index 00000000000..0336b16a133
--- /dev/null
+++ b/arch/arm/mach-mx5/usb_h1.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/gpio.h>
+
+#include <asm/delay.h>
+#include <mach/hardware.h>
+#include <mach/arc_otg.h>
+#include <mach/iomux-mx51.h>
+#include <mach/iomux-mx53.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include "usb.h"
+
+static struct clk *usb_phy2_clk;
+static struct clk *usb_oh3_clk;
+static struct clk *usb_ahb_clk;
+extern int clk_get_usecount(struct clk *clk);
+
+#define MX5X_USBH1_STP		IMX_GPIO_NR(1, 27)
+#define MX51_3DS_PHY_RESET	IMX_GPIO_NR(2, 5)
+
+#ifdef CONFIG_USB_EHCI_ARC
+extern void fsl_usb_recover_hcd(struct platform_device *pdev);
+#else
+static void fsl_usb_recover_hcd(struct platform_device *pdev)
+{; }
+#endif
+/*
+ * USB Host1 HS port
+ */
+static int gpio_usbh1_active(void)
+{
+	iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
+	iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D17__GPIO2_1;
+	int ret;
+
+	/* Set USBH1_STP to GPIO and toggle it */
+	mxc_iomux_v3_setup_pad(usbh1stp_gpio);
+	ret = gpio_request(MX5X_USBH1_STP, "usbh1_stp");
+
+	if (ret) {
+		pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
+		return ret;
+	}
+	gpio_direction_output(MX5X_USBH1_STP, 0);
+	gpio_set_value(MX5X_USBH1_STP, 1);
+
+	/* Signal only used on MX51-3DS for reset to PHY.*/
+	if (machine_is_mx51_3ds()) {
+		mxc_iomux_v3_setup_pad(phyreset_gpio);
+		ret = gpio_request(MX51_3DS_PHY_RESET, "eim_d17");
+		if (ret) {
+			pr_debug("failed to get MX51_PAD_EIM_D17__GPIO2_1: %d\n", ret);
+			return ret;
+		}
+		gpio_direction_output(MX51_3DS_PHY_RESET, 0);
+		gpio_set_value(MX51_3DS_PHY_RESET, 1);
+	}
+
+	msleep(100);
+
+	return 0;
+}
+
+static void gpio_usbh1_inactive(void)
+{
+	/* Signal only used on MX51-3DS for reset to PHY.*/
+	if (machine_is_mx51_3ds()) {
+		gpio_free(MX51_3DS_PHY_RESET);
+	}
+	gpio_free(MX5X_USBH1_STP);
+}
+
+
+static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+	pr_debug("host1, %s, enable is %d\n", __func__, enable);
+	if (enable)
+		USBCTRL |= UCTRL_H1WIE;
+	else {
+		USBCTRL &= ~UCTRL_H1WIE;
+		/* The interrupt must be disabled for at least 3
+		* cycles of the standby clock(32k Hz) , that is 0.094 ms*/
+		udelay(100);
+	}
+}
+
+static void _phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+	pr_debug("host1, %s, enable is %d\n", __func__, enable);
+	if (enable) {
+		UH1_PORTSC1 |= PORTSC_PHCD;
+	} else {
+		UH1_PORTSC1 &= ~PORTSC_PHCD;
+	}
+}
+
+static void usbh1_clock_gate(bool on)
+{
+	pr_debug("%s: on is %d\n", __func__, on);
+	if (on) {
+		clk_enable(usb_ahb_clk);
+		clk_enable(usb_oh3_clk);
+		clk_enable(usb_phy2_clk);
+	} else {
+		clk_disable(usb_phy2_clk);
+		clk_disable(usb_oh3_clk);
+		clk_disable(usb_ahb_clk);
+	}
+}
+
+static enum usb_wakeup_event _is_usbh1_wakeup(struct fsl_usb2_platform_data *pdata)
+{
+	int wakeup_req = USBCTRL & UCTRL_H1WIR;
+
+	if (wakeup_req)
+		return !WAKEUP_EVENT_INVALID;
+
+	return WAKEUP_EVENT_INVALID;
+}
+
+static void h1_wakeup_handler(struct fsl_usb2_platform_data *pdata)
+{
+	_wake_up_enable(pdata, false);
+	_phy_lowpower_suspend(pdata, false);
+	fsl_usb_recover_hcd(&mxc_usbh1_device);
+}
+
+static void usbh1_wakeup_event_clear(void)
+{
+	int wakeup_req = USBCTRL & UCTRL_H1WIR;
+
+	if (wakeup_req != 0) {
+		printk(KERN_INFO "Unknown wakeup.(OTGSC 0x%x)\n", UOG_OTGSC);
+		/* Disable H1WIE to clear H1WIR, wait 3 clock
+		 * cycles of standly clock(32KHz)
+		 */
+		USBCTRL &= ~UCTRL_H1WIE;
+		udelay(100);
+		USBCTRL |= UCTRL_H1WIE;
+	}
+}
+static int fsl_usb_host_init_ext(struct platform_device *pdev)
+{
+	iomux_v3_cfg_t usbh1stp_func = MX51_PAD_USBH1_STP__USBH1_STP;
+	struct clk *usb_clk;
+	int ret;
+
+	/* the usb_ahb_clk will be enabled in usb_otg_init */
+	usb_ahb_clk = clk_get(NULL, "usb_ahb_clk");
+
+	if (cpu_is_mx53()) {
+		usb_clk = clk_get(NULL, "usboh3_clk");
+		if (usb_clk) {
+			clk_enable(usb_clk);
+			usb_oh3_clk = usb_clk;
+		}
+
+		usb_clk = clk_get(NULL, "usb_phy2_clk");
+		if (usb_clk) {
+			clk_enable(usb_clk);
+			usb_phy2_clk = usb_clk;
+		}
+	} else if (cpu_is_mx50()) {
+		usb_clk = clk_get(NULL, "usb_phy2_clk");
+		if (usb_clk) {
+			clk_enable(usb_clk);
+			usb_phy2_clk = usb_clk;
+		}
+	} else if (cpu_is_mx51()) {
+		usb_clk = clk_get(NULL, "usboh3_clk");
+		if (usb_clk) {
+			clk_enable(usb_clk);
+			usb_oh3_clk = usb_clk;
+		}
+	}
+
+	ret = fsl_usb_host_init(pdev);
+	if (ret)
+		return ret;
+
+	if (cpu_is_mx51()) {
+		/* setback USBH1_STP to be function */
+#if 0	/* Jasper: Need to do... */
+		mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST |
+				  PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE |
+				  PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+				  PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS |
+				  PAD_CTL_DRV_VOT_LOW);
+		gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP));
+#endif
+		mxc_iomux_v3_setup_pad(usbh1stp_func);
+		gpio_free(MX5X_USBH1_STP);
+	}
+
+	/* disable remote wakeup irq */
+	USBCTRL &= ~UCTRL_H1WIE;
+	return 0;
+}
+
+static void fsl_usb_host_uninit_ext(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	if (cpu_is_mx53()) {
+		if (usb_oh3_clk) {
+			clk_disable(usb_oh3_clk);
+			clk_put(usb_oh3_clk);
+		}
+
+		if (usb_phy2_clk) {
+			clk_disable(usb_phy2_clk);
+			clk_put(usb_phy2_clk);
+		}
+	} else if (cpu_is_mx50()) {
+		if (usb_phy2_clk) {
+			clk_disable(usb_phy2_clk);
+			clk_put(usb_phy2_clk);
+		}
+	} else if (cpu_is_mx51()) {
+		if (usb_oh3_clk) {
+			clk_disable(usb_oh3_clk);
+			clk_put(usb_oh3_clk);
+		}
+	}
+
+	fsl_usb_host_uninit(pdata);
+	/* usb_ahb_clk will be disabled at usb_common.c */
+	clk_put(usb_ahb_clk);
+}
+
+static struct fsl_usb2_platform_data usbh1_config = {
+	.name		= "Host 1",
+	.init		= fsl_usb_host_init_ext,
+	.exit		= fsl_usb_host_uninit_ext,
+	.operating_mode = FSL_USB2_MPH_HOST,
+	.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
+	.power_budget = 500,	/* 500 mA max power */
+	.wake_up_enable = _wake_up_enable,
+	.usb_clock_for_pm  = usbh1_clock_gate,
+	.phy_lowpower_suspend = _phy_lowpower_suspend,
+	.is_wakeup_event = _is_usbh1_wakeup,
+	.wakeup_handler = h1_wakeup_handler,
+	.transceiver = "utmi",
+};
+
+static struct fsl_usb2_wakeup_platform_data usbh1_wakeup_config = {
+		.name = "USBH1 wakeup",
+		.usb_clock_for_pm  = usbh1_clock_gate,
+		.usb_pdata = {&usbh1_config, NULL, NULL},
+		.usb_wakeup_exhandle = usbh1_wakeup_event_clear,
+};
+
+void mx5_set_host1_vbus_func(driver_vbus_func driver_vbus)
+{
+	usbh1_config.platform_driver_vbus = driver_vbus;
+}
+
+#define MX53_OFFSET	0x20000000
+void __init mx5_usbh1_init(void)
+{
+	if (cpu_is_mx51()) {
+		usbh1_config.phy_mode = FSL_USB2_PHY_ULPI;
+		usbh1_config.transceiver = "isp1504";
+		usbh1_config.gpio_usb_active = gpio_usbh1_active;
+		usbh1_config.gpio_usb_inactive = gpio_usbh1_inactive;
+	}
+	if (cpu_is_mx53() || cpu_is_mx50()) {
+		mx53_usbh1_device.resource[0].start	-= MX53_OFFSET;
+		mx53_usbh1_device.resource[0].end	-= MX53_OFFSET;
+	}
+	if (cpu_is_mx53()) {
+		usbh1_config.wakeup_pdata = &usbh1_wakeup_config;
+
+		mx53_usbh1_device.dev.platform_data = &usbh1_config;
+		platform_device_register(&mx53_usbh1_device);
+
+		mx53_usbh1_wakeup_device.dev.platform_data = &usbh1_wakeup_config;
+		platform_device_register(&mx53_usbh1_wakeup_device);
+	}
+}
+
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index b3a1f2b3ada..1c920b2b881 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -39,6 +39,12 @@ source "arch/arm/mach-mx5/Kconfig"
 
 endmenu
 
+# set if we need the UTMI transceiver
+config UTMI_MXC
+        bool
+        default y
+        depends on ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX503
+
 config MXC_IRQ_PRIOR
 	bool "Use IRQ priority"
 	help
@@ -106,4 +112,11 @@ config IRAM_ALLOC
 	bool
 	select GENERIC_ALLOCATOR
 
+config CLK_DEBUG
+	bool "clock debug information export to user space"
+	depends on PM_DEBUG && DEBUG_FS
+	default n
+	help
+	  export clk debug information to user space
+
 endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index b9f0f5f499a..bc2a8237dae 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -25,3 +25,11 @@ obj-y += ssi-fiq-ksym.o
 endif
 
 obj-y += devices/
+
+obj-$(CONFIG_ARCH_MX5) += dvfs_core.o
+
+# DVFS-PER support
+obj-$(CONFIG_MXC_DVFS_PER)	+= dvfs_per.o
+obj-$(CONFIG_UTMI_MXC)    += utmixc.o
+
+obj-$(CONFIG_USB_EHCI_ARC)	+= usb_common.o usb_wakeup.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 2ed3ab173ad..5643be65e46 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2004 - 2005 Nokia corporation
  * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  *
  * This program is free software; you can redistribute it and/or
@@ -37,6 +37,8 @@
 #include <linux/proc_fs.h>
 #include <linux/semaphore.h>
 #include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/debugfs.h>
 
 #include <mach/clock.h>
 #include <mach/hardware.h>
@@ -110,6 +112,24 @@ void clk_disable(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_disable);
 
+/*!
+ * @brief Function to get the usage count for the requested clock.
+ *
+ * This function returns the reference count for the clock.
+ *
+ * @param clk 	Handle to clock to disable.
+ *
+ * @return Returns the usage count for the requested clock.
+ */
+int clk_get_usecount(struct clk *clk)
+{
+	if (clk == NULL || IS_ERR(clk))
+		return 0;
+
+	return clk->usecount;
+}
+EXPORT_SYMBOL(clk_get_usecount);
+
 /* Retrieve the *current* clock rate. If the clock itself
  * does not provide a special calculation routine, ask
  * its parent and so on, until one is able to return
@@ -244,3 +264,122 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
 
 	return ll;
 }
+
+#ifdef CONFIG_CLK_DEBUG
+/*
+ *	debugfs support to trace clock tree hierarchy and attributes
+ */
+static int clk_debug_rate_get(void *data, u64 *val)
+{
+	struct clk *clk = data;
+
+	*val = (u64)clk_get_rate(clk);
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(clk_debug_rate_fops, clk_debug_rate_get, NULL,
+		"%llu\n");
+
+
+static struct dentry *clk_root;
+static int clk_debug_register_one(struct clk *clk)
+{
+	int err;
+	struct dentry *d, *child, *child_tmp;
+	struct clk *pa = clk_get_parent(clk);
+
+	if (pa && !IS_ERR(pa))
+		d = debugfs_create_dir(clk->name, pa->dentry);
+	else {
+		if (!clk_root)
+			clk_root = debugfs_create_dir("clock", NULL);
+		if (!clk_root)
+			return -ENOMEM;
+		d = debugfs_create_dir(clk->name, clk_root);
+	}
+
+	if (!d)
+		return -ENOMEM;
+
+	clk->dentry = d;
+
+	d = debugfs_create_u8("enable_count", S_IRUGO, clk->dentry,
+			(u8 *)&clk->usecount);
+	if (!d) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	d = debugfs_create_file("rate", S_IRUGO, clk->dentry, (void *)clk,
+			&clk_debug_rate_fops);
+	if (!d) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	return 0;
+
+err_out:
+	d = clk->dentry;
+	list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
+		debugfs_remove(child);
+	debugfs_remove(clk->dentry);
+	return err;
+}
+
+struct preinit_clk {
+	struct list_head list;
+	struct clk *clk;
+};
+static LIST_HEAD(preinit_clks);
+static DEFINE_MUTEX(preinit_lock);
+static int init_done;
+
+void clk_debug_register(struct clk *clk)
+{
+	int err;
+	struct clk *pa;
+
+	if (init_done) {
+		pa = clk_get_parent(clk);
+
+		if (pa && !IS_ERR(pa) && !pa->dentry)
+			clk_debug_register(pa);
+
+		if (!clk->dentry) {
+			err = clk_debug_register_one(clk);
+			if (err)
+				return;
+		}
+	} else {
+		struct preinit_clk *p;
+		mutex_lock(&preinit_lock);
+		p = kmalloc(sizeof(*p), GFP_KERNEL);
+		if (p) {
+			p->clk = clk;
+			list_add(&p->list, &preinit_clks);
+		}
+		mutex_unlock(&preinit_lock);
+	}
+}
+EXPORT_SYMBOL_GPL(clk_debug_register);
+
+static int __init clk_debugfs_init(void)
+{
+	struct preinit_clk *pclk, *tmp;
+
+	init_done = 1;
+
+	mutex_lock(&preinit_lock);
+	list_for_each_entry(pclk, &preinit_clks, list) {
+		clk_debug_register(pclk->clk);
+	}
+
+	list_for_each_entry_safe(pclk, tmp, &preinit_clks, list) {
+		list_del(&pclk->list);
+		kfree(pclk);
+	}
+	mutex_unlock(&preinit_lock);
+	return 0;
+}
+late_initcall(clk_debugfs_init);
+#endif
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index f5b7e0fa237..4fdf4a80c59 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -18,3 +18,26 @@ void imx_print_silicon_rev(const char *cpu, int srev)
 		pr_info("CPU identified as %s, silicon rev %d.%d\n",
 				cpu, (srev >> 4) & 0xf, srev & 0xf);
 }
+
+int mxc_jtag_enabled;		/* OFF: 0 (default), ON: 1 */
+int uart_at_24; 			/* OFF: 0 (default); ON: 1 */
+/*
+ * Here are the JTAG options from the command line. By default JTAG
+ * is OFF which means JTAG is not connected and WFI is enabled
+ *
+ *       "on" --  JTAG is connected, so WFI is disabled
+ *       "off" -- JTAG is disconnected, so WFI is enabled
+ */
+
+static int __init jtag_wfi_setup(char *p)
+{
+	if (memcmp(p, "on", 2) == 0) {
+		mxc_jtag_enabled = 1;
+		p += 2;
+	} else if (memcmp(p, "off", 3) == 0) {
+		mxc_jtag_enabled = 0;
+		p += 3;
+	}
+	return 0;
+}
+early_param("jtag", jtag_wfi_setup);
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 73db34bf588..7e8bc5cdfe8 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -39,7 +39,7 @@ static struct cpufreq_frequency_table *imx_freq_table;
 static int cpu_op_nr;
 static struct cpu_op *cpu_op_tbl;
 
-static int set_cpu_freq(int freq)
+int set_cpu_freq(int freq)
 {
 	int ret = 0;
 	int org_cpu_rate;
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index cb3e3eef55c..f7161253297 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -22,6 +22,9 @@ config IMX_HAVE_PLATFORM_IMX2_WDT
 config IMX_HAVE_PLATFORM_IMXDI_RTC
 	bool
 
+config IMX_HAVE_PLATFORM_IMX_SRTC
+	bool
+
 config IMX_HAVE_PLATFORM_IMX_FB
 	bool
 
@@ -43,6 +46,15 @@ config IMX_HAVE_PLATFORM_IMX_UART
 config IMX_HAVE_PLATFORM_IMX_UDC
 	bool
 
+config IMX_HAVE_PLATFORM_IMX_IPUV3
+	bool
+
+config IMX_HAVE_PLATFORM_IMX_TVE
+	bool
+
+config IMX_HAVE_PLATFORM_LDB
+	bool
+
 config IMX_HAVE_PLATFORM_IPU_CORE
 	bool
 
@@ -55,6 +67,9 @@ config IMX_HAVE_PLATFORM_MX2_CAMERA
 config IMX_HAVE_PLATFORM_MXC_EHCI
 	bool
 
+config IMX_HAVE_PLATFORM_MXC_GPU
+	bool
+
 config IMX_HAVE_PLATFORM_MXC_MMC
 	bool
 
@@ -80,6 +95,15 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
 config IMX_HAVE_PLATFORM_SPI_IMX
 	bool
 
+config IMX_HAVE_PLATFORM_IMX_IIM
+	bool
+
 config IMX_HAVE_PLATFORM_AHCI
 	bool
 	default y if ARCH_MX53
+
+config IMX_HAVE_PLATFORM_IMX_VPU
+	bool
+
+config IMX_HAVE_PLATFORM_IMX_SPDIF
+	bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index c11ac8472be..615d32f7ef4 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -6,6 +6,7 @@ obj-y += platform-gpio-mxc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SRTC) += platform-imx_srtc.o
 obj-y += platform-imx-dma.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
@@ -15,9 +16,14 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3) +=  platform-imx_ipuv3.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_TVE) += platform-imx_tve.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_VPU) +=  platform-imx_vpu.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_LDB) += platform-imx_ldb.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_GPU) +=  platform-mxc_gpu.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
@@ -26,4 +32,8 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_IIM)	+= platform-imx-iim.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) +=  platform-ahci-imx.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif-dai.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif-audio.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx-iim.c b/arch/arm/plat-mxc/devices/platform-imx-iim.c
new file mode 100644
index 00000000000..74043ded3c0
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-iim.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx5_iim_data_entry_single(soc)				\
+	{							\
+		.iobase = soc ## _IIM_BASE_ADDR,		\
+		.irq = soc ## _INT_IIM,				\
+	}
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_iim_data imx51_imx_iim_data __initconst =
+			imx5_iim_data_entry_single(MX51);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_iim_data imx53_imx_iim_data __initconst =
+			imx5_iim_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_iim(
+		const struct imx_iim_data *data,
+		const struct mxc_iim_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = data->iobase,
+			.end = data->iobase + SZ_16 - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = data->irq,
+			.end = data->irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device("mxc_iim", 0,
+			res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
+
diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdif-audio.c b/arch/arm/plat-mxc/devices/platform-imx-spdif-audio.c
new file mode 100644
index 00000000000..4a0cb7bf9a1
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-spdif-audio.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_spdif_audio_device(void)
+{
+	return imx_add_platform_device("imx-spdif-audio-device", 0,
+				NULL, 0, NULL, 0);
+}
+
diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdif-dai.c b/arch/arm/plat-mxc/devices/platform-imx-spdif-dai.c
new file mode 100644
index 00000000000..516ebc52467
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-spdif-dai.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define MXC_SPDIF_TX_REG          0x2C
+#define MXC_SPDIF_RX_REG          0x14
+
+#define imx_spdif_dai_data_entry(soc)					\
+	{								\
+		.iobase = soc ## _SPDIF_BASE_ADDR,			\
+		.dmatx = soc ## _DMA_REQ_SPDIF_TX,			\
+		.dmarx = soc ## _DMA_REQ_SPDIF_RX,			\
+	}
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_spdif_dai_data imx51_spdif_dai_data __initconst = {
+		.iobase = MX51_SPDIF_BASE_ADDR,
+		.dmatx = MX51_DMA_REQ_SPDIF,
+	};
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_spdif_dai_data imx53_spdif_dai_data __initconst =
+			imx_spdif_dai_data_entry(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_spdif_dai(
+			const struct imx_spdif_dai_data *data)
+{
+	struct resource res[] = {
+		{
+			.name = "tx_reg",
+			.start = data->iobase + MXC_SPDIF_TX_REG,
+			.end = data->iobase + MXC_SPDIF_TX_REG,
+			.flags = IORESOURCE_DMA,
+		}, {
+			.name = "rx_reg",
+			.start = data->iobase + MXC_SPDIF_RX_REG,
+			.end = data->iobase + MXC_SPDIF_RX_REG,
+			.flags = IORESOURCE_DMA,
+		}, {
+			.name = "tx",
+			.start = data->dmatx,
+			.end = data->dmatx,
+			.flags = IORESOURCE_DMA,
+		}, {
+			.name = "rx",
+			.start = data->dmarx,
+			.end = data->dmarx,
+			.flags = IORESOURCE_DMA,
+		},
+	};
+
+	return imx_add_platform_device("imx-spdif-dai", 0,
+				res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdif.c b/arch/arm/plat-mxc/devices/platform-imx-spdif.c
new file mode 100644
index 00000000000..80a5e782067
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-spdif.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx5_spdif_data_entry_single(soc)			\
+	{							\
+		.iobase = soc ## _SPDIF_BASE_ADDR,		\
+		.irq = soc ## _INT_SPDIF,			\
+	}
+
+#ifdef CONFIG_SOC_IMX50
+const struct imx_spdif_data imx50_imx_spdif_data __initconst =
+			imx5_spdif_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX50 */
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_spdif_data imx51_imx_spdif_data __initconst =
+			imx5_spdif_data_entry_single(MX51);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_spdif_data imx53_imx_spdif_data __initconst =
+			imx5_spdif_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_spdif(
+		const struct imx_spdif_data *data,
+		const struct mxc_spdif_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = data->iobase,
+			.end = data->iobase + 0x50,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = data->irq,
+			.end = data->irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device("mxc_spdif", 0,
+			res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
+
diff --git a/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c b/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c
new file mode 100644
index 00000000000..a353060bc95
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+
+#define imx5_ipuv3_data_entry_single(soc, size, ipu_init, ipu_pg)	\
+	{								\
+		.iobase = soc ## _IPU_CTRL_BASE_ADDR,			\
+		.irq_err = soc ## _INT_IPU_ERR,				\
+		.irq = soc ## _INT_IPU_SYN,				\
+		.irq_start = MXC_IPU_IRQ_START, 			\
+		.iosize = size,						\
+		.init = ipu_init,					\
+		.pg = ipu_pg,						\
+	}
+
+#define imx6_ipuv3_data_entry_single(soc, id, size, ipu_init, ipu_pg)	\
+	{								\
+		.iobase = soc ## _IPU ## id ## _ARB_BASE_ADDR,			\
+		.irq_err = soc ## _INT_IPU ## id ## _ERR,			\
+		.irq = soc ## _INT_IPU ## id ## _SYN,				\
+		.irq_start = MXC_IPU_IRQ_START, 			\
+		.iosize = size,						\
+		.init = ipu_init,					\
+		.pg = ipu_pg,						\
+	}
+
+#ifdef CONFIG_SOC_IMX51
+/*
+ * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
+ * the Freescale marketing division. However this did not remove the
+ * hardware from the chip which still needs to be configured...
+ */
+static int __init ipu_mipi_setup(void)
+{
+	struct clk *hsc_clk;
+	void __iomem *hsc_addr;
+	int ret = 0;
+
+	hsc_addr = ioremap(MX51_MIPI_HSC_BASE_ADDR, PAGE_SIZE);
+	if (!hsc_addr)
+		return -ENOMEM;
+
+	hsc_clk = clk_get_sys(NULL, "mipi_hsp");
+	if (IS_ERR(hsc_clk)) {
+		ret = PTR_ERR(hsc_clk);
+		goto unmap;
+	}
+	clk_enable(hsc_clk);
+
+	/* setup MIPI module to legacy mode */
+	writel(0xF00, hsc_addr);
+
+	/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
+	writel(readl(hsc_addr + 0x800) | 0x30ff,
+			hsc_addr + 0x800);
+
+	clk_disable(hsc_clk);
+	clk_put(hsc_clk);
+unmap:
+	iounmap(hsc_addr);
+
+	return ret;
+}
+
+int __init mx51_ipuv3_init(int id)
+{
+	int ret = 0;
+	u32 val;
+
+	ret = ipu_mipi_setup();
+
+	/* hard reset the IPU */
+	val = readl(MX51_IO_ADDRESS(MX51_SRC_BASE_ADDR));
+	val |= 1 << 3;
+	writel(val, MX51_IO_ADDRESS(MX51_SRC_BASE_ADDR));
+
+	return ret;
+}
+
+void mx51_ipuv3_pg(int enable)
+{
+	if (enable) {
+		writel(MXC_PGCR_PCR, MX51_PGC_IPU_PGCR);
+		writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR);
+	} else {
+		writel(0x0, MX51_PGC_IPU_PGCR);
+		if (readl(MX51_PGC_IPU_PGSR) & MXC_PGSR_PSR)
+			printk(KERN_DEBUG "power gating successful\n");
+		writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR);
+	}
+}
+
+const struct imx_ipuv3_data imx51_ipuv3_data __initconst =
+			imx5_ipuv3_data_entry_single(MX51, SZ_512M,
+					mx51_ipuv3_init, mx51_ipuv3_pg);
+#endif
+
+#ifdef CONFIG_SOC_IMX53
+int __init mx53_ipuv3_init(int id)
+{
+	int ret = 0;
+	u32 val;
+
+	/* hard reset the IPU */
+	val = readl(MX53_IO_ADDRESS(MX53_SRC_BASE_ADDR));
+	val |= 1 << 3;
+	writel(val, MX53_IO_ADDRESS(MX53_SRC_BASE_ADDR));
+
+	return ret;
+}
+
+void mx53_ipuv3_pg(int enable)
+{
+	if (enable) {
+		writel(MXC_PGCR_PCR, MX53_PGC_IPU_PGCR);
+		writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR);
+	} else {
+		writel(0x0, MX53_PGC_IPU_PGCR);
+		if (readl(MX53_PGC_IPU_PGSR) & MXC_PGSR_PSR)
+			printk(KERN_DEBUG "power gating successful\n");
+		writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR);
+	}
+}
+
+const struct imx_ipuv3_data imx53_ipuv3_data __initconst =
+			imx5_ipuv3_data_entry_single(MX53, SZ_128M,
+					mx53_ipuv3_init, mx53_ipuv3_pg);
+#endif
+
+#ifdef CONFIG_SOC_IMX6Q
+int __init mx6q_ipuv3_init(int id)
+{
+	int ret = 0;
+	u32 val;
+
+	/* hard reset the IPU */
+	val = readl(MX6_IO_ADDRESS(SRC_BASE_ADDR));
+	if (id == 0)
+		val |= 1 << 3;
+	else
+		val |= 1 << 12;
+	writel(val, MX6_IO_ADDRESS(SRC_BASE_ADDR));
+
+	return ret;
+}
+
+void mx6q_ipuv3_pg(int enable)
+{
+	/*TODO*/
+}
+
+const struct imx_ipuv3_data imx6q_ipuv3_data[] __initconst = {
+	imx6_ipuv3_data_entry_single(MX6Q, 1, SZ_4M,
+			mx6q_ipuv3_init, mx6q_ipuv3_pg),
+	imx6_ipuv3_data_entry_single(MX6Q, 2, SZ_4M,
+			mx6q_ipuv3_init, mx6q_ipuv3_pg),
+};
+#endif
+
+struct platform_device *__init imx_add_ipuv3(
+		const int id,
+		const struct imx_ipuv3_data *data,
+		struct imx_ipuv3_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = data->iobase,
+			.end = data->iobase + data->iosize - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = data->irq_err,
+			.end = data->irq_err,
+			.flags = IORESOURCE_IRQ,
+		}, {
+			.start = data->irq,
+			.end = data->irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	pdata->init = data->init;
+	pdata->pg = data->pg;
+
+	return imx_add_platform_device_dmamask("imx-ipuv3", id,
+			res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
+			DMA_BIT_MASK(32));
+}
+
+struct platform_device *__init imx_add_ipuv3_fb(
+		const int id,
+		const struct ipuv3_fb_platform_data *pdata)
+{
+	if (pdata->res_size > 0) {
+		struct resource res[] = {
+			{
+				.start = pdata->res_base,
+				.end = pdata->res_base + pdata->res_size - 1,
+				.flags = IORESOURCE_MEM,
+			},
+		};
+
+		return imx_add_platform_device_dmamask("mxc_sdc_fb",
+				id, res, ARRAY_SIZE(res), pdata,
+				sizeof(*pdata), DMA_BIT_MASK(32));
+	} else
+		return imx_add_platform_device_dmamask("mxc_sdc_fb", id,
+				NULL, 0, pdata, sizeof(*pdata),
+				DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_ldb.c b/arch/arm/plat-mxc/devices/platform-imx_ldb.c
new file mode 100644
index 00000000000..0269a8165b2
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_ldb.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#include <linux/clk.h>
+
+#define imx_ldb_data_entry_single(soc, size)	\
+	{								\
+		.iobase = soc ## _IOMUXC_BASE_ADDR,			\
+		.iosize = size,						\
+	}
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_ldb_data imx53_ldb_data __initconst =
+			imx_ldb_data_entry_single(MX53, SZ_4K);
+#endif
+
+#ifdef CONFIG_SOC_IMX6Q
+const struct imx_ldb_data imx6q_ldb_data __initconst =
+			imx_ldb_data_entry_single(MX6Q, SZ_4K);
+#endif
+
+struct platform_device *__init imx_add_ldb(
+		const struct imx_ldb_data *data,
+		struct fsl_mxc_ldb_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = data->iobase,
+			.end = data->iobase + data->iosize - 1,
+			.flags = IORESOURCE_MEM,
+		},
+	};
+
+	return imx_add_platform_device("mxc_ldb", -1,
+			res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_srtc.c b/arch/arm/plat-mxc/devices/platform-imx_srtc.c
new file mode 100644
index 00000000000..9e4191ecd52
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_srtc.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imx_srtc_data_entry_single(soc)				\
+	{								\
+		.iobase = soc ## _SRTC_BASE_ADDR,			\
+		.irq = soc ## _INT_SRTC_NTZ,				\
+	}
+
+#ifdef CONFIG_SOC_IMX50
+const struct imx_srtc_data imx50_imx_srtc_data __initconst =
+	imx_imx_srtc_data_entry_single(MX50);
+#endif /* ifdef CONFIG_SOC_IMX50 */
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_srtc_data imx51_imx_srtc_data __initconst =
+	imx_imx_srtc_data_entry_single(MX51);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_srtc_data imx53_imx_srtc_data __initconst =
+	imx_imx_srtc_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_srtc(
+		const struct imx_srtc_data *data)
+{
+	struct resource res[] = {
+		{
+			.start = data->iobase,
+			.end = data->iobase + SZ_16K - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = data->irq,
+			.end = data->irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device("mxc_rtc", 0,
+			res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_tve.c b/arch/arm/plat-mxc/devices/platform-imx_tve.c
new file mode 100644
index 00000000000..7ab501a605c
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_tve.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Jason Chen <jason.chen@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx5_tve_data_entry_single(soc)				\
+	{							\
+		.iobase = soc ## _TVE_BASE_ADDR,		\
+		.irq = soc ## _INT_TVE,				\
+	}
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_tve_data imx51_tve_data __initconst =
+			imx5_tve_data_entry_single(MX51);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_tve_data imx53_tve_data __initconst =
+			imx5_tve_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_tve(
+		const struct imx_tve_data *data,
+		const struct fsl_mxc_tve_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = data->iobase,
+			.end = data->iobase + SZ_4K - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = data->irq,
+			.end = data->irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device("mxc_tve", -1,
+			res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_vpu.c b/arch/arm/plat-mxc/devices/platform-imx_vpu.c
new file mode 100644
index 00000000000..a3a3927e535
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_vpu.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Jason Chen <jason.chen@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx5_vpu_data_entry_single(soc, flag, size, vpu_reset, vpu_pg)	\
+	{							\
+		.iobase = soc ## _VPU_BASE_ADDR,		\
+		.irq_ipi = soc ## _INT_VPU,			\
+		.iram_enable = flag,				\
+		.iram_size = size,				\
+		.reset = vpu_reset,				\
+		.pg = vpu_pg,					\
+	}
+
+#define imx6_vpu_data_entry_single(soc, flag, size, vpu_reset, vpu_pg)  \
+	{                                                       \
+		.iobase = soc ## _VPU_BASE_ADDR,                \
+		.irq_ipi = soc ## _INT_VPU_IPI,                 \
+		.irq_jpg = soc ## _INT_VPU_JPG,			\
+		.iram_enable = flag,                            \
+		.iram_size = size,                              \
+		.reset = vpu_reset,                             \
+		.pg = vpu_pg,                                   \
+	}
+
+#ifdef CONFIG_SOC_IMX51
+void mx51_vpu_reset(void)
+{
+	u32 reg;
+	void __iomem *src_base;
+
+	src_base = ioremap(MX51_SRC_BASE_ADDR, PAGE_SIZE);
+
+	/* mask interrupt due to vpu passed reset */
+	reg = __raw_readl(src_base + 0x18);
+	reg |= 0x02;
+	__raw_writel(reg, src_base + 0x18);
+
+	reg = __raw_readl(src_base);
+	reg |= 0x5;    /* warm reset vpu */
+	__raw_writel(reg, src_base);
+	while (__raw_readl(src_base) & 0x04)
+		;
+
+	iounmap(src_base);
+}
+
+void mx51_vpu_pg(int enable)
+{
+	if (enable) {
+		__raw_writel(MXC_PGCR_PCR, MX51_PGC_VPU_PGCR);
+		__raw_writel(MXC_PGSR_PSR, MX51_PGC_VPU_PGSR);
+	} else {
+		__raw_writel(0x0, MX51_PGC_VPU_PGCR);
+		if (__raw_readl(MX51_PGC_VPU_PGSR) & MXC_PGSR_PSR)
+			printk(KERN_DEBUG "power gating successful\n");
+		__raw_writel(MXC_PGSR_PSR, MX51_PGC_VPU_PGSR);
+	}
+}
+const struct imx_vpu_data imx51_vpu_data __initconst =
+			imx5_vpu_data_entry_single(MX51,
+			false, 0x14000, mx51_vpu_reset, mx51_vpu_pg);
+#endif
+
+#ifdef CONFIG_SOC_IMX53
+void mx53_vpu_reset(void)
+{
+	u32 reg;
+	void __iomem *src_base;
+
+	src_base = ioremap(MX53_SRC_BASE_ADDR, PAGE_SIZE);
+
+	/* mask interrupt due to vpu passed reset */
+	reg = __raw_readl(src_base + 0x18);
+	reg |= 0x02;
+	__raw_writel(reg, src_base + 0x18);
+
+	reg = __raw_readl(src_base);
+	reg |= 0x5;    /* warm reset vpu */
+	__raw_writel(reg, src_base);
+	while (__raw_readl(src_base) & 0x04)
+		;
+
+	iounmap(src_base);
+}
+
+void mx53_vpu_pg(int enable)
+{
+	if (enable) {
+		__raw_writel(MXC_PGCR_PCR, MX53_PGC_VPU_PGCR);
+		__raw_writel(MXC_PGSR_PSR, MX53_PGC_VPU_PGSR);
+	} else {
+		__raw_writel(0x0, MX53_PGC_VPU_PGCR);
+		if (__raw_readl(MX53_PGC_VPU_PGSR) & MXC_PGSR_PSR)
+			printk(KERN_DEBUG "power gating successful\n");
+		__raw_writel(MXC_PGSR_PSR, MX53_PGC_VPU_PGSR);
+	}
+}
+
+const struct imx_vpu_data imx53_vpu_data __initconst =
+			imx5_vpu_data_entry_single(MX53,
+			true, 0x14000, mx53_vpu_reset, mx53_vpu_pg);
+#endif
+
+#ifdef CONFIG_SOC_IMX6Q
+const struct imx_vpu_data imx6q_vpu_data __initconst =
+			imx6_vpu_data_entry_single(MX6Q,
+			true, 0x21000, NULL, NULL);
+#endif
+
+struct platform_device *__init imx_add_vpu(
+		const struct imx_vpu_data *data)
+{
+	struct mxc_vpu_platform_data pdata;
+	struct resource res[] = {
+		{
+			.start = data->iobase,
+			.end = data->iobase + SZ_16K - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = data->irq_ipi,
+			.end = data->irq_ipi,
+			.flags = IORESOURCE_IRQ,
+		},
+#ifdef CONFIG_SOC_IMX6Q
+		{
+			.start = data->irq_jpg,
+			.end = data->irq_jpg,
+			.flags = IORESOURCE_IRQ,
+		},
+#endif
+	};
+
+	pdata.reset = data->reset;
+	pdata.pg = data->pg;
+	pdata.iram_enable = data->iram_enable;
+	pdata.iram_size = data->iram_size;
+
+	return imx_add_platform_device("mxc_vpu", -1,
+			res, ARRAY_SIZE(res), &pdata, sizeof(pdata));
+}
+
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_gpu.c b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c
new file mode 100644
index 00000000000..6b0b48b0197
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/dma-mapping.h>
+
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mxc_gpu_entry_3d_2d(soc)					\
+	{								\
+		.irq_3d = soc ## _INT_GPU,				\
+		.irq_2d = soc ## _INT_GPU2_IRQ,				\
+		.iobase_3d = soc ## _GPU_BASE_ADDR,			\
+		.iobase_2d = soc ## _GPU2D_BASE_ADDR,			\
+		.gmem_base = soc ## _GPU_GMEM_BASE_ADDR,		\
+		.gmem_size = soc ## _GPU_GMEM_SIZE,			\
+	}
+
+#define imx_mxc_gpu_entry_2d(soc)					\
+	{								\
+		.irq_2d = soc ## _INT_GPU2_IRQ,				\
+		.iobase_2d = soc ## _GPU2D_BASE_ADDR,			\
+	}
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_mxc_gpu_data imx35_gpu_data __initconst =
+	imx_mxc_gpu_entry_2d(MX35);
+#endif
+
+#ifdef CONFIG_SOC_IMX50
+const struct imx_mxc_gpu_data imx50_gpu_data __initconst =
+	imx_mxc_gpu_entry_2d(MX50);
+#endif
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_mxc_gpu_data imx51_gpu_data __initconst =
+	imx_mxc_gpu_entry_3d_2d(MX51);
+#endif
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_mxc_gpu_data imx53_gpu_data __initconst =
+	imx_mxc_gpu_entry_3d_2d(MX53);
+#endif
+
+struct platform_device *__init imx_add_mxc_gpu(
+		const struct imx_mxc_gpu_data *data,
+		const struct mxc_gpu_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = data->irq_2d,
+			.end = data->irq_2d,
+			.name = "gpu_2d_irq",
+			.flags = IORESOURCE_IRQ,
+		},
+		{
+			.start = data->irq_3d,
+			.end = data->irq_3d,
+			.name = "gpu_3d_irq",
+			.flags = IORESOURCE_IRQ,
+		},
+		{
+			.start = data->iobase_2d,
+			.end = data->iobase_2d + SZ_4K - 1,
+			.name = "gpu_2d_registers",
+			.flags = IORESOURCE_MEM,
+		},
+		{
+			.start = data->iobase_3d,
+			.end = data->iobase_3d + SZ_128K - 1,
+			.name = "gpu_3d_registers",
+			.flags = IORESOURCE_MEM,
+		},
+		{
+			.start = data->gmem_base,
+			.end = data->gmem_base + data->gmem_size - 1,
+			.name = "gpu_graphics_mem",
+			.flags = IORESOURCE_MEM,
+		},
+	};
+
+	return imx_add_platform_device_dmamask("mxc_gpu", 0,
+			res, ARRAY_SIZE(res),
+			pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
index b0c4ae29811..18cfd07ab41 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
@@ -49,6 +49,15 @@ const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
+#ifdef CONFIG_SOC_IMX53
+const struct imx_mxc_pwm_data imx53_mxc_pwm_data[] __initconst = {
+#define imx53_mxc_pwm_data_entry(_id, _hwid)				\
+	imx_mxc_pwm_data_entry(MX53, _id, _hwid, SZ_16K)
+	imx53_mxc_pwm_data_entry(0, 1),
+	imx53_mxc_pwm_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
 struct platform_device *__init imx_add_mxc_pwm(
 		const struct imx_mxc_pwm_data *data)
 {
diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
new file mode 100644
index 00000000000..6f6e9c59e2f
--- /dev/null
+++ b/arch/arm/plat-mxc/dvfs_core.c
@@ -0,0 +1,994 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file dvfs_core.c
+ *
+ * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module.
+ *
+ * Upon initialization, the DVFS driver initializes the DVFS hardware
+ * sets up driver nodes attaches to the DVFS interrupt and initializes internal
+ * data structures. When the DVFS interrupt occurs the driver checks the cause
+ * of the interrupt (lower frequency, increase frequency or emergency) and
+ * changes the CPU voltage according to translation table that is loaded into
+ * the driver.
+ *
+ * @ingroup PM
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/device.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <linux/cpufreq.h>
+#include <mach/hardware.h>
+#include <mach/mxc_dvfs.h>
+
+#define MXC_DVFSTHRS_UPTHR_MASK               0x0FC00000
+#define MXC_DVFSTHRS_UPTHR_OFFSET             22
+#define MXC_DVFSTHRS_DNTHR_MASK               0x003F0000
+#define MXC_DVFSTHRS_DNTHR_OFFSET             16
+#define MXC_DVFSTHRS_PNCTHR_MASK              0x0000003F
+#define MXC_DVFSTHRS_PNCTHR_OFFSET            0
+
+#define MXC_DVFSCOUN_DNCNT_MASK               0x00FF0000
+#define MXC_DVFSCOUN_DNCNT_OFFSET             16
+#define MXC_DVFSCOUN_UPCNT_MASK              0x000000FF
+#define MXC_DVFSCOUN_UPCNT_OFFSET            0
+
+#define MXC_DVFSEMAC_EMAC_MASK               0x000001FF
+#define MXC_DVFSEMAC_EMAC_OFFSET             0
+
+#define MXC_DVFSCNTR_DVFEV                   0x10000000
+#define MXC_DVFSCNTR_LBMI                    0x08000000
+#define MXC_DVFSCNTR_LBFL                    0x06000000
+#define MXC_DVFSCNTR_DVFIS                   0x01000000
+#define MXC_DVFSCNTR_FSVAIM                  0x00400000
+#define MXC_DVFSCNTR_FSVAI_MASK              0x00300000
+#define MXC_DVFSCNTR_FSVAI_OFFSET            20
+#define MXC_DVFSCNTR_WFIM                    0x00080000
+#define MXC_DVFSCNTR_WFIM_OFFSET             19
+#define MXC_DVFSCNTR_MAXF_MASK               0x00040000
+#define MXC_DVFSCNTR_MAXF_OFFSET             18
+#define MXC_DVFSCNTR_MINF_MASK               0x00020000
+#define MXC_DVFSCNTR_MINF_OFFSET             17
+#define MXC_DVFSCNTR_LTBRSR_MASK             0x00000018
+#define MXC_DVFSCNTR_LTBRSR_OFFSET           3
+#define MXC_DVFSCNTR_DVFEN                   0x00000001
+
+#define CCM_CDCR_SW_DVFS_EN			0x20
+#define CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER		0x4
+
+int dvfs_core_is_active;
+extern void setup_pll(void);
+static struct mxc_dvfs_platform_data *dvfs_data;
+static struct device *dvfs_dev;
+static struct cpu_op *cpu_op_tbl;
+int dvfs_core_resume;
+int curr_op;
+int old_op;
+
+int cpufreq_trig_needed;
+struct timeval core_prev_intr;
+
+void dump_dvfs_core_regs(void);
+void stop_dvfs(void);
+static struct delayed_work dvfs_core_handler;
+
+/*
+ * Clock structures
+ */
+static struct clk *pll1_sw_clk;
+static struct clk *cpu_clk;
+static struct clk *dvfs_clk;
+static struct regulator *core_regulator;
+
+extern int cpu_op_nr;
+#ifdef CONFIG_ARCH_MX5
+extern struct cpu_op *(*get_cpu_op)(int *op);
+#endif
+
+enum {
+	FSVAI_FREQ_NOCHANGE = 0x0,
+	FSVAI_FREQ_INCREASE,
+	FSVAI_FREQ_DECREASE,
+	FSVAI_FREQ_EMERG,
+};
+
+/*
+ * Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add; 2 for after EMA
+ */
+#define DVFS_LTBRSR		(2 << MXC_DVFSCNTR_LTBRSR_OFFSET)
+
+extern struct dvfs_wp dvfs_core_setpoint[4];
+extern int low_bus_freq_mode;
+extern int high_bus_freq_mode;
+extern int set_low_bus_freq(void);
+extern int set_high_bus_freq(int high_bus_speed);
+extern int low_freq_bus_used(void);
+
+DEFINE_SPINLOCK(mxc_dvfs_core_lock);
+
+static void dvfs_load_config(int set_point)
+{
+	u32 reg;
+	reg = 0;
+
+	reg |= dvfs_core_setpoint[set_point].upthr << MXC_DVFSTHRS_UPTHR_OFFSET;
+	reg |= dvfs_core_setpoint[set_point].downthr <<
+	    MXC_DVFSTHRS_DNTHR_OFFSET;
+	reg |= dvfs_core_setpoint[set_point].panicthr;
+	__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_THRS);
+
+	reg = 0;
+	reg |= dvfs_core_setpoint[set_point].downcnt <<
+	    MXC_DVFSCOUN_DNCNT_OFFSET;
+	reg |= dvfs_core_setpoint[set_point].upcnt << MXC_DVFSCOUN_UPCNT_OFFSET;
+	__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_COUN);
+
+	/* Set EMAC value */
+	__raw_writel((dvfs_core_setpoint[set_point].emac <<
+					MXC_DVFSEMAC_EMAC_OFFSET),
+					dvfs_data->membase
+					+ MXC_DVFSCORE_EMAC);
+
+
+}
+
+static int set_cpu_freq(int op)
+{
+	int arm_podf;
+	int podf;
+	int vinc = 0;
+	int ret = 0;
+	int org_cpu_rate;
+	unsigned long rate = 0;
+	int gp_volt = 0;
+	u32 reg;
+	u32 reg1;
+	u32 en_sw_dvfs = 0;
+	unsigned long flags;
+
+	if (cpu_op_tbl[op].pll_rate != cpu_op_tbl[old_op].pll_rate) {
+		org_cpu_rate = clk_get_rate(cpu_clk);
+		rate = cpu_op_tbl[op].cpu_rate;
+
+		if (org_cpu_rate == rate)
+			return ret;
+
+		gp_volt = cpu_op_tbl[op].cpu_voltage;
+		if (gp_volt == 0)
+			return ret;
+
+		/*Set the voltage for the GP domain. */
+		if (rate > org_cpu_rate) {
+			ret = regulator_set_voltage(core_regulator, gp_volt,
+						    gp_volt);
+			if (ret < 0) {
+				printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE\n");
+				return ret;
+			}
+			udelay(dvfs_data->delay_time);
+		}
+		spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
+		/* PLL_RELOCK, set ARM_FREQ_SHIFT_DIVIDER */
+		reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+		/* Check if software_dvfs_en bit set */
+		if ((reg & CCM_CDCR_SW_DVFS_EN) != 0)
+			en_sw_dvfs = CCM_CDCR_SW_DVFS_EN;
+		else
+			en_sw_dvfs = 0x0;
+		reg &= ~(CCM_CDCR_SW_DVFS_EN);
+		reg &= 0xFFFFFFFB;
+		__raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+
+		setup_pll();
+		/* START the GPC main control FSM */
+		/* set VINC */
+		reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
+		reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
+			 MXC_GPCVCR_VCNT_MASK);
+
+		if (rate > org_cpu_rate)
+			reg |= 1 << MXC_GPCVCR_VINC_OFFSET;
+
+		reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
+		       (1 << MXC_GPCVCR_VCNT_OFFSET);
+		__raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
+
+		reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+		reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK);
+		reg |= MXC_GPCCNTR_FUPD;
+		reg |= MXC_GPCCNTR_ADU;
+		__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+		reg |= MXC_GPCCNTR_STRT;
+		__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+		while (__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
+				& 0x4000)
+			udelay(10);
+		spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
+
+		if (rate < org_cpu_rate) {
+			ret = regulator_set_voltage(core_regulator,
+						    gp_volt, gp_volt);
+			if (ret < 0) {
+				printk(KERN_DEBUG
+				       "COULD NOT SET GP VOLTAGE!!!!\n");
+				return ret;
+			}
+			udelay(dvfs_data->delay_time);
+		}
+		/* set software_dvfs_en bit back to original setting*/
+		reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+		reg &= ~(CCM_CDCR_SW_DVFS_EN);
+		reg |= en_sw_dvfs;
+		clk_set_rate(cpu_clk, rate);
+	} else {
+		podf = cpu_op_tbl[op].cpu_podf;
+		gp_volt = cpu_op_tbl[op].cpu_voltage;
+
+		/* Change arm_podf only */
+		/* set ARM_FREQ_SHIFT_DIVIDER */
+		reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+
+		/* Check if software_dvfs_en bit set */
+		if ((reg & CCM_CDCR_SW_DVFS_EN) != 0)
+			en_sw_dvfs = CCM_CDCR_SW_DVFS_EN;
+		else
+			en_sw_dvfs = 0x0;
+
+		reg &= ~(CCM_CDCR_SW_DVFS_EN | CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER);
+		reg |= CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER;
+		__raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+
+		/* Get ARM_PODF */
+		reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset);
+		arm_podf = reg & 0x07;
+		if (podf == arm_podf) {
+			printk(KERN_DEBUG
+			       "No need to change freq and voltage!!!!\n");
+			return 0;
+		}
+
+		/* Check if FSVAI indicate freq up */
+		if (podf < arm_podf) {
+			ret = regulator_set_voltage(core_regulator,
+						    gp_volt, gp_volt);
+			if (ret < 0) {
+				printk(KERN_DEBUG
+				       "COULD NOT SET GP VOLTAGE!!!!\n");
+				return 0;
+			}
+			udelay(dvfs_data->delay_time);
+			vinc = 1;
+		} else {
+			vinc = 0;
+		}
+
+		arm_podf = podf;
+		/* Set ARM_PODF */
+		reg &= 0xFFFFFFF8;
+		reg |= arm_podf;
+		spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
+
+		reg1 = __raw_readl(ccm_base + dvfs_data->ccm_cdhipr_offset);
+		if ((reg1 & 0x00010000) == 0)
+			__raw_writel(reg,
+				ccm_base + dvfs_data->ccm_cacrr_offset);
+		else {
+			printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n");
+			return 0;
+		}
+		/* set VINC */
+		reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
+		reg &=
+		    ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
+		      MXC_GPCVCR_VCNT_MASK);
+		reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
+		    (100 << MXC_GPCVCR_VCNT_OFFSET) |
+		    (vinc << MXC_GPCVCR_VINC_OFFSET);
+		__raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
+
+		reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+		reg &= (~(MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD
+				| MXC_GPCCNTR_STRT));
+		__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+		reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+		reg |= MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD;
+		__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+		reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+		reg |= MXC_GPCCNTR_STRT;
+		__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+		/* Wait for arm podf Enable */
+		while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) &
+			MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) {
+			printk(KERN_DEBUG "Waiting arm_podf enabled!\n");
+			udelay(10);
+		}
+		spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
+
+		if (vinc == 0) {
+			ret = regulator_set_voltage(core_regulator,
+						    gp_volt, gp_volt);
+			if (ret < 0) {
+				printk(KERN_DEBUG
+				       "COULD NOT SET GP VOLTAGE!!!!\n");
+				return ret;
+			}
+			udelay(dvfs_data->delay_time);
+		}
+
+		/* Clear the ARM_FREQ_SHIFT_DIVIDER and */
+		/* set software_dvfs_en bit back to original setting*/
+		reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+		reg &= ~(CCM_CDCR_SW_DVFS_EN | CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER);
+		reg |= en_sw_dvfs;
+		__raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+	}
+#if defined(CONFIG_CPU_FREQ)
+		cpufreq_trig_needed = 1;
+#endif
+	old_op = op;
+	return ret;
+}
+
+static int start_dvfs(void)
+{
+	u32 reg, cpu_rate;
+	unsigned long flags;
+
+	if (dvfs_core_is_active)
+		return 0;
+
+	spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
+
+	clk_enable(dvfs_clk);
+
+	dvfs_load_config(0);
+
+	/* get current working point */
+	cpu_rate = clk_get_rate(cpu_clk);
+	curr_op = cpu_op_nr - 1;
+	do {
+		if (cpu_rate <= cpu_op_tbl[curr_op].cpu_rate)
+			break;
+	} while (--curr_op >= 0);
+	old_op = curr_op;
+	/* config reg GPC_CNTR */
+	reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+
+	reg &= ~MXC_GPCCNTR_GPCIRQM;
+	/* GPCIRQ=1, select ARM IRQ */
+	reg |= MXC_GPCCNTR_GPCIRQ_ARM;
+	/* ADU=1, select ARM domain */
+	reg |= MXC_GPCCNTR_ADU;
+	__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+	/* Set PREDIV bits */
+	reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+	reg = (reg & ~(dvfs_data->prediv_mask));
+	reg |= (dvfs_data->prediv_val) << (dvfs_data->prediv_offset);
+	__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+
+	/* Enable DVFS interrupt */
+	reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+	/* FSVAIM=0 */
+	reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
+	/* Set MAXF, MINF */
+	reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK));
+	reg |= 1 << MXC_DVFSCNTR_MAXF_OFFSET;
+	/* Select ARM domain */
+	reg |= MXC_DVFSCNTR_DVFIS;
+	/* Enable DVFS frequency adjustment interrupt */
+	reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
+	/* Set load tracking buffer register source */
+	reg = (reg & ~MXC_DVFSCNTR_LTBRSR_MASK);
+	reg |= DVFS_LTBRSR;
+	/* Set DIV3CK */
+	reg = (reg & ~(dvfs_data->div3ck_mask));
+	reg |= (dvfs_data->div3ck_val) << (dvfs_data->div3ck_offset);
+	__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+
+	/* Enable DVFS */
+	reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+	reg |= MXC_DVFSCNTR_DVFEN;
+	__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+
+	dvfs_core_is_active = 1;
+
+	spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
+
+	printk(KERN_DEBUG "DVFS is started\n");
+
+	return 0;
+}
+
+/*!
+ * This function is called for module initialization.
+ * It sets up the DVFS hardware.
+ * It sets default values for DVFS thresholds and counters. The default
+ * values was chosen from a set of different reasonable values. They was tested
+ * and the default values in the driver gave the best results.
+ * More work should be done to find optimal values.
+ *
+ * @return   0 if successful; non-zero otherwise.
+ *
+ */
+static int init_dvfs_controller(void)
+{
+	/* DVFS loading config */
+	dvfs_load_config(0);
+
+	return 0;
+}
+
+static irqreturn_t dvfs_irq(int irq, void *dev_id)
+{
+	u32 reg;
+
+	/* Check if DVFS0 (ARM) id requesting for freqency/voltage update */
+	if ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
+			& MXC_GPCCNTR_DVFS0CR) == 0)
+		return IRQ_NONE;
+
+	/* Mask DVFS irq */
+	reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+	/* FSVAIM=1 */
+	reg |= MXC_DVFSCNTR_FSVAIM;
+	__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+
+	/* Mask GPC1 irq */
+	reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+	reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000;
+	__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+	schedule_delayed_work(&dvfs_core_handler, 0);
+	return IRQ_HANDLED;
+}
+
+static void dvfs_core_work_handler(struct work_struct *work)
+{
+	u32 fsvai;
+	u32 reg;
+	u32 curr_cpu;
+	int ret = 0;
+	int maxf = 0, minf = 0;
+	int low_freq_bus_ready = 0;
+	int bus_incr = 0, cpu_dcr = 0;
+
+	low_freq_bus_ready = low_freq_bus_used();
+
+	/* Check DVFS frequency adjustment interrupt status */
+	reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+	fsvai = (reg & MXC_DVFSCNTR_FSVAI_MASK) >> MXC_DVFSCNTR_FSVAI_OFFSET;
+	/* Check FSVAI, FSVAI=0 is error */
+	if (fsvai == FSVAI_FREQ_NOCHANGE) {
+		/* Do nothing. Freq change is not required */
+		goto END;
+	}
+	curr_cpu = clk_get_rate(cpu_clk);
+	/* If FSVAI indicate freq down,
+	   check arm-clk is not in lowest frequency 200 MHz */
+	if (fsvai == FSVAI_FREQ_DECREASE) {
+		if (curr_cpu == cpu_op_tbl[cpu_op_nr - 1].cpu_rate) {
+			minf = 1;
+			if (low_bus_freq_mode)
+				goto END;
+		} else {
+			/* freq down */
+			curr_op++;
+			if (curr_op >= cpu_op_nr) {
+				curr_op = cpu_op_nr - 1;
+				goto END;
+			}
+
+			if (curr_op == cpu_op_nr - 1 && !low_freq_bus_ready) {
+				minf = 1;
+				dvfs_load_config(1);
+			} else {
+				cpu_dcr = 1;
+			}
+		}
+	} else {
+		if (curr_cpu == cpu_op_tbl[0].cpu_rate) {
+			maxf = 1;
+			goto END;
+		} else {
+			if (!high_bus_freq_mode && !cpu_is_mx50()) {
+				/* bump up LP freq first. */
+				bus_incr = 1;
+				dvfs_load_config(2);
+			} else {
+				/* freq up */
+				curr_op = 0;
+				maxf = 1;
+				dvfs_load_config(0);
+			}
+		}
+	}
+
+	low_freq_bus_ready = low_freq_bus_used();
+	if ((curr_op == cpu_op_nr - 1) && (!low_bus_freq_mode)
+	    && (low_freq_bus_ready) && !bus_incr) {
+		if (cpu_dcr)
+			ret = set_cpu_freq(curr_op);
+		if (!cpu_dcr) {
+			set_low_bus_freq();
+			dvfs_load_config(3);
+		} else {
+			dvfs_load_config(2);
+			cpu_dcr = 0;
+		}
+	} else {
+		if (!high_bus_freq_mode)
+			set_high_bus_freq(1);
+		if (!bus_incr)
+			ret = set_cpu_freq(curr_op);
+		bus_incr = 0;
+	}
+
+
+END:	/* Set MAXF, MINF */
+	reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+	reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK));
+	reg |= maxf << MXC_DVFSCNTR_MAXF_OFFSET;
+	reg |= minf << MXC_DVFSCNTR_MINF_OFFSET;
+
+	/* Enable DVFS interrupt */
+	/* FSVAIM=0 */
+	reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
+	reg |= FSVAI_FREQ_NOCHANGE;
+	/* LBFL=1 */
+	reg = (reg & ~MXC_DVFSCNTR_LBFL);
+	reg |= MXC_DVFSCNTR_LBFL;
+	__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+	/*Unmask GPC1 IRQ */
+	reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+	reg &= ~MXC_GPCCNTR_GPCIRQM;
+	__raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+#if defined(CONFIG_CPU_FREQ)
+	if (cpufreq_trig_needed == 1) {
+		cpufreq_trig_needed = 0;
+		cpufreq_update_policy(0);
+	}
+#endif
+}
+
+
+/*!
+ * This function disables the DVFS module.
+ */
+void stop_dvfs(void)
+{
+	u32 reg = 0;
+	unsigned long flags;
+	u32 curr_cpu;
+
+	if (dvfs_core_is_active) {
+
+		/* Mask dvfs irq, disable DVFS */
+		reg = __raw_readl(dvfs_data->membase
+				  + MXC_DVFSCORE_CNTR);
+		/* FSVAIM=1 */
+		reg |= MXC_DVFSCNTR_FSVAIM;
+		__raw_writel(reg, dvfs_data->membase
+				  + MXC_DVFSCORE_CNTR);
+
+		curr_op = 0;
+		if (!high_bus_freq_mode)
+			set_high_bus_freq(1);
+
+		curr_cpu = clk_get_rate(cpu_clk);
+		if (curr_cpu != cpu_op_tbl[curr_op].cpu_rate) {
+			set_cpu_freq(curr_op);
+#if defined(CONFIG_CPU_FREQ)
+			if (cpufreq_trig_needed == 1) {
+				cpufreq_trig_needed = 0;
+				cpufreq_update_policy(0);
+			}
+#endif
+		}
+		spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
+
+		reg = __raw_readl(dvfs_data->membase
+				  + MXC_DVFSCORE_CNTR);
+		reg = (reg & ~MXC_DVFSCNTR_DVFEN);
+		__raw_writel(reg, dvfs_data->membase
+				  + MXC_DVFSCORE_CNTR);
+
+		spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
+
+		dvfs_core_is_active = 0;
+
+		clk_disable(dvfs_clk);
+	}
+
+	printk(KERN_DEBUG "DVFS is stopped\n");
+}
+
+void dump_dvfs_core_regs()
+{
+	struct timeval cur;
+	u32 diff = 0;
+	if (core_prev_intr.tv_sec == 0)
+		do_gettimeofday(&core_prev_intr);
+	else {
+		do_gettimeofday(&cur);
+		diff = (cur.tv_sec - core_prev_intr.tv_sec)*1000000
+			 + (cur.tv_usec - core_prev_intr.tv_usec);
+		core_prev_intr = cur;
+	}
+	if (diff < 90000)
+		printk(KERN_DEBUG "diff = %d\n", diff);
+
+	printk(KERN_INFO "THRS = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS));
+	printk(KERN_INFO "COUNT = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x04));
+	printk(KERN_INFO "SIG1 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x08));
+	printk(KERN_INFO "SIG0 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x0c));
+	printk(KERN_INFO "GPC0 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x10));
+	printk(KERN_INFO "GPC1 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x14));
+	printk(KERN_INFO "GPBT = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x18));
+	printk(KERN_INFO "EMAC = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x1c));
+	printk(KERN_INFO "CNTR = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x20));
+	printk(KERN_INFO "LTR0_0 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x24));
+	printk(KERN_INFO "LTR0_1 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x28));
+	printk(KERN_INFO "LTR1_0 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x2c));
+	printk(KERN_DEBUG "LTR1_1 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x30));
+	printk(KERN_INFO "PT0 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x34));
+	printk(KERN_INFO "PT1 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x38));
+	printk(KERN_INFO "PT2 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x3c));
+	printk(KERN_INFO "PT3 = 0x%08x\n",
+			__raw_readl(dvfs_data->membase
+				    + MXC_DVFSCORE_THRS + 0x40));
+}
+
+static ssize_t downthreshold_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	return sprintf(buf, "%u\n", dvfs_core_setpoint[0].downthr);
+}
+
+static ssize_t downthreshold_store(struct device *dev,
+				 struct device_attribute *attr,
+				 const char *buf, size_t size)
+{
+	int ret = 0;
+	int val;
+	ret = sscanf(buf, "%u", &val);
+	dvfs_core_setpoint[0].downthr = val;
+
+	return size;
+}
+
+static ssize_t downcount_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	return sprintf(buf, "%u\n", dvfs_core_setpoint[0].downcnt);
+}
+
+static ssize_t downcount_store(struct device *dev,
+				 struct device_attribute *attr,
+				 const char *buf, size_t size)
+{
+	int ret = 0;
+	int val;
+	ret = sscanf(buf, "%u", &val);
+	dvfs_core_setpoint[0].downcnt = val;
+
+	return size;
+}
+
+
+static ssize_t dvfs_enable_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	if (dvfs_core_is_active)
+		return sprintf(buf, "DVFS is enabled\n");
+	else
+		return sprintf(buf, "DVFS is disabled\n");
+}
+
+static ssize_t dvfs_enable_store(struct device *dev,
+				 struct device_attribute *attr,
+				 const char *buf, size_t size)
+{
+	if (strstr(buf, "1") != NULL) {
+		if (start_dvfs() != 0)
+			printk(KERN_ERR "Failed to start DVFS\n");
+	} else if (strstr(buf, "0") != NULL)
+		stop_dvfs();
+
+	return size;
+}
+
+static ssize_t dvfs_regs_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	if (dvfs_core_is_active)
+		dump_dvfs_core_regs();
+	return 0;
+}
+
+static ssize_t dvfs_regs_store(struct device *dev,
+				 struct device_attribute *attr,
+				 const char *buf, size_t size)
+{
+	if (dvfs_core_is_active)
+		dump_dvfs_core_regs();
+	return 0;
+
+	return size;
+}
+
+static DEVICE_ATTR(enable, 0644, dvfs_enable_show, dvfs_enable_store);
+static DEVICE_ATTR(show_regs, 0644, dvfs_regs_show, dvfs_regs_store);
+
+static DEVICE_ATTR(down_threshold, 0644, downthreshold_show,
+						downthreshold_store);
+static DEVICE_ATTR(down_count, 0644, downcount_show, downcount_store);
+
+/*!
+ * This is the probe routine for the DVFS driver.
+ *
+ * @param   pdev   The platform device structure
+ *
+ * @return         The function returns 0 on success
+ */
+static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
+{
+	int err = 0;
+	struct resource *res;
+
+	printk(KERN_INFO "mxc_dvfs_core_probe\n");
+	dvfs_dev = &pdev->dev;
+	dvfs_data = pdev->dev.platform_data;
+
+	INIT_DELAYED_WORK(&dvfs_core_handler, dvfs_core_work_handler);
+
+	pll1_sw_clk = clk_get(NULL, "pll1_sw_clk");
+	if (IS_ERR(pll1_sw_clk)) {
+		printk(KERN_INFO "%s: failed to get pll1_sw_clk\n", __func__);
+		return PTR_ERR(pll1_sw_clk);
+	}
+
+	cpu_clk = clk_get(NULL, dvfs_data->clk1_id);
+	if (IS_ERR(cpu_clk)) {
+		printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
+		return PTR_ERR(cpu_clk);
+	}
+
+	dvfs_clk = clk_get(NULL, dvfs_data->clk2_id);
+	if (IS_ERR(dvfs_clk)) {
+		printk(KERN_ERR "%s: failed to get dvfs clock\n", __func__);
+		return PTR_ERR(dvfs_clk);
+	}
+
+	core_regulator = regulator_get(NULL, dvfs_data->reg_id);
+	if (IS_ERR(core_regulator)) {
+		clk_put(cpu_clk);
+		clk_put(dvfs_clk);
+		printk(KERN_ERR "%s: failed to get gp regulator\n", __func__);
+		return PTR_ERR(core_regulator);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		err = -ENODEV;
+		goto err1;
+	}
+	dvfs_data->membase = ioremap(res->start, res->end - res->start + 1);
+	/*
+	 * Request the DVFS interrupt
+	 */
+	dvfs_data->irq = platform_get_irq(pdev, 0);
+	if (dvfs_data->irq < 0) {
+		err = dvfs_data->irq;
+		goto err2;
+	}
+
+	/* request the DVFS interrupt */
+	err = request_irq(dvfs_data->irq, dvfs_irq, IRQF_SHARED, "dvfs",
+			  dvfs_dev);
+	if (err) {
+		printk(KERN_ERR
+		       "DVFS: Unable to attach to DVFS interrupt,err = %d",
+		       err);
+		goto err2;
+	}
+
+	clk_enable(dvfs_clk);
+	err = init_dvfs_controller();
+	if (err) {
+		printk(KERN_ERR "DVFS: Unable to initialize DVFS");
+		return err;
+	}
+	clk_disable(dvfs_clk);
+
+	err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_enable.attr);
+	if (err) {
+		printk(KERN_ERR
+		       "DVFS: Unable to register sysdev entry for DVFS");
+		goto err3;
+	}
+
+	err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_show_regs.attr);
+	if (err) {
+		printk(KERN_ERR
+		       "DVFS: Unable to register sysdev entry for DVFS");
+		goto err3;
+	}
+
+
+	err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_threshold.attr);
+	if (err) {
+		printk(KERN_ERR
+		       "DVFS: Unable to register sysdev entry for DVFS");
+		goto err3;
+	}
+
+	err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_count.attr);
+	if (err) {
+		printk(KERN_ERR
+		       "DVFS: Unable to register sysdev entry for DVFS");
+		goto err3;
+	}
+
+	/* Set the current working point. */
+	cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+	old_op = 0;
+	curr_op = 0;
+	dvfs_core_resume = 0;
+	cpufreq_trig_needed = 0;
+
+	return err;
+err3:
+	free_irq(dvfs_data->irq, dvfs_dev);
+err2:
+	iounmap(dvfs_data->membase);
+err1:
+	dev_err(&pdev->dev, "Failed to probe DVFS CORE\n");
+	return err;
+}
+
+/*!
+ * This function is called to put DVFS in a low power state.
+ *
+ * @param   pdev  the device structure
+ * @param   state the power state the device is entering
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_dvfs_core_suspend(struct platform_device *pdev,
+				 pm_message_t state)
+{
+	if (dvfs_core_is_active) {
+		dvfs_core_resume = 1;
+		stop_dvfs();
+	}
+
+	return 0;
+}
+
+/*!
+ * This function is called to resume the MU from a low power state.
+ *
+ * @param   dev   the device structure
+ * @param   level the stage in device suspension process that we want the
+ *                device to be put in
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_dvfs_core_resume(struct platform_device *pdev)
+{
+	if (dvfs_core_resume) {
+		dvfs_core_resume = 0;
+		start_dvfs();
+	}
+
+	return 0;
+}
+
+static struct platform_driver mxc_dvfs_core_driver = {
+	.driver = {
+		   .name = "mxc_dvfs_core",
+		   },
+	.probe = mxc_dvfs_core_probe,
+	.suspend = mxc_dvfs_core_suspend,
+	.resume = mxc_dvfs_core_resume,
+};
+
+static int __init dvfs_init(void)
+{
+	if (platform_driver_register(&mxc_dvfs_core_driver) != 0) {
+		printk(KERN_ERR "mxc_dvfs_core_driver register failed\n");
+		return -ENODEV;
+	}
+
+	dvfs_core_is_active = 0;
+	printk(KERN_INFO "DVFS driver module loaded\n");
+	return 0;
+}
+
+static void __exit dvfs_cleanup(void)
+{
+	stop_dvfs();
+
+	/* release the DVFS interrupt */
+	free_irq(dvfs_data->irq, dvfs_dev);
+
+	sysfs_remove_file(&dvfs_dev->kobj, &dev_attr_enable.attr);
+
+	/* Unregister the device structure */
+	platform_driver_unregister(&mxc_dvfs_core_driver);
+
+	iounmap(ccm_base);
+	iounmap(dvfs_data->membase);
+	clk_put(cpu_clk);
+	clk_put(dvfs_clk);
+
+	dvfs_core_is_active = 0;
+	printk(KERN_INFO "DVFS driver module unloaded\n");
+
+}
+
+module_init(dvfs_init);
+module_exit(dvfs_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("DVFS driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h
new file mode 100755
index 00000000000..f121dc17fe6
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/arc_otg.h
@@ -0,0 +1,377 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_MXC_ARC_OTG_H__
+#define __ASM_ARCH_MXC_ARC_OTG_H__
+
+#ifdef CONFIG_ARCH_MX3
+extern volatile u32 *mx3_usb_otg_addr;
+#define OTG_BASE_ADDR		mx3_usb_otg_addr
+#else
+extern void __iomem *imx_otg_base;
+#define OTG_BASE_ADDR           imx_otg_base
+#endif
+
+#define USB_OTGREGS_BASE	(OTG_BASE_ADDR + 0x000)
+#define USB_H1REGS_BASE		(OTG_BASE_ADDR + 0x200)
+#define USB_H2REGS_BASE		(OTG_BASE_ADDR + 0x400)
+#ifdef CONFIG_ARCH_MX5
+#define USB_H3REGS_BASE		(OTG_BASE_ADDR + 0x600)
+#define USB_OTHERREGS_BASE	(OTG_BASE_ADDR + 0x800)
+#else
+#define USB_OTHERREGS_BASE	(OTG_BASE_ADDR + 0x600)
+#endif
+
+
+#define USBOTG_REG32(offset)	(*((volatile u32 __force *)(USB_OTGREGS_BASE + (offset))))
+#define USBOTG_REG16(offset)	(*((volatile u16 __force *)(USB_OTGREGS_BASE + (offset))))
+
+#define USBH1_REG32(offset)	(*((volatile u32 __force *)(USB_H1REGS_BASE + (offset))))
+#define USBH1_REG16(offset)	(*((volatile u16 __force *)(USB_H1REGS_BASE + (offset))))
+
+#define USBH2_REG32(offset)	(*((volatile u32 __force *)(USB_H2REGS_BASE + (offset))))
+#define USBH2_REG16(offset)	(*((volatile u16 __force *)(USB_H2REGS_BASE + (offset))))
+
+#define USBOTHER_REG(offset)	(*((volatile u32 __force *)(USB_OTHERREGS_BASE + (offset))))
+
+/*
+ * OTG registers
+ */
+#define UOG_ID			USBOTG_REG32(0x00)	/* Host ID */
+#define UOG_HWGENERAL		USBOTG_REG32(0x04)	/* Host General */
+#define UOG_HWHOST		USBOTG_REG32(0x08)	/* Host h/w params */
+#define UOG_HWTXBUF		USBOTG_REG32(0x10)	/* TX buffer h/w params */
+#define UOG_HWRXBUF		USBOTG_REG32(0x14)	/* RX buffer h/w params */
+#define UOG_CAPLENGTH		USBOTG_REG16(0x100)	/* Capability register length */
+#define UOG_HCIVERSION		USBOTG_REG16(0x102)	/* Host Interface version */
+#define UOG_HCSPARAMS		USBOTG_REG32(0x104)	/* Host control structural params */
+#define UOG_HCCPARAMS		USBOTG_REG32(0x108)	/* control capability params */
+#define UOG_DCIVERSION		USBOTG_REG32(0x120)	/* device interface version */
+/* start EHCI registers: */
+#define UOG_USBCMD		USBOTG_REG32(0x140)	/* USB command register */
+#define UOG_USBSTS		USBOTG_REG32(0x144)	/* USB status register */
+#define UOG_USBINTR		USBOTG_REG32(0x148)	/* interrupt enable register */
+#define UOG_FRINDEX		USBOTG_REG32(0x14c)	/* USB frame index */
+/*      segment                             (0x150)	   addr bits 63:32 if needed */
+#define UOG_PERIODICLISTBASE	USBOTG_REG32(0x154)	/* host crtlr frame list base addr */
+#define UOG_DEVICEADDR		USBOTG_REG32(0x154)	/* device crtlr device address */
+#define UOG_ASYNCLISTADDR	USBOTG_REG32(0x158)	/* host ctrlr next async addr */
+#define UOG_EPLISTADDR		USBOTG_REG32(0x158)	/* device ctrlr endpoint list addr */
+#define UOG_BURSTSIZE		USBOTG_REG32(0x160)	/* host ctrlr embedded TT async buf status */
+#define UOG_TXFILLTUNING	USBOTG_REG32(0x164)	/* TX FIFO fill tuning */
+#define UOG_ULPIVIEW		USBOTG_REG32(0x170)	/* ULPI viewport */
+#define UOG_CFGFLAG		USBOTG_REG32(0x180)	/* configflag (supports HS) */
+#define UOG_PORTSC1		USBOTG_REG32(0x184)	/* port status and control */
+/* end EHCI registers: */
+#define UOG_OTGSC		USBOTG_REG32(0x1a4)	/* OTG status and control */
+#define UOG_USBMODE		USBOTG_REG32(0x1a8)	/* USB device mode */
+#define UOG_ENDPTSETUPSTAT	USBOTG_REG32(0x1ac)	/* endpoint setup status */
+#define UOG_ENDPTPRIME		USBOTG_REG32(0x1b0)	/* endpoint initialization */
+#define UOG_ENDPTFLUSH		USBOTG_REG32(0x1b4)	/* endpoint de-initialize */
+#define UOG_ENDPTSTAT		USBOTG_REG32(0x1b8)	/* endpoint status */
+#define UOG_ENDPTCOMPLETE	USBOTG_REG32(0x1bc)	/* endpoint complete */
+#define UOG_EPCTRL0		USBOTG_REG32(0x1c0)	/* endpoint control0 */
+#define UOG_EPCTRL1		USBOTG_REG32(0x1c4)	/* endpoint control1 */
+#define UOG_EPCTRL2		USBOTG_REG32(0x1c8)	/* endpoint control2 */
+#define UOG_EPCTRL3		USBOTG_REG32(0x1cc)	/* endpoint control3 */
+#define UOG_EPCTRL4		USBOTG_REG32(0x1d0)	/* endpoint control4 */
+#define UOG_EPCTRL5		USBOTG_REG32(0x1d4)	/* endpoint control5 */
+#define UOG_EPCTRL6		USBOTG_REG32(0x1d8)	/* endpoint control6 */
+#define UOG_EPCTRL7		USBOTG_REG32(0x1dc)	/* endpoint control7 */
+
+/*
+ * Host 1 registers
+ */
+#define UH1_ID			USBH1_REG32(0x00)	/* Host ID */
+#define UH1_HWGENERAL		USBH1_REG32(0x04)	/* Host General */
+#define UH1_HWHOST		USBH1_REG32(0x08)	/* Host h/w params */
+#define UH1_HWTXBUF		USBH1_REG32(0x10)	/* TX buffer h/w params */
+#define UH1_HWRXBUF		USBH1_REG32(0x14)	/* RX buffer h/w params */
+#define UH1_CAPLENGTH		USBH1_REG16(0x100)	/* Capability register length */
+#define UH1_HCIVERSION		USBH1_REG16(0x102)	/* Host Interface version */
+#define UH1_HCSPARAMS		USBH1_REG32(0x104)	/* Host control structural params */
+#define UH1_HCCPARAMS		USBH1_REG32(0x108)	/* control capability params */
+/* start EHCI registers: */
+#define UH1_USBCMD		USBH1_REG32(0x140)	/* USB command register */
+#define UH1_USBSTS		USBH1_REG32(0x144)	/* USB status register */
+#define UH1_USBINTR		USBH1_REG32(0x148)	/* interrupt enable register */
+#define UH1_FRINDEX		USBH1_REG32(0x14c)	/* USB frame index */
+/*      segment                            (0x150)	   addr bits 63:32 if needed */
+#define UH1_PERIODICLISTBASE	USBH1_REG32(0x154)	/* host crtlr frame list base addr */
+#define UH1_ASYNCLISTADDR	USBH1_REG32(0x158)	/* host ctrlr nest async addr */
+#define UH1_BURSTSIZE		USBH1_REG32(0x160)	/* host ctrlr embedded TT async buf status */
+#define UH1_TXFILLTUNING	USBH1_REG32(0x164)	/* TX FIFO fill tuning */
+/*      configured_flag                    (0x180)	   configflag (supports HS) */
+#define UH1_PORTSC1		USBH1_REG32(0x184)	/* port status and control */
+/* end EHCI registers: */
+#define UH1_USBMODE		USBH1_REG32(0x1a8)	/* USB device mode */
+
+/*
+ * Host 2 registers
+ */
+#define UH2_ID			USBH2_REG32(0x00)	/* Host ID */
+#define UH2_HWGENERAL		USBH2_REG32(0x04)	/* Host General */
+#define UH2_HWHOST		USBH2_REG32(0x08)	/* Host h/w params */
+#define UH2_HWTXBUF		USBH2_REG32(0x10)	/* TX buffer h/w params */
+#define UH2_HWRXBUF		USBH2_REG32(0x14)	/* RX buffer h/w params */
+#define UH2_CAPLENGTH		USBH2_REG16(0x100)	/* Capability register length */
+#define UH2_HCIVERSION		USBH2_REG16(0x102)	/* Host Interface version */
+#define UH2_HCSPARAMS		USBH2_REG32(0x104)	/* Host control structural params */
+#define UH2_HCCPARAMS		USBH2_REG32(0x108)	/* control capability params */
+/* start EHCI registers: */
+#define UH2_USBCMD		USBH2_REG32(0x140)	/* USB command register */
+#define UH2_USBSTS		USBH2_REG32(0x144)	/* USB status register */
+#define UH2_USBINTR		USBH2_REG32(0x148)	/* interrupt enable register */
+#define UH2_FRINDEX		USBH2_REG32(0x14c)	/* USB frame index */
+/*      segment                            (0x150)	   addr bits 63:32 if needed */
+#define UH2_PERIODICLISTBASE	USBH2_REG32(0x154)	/* host crtlr frame list base addr */
+#define UH2_ASYNCLISTADDR	USBH2_REG32(0x158)	/* host ctrlr nest async addr */
+#define UH2_BURSTSIZE		USBH2_REG32(0x160)	/* host ctrlr embedded TT async buf status */
+#define UH2_TXFILLTUNING	USBH2_REG32(0x164)	/* TX FIFO fill tuning */
+#define UH2_ULPIVIEW		USBH2_REG32(0x170)	/* ULPI viewport */
+/*      configured_flag                    (0x180)	   configflag (supports HS) */
+#define UH2_PORTSC1		USBH2_REG32(0x184)	/* port status and control */
+/* end EHCI registers */
+#define UH2_USBMODE		USBH2_REG32(0x1a8)	/* USB device mode */
+
+/*
+ * other regs (not part of ARC core)
+ */
+#define USBCTRL			USBOTHER_REG(0x00)	/* USB Control register */
+#define USB_OTG_MIRROR		USBOTHER_REG(0x04)	/* USB OTG mirror register */
+#define USB_PHY_CTR_FUNC	USBOTHER_REG(0x08)      /* OTG UTMI PHY Function Control register */
+#define USB_PHY_CTR_FUNC2	USBOTHER_REG(0x0c)      /* OTG UTMI PHY Function Control register */
+#define USB_CTRL_1		USBOTHER_REG(0x10)	/* USB Cotrol Register 1*/
+#define USBCTRL_HOST2		USBOTHER_REG(0x14)	/* USB Cotrol Register 1*/
+#define USBCTRL_HOST3		USBOTHER_REG(0x18)	/* USB Cotrol Register 1*/
+#define USBH1_PHY_CTRL0		USBOTHER_REG(0x1c)	/* USB Cotrol Register 1*/
+#define USBH1_PHY_CTRL1		USBOTHER_REG(0x20)	/* USB Cotrol Register 1*/
+#define USB_CLKONOFF_CTRL       USBOTHER_REG(0x24)      /* USB Clock on/off Control Register */
+
+/*
+ * register bits
+ */
+
+/* x_PORTSCx */
+#define PORTSC_PTS_MASK			(3 << 30)	/* parallel xcvr select mask */
+#define PORTSC_PTS_UTMI			(0 << 30)	/* UTMI/UTMI+ */
+#define PORTSC_PTS_PHILIPS		(1 << 30)	/* Philips classic */
+#define PORTSC_PTS_ULPI			(2 << 30)	/* ULPI */
+#define PORTSC_PTS_SERIAL		(3 << 30)	/* serial */
+#define PORTSC_STS			(1 << 29)	/* serial xcvr select */
+#define PORTSC_PTW                      (1 << 28)       /* UTMI width */
+#define PORTSC_PHCD                     (1 << 23)       /* Low Power Suspend */
+#define PORTSC_PORT_POWER		(1 << 12)	/* port power */
+#define PORTSC_LS_MASK			(3 << 10)	/* Line State mask */
+#define PORTSC_LS_SE0			(0 << 10)	/* SE0     */
+#define PORTSC_LS_K_STATE		(1 << 10)	/* K-state */
+#define PORTSC_LS_J_STATE		(2 << 10)	/* J-state */
+#define PORTSC_PORT_RESET		(1 <<  8)	/* Port reset */
+#define PORTSC_PORT_SUSPEND		(1 <<  7)	/* Suspend */
+#define PORTSC_PORT_FORCE_RESUME	(1 <<  6)	/* Force port resume */
+#define PORTSC_OVER_CURRENT_CHG		(1 <<  5)	/* over current change */
+#define PORTSC_OVER_CURRENT_ACT		(1 <<  4)	/* over currrent active */
+#define PORTSC_PORT_EN_DIS_CHANGE	(1 <<  3)	/* port {en,dis}able change */
+#define PORTSC_PORT_ENABLE		(1 <<  2)	/* port enabled */
+#define PORTSC_CONNECT_STATUS_CHANGE	(1 <<  1)	/* connect status change */
+#define PORTSC_CURRENT_CONNECT_STATUS	(1 <<  0)	/* current connect status */
+
+#define PORTSC_W1C_BITS                     \
+	(PORTSC_CONNECT_STATUS_CHANGE | \
+	PORTSC_PORT_EN_DIS_CHANGE | \
+	PORTSC_OVER_CURRENT_CHG)
+
+/* UOG_OTGSC Register Bits */
+/* control bits: */
+#define  OTGSC_CTRL_VBUS_DISCHARGE	(1 <<  0)
+#define  OTGSC_CTRL_VBUS_CHARGE		(1 <<  1)
+#define  OTGSC_CTRL_OTG_TERM		(1 <<  3)	/* controls DM pulldown */
+#define  OTGSC_CTRL_DATA_PULSING	(1 <<  4)
+#define  OTGSC_CTRL_USB_ID_PU		(1 <<  5)	/* enable ID pullup */
+/* current status: (R/O) */
+#define  OTGSC_STS_USB_ID		(1 <<  8)	/* 0=A-device  1=B-device */
+#define  OTGSC_STS_A_VBUS_VALID		(1 <<  9)
+#define  OTGSC_STS_A_SESSION_VALID	(1 << 10)
+#define  OTGSC_STS_B_SESSION_VALID	(1 << 11)
+#define  OTGSC_STS_B_SESSION_END	(1 << 12)
+#define  OTGSC_STS_1ms_TIMER		(1 << 13)
+#define  OTGSC_STS_DATA_PULSE		(1 << 14)
+/* interrupt status: (write to clear) */
+#define  OTGSC_IS_MASK			(0x7f << 16)
+#define  OTGSC_IS_USB_ID		(1 << 16)
+#define  OTGSC_IS_A_VBUS_VALID		(1 << 17)
+#define  OTGSC_IS_A_SESSION_VALID	(1 << 18)
+#define  OTGSC_IS_B_SESSION_VALID	(1 << 19)
+#define  OTGSC_IS_B_SESSION_END		(1 << 20)
+#define  OTGSC_IS_1ms_TIMER		(1 << 21)
+#define  OTGSC_IS_DATA_PULSE		(1 << 22)
+/* interrupt enables: */
+#define  OTGSC_IE_MASK			(0x7f << 24)
+#define  OTGSC_IE_USB_ID		(1 << 24)
+#define  OTGSC_IE_A_VBUS_VALID		(1 << 25)
+#define  OTGSC_IE_A_SESSION_VALID	(1 << 26)
+#define  OTGSC_IE_B_SESSION_VALID	(1 << 27)
+#define  OTGSC_IE_B_SESSION_END		(1 << 28)
+#define  OTGSC_IE_1ms_TIMER		(1 << 29)
+#define  OTGSC_IE_DATA_PULSE		(1 << 30)
+
+#if 1				/* FIXME these here for compatibility between my names and Leo's */
+/* OTG interrupt enable bit masks */
+#define  OTGSC_INTERRUPT_ENABLE_BITS_MASK	OTGSC_IE_MASK
+#define  OTGSC_INTSTS_MASK			OTGSC_IS_MASK
+
+/* OTG interrupt status bit masks */
+#define  OTGSC_INTERRUPT_STATUS_BITS_MASK	OTGSC_IS_MASK
+#endif
+
+/* x_USBMODE */
+#define USBMODE_SLOM		(1 << 3)	/* setup lockout mode */
+#define USBMODE_ES		(1 << 2)	/* (big) endian select */
+#define USBMODE_CM_MASK		(3 << 0)	/* controller mode mask */
+#define USBMODE_CM_HOST		(3 << 0)	/* host */
+#define USBMODE_CM_DEVICE	(2 << 0)	/* device */
+#define USBMODE_CM_reserved	(1 << 0)	/* reserved */
+
+/* USBCTRL */
+#define UCTRL_OWIR		(1 << 31)	/* OTG wakeup intr request received */
+#define UCTRL_OSIC_MASK		(3 << 29)	/* OTG  Serial Interface Config: */
+#define UCTRL_OSIC_DU6		(0 << 29)	/* Differential/unidirectional 6 wire */
+#define UCTRL_OSIC_DB4		(1 << 29)	/* Differential/bidirectional  4 wire */
+#define UCTRL_OSIC_SU6		(2 << 29)	/* single-ended/unidirectional 6 wire */
+#define UCTRL_OSIC_SB3		(3 << 29)	/* single-ended/bidirectional  3 wire */
+
+#define UCTRL_OUIE		(1 << 28)	/* OTG ULPI intr enable */
+#define UCTRL_OWIE		(1 << 27)	/* OTG wakeup intr enable */
+#define UCTRL_OBPVAL_RXDP	(1 << 26)	/* OTG RxDp status in bypass mode */
+#define UCTRL_OBPVAL_RXDM	(1 << 25)	/* OTG RxDm status in bypass mode */
+#define UCTRL_OPM		(1 << 24)	/* OTG power mask */
+#define UCTRL_O_PWR_POL	(1 << 24)	/* OTG power pin polarity */
+#ifdef CONFIG_ARCH_MX5
+#define UCTRL_H2WIR		(1 << 17)	/* HOST2 wakeup intr request received */
+#else
+#define UCTRL_H2WIR		(1 << 23)	/* HOST2 wakeup intr request received */
+#endif
+#define UCTRL_H2SIC_MASK	(3 << 21)	/* HOST2 Serial Interface Config: */
+#define UCTRL_H2SIC_DU6		(0 << 21)	/* Differential/unidirectional 6 wire */
+#define UCTRL_H2SIC_DB4		(1 << 21)	/* Differential/bidirectional  4 wire */
+#define UCTRL_H2SIC_SU6		(2 << 21)	/* single-ended/unidirectional 6 wire */
+#define UCTRL_H2SIC_SB3		(3 << 21)	/* single-ended/bidirectional  3 wire */
+
+#ifdef CONFIG_ARCH_MX5
+#define UCTRL_H2UIE		(1 << 8)	/* HOST2 ULPI intr enable */
+#define UCTRL_H2WIE		(1 << 7)	/* HOST2 wakeup intr enable */
+#define UCTRL_H2PP		0	/* Power Polarity for uh2 */
+#define UCTRL_H2PM		(1 << 4)	/* HOST2 power mask */
+#else
+#define UCTRL_H2UIE		(1 << 20)	/* HOST2 ULPI intr enable */
+#define UCTRL_H2WIE		(1 << 19)	/* HOST2 wakeup intr enable */
+#define UCTRL_H2PP		(1 << 18)	/* Power Polarity for uh2 */
+#define UCTRL_H2PM		(1 << 16)	/* HOST2 power mask */
+#endif
+#define UCTRL_H2OVBWK_EN	(1 << 6) /* OTG VBUS Wakeup Enable */
+#define UCTRL_H2OIDWK_EN	(1 << 5) /* OTG ID Wakeup Enable */
+
+#define UCTRL_H1WIR		(1 << 15)	/* HOST1 wakeup intr request received */
+#define UCTRL_H1SIC_MASK	(3 << 13)	/* HOST1 Serial Interface Config: */
+#define UCTRL_H1SIC_DU6		(0 << 13)	/* Differential/unidirectional 6 wire */
+#define UCTRL_H1SIC_DB4		(1 << 13)	/* Differential/bidirectional  4 wire */
+#define UCTRL_H1SIC_SU6		(2 << 13)	/* single-ended/unidirectional 6 wire */
+#define UCTRL_H1SIC_SB3		(3 << 13)	/* single-ended/bidirectional  3 wire */
+#define UCTRL_OLOCKD		(1 << 13)	/* otg lock disable */
+#define UCTRL_H2LOCKD		(1 << 12)	/* HOST2 lock disable */
+#define UCTRL_H1UIE		(1 << 12)	/* Host1 ULPI interrupt enable */
+
+#if defined(CONFIG_ARCH_MX37)
+/* VBUS wakeup enable, UTMI only */
+#define UCTRL_VBUS_WKUP_EN	(1 << 12)
+#elif defined(CONFIG_ARCH_MX25) || defined(CONFIG_ARCH_MX35)
+#define UCTRL_VBUS_WKUP_EN      (1 << 15)
+#endif
+
+#define UCTRL_PP                (1 << 11)       /* power polarity bit */
+#define UCTRL_H1WIE		(1 << 11)	/* HOST1 wakeup intr enable */
+#define UCTRL_H1BPVAL_RXDP	(1 << 10)	/* HOST1 RxDp status in bypass mode */
+#define UCTRL_XCSO              (1 << 10)       /* Xcvr Clock Select for OTG port */
+#define UCTRL_H1BPVAL_RXDM	(1 <<  9)	/* HOST1 RxDm status in bypass mode */
+#define UCTRL_XCSH2             (1 <<  9)       /* Xcvr Clock Select for Host port */
+#define UCTRL_H1PM		(1 <<  8)	/* HOST1 power mask */
+#define UCTRL_IP_PULIDP         (1 <<  8)       /* Ipp_Puimpel_Pullup_Dp */
+
+#define UCTRL_IP_PUE_UP         (1 <<  7)       /* ipp_pue_pullup_dp */
+#define UCTRL_IP_PUE_DOWN       (1 <<  6)       /* ipp_pue_pulldwn_dpdm */
+#define UCTRL_H2DT		(1 <<  5)	/* HOST2 TLL disabled */
+#define UCTRL_H1DT		(1 <<  4)	/* HOST1 TLL disabled */
+#define UCTRL_USBTE             (1 <<  4)       /* USBT Transceiver enable */
+#define UCTRL_OCPOL             (1 <<  3)       /* OverCurrent Polarity */
+#define UCTRL_OCE               (1 <<  2)       /* OverCurrent Enable */
+#define UCTRL_H2OCPOL		(1 <<  2)       /* OverCurrent Polarity of Host2 */
+#define UCTRL_H2OCS             (1 <<  1)       /* Host OverCurrent State */
+#define UCTRL_BPE		(1 <<  0)	/* bypass mode enable */
+#define UCTRL_OTD		(1 <<  0)	/* OTG TLL Disable */
+#define UCTRL_OOCS              (1 <<  0)       /* OTG OverCurrent State */
+
+/* USBCMD */
+#define UCMD_RUN_STOP           (1 << 0)        /* controller run/stop */
+#define UCMD_RESET		(1 << 1)	/* controller reset */
+#define UCMD_ITC_NO_THRESHOLD	 (~(0xff << 16))	/* Interrupt Threshold Control */
+
+/* OTG_MIRROR */
+#define OTGM_SESEND		(1 << 4)	/* B device session end */
+#define OTGM_VBUSVAL		(1 << 3)	/* Vbus valid */
+#define OTGM_BSESVLD		(1 << 2)	/* B session Valid */
+#define OTGM_ASESVLD		(1 << 1)	/* A session Valid */
+#define OTGM_IDIDG		(1 << 0)	/* OTG ID pin status */
+				/* 1=high: Operate as B-device */
+				/* 0=low : Operate as A-device */
+
+/* USB_PHY_CTRL_FUNC */
+/* PHY control0 Register Bit Masks */
+#define USB_UTMI_PHYCTRL_CONF2	(1 << 26)
+
+#define USB_UTMI_PHYCTRL_UTMI_ENABLE (1 << 24)
+#define USB_UTMI_PHYCTRL_CHGRDETEN (1 << 24)    /* Enable Charger Detector */
+#define USB_UTMI_PHYCTRL_CHGRDETON (1 << 23)    /* Charger Detector Power On Control */
+#define USB_UTMI_PHYCTRL_OC_POL	(1 << 9)	/* OTG Polarity of Overcurrent */
+#define USB_UTMI_PHYCTRL_OC_DIS	(1 << 8)	/* OTG Disable Overcurrent Event */
+#define USB_UH1_OC_DIS	(1 << 5)		/* UH1 Disable Overcurrent Event */
+#define USB_UH1_OC_POL	(1 << 6)		/* UH1 Polarity of OC,Low active */
+/* USB_PHY_CTRL_FUNC2*/
+#define USB_UTMI_PHYCTRL2_PLLDIV_MASK		0x3
+#define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT		0
+#define USB_UTMI_PHYCTRL2_HSDEVSEL_MASK		0x3
+#define USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT	19
+
+/* USB_CTRL_1 */
+#define USB_CTRL_UH1_EXT_CLK_EN			(1 << 25)
+#define USB_CTRL_UH2_EXT_CLK_EN			(1 << 26)
+#define USB_CTRL_UH2_CLK_FROM_ULPI_PHY  	(1 << 2)
+/* ULPIVIEW register bits */
+#define ULPIVW_OFF		(0x170)
+#define ULPIVW_WU		(1 << 31)	/* Wakeup */
+#define ULPIVW_RUN		(1 << 30)	/* read/write run */
+#define ULPIVW_WRITE		(1 << 29)	/* 0=read  1=write */
+#define ULPIVW_SS		(1 << 27)	/* SyncState */
+#define ULPIVW_PORT_MASK	0x07	/* Port field */
+#define ULPIVW_PORT_SHIFT	24
+#define ULPIVW_ADDR_MASK	0xFF	/* data address field */
+#define ULPIVW_ADDR_SHIFT	16
+#define ULPIVW_RDATA_MASK	0xFF	/* read data field */
+#define ULPIVW_RDATA_SHIFT	8
+#define ULPIVW_WDATA_MASK	0xFF	/* write data field */
+#define ULPIVW_WDATA_SHIFT	0
+
+#define HCSPARAMS_PPC           (0x1<<4)        /* Port Power Control */
+/* USB Clock on/off Control Register */
+#define OTG_AHBCLK_OFF          (0x1<<17)      /* 1: OFF */
+#define H1_AHBCLK_OFF           (0x1<<18)      /* 1: OFF */
+extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata);
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 753a5988d85..3c8802cc54f 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  *
  * This program is free software; you can redistribute it and/or
@@ -23,9 +23,14 @@
 #ifndef __ASSEMBLY__
 #include <linux/list.h>
 
+#define CLK_NAME_LEN 32
 struct module;
 
 struct clk {
+#ifdef CONFIG_CLK_DEBUG
+	char name[CLK_NAME_LEN];
+	struct dentry           *dentry;
+#endif
 	int id;
 	/* Source clock this clk depends on */
 	struct clk *parent;
@@ -57,10 +62,26 @@ struct clk {
 	int (*set_parent) (struct clk *, struct clk *);
 };
 
+int clk_get_usecount(struct clk *clk);
+
 int clk_register(struct clk *clk);
 void clk_unregister(struct clk *clk);
 
+/* Clock flags */
+#define RATE_PROPAGATES		(1 << 0)	/* Program children too */
+#define ALWAYS_ENABLED		(1 << 1)	/* Clock cannot be disabled */
+#define RATE_FIXED		(1 << 2)	/* Fixed clock rate */
+#define CPU_FREQ_TRIG_UPDATE	(1 << 3)	/* CPUFREQ trig update */
+#define AHB_HIGH_SET_POINT	(1 << 4)	/* Requires max AHB clock */
+#define AHB_MED_SET_POINT	(1 << 5)	/* Requires med AHB clock */
+
 unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
 
+#ifdef CONFIG_CLK_DEBUG
+void clk_debug_register(struct clk *clk);
+#else
+static inline void clk_debug_register(struct clk *clk) {}
+#endif
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index f4ebdb817ab..a9727648c72 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -87,6 +87,8 @@ enum mxc_cpu_pwr_mode {
 extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 extern void imx_print_silicon_rev(const char *cpu, int srev);
 
+struct pt_regs;
+
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
 void gic_handle_irq(struct pt_regs *);
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index def9ba53e23..1a0faba6dc3 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -144,6 +144,24 @@ struct platform_device *__init imx_add_imx_ssi(
 		const struct imx_imx_ssi_data *data,
 		const struct imx_ssi_platform_data *pdata);
 
+struct imx_spdif_data {
+	resource_size_t iobase;
+	resource_size_t irq;
+};
+struct platform_device *__init imx_add_spdif(
+		const struct imx_spdif_data *data,
+		const struct mxc_spdif_platform_data *pdata);
+
+struct imx_spdif_dai_data {
+	resource_size_t iobase;
+	resource_size_t dmatx;
+	resource_size_t dmarx;
+};
+struct platform_device *__init imx_add_spdif_dai(
+		const struct imx_spdif_dai_data *data);
+
+struct platform_device *__init imx_add_spdif_audio_device(void);
+
 #include <mach/imx-uart.h>
 struct imx_imx_uart_3irq_data {
 	int id;
@@ -183,23 +201,55 @@ struct platform_device *__init imx_add_imx_udc(
 		const struct imx_imx_udc_data *data,
 		const struct imxusb_platform_data *pdata);
 
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
-#include <mach/mx3_camera.h>
-struct imx_ipu_core_data {
+#include <mach/mxc_vpu.h>
+struct imx_vpu_data {
+	resource_size_t iobase;
+	resource_size_t irq_ipi;
+	resource_size_t irq_jpg;
+	bool iram_enable;
+	int iram_size;
+	void (*reset) (void);
+	void (*pg) (int);
+};
+struct platform_device *__init imx_add_vpu(
+		const struct imx_vpu_data *data);
+
+#include <mach/ipu-v3.h>
+struct imx_ipuv3_data {
 	resource_size_t iobase;
-	resource_size_t synirq;
-	resource_size_t errirq;
+	resource_size_t iosize;
+	resource_size_t irq_err;
+	resource_size_t irq;
+	unsigned int irq_start;
+	int (*init) (int);
+	void (*pg) (int);
 };
-struct platform_device *__init imx_add_ipu_core(
-		const struct imx_ipu_core_data *data,
-		const struct ipu_platform_data *pdata);
-struct platform_device *__init imx_alloc_mx3_camera(
-		const struct imx_ipu_core_data *data,
-		const struct mx3_camera_pdata *pdata);
-struct platform_device *__init imx_add_mx3_sdc_fb(
-		const struct imx_ipu_core_data *data,
-		struct mx3fb_platform_data *pdata);
+struct platform_device *__init imx_add_ipuv3(
+		const int id,
+		const struct imx_ipuv3_data *data,
+		struct imx_ipuv3_platform_data *pdata);
+
+struct platform_device *__init imx_add_ipuv3_fb(
+		const int id,
+		const struct ipuv3_fb_platform_data *pdata);
+
+#include <linux/fsl_devices.h>
+struct imx_tve_data {
+	resource_size_t iobase;
+	resource_size_t irq;
+};
+struct platform_device *__init imx_add_tve(
+		const struct imx_tve_data *data,
+		const struct fsl_mxc_tve_platform_data *pdata);
+
+struct imx_ldb_data {
+	resource_size_t iobase;
+	resource_size_t iosize;
+};
+
+struct platform_device *__init imx_add_ldb(
+	const struct imx_ldb_data *data,
+	struct fsl_mxc_ldb_platform_data *pdata);
 
 #include <mach/mx1_camera.h>
 struct imx_mx1_camera_data {
@@ -331,3 +381,32 @@ struct imx_ahci_imx_data {
 struct platform_device *__init imx_add_ahci_imx(
 		const struct imx_ahci_imx_data *data,
 		const struct ahci_platform_data *pdata);
+
+struct imx_srtc_data {
+	resource_size_t iobase;
+	resource_size_t irq;
+};
+struct platform_device *__init imx_add_srtc(
+		const struct imx_srtc_data *data);
+
+struct imx_iim_data {
+	resource_size_t iobase;
+	resource_size_t irq;
+};
+struct platform_device *__init imx_add_iim(
+		const struct imx_iim_data *data,
+		const struct mxc_iim_platform_data *pdata);
+
+#include <mach/mxc_gpu.h>
+struct imx_mxc_gpu_data {
+	resource_size_t irq_2d;
+	resource_size_t irq_3d;
+	resource_size_t iobase_2d;
+	resource_size_t iobase_3d;
+	resource_size_t gmem_base;
+	resource_size_t gmem_size;
+};
+
+struct platform_device *__init imx_add_mxc_gpu(
+		const struct imx_mxc_gpu_data *data,
+		const struct mxc_gpu_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
index 233d0a5e2d6..dd41a6475be 100644
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ b/arch/arm/plat-mxc/include/mach/dma.h
@@ -53,6 +53,13 @@ struct imx_dma_data {
 	int priority;
 };
 
+struct imx_pcm_dma_params {
+	enum sdma_peripheral_type peripheral_type;
+	int dma;
+	unsigned long dma_addr;
+	int burstsize;
+};
+
 static inline int imx_dma_is_ipu(struct dma_chan *chan)
 {
 	return !strcmp(dev_name(chan->device->dev), "ipu-core");
diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb.h b/arch/arm/plat-mxc/include/mach/fsl_usb.h
new file mode 100755
index 00000000000..735e5b3f365
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/fsl_usb.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * USB Host side, platform-specific functionality.
+ */
+
+#include <linux/usb/fsl_xcvr.h>
+#include <mach/hardware.h>
+#include <mach/arc_otg.h>
+
+static void fsl_setup_phy(struct ehci_hcd *ehci,
+			  enum fsl_usb2_phy_modes phy_mode,
+			  int port_offset);
+
+static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci)
+{
+	struct fsl_usb2_platform_data *pdata;
+
+	pdata = ehci_to_hcd(ehci)->self.controller->platform_data;
+	fsl_setup_phy(ehci, pdata->phy_mode, 0);
+}
+
+static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd)
+{
+	unsigned int temp;
+	struct fsl_usb2_platform_data *pdata;
+
+	pdata = hcd->self.controller->platform_data;
+
+	if (pdata->xcvr_ops && pdata->xcvr_ops->set_host)
+		pdata->xcvr_ops->set_host();
+
+	/* set host mode */
+	temp = readl(hcd->regs + 0x1a8);
+	writel(temp | USBMODE_CM_HOST, hcd->regs + 0x1a8);
+}
+
+/* Needed for enable PP and i2c/serial transceivers */
+static inline void
+fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on)
+{
+	u32 temp;
+
+	/* HCSPARAMS */
+	temp = readl(pdata->regs + 0x104);
+	/* Port Power Control */
+	if (temp & HCSPARAMS_PPC) {
+		temp = readl(pdata->regs + FSL_SOC_USB_PORTSC1);
+		if (on)
+			temp |= PORT_POWER;
+		else
+			temp &= ~PORT_POWER;
+
+		writel(temp, pdata->regs + FSL_SOC_USB_PORTSC1);
+	}
+
+	if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power)
+		pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on);
+}
+
+/* Set USB AHB burst length for host */
+static inline void fsl_platform_set_ahb_burst(struct usb_hcd *hcd)
+{
+	struct fsl_usb2_platform_data *pdata;
+	unsigned int temp;
+
+	pdata = hcd->self.controller->platform_data;
+	if (pdata->change_ahb_burst) {
+		temp = readl(hcd->regs + FSL_SOC_USB_SBUSCFG);
+		writel((temp & (~(0x7))) | pdata->ahb_burst_mode,
+			hcd->regs + FSL_SOC_USB_SBUSCFG);
+	}
+
+	/* Increase TX fifo threshold for USB+ATA for i.mx35 2.0 */
+	if (cpu_is_mx35() && (imx_cpu_ver() >= IMX_CHIP_REVISION_2_0)) {
+		temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+		/* Change TX FIFO threshold to be 0x20 */
+		writel((temp & (~(0x3f << 16))) | (0x20 << 16),
+			hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+	}
+
+	/* Increase TX fifo threshold for USB+SD in Hostx */
+	if (cpu_is_mx53() && (strcmp("DR", pdata->name))) {
+		temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+		/* Change TX FIFO threshold to be 0x08 */
+		writel((temp & (~(0x3f << 16))) | (0x08 << 16),
+				hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+	}
+
+}
diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h
new file mode 100755
index 00000000000..53f9b05a3ba
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * USB Gadget side, platform-specific functionality.
+ */
+
+#include <linux/usb/fsl_xcvr.h>
+
+/* Needed for i2c/serial transceivers */
+static inline void
+fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata)
+{
+	if (pdata->xcvr_ops && pdata->xcvr_ops->set_device)
+		pdata->xcvr_ops->set_device();
+}
+
+static inline void
+fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata)
+{
+	if (pdata->xcvr_ops && pdata->xcvr_ops->pullup)
+		pdata->xcvr_ops->pullup(1);
+}
+
+static inline void
+fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata)
+{
+	if (pdata->xcvr_ops && pdata->xcvr_ops->pullup)
+		pdata->xcvr_ops->pullup(0);
+}
diff --git a/arch/arm/plat-mxc/include/mach/ipu-v3.h b/arch/arm/plat-mxc/include/mach/ipu-v3.h
new file mode 100644
index 00000000000..0816ae9b4c4
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/ipu-v3.h
@@ -0,0 +1,710 @@
+/*
+ * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef __MACH_IPU_V3_H_
+#define __MACH_IPU_V3_H_
+
+#include <linux/ipu.h>
+
+/* IPU Driver channels definitions.	*/
+/* Note these are different from IDMA channels */
+#define IPU_MAX_CH	32
+#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
+	((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
+#define _MAKE_ALT_CHAN(ch)		(ch | (IPU_MAX_CH << 24))
+#define IPU_CHAN_ID(ch)			(ch >> 24)
+#define IPU_CHAN_ALT(ch)		(ch & 0x02000000)
+#define IPU_CHAN_ALPHA_IN_DMA(ch)	((uint32_t) (ch >> 6) & 0x3F)
+#define IPU_CHAN_GRAPH_IN_DMA(ch)	((uint32_t) (ch >> 12) & 0x3F)
+#define IPU_CHAN_VIDEO_IN_DMA(ch)	((uint32_t) (ch >> 18) & 0x3F)
+#define IPU_CHAN_OUT_DMA(ch)		((uint32_t) (ch & 0x3F))
+#define NO_DMA 0x3F
+#define ALT	1
+/*!
+ * Enumeration of IPU logical channels. An IPU logical channel is defined as a
+ * combination of an input (memory to IPU), output (IPU to memory), and/or
+ * secondary input IDMA channels and in some cases an Image Converter task.
+ * Some channels consist of only an input or output.
+ */
+typedef enum {
+	CHAN_NONE = -1,
+	MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48),
+	MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49),
+	MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50),
+
+	MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20),
+	MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21),
+	MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22),
+
+	MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
+	MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
+	MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
+	MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
+
+	MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
+	MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
+	MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
+	MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
+
+	DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
+	DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
+
+	CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0),
+	CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1),
+	CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2),
+	CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3),
+
+	CSI_MEM = CSI_MEM0,
+
+	CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20),
+	CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21),
+
+	MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21),
+	MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21),
+	MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21),
+
+	MEM_PP_ADC = CHAN_NONE,
+	ADC_SYS2 = CHAN_NONE,
+
+} ipu_channel_t;
+
+/*!
+ * Enumeration of types of buffers for a logical channel.
+ */
+typedef enum {
+	IPU_OUTPUT_BUFFER = 0,	/*!< Buffer for output from IPU */
+	IPU_ALPHA_IN_BUFFER = 1,	/*!< Buffer for input to IPU */
+	IPU_GRAPH_IN_BUFFER = 2,	/*!< Buffer for input to IPU */
+	IPU_VIDEO_IN_BUFFER = 3,	/*!< Buffer for input to IPU */
+	IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
+	IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
+} ipu_buffer_t;
+
+#define IPU_PANEL_SERIAL		1
+#define IPU_PANEL_PARALLEL		2
+
+/*!
+ * Enumeration of ADC channel operation mode.
+ */
+typedef enum {
+	Disable,
+	WriteTemplateNonSeq,
+	ReadTemplateNonSeq,
+	WriteTemplateUnCon,
+	ReadTemplateUnCon,
+	WriteDataWithRS,
+	WriteDataWoRS,
+	WriteCmd
+} mcu_mode_t;
+
+/*!
+ * Enumeration of ADC channel addressing mode.
+ */
+typedef enum {
+	FullWoBE,
+	FullWithBE,
+	XY
+} display_addressing_t;
+
+/*!
+ * Union of initialization parameters for a logical channel.
+ */
+typedef union {
+	struct {
+		uint32_t csi;
+		uint32_t mipi_id;
+		bool mipi_en;
+		bool interlaced;
+	} csi_mem;
+	struct {
+		uint32_t in_width;
+		uint32_t in_height;
+		uint32_t in_pixel_fmt;
+		uint32_t out_width;
+		uint32_t out_height;
+		uint32_t out_pixel_fmt;
+		uint32_t csi;
+	} csi_prp_enc_mem;
+	struct {
+		uint32_t in_width;
+		uint32_t in_height;
+		uint32_t in_pixel_fmt;
+		uint32_t out_width;
+		uint32_t out_height;
+		uint32_t out_pixel_fmt;
+		uint32_t outh_resize_ratio;
+		uint32_t outv_resize_ratio;
+	} mem_prp_enc_mem;
+	struct {
+		uint32_t in_width;
+		uint32_t in_height;
+		uint32_t in_pixel_fmt;
+		uint32_t out_width;
+		uint32_t out_height;
+		uint32_t out_pixel_fmt;
+	} mem_rot_enc_mem;
+	struct {
+		uint32_t in_width;
+		uint32_t in_height;
+		uint32_t in_pixel_fmt;
+		uint32_t out_width;
+		uint32_t out_height;
+		uint32_t out_pixel_fmt;
+		bool graphics_combine_en;
+		bool global_alpha_en;
+		bool key_color_en;
+		uint32_t csi;
+	} csi_prp_vf_mem;
+	struct {
+		uint32_t in_width;
+		uint32_t in_height;
+		uint32_t in_pixel_fmt;
+		uint32_t out_width;
+		uint32_t out_height;
+		uint32_t out_pixel_fmt;
+		bool graphics_combine_en;
+		bool global_alpha_en;
+		bool key_color_en;
+		display_port_t disp;
+		uint32_t out_left;
+		uint32_t out_top;
+	} csi_prp_vf_adc;
+	struct {
+		uint32_t in_width;
+		uint32_t in_height;
+		uint32_t in_pixel_fmt;
+		uint32_t out_width;
+		uint32_t out_height;
+		uint32_t out_pixel_fmt;
+		uint32_t outh_resize_ratio;
+		uint32_t outv_resize_ratio;
+		bool graphics_combine_en;
+		bool global_alpha_en;
+		bool key_color_en;
+		uint32_t in_g_pixel_fmt;
+		uint8_t alpha;
+		uint32_t key_color;
+		bool alpha_chan_en;
+		ipu_motion_sel motion_sel;
+		enum v4l2_field field_fmt;
+	} mem_prp_vf_mem;
+	struct {
+		uint32_t temp;
+	} mem_prp_vf_adc;
+	struct {
+		uint32_t temp;
+	} mem_rot_vf_mem;
+	struct {
+		uint32_t in_width;
+		uint32_t in_height;
+		uint32_t in_pixel_fmt;
+		uint32_t out_width;
+		uint32_t out_height;
+		uint32_t out_pixel_fmt;
+		uint32_t outh_resize_ratio;
+		uint32_t outv_resize_ratio;
+		bool graphics_combine_en;
+		bool global_alpha_en;
+		bool key_color_en;
+		uint32_t in_g_pixel_fmt;
+		uint8_t alpha;
+		uint32_t key_color;
+		bool alpha_chan_en;
+	} mem_pp_mem;
+	struct {
+		uint32_t temp;
+	} mem_rot_mem;
+	struct {
+		uint32_t in_width;
+		uint32_t in_height;
+		uint32_t in_pixel_fmt;
+		uint32_t out_width;
+		uint32_t out_height;
+		uint32_t out_pixel_fmt;
+		bool graphics_combine_en;
+		bool global_alpha_en;
+		bool key_color_en;
+		display_port_t disp;
+		uint32_t out_left;
+		uint32_t out_top;
+	} mem_pp_adc;
+	struct {
+		uint32_t di;
+		bool interlaced;
+		uint32_t in_pixel_fmt;
+		uint32_t out_pixel_fmt;
+	} mem_dc_sync;
+	struct {
+		uint32_t temp;
+	} mem_sdc_fg;
+	struct {
+		uint32_t di;
+		bool interlaced;
+		uint32_t in_pixel_fmt;
+		uint32_t out_pixel_fmt;
+		bool alpha_chan_en;
+	} mem_dp_bg_sync;
+	struct {
+		uint32_t temp;
+	} mem_sdc_bg;
+	struct {
+		uint32_t di;
+		bool interlaced;
+		uint32_t in_pixel_fmt;
+		uint32_t out_pixel_fmt;
+		bool alpha_chan_en;
+	} mem_dp_fg_sync;
+	struct {
+		uint32_t di;
+	} direct_async;
+	struct {
+		display_port_t disp;
+		mcu_mode_t ch_mode;
+		uint32_t out_left;
+		uint32_t out_top;
+	} adc_sys1;
+	struct {
+		display_port_t disp;
+		mcu_mode_t ch_mode;
+		uint32_t out_left;
+		uint32_t out_top;
+	} adc_sys2;
+} ipu_channel_params_t;
+
+/*!
+ * Enumeration of IPU interrupt sources.
+ */
+enum ipu_irq_line {
+	IPU_IRQ_CSI0_OUT_EOF = 0,
+	IPU_IRQ_CSI1_OUT_EOF = 1,
+	IPU_IRQ_CSI2_OUT_EOF = 2,
+	IPU_IRQ_CSI3_OUT_EOF = 3,
+	IPU_IRQ_VDI_P_IN_EOF = 8,
+	IPU_IRQ_VDI_C_IN_EOF = 9,
+	IPU_IRQ_VDI_N_IN_EOF = 10,
+	IPU_IRQ_PP_IN_EOF = 11,
+	IPU_IRQ_PRP_IN_EOF = 12,
+	IPU_IRQ_PRP_GRAPH_IN_EOF = 14,
+	IPU_IRQ_PP_GRAPH_IN_EOF = 15,
+	IPU_IRQ_PRP_ALPHA_IN_EOF = 17,
+	IPU_IRQ_PP_ALPHA_IN_EOF = 18,
+	IPU_IRQ_PRP_ENC_OUT_EOF = 20,
+	IPU_IRQ_PRP_VF_OUT_EOF = 21,
+	IPU_IRQ_PP_OUT_EOF = 22,
+	IPU_IRQ_BG_SYNC_EOF = 23,
+	IPU_IRQ_BG_ASYNC_EOF = 24,
+	IPU_IRQ_FG_SYNC_EOF = 27,
+	IPU_IRQ_DC_SYNC_EOF = 28,
+	IPU_IRQ_FG_ASYNC_EOF = 29,
+	IPU_IRQ_FG_ALPHA_SYNC_EOF = 31,
+
+	IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33,
+	IPU_IRQ_DC_READ_EOF = 40,
+	IPU_IRQ_DC_ASYNC_EOF = 41,
+	IPU_IRQ_DC_CMD1_EOF = 42,
+	IPU_IRQ_DC_CMD2_EOF = 43,
+	IPU_IRQ_DC_MASK_EOF = 44,
+	IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45,
+	IPU_IRQ_PRP_VF_ROT_IN_EOF = 46,
+	IPU_IRQ_PP_ROT_IN_EOF = 47,
+	IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48,
+	IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49,
+	IPU_IRQ_PP_ROT_OUT_EOF = 50,
+	IPU_IRQ_BG_ALPHA_SYNC_EOF = 51,
+	IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52,
+
+	IPU_IRQ_DP_SF_START = 448 + 2,
+	IPU_IRQ_DP_SF_END = 448 + 3,
+	IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END,
+	IPU_IRQ_DC_FC_0 = 448 + 8,
+	IPU_IRQ_DC_FC_1 = 448 + 9,
+	IPU_IRQ_DC_FC_2 = 448 + 10,
+	IPU_IRQ_DC_FC_3 = 448 + 11,
+	IPU_IRQ_DC_FC_4 = 448 + 12,
+	IPU_IRQ_DC_FC_6 = 448 + 13,
+	IPU_IRQ_VSYNC_PRE_0 = 448 + 14,
+	IPU_IRQ_VSYNC_PRE_1 = 448 + 15,
+
+	IPU_IRQ_COUNT
+};
+
+/*!
+ * Bitfield of Display Interface signal polarities.
+ */
+typedef struct {
+	unsigned datamask_en:1;
+	unsigned int_clk:1;
+	unsigned interlaced:1;
+	unsigned odd_field_first:1;
+	unsigned clksel_en:1;
+	unsigned clkidle_en:1;
+	unsigned data_pol:1;	/* true = inverted */
+	unsigned clk_pol:1;	/* true = rising edge */
+	unsigned enable_pol:1;
+	unsigned Hsync_pol:1;	/* true = active high */
+	unsigned Vsync_pol:1;
+} ipu_di_signal_cfg_t;
+
+/*!
+ * Bitfield of CSI signal polarities and modes.
+ */
+
+typedef struct {
+	unsigned data_width:4;
+	unsigned clk_mode:3;
+	unsigned ext_vsync:1;
+	unsigned Vsync_pol:1;
+	unsigned Hsync_pol:1;
+	unsigned pixclk_pol:1;
+	unsigned data_pol:1;
+	unsigned sens_clksrc:1;
+	unsigned pack_tight:1;
+	unsigned force_eof:1;
+	unsigned data_en_pol:1;
+	unsigned data_fmt;
+	unsigned csi;
+	unsigned mclk;
+} ipu_csi_signal_cfg_t;
+
+/*!
+ * Enumeration of CSI data bus widths.
+ */
+enum {
+	IPU_CSI_DATA_WIDTH_4,
+	IPU_CSI_DATA_WIDTH_8,
+	IPU_CSI_DATA_WIDTH_10,
+	IPU_CSI_DATA_WIDTH_16,
+};
+
+/*!
+ * Enumeration of CSI clock modes.
+ */
+enum {
+	IPU_CSI_CLK_MODE_GATED_CLK,
+	IPU_CSI_CLK_MODE_NONGATED_CLK,
+	IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
+	IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
+	IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
+	IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
+	IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
+	IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
+};
+
+enum {
+	IPU_CSI_MIPI_DI0,
+	IPU_CSI_MIPI_DI1,
+	IPU_CSI_MIPI_DI2,
+	IPU_CSI_MIPI_DI3,
+};
+
+typedef enum {
+	RGB,
+	YCbCr,
+	YUV
+} ipu_color_space_t;
+
+/*!
+ * Enumeration of ADC vertical sync mode.
+ */
+typedef enum {
+	VsyncNone,
+	VsyncInternal,
+	VsyncCSI,
+	VsyncExternal
+} vsync_t;
+
+typedef enum {
+	DAT,
+	CMD
+} cmddata_t;
+
+/*!
+ * Enumeration of ADC display update mode.
+ */
+typedef enum {
+	IPU_ADC_REFRESH_NONE,
+	IPU_ADC_AUTO_REFRESH,
+	IPU_ADC_AUTO_REFRESH_SNOOP,
+	IPU_ADC_SNOOPING,
+} ipu_adc_update_mode_t;
+
+/*!
+ * Enumeration of ADC display interface types (serial or parallel).
+ */
+enum {
+	IPU_ADC_IFC_MODE_SYS80_TYPE1,
+	IPU_ADC_IFC_MODE_SYS80_TYPE2,
+	IPU_ADC_IFC_MODE_SYS68K_TYPE1,
+	IPU_ADC_IFC_MODE_SYS68K_TYPE2,
+	IPU_ADC_IFC_MODE_3WIRE_SERIAL,
+	IPU_ADC_IFC_MODE_4WIRE_SERIAL,
+	IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK,
+	IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS,
+};
+
+enum {
+	IPU_ADC_IFC_WIDTH_8,
+	IPU_ADC_IFC_WIDTH_16,
+};
+
+/*!
+ * Enumeration of ADC display interface burst mode.
+ */
+enum {
+	IPU_ADC_BURST_WCS,
+	IPU_ADC_BURST_WBLCK,
+	IPU_ADC_BURST_NONE,
+	IPU_ADC_BURST_SERIAL,
+};
+
+/*!
+ * Enumeration of ADC display interface RW signal timing modes.
+ */
+enum {
+	IPU_ADC_SER_NO_RW,
+	IPU_ADC_SER_RW_BEFORE_RS,
+	IPU_ADC_SER_RW_AFTER_RS,
+};
+
+/*!
+ * Bitfield of ADC signal polarities and modes.
+ */
+typedef struct {
+	unsigned data_pol:1;
+	unsigned clk_pol:1;
+	unsigned cs_pol:1;
+	unsigned rs_pol:1;
+	unsigned addr_pol:1;
+	unsigned read_pol:1;
+	unsigned write_pol:1;
+	unsigned Vsync_pol:1;
+	unsigned burst_pol:1;
+	unsigned burst_mode:2;
+	unsigned ifc_mode:3;
+	unsigned ifc_width:5;
+	unsigned ser_preamble_len:4;
+	unsigned ser_preamble:8;
+	unsigned ser_rw_mode:2;
+} ipu_adc_sig_cfg_t;
+
+/*!
+ * Enumeration of ADC template commands.
+ */
+enum {
+	RD_DATA,
+	RD_ACK,
+	RD_WAIT,
+	WR_XADDR,
+	WR_YADDR,
+	WR_ADDR,
+	WR_CMND,
+	WR_DATA,
+};
+
+/*!
+ * Enumeration of ADC template command flow control.
+ */
+enum {
+	SINGLE_STEP,
+	PAUSE,
+	STOP,
+};
+
+
+/*Define template constants*/
+#define     ATM_ADDR_RANGE      0x20	/*offset address of DISP */
+#define     TEMPLATE_BUF_SIZE   0x20	/*size of template */
+
+/*!
+ * Define to create ADC template command entry.
+ */
+#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \
+			((oc) << 24) | (dat))
+
+typedef struct {
+	u32 reg;
+	u32 value;
+} ipu_lpmc_reg_t;
+
+#define IPU_LPMC_REG_READ       0x80000000L
+
+#define CSI_MCLK_VF  1
+#define CSI_MCLK_ENC 2
+#define CSI_MCLK_RAW 4
+#define CSI_MCLK_I2C 8
+
+struct ipu_soc;
+/* Common IPU API */
+struct ipu_soc *ipu_get_soc(int id);
+int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
+void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel);
+
+static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot)
+{
+#ifdef CONFIG_MXC_IPU_V3D
+	return (rot < IPU_ROTATE_HORIZ_FLIP);
+#else
+	return (rot < IPU_ROTATE_90_RIGHT);
+#endif
+}
+
+int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				ipu_rotate_mode_t rot_mode,
+				dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+				dma_addr_t phyaddr_2,
+				uint32_t u_offset, uint32_t v_offset);
+
+int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+				  uint32_t bufNum, dma_addr_t phyaddr);
+
+int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				uint32_t u, uint32_t v,
+				uint32_t vertical_offset, uint32_t horizontal_offset);
+
+int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
+			  ipu_buffer_t type, uint32_t bufNum);
+int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum);
+
+int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
+int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
+
+int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel);
+int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum);
+void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum);
+uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type);
+int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel);
+int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop);
+int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch);
+
+int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi);
+int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi);
+
+int ipu_lowpwr_display_enable(void);
+int ipu_lowpwr_display_disable(void);
+
+void ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq);
+void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq);
+void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq);
+int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
+		    irqreturn_t(*handler) (int, void *),
+		    uint32_t irq_flags, const char *devname, void *dev_id);
+void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id);
+bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq);
+void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
+
+/* two stripe calculations */
+struct stripe_param{
+	unsigned int input_width; /* width of the input stripe */
+	unsigned int output_width; /* width of the output stripe */
+	unsigned int input_column; /* the first column on the input stripe */
+	unsigned int output_column; /* the first column on the output stripe */
+	unsigned int idr;
+	/* inverse downisizing ratio parameter; expressed as a power of 2 */
+	unsigned int irr;
+	/* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */
+};
+int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
+				unsigned int output_frame_width,
+				const unsigned int maximal_stripe_width,
+				const unsigned long long cirr,
+				const unsigned int equal_stripes,
+				u32 input_pixelformat,
+				u32 output_pixelformat,
+				struct stripe_param *left,
+				struct stripe_param *right);
+
+/* SDC API */
+int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp,
+			    uint32_t pixel_clk,
+			    uint16_t width, uint16_t height,
+			    uint32_t pixel_fmt,
+			    uint16_t h_start_width, uint16_t h_sync_width,
+			    uint16_t h_end_width, uint16_t v_start_width,
+			    uint16_t v_sync_width, uint16_t v_end_width,
+			    uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
+
+void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp);
+
+int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos,
+				int16_t y_pos);
+int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos,
+				int16_t *y_pos);
+int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
+				  uint8_t alpha);
+int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
+			       uint32_t colorKey);
+int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
+				int constk[], int slopek[]);
+
+int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
+			 uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig);
+void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset);
+void ipu_reset_disp_panel(struct ipu_soc *ipu);
+
+/* CMOS Sensor Interface API */
+int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
+			       uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig);
+
+int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi);
+
+int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait);
+
+static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi,
+		bool flag, bool wait)
+{
+	return ipu_csi_enable_mclk(ipu, csi, flag, wait);
+}
+
+int ipu_csi_read_mclk_flag(void);
+
+void ipu_csi_flash_strobe(bool flag);
+
+void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi);
+
+void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi);
+
+void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi);
+
+uint32_t bytes_per_pixel(uint32_t fmt);
+
+struct ipuv3_fb_platform_data {
+	char				disp_dev[32];
+	u32				interface_pix_fmt;
+	char				*mode_str;
+	int				default_bpp;
+	bool				int_clk;
+
+	/* reserved mem */
+	resource_size_t 		res_base;
+	resource_size_t 		res_size;
+};
+
+struct imx_ipuv3_platform_data {
+	int rev;
+	int (*init) (int);
+	void (*pg) (int);
+
+	char *csi_clk[2];
+};
+
+#endif /* __MACH_IPU_V3_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h
index a9221f1cc1a..f7344ab81e4 100644
--- a/arch/arm/plat-mxc/include/mach/ipu.h
+++ b/arch/arm/plat-mxc/include/mach/ipu.h
@@ -14,6 +14,7 @@
 
 #include <linux/types.h>
 #include <linux/dmaengine.h>
+#include <linux/ipu.h>
 
 /* IPU DMA Controller channel definitions. */
 enum ipu_channel {
@@ -95,35 +96,10 @@ enum ipu_color_space {
 	IPU_COLORSPACE_YUV
 };
 
-/*
- * Enumeration of IPU rotation modes
- */
-enum ipu_rotate_mode {
-	/* Note the enum values correspond to BAM value */
-	IPU_ROTATE_NONE = 0,
-	IPU_ROTATE_VERT_FLIP = 1,
-	IPU_ROTATE_HORIZ_FLIP = 2,
-	IPU_ROTATE_180 = 3,
-	IPU_ROTATE_90_RIGHT = 4,
-	IPU_ROTATE_90_RIGHT_VFLIP = 5,
-	IPU_ROTATE_90_RIGHT_HFLIP = 6,
-	IPU_ROTATE_90_LEFT = 7,
-};
-
 struct ipu_platform_data {
 	unsigned int	irq_base;
 };
 
-/*
- * Enumeration of DI ports for ADC.
- */
-enum display_port {
-	DISP0,
-	DISP1,
-	DISP2,
-	DISP3
-};
-
 struct idmac_video_param {
 	unsigned short		in_width;
 	unsigned short		in_height;
@@ -135,7 +111,7 @@ struct idmac_video_param {
 	bool			graphics_combine_en;
 	bool			global_alpha_en;
 	bool			key_color_en;
-	enum display_port	disp;
+	display_port_t		disp;
 	unsigned short		out_left;
 	unsigned short		out_top;
 };
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
index 5f2da75a47f..aea89f27471 100644
--- a/arch/arm/plat-mxc/include/mach/mx50.h
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -21,7 +21,33 @@
 /*
  * Databahn
  */
-#define MX50_DATABAHN_BASE_ADDR			0x14000000
+#define MX50_DATABAHN_BASE_ADDR		0x14000000
+#define DATABAHN_CTL_REG19		0x4c
+#define DATABAHN_CTL_REG20		0x50
+#define DATABAHN_CTL_REG21		0x54
+#define DATABAHN_CTL_REG22		0x58
+#define DATABAHN_CTL_REG23		0x5c
+#define DATABAHN_CTL_REG42		0xa8
+#define DATABAHN_CTL_REG43		0xac
+#define DATABAHN_CTL_REG55		0xdc
+#define DATABAHN_CTL_REG63		0xFC
+#define DATABAHN_CTL_REG73		0x124
+#define DATABAHN_CTL_REG74		0x128
+#define DATABAHN_CTL_REG75		0x12C
+#define DATABAHN_CTL_REG83		0x14C
+#define LOWPOWER_CONTROL_MASK	 	0x1F
+#define LOWPOWER_AUTOENABLE_MASK 	0x1F
+#define LOWPOWER_EXTERNAL_CNT_MASK	(0xFFFF << 16)
+#define LOWPOWER_EXTERNAL_CNT_OFFSET	16
+#define LOWPOWER_INTERNAL_CNT_MASK	(0xFFFF << 8)
+#define LOWPOWER_INTERNAL_CNT_OFFSET	8
+#define LOWPOWER_REFRESH_ENABLE_MASK	(3 << 16)
+#define LOWPOWER_REFRESH_ENABLE_OFFSET	16
+#define LOWPOWER_REFRESH_HOLD_MASK	0xFFFF
+#define LOWPOWER_REFRESH_HOLD_OFFSET	0
+#define MX50_LPDDR2			(0x5 << 8)
+#define MX50_MDDR			(0x1 << 8)
+
 
 /*
  * Graphics Memory of GPU
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index cdf07c65ec1..d198524cfe7 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -14,8 +14,9 @@
 #define MX51_IRAM_PARTITIONS		16
 #define MX51_IRAM_SIZE		(MX51_IRAM_PARTITIONS * SZ_8K)	/* 128KB */
 
-#define MX51_GPU_BASE_ADDR		0x20000000
-#define MX51_GPU_CTRL_BASE_ADDR		0x30000000
+#define MX51_GPU_GMEM_BASE_ADDR		0x20000000
+#define MX51_GPU_GMEM_SIZE		SZ_128K
+#define MX51_GPU_BASE_ADDR		0x30000000
 #define MX51_IPU_CTRL_BASE_ADDR		0x40000000
 
 /*
@@ -128,6 +129,18 @@
 #define MX51_IO_P2V(x)			IMX_IO_P2V(x)
 #define MX51_IO_ADDRESS(x)		IOMEM(MX51_IO_P2V(x))
 
+/* PGC */
+#define MX51_GPC_BASE		(MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR))
+#define MX51_PGC_IPU_BASE	(MX51_GPC_BASE + 0x220)
+#define MX51_PGC_VPU_BASE	(MX51_GPC_BASE + 0x240)
+#define MX51_PGC_GPU_BASE	(MX51_GPC_BASE + 0x260)
+#define MX51_PGC_IPU_PGCR	(MX51_PGC_IPU_BASE + 0x0)
+#define MX51_PGC_IPU_PGSR	(MX51_PGC_IPU_BASE + 0xC)
+#define MX51_PGC_VPU_PGCR	(MX51_PGC_VPU_BASE + 0x0)
+#define MX51_PGC_VPU_PGSR	(MX51_PGC_VPU_BASE + 0xC)
+#define MX51_PGC_GPU_PGCR	(MX51_PGC_GPU_BASE + 0x0)
+#define MX51_PGC_GPU_PGSR	(MX51_PGC_GPU_BASE + 0xC)
+
 /*
  * defines for SPBA modules
  */
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index a37e8c35399..1f5097a2ed2 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -33,9 +33,10 @@
  * Graphics Memory of GPU
  */
 #define MX53_IPU_CTRL_BASE_ADDR	0x18000000
-#define MX53_GPU2D_BASE_ADDR		0x20000000
-#define MX53_GPU_BASE_ADDR		0x30000000
+#define MX53_GPU2D_BASE_ADDR	0x20000000
+#define MX53_GPU_BASE_ADDR	0x30000000
 #define MX53_GPU_GMEM_BASE_ADDR	0xF8020000
+#define MX53_GPU_GMEM_SIZE	SZ_256K
 
 #define MX53_DEBUG_BASE_ADDR		0x40000000
 #define MX53_DEBUG_SIZE		SZ_1M
@@ -158,6 +159,18 @@
 #define MX53_IO_P2V(x)			IMX_IO_P2V(x)
 #define MX53_IO_ADDRESS(x)		IOMEM(MX53_IO_P2V(x))
 
+/* PGC */
+#define MX53_GPC_BASE		(MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR))
+#define MX53_PGC_IPU_BASE	(MX53_GPC_BASE + 0x220)
+#define MX53_PGC_VPU_BASE	(MX53_GPC_BASE + 0x240)
+#define MX53_PGC_GPU_BASE	(MX53_GPC_BASE + 0x260)
+#define MX53_PGC_IPU_PGCR	(MX53_PGC_IPU_BASE + 0x0)
+#define MX53_PGC_IPU_PGSR	(MX53_PGC_IPU_BASE + 0xC)
+#define MX53_PGC_VPU_PGCR	(MX53_PGC_VPU_BASE + 0x0)
+#define MX53_PGC_VPU_PGSR	(MX53_PGC_VPU_BASE + 0xC)
+#define MX53_PGC_GPU_PGCR	(MX53_PGC_GPU_BASE + 0x0)
+#define MX53_PGC_GPU_PGSR	(MX53_PGC_GPU_BASE + 0xC)
+
 /*
  * defines for SPBA modules
  */
@@ -338,4 +351,14 @@
 #define MX53_INT_GPIO7_LOW	107
 #define MX53_INT_GPIO7_HIGH	108
 
+/*!
+ * IIM bank info
+ */
+#define MXC_IIM_MX51_BANK_START_ADDR 0x0800
+#define MXC_IIM_MX51_BANK_END_ADDR   0x147c
+#define MXC_IIM_MX53_BANK_START_ADDR 0x0800
+#define MXC_IIM_MX53_BANK_END_ADDR   0x183c
+#define MXC_IIM_MX53_BANK_AREA_1_OFFSET 0xc00
+#define MXC_IIM_MX53_MAC_ADDR_OFFSET    0x24
+
 #endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a4d36d601d5..eb49d7114ca 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -50,6 +50,36 @@
 #define IMX_CHIP_REVISION_3_3		0x33
 #define IMX_CHIP_REVISION_UNKNOWN	0xff
 
+#define IMX_CHIP_REVISION_1_0_STRING		"1.0"
+#define IMX_CHIP_REVISION_1_1_STRING		"1.1"
+#define IMX_CHIP_REVISION_1_2_STRING		"1.2"
+#define IMX_CHIP_REVISION_1_3_STRING		"1.3"
+#define IMX_CHIP_REVISION_2_0_STRING		"2.0"
+#define IMX_CHIP_REVISION_2_1_STRING		"2.1"
+#define IMX_CHIP_REVISION_2_2_STRING		"2.2"
+#define IMX_CHIP_REVISION_2_3_STRING		"2.3"
+#define IMX_CHIP_REVISION_3_0_STRING		"3.0"
+#define IMX_CHIP_REVISION_3_1_STRING		"3.1"
+#define IMX_CHIP_REVISION_3_2_STRING		"3.2"
+#define IMX_CHIP_REVISION_3_3_STRING		"3.3"
+#define IMX_CHIP_REVISION_UNKNOWN_STRING	"unknown"
+
+#define IMX_BOARD_REV_1		0x000
+#define IMX_BOARD_REV_2		0x100
+#define IMX_BOARD_REV_3		0x200
+
+#ifndef __ASSEMBLY__
+extern unsigned int system_rev;
+#define board_is_rev(rev)	(((system_rev & 0x0F00) == rev) ? 1 : 0)
+#define imx_cpu_ver()		(system_rev & 0xFF)
+#endif
+
+#ifdef CONFIG_ARCH_MX5
+#define board_is_mx53_arm2() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_2))
+#define board_is_mx53_evk_a()    (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_1))
+#define board_is_mx53_evk_b()    (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_3))
+#endif
+
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
 #endif
@@ -162,18 +192,37 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx53()		(0)
 #endif
 
+#define cpu_is_mx6q()		(0)
+
 #ifndef __ASSEMBLY__
 
+#include <mach/common.h>
+
 struct cpu_op {
+	u32 pll_reg;
+	u32 pll_rate;
 	u32 cpu_rate;
+	u32 pdr0_reg;
+	u32 pdf;
+	u32 mfi;
+	u32 mfd;
+	u32 mfn;
+	u32 cpu_voltage;
+	u32 cpu_podf;
 };
 
 int tzic_enable_wake(int is_idle);
 
+extern void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 extern struct cpu_op *(*get_cpu_op)(int *op);
 #endif
 
 #define cpu_is_mx3()	(cpu_is_mx31() || cpu_is_mx35())
 #define cpu_is_mx2()	(cpu_is_mx21() || cpu_is_mx27())
 
+#define MXC_PGCR_PCR		1
+#define MXC_SRPGCR_PCR		1
+#define MXC_EMPGCR_PCR		1
+#define MXC_PGSR_PSR		1
+
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
new file mode 100644
index 00000000000..35aefaa8796
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver
+ */
+
+/*!
+ * @file arch-mxc/mxc_dvfs.h
+ *
+ * @brief This file contains the DVFS configuration structure definition.
+ *
+ *
+ * @ingroup DVFS
+ */
+
+#ifndef __ASM_ARCH_MXC_DVFS_H__
+#define __ASM_ARCH_MXC_DVFS_H__
+
+#ifdef __KERNEL__
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+#include <linux/device.h>
+
+extern void __iomem *gpc_base;
+extern void __iomem *ccm_base;
+
+#define MXC_GPCCNTR_GPCIRQ2M		(1 << 25)
+#define MXC_GPCCNTR_GPCIRQ2		(1 << 24)
+#define MXC_GPCCNTR_GPCIRQM		(1 << 21)
+#define MXC_GPCCNTR_GPCIRQ_ARM	(1 << 20)
+#define MXC_GPCCNTR_GPCIRQ_SDMA	(0 << 20)
+#define MXC_GPCCNTR_DVFS0CR		(1 << 16)
+#define MXC_GPCCNTR_DVFS1CR		(1 << 17)
+#define MXC_GPCCNTR_ADU_MASK		0x8000
+#define MXC_GPCCNTR_ADU			(1 << 15)
+#define MXC_GPCCNTR_STRT			(1 << 14)
+#define MXC_GPCCNTR_FUPD_MASK	0x2000
+#define MXC_GPCCNTR_FUPD			(1 << 13)
+#define MXC_GPCCNTR_HTRI_MASK		0x0000000F
+#define MXC_GPCCNTR_HTRI_OFFSET	0
+
+#define MXC_GPCVCR_VINC_MASK		0x00020000
+#define MXC_GPCVCR_VINC_OFFSET	17
+#define MXC_GPCVCR_VCNTU_MASK	0x00010000
+#define MXC_GPCVCR_VCNTU_OFFSET	16
+#define MXC_GPCVCR_VCNT_MASK		0x00007FFF
+#define MXC_GPCVCR_VCNT_OFFSET	0
+
+/* DVFS-PER */
+#define MXC_DVFSPER_PMCR0_UDCS			(1 << 27)
+#define MXC_DVFSPER_PMCR0_UDCS_MASK		0x8000000
+#define MXC_DVFSPER_PMCR0_ENABLE_MASK	0x10
+#define MXC_DVFSPER_PMCR0_ENABLE			(1 << 4)
+
+#define MXC_DVFSLTR0_UPTHR_MASK		0x0FC00000
+#define MXC_DVFSLTR0_UPTHR_OFFSET	22
+#define MXC_DVFSLTR0_DNTHR_MASK		0x003F0000
+#define MXC_DVFSLTR0_DNTHR_OFFSET	16
+
+#define MXC_DVFSLTR1_PNCTHR_MASK	0x0000003F
+#define MXC_DVFSLTR1_PNCTHR_OFFSET	0
+#define MXC_DVFSLTR1_DNCNT_MASK		0x003FC000
+#define MXC_DVFSLTR1_DNCNT_OFFSET	14
+#define MXC_DVFSLTR1_UPCNT_MASK		0x00003FC0
+#define MXC_DVFSLTR1_UPCNT_OFFSET	6
+#define MXC_DVFSLTR1_LTBRSR		0x800000
+#define MXC_DVFSLTR1_LTBRSH		0x400000
+
+#define MXC_DVFSLTR2_EMAC_MASK		0x000001FF
+#define MXC_DVFSLTR2_EMAC_OFFSET	0
+
+#define MXC_DVFSPMCR0_UDCS		0x8000000
+#define MXC_DVFSPMCR0_DVFEV		0x800000
+#define MXC_DVFSPMCR0_DVFIS		0x400000
+#define MXC_DVFSPMCR0_LBMI		0x200000
+#define MXC_DVFSPMCR0_LBFL		0x100000
+#define MXC_DVFSPMCR0_LBFC_MASK		0xC0000
+#define MXC_DVFSPMCR0_LBFC_OFFSET	18
+#define MXC_DVFSPMCR0_FSVAIM		0x00008000
+#define MXC_DVFSPMCR0_FSVAI_MASK	0x00006000
+#define MXC_DVFSPMCR0_FSVAI_OFFSET	13
+#define MXC_DVFSPMCR0_WFIM		0x00000400
+#define MXC_DVFSPMCR0_WFIM_OFFSET	10
+#define MXC_DVFSPMCR0_DVFEN		0x00000010
+
+#define MXC_DVFSPMCR1_P1INM		0x00100000
+#define MXC_DVFSPMCR1_P1ISM		0x00080000
+#define MXC_DVFSPMCR1_P1IFM		0x00040000
+#define MXC_DVFSPMCR1_P4PM		0x00020000
+#define MXC_DVFSPMCR1_P2PM		0x00010000
+
+/* DVFS CORE register offsets*/
+#define MXC_DVFSCORE_THRS		0x00
+#define MXC_DVFSCORE_COUN		0x04
+#define MXC_DVFSCORE_SIG1		0x08
+#define MXC_DVFSCORE_SIG0		0x0C
+#define MXC_DVFSCORE_GPC0		0x10
+#define MXC_DVFSCORE_GPC1		0x14
+#define MXC_DVFSCORE_GPBT		0x18
+#define MXC_DVFSCORE_EMAC		0x1C
+#define MXC_DVFSCORE_CNTR		0x20
+#define MXC_DVFSCORE_LTR0_0		0x24
+#define MXC_DVFSCORE_LTR0_1		0x28
+#define MXC_DVFSCORE_LTR1_0		0x2C
+#define MXC_DVFSCORE_LTR1_1		0x30
+#define MXC_DVFSCORE_PT0 		0x34
+#define MXC_DVFSCORE_PT1 		0x38
+#define MXC_DVFSCORE_PT2 		0x3C
+#define MXC_DVFSCORE_PT3 		0x40
+
+/*
+ * DVFS structure
+ */
+struct dvfs_wp {
+	int upthr;
+	int downthr;
+	int panicthr;
+	int upcnt;
+	int downcnt;
+	int emac;
+};
+
+struct mxc_dvfs_platform_data {
+	/** Supply voltage regulator name string */
+	char *reg_id;
+	/* CPU clock name string */
+	char *clk1_id;
+	/* DVFS clock name string */
+	char *clk2_id;
+	/* The base address of the DVFS core */
+	void __iomem *membase;
+	/* The interrupt number used by the DVFS core */
+	int irq;
+	/* GPC control reg offset */
+	int gpc_cntr_offset;
+	/* GPC voltage counter reg offset */
+	int gpc_vcr_offset;
+	/* CCM DVFS control reg offset */
+	int ccm_cdcr_offset;
+	/* CCM ARM clock root reg offset */
+	int ccm_cacrr_offset;
+	/* CCM divider handshake in-progress reg offset */
+	int ccm_cdhipr_offset;
+	/* PREDIV mask */
+	u32 prediv_mask;
+	/* PREDIV offset */
+	int prediv_offset;
+	/* PREDIV value */
+	int prediv_val;
+	/* DIV3CK mask */
+	u32 div3ck_mask;
+	/* DIV3CK offset */
+	int div3ck_offset;
+	/* DIV3CK value */
+	int div3ck_val;
+	/* EMAC value */
+	int emac_val;
+	/* Frequency increase threshold. Increase frequency change request
+	   will be sent if DVFS counter value will be more than this value */
+	int upthr_val;
+	/* Frequency decrease threshold. Decrease frequency change request
+	   will be sent if DVFS counter value will be less than this value */
+	int dnthr_val;
+	/* Panic threshold. Panic frequency change request
+	   will be sent if DVFS counter value will be more than this value */
+	int pncthr_val;
+	/* The amount of times the up threshold should be exceeded
+	   before DVFS will trigger frequency increase request */
+	int upcnt_val;
+	/* The amount of times the down threshold should be exceeded
+	   before DVFS will trigger frequency decrease request */
+	int dncnt_val;
+	/* Delay time in us */
+	int delay_time;
+	/* Number of woking points supported */
+	int num_wp;
+};
+
+/*!
+ * This structure is used to define the dvfs controller's platform
+ * data. It includes the regulator name string and DVFS clock name string.
+ */
+struct mxc_dvfsper_data {
+	/** Regulator name string */
+	char *reg_id;
+	/* DVFS clock name string */
+	char *clk_id;
+	/* The base address of the DVFS per */
+	void __iomem *membase;
+	/* GPC control reg address */
+	void __iomem *gpc_cntr_reg_addr;
+	/* GPC VCR reg address */
+	void __iomem *gpc_vcr_reg_addr;
+	/* DVFS enable bit */
+	u32 dvfs_enable_bit;
+	/* DVFS ADU bit */
+	int gpc_adu;
+	/* VAI mask */
+	u32 vai_mask;
+	/* VAI offset */
+	int vai_offset;
+	/* Mask DVFS interrupt */
+	u32 irq_mask;
+	/* Div3 clock offset. */
+	u32 div3_offset;
+	/*div3 clock mask. */
+	u32 div3_mask;
+	/*div3 clock divider */
+	u32 div3_div;
+	/* LP voltage - high setpoint*/
+	u32 lp_high;
+	/* LP voltage - low setpoint*/
+	u32 lp_low;
+};
+
+/*!
+ * This structure is used to define the platform data of bus freq
+ * driver. It includes the regulator name strings.
+ */
+
+struct mxc_bus_freq_platform_data {
+	/* VDDGP regulator name */
+	char *gp_reg_id;
+	/* VCC regulator name */
+	char *lp_reg_id;
+};
+
+#if defined(CONFIG_MXC_DVFS_PER)
+extern int start_dvfs_per(void);
+extern void stop_dvfs_per(void);
+extern int dvfs_per_active(void);
+extern int dvfs_per_divider_active(void);
+extern int dvfs_per_pixel_clk_limit(void);
+#else
+static inline int start_dvfs_per(void)
+{
+	return 0;
+}
+
+static inline void stop_dvfs_per(void)
+{
+}
+
+static inline int dvfs_per_active(void)
+{
+	return 0;
+}
+
+static inline int dvfs_per_divider_active(void)
+{
+	return 0;
+}
+
+static inline int dvfs_per_pixel_clk_limit(void)
+{
+	return 0;
+}
+
+#endif
+
+#endif				/* __KERNEL__ */
+
+#endif				/* __ASM_ARCH_MXC_DVFS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_gpu.h b/arch/arm/plat-mxc/include/mach/mxc_gpu.h
new file mode 100644
index 00000000000..a43d6ec99bf
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_gpu.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef __MACH_MXC_GPU_H_
+#define __MACH_MXC_GPU_H_
+
+struct mxc_gpu_platform_data {
+	int z160_revision;
+	resource_size_t reserved_mem_base;
+	resource_size_t reserved_mem_size;
+};
+
+#endif /* __MACH_MXC_GPU_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
new file mode 100644
index 00000000000..0f81fb9eb7d
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+/*!
+ * @defgroup VPU Video Processor Unit Driver
+ */
+
+/*!
+ * @file arch-mxc/mxc_vpu.h
+ *
+ * @brief VPU system initialization and file operation definition
+ *
+ * @ingroup VPU
+ */
+
+#ifndef __ASM_ARCH_MXC_VPU_H__
+#define __ASM_ARCH_MXC_VPU_H__
+
+#include <linux/fs.h>
+
+struct mxc_vpu_platform_data {
+	bool iram_enable;
+	int  iram_size;
+	void (*reset) (void);
+	void (*pg) (int);
+};
+
+struct vpu_mem_desc {
+	u32 size;
+	dma_addr_t phy_addr;
+	u32 cpu_addr;		/* cpu address to free the dma mem */
+	u32 virt_uaddr;		/* virtual user space address */
+};
+
+#define VPU_IOC_MAGIC  'V'
+
+#define VPU_IOC_PHYMEM_ALLOC	_IO(VPU_IOC_MAGIC, 0)
+#define VPU_IOC_PHYMEM_FREE	_IO(VPU_IOC_MAGIC, 1)
+#define VPU_IOC_WAIT4INT	_IO(VPU_IOC_MAGIC, 2)
+#define VPU_IOC_PHYMEM_DUMP	_IO(VPU_IOC_MAGIC, 3)
+#define VPU_IOC_REG_DUMP	_IO(VPU_IOC_MAGIC, 4)
+#define VPU_IOC_IRAM_SETTING	_IO(VPU_IOC_MAGIC, 6)
+#define VPU_IOC_CLKGATE_SETTING	_IO(VPU_IOC_MAGIC, 7)
+#define VPU_IOC_GET_WORK_ADDR   _IO(VPU_IOC_MAGIC, 8)
+#define VPU_IOC_REQ_VSHARE_MEM	_IO(VPU_IOC_MAGIC, 9)
+#define VPU_IOC_SYS_SW_RESET	_IO(VPU_IOC_MAGIC, 11)
+#define VPU_IOC_GET_SHARE_MEM   _IO(VPU_IOC_MAGIC, 12)
+
+#define BIT_CODE_RUN			0x000
+#define BIT_CODE_DOWN			0x004
+#define	BIT_INT_CLEAR			0x00C
+#define	BIT_INT_STATUS			0x010
+
+#define MJPEG_PIC_STATUS_REG		0x3004
+
+#define BIT_WORK_CTRL_BUF_BASE		0x100
+#define BIT_WORK_CTRL_BUF_REG(i)	(BIT_WORK_CTRL_BUF_BASE + i * 4)
+#define BIT_CODE_BUF_ADDR		BIT_WORK_CTRL_BUF_REG(0)
+#define BIT_WORK_BUF_ADDR		BIT_WORK_CTRL_BUF_REG(1)
+#define BIT_PARA_BUF_ADDR		BIT_WORK_CTRL_BUF_REG(2)
+#define BIT_BIT_STREAM_CTRL		BIT_WORK_CTRL_BUF_REG(3)
+#define BIT_FRAME_MEM_CTRL		BIT_WORK_CTRL_BUF_REG(4)
+#define BIT_BIT_STREAM_PARAM		BIT_WORK_CTRL_BUF_REG(5)
+
+#define BIT_RESET_CTRL			0x11C
+
+/* i could be 0, 1, 2, 3 */
+#define	BIT_RD_PTR_BASE			0x120
+#define BIT_RD_PTR_REG(i)		(BIT_RD_PTR_BASE + i * 8)
+#define BIT_WR_PTR_REG(i)		(BIT_RD_PTR_BASE + i * 8 + 4)
+
+/* i could be 0, 1, 2, 3 */
+#define BIT_FRM_DIS_FLG_BASE		(cpu_is_mx51() ? 0x150 : 0x140)
+#define	BIT_FRM_DIS_FLG_REG(i)		(BIT_FRM_DIS_FLG_BASE + i * 4)
+
+#define BIT_BUSY_FLAG			0x160
+#define BIT_RUN_COMMAND			0x164
+#define BIT_INT_ENABLE			0x170
+
+#define	BITVAL_PIC_RUN			8
+
+#define	VPU_SLEEP_REG_VALUE		10
+#define	VPU_WAKE_REG_VALUE		11
+
+int vl2cc_init(u32 vl2cc_hw_base);
+void vl2cc_enable(void);
+void vl2cc_flush(void);
+void vl2cc_disable(void);
+void vl2cc_cleanup(void);
+
+int vl2cc_init(u32 vl2cc_hw_base);
+void vl2cc_enable(void);
+void vl2cc_flush(void);
+void vl2cc_disable(void);
+void vl2cc_cleanup(void);
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/sdram_autogating.h b/arch/arm/plat-mxc/include/mach/sdram_autogating.h
new file mode 100644
index 00000000000..e102add8a4c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/sdram_autogating.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver
+ */
+
+/*!
+ * @file arch-mxc/sdram_autogating.h
+ *
+ * @brief This file contains the SDRAM autogating function prototypes
+ *
+ *
+ * @ingroup PM
+ */
+
+#ifndef __ASM_ARCH_SDRAM_AUTOGATING_H__
+#define __ASM_ARCH_SDRAM_AUTOGATING_H__
+
+#ifdef __KERNEL__
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+#include <linux/device.h>
+
+
+#ifdef CONFIG_ARCH_MX5
+extern void start_sdram_autogating(void);
+extern void stop_sdram_autogating(void);
+extern int sdram_autogating_active(void);
+#else
+static inline void start_sdram_autogating(void)
+{}
+
+static inline void stop_sdram_autogating(void)
+{}
+
+static inline int sdram_autogating_active(void)
+{
+	return 0;
+}
+#endif
+
+#endif				/*__KERNEL__ */
+#endif				/* __ASM_ARCH_MXC_DVFS_H__ */
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 4b0fe285e83..dd6b74e378c 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -57,6 +57,7 @@
 /* MX31, MX35, MX25, MX5 */
 #define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
 #define V2_TCTL_CLK_IPG		(1 << 6)
+#define V2_TCTL_CLK_PER		(2 << 6)
 #define V2_TCTL_FRR		(1 << 9)
 #define V2_IR			0x0c
 #define V2_TSTAT		0x08
@@ -304,7 +305,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 
 	if (timer_is_v2())
-		tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
+		tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
 	else
 		tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
 
diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c
new file mode 100644
index 00000000000..716a03d212e
--- /dev/null
+++ b/arch/arm/plat-mxc/usb_common.c
@@ -0,0 +1,876 @@
+/*
+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ *@defgroup USB ARC OTG USB Driver
+ */
+
+/*!
+ * @file usb_common.c
+ *
+ * @brief platform related part of usb driver.
+ * @ingroup USB
+ */
+
+/*!
+ *Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/fsl_xcvr.h>
+#include <linux/regulator/consumer.h>
+#include <mach/arc_otg.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+void __iomem *imx_otg_base;
+
+#define MXC_NUMBER_USB_TRANSCEIVER 6
+struct fsl_xcvr_ops *g_xc_ops[MXC_NUMBER_USB_TRANSCEIVER] = { NULL };
+
+enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata)
+{
+	enum fsl_usb2_modes mode;
+	mode = FSL_USB_UNKNOWN;
+
+	if (!strcmp("DR", pdata->name)) {
+		if ((UOG_USBMODE & 0x3) == 0x2)
+			mode = FSL_USB_DR_DEVICE;
+		else if ((UOG_USBMODE & 0x3) == 0x3)
+			mode = FSL_USB_DR_HOST;
+	} else if (!strcmp("Host 1", pdata->name))
+		mode = FSL_USB_MPH_HOST1;
+	else if (!strcmp("Host 2", pdata->name))
+		mode = FSL_USB_MPH_HOST2;
+
+	if (mode == FSL_USB_UNKNOWN)
+		printk(KERN_ERR "unknow usb mode,name is %s\n", pdata->name);
+	return mode;
+}
+
+static struct clk *usb_clk;
+static struct clk *usb_ahb_clk;
+
+
+/*
+ * make sure USB_CLK is running at 60 MHz +/- 1000 Hz
+ */
+static int fsl_check_usbclk(void)
+{
+	unsigned long freq;
+
+	usb_ahb_clk = clk_get(NULL, "usb_ahb_clk");
+	if (clk_enable(usb_ahb_clk)) {
+		printk(KERN_ERR "clk_enable(usb_ahb_clk) failed\n");
+		return -EINVAL;
+	}
+	clk_put(usb_ahb_clk);
+
+	usb_clk = clk_get(NULL, "usb_clk");
+	freq = clk_get_rate(usb_clk);
+	clk_put(usb_clk);
+	if ((freq < 59999000) || (freq > 60001000)) {
+		printk(KERN_ERR "USB_CLK=%lu, should be 60MHz\n", freq);
+		return -1;
+	}
+
+	return 0;
+}
+
+void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops)
+{
+	int i;
+
+	for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) {
+		if (g_xc_ops[i] == NULL) {
+			g_xc_ops[i] = xcvr_ops;
+			return;
+		}
+	}
+}
+EXPORT_SYMBOL(fsl_usb_xcvr_register);
+
+void fsl_platform_set_test_mode (struct fsl_usb2_platform_data *pdata, enum usb_test_mode mode)
+{
+	if (pdata->xcvr_ops && pdata->xcvr_ops->set_test_mode)
+		pdata->xcvr_ops->set_test_mode((u32 *)(pdata->regs + ULPIVW_OFF), mode);
+}
+EXPORT_SYMBOL(fsl_platform_set_test_mode);
+
+void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops)
+{
+	int i;
+
+	for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) {
+		if (g_xc_ops[i] == xcvr_ops) {
+			g_xc_ops[i] = NULL;
+			return;
+		}
+	}
+}
+EXPORT_SYMBOL(fsl_usb_xcvr_unregister);
+
+static struct fsl_xcvr_ops *fsl_usb_get_xcvr(char *name)
+{
+	int i;
+
+	if (name == NULL) {
+		pr_err("get_xcvr(): No tranceiver name\n");
+		return NULL;
+	}
+
+	for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) {
+		if (g_xc_ops[i] == NULL)
+			continue;
+		if (strcmp(g_xc_ops[i]->name, name) == 0) {
+			return g_xc_ops[i];
+		}
+	}
+	return NULL;
+}
+
+/* The dmamask must be set for EHCI to work */
+static u64 ehci_dmamask = ~(u32) 0;
+
+/*!
+ * Register an instance of a USB host platform device.
+ *
+ * @param	res:	resource pointer
+ * @param       n_res:	number of resources
+ * @param       config: config pointer
+ *
+ * @return      newly-registered platform_device
+ *
+ * The USB controller supports 3 host interfaces, and the
+ * kernel can be configured to support some number of them.
+ * Each supported host interface is registered as an instance
+ * of the "fsl-ehci" device.  Call this function multiple times
+ * to register each host interface.
+ */
+static int usb_mxc_instance_id;
+__init struct platform_device *host_pdev_register(struct resource *res, int n_res,
+					   struct fsl_usb2_platform_data *config)
+{
+	struct platform_device *pdev;
+	int rc;
+
+	pdev = platform_device_register_simple("fsl-ehci",
+			 usb_mxc_instance_id, res, n_res);
+	if (IS_ERR(pdev)) {
+		pr_debug("can't register %s Host, %ld\n",
+			 config->name, PTR_ERR(pdev));
+		return NULL;
+	}
+
+	pdev->dev.coherent_dma_mask = 0xffffffff;
+	pdev->dev.dma_mask = &ehci_dmamask;
+
+	/*
+	 * platform_device_add_data() makes a copy of
+	 * the platform_data passed in.  That makes it
+	 * impossible to share the same config struct for
+	 * all OTG devices (host,gadget,otg).  So, just
+	 * set the platorm_data pointer ourselves.
+	 */
+	rc = platform_device_add_data(pdev, config,
+				      sizeof(struct fsl_usb2_platform_data));
+	if (rc) {
+		platform_device_unregister(pdev);
+		return NULL;
+	}
+
+	printk(KERN_INFO "usb: %s host (%s) registered\n", config->name,
+	       config->transceiver);
+
+	usb_mxc_instance_id++;
+
+	return pdev;
+}
+
+static void usbh1_set_serial_xcvr(void)
+{
+	USBCTRL &= ~(UCTRL_H1SIC_MASK | UCTRL_BPE); /* disable bypass mode */
+	USBCTRL |= UCTRL_H1SIC_SU6 |		/* single-ended / unidir. */
+		   UCTRL_H1WIE | UCTRL_H1DT |	/* disable H1 TLL */
+		   UCTRL_H1PM;			/* power mask */
+}
+
+static void usbh1_set_ulpi_xcvr(void)
+{
+	/* Stop then Reset */
+	UH1_USBCMD &= ~UCMD_RUN_STOP;
+	while (UH1_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UH1_USBCMD |= UCMD_RESET;
+	while (UH1_USBCMD & UCMD_RESET)
+		;
+
+	/* Select the clock from external PHY */
+	USB_CTRL_1 |= USB_CTRL_UH1_EXT_CLK_EN;
+
+	/* select ULPI PHY PTS=2 */
+	UH1_PORTSC1 = (UH1_PORTSC1 & ~PORTSC_PTS_MASK) | PORTSC_PTS_ULPI;
+
+	USBCTRL &= ~UCTRL_H1WIE; /* HOST1 wakeup intr disable */
+	USBCTRL &= ~UCTRL_H1UIE; /* Host1 ULPI interrupt disable */
+	USBCTRL |= UCTRL_H1PM; /* HOST1 power mask */
+	USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS; /* OC is not used */
+
+	/* Interrupt Threshold Control:Immediate (no threshold) */
+	UH1_USBCMD &= UCMD_ITC_NO_THRESHOLD;
+
+	UH1_USBCMD |= UCMD_RESET;       /* reset the controller */
+
+	/* allow controller to reset, and leave time for
+	* the ULPI transceiver to reset too.
+	*/
+	msleep(100);
+
+	/* Turn off the usbpll for ulpi tranceivers */
+	clk_disable(usb_clk);
+}
+
+static void usbh1_set_utmi_xcvr(void)
+{
+	u32 tmp;
+
+	/* Stop then Reset */
+	UH1_USBCMD &= ~UCMD_RUN_STOP;
+	while (UH1_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UH1_USBCMD |= UCMD_RESET;
+	while ((UH1_USBCMD) & (UCMD_RESET))
+		;
+
+	/* For OC and PWR, it is board level setting
+	 * The default setting is for mx53 evk
+	 */
+	USBCTRL &= ~UCTRL_H1PM;	/* Host1 Power Mask */
+	USBCTRL &= ~UCTRL_H1WIE; /* Host1 Wakeup Intr Disable */
+	USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS; /* Over current disable */
+
+	if (cpu_is_mx50()) {
+		USBCTRL |= UCTRL_H1PM; /* Host1 Power Mask */
+		USB_PHY_CTR_FUNC &= ~USB_UH1_OC_DIS; /* Over current enable */
+		/* Over current polarity low active */
+		USB_PHY_CTR_FUNC |= USB_UH1_OC_POL;
+	}
+	/* set UTMI xcvr */
+	tmp = UH1_PORTSC1 & ~PORTSC_PTS_MASK;
+	tmp |= PORTSC_PTS_UTMI;
+	UH1_PORTSC1 = tmp;
+
+	/* Set the PHY clock to 24MHz */
+	USBH1_PHY_CTRL1 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK;
+	USBH1_PHY_CTRL1 |= 0x01;
+
+	/* Workaround an IC issue for ehci driver:
+	 * when turn off root hub port power, EHCI set
+	 * PORTSC reserved bits to be 0, but PTW with 0
+	 * means 8 bits tranceiver width, here change
+	 * it back to be 16 bits and do PHY diable and
+	 * then enable.
+	 */
+	UH1_PORTSC1 |= PORTSC_PTW;
+
+	/* need to reset the controller here so that the ID pin
+	 * is correctly detected.
+	 */
+	/* Stop then Reset */
+	UH1_USBCMD &= ~UCMD_RUN_STOP;
+	while (UH1_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UH1_USBCMD |= UCMD_RESET;
+	while ((UH1_USBCMD) & (UCMD_RESET))
+		;
+
+	/* allow controller to reset, and leave time for
+	 * the ULPI transceiver to reset too.
+	 */
+	msleep(100);
+
+	/* Turn off the usbpll for UTMI tranceivers */
+	clk_disable(usb_clk);
+}
+
+static void usbh2_set_ulpi_xcvr(void)
+{
+	u32 tmp;
+
+	UH2_USBCMD &= ~UCMD_RUN_STOP;
+	while (UH2_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UH2_USBCMD |= UCMD_RESET;
+	while (UH2_USBCMD & UCMD_RESET)
+
+	USBCTRL_HOST2 &= ~(UCTRL_H2SIC_MASK | UCTRL_BPE);
+	USBCTRL_HOST2 &= ~UCTRL_H2WIE;	/* wakeup intr enable */
+	USBCTRL_HOST2 &= ~UCTRL_H2UIE;	/* ULPI intr enable */
+	USB_CTRL_1 |= USB_CTRL_UH2_EXT_CLK_EN;
+	if (cpu_is_mx53())
+		USB_CTRL_1 |= USB_CTRL_UH2_CLK_FROM_ULPI_PHY;
+	if (cpu_is_mx51())/* not tested */
+		USBCTRL_HOST2 |= (1 << 12);
+	/* must set ULPI phy before turning off clock */
+	tmp = UH2_PORTSC1 & ~PORTSC_PTS_MASK;
+	tmp |= PORTSC_PTS_ULPI;
+	UH2_PORTSC1 = tmp;
+	if (cpu_is_mx53()) {
+		/* turn off the internal 60MHZ clk  */
+		USB_CLKONOFF_CTRL |= (1 << 21);
+	}
+	UH2_USBCMD |= UCMD_RESET;	/* reset the controller */
+
+	/* allow controller to reset, and leave time for
+	 * the ULPI transceiver to reset too.
+	 */
+	msleep(100);
+
+	/* Turn off the usbpll for ulpi tranceivers */
+	clk_disable(usb_clk);
+}
+
+static void usbh2_set_serial_xcvr(void)
+{
+	/* Stop then Reset */
+	UH2_USBCMD &= ~UCMD_RUN_STOP;
+	while (UH2_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UH2_USBCMD |= UCMD_RESET;
+	while (UH2_USBCMD & UCMD_RESET)
+		;
+
+	USBCTRL &= ~(UCTRL_H2SIC_MASK);	/* Disable bypass mode */
+	USBCTRL &= ~(UCTRL_H2PM);	/* Power Mask */
+	USBCTRL &= ~UCTRL_H2OCPOL;	/* OverCurrent Polarity is Low Active */
+	USBCTRL &= ~UCTRL_H2WIE;	/* Wakeup intr disable */
+	USBCTRL |= UCTRL_IP_PUE_DOWN |	/* ipp_pue_pulldwn_dpdm */
+	    UCTRL_USBTE |	/* USBT is enabled */
+	    UCTRL_H2DT;		/* Disable H2 TLL */
+
+	if (cpu_is_mx35() && (imx_cpu_ver() < IMX_CHIP_REVISION_2_0)) {
+		/* Disable Host2 bus Lock for i.MX35 1.0 */
+		USBCTRL |= UCTRL_H2LOCKD;
+		/* USBOTG_PWR low active */
+		USBCTRL &= ~UCTRL_PP;
+		/* OverCurrent Polarity is Low Active */
+		USBCTRL &= ~UCTRL_OCPOL;
+	} else if (cpu_is_mx35() && (imx_cpu_ver() >= IMX_CHIP_REVISION_2_0)) {
+		/* i.MX35 2.0 OTG and Host2 have seperate OC/PWR polarity */
+		USBCTRL &= ~UCTRL_H2PP;
+		USBCTRL &= ~UCTRL_H2OCPOL;
+	} else if (cpu_is_mx25()) {
+		/*
+		 * USBH2_PWR and USBH2_OC are active high.
+		 * Must force xcvr clock to "internal" so that
+		 * we can write to PTS field after it's been
+		 * cleared by ehci_turn_off_all_ports().
+		 */
+		USBCTRL |= UCTRL_H2PP | UCTRL_H2OCPOL | UCTRL_XCSH2;
+		/* Disable Host2 bus Lock */
+		USBCTRL |= UCTRL_H2LOCKD;
+	}
+
+	USBCTRL &= ~(UCTRL_PP);
+	UH2_PORTSC1 = (UH2_PORTSC1 & (~PORTSC_PTS_MASK)) | PORTSC_PTS_SERIAL;
+
+	if (UH2_HCSPARAMS & HCSPARAMS_PPC)
+		UH2_PORTSC1 |= PORTSC_PORT_POWER;
+
+	/* Reset controller before set host mode */
+	UH2_USBCMD |= UCMD_RESET;
+	while (UH2_USBCMD & UCMD_RESET)
+		;
+
+	msleep(100);
+}
+
+/*!
+ * Register remote wakeup by this usb controller
+ *
+ * @param pdev: platform_device for this usb controller
+ *
+ * @return 0 or negative error code in case not supportted.
+ */
+static int usb_register_remote_wakeup(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+	struct resource *res;
+	int irq;
+
+	if (!(pdata->wake_up_enable))
+		return -ECANCELED;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev,
+		"Found HC with no IRQ. Check %s setup!\n",
+		dev_name(&pdev->dev));
+		return -ENODEV;
+	}
+	irq = res->start;
+	pdev->dev.power.can_wakeup = 1;
+	enable_irq_wake(irq);
+
+	return 0;
+}
+
+int fsl_usb_host_init(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+	struct fsl_xcvr_ops *xops;
+
+	xops = fsl_usb_get_xcvr(pdata->transceiver);
+	if (!xops) {
+		printk(KERN_ERR "%s transceiver ops missing\n", pdata->name);
+		return -EINVAL;
+	}
+	pdata->xcvr_ops = xops;
+	pdata->xcvr_type = xops->xcvr_type;
+	pdata->pdev = pdev;
+
+	if (fsl_check_usbclk() != 0)
+		return -EINVAL;
+
+	if (pdata->gpio_usb_active && pdata->gpio_usb_active())
+		return -EINVAL;
+
+	if (clk_enable(usb_clk)) {
+		printk(KERN_ERR "clk_enable(usb_clk) failed\n");
+		return -EINVAL;
+	}
+
+	if (cpu_is_mx50())
+		/* Turn on AHB CLK for H1*/
+		USB_CLKONOFF_CTRL &= ~H1_AHBCLK_OFF;
+
+	/* enable board power supply for xcvr */
+	if (pdata->xcvr_pwr) {
+		if (pdata->xcvr_pwr->regu1)
+			regulator_enable(pdata->xcvr_pwr->regu1);
+		if (pdata->xcvr_pwr->regu2)
+			regulator_enable(pdata->xcvr_pwr->regu2);
+	}
+
+	if (xops->init)
+		xops->init(xops);
+
+	if (usb_register_remote_wakeup(pdev))
+		pr_debug("%s port is not a wakeup source.\n", pdata->name);
+
+	if (xops->xcvr_type == PORTSC_PTS_SERIAL) {
+		if (cpu_is_mx35()) {
+			usbh2_set_serial_xcvr();
+			/* Close the internal 60Mhz */
+			USBCTRL &= ~UCTRL_XCSH2;
+		} else if (cpu_is_mx25())
+			usbh2_set_serial_xcvr();
+		else
+			usbh1_set_serial_xcvr();
+	} else if (xops->xcvr_type == PORTSC_PTS_ULPI) {
+		if (!strcmp("Host 1", pdata->name))
+			usbh1_set_ulpi_xcvr();
+		if (!strcmp("Host 2", pdata->name))
+			usbh2_set_ulpi_xcvr();
+	} else if (xops->xcvr_type == PORTSC_PTS_UTMI) {
+		usbh1_set_utmi_xcvr();
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_usb_host_init);
+
+void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata)
+{
+	if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
+		pdata->xcvr_ops->uninit(pdata->xcvr_ops);
+
+	if (pdata->gpio_usb_inactive)
+		pdata->gpio_usb_inactive();
+	if (pdata->xcvr_type == PORTSC_PTS_SERIAL) {
+		/* Workaround an IC issue for ehci driver.
+		 * when turn off root hub port power, EHCI set
+		 * PORTSC reserved bits to be 0, but PTS with 0
+		 * means UTMI interface, so here force the Host2
+		 * port use the internal 60Mhz.
+		 */
+		if (cpu_is_mx35())
+			USBCTRL |= UCTRL_XCSH2;
+		clk_disable(usb_clk);
+	}
+
+	/* disable board power supply for xcvr */
+	if (pdata->xcvr_pwr) {
+		if (pdata->xcvr_pwr->regu1)
+			regulator_disable(pdata->xcvr_pwr->regu1);
+		if (pdata->xcvr_pwr->regu2)
+			regulator_disable(pdata->xcvr_pwr->regu2);
+	}
+
+	pdata->regs = NULL;
+	if (usb_ahb_clk)
+		clk_disable(usb_ahb_clk);
+}
+EXPORT_SYMBOL(fsl_usb_host_uninit);
+
+static void otg_set_serial_xcvr(void)
+{
+	pr_debug("%s\n", __func__);
+}
+
+void otg_set_serial_host(void)
+{
+	/* set USBCTRL for host operation
+	 * disable: bypass mode,
+	 * set: single-ended/unidir/6 wire, OTG wakeup intr enable,
+	 *      power mask
+	 */
+	USBCTRL &= ~UCTRL_OSIC_MASK;
+#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3)
+	USBCTRL &= ~UCTRL_BPE;
+#endif
+
+#if defined(CONFIG_MXC_USB_SB3)
+	USBCTRL |= UCTRL_OSIC_SB3 | UCTRL_OWIE | UCTRL_OPM;
+#elif defined(CONFIG_MXC_USB_SU6)
+	USBCTRL |= UCTRL_OSIC_SU6 | UCTRL_OWIE | UCTRL_OPM;
+#elif defined(CONFIG_MXC_USB_DB4)
+	USBCTRL |= UCTRL_OSIC_DB4 | UCTRL_OWIE | UCTRL_OPM;
+#else
+	USBCTRL |= UCTRL_OSIC_DU6 | UCTRL_OWIE | UCTRL_OPM;
+#endif
+
+	USB_OTG_MIRROR = OTGM_VBUSVAL | OTGM_ASESVLD;	/* 0xa */
+}
+EXPORT_SYMBOL(otg_set_serial_host);
+
+void otg_set_serial_peripheral(void)
+{
+	/* set USBCTRL for device operation
+	 * disable: bypass mode
+	 * set: differential/unidir/6 wire, OTG wakeup intr enable,
+	 *      power mask
+	 */
+	USBCTRL &= ~UCTRL_OSIC_MASK;
+#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3)
+	USBCTRL &= ~UCTRL_BPE;
+#endif
+
+#if defined(CONFIG_MXC_USB_SB3)
+	USBCTRL |= UCTRL_OSIC_SB3 | UCTRL_OWIE | UCTRL_OPM;
+#elif defined(CONFIG_MXC_USB_SU6)
+	USBCTRL |= UCTRL_OSIC_SU6 | UCTRL_OWIE | UCTRL_OPM;
+#elif defined(CONFIG_MXC_USB_DB4)
+	USBCTRL |= UCTRL_OSIC_DB4 | UCTRL_OWIE | UCTRL_OPM;
+#else
+	USBCTRL |= UCTRL_OSIC_DU6 | UCTRL_OWIE | UCTRL_OPM;
+#endif
+
+	USB_OTG_MIRROR = OTGM_VBUSVAL | OTGM_BSESVLD | OTGM_IDIDG;	/* oxd */
+}
+EXPORT_SYMBOL(otg_set_serial_peripheral);
+
+static void otg_set_ulpi_xcvr(void)
+{
+	u32 tmp;
+
+	USBCTRL &= ~UCTRL_OSIC_MASK;
+#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3)
+	USBCTRL &= ~UCTRL_BPE;
+#endif
+	USBCTRL |= UCTRL_OUIE |	/* ULPI intr enable */
+	    UCTRL_OWIE |	/* OTG wakeup intr enable */
+	    UCTRL_OPM;		/* power mask */
+
+	/* must set ULPI phy before turning off clock */
+	tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK;
+	tmp |= PORTSC_PTS_ULPI;
+	UOG_PORTSC1 = tmp;
+
+	/* need to reset the controller here so that the ID pin
+	 * is correctly detected.
+	 */
+	UOG_USBCMD |= UCMD_RESET;
+
+	/* allow controller to reset, and leave time for
+	 * the ULPI transceiver to reset too.
+	 */
+	msleep(100);
+
+	/* Turn off the usbpll for ulpi tranceivers */
+	clk_disable(usb_clk);
+}
+
+int fsl_usb_xcvr_suspend(struct fsl_xcvr_ops *xcvr_ops)
+{
+	if (!machine_is_mx31_3ds())
+		return -ECANCELED;
+
+	if (xcvr_ops->xcvr_type == PORTSC_PTS_ULPI) {
+		if (fsl_check_usbclk() != 0)
+			return -EINVAL;
+		clk_enable(usb_clk);
+
+		otg_set_ulpi_xcvr();
+
+		if (xcvr_ops->suspend)
+			/* suspend transceiver */
+			xcvr_ops->suspend(xcvr_ops);
+
+		clk_disable(usb_clk);
+	}
+	return 0;
+}
+EXPORT_SYMBOL(fsl_usb_xcvr_suspend);
+
+static void otg_set_utmi_xcvr(void)
+{
+	u32 tmp;
+
+	/* Stop then Reset */
+	UOG_USBCMD &= ~UCMD_RUN_STOP;
+	while (UOG_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UOG_USBCMD |= UCMD_RESET;
+	while ((UOG_USBCMD) & (UCMD_RESET))
+		;
+
+	if (cpu_is_mx53())
+		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
+
+	if (cpu_is_mx51()) {
+		if (machine_is_mx51_3ds()) {
+			/* OTG Polarity of Overcurrent is Low active */
+			USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL;
+			/* Enable OTG Overcurrent Event */
+			USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS;
+		} else {
+			/* BBG is not using OC */
+			USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
+		}
+	} else if (cpu_is_mx25()) {
+		USBCTRL |= UCTRL_OCPOL;
+		USBCTRL &= ~UCTRL_PP;
+	} else if (cpu_is_mx50()) {
+		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
+	} else {
+		/* USBOTG_PWR low active */
+		USBCTRL &= ~UCTRL_PP;
+		/* OverCurrent Polarity is Low Active */
+		USBCTRL &= ~UCTRL_OCPOL;
+
+		if (cpu_is_mx35() && (imx_cpu_ver() < IMX_CHIP_REVISION_2_0))
+			/* OTG Lock Disable */
+			USBCTRL |= UCTRL_OLOCKD;
+	}
+
+	if (cpu_is_mx51())
+		USBCTRL &= ~UCTRL_OPM;	/* OTG Power Mask */
+
+	USBCTRL &= ~UCTRL_OWIE;	/* OTG Wakeup Intr Disable */
+
+	/* set UTMI xcvr */
+	tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK;
+	tmp |= PORTSC_PTS_UTMI;
+	UOG_PORTSC1 = tmp;
+
+	if (cpu_is_mx51()) {
+		/* Set the PHY clock to 19.2MHz */
+		USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK;
+		USB_PHY_CTR_FUNC2 |= 0x01;
+	}
+
+	/* Workaround an IC issue for ehci driver:
+	 * when turn off root hub port power, EHCI set
+	 * PORTSC reserved bits to be 0, but PTW with 0
+	 * means 8 bits tranceiver width, here change
+	 * it back to be 16 bits and do PHY diable and
+	 * then enable.
+	 */
+	UOG_PORTSC1 |= PORTSC_PTW;
+
+	if (cpu_is_mx35() || cpu_is_mx25()) {
+		/* Enable UTMI interface in PHY control Reg */
+		USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_UTMI_ENABLE;
+		USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE;
+	}
+
+	/* need to reset the controller here so that the ID pin
+	 * is correctly detected.
+	 */
+	/* Stop then Reset */
+	UOG_USBCMD &= ~UCMD_RUN_STOP;
+	while (UOG_USBCMD & UCMD_RUN_STOP)
+		;
+
+	UOG_USBCMD |= UCMD_RESET;
+	while ((UOG_USBCMD) & (UCMD_RESET))
+		;
+
+	/* allow controller to reset, and leave time for
+	 * the ULPI transceiver to reset too.
+	 */
+	msleep(100);
+
+	/* Turn off the usbpll for UTMI tranceivers */
+	clk_disable(usb_clk);
+}
+
+static int mxc_otg_used;
+
+int usbotg_init(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+	struct fsl_xcvr_ops *xops;
+
+	xops = fsl_usb_get_xcvr(pdata->transceiver);
+	if (!xops) {
+		printk(KERN_ERR "DR transceiver ops missing\n");
+		return -EINVAL;
+	}
+	pdata->xcvr_ops = xops;
+	pdata->xcvr_type = xops->xcvr_type;
+	pdata->pdev = pdev;
+
+	if (fsl_check_usbclk() != 0)
+		return -EINVAL;
+	if (!mxc_otg_used) {
+		if (cpu_is_mx50())
+			/* Turn on AHB CLK for OTG*/
+			USB_CLKONOFF_CTRL &= ~OTG_AHBCLK_OFF;
+
+		if (pdata->gpio_usb_active && pdata->gpio_usb_active())
+			return -EINVAL;
+
+		if (clk_enable(usb_clk)) {
+			printk(KERN_ERR "clk_enable(usb_clk) failed\n");
+			return -EINVAL;
+		}
+
+		if (xops->init)
+			xops->init(xops);
+
+		UOG_PORTSC1 = UOG_PORTSC1 & ~PORTSC_PHCD;
+		if (xops->xcvr_type == PORTSC_PTS_SERIAL) {
+			if (pdata->operating_mode == FSL_USB2_DR_HOST) {
+				otg_set_serial_host();
+				/* need reset */
+				UOG_USBCMD |= UCMD_RESET;
+				msleep(100);
+			} else if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
+				otg_set_serial_peripheral();
+			otg_set_serial_xcvr();
+		} else if (xops->xcvr_type == PORTSC_PTS_ULPI) {
+			otg_set_ulpi_xcvr();
+		} else if (xops->xcvr_type == PORTSC_PTS_UTMI) {
+			otg_set_utmi_xcvr();
+		}
+	}
+
+	if (usb_register_remote_wakeup(pdev))
+		pr_debug("DR is not a wakeup source.\n");
+
+	mxc_otg_used++;
+	return 0;
+}
+EXPORT_SYMBOL(usbotg_init);
+
+void usbotg_uninit(struct fsl_usb2_platform_data *pdata)
+{
+	mxc_otg_used--;
+	if (!mxc_otg_used) {
+		if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
+			pdata->xcvr_ops->uninit(pdata->xcvr_ops);
+
+		pdata->regs = NULL;
+
+		if (machine_is_mx31_3ds()) {
+			if (pdata->xcvr_ops && pdata->xcvr_ops->suspend)
+				pdata->xcvr_ops->suspend(pdata->xcvr_ops);
+			clk_disable(usb_clk);
+		}
+		msleep(1);
+		UOG_PORTSC1 = UOG_PORTSC1 | PORTSC_PHCD;
+		if (pdata->gpio_usb_inactive)
+			pdata->gpio_usb_inactive();
+		if (pdata->xcvr_type == PORTSC_PTS_SERIAL)
+			clk_disable(usb_clk);
+		clk_disable(usb_ahb_clk);
+	}
+}
+EXPORT_SYMBOL(usbotg_uninit);
+
+/*
+ * This function is used to debounce the reading value for id/vbus at
+ * the register of otgsc
+ */
+void usb_debounce_id_vbus(void)
+{
+	mdelay(3);
+}
+EXPORT_SYMBOL(usb_debounce_id_vbus);
+
+int usb_host_wakeup_irq(struct device *wkup_dev)
+{
+	int wakeup_req = 0;
+	struct fsl_usb2_platform_data *pdata = wkup_dev->platform_data;
+
+	if (!strcmp("Host 1", pdata->name)) {
+		wakeup_req = USBCTRL & UCTRL_H1WIR;
+	} else if (!strcmp("Host 2", pdata->name)) {
+		wakeup_req = USBCTRL_HOST2 & UCTRL_H2WIR;
+	} else if (!strcmp("DR", pdata->name)) {
+		wakeup_req = USBCTRL & UCTRL_OWIR;
+		/*if only host mode is enabled, the wakeup event
+		 * must be host wakeup event */
+#ifdef CONFIG_USB_OTG
+		/* if ID change status, it is host wakeup event */
+		if (wakeup_req && (UOG_OTGSC & OTGSC_IS_USB_ID))
+			wakeup_req = 0;
+#endif
+	}
+
+	return wakeup_req;
+}
+EXPORT_SYMBOL(usb_host_wakeup_irq);
+
+int usb_event_is_otg_wakeup(void)
+{
+	int ret = (USBCTRL & UCTRL_OWIR) ? 1 : 0;
+	return ret;
+}
+EXPORT_SYMBOL(usb_event_is_otg_wakeup);
+
+void usb_host_set_wakeup(struct device *wkup_dev, bool para)
+{
+	struct fsl_usb2_platform_data *pdata = wkup_dev->platform_data;
+	if (pdata->wake_up_enable)
+		pdata->wake_up_enable(pdata, para);
+}
+EXPORT_SYMBOL(usb_host_set_wakeup);
diff --git a/arch/arm/plat-mxc/usb_wakeup.c b/arch/arm/plat-mxc/usb_wakeup.c
new file mode 100644
index 00000000000..80bc6c9861d
--- /dev/null
+++ b/arch/arm/plat-mxc/usb_wakeup.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ *  The code contained herein is licensed under the GNU General Public
+ *  License. You may obtain a copy of the GNU General Public License
+ *  Version 2 or later at the following locations:
+ *  *
+ *  http://www.opensource.org/licenses/gpl-license.html
+ *  http://www.gnu.org/copyleft/gpl.html
+*/
+
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/kthread.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/fsl_devices.h>
+#include <linux/suspend.h>
+
+struct wakeup_ctrl {
+	int wakeup_irq;
+	int usb_irq;
+	struct fsl_usb2_wakeup_platform_data *pdata;
+	struct task_struct *thread;
+	struct completion  event;
+};
+static struct wakeup_ctrl *g_ctrl;
+
+extern int usb_event_is_otg_wakeup(void);
+extern void usb_debounce_id_vbus(void);
+
+static void wakeup_clk_gate(struct fsl_usb2_wakeup_platform_data *pdata, bool on)
+{
+	if (pdata->usb_clock_for_pm)
+		pdata->usb_clock_for_pm(on);
+}
+
+static bool usb2_is_in_lowpower(struct wakeup_ctrl *ctrl)
+{
+	int i;
+	struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata;
+	/* all the usb module related the wakeup is in lowpower mode */
+	for (i = 0; i < 3; i++) {
+		if (pdata->usb_pdata[i]) {
+			if (pdata->usb_pdata[i]->phy_lowpower_suspend && !pdata->usb_pdata[i]->lowpower)
+				return false;
+		}
+	}
+	return true;
+}
+
+static void delay_process_wakeup(struct wakeup_ctrl *ctrl)
+{
+	int i;
+	struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata;
+	disable_irq_nosync(ctrl->wakeup_irq);
+	if ((ctrl->usb_irq > 0) && (ctrl->wakeup_irq != ctrl->usb_irq))
+		disable_irq_nosync(ctrl->usb_irq);
+
+	for (i = 0; i < 3; i++) {
+		if (pdata->usb_pdata[i]) {
+			pdata->usb_pdata[i]->irq_delay = 1;
+		}
+	}
+	pdata->usb_wakeup_is_pending = true;
+	complete(&ctrl->event);
+}
+
+static irqreturn_t usb_wakeup_handler(int irq, void *_dev)
+{
+	struct wakeup_ctrl *ctrl = (struct wakeup_ctrl *)_dev;
+	irqreturn_t ret = IRQ_NONE;
+
+	if (usb2_is_in_lowpower(ctrl)) {
+		printk(KERN_INFO "usb wakeup is here\n");
+		delay_process_wakeup(ctrl);
+		ret = IRQ_HANDLED;
+	}
+	return ret;
+}
+
+static enum usb_wakeup_event is_wakeup(struct fsl_usb2_platform_data *pdata)
+{
+	if (pdata->is_wakeup_event)
+		return pdata->is_wakeup_event(pdata);
+	else
+		return WAKEUP_EVENT_INVALID;
+}
+
+static void wakeup_event_handler(struct wakeup_ctrl *ctrl)
+{
+	struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata;
+	int already_waked = 0;
+	enum usb_wakeup_event wakeup_evt;
+	int i, cnt = 0;
+
+	wakeup_clk_gate(ctrl->pdata, true);
+
+recheck:
+	/* In order to get the real id/vbus value */
+	if (usb_event_is_otg_wakeup())
+		msleep(10);	/* usb_debounce_id_vbus(); */
+
+	for (i = 0; i < 3; i++) {
+		struct fsl_usb2_platform_data *usb_pdata = pdata->usb_pdata[i];
+		if (usb_pdata) {
+			usb_pdata->irq_delay = 0;
+			wakeup_evt = is_wakeup(usb_pdata);
+			if (wakeup_evt != WAKEUP_EVENT_INVALID) {
+				if (usb_pdata->usb_clock_for_pm)
+					usb_pdata->usb_clock_for_pm(true);
+				usb_pdata->lowpower = 0;
+				already_waked = 1;
+				if (usb_pdata->wakeup_handler) {
+					usb_pdata->wakeup_handler(usb_pdata);
+				}
+			}
+		}
+	}
+	/* for IC: ID/VBUS status change after wakeup interrupt */
+	if ((cnt++ < 5) && (already_waked == 0))
+		goto recheck;
+	/* If nothing to wakeup, clear wakeup event */
+	if ((already_waked == 0) && pdata->usb_wakeup_exhandle)
+		pdata->usb_wakeup_exhandle();
+
+	wakeup_clk_gate(ctrl->pdata, false);
+	pdata->usb_wakeup_is_pending = false;
+	wake_up(&pdata->wq);
+}
+
+static int wakeup_event_thread(void *param)
+{
+	struct wakeup_ctrl *ctrl = (struct wakeup_ctrl *)param;
+	struct sched_param sch_param = {.sched_priority = 1};
+
+	sched_setscheduler(current, SCHED_RR, &sch_param);
+	while (1) {
+		wait_for_completion_interruptible(&ctrl->event);
+		if (kthread_should_stop())
+			break;
+		wakeup_event_handler(ctrl);
+		enable_irq(ctrl->wakeup_irq);
+		if ((ctrl->usb_irq > 0) && (ctrl->wakeup_irq != ctrl->usb_irq))
+			enable_irq(ctrl->usb_irq);
+	}
+	return 0;
+}
+
+static int wakeup_dev_probe(struct platform_device *pdev)
+{
+	struct fsl_usb2_wakeup_platform_data *pdata;
+	struct wakeup_ctrl *ctrl = NULL;
+	int status;
+
+	printk(KERN_INFO "IMX usb wakeup probe\n");
+
+	if (!pdev || !pdev->dev.platform_data)
+		return -ENODEV;
+	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
+	if (!ctrl)
+		return -ENOMEM;
+	pdata = pdev->dev.platform_data;
+	init_waitqueue_head(&pdata->wq);
+	pdata->usb_wakeup_is_pending = false;
+
+	ctrl->pdata = pdata;
+	init_completion(&ctrl->event);
+	ctrl->wakeup_irq = platform_get_irq(pdev, 0);
+	status = request_irq(ctrl->wakeup_irq, usb_wakeup_handler, IRQF_SHARED, "usb_wakeup", (void *)ctrl);
+	if (status)
+		goto error1;
+	ctrl->usb_irq = platform_get_irq(pdev, 1);
+
+	ctrl->thread = kthread_run(wakeup_event_thread, (void *)ctrl, "usb_wakeup thread");
+	status = IS_ERR(ctrl->thread) ? -1 : 0;
+	if (status)
+		goto error2;
+	g_ctrl = ctrl;
+	printk(KERN_DEBUG "the wakeup pdata is 0x%p\n", pdata);
+
+	return 0;
+error2:
+	free_irq(ctrl->wakeup_irq, (void *)ctrl);
+error1:
+	kfree(ctrl);
+	return status;
+}
+
+static int  wakeup_dev_exit(struct platform_device *pdev)
+{
+	if (g_ctrl->thread) {
+		complete(&g_ctrl->event);
+		kthread_stop(g_ctrl->thread);
+	}
+	free_irq(g_ctrl->wakeup_irq, (void *)g_ctrl);
+	kfree(g_ctrl);
+	return 0;
+}
+static struct platform_driver wakeup_d = {
+	.probe   = wakeup_dev_probe,
+	.remove  = wakeup_dev_exit,
+	.driver = {
+		.name = "usb_wakeup",
+	},
+};
+
+static int __init wakeup_dev_init(void)
+{
+	return platform_driver_register(&wakeup_d);
+}
+static void __exit wakeup_dev_uninit(void)
+{
+	platform_driver_unregister(&wakeup_d);
+}
+
+subsys_initcall(wakeup_dev_init);
+module_exit(wakeup_dev_uninit);
+
diff --git a/arch/arm/plat-mxc/utmixc.c b/arch/arm/plat-mxc/utmixc.c
new file mode 100644
index 00000000000..e03b9510c55
--- /dev/null
+++ b/arch/arm/plat-mxc/utmixc.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/usb/fsl_xcvr.h>
+
+#include <mach/hardware.h>
+#include <mach/arc_otg.h>
+#include <asm/mach-types.h>
+
+static struct regulator *usbotg_regux;
+
+static void usb_utmi_init(struct fsl_xcvr_ops *this)
+{
+#if defined(CONFIG_MXC_PMIC_MC13892_MODULE) || defined(CONFIG_MXC_PMIC_MC13892)
+	if (machine_is_mx51_3ds()) {
+		unsigned int value;
+
+		/* VUSBIN */
+		pmic_read_reg(REG_USB1, &value, 0xffffff);
+		value |= 0x1;
+		value |= (0x1 << 3);
+		pmic_write_reg(REG_USB1, value, 0xffffff);
+	}
+#endif
+}
+
+static void usb_utmi_uninit(struct fsl_xcvr_ops *this)
+{
+}
+
+/*!
+ * set vbus power
+ *
+ * @param       view  viewport register
+ * @param       on    power on or off
+ */
+static void set_power(struct fsl_xcvr_ops *this,
+		      struct fsl_usb2_platform_data *pdata, int on)
+{
+	struct device *dev = &pdata->pdev->dev;
+
+	pr_debug("real %s(on=%d) pdata=0x%p\n", __func__, on, pdata);
+	if (pdata && pdata->platform_driver_vbus)
+		pdata->platform_driver_vbus(on);
+}
+
+static struct fsl_xcvr_ops utmi_ops = {
+	.name = "utmi",
+	.xcvr_type = PORTSC_PTS_UTMI,
+	.init = usb_utmi_init,
+	.uninit = usb_utmi_uninit,
+	.set_vbus_power = set_power,
+};
+
+extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops);
+
+static int __init utmixc_init(void)
+{
+	fsl_usb_xcvr_register(&utmi_ops);
+	return 0;
+}
+
+extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops);
+
+static void __exit utmixc_exit(void)
+{
+	fsl_usb_xcvr_unregister(&utmi_ops);
+}
+
+subsys_initcall(utmixc_init);
+module_exit(utmixc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("utmi xcvr driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b5e6f243f74..7729b0856e6 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -136,4 +136,5 @@ source "drivers/hv/Kconfig"
 
 source "drivers/devfreq/Kconfig"
 
+source "drivers/mxc/Kconfig"
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 1b3142127bf..2151b486f98 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -98,6 +98,7 @@ obj-y				+= lguest/
 obj-$(CONFIG_CPU_FREQ)		+= cpufreq/
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle/
 obj-$(CONFIG_MMC)		+= mmc/
+obj-$(CONFIG_ARCH_MXC)		+= mxc/
 obj-$(CONFIG_MEMSTICK)		+= memstick/
 obj-y				+= leds/
 obj-$(CONFIG_INFINIBAND)	+= infiniband/
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 43643033a3a..236b6084426 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -608,6 +608,12 @@ config RAMOOPS
 	  This enables panic and oops messages to be logged to a circular
 	  buffer in RAM where it can be read back at some later point.
 
+config MXC_IIM
+	tristate "MXC IIM device driver"
+	depends on ARCH_MXC
+	help
+	  Support for access to MXC IIM device, most people should say N here.
+
 config MSM_SMD_PKT
 	bool "Enable device interface for some SMD packet ports"
 	default n
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 32762ba769c..279a6cef4cd 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -61,6 +61,8 @@ obj-$(CONFIG_TCG_TPM)		+= tpm/
 obj-$(CONFIG_PS3_FLASH)		+= ps3flash.o
 obj-$(CONFIG_RAMOOPS)		+= ramoops.o
 
+obj-$(CONFIG_MXC_IIM)           += mxc_iim.o
+
 obj-$(CONFIG_JS_RTC)		+= js-rtc.o
 js-rtc-y = rtc.o
 
diff --git a/drivers/char/mxc_iim.c b/drivers/char/mxc_iim.c
new file mode 100644
index 00000000000..9d2f4b96555
--- /dev/null
+++ b/drivers/char/mxc_iim.c
@@ -0,0 +1,645 @@
+/*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/miscdevice.h>
+#include <linux/uaccess.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include "mxc_iim.h"
+
+static struct mxc_iim_platform_data *iim_data;
+
+
+#ifdef MXC_IIM_DEBUG
+static inline void dump_reg(void)
+{
+	struct iim_regs *iim_reg_base =
+		(struct iim_regs *)iim_data->virt_base;
+
+	dev_dbg(iim_data->dev, "stat: 0x%08x\n",
+			__raw_readl(&iim_reg_base->stat));
+	dev_dbg(iim_data->dev, "statm: 0x%08x\n",
+			__raw_readl(&iim_reg_base->statm));
+	dev_dbg(iim_data->dev, "err: 0x%08x\n",
+			__raw_readl(&iim_reg_base->err));
+	dev_dbg(iim_data->dev, "emask: 0x%08x\n",
+			__raw_readl(&iim_reg_base->emask));
+	dev_dbg(iim_data->dev, "fctl: 0x%08x\n",
+			__raw_readl(&iim_reg_base->fctl));
+	dev_dbg(iim_data->dev, "ua: 0x%08x\n",
+			__raw_readl(&iim_reg_base->ua));
+	dev_dbg(iim_data->dev, "la: 0x%08x\n",
+			__raw_readl(&iim_reg_base->la));
+	dev_dbg(iim_data->dev, "sdat: 0x%08x\n",
+			__raw_readl(&iim_reg_base->sdat));
+	dev_dbg(iim_data->dev, "prev: 0x%08x\n",
+			__raw_readl(&iim_reg_base->prev));
+	dev_dbg(iim_data->dev, "srev: 0x%08x\n",
+			__raw_readl(&iim_reg_base->srev));
+	dev_dbg(iim_data->dev, "preg_p: 0x%08x\n",
+			__raw_readl(&iim_reg_base->preg_p));
+	dev_dbg(iim_data->dev, "scs0: 0x%08x\n",
+			__raw_readl(&iim_reg_base->scs0));
+	dev_dbg(iim_data->dev, "scs1: 0x%08x\n",
+			__raw_readl(&iim_reg_base->scs1));
+	dev_dbg(iim_data->dev, "scs2: 0x%08x\n",
+			__raw_readl(&iim_reg_base->scs2));
+	dev_dbg(iim_data->dev, "scs3: 0x%08x\n",
+			__raw_readl(&iim_reg_base->scs3));
+}
+#endif
+
+static inline void mxc_iim_disable_irq(void)
+{
+	struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+
+	__raw_writel(0x0, &(iim_reg_base->statm));
+	__raw_writel(0x0, &(iim_reg_base->emask));
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+}
+
+static inline void fuse_op_start(void)
+{
+	struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+
+#ifdef MXC_IIM_DEBUG
+	dump_reg();
+#endif
+
+	/* Clear the status bits and error bits */
+	__raw_writel(0x3, &(iim_reg_base->stat));
+	__raw_writel(0xfe, &(iim_reg_base->err));
+	/* Generate interrupt */
+	__raw_writel(0x3, &(iim_reg_base->statm));
+	__raw_writel(0xfe, &(iim_reg_base->emask));
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+}
+
+static u32 sense_fuse(u32 bank, u32 row, u32 bit)
+{
+	u32 addr, addr_l, addr_h;
+	s32 err = 0;
+	struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+
+	init_completion(&(iim_data->completion));
+
+	iim_data->action = POLL_FUSE_SNSD;
+
+	fuse_op_start();
+
+	addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+	/* Set IIM Program Upper Address */
+	addr_h = (addr >> 8) & 0x000000FF;
+	/* Set IIM Program Lower Address */
+	addr_l = (addr & 0x000000FF);
+
+	dev_dbg(iim_data->dev, "%s: addr_h=0x%x, addr_l=0x%x\n",
+			__func__, addr_h, addr_l);
+	__raw_writel(addr_h, &(iim_reg_base->ua));
+	__raw_writel(addr_l, &(iim_reg_base->la));
+
+	/* Start sensing */
+#ifdef MXC_IIM_DEBUG
+	dump_reg();
+#endif
+	__raw_writel(0x8, &(iim_reg_base->fctl));
+
+	err = wait_for_completion_timeout(&(iim_data->completion),
+					msecs_to_jiffies(1000));
+	err = (!err) ? -ETIMEDOUT : 0;
+	if (err)
+		dev_dbg(iim_data->dev, "Sense timeout!");
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+
+	return __raw_readl(&(iim_reg_base->sdat));
+}
+
+/* Blow fuses based on the bank, row and bit positions (all 0-based)
+*/
+static s32 fuse_blow_bit(u32 bank, u32 row, u32 bit)
+{
+	int addr, addr_l, addr_h, err;
+	struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+
+	init_completion(&iim_data->completion);
+
+	iim_data->action = POLL_FUSE_PRGD;
+
+	fuse_op_start();
+
+	/* Disable IIM Program Protect */
+	__raw_writel(0xaa, &(iim_reg_base->preg_p));
+
+	addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+	/* Set IIM Program Upper Address */
+	addr_h = (addr >> 8) & 0x000000FF;
+	/* Set IIM Program Lower Address */
+	addr_l = (addr & 0x000000FF);
+
+	dev_dbg(iim_data->dev, "blowing addr_h=0x%x, addr_l=0x%x\n",
+		addr_h, addr_l);
+
+	__raw_writel(addr_h, &(iim_reg_base->ua));
+	__raw_writel(addr_l, &(iim_reg_base->la));
+
+	/* Start Programming */
+#ifdef MXC_IIM_DEBUG
+	dump_reg();
+#endif
+	__raw_writel(0x31, &(iim_reg_base->fctl));
+	err = wait_for_completion_timeout(&(iim_data->completion),
+					msecs_to_jiffies(1000));
+	err = (!err) ? -ETIMEDOUT : 0;
+	if (err)
+		dev_dbg(iim_data->dev, "Fuse timeout!\n");
+
+	/* Enable IIM Program Protect */
+	__raw_writel(0x0, &(iim_reg_base->preg_p));
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+
+	return err;
+}
+
+static void fuse_blow_row(u32 bank, u32 row, u32 value)
+{
+	u32 i;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+
+	/* Enable fuse blown */
+	if (iim_data->enable_fuse)
+		iim_data->enable_fuse();
+
+	for (i = 0; i < 8; i++) {
+		if (((value >> i) & 0x1) == 0)
+			continue;
+		if (fuse_blow_bit(bank, row, i) != 0) {
+			dev_dbg(iim_data->dev,
+				"fuse_blow_bit(bank: %d, row: %d, "
+				"bit: %d failed\n",
+				bank, row, i);
+		}
+	}
+
+	if (iim_data->disable_fuse)
+		iim_data->disable_fuse();
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+}
+
+static irqreturn_t mxc_iim_irq(int irq, void *dev_id)
+{
+	u32 status, error, rtn = 0;
+	ulong flags;
+	struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+
+	spin_lock_irqsave(&iim_data->lock, flags);
+
+	mxc_iim_disable_irq();
+#ifdef MXC_IIM_DEBUG
+	dump_reg();
+#endif
+	if (iim_data->action != POLL_FUSE_PRGD &&
+		iim_data->action != POLL_FUSE_SNSD) {
+		dev_dbg(iim_data->dev, "%s(%d) invalid operation\n",
+			__func__, iim_data->action);
+		rtn = 1;
+		goto out;
+	}
+
+	/* Test for successful write */
+	status = readl(&(iim_reg_base->stat));
+	error = readl(&(iim_reg_base->err));
+
+	if ((status & iim_data->action) != 0 && \
+		(error & (iim_data->action >> IIM_ERR_SHIFT)) == 0) {
+		if (error) {
+			printk(KERN_NOTICE "Even though the operation"
+				"seems successful...\n");
+			printk(KERN_NOTICE "There are some error(s) "
+				"at addr=0x%x: 0x%x\n",
+				(u32)&(iim_reg_base->err), error);
+		}
+		__raw_writel(0x3, &(iim_reg_base->stat));
+		rtn = 0;
+		goto out;
+	}
+	printk(KERN_NOTICE "%s(%d) failed\n", __func__, iim_data->action);
+	printk(KERN_NOTICE "status address=0x%x, value=0x%x\n",
+		(u32)&(iim_reg_base->stat), status);
+	printk(KERN_NOTICE "There are some error(s) at addr=0x%x: 0x%x\n",
+		(u32)&(iim_reg_base->err), error);
+#ifdef MXC_IIM_DEBUG
+	dump_reg();
+#endif
+
+out:
+	complete(&(iim_data->completion));
+	spin_unlock_irqrestore(&iim_data->lock, flags);
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+
+	return IRQ_RETVAL(rtn);
+}
+
+static loff_t mxc_iim_llseek(struct file *filp, loff_t off, int whence)
+{
+	loff_t newpos;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+	dev_dbg(iim_data->dev, "off: %lld, whence: %d\n", off, whence);
+
+	if (off < iim_data->bank_start ||
+		off > iim_data->bank_end) {
+		dev_dbg(iim_data->dev, "invalid seek offset: %lld\n", off);
+		goto invald_arg_out;
+	}
+
+	switch (whence) {
+	case 0: /* SEEK_SET */
+		newpos = off;
+		break;
+	case 1: /* SEEK_CUR */
+		newpos = filp->f_pos + off;
+		break;
+	case 2: /* SEEK_END */
+		newpos = iim_data->bank_end + off;
+		break;
+	default: /* can't happen */
+		return -EINVAL;
+
+	}
+
+	if (newpos < 0)
+		return -EINVAL;
+	filp->f_pos = newpos;
+
+	dev_dbg(iim_data->dev, "newpos: %lld\n", newpos);
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+
+	return newpos;
+invald_arg_out:
+	return -EINVAL;
+}
+
+static ssize_t mxc_iim_read(struct file *filp, char __user *buf,
+			size_t count, loff_t *f_pos)
+{
+	u32 bank, row, fuse_val;
+	ssize_t retval = 0;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+	dev_dbg(iim_data->dev, "count: %d f_pos: %lld\n", count, *f_pos);
+
+	if (1 != count)
+		goto invald_arg_out;
+	if (*f_pos & 0x3)
+		goto invald_arg_out;
+	if (*f_pos < iim_data->bank_start ||
+		*f_pos > iim_data->bank_end) {
+		dev_dbg(iim_data->dev, "bank_start: 0x%08x, bank_end: 0x%08x\n",
+			iim_data->bank_start, iim_data->bank_end);
+		goto out;
+	}
+
+	bank = (*f_pos - iim_data->bank_start) >> 10;
+	row  = ((*f_pos - iim_data->bank_start) & 0x3ff) >> 2;
+
+	dev_dbg(iim_data->dev, "Read fuse at bank:%d row:%d\n",
+		bank, row);
+	mutex_lock(&iim_data->mutex);
+	fuse_val = sense_fuse(bank, row, 0);
+	mutex_unlock(&iim_data->mutex);
+	dev_info(iim_data->dev, "fuses at (bank:%d, row:%d) = 0x%x\n",
+		bank, row, fuse_val);
+	if (copy_to_user(buf, &fuse_val, count)) {
+		retval = -EFAULT;
+		goto out;
+	}
+
+out:
+	retval = count;
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+	return retval;
+invald_arg_out:
+	retval = -EINVAL;
+	return retval;
+}
+
+static ssize_t mxc_iim_write(struct file *filp, const char __user *buf,
+			size_t count, loff_t *f_pos)
+{
+	u32 bank;
+	ulong fuse_val;
+	u8 row;
+	u8 *tmp_buf = NULL;
+	loff_t file_pos = *f_pos;
+	ssize_t retval = 0;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+	dev_dbg(iim_data->dev, "count: %d f_pos: %lld\n", count, file_pos);
+
+	tmp_buf = kmalloc(count + 1, GFP_KERNEL);
+	if (unlikely(!tmp_buf)) {
+		retval = -ENOMEM;
+		goto out;
+	}
+	memset(tmp_buf, 0, count + 1);
+	if (copy_from_user(tmp_buf, buf, count)) {
+		retval = -EFAULT;
+		goto out;
+	}
+
+	if (count > 1 && 0 == file_pos) {
+		/* Check if file_pos and fuse val are in tmp_buf */
+		if (sscanf(tmp_buf, "%x %x",
+			(s32 *)&file_pos, (s32 *)&fuse_val) < 0) {
+			dev_info(iim_data->dev,
+				"Invalid input string: %s\n", tmp_buf);
+			retval = -EINVAL;
+			goto out;
+		}
+		dev_dbg(iim_data->dev,
+			"file_pos: 0x%08x, fuse_val: 0x%08x\n",
+			(s32)file_pos, (s32)fuse_val);
+	} else if (1 == count)
+		fuse_val = tmp_buf[0];
+	else {
+		dev_info(iim_data->dev,
+			"Invalid input: %s, count: %d, file pos: %d\n",
+			tmp_buf, count, (s32)file_pos);
+		retval = -EINVAL;
+		goto out;
+	}
+
+	if (fuse_val > 0xff) {
+		dev_info(iim_data->dev,
+			"Invalid blow value: 0x%08x\n", (s32)fuse_val);
+		retval = -EINVAL;
+		goto out;
+	}
+
+	if (file_pos & 0x3) {
+		dev_info(iim_data->dev, "file pos is not 4-byte aligned!\n");
+		retval = -EINVAL;
+		goto out;
+	}
+
+	if (file_pos < iim_data->bank_start ||
+		file_pos > iim_data->bank_end) {
+		dev_dbg(iim_data->dev,
+			"bank_start: 0x%08x, bank_end: 0x%08x\n",
+			iim_data->bank_start, iim_data->bank_end);
+		dev_info(iim_data->dev,
+			"file pos out of range: 0x%08x\n", (u32)file_pos);
+		retval = -EINVAL;
+		goto out;
+	}
+
+	bank = (file_pos - iim_data->bank_start) >> 10;
+	row  = ((file_pos - iim_data->bank_start) & 0x3ff) >> 2;
+
+	dev_info(iim_data->dev, "Blowing fuse at bank:%d row:%d value:%d\n",
+			bank, row, (int)fuse_val);
+	mutex_lock(&iim_data->mutex);
+	fuse_blow_row(bank, row, fuse_val);
+	fuse_val = sense_fuse(bank, row, 0);
+	mutex_unlock(&iim_data->mutex);
+	dev_info(iim_data->dev, "fuses at (bank:%d, row:%d) = 0x%x\n",
+		bank, row, (unsigned int)fuse_val);
+
+	retval = count;
+out:
+	if (tmp_buf)
+		kfree(tmp_buf);
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+	return retval;
+}
+
+/*!
+ * MXC IIM interface - memory map function
+ * This function maps IIM registers from IIM base address.
+ *
+ * @param file	     struct file *
+ * @param vma	     structure vm_area_struct *
+ *
+ * @return	     Return 0 on success or negative error code on error
+ */
+static int mxc_iim_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	/* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */
+	if (remap_pfn_range(vma,
+			    vma->vm_start,
+			    iim_data->reg_base >> PAGE_SHIFT,
+			    vma->vm_end - vma->vm_start,
+			    vma->vm_page_prot))
+		return -EAGAIN;
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+
+	return 0;
+}
+
+/*!
+ * MXC IIM interface - open function
+ *
+ * @param inode	     struct inode *
+ * @param filp	     struct file *
+ *
+ * @return	     Return 0 on success or negative error code on error
+ */
+static int mxc_iim_open(struct inode *inode, struct file *filp)
+{
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+
+	dev_dbg(iim_data->dev, "iim_data addr: 0x%08x\n", (u32)iim_data);
+
+	iim_data->clk = clk_get(NULL, "iim_clk");
+	if (IS_ERR(iim_data->clk)) {
+		dev_err(iim_data->dev, "No IIM clock defined\n");
+		return -ENODEV;
+	}
+	clk_enable(iim_data->clk);
+
+	mxc_iim_disable_irq();
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+
+	return 0;
+}
+
+/*!
+ * MXC IIM interface - release function
+ *
+ * @param inode	     struct inode *
+ * @param filp	     struct file *
+ *
+ * @return	     Return 0 on success or negative error code on error
+ */
+static int mxc_iim_release(struct inode *inode, struct file *filp)
+{
+	clk_disable(iim_data->clk);
+	clk_put(iim_data->clk);
+	return 0;
+}
+
+static const struct file_operations mxc_iim_fops = {
+	.read = mxc_iim_read,
+	.write = mxc_iim_write,
+	.llseek = mxc_iim_llseek,
+	.mmap = mxc_iim_mmap,
+	.open = mxc_iim_open,
+	.release = mxc_iim_release,
+};
+
+static struct miscdevice mxc_iim_miscdev = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "mxc_iim",
+	.fops = &mxc_iim_fops,
+};
+
+/*!
+ * This function is called by the driver framework to get iim base/end address
+ * and register iim misc device.
+ *
+ * @param	dev	The device structure for IIM passed in by the driver
+ *			framework.
+ *
+ * @return      Returns 0 on success or negative error code on error
+ */
+static __devinit int mxc_iim_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret;
+
+	iim_data = pdev->dev.platform_data;
+	iim_data->dev = &pdev->dev;
+	iim_data->name = mxc_iim_miscdev.name;
+
+	dev_dbg(iim_data->dev, "=> %s\n", __func__);
+
+	dev_dbg(iim_data->dev, "iim_data addr: 0x%08x "
+		"bank_start: 0x%04x bank_end: 0x%04x "
+		"enable_fuse: 0x%08x disable_fuse: 0x%08x\n",
+		(u32)iim_data,
+		iim_data->bank_start, iim_data->bank_end,
+		(u32)iim_data->enable_fuse,
+		(u32)iim_data->disable_fuse);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res)) {
+		dev_err(iim_data->dev, "Unable to get IIM resource\n");
+		return -ENODEV;
+	}
+
+	iim_data->irq = platform_get_irq(pdev, 0);
+	dev_dbg(iim_data->dev, "irq number: %d\n", iim_data->irq);
+	if (!iim_data->irq) {
+		ret = -ENOMEM;
+		return ret;
+	}
+
+	ret = request_irq(iim_data->irq, mxc_iim_irq, IRQF_DISABLED,
+			iim_data->name, iim_data);
+	if (ret)
+		return ret;
+
+	iim_data->reg_base = res->start;
+	iim_data->reg_end = res->end;
+	iim_data->reg_size =
+		iim_data->reg_end - iim_data->reg_base + 1;
+	iim_data->virt_base =
+		(u32)ioremap(iim_data->reg_base, iim_data->reg_size);
+
+	mutex_init(&(iim_data->mutex));
+	spin_lock_init(&(iim_data->lock));
+
+	ret = misc_register(&mxc_iim_miscdev);
+	if (ret)
+		return ret;
+
+	dev_dbg(iim_data->dev, "<= %s\n", __func__);
+
+	return 0;
+}
+
+static int __devexit mxc_iim_remove(struct platform_device *pdev)
+{
+	free_irq(iim_data->irq, iim_data);
+	iounmap((void *)iim_data->virt_base);
+	misc_deregister(&mxc_iim_miscdev);
+	return 0;
+}
+
+static struct platform_driver mxc_iim_driver = {
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = "mxc_iim",
+		   },
+	.probe = mxc_iim_probe,
+	.remove = mxc_iim_remove,
+};
+
+static int __init mxc_iim_dev_init(void)
+{
+	return platform_driver_register(&mxc_iim_driver);
+}
+
+static void __exit mxc_iim_dev_cleanup(void)
+{
+	platform_driver_unregister(&mxc_iim_driver);
+}
+
+module_init(mxc_iim_dev_init);
+module_exit(mxc_iim_dev_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC IIM driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(MISC_DYNAMIC_MINOR);
diff --git a/drivers/char/mxc_iim.h b/drivers/char/mxc_iim.h
new file mode 100644
index 00000000000..0a0814562da
--- /dev/null
+++ b/drivers/char/mxc_iim.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMX_IIM_H__
+#define __IMX_IIM_H__
+
+#include <linux/mutex.h>
+#include <linux/cdev.h>
+
+/* IIM Control Registers */
+struct iim_regs {
+	u32 stat;
+	u32 statm;
+	u32 err;
+	u32 emask;
+	u32 fctl;
+	u32 ua;
+	u32 la;
+	u32 sdat;
+	u32 prev;
+	u32 srev;
+	u32 preg_p;
+	u32 scs0;
+	u32 scs1;
+	u32 scs2;
+	u32 scs3;
+};
+
+#define IIM_STAT_BUSY   (1 << 7)
+#define IIM_STAT_PRGD   (1 << 1)
+#define IIM_STAT_SNSD   (1 << 0)
+
+#define IIM_ERR_PRGE    (1 << 7)
+#define IIM_ERR_WPE     (1 << 6)
+#define IIM_ERR_OPE     (1 << 5)
+#define IIM_ERR_RPE     (1 << 4)
+#define IIM_ERR_WLRE    (1 << 3)
+#define IIM_ERR_SNSE    (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+
+#define IIM_PROD_REV_SH         3
+#define IIM_PROD_REV_LEN        5
+#define IIM_SREV_REV_SH         4
+#define IIM_SREV_REV_LEN        4
+#define PROD_SIGNATURE_MX51     0x1
+
+#define IIM_ERR_SHIFT       8
+#define POLL_FUSE_PRGD      (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD      (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+
+#endif
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index f993955a640..c3d135afe66 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -7,7 +7,7 @@
  *
  * Based on code from Freescale:
  *
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -832,17 +832,18 @@ static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 
 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
+	unsigned long flags;
 	struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 	struct sdma_engine *sdma = sdmac->sdma;
 	dma_cookie_t cookie;
 
-	spin_lock_irq(&sdmac->lock);
+	spin_lock_irqsave(&sdmac->lock, flags);
 
 	cookie = sdma_assign_cookie(sdmac);
 
 	sdma_enable_channel(sdma, sdmac->channel);
 
-	spin_unlock_irq(&sdmac->lock);
+	spin_unlock_irqrestore(&sdmac->lock, flags);
 
 	return cookie;
 }
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 8482a23887d..a09a46f6b9d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -489,4 +489,11 @@ config GPIO_TPS65910
 	help
 	  Select this option to enable GPIO driver for the TPS65910
 	  chip family.
+
+config DA9052_GPIO_ENABLE
+	bool "Dialog DA9052 GPIO"
+	depends on PMIC_DIALOG
+	help
+	  Say Y  to enable the GPIO driver for the DA9052 chip
+
 endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4e018d6a763..f865b0c5371 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_GPIO_TIMBERDALE)	+= gpio-timberdale.o
 obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o
 obj-$(CONFIG_GPIO_TPS65910)	+= gpio-tps65910.o
 obj-$(CONFIG_GPIO_TPS65912)	+= gpio-tps65912.o
+obj-$(CONFIG_DA9052_GPIO_ENABLE) += da9052-gpio.o
 obj-$(CONFIG_GPIO_TWL4030)	+= gpio-twl4030.o
 obj-$(CONFIG_MACH_U300)		+= gpio-u300.o
 obj-$(CONFIG_GPIO_UCB1400)	+= gpio-ucb1400.o
diff --git a/drivers/gpio/da9052-gpio.c b/drivers/gpio/da9052-gpio.c
new file mode 100644
index 00000000000..a9c53f219c3
--- /dev/null
+++ b/drivers/gpio/da9052-gpio.c
@@ -0,0 +1,731 @@
+/*
+ * da9052-gpio.c  --  GPIO Driver for Dialog DA9052
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * Author: Dialog Semiconductor Ltd <dchen@diasemi.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/platform_device.h>
+#include <linux/syscalls.h>
+#include <linux/seq_file.h>
+#include <linux/gpio.h>
+
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/gpio.h>
+
+#define DRIVER_NAME "da9052-gpio"
+static inline struct da9052_gpio_chip *to_da9052_gpio(struct gpio_chip *chip)
+{
+	return container_of(chip, struct da9052_gpio_chip, gp);
+}
+
+void da9052_gpio_notifier(struct da9052_eh_nb *eh_data, unsigned int event)
+{
+	struct da9052_gpio_chip *gpio =
+			container_of(eh_data, struct da9052_gpio_chip, eh_data);
+	kobject_uevent(&gpio->gp.dev->kobj, KOBJ_CHANGE);
+	printk(KERN_INFO "Event received from GPIO8\n");
+}
+
+static u8 create_gpio_config_value(u8 gpio_function, u8 gpio_type, u8 gpio_mode)
+{
+	/* The format is -
+		function - 2 bits
+		type - 1 bit
+		mode - 1 bit */
+	return gpio_function | (gpio_type << 2) | (gpio_mode << 3);
+}
+
+static s32 write_default_gpio_values(struct da9052 *da9052)
+{
+	struct da9052_ssc_msg msg;
+	u8 created_val = 0;
+
+#if (DA9052_GPIO_PIN_0 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0001_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO0_FUNCTION,
+			DEFAULT_GPIO0_TYPE, DEFAULT_GPIO0_MODE);
+	msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+#if (DA9052_GPIO_PIN_1 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0001_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO1_FUNCTION,
+			DEFAULT_GPIO1_TYPE, DEFAULT_GPIO1_MODE);
+	created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT;
+	msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+/* GPIO 2-3*/
+#if (DA9052_GPIO_PIN_2 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0203_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO2_FUNCTION,
+			DEFAULT_GPIO2_TYPE, DEFAULT_GPIO2_MODE);
+	msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+#if (DA9052_GPIO_PIN_3 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0203_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO3_FUNCTION,
+			DEFAULT_GPIO3_TYPE, DEFAULT_GPIO3_MODE);
+	created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT;
+	msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+/* GPIO 4-5*/
+#if (DA9052_GPIO_PIN_4 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0405_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO4_FUNCTION,
+			DEFAULT_GPIO4_TYPE, DEFAULT_GPIO4_MODE);
+	msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+#if (DA9052_GPIO_PIN_5 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0405_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO5_FUNCTION,
+			DEFAULT_GPIO5_TYPE, DEFAULT_GPIO5_MODE);
+	created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT;
+	msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+/* GPIO 6-7*/
+#if (DA9052_GPIO_PIN_6 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0607_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO6_FUNCTION,
+			DEFAULT_GPIO6_TYPE, DEFAULT_GPIO6_MODE);
+	msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+#if (DA9052_GPIO_PIN_7 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0607_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO7_FUNCTION,
+			DEFAULT_GPIO7_TYPE, DEFAULT_GPIO7_MODE);
+	created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT;
+	msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+/* GPIO 8-9*/
+#if (DA9052_GPIO_PIN_8 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0809_REG;
+	msg.data = 0;
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO8_FUNCTION,
+			DEFAULT_GPIO8_TYPE, DEFAULT_GPIO8_MODE);
+	msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+#if (DA9052_GPIO_PIN_9 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO0809_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO9_FUNCTION,
+			DEFAULT_GPIO9_TYPE, DEFAULT_GPIO9_MODE);
+	created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT;
+	msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+/* GPIO 10-11*/
+#if (DA9052_GPIO_PIN_10 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO1011_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO10_FUNCTION,
+			DEFAULT_GPIO10_TYPE, DEFAULT_GPIO10_MODE);
+	msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+#if (DA9052_GPIO_PIN_11 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO1011_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO11_FUNCTION,
+			DEFAULT_GPIO11_TYPE, DEFAULT_GPIO11_MODE);
+	created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT;
+	msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+/* GPIO 12-13*/
+#if (DA9052_GPIO_PIN_12 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO1213_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO12_FUNCTION,
+			DEFAULT_GPIO12_TYPE, DEFAULT_GPIO12_MODE);
+	msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+#if (DA9052_GPIO_PIN_13 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO1213_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO13_FUNCTION,
+			DEFAULT_GPIO13_TYPE, DEFAULT_GPIO13_MODE);
+	created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT;
+	msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+/* GPIO 14-15*/
+#if (DA9052_GPIO_PIN_14 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO1415_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO14_FUNCTION,
+			DEFAULT_GPIO14_TYPE, DEFAULT_GPIO14_MODE);
+	msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+#if (DA9052_GPIO_PIN_15 == DA9052_GPIO_CONFIG)
+	da9052_lock(da9052);
+	msg.addr = DA9052_GPIO1415_REG;
+	msg.data = 0;
+
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+
+	created_val = create_gpio_config_value(DEFAULT_GPIO15_FUNCTION,
+			DEFAULT_GPIO15_TYPE, DEFAULT_GPIO15_MODE);
+	created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT;
+	msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE;
+	msg.data |= created_val;
+
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+#endif
+	return 0;
+}
+
+s32 da9052_gpio_read_port(struct da9052_gpio_read_write *read_port,
+				struct da9052 *da9052)
+{
+	struct da9052_ssc_msg msg;
+	u8 shift_value = 0;
+	u8 port_functionality = 0;
+	msg.addr = (read_port->port_number / 2) + DA9052_GPIO0001_REG;
+	msg.data = 0;
+	da9052_lock(da9052);
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+	port_functionality =
+			(read_port->port_number % 2) ?
+			((msg.data & DA9052_GPIO_ODD_PORT_FUNCTIONALITY) >>
+					DA9052_GPIO_NIBBLE_SHIFT) :
+			(msg.data & DA9052_GPIO_EVEN_PORT_FUNCTIONALITY);
+
+	if (port_functionality != INPUT)
+		return DA9052_GPIO_INVALID_PORTNUMBER;
+
+	if (read_port->port_number >= (DA9052_GPIO_MAX_PORTNUMBER))
+		return DA9052_GPIO_INVALID_PORTNUMBER;
+
+	if (read_port->port_number < DA9052_GPIO_MAX_PORTS_PER_REGISTER)
+		msg.addr = DA9052_STATUSC_REG;
+	else
+		msg.addr = DA9052_STATUSD_REG;
+	msg.data = 0;
+
+	da9052_lock(da9052);
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+
+	shift_value = msg.data &
+		(1 << DA9052_GPIO_SHIFT_COUNT(read_port->port_number));
+	read_port->read_write_value = (shift_value >>
+			DA9052_GPIO_SHIFT_COUNT(read_port->port_number));
+
+	return 0;
+}
+
+s32 da9052_gpio_multiple_read(struct da9052_gpio_multiple_read *multiple_port,
+				struct da9052 *da9052)
+{
+	struct da9052_ssc_msg msg[2];
+	u8 port_number = 0;
+	u8 loop_index = 0;
+	msg[loop_index++].addr = DA9052_STATUSC_REG;
+	msg[loop_index++].addr = DA9052_STATUSD_REG;
+
+	da9052_lock(da9052);
+	if (da9052->read_many(da9052, msg, loop_index)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+	loop_index = 0;
+	for (port_number = 0; port_number < DA9052_GPIO_MAX_PORTS_PER_REGISTER;
+							port_number++) {
+		multiple_port->signal_value[port_number] =
+			msg[loop_index].data & 1;
+		msg[loop_index].data = msg[loop_index].data >> 1;
+	}
+	loop_index++;
+	for (port_number = DA9052_GPIO_MAX_PORTS_PER_REGISTER;
+		port_number < DA9052_GPIO_MAX_PORTNUMBER; port_number++) {
+		multiple_port->signal_value[port_number] =
+			msg[loop_index].data & 1;
+		msg[loop_index].data = msg[loop_index].data >> 1;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(da9052_gpio_multiple_read);
+
+s32 da9052_gpio_write_port(struct da9052_gpio_read_write *write_port,
+				struct da9052 *da9052)
+{
+	struct da9052_ssc_msg msg;
+	u8 port_functionality  = 0;
+	u8 bit_pos = 0;
+	msg.addr = DA9052_GPIO0001_REG + (write_port->port_number / 2);
+	msg.data = 0;
+
+	da9052_lock(da9052);
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+
+	port_functionality =
+			(write_port->port_number % 2) ?
+			((msg.data & DA9052_GPIO_ODD_PORT_FUNCTIONALITY) >>
+						DA9052_GPIO_NIBBLE_SHIFT) :
+			(msg.data & DA9052_GPIO_EVEN_PORT_FUNCTIONALITY);
+
+	if (port_functionality < 2)
+		return DA9052_GPIO_INVALID_PORTNUMBER;
+
+	bit_pos = (write_port->port_number % 2) ?
+			DA9052_GPIO_ODD_PORT_WRITE_MODE :
+				DA9052_GPIO_EVEN_PORT_WRITE_MODE;
+
+	if (write_port->read_write_value)
+		msg.data = msg.data | bit_pos;
+	else
+		msg.data = (msg.data & ~(bit_pos));
+
+	da9052_lock(da9052);
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+	return 0;
+}
+
+s32 da9052_gpio_configure_port(struct da9052_gpio *gpio_data,
+				struct da9052 *da9052)
+{
+	struct da9052_ssc_msg msg;
+	u8 register_value = 0;
+	u8 function = 0;
+	u8 port_functionality = 0;
+	msg.addr = (gpio_data->port_number / 2) + DA9052_GPIO0001_REG;
+	msg.data = 0;
+
+	da9052_lock(da9052);
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+
+	port_functionality =
+			(gpio_data->port_number % 2) ?
+			((msg.data & DA9052_GPIO_ODD_PORT_FUNCTIONALITY) >>
+					DA9052_GPIO_NIBBLE_SHIFT) :
+			(msg.data & DA9052_GPIO_EVEN_PORT_FUNCTIONALITY);
+	if (port_functionality < INPUT)
+		return DA9052_GPIO_INVALID_PORTNUMBER;
+	if (gpio_data->gpio_config.input.type > ACTIVE_HIGH)
+		return DA9052_GPIO_INVALID_TYPE;
+	if (gpio_data->gpio_config.input.mode > DEBOUNCING_ON)
+		return DA9052_GPIO_INVALID_MODE;
+	function = gpio_data->gpio_function;
+	switch (function) {
+	case INPUT:
+		register_value = create_gpio_config_value(function,
+					gpio_data->gpio_config.input.type,
+					gpio_data->gpio_config.input.mode);
+	break;
+	case OUTPUT_OPENDRAIN:
+	case OUTPUT_PUSHPULL:
+		register_value = create_gpio_config_value(function,
+					gpio_data->gpio_config.input.type,
+					gpio_data->gpio_config.input.mode);
+	break;
+	default:
+		return DA9052_GPIO_INVALID_FUNCTION;
+	break;
+	}
+
+	if (gpio_data->port_number % 2) {
+		msg.data = (msg.data & ~(DA9052_GPIO_MASK_UPPER_NIBBLE)) |
+				(register_value << DA9052_GPIO_NIBBLE_SHIFT);
+	} else {
+		msg.data = (msg.data & ~(DA9052_GPIO_MASK_LOWER_NIBBLE)) |
+				register_value;
+	}
+	da9052_lock(da9052);
+	if (da9052->write(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return -EIO;
+	}
+	da9052_unlock(da9052);
+	return 0;
+}
+
+static s32 da9052_gpio_read(struct gpio_chip *gc, u32 offset)
+{
+	struct da9052_gpio_chip *gpio;
+	gpio = to_da9052_gpio(gc);
+	gpio->read_write.port_number		= offset;
+	da9052_gpio_read_port(&gpio->read_write, gpio->da9052);
+	return gpio->read_write.read_write_value;
+}
+
+static void da9052_gpio_write(struct gpio_chip *gc, u32 offset, s32 value)
+{
+	struct da9052_gpio_chip *gpio;
+	gpio = to_da9052_gpio(gc);
+	gpio->read_write.port_number		= offset;
+	gpio->read_write.read_write_value	= (u8)value;
+	da9052_gpio_write_port(&gpio->read_write, gpio->da9052);
+}
+
+static s32 da9052_gpio_ip(struct gpio_chip *gc, u32 offset)
+{
+	struct da9052_gpio_chip *gpio;
+	gpio = to_da9052_gpio(gc);
+	gpio->gpio.gpio_function			= INPUT;
+	gpio->gpio.gpio_config.input.type	= ACTIVE_LOW;
+	gpio->gpio.gpio_config.input.mode	= DEBOUNCING_ON;
+	gpio->gpio.port_number				= offset;
+	return da9052_gpio_configure_port(&gpio->gpio, gpio->da9052);
+}
+
+static s32 da9052_gpio_op(struct gpio_chip *gc, u32 offset, s32 value)
+{
+	struct da9052_gpio_chip *gpio;
+	gpio = to_da9052_gpio(gc);
+	gpio->gpio.gpio_function		= OUTPUT_PUSHPULL;
+	gpio->gpio.gpio_config.output.type	= SUPPLY_VDD_IO1;
+	gpio->gpio.gpio_config.output.mode	= value;
+	gpio->gpio.port_number			= offset;
+	return da9052_gpio_configure_port(&gpio->gpio, gpio->da9052);
+}
+
+static int da9052_gpio_to_irq(struct gpio_chip *gc, u32 offset)
+{
+	struct da9052_gpio_chip *gpio;
+	gpio = to_da9052_gpio(gc);
+	kobject_uevent(&gpio->gp.dev->kobj, KOBJ_CHANGE);
+	printk(KERN_INFO"gpio->gp.base +offset = %d\n", gpio->gp.base + offset);
+	printk(KERN_INFO"Test1\n\n");
+	return gpio->gp.base + offset;
+}
+
+static int __devinit da9052_gpio_probe(struct platform_device *pdev)
+{
+	struct da9052_gpio_chip *gpio;
+	struct da9052_platform_data *pdata = (pdev->dev.platform_data);
+	s32 ret;
+	gpio = kzalloc(sizeof(*gpio), GFP_KERNEL);
+	if (gpio == NULL)
+		return -ENOMEM;
+	gpio->da9052 = dev_get_drvdata(pdev->dev.parent);
+	gpio->gp.get			= da9052_gpio_read;
+	gpio->gp.direction_input	= da9052_gpio_ip;
+	gpio->gp.direction_output	= da9052_gpio_op;
+	gpio->gp.set			= da9052_gpio_write;
+
+	gpio->gp.base				= pdata->gpio_base;
+	gpio->gp.ngpio				= DA9052_GPIO_MAX_PORTNUMBER;
+	gpio->gp.can_sleep			= 1;
+	gpio->gp.dev				= &pdev->dev;
+	gpio->gp.owner				= THIS_MODULE;
+	gpio->gp.label				= "da9052-gpio";
+	gpio->gp.to_irq				= da9052_gpio_to_irq;
+
+	gpio->eh_data.eve_type = GPI8_EVE;
+	gpio->eh_data.call_back = &da9052_gpio_notifier;
+	ret = gpio->da9052->register_event_notifier(gpio->da9052,
+			&gpio->eh_data);
+
+	ret = write_default_gpio_values(gpio->da9052);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "GPIO initial config failed, %d\n",
+			ret);
+		goto ret;
+	}
+
+	ret = gpiochip_add(&gpio->gp);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
+			ret);
+		goto ret;
+	}
+	platform_set_drvdata(pdev, gpio);
+
+	return ret;
+
+ret:
+	kfree(gpio);
+	return ret;
+
+}
+
+static int __devexit da9052_gpio_remove(struct platform_device *pdev)
+{
+	struct da9052_gpio_chip *gpio = platform_get_drvdata(pdev);
+	int ret;
+
+	gpio->da9052->unregister_event_notifier
+			(gpio->da9052, &gpio->eh_data);
+	ret = gpiochip_remove(&gpio->gp);
+	if (ret == 0)
+		kfree(gpio);
+	return 0;
+}
+
+static struct platform_driver da9052_gpio_driver = {
+	.probe		= da9052_gpio_probe,
+	.remove		= __devexit_p(da9052_gpio_remove),
+	.driver		= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init da9052_gpio_init(void)
+{
+	return platform_driver_register(&da9052_gpio_driver);
+}
+
+static void __exit da9052_gpio_exit(void)
+{
+	return platform_driver_unregister(&da9052_gpio_driver);
+}
+
+module_init(da9052_gpio_init);
+module_exit(da9052_gpio_exit);
+
+MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
+MODULE_DESCRIPTION("DA9052 GPIO Device Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 91be41f6080..bc658aeefdb 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -39,6 +39,16 @@ config HWMON_DEBUG_CHIP
 
 comment "Native drivers"
 
+config SENSORS_DA9052
+	tristate "Dialog DA9052 HWMon"
+	depends on PMIC_DIALOG
+	help
+	  Say y here to support the ADC found on Dialog Semiconductor DA9052
+	  PMIC.
+
+	  This driver can also be built as a module.  If so, the module
+	  will be called da9052-adc.
+
 config SENSORS_ABITUGURU
 	tristate "Abit uGuru (rev 1 & 2)"
 	depends on X86 && DMI && EXPERIMENTAL
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 8251ce8cd03..7e2f333bb65 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -125,6 +125,7 @@ obj-$(CONFIG_SENSORS_W83L785TS)	+= w83l785ts.o
 obj-$(CONFIG_SENSORS_W83L786NG)	+= w83l786ng.o
 obj-$(CONFIG_SENSORS_WM831X)	+= wm831x-hwmon.o
 obj-$(CONFIG_SENSORS_WM8350)	+= wm8350-hwmon.o
+obj-$(CONFIG_SENSORS_DA9052)	+= da9052-adc.o
 
 obj-$(CONFIG_PMBUS)		+= pmbus/
 
diff --git a/drivers/hwmon/da9052-adc.c b/drivers/hwmon/da9052-adc.c
new file mode 100644
index 00000000000..57985c2294b
--- /dev/null
+++ b/drivers/hwmon/da9052-adc.c
@@ -0,0 +1,644 @@
+/*
+ * da9052-adc.c  --  ADC Driver for Dialog DA9052
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * Author: Dialog Semiconductor Ltd <dchen@diasemi.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+#include <linux/platform_device.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/hwmon.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/adc.h>
+
+#define DRIVER_NAME "da9052-adc"
+
+static const char * const input_names[] = {
+	[DA9052_ADC_VDDOUT]	=	"VDDOUT",
+	[DA9052_ADC_ICH]	=	"CHARGING CURRENT",
+	[DA9052_ADC_TBAT]	=	"BATTERY TEMP",
+	[DA9052_ADC_VBAT]	=	"BATTERY VOLTAGE",
+	[DA9052_ADC_ADCIN4]	=	"ADC INPUT 4",
+	[DA9052_ADC_ADCIN5]	=	"ADC INPUT 5",
+	[DA9052_ADC_ADCIN6]	=	"ADC INPUT 6",
+	[DA9052_ADC_TSI]	=	"TSI",
+	[DA9052_ADC_TJUNC]	=	"BATTERY JUNCTION TEMP",
+	[DA9052_ADC_VBBAT]	=	"BACK-UP BATTERY TEMP",
+};
+
+
+int da9052_manual_read(struct da9052 *da9052,
+			unsigned char channel)
+{
+	unsigned char man_timeout_cnt = DA9052_ADC_MAX_MANCONV_RETRY_COUNT;
+	struct da9052_ssc_msg msg;
+	unsigned short calc_data;
+	unsigned int ret;
+	u16 data = 0;
+
+	msg.addr = DA9052_ADCMAN_REG;
+	msg.data = channel;
+	msg.data =  (msg.data | DA9052_ADCMAN_MANCONV);
+
+	mutex_lock(&da9052->manconv_lock);
+	da9052_lock(da9052);
+
+	ret = da9052->write(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+
+	/* Wait for the event */
+	do {
+		msg.addr = DA9052_ADCCONT_REG;
+		msg.data = 0;
+		da9052_lock(da9052);
+		ret = da9052->read(da9052, &msg);
+		if (ret)
+			goto err_ssc_comm;
+		da9052_unlock(da9052);
+
+		if (DA9052_ADCCONT_ADCMODE & msg.data)
+			msleep(1);
+		else
+			msleep(10);
+
+		msg.addr = DA9052_ADCMAN_REG;
+		msg.data = 0;
+		da9052_lock(da9052);
+		ret = da9052->read(da9052, &msg);
+		if (ret)
+			goto err_ssc_comm;
+		da9052_unlock(da9052);
+
+		/* Counter to avoid endless while loop */
+		man_timeout_cnt--;
+		if (man_timeout_cnt == 1) {
+			if (!(msg.data & DA9052_ADCMAN_MANCONV))
+				break;
+			else
+				goto err_ssc_comm;
+		}
+	/* Wait until the MAN_CONV bit is cleared to zero */
+	} while (msg.data & DA9052_ADCMAN_MANCONV);
+
+	msg.addr = DA9052_ADCRESH_REG;
+	msg.data = 0;
+
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+
+	calc_data = (unsigned short)msg.data;
+	data = (calc_data << 2);
+
+	msg.addr = DA9052_ADCRESL_REG;
+	msg.data = 0;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+
+	/* Clear first 14 bits before ORing */
+	calc_data = (unsigned short)msg.data & 0x0003;
+	data |= calc_data;
+
+	mutex_unlock(&da9052->manconv_lock);
+
+	return data;
+err_ssc_comm:
+	mutex_unlock(&da9052->manconv_lock);
+	da9052_unlock(da9052);
+	return -EIO;
+}
+EXPORT_SYMBOL(da9052_manual_read);
+
+int da9052_read_tjunc(struct da9052 *da9052, char *buf)
+{
+	struct da9052_ssc_msg msg;
+	unsigned char temp;
+	int ret;
+
+	msg.addr = DA9052_TJUNCRES_REG;
+	msg.data = 0;
+
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+
+	temp = msg.data;
+
+	msg.addr = DA9052_TOFFSET_REG;
+	msg.data = 0;
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+	/* Calculate Junction temperature */
+	temp = (temp - msg.data);
+	*buf = temp;
+	return 0;
+err_ssc_comm:
+	da9052_unlock(da9052);
+	return -EIO;
+}
+EXPORT_SYMBOL(da9052_read_tjunc);
+
+int da9052_read_tbat_ich(struct da9052 *da9052, char *data, int channel_no)
+{
+	struct da9052_ssc_msg msg;
+	int ret;
+
+	/* Read TBAT conversion result */
+	switch (channel_no) {
+	case DA9052_ADC_TBAT:
+		msg.addr = DA9052_TBATRES_REG;
+	break;
+	case DA9052_ADC_ICH:
+		msg.addr = DA9052_ICHGAV_REG;
+	break;
+	default:
+		return -EINVAL;
+	}
+	msg.data = 0;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+	*data = msg.data;
+	printk(KERN_INFO"msg.data 1= %d\n", msg.data);
+	msg.data = 28;
+	da9052_lock(da9052);
+	ret = da9052->write(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+	printk(KERN_INFO"msg.data2 = %d\n", msg.data);
+	msg.data = 0;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+	printk(KERN_INFO"msg.data3 = %d\n", msg.data);
+	return 0;
+
+err_ssc_comm:
+	da9052_unlock(da9052);
+	return ret;
+}
+EXPORT_SYMBOL(da9052_read_tbat_ich);
+
+static int da9052_start_adc(struct da9052 *da9052, unsigned channel)
+{
+	struct da9052_ssc_msg msg;
+	int ret;
+
+	msg.addr = DA9052_ADCCONT_REG;
+	msg.data = 0;
+
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+
+	if (channel == DA9052_ADC_VDDOUT)
+		msg.data = (msg.data | DA9052_ADCCONT_AUTOVDDEN);
+	else if (channel == DA9052_ADC_ADCIN4)
+		msg.data = (msg.data | DA9052_ADCCONT_AUTOAD4EN);
+	else if (channel == DA9052_ADC_ADCIN5)
+		msg.data = (msg.data | DA9052_ADCCONT_AUTOAD5EN);
+	else if (channel == DA9052_ADC_ADCIN6)
+		msg.data = (msg.data | DA9052_ADCCONT_AUTOAD6EN);
+	else
+		return -EINVAL;
+
+	ret = da9052->write(da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+	return 0;
+
+err_ssc_comm:
+	da9052_unlock(da9052);
+	return -EIO;
+}
+
+static int da9052_stop_adc(struct da9052 *da9052, unsigned channel)
+{
+	int ret;
+	struct da9052_ssc_msg msg;
+
+	msg.addr = DA9052_ADCCONT_REG;
+	msg.data = 0;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+
+	if (channel == DA9052_ADC_VDDOUT)
+		msg.data = (msg.data & ~(DA9052_ADCCONT_AUTOVDDEN));
+	else if (channel == DA9052_ADC_ADCIN4)
+		msg.data = (msg.data & ~(DA9052_ADCCONT_AUTOAD4EN));
+	else if (channel == DA9052_ADC_ADCIN5)
+		msg.data = (msg.data & ~(DA9052_ADCCONT_AUTOAD5EN));
+	else if (channel == DA9052_ADC_ADCIN6)
+		msg.data =  (msg.data & ~(DA9052_ADCCONT_AUTOAD6EN));
+	else
+		return -EINVAL;
+
+	ret = da9052->write(da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+
+	return 0;
+err_ssc_comm:
+	da9052_unlock(da9052);
+	return -EIO;
+}
+
+static ssize_t da9052_adc_read_start_stop(struct device *dev,
+	struct device_attribute *devattr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct da9052_adc_priv *priv = platform_get_drvdata(pdev);
+	struct da9052_ssc_msg msg;
+	int channel = to_sensor_dev_attr(devattr)->index;
+	int ret;
+
+	ret = da9052_start_adc(priv->da9052, channel);
+	if (ret < 0)
+		return ret;
+
+	/* Read the ADC converted value */
+	switch (channel) {
+	case DA9052_ADC_VDDOUT:
+		msg.addr = DA9052_VDDRES_REG;
+	break;
+#if (DA9052_ADC_CONF_ADC4 == 1)
+	case DA9052_ADC_ADCIN4:
+		msg.addr = DA9052_ADCIN4RES_REG;
+	break;
+#endif
+#if (DA9052_ADC_CONF_ADC5 == 1)
+	case DA9052_ADC_ADCIN5:
+		msg.addr = DA9052_ADCIN5RES_REG;
+	break;
+#endif
+#if (DA9052_ADC_CONF_ADC6 == 1)
+	case DA9052_ADC_ADCIN6:
+		msg.addr = DA9052_ADCIN6RES_REG;
+	break;
+#endif
+	default:
+		return -EINVAL;
+	}
+	msg.data = 0;
+	da9052_lock(priv->da9052);
+	ret = priv->da9052->read(priv->da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+	da9052_unlock(priv->da9052);
+
+	ret = da9052_stop_adc(priv->da9052, channel);
+	if (ret < 0)
+		return ret;
+
+	return sprintf(buf, "%u\n", msg.data);
+
+err_ssc_comm:
+	da9052_unlock(priv->da9052);
+	return ret;
+}
+
+static ssize_t da9052_adc_read_ich(struct device *dev,
+	struct device_attribute *devattr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct da9052_adc_priv *priv = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = da9052_read_tbat_ich(priv->da9052, buf, DA9052_ADC_ICH);
+	if (ret < 0)
+		return ret;
+	return sprintf(buf, "%u\n", *buf);
+}
+
+static ssize_t da9052_adc_read_tbat(struct device *dev,
+	struct device_attribute *devattr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct da9052_adc_priv *priv = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = da9052_read_tbat_ich(priv->da9052, buf, DA9052_ADC_TBAT);
+	if (ret < 0)
+		return ret;
+	return sprintf(buf, "%u\n", *buf);
+}
+
+static ssize_t da9052_adc_read_vbat(struct device *dev,
+	struct device_attribute *devattr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct da9052_adc_priv *priv = platform_get_drvdata(pdev);
+	s32 ret;
+
+	ret = da9052_manual_read(priv->da9052, DA9052_ADC_VBAT);
+	if (ret < 0)
+		return ret;
+	return sprintf(buf, "%u\n", ret);
+}
+
+static ssize_t da9052_adc_read_tjunc(struct device *dev,
+	struct device_attribute *devattr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct da9052_adc_priv *priv = platform_get_drvdata(pdev);
+	int ret;
+	ret = da9052_read_tjunc(priv->da9052, buf);
+	if (ret < 0)
+		return ret;
+	return sprintf(buf, "%u\n", *buf);
+}
+
+static ssize_t da9052_adc_read_vbbat(struct device *dev,
+	struct device_attribute *devattr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct da9052_adc_priv *priv = platform_get_drvdata(pdev);
+	s32 ret;
+
+	ret = da9052_manual_read(priv->da9052, DA9052_ADC_VBBAT);
+	if (ret < 0)
+		return ret;
+	return sprintf(buf, "%u\n", ret);
+}
+
+static int da9052_adc_hw_init(struct da9052 *da9052)
+{
+	struct da9052_ssc_msg msg;
+	int ret;
+
+	/* ADC channel 4 and 5 are by default enabled */
+#if (DA9052_ADC_CONF_ADC4 == 1)
+	msg.addr = DA9052_GPIO0001_REG;
+	msg.data = 0;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+
+	msg.data = (msg.data & ~(DA9052_GPIO0001_GPIO0PIN));
+	ret = da9052->write(da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+#endif
+
+#if (DA9052_ADC_CONF_ADC5 == 1)
+	msg.addr = DA9052_GPIO0001_REG;
+	msg.data = 0;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+
+	msg.data = (msg.data & ~(DA9052_GPIO0001_GPIO0PIN));
+	ret = da9052->write(da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+#endif
+
+#if (DA9052_ADC_CONF_ADC6 == 1)
+	msg.addr = DA9052_GPIO0203_REG;
+	msg.data = 0;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto err_ssc_comm;
+
+	msg.data = (msg.data & ~(DA9052_GPIO0203_GPIO2PIN));
+	ret = da9052->write(da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+#endif
+#if 0
+	/* By default configure the Measurement sequence interval to 10ms */
+	msg.addr = DA9052_ADCCONT_REG;
+	msg.data = 0;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+
+	/* Set the ADC MODE bit for 10msec sampling timer */
+	msg.data = (msg.data & ~(DA9052_ADCCONT_ADCMODE));
+	ret = da9052->write(da9052, &msg);
+	if (ret != 0)
+		goto err_ssc_comm;
+	da9052_unlock(da9052);
+#endif
+	return 0;
+err_ssc_comm:
+	da9052_unlock(da9052);
+	return -EIO;
+}
+
+static ssize_t da9052_adc_show_name(struct device *dev,
+		struct device_attribute *devattr, char *buf)
+{
+	return sprintf(buf, "da9052-adc\n");
+}
+
+static ssize_t show_label(struct device *dev,
+			  struct device_attribute *devattr, char *buf)
+{
+	int channel = to_sensor_dev_attr(devattr)->index;
+
+	return sprintf(buf, "%s\n", input_names[channel]);
+}
+#define DA9052_ADC_CHANNELS(id, name) \
+	static SENSOR_DEVICE_ATTR(in##id##_label, S_IRUGO, show_label, \
+				  NULL, name)
+
+DA9052_ADC_CHANNELS(0, DA9052_ADC_VDDOUT);
+DA9052_ADC_CHANNELS(1, DA9052_ADC_ICH);
+DA9052_ADC_CHANNELS(2, DA9052_ADC_TBAT);
+DA9052_ADC_CHANNELS(3, DA9052_ADC_VBAT);
+#if (DA9052_ADC_CONF_ADC4 == 1)
+DA9052_ADC_CHANNELS(4, DA9052_ADC_ADCIN4);
+#endif
+#if (DA9052_ADC_CONF_ADC5 == 1)
+DA9052_ADC_CHANNELS(5, DA9052_ADC_ADCIN5);
+#endif
+#if (DA9052_ADC_CONF_ADC6 == 1)
+DA9052_ADC_CHANNELS(6, DA9052_ADC_ADCIN6);
+#endif
+DA9052_ADC_CHANNELS(7, DA9052_ADC_TSI);
+DA9052_ADC_CHANNELS(8, DA9052_ADC_TJUNC);
+DA9052_ADC_CHANNELS(9, DA9052_ADC_VBBAT);
+
+
+static DEVICE_ATTR(name, S_IRUGO, da9052_adc_show_name, NULL);
+static SENSOR_DEVICE_ATTR(read_vddout, S_IRUGO,
+				da9052_adc_read_start_stop, NULL,
+				DA9052_ADC_VDDOUT);
+static SENSOR_DEVICE_ATTR(read_ich, S_IRUGO, da9052_adc_read_ich, NULL,
+				DA9052_ADC_ICH);
+static SENSOR_DEVICE_ATTR(read_tbat, S_IRUGO, da9052_adc_read_tbat, NULL,
+				DA9052_ADC_TBAT);
+static SENSOR_DEVICE_ATTR(read_vbat, S_IRUGO, da9052_adc_read_vbat, NULL,
+				DA9052_ADC_VBAT);
+#if (DA9052_ADC_CONF_ADC4 == 1)
+static SENSOR_DEVICE_ATTR(in4_input, S_IRUGO, da9052_adc_read_start_stop, NULL,
+				DA9052_ADC_ADCIN4);
+#endif
+#if (DA9052_ADC_CONF_ADC5 == 1)
+static SENSOR_DEVICE_ATTR(in5_input, S_IRUGO, da9052_adc_read_start_stop, NULL,
+				DA9052_ADC_ADCIN5);
+#endif
+#if (DA9052_ADC_CONF_ADC6 == 1)
+static SENSOR_DEVICE_ATTR(in6_input, S_IRUGO, da9052_adc_read_start_stop, NULL,
+				DA9052_ADC_ADCIN6);
+#endif
+static SENSOR_DEVICE_ATTR(read_tjunc, S_IRUGO, da9052_adc_read_tjunc, NULL,
+				DA9052_ADC_TJUNC);
+static SENSOR_DEVICE_ATTR(read_vbbat, S_IRUGO, da9052_adc_read_vbbat, NULL,
+				DA9052_ADC_VBBAT);
+
+static struct attribute *da9052_attr[] = {
+	&dev_attr_name.attr,
+	&sensor_dev_attr_read_vddout.dev_attr.attr,
+	&sensor_dev_attr_in0_label.dev_attr.attr,
+	&sensor_dev_attr_read_ich.dev_attr.attr,
+	&sensor_dev_attr_in1_label.dev_attr.attr,
+	&sensor_dev_attr_read_tbat.dev_attr.attr,
+	&sensor_dev_attr_in2_label.dev_attr.attr,
+	&sensor_dev_attr_read_vbat.dev_attr.attr,
+	&sensor_dev_attr_in3_label.dev_attr.attr,
+#if (DA9052_ADC_CONF_ADC4 == 1)
+	&sensor_dev_attr_in4_input.dev_attr.attr,
+	&sensor_dev_attr_in4_label.dev_attr.attr,
+#endif
+#if (DA9052_ADC_CONF_ADC5 == 1)
+	&sensor_dev_attr_in5_input.dev_attr.attr,
+	&sensor_dev_attr_in5_label.dev_attr.attr,
+#endif
+#if (DA9052_ADC_CONF_ADC6 == 1)
+	&sensor_dev_attr_in6_input.dev_attr.attr,
+	&sensor_dev_attr_in6_label.dev_attr.attr,
+#endif
+	&sensor_dev_attr_in7_label.dev_attr.attr,
+	&sensor_dev_attr_read_tjunc.dev_attr.attr,
+	&sensor_dev_attr_in8_label.dev_attr.attr,
+	&sensor_dev_attr_read_vbbat.dev_attr.attr,
+	&sensor_dev_attr_in9_label.dev_attr.attr,
+	NULL
+};
+
+static const struct attribute_group da9052_group = {
+	.attrs = da9052_attr,
+};
+
+static int __init da9052_adc_probe(struct platform_device *pdev)
+{
+	struct da9052_adc_priv *priv;
+	int ret;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->da9052 = dev_get_drvdata(pdev->dev.parent);
+
+	platform_set_drvdata(pdev, priv);
+
+	/* Register sysfs hooks */
+	ret = sysfs_create_group(&pdev->dev.kobj, &da9052_group);
+	if (ret)
+		goto out_err_create1;
+
+	priv->hwmon_dev = hwmon_device_register(&pdev->dev);
+	if (IS_ERR(priv->hwmon_dev)) {
+		ret = PTR_ERR(priv->hwmon_dev);
+		goto out_err_create2;
+	}
+	/* Initializes the hardware for ADC module */
+	da9052_adc_hw_init(priv->da9052);
+
+	/* Initialize mutex required for ADC Manual read */
+	mutex_init(&priv->da9052->manconv_lock);
+
+	return 0;
+
+out_err_create2:
+	sysfs_remove_group(&pdev->dev.kobj, &da9052_group);
+out_err_create1:
+	platform_set_drvdata(pdev, NULL);
+	kfree(priv);
+
+	return ret;
+}
+
+static int __devexit da9052_adc_remove(struct platform_device *pdev)
+{
+	struct da9052_adc_priv *priv = platform_get_drvdata(pdev);
+
+	mutex_destroy(&priv->da9052->manconv_lock);
+
+	hwmon_device_unregister(priv->hwmon_dev);
+
+	sysfs_remove_group(&pdev->dev.kobj, &da9052_group);
+
+	platform_set_drvdata(pdev, NULL);
+	kfree(priv);
+
+	return 0;
+}
+
+static struct platform_driver da9052_adc_driver = {
+	.remove		= __devexit_p(da9052_adc_remove),
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= DRIVER_NAME,
+	},
+};
+
+static int __init da9052_adc_init(void)
+{
+	return platform_driver_probe(&da9052_adc_driver, da9052_adc_probe);
+}
+module_init(da9052_adc_init);
+
+static void __exit da9052_adc_exit(void)
+{
+	platform_driver_unregister(&da9052_adc_driver);
+}
+module_exit(da9052_adc_exit);
+
+MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
+MODULE_DESCRIPTION("DA9052 ADC driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 22d875fde53..53ecd769dfc 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -544,4 +544,14 @@ config INPUT_XEN_KBDDEV_FRONTEND
 	  To compile this driver as a module, choose M here: the
 	  module will be called xen-kbdfront.
 
+config INPUT_DA9052_ONKEY
+	tristate "Dialog DA9052 Onkey"
+	depends on PMIC_DIALOG
+	help
+	  Support the ONKEY of Dialog DA9052 PMICs as an input device
+	  reporting power button status.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called da9052_onkey.
+
 endif
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index a244fc6a781..bb0db4c3470 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_INPUT_WISTRON_BTNS)	+= wistron_btns.o
 obj-$(CONFIG_INPUT_WM831X_ON)		+= wm831x-on.o
 obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND)	+= xen-kbdfront.o
 obj-$(CONFIG_INPUT_YEALINK)		+= yealink.o
+obj-$(CONFIG_INPUT_DA9052_ONKEY)	+= da9052_onkey.o
diff --git a/drivers/input/misc/da9052_onkey.c b/drivers/input/misc/da9052_onkey.c
new file mode 100644
index 00000000000..295b2005cbe
--- /dev/null
+++ b/drivers/input/misc/da9052_onkey.c
@@ -0,0 +1,133 @@
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/reg.h>
+
+#define DRIVER_NAME "da9052-onkey"
+
+struct da9052_onkey_data {
+	struct da9052 *da9052;
+	struct da9052_eh_nb eh_data;
+	struct input_dev *input;
+};
+
+static void da9052_onkey_report_event(struct da9052_eh_nb *eh_data,
+				unsigned int event)
+{
+	struct da9052_onkey_data *da9052_onkey =
+		container_of(eh_data, struct da9052_onkey_data, eh_data);
+	struct da9052_ssc_msg msg;
+	unsigned int ret;
+
+	/* Read the Evnet Register */
+	msg.addr = DA9052_EVENTB_REG;
+	da9052_lock(da9052_onkey->da9052);
+	ret = da9052_onkey->da9052->read(da9052_onkey->da9052, &msg);
+	if (ret) {
+		da9052_unlock(da9052_onkey->da9052);
+		return;
+	}
+	da9052_unlock(da9052_onkey->da9052);
+	msg.data = msg.data & DA9052_EVENTB_ENONKEY;
+
+	input_report_key(da9052_onkey->input, KEY_POWER, msg.data);
+	input_sync(da9052_onkey->input);
+	printk(KERN_INFO "DA9052 ONKEY EVENT REPORTED\n");
+}
+
+static int __devinit da9052_onkey_probe(struct platform_device *pdev)
+{
+	struct da9052_onkey_data *da9052_onkey;
+	int error;
+
+	da9052_onkey = kzalloc(sizeof(*da9052_onkey), GFP_KERNEL);
+	da9052_onkey->input = input_allocate_device();
+	if (!da9052_onkey->input) {
+		dev_err(&pdev->dev, "failed to allocate data device\n");
+		error = -ENOMEM;
+		goto fail1;
+	}
+	da9052_onkey->da9052 = dev_get_drvdata(pdev->dev.parent);
+
+	if (!da9052_onkey->input) {
+		dev_err(&pdev->dev, "failed to allocate input device\n");
+		error = -ENOMEM;
+		goto fail2;
+	}
+
+	da9052_onkey->input->evbit[0] = BIT_MASK(EV_KEY);
+	da9052_onkey->input->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER);
+	da9052_onkey->input->name = "da9052-onkey";
+	da9052_onkey->input->phys = "da9052-onkey/input0";
+	da9052_onkey->input->dev.parent = &pdev->dev;
+
+	/* Set the EH structure */
+	da9052_onkey->eh_data.eve_type = ONKEY_EVE;
+	da9052_onkey->eh_data.call_back = &da9052_onkey_report_event;
+	error = da9052_onkey->da9052->register_event_notifier(
+				da9052_onkey->da9052,
+				&da9052_onkey->eh_data);
+	if (error)
+		goto fail2;
+
+	error = input_register_device(da9052_onkey->input);
+	if (error) {
+		dev_err(&pdev->dev, "Unable to register input "
+				"device,error: %d\n", error);
+		goto fail3;
+	}
+
+	platform_set_drvdata(pdev, da9052_onkey);
+
+	return 0;
+
+fail3:
+	da9052_onkey->da9052->unregister_event_notifier(da9052_onkey->da9052,
+					&da9052_onkey->eh_data);
+fail2:
+	input_free_device(da9052_onkey->input);
+fail1:
+	kfree(da9052_onkey);
+	return error;
+}
+
+static int __devexit da9052_onkey_remove(struct platform_device *pdev)
+{
+	struct da9052_onkey_data *da9052_onkey = pdev->dev.platform_data;
+	da9052_onkey->da9052->unregister_event_notifier(da9052_onkey->da9052,
+					&da9052_onkey->eh_data);
+	input_unregister_device(da9052_onkey->input);
+	kfree(da9052_onkey);
+
+	return 0;
+}
+
+static struct platform_driver da9052_onkey_driver = {
+	.probe		= da9052_onkey_probe,
+	.remove		= __devexit_p(da9052_onkey_remove),
+	.driver		= {
+		.name	= "da9052-onkey",
+		.owner	= THIS_MODULE,
+	}
+};
+
+static int __init da9052_onkey_init(void)
+{
+	return platform_driver_register(&da9052_onkey_driver);
+}
+
+static void __exit da9052_onkey_exit(void)
+{
+	platform_driver_unregister(&da9052_onkey_driver);
+}
+
+module_init(da9052_onkey_init);
+module_exit(da9052_onkey_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
+MODULE_DESCRIPTION("Onkey driver for DA9052");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 3488ffe1fa0..0a3433db0c8 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -738,4 +738,11 @@ config TOUCHSCREEN_TPS6507X
 	  To compile this driver as a module, choose M here: the
 	  module will be called tps6507x_ts.
 
+config TOUCHSCREEN_DA9052
+        tristate "Dialog DA9052 TSI"
+        depends on PMIC_DIALOG
+        help
+          Say y here to support the touchscreen found on
+          Dialog Semiconductor DA9052 PMIC
+
 endif
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index f957676035a..dbc9563dadb 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -6,6 +6,8 @@
 
 wm97xx-ts-y := wm97xx-core.o
 
+da9052-tsi-objs				:= da9052_tsi.o da9052_tsi_filter.o da9052_tsi_calibrate.o
+obj-$(CONFIG_TOUCHSCREEN_DA9052)      	 += da9052-tsi.o
 obj-$(CONFIG_TOUCHSCREEN_88PM860X)	+= 88pm860x-ts.o
 obj-$(CONFIG_TOUCHSCREEN_AD7877)	+= ad7877.o
 obj-$(CONFIG_TOUCHSCREEN_AD7879)	+= ad7879.o
diff --git a/drivers/input/touchscreen/da9052_tsi.c b/drivers/input/touchscreen/da9052_tsi.c
new file mode 100644
index 00000000000..fa250ab1bf9
--- /dev/null
+++ b/drivers/input/touchscreen/da9052_tsi.c
@@ -0,0 +1,1446 @@
+/*
+ * da9052_tsi.c  --  TSI driver for Dialog DA9052
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * Author: Dialog Semiconductor Ltd <dchen@diasemi.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+#include <linux/module.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/freezer.h>
+#include <linux/kthread.h>
+
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/tsi_cfg.h>
+#include <linux/mfd/da9052/tsi.h>
+#include <linux/mfd/da9052/gpio.h>
+#include <linux/mfd/da9052/adc.h>
+
+#define WAIT_FOR_PEN_DOWN	0
+#define WAIT_FOR_SAMPLING	1
+#define SAMPLING_ACTIVE		2
+
+static ssize_t __init da9052_tsi_create_input_dev(struct input_dev **ip_dev,
+					u8 n);
+static ssize_t read_da9052_reg(struct da9052 *da9052, u8 reg_addr);
+static ssize_t write_da9052_reg(struct da9052 *da9052, u8 reg_addr, u8 data);
+
+static void da9052_tsi_reg_pendwn_event(struct da9052_ts_priv *priv);
+static void da9052_tsi_reg_datardy_event(struct da9052_ts_priv *priv);
+static ssize_t da9052_tsi_config_delay(struct da9052_ts_priv *priv,
+					enum TSI_DELAY delay);
+static ssize_t da9052_tsi_config_measure_seq(struct da9052_ts_priv *priv,
+					enum TSI_MEASURE_SEQ seq);
+static ssize_t da9052_tsi_config_state(struct da9052_ts_priv *ts,
+					enum TSI_STATE state);
+static ssize_t da9052_tsi_set_sampling_mode(struct da9052_ts_priv *priv,
+					u8 interval);
+static ssize_t da9052_tsi_config_skip_slots(struct da9052_ts_priv *priv,
+					enum TSI_SLOT_SKIP skip);
+static ssize_t da9052_tsi_config_pen_detect(struct da9052_ts_priv *priv,
+					u8 flag);
+static ssize_t da9052_tsi_disable_irq(struct da9052_ts_priv *priv,
+					enum TSI_IRQ tsi_irq);
+static ssize_t da9052_tsi_enable_irq(struct da9052_ts_priv *priv,
+					enum TSI_IRQ tsi_irq);
+static ssize_t da9052_tsi_config_manual_mode(struct da9052_ts_priv *priv,
+					u8 coordinate);
+static ssize_t da9052_tsi_config_auto_mode(struct da9052_ts_priv *priv,
+					u8 state);
+static ssize_t da9052_tsi_config_gpio(struct da9052_ts_priv *priv);
+static ssize_t da9052_tsi_config_power_supply(struct da9052_ts_priv *priv,
+					u8 state);
+static struct da9052_tsi_info *get_tsi_drvdata(void);
+static void da9052_tsi_penup_event(struct da9052_ts_priv *priv);
+static s32 da9052_tsi_get_rawdata(struct da9052_tsi_reg *buf, u8 cnt);
+static ssize_t da9052_tsi_reg_proc_thread(void *ptr);
+static ssize_t da9052_tsi_resume(struct platform_device *dev);
+static ssize_t da9052_tsi_suspend(struct platform_device *dev,
+					pm_message_t state);
+struct da9052_tsi tsi_reg;
+struct da9052_tsi_info gda9052_tsi_info;
+
+static ssize_t write_da9052_reg(struct da9052 *da9052, u8 reg_addr, u8 data)
+{
+	ssize_t ret = 0;
+	struct da9052_ssc_msg ssc_msg;
+
+	ssc_msg.addr =  reg_addr;
+	ssc_msg.data =  data;
+	ret = da9052->write(da9052, &ssc_msg);
+	if (ret) {
+		DA9052_DEBUG("%s: ", __func__);
+		DA9052_DEBUG("da9052_ssc_write Failed %d\n", ret);
+	}
+
+	return ret;
+}
+
+static ssize_t read_da9052_reg(struct da9052 *da9052, u8 reg_addr)
+{
+	 ssize_t ret = 0;
+	 struct da9052_ssc_msg ssc_msg;
+
+	ssc_msg.addr =  reg_addr;
+	ssc_msg.data =  0;
+	ret = da9052->read(da9052, &ssc_msg);
+	if (ret) {
+		DA9052_DEBUG("%s: ", __func__);
+		DA9052_DEBUG("da9052_ssc_read Failed => %d\n", ret);
+		return -ret;
+	}
+	return ssc_msg.data;
+}
+
+static struct da9052_tsi_info *get_tsi_drvdata(void)
+{
+	return &gda9052_tsi_info;
+}
+
+static ssize_t da9052_tsi_config_measure_seq(struct da9052_ts_priv *priv,
+						enum TSI_MEASURE_SEQ seq)
+{
+	ssize_t ret = 0;
+	u8 data = 0;
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+
+	if (seq > 1)
+		return -EINVAL;
+
+	da9052_lock(priv->da9052);
+	ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG);
+	if (ret < 0) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("read_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+
+	data = (u8)ret;
+
+	if (seq == XYZP_MODE)
+		data = enable_xyzp_mode(data);
+	else if (seq == XP_MODE)
+		data = enable_xp_mode(data);
+	else {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("Invalid Value passed\n");
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+
+	ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG(" write_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+
+	ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data;
+
+	return 0;
+}
+
+static ssize_t da9052_tsi_set_sampling_mode(struct da9052_ts_priv *priv,
+					u8 mode)
+{
+	u8 data = 0;
+	ssize_t ret = 0;
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+
+	da9052_lock(priv->da9052);
+
+	ret = read_da9052_reg(priv->da9052, DA9052_ADCCONT_REG);
+	if (ret < 0) {
+		DA9052_DEBUG("DA9052_TSI:%s:", __func__);
+		DA9052_DEBUG("read_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	data = (u8)ret;
+
+	if (mode == ECONOMY_MODE)
+		data = adc_mode_economy_mode(data);
+	else if (mode == FAST_MODE)
+		data = adc_mode_fast_mode(data);
+	else {
+		DA9052_DEBUG("DA9052_TSI:%s:", __func__);
+		DA9052_DEBUG("Invalid interval passed\n");
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+
+	ret = write_da9052_reg(priv->da9052, DA9052_ADCCONT_REG, data);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI:%s:", __func__);
+		DA9052_DEBUG("write_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+
+	switch (mode) {
+	case ECONOMY_MODE:
+		priv->tsi_reg_data_poll_interval =
+			TSI_ECO_MODE_REG_DATA_PROCESSING_INTERVAL;
+		priv->tsi_raw_data_poll_interval =
+			TSI_ECO_MODE_RAW_DATA_PROCESSING_INTERVAL;
+		break;
+	case FAST_MODE:
+		priv->tsi_reg_data_poll_interval =
+			TSI_FAST_MODE_REG_DATA_PROCESSING_INTERVAL;
+		priv->tsi_raw_data_poll_interval =
+			TSI_FAST_MODE_RAW_DATA_PROCESSING_INTERVAL;
+		break;
+	default:
+		DA9052_DEBUG("DA9052_TSI:%s:", __func__);
+		DA9052_DEBUG("Invalid interval passed\n");
+		return -EINVAL;
+	}
+
+	ts->tsi_penup_count =
+		(u32)priv->tsi_pdata->pen_up_interval /
+		priv->tsi_reg_data_poll_interval;
+
+	return 0;
+}
+
+static ssize_t da9052_tsi_config_delay(struct da9052_ts_priv *priv,
+					enum TSI_DELAY delay)
+{
+	ssize_t ret = 0;
+	u8 data = 0;
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+
+	if (delay > priv->tsi_pdata->max_tsi_delay) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG(" invalid value for tsi delay!!!\n");
+		return -EINVAL;
+	}
+
+	da9052_lock(priv->da9052);
+
+	ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG);
+	if (ret < 0) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("read_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+
+	data = clear_bits((u8)ret, DA9052_TSICONTA_TSIDELAY);
+
+	data = set_bits(data, (delay << priv->tsi_pdata->tsi_delay_bit_shift));
+
+	ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG(" write_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+
+	ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data;
+
+	return 0;
+}
+
+ssize_t da9052_tsi_config_skip_slots(struct da9052_ts_priv *priv,
+					enum TSI_SLOT_SKIP skip)
+{
+	ssize_t ret = 0;
+	u8 data = 0;
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+
+	if (skip > priv->tsi_pdata->max_tsi_skip_slot) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG(" invalid value for tsi skip slots!!!\n");
+		return -EINVAL;
+	}
+
+	da9052_lock(priv->da9052);
+
+	ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG);
+	if (ret < 0) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("read_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+
+	data = clear_bits((u8)ret, DA9052_TSICONTA_TSISKIP);
+
+	data = set_bits(data, (skip << priv->tsi_pdata->tsi_skip_bit_shift));
+
+	ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI:da9052_tsi_config_skip_slots:");
+		DA9052_DEBUG(" write_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+
+	ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data;
+
+	return 0;
+}
+
+static ssize_t da9052_tsi_config_state(struct da9052_ts_priv *priv,
+					enum TSI_STATE state)
+{
+	s32 ret;
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+
+	if (ts->tsi_conf.state == state)
+		return 0;
+
+	switch (state) {
+	case TSI_AUTO_MODE:
+		ts->tsi_zero_data_cnt = 0;
+		priv->early_data_flag = TRUE;
+		priv->debounce_over = FALSE;
+		priv->win_reference_valid = FALSE;
+
+		clean_tsi_fifos(priv);
+
+		ret = da9052_tsi_config_auto_mode(priv, DISABLE);
+		if (ret)
+			return ret;
+
+		ret = da9052_tsi_config_manual_mode(priv, DISABLE);
+		if (ret)
+			return ret;
+
+		ret = da9052_tsi_config_power_supply(priv, DISABLE);
+		if (ret)
+			return ret;
+
+		ret = da9052_tsi_enable_irq(priv, TSI_PEN_DWN);
+		if (ret)
+			return ret;
+		ts->tsi_conf.tsi_pendown_irq_mask = RESET;
+
+		ret = da9052_tsi_disable_irq(priv, TSI_DATA_RDY);
+		if (ret)
+			return ret;
+		ts->tsi_conf.tsi_ready_irq_mask	  = SET;
+
+		da9052_tsi_reg_pendwn_event(priv);
+		da9052_tsi_reg_datardy_event(priv);
+
+		ret = da9052_tsi_config_pen_detect(priv, ENABLE);
+		if (ret)
+			return ret;
+		break;
+
+	case TSI_IDLE:
+		ts->pen_dwn_event = RESET;
+
+		ret = da9052_tsi_config_pen_detect(priv, DISABLE);
+		if (ret)
+			return ret;
+
+		ret = da9052_tsi_config_auto_mode(priv, DISABLE);
+		if (ret)
+			return ret;
+
+		ret = da9052_tsi_config_manual_mode(priv, DISABLE);
+		if (ret)
+			return ret;
+
+		ret = da9052_tsi_config_power_supply(priv, DISABLE);
+		if (ret)
+			return ret;
+
+		if (ts->pd_reg_status) {
+			priv->da9052->unregister_event_notifier(priv->da9052,
+								&priv->pd_nb);
+		ts->pd_reg_status = RESET;
+		}
+		break;
+
+	default:
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG(" Invalid state passed");
+		return -EINVAL;
+	}
+
+	ts->tsi_conf.state = state;
+
+	return 0;
+}
+
+static void da9052_tsi_reg_pendwn_event(struct da9052_ts_priv *priv)
+{
+	ssize_t ret = 0;
+	struct da9052_tsi_info  *ts = get_tsi_drvdata();
+
+	if (ts->pd_reg_status) {
+		DA9052_DEBUG("%s: Pen down ", __func__);
+		DA9052_DEBUG("Registeration is already done\n");
+		return;
+	}
+
+	priv->pd_nb.eve_type = PEN_DOWN_EVE;
+	priv->pd_nb.call_back = &da9052_tsi_pen_down_handler;
+
+	ret = priv->da9052->register_event_notifier(priv->da9052, &priv->pd_nb);
+	if (ret) {
+		DA9052_DEBUG("%s: EH Registeration", __func__);
+		DA9052_DEBUG(" Failed: ret = %d\n", ret);
+		ts->pd_reg_status = RESET;
+	} else
+		ts->pd_reg_status = SET;
+
+	priv->os_data_cnt = 0;
+	priv->raw_data_cnt = 0;
+
+	return;
+}
+
+static void da9052_tsi_reg_datardy_event(struct da9052_ts_priv *priv)
+{
+	ssize_t ret = 0;
+	struct da9052_tsi_info  *ts = get_tsi_drvdata();
+
+	if (ts->datardy_reg_status) {
+		DA9052_DEBUG("%s: Data Ready ", __func__);
+		DA9052_DEBUG("Registeration is already done\n");
+		return;
+	}
+
+	priv->datardy_nb.eve_type = TSI_READY_EVE;
+	priv->datardy_nb.call_back = &da9052_tsi_data_ready_handler;
+
+	ret = priv->da9052->register_event_notifier(priv->da9052,
+						&priv->datardy_nb);
+
+	if (ret) {
+		DA9052_DEBUG("%s: EH Registeration", __func__);
+		DA9052_DEBUG(" Failed: ret = %d\n", ret);
+		ts->datardy_reg_status = RESET;
+	} else
+		ts->datardy_reg_status = SET;
+
+	return;
+}
+
+static ssize_t __init da9052_tsi_create_input_dev(struct input_dev **ip_dev,
+							u8 n)
+{
+	u8 i;
+	s32 ret;
+	struct input_dev *dev = NULL;
+
+	if (!n)
+		return -EINVAL;
+
+	for (i = 0; i < n; i++) {
+		dev = input_allocate_device();
+		if (!dev) {
+			DA9052_DEBUG(KERN_ERR "%s:%s():memory allocation for "\
+					"inputdevice failed\n", __FILE__,
+								__func__);
+			return -ENOMEM;
+		}
+
+		ip_dev[i] = dev;
+		switch (i) {
+		case TSI_INPUT_DEVICE_OFF:
+			dev->name = DA9052_TSI_INPUT_DEV;
+			dev->phys = "input(tsi)";
+			break;
+		default:
+			break;
+		}
+	}
+	dev->id.vendor = DA9052_VENDOR_ID;
+	dev->id.product = DA9052_PRODUCT_ID;
+	dev->id.bustype = BUS_RS232;
+	dev->id.version = TSI_VERSION;
+	dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
+	dev->evbit[0] = (BIT_MASK(EV_SYN) |
+			BIT_MASK(EV_KEY) |
+			BIT_MASK(EV_ABS));
+
+	input_set_abs_params(dev, ABS_X, 0, DA9052_DISPLAY_X_MAX, 0, 0);
+	input_set_abs_params(dev, ABS_Y, 0, DA9052_DISPLAY_Y_MAX, 0, 0);
+	input_set_abs_params(dev, ABS_PRESSURE, 0, DA9052_TOUCH_PRESSURE_MAX,
+				0, 0);
+
+	ret = input_register_device(dev);
+	if (ret) {
+		DA9052_DEBUG(KERN_ERR "%s: Could ", __func__);
+		DA9052_DEBUG("not register input device(touchscreen)!\n");
+		ret = -EIO;
+		goto fail;
+	}
+	return 0;
+
+fail:
+	for (; i-- != 0; )
+		input_free_device(ip_dev[i]);
+	return -EINVAL;
+}
+
+static ssize_t __init da9052_tsi_init_drv(struct da9052_ts_priv *priv)
+{
+	u8 cnt = 0;
+	ssize_t ret = 0;
+	struct da9052_tsi_info  *ts = get_tsi_drvdata();
+
+	if ((DA9052_GPIO_PIN_3 != DA9052_GPIO_CONFIG_TSI) ||
+		(DA9052_GPIO_PIN_4 != DA9052_GPIO_CONFIG_TSI) ||
+		(DA9052_GPIO_PIN_5 != DA9052_GPIO_CONFIG_TSI) ||
+		(DA9052_GPIO_PIN_6 != DA9052_GPIO_CONFIG_TSI) ||
+		(DA9052_GPIO_PIN_7 != DA9052_GPIO_CONFIG_TSI)) {
+		printk(KERN_ERR"DA9052_TSI: Configure DA9052 GPIO ");
+		printk(KERN_ERR"pins for TSI\n");
+		return -EINVAL;
+	}
+
+	ret = da9052_tsi_config_gpio(priv);
+
+	ret = da9052_tsi_config_state(priv, TSI_IDLE);
+	ts->tsi_conf.state = TSI_IDLE;
+
+	da9052_tsi_config_measure_seq(priv, TSI_MODE_VALUE);
+
+	da9052_tsi_config_skip_slots(priv, TSI_SLOT_SKIP_VALUE);
+
+	da9052_tsi_config_delay(priv, TSI_DELAY_VALUE);
+
+	da9052_tsi_set_sampling_mode(priv, DEFAULT_TSI_SAMPLING_MODE);
+
+	ts->tsi_calib = get_calib_config();
+
+	ret = da9052_tsi_create_input_dev(ts->input_devs, NUM_INPUT_DEVS);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI: %s: ", __func__);
+		DA9052_DEBUG("da9052_tsi_create_input_dev Failed\n");
+		return ret;
+	}
+
+	da9052_init_tsi_fifos(priv);
+
+	init_completion(&priv->tsi_reg_proc_thread.notifier);
+	priv->tsi_reg_proc_thread.state = ACTIVE;
+	priv->tsi_reg_proc_thread.thread_task =
+		kthread_run(da9052_tsi_reg_proc_thread,
+			    priv, "da9052_tsi_reg");
+
+	init_completion(&priv->tsi_raw_proc_thread.notifier);
+	priv->tsi_raw_proc_thread.state = ACTIVE;
+	priv->tsi_raw_proc_thread.thread_task =
+		kthread_run(da9052_tsi_raw_proc_thread,
+			    priv, "da9052_tsi_raw");
+
+	ret = da9052_tsi_config_state(priv, DEFAULT_TSI_STATE);
+	if (ret) {
+		for (cnt = 0; cnt < NUM_INPUT_DEVS; cnt++) {
+			if (ts->input_devs[cnt] != NULL)
+				input_free_device(ts->input_devs[cnt]);
+		}
+	}
+
+	return 0;
+}
+
+u32 da9052_tsi_get_input_dev(u8 off)
+{
+	struct da9052_tsi_info   *ts = get_tsi_drvdata();
+
+	if (off > NUM_INPUT_DEVS-1)
+		return -EINVAL;
+
+	return (u32)ts->input_devs[off];
+}
+
+static ssize_t da9052_tsi_config_pen_detect(struct da9052_ts_priv *priv,
+						u8 flag)
+{
+	u8 data;
+	u32 ret;
+	struct da9052_tsi_info  *ts = get_tsi_drvdata();
+
+	da9052_lock(priv->da9052);
+	ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG);
+	if (ret < 0) {
+		DA9052_DEBUG("%s:", __func__);
+		DA9052_DEBUG(" read_da9052_reg	Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+
+	if (flag == ENABLE)
+		data = set_bits((u8)ret, DA9052_TSICONTA_PENDETEN);
+	else if (flag == DISABLE)
+		data = clear_bits((u8)ret, DA9052_TSICONTA_PENDETEN);
+	else {
+		DA9052_DEBUG("%s:", __func__);
+		DA9052_DEBUG(" Invalid flag passed\n");
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+
+	ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data);
+	if (ret < 0) {
+		DA9052_DEBUG("%s:", __func__);
+		DA9052_DEBUG(" write_da9052_reg	Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+
+	ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data;
+	return 0;
+}
+
+static ssize_t da9052_tsi_disable_irq(struct da9052_ts_priv *priv,
+					enum TSI_IRQ tsi_irq)
+{
+	u8 data = 0;
+	ssize_t ret = 0;
+	struct da9052_tsi_info	*ts = get_tsi_drvdata();
+
+	da9052_lock(priv->da9052);
+	ret = read_da9052_reg(priv->da9052, DA9052_IRQMASKB_REG);
+	if (ret < 0)	{
+		DA9052_DEBUG("DA9052_TSI:da9052_tsi_disable_irq:");
+		DA9052_DEBUG("read_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	data = ret;
+	switch (tsi_irq) {
+	case TSI_PEN_DWN:
+		data = mask_pendwn_irq(data);
+	break;
+	case TSI_DATA_RDY:
+		data = mask_tsi_rdy_irq(data);
+	break;
+	default:
+		DA9052_DEBUG("DA9052_TSI:da9052_tsi_disable_irq:");
+		DA9052_DEBUG("Invalid IRQ passed\n");
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+	ret = write_da9052_reg(priv->da9052, DA9052_IRQMASKB_REG, data);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI:da9052_tsi_disable_irq:");
+		DA9052_DEBUG("write_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+	switch (tsi_irq) {
+	case TSI_PEN_DWN:
+		ts->tsi_conf.tsi_pendown_irq_mask = SET;
+	break;
+	case TSI_DATA_RDY:
+		ts->tsi_conf.tsi_ready_irq_mask = SET;
+	break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+
+}
+
+static ssize_t da9052_tsi_enable_irq(struct da9052_ts_priv *priv,
+					enum TSI_IRQ tsi_irq)
+{
+	u8 data = 0;
+	ssize_t ret = 0;
+	struct da9052_tsi_info  *ts = get_tsi_drvdata();
+
+	da9052_lock(priv->da9052);
+	ret = read_da9052_reg(priv->da9052, DA9052_IRQMASKB_REG);
+	if (ret < 0) {
+		DA9052_DEBUG("DA9052_TSI:da9052_tsi_enable_irq:");
+		DA9052_DEBUG("read_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+
+	data = ret;
+	switch (tsi_irq) {
+	case TSI_PEN_DWN:
+		data = unmask_pendwn_irq(data);
+	break;
+	case TSI_DATA_RDY:
+		data = unmask_tsi_rdy_irq(data);
+	break;
+	default:
+		DA9052_DEBUG("DA9052_TSI:da9052_tsi_enable_irq:");
+		DA9052_DEBUG("Invalid IRQ passed\n");
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+	ret = write_da9052_reg(priv->da9052, DA9052_IRQMASKB_REG, data);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI:da9052_tsi_enable_irq:");
+		DA9052_DEBUG("write_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+	switch (tsi_irq) {
+	case TSI_PEN_DWN:
+		ts->tsi_conf.tsi_pendown_irq_mask = RESET;
+	break;
+	case TSI_DATA_RDY:
+		ts->tsi_conf.tsi_ready_irq_mask = RESET;
+	break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static ssize_t da9052_tsi_config_gpio(struct da9052_ts_priv *priv)
+{
+	u8 idx = 0;
+	ssize_t ret = 0;
+	struct da9052_ssc_msg ssc_msg[priv->tsi_pdata->num_gpio_tsi_register];
+
+	ssc_msg[idx++].addr  = DA9052_GPIO0203_REG;
+	ssc_msg[idx++].addr  = DA9052_GPIO0405_REG;
+	ssc_msg[idx++].addr  = DA9052_GPIO0607_REG;
+
+	da9052_lock(priv->da9052);
+	ret = priv->da9052->read_many(priv->da9052, ssc_msg, idx);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("da9052_ssc_read_many Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+
+	idx = 0;
+	ssc_msg[idx].data = clear_bits(ssc_msg[idx].data,
+						DA9052_GPIO0203_GPIO3PIN);
+	idx++;
+	ssc_msg[idx].data = clear_bits(ssc_msg[idx].data,
+		(DA9052_GPIO0405_GPIO4PIN | DA9052_GPIO0405_GPIO5PIN));
+	idx++;
+	ssc_msg[idx].data = clear_bits(ssc_msg[idx].data,
+		(DA9052_GPIO0607_GPIO6PIN | DA9052_GPIO0607_GPIO7PIN));
+	idx++;
+
+	ret = priv->da9052->write_many(priv->da9052, ssc_msg, idx);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("da9052_ssc_read_many Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+
+	return 0;
+}
+
+s32 da9052_pm_configure_ldo(struct da9052_ts_priv *priv,
+				struct da9052_ldo_config ldo_config)
+{
+	struct da9052_ssc_msg msg;
+	u8 reg_num;
+	u8 ldo_volt;
+	u8 ldo_volt_bit = 0;
+	u8 ldo_conf_bit = 0;
+	u8 ldo_en_bit = 0;
+	s8 ldo_pd_bit = -1;
+	s32 ret = 0;
+
+	if (validate_ldo9_mV(ldo_config.ldo_volt))
+		return INVALID_LDO9_VOLT_VALUE;
+
+	ldo_volt = ldo9_mV_to_reg(ldo_config.ldo_volt);
+
+	reg_num = DA9052_LDO9_REG;
+	ldo_volt_bit = DA9052_LDO9_VLDO9;
+	ldo_conf_bit = DA9052_LDO9_LDO9CONF;
+	ldo_en_bit = DA9052_LDO9_LDO9EN;
+
+	da9052_lock(priv->da9052);
+
+	msg.addr = reg_num;
+
+	ret = priv->da9052->read(priv->da9052, &msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+	msg.data = ldo_volt |
+		(ldo_config.ldo_conf ? ldo_conf_bit : 0) |
+		(msg.data & ldo_en_bit);
+
+	ret = priv->da9052->write(priv->da9052, &msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+
+	if (-1 != ldo_pd_bit) {
+		msg.addr = DA9052_PULLDOWN_REG;
+		ret = priv->da9052->read(priv->da9052, &msg);
+		if (ret) {
+			da9052_unlock(priv->da9052);
+			return -EINVAL;
+		}
+
+		msg.data = (ldo_config.ldo_pd ?
+				set_bits(msg.data, ldo_pd_bit) :
+				clear_bits(msg.data, ldo_pd_bit));
+
+		ret = priv->da9052->write(priv->da9052, &msg);
+		if (ret) {
+			da9052_unlock(priv->da9052);
+			return -EINVAL;
+		}
+
+	}
+	da9052_unlock(priv->da9052);
+
+	return 0;
+}
+
+
+s32 da9052_pm_set_ldo(struct da9052_ts_priv *priv, u8 ldo_num, u8 flag)
+{
+	struct da9052_ssc_msg msg;
+	u8 reg_num = 0;
+	u8 value = 0;
+	s32 ret = 0;
+
+	DA9052_DEBUG("I am in function: %s\n", __func__);
+
+	reg_num = DA9052_LDO9_REG;
+	value =	DA9052_LDO9_LDO9EN;
+	da9052_lock(priv->da9052);
+
+	msg.addr = reg_num;
+
+	ret = priv->da9052->read(priv->da9052, &msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+
+	msg.data = flag ?
+		set_bits(msg.data, value) :
+		clear_bits(msg.data, value);
+
+	ret = priv->da9052->write(priv->da9052, &msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+
+	da9052_unlock(priv->da9052);
+
+	return 0;
+}
+
+static ssize_t da9052_tsi_config_power_supply(struct da9052_ts_priv *priv,
+						u8 state)
+{
+	struct da9052_ldo_config ldo_config;
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+
+	if (state != ENABLE && state != DISABLE) {
+		DA9052_DEBUG("DA9052_TSI: %s: ", __func__);
+		DA9052_DEBUG("Invalid state Passed\n");
+		return -EINVAL;
+	}
+
+	ldo_config.ldo_volt = priv->tsi_pdata->tsi_supply_voltage;
+	ldo_config.ldo_num =  priv->tsi_pdata->tsi_ref_source;
+	ldo_config.ldo_conf = RESET;
+
+	if (da9052_pm_configure_ldo(priv, ldo_config))
+		return -EINVAL;
+
+	if (da9052_pm_set_ldo(priv, priv->tsi_pdata->tsi_ref_source, state))
+		return -EINVAL;
+
+	if (state == ENABLE)
+		ts->tsi_conf.ldo9_en = SET;
+	else
+		ts->tsi_conf.ldo9_en = RESET;
+
+	return 0;
+}
+
+static ssize_t da9052_tsi_config_auto_mode(struct da9052_ts_priv *priv,
+						u8 state)
+{
+	u8 data;
+	s32 ret = 0;
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+
+	if (state != ENABLE && state != DISABLE)
+		return -EINVAL;
+
+	da9052_lock(priv->da9052);
+
+	ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG);
+	if (ret < 0) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("read_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+
+	data = (u8)ret;
+
+	if (state == ENABLE)
+		data = set_auto_tsi_en(data);
+	else if (state == DISABLE)
+		data = reset_auto_tsi_en(data);
+	else {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("Invalid Parameter Passed\n");
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+
+	ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG(" Failed to configure Auto TSI mode\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+	ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data;
+	return 0;
+}
+
+static ssize_t da9052_tsi_config_manual_mode(struct da9052_ts_priv *priv,
+						u8 state)
+{
+	u8 data = 0;
+	ssize_t ret = 0;
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+
+	if (state != ENABLE && state != DISABLE) {
+		DA9052_DEBUG("DA9052_TSI: %s: ", __func__);
+		DA9052_DEBUG("Invalid state Passed\n");
+		return -EINVAL;
+	}
+
+	da9052_lock(priv->da9052);
+
+	ret = read_da9052_reg(priv->da9052, DA9052_TSICONTB_REG);
+	if (ret < 0) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("read_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+
+	data = (u8)ret;
+	if (state == DISABLE)
+		data = disable_tsi_manual_mode(data);
+	else
+		data = enable_tsi_manual_mode(data);
+
+	ret = write_da9052_reg(priv->da9052, DA9052_TSICONTB_REG, data);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("write_da9052_reg Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+
+	if (state == DISABLE)
+		ts->tsi_conf.man_cont.tsi_cont_b.tsi_man = RESET;
+	else
+		ts->tsi_conf.man_cont.tsi_cont_b.tsi_man = SET;
+
+	data = 0;
+	data = set_bits(data, DA9052_ADC_TSI);
+
+	ret = write_da9052_reg(priv->da9052, DA9052_ADCMAN_REG, data);
+	if (ret) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG("ADC write Failed\n");
+		da9052_unlock(priv->da9052);
+		return ret;
+	}
+	da9052_unlock(priv->da9052);
+
+	return 0;
+}
+
+static u32 da9052_tsi_get_reg_data(struct da9052_ts_priv *priv)
+{
+	u32 free_cnt, copy_cnt, cnt;
+
+	if (down_interruptible(&priv->tsi_reg_fifo.lock))
+		return 0;
+
+	copy_cnt = 0;
+
+	if ((priv->tsi_reg_fifo.head - priv->tsi_reg_fifo.tail) > 1) {
+		free_cnt = get_reg_free_space_cnt(priv);
+		if (free_cnt > TSI_POLL_SAMPLE_CNT)
+			free_cnt = TSI_POLL_SAMPLE_CNT;
+
+		cnt = da9052_tsi_get_rawdata(
+			&priv->tsi_reg_fifo.data[priv->tsi_reg_fifo.tail],
+			free_cnt);
+
+		if (cnt > free_cnt) {
+			DA9052_DEBUG("EH copied more data");
+			return -EINVAL;
+		}
+
+		copy_cnt = cnt;
+
+		while (cnt--)
+			incr_with_wrap_reg_fifo(priv->tsi_reg_fifo.tail);
+
+	} else if ((priv->tsi_reg_fifo.head - priv->tsi_reg_fifo.tail) <= 0) {
+
+		free_cnt = (TSI_REG_DATA_BUF_SIZE - priv->tsi_reg_fifo.tail);
+		if (free_cnt > TSI_POLL_SAMPLE_CNT) {
+			free_cnt = TSI_POLL_SAMPLE_CNT;
+
+			cnt = da9052_tsi_get_rawdata(
+			&priv->tsi_reg_fifo.data[priv->tsi_reg_fifo.tail],
+			free_cnt);
+			if (cnt > free_cnt) {
+				DA9052_DEBUG("EH copied more data");
+				return -EINVAL;
+			}
+			copy_cnt = cnt;
+
+			while (cnt--)
+				incr_with_wrap_reg_fifo(
+						priv->tsi_reg_fifo.tail);
+		} else {
+			if (free_cnt) {
+				cnt = da9052_tsi_get_rawdata(
+					&priv->
+					tsi_reg_fifo.data[priv->
+					tsi_reg_fifo.tail],
+					free_cnt
+					);
+				if (cnt > free_cnt) {
+					DA9052_DEBUG("EH copied more data");
+					return -EINVAL;
+				}
+				copy_cnt = cnt;
+				while (cnt--)
+					incr_with_wrap_reg_fifo(
+						priv->tsi_reg_fifo.tail);
+			}
+			free_cnt = priv->tsi_reg_fifo.head;
+			if (free_cnt > TSI_POLL_SAMPLE_CNT - copy_cnt)
+				free_cnt = TSI_POLL_SAMPLE_CNT - copy_cnt;
+			if (free_cnt) {
+				cnt = da9052_tsi_get_rawdata(
+					&priv->tsi_reg_fifo.data[priv->
+					tsi_reg_fifo.tail], free_cnt
+					);
+				if (cnt > free_cnt) {
+					DA9052_DEBUG("EH copied more data");
+					return -EINVAL;
+				}
+
+				copy_cnt += cnt;
+
+				while (cnt--)
+					incr_with_wrap_reg_fifo(
+						priv->tsi_reg_fifo.tail);
+			}
+		}
+	} else
+		copy_cnt = 0;
+
+	up(&priv->tsi_reg_fifo.lock);
+
+	return copy_cnt;
+}
+
+
+static ssize_t da9052_tsi_reg_proc_thread(void *ptr)
+{
+	u32 data_cnt;
+	ssize_t ret = 0;
+	struct da9052_tsi_info *ts;
+	struct da9052_ts_priv *priv = (struct da9052_ts_priv *)ptr;
+
+	set_freezable();
+
+	while (priv->tsi_reg_proc_thread.state == ACTIVE) {
+
+		try_to_freeze();
+
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(msecs_to_jiffies(priv->
+					tsi_reg_data_poll_interval));
+
+		ts = get_tsi_drvdata();
+
+		if (!ts->pen_dwn_event)
+			continue;
+
+		data_cnt = da9052_tsi_get_reg_data(priv);
+
+		da9052_tsi_process_reg_data(priv);
+
+		if (data_cnt)
+			ts->tsi_zero_data_cnt = 0;
+		else {
+			if ((++(ts->tsi_zero_data_cnt)) >
+						     ts->tsi_penup_count) {
+				ts->pen_dwn_event = RESET;
+				da9052_tsi_penup_event(priv);
+			}
+		}
+	}
+
+	complete_and_exit(&priv->tsi_reg_proc_thread.notifier, 0);
+	return 0;
+}
+
+
+static void da9052_tsi_penup_event(struct da9052_ts_priv *priv)
+{
+
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+	struct input_dev *ip_dev =
+		(struct input_dev *)da9052_tsi_get_input_dev(
+		(u8)TSI_INPUT_DEVICE_OFF);
+
+	if (da9052_tsi_config_auto_mode(priv, DISABLE))
+		goto exit;
+	ts->tsi_conf.auto_cont.tsi_cont_a.auto_tsi_en = RESET;
+
+	if (da9052_tsi_config_power_supply(priv, ENABLE))
+		goto exit;
+
+	ts->tsi_conf.ldo9_en = RESET;
+
+	if (da9052_tsi_enable_irq(priv, TSI_PEN_DWN))
+		goto exit;
+	ts->tsi_conf.tsi_pendown_irq_mask = RESET;
+	tsi_reg.tsi_state =  WAIT_FOR_PEN_DOWN;
+
+	if (da9052_tsi_disable_irq(priv, TSI_DATA_RDY))
+		goto exit;
+
+	ts->tsi_zero_data_cnt = 0;
+	priv->early_data_flag = TRUE;
+	priv->debounce_over = FALSE;
+	priv->win_reference_valid = FALSE;
+
+	printk(KERN_INFO "The raw data count is %d\n", priv->raw_data_cnt);
+	printk(KERN_INFO "The OS data count is %d\n", priv->os_data_cnt);
+	printk(KERN_INFO "PEN UP DECLARED\n");
+	input_report_abs(ip_dev, BTN_TOUCH, 0);
+	input_sync(ip_dev);
+	priv->os_data_cnt = 0;
+	priv->raw_data_cnt = 0;
+
+exit:
+	clean_tsi_fifos(priv);
+	return;
+}
+
+void da9052_tsi_pen_down_handler(struct da9052_eh_nb *eh_data, u32 event)
+{
+	ssize_t ret = 0;
+	struct da9052_ts_priv *priv =
+		container_of(eh_data, struct da9052_ts_priv, pd_nb);
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+	struct input_dev *ip_dev =
+		(struct input_dev *)da9052_tsi_get_input_dev(
+		(u8)TSI_INPUT_DEVICE_OFF);
+
+	if (tsi_reg.tsi_state !=  WAIT_FOR_PEN_DOWN)
+		return;
+
+	tsi_reg.tsi_state = WAIT_FOR_SAMPLING;
+
+	if (ts->tsi_conf.state != TSI_AUTO_MODE) {
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG(" Configure TSI to auto mode.\n");
+		DA9052_DEBUG("DA9052_TSI: %s:", __func__);
+		DA9052_DEBUG(" Then call this API.\n");
+		goto fail;
+	}
+
+	if (da9052_tsi_config_power_supply(priv, ENABLE))
+		goto fail;
+
+	if (da9052_tsi_disable_irq(priv, TSI_PEN_DWN))
+		goto fail;
+
+	if (da9052_tsi_config_auto_mode(priv, ENABLE))
+		goto fail;
+	ts->tsi_conf.auto_cont.tsi_cont_a.auto_tsi_en = SET;
+
+	if (da9052_tsi_enable_irq(priv, TSI_DATA_RDY))
+		goto fail;
+
+	input_sync(ip_dev);
+
+	ts->tsi_rdy_event = (DA9052_EVENTB_ETSIREADY & (event>>8));
+	ts->pen_dwn_event = (DA9052_EVENTB_EPENDOWN & (event>>8));
+
+	tsi_reg.tsi_state =  SAMPLING_ACTIVE;
+
+	goto success;
+
+fail:
+	if (ts->pd_reg_status) {
+		priv->da9052->unregister_event_notifier(priv->da9052,
+						&priv->pd_nb);
+		ts->pd_reg_status = RESET;
+
+		priv->da9052->register_event_notifier(priv->da9052,
+					&priv->datardy_nb);
+		da9052_tsi_reg_pendwn_event(priv);
+	}
+
+success:
+	ret = 0;
+	printk(KERN_INFO "Exiting PEN DOWN HANDLER\n");
+}
+
+void da9052_tsi_data_ready_handler(struct da9052_eh_nb *eh_data, u32 event)
+{
+	struct da9052_ssc_msg tsi_data[4];
+	s32 ret;
+	struct da9052_ts_priv *priv =
+		container_of(eh_data, struct da9052_ts_priv, datardy_nb);
+
+	if (tsi_reg.tsi_state !=  SAMPLING_ACTIVE)
+		return;
+
+	tsi_data[0].addr  = DA9052_TSIXMSB_REG;
+	tsi_data[1].addr  = DA9052_TSIYMSB_REG;
+	tsi_data[2].addr  = DA9052_TSILSB_REG;
+	tsi_data[3].addr  = DA9052_TSIZMSB_REG;
+
+	tsi_data[0].data  = 0;
+	tsi_data[1].data  = 0;
+	tsi_data[2].data  = 0;
+	tsi_data[3].data  = 0;
+
+	da9052_lock(priv->da9052);
+
+	ret = priv->da9052->read_many(priv->da9052, tsi_data, 4);
+	if (ret) {
+		DA9052_DEBUG("Error in reading TSI data\n");
+		da9052_unlock(priv->da9052);
+		return;
+	}
+	da9052_unlock(priv->da9052);
+
+#if 1
+	mutex_lock(&tsi_reg.tsi_fifo_lock);
+
+	tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_end].x_msb = tsi_data[0].data;
+	tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_end].y_msb = tsi_data[1].data;
+	tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_end].lsb   = tsi_data[2].data;
+	tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_end].z_msb = tsi_data[3].data;
+	incr_with_wrap(tsi_reg.tsi_fifo_end);
+
+	if (tsi_reg.tsi_fifo_end == tsi_reg.tsi_fifo_start)
+		tsi_reg.tsi_fifo_start++;
+
+	mutex_unlock(&tsi_reg.tsi_fifo_lock);
+#endif
+/*	printk(KERN_INFO "Exiting Data ready handler\n");*/
+}
+
+static s32 da9052_tsi_get_rawdata(struct da9052_tsi_reg *buf, u8 cnt)
+{
+	u32 data_cnt = 0;
+	u32 rem_data_cnt = 0;
+
+	mutex_lock(&tsi_reg.tsi_fifo_lock);
+
+	if (tsi_reg.tsi_fifo_start < tsi_reg.tsi_fifo_end) {
+		data_cnt = (tsi_reg.tsi_fifo_end - tsi_reg.tsi_fifo_start);
+
+		if (cnt < data_cnt)
+			data_cnt = cnt;
+
+		memcpy(buf, &tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_start],
+				sizeof(struct da9052_tsi_reg) * data_cnt);
+
+		tsi_reg.tsi_fifo_start += data_cnt;
+
+		if (tsi_reg.tsi_fifo_start == tsi_reg.tsi_fifo_end) {
+			tsi_reg.tsi_fifo_start = 0;
+			tsi_reg.tsi_fifo_end = 0;
+		}
+	} else if (tsi_reg.tsi_fifo_start > tsi_reg.tsi_fifo_end) {
+		data_cnt = ((TSI_FIFO_SIZE - tsi_reg.tsi_fifo_start)
+		+ tsi_reg.tsi_fifo_end);
+
+		if (cnt < data_cnt)
+			data_cnt = cnt;
+
+		if (data_cnt <= (TSI_FIFO_SIZE - tsi_reg.tsi_fifo_start)) {
+			memcpy(buf, &tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_start],
+				sizeof(struct da9052_tsi_reg) * data_cnt);
+
+			tsi_reg.tsi_fifo_start += data_cnt;
+			if (tsi_reg.tsi_fifo_start >= TSI_FIFO_SIZE)
+				tsi_reg.tsi_fifo_start = 0;
+		} else {
+			memcpy(buf, &tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_start],
+				sizeof(struct da9052_tsi_reg)
+				* (TSI_FIFO_SIZE - tsi_reg.tsi_fifo_start));
+
+			rem_data_cnt = (data_cnt -
+				(TSI_FIFO_SIZE - tsi_reg.tsi_fifo_start));
+
+			memcpy(buf, &tsi_reg.tsi_fifo[0],
+				sizeof(struct da9052_tsi_reg) * rem_data_cnt);
+
+			tsi_reg.tsi_fifo_start = rem_data_cnt;
+		}
+
+		if (tsi_reg.tsi_fifo_start == tsi_reg.tsi_fifo_end) {
+				tsi_reg.tsi_fifo_start = 0;
+			tsi_reg.tsi_fifo_end = 0;
+		}
+	} else
+		data_cnt = 0;
+
+	mutex_unlock(&tsi_reg.tsi_fifo_lock);
+
+	return data_cnt;
+}
+
+static ssize_t da9052_tsi_suspend(struct platform_device *dev,
+							pm_message_t state)
+{
+	printk(KERN_INFO "%s: called\n", __func__);
+	return 0;
+}
+
+static ssize_t da9052_tsi_resume(struct platform_device *dev)
+{
+	printk(KERN_INFO "%s: called\n", __func__);
+	return 0;
+}
+
+static s32 __devinit da9052_tsi_probe(struct platform_device *pdev)
+{
+
+	struct da9052_ts_priv *priv;
+	struct da9052_tsi_platform_data *pdata = pdev->dev.platform_data;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	priv->da9052 = dev_get_drvdata(pdev->dev.parent);
+	platform_set_drvdata(pdev, priv);
+
+	priv->tsi_pdata = pdata;
+
+	if (da9052_tsi_init_drv(priv))
+			return -EFAULT;
+
+	mutex_init(&tsi_reg.tsi_fifo_lock);
+	tsi_reg.tsi_state = WAIT_FOR_PEN_DOWN;
+
+	printk(KERN_INFO "TSI Drv Successfully Inserted %s\n",
+					DA9052_TSI_DEVICE_NAME);
+	return 0;
+}
+
+static int __devexit da9052_tsi_remove(struct platform_device *pdev)
+{
+	struct da9052_ts_priv *priv = platform_get_drvdata(pdev);
+	struct da9052_tsi_info *ts = get_tsi_drvdata();
+	s32 ret = 0, i = 0;
+
+	ret = da9052_tsi_config_state(priv, TSI_IDLE);
+	if (!ret)
+		return -EINVAL;
+
+	if (ts->pd_reg_status) {
+		priv->da9052->unregister_event_notifier(priv->da9052,
+							&priv->pd_nb);
+		ts->pd_reg_status = RESET;
+	}
+
+	if (ts->datardy_reg_status) {
+		priv->da9052->unregister_event_notifier(priv->da9052,
+							&priv->datardy_nb);
+		ts->datardy_reg_status = RESET;
+	}
+
+	mutex_destroy(&tsi_reg.tsi_fifo_lock);
+
+	priv->tsi_reg_proc_thread.state = INACTIVE;
+	wait_for_completion(&priv->tsi_reg_proc_thread.notifier);
+
+	priv->tsi_raw_proc_thread.state = INACTIVE;
+	wait_for_completion(&priv->tsi_raw_proc_thread.notifier);
+
+	for (i = 0; i < NUM_INPUT_DEVS; i++)
+		input_unregister_device(ts->input_devs[i]);
+
+	platform_set_drvdata(pdev, NULL);
+	DA9052_DEBUG(KERN_DEBUG "Removing %s\n", DA9052_TSI_DEVICE_NAME);
+
+	return 0;
+}
+
+static struct platform_driver da9052_tsi_driver = {
+	.probe		= da9052_tsi_probe,
+	.remove		= __devexit_p(da9052_tsi_remove),
+	.suspend	= da9052_tsi_suspend,
+	.resume		= da9052_tsi_resume,
+	.driver		= {
+				.name	= DA9052_TSI_DEVICE_NAME,
+				.owner	= THIS_MODULE,
+			},
+};
+
+static int __init da9052_tsi_init(void)
+{
+	printk(KERN_DEBUG "DA9052 TSI Device Driver, v1.0\n");
+	return platform_driver_register(&da9052_tsi_driver);
+}
+module_init(da9052_tsi_init);
+
+static void __exit da9052_tsi_exit(void)
+{
+	printk(KERN_ERR "TSI Driver %s Successfully Removed\n",
+					DA9052_TSI_DEVICE_NAME);
+	return;
+
+}
+module_exit(da9052_tsi_exit);
+
+MODULE_DESCRIPTION("Touchscreen driver for Dialog Semiconductor DA9052");
+MODULE_AUTHOR("Dialog Semiconductor Ltd <dchen@diasemi.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/input/touchscreen/da9052_tsi_calibrate.c b/drivers/input/touchscreen/da9052_tsi_calibrate.c
new file mode 100644
index 00000000000..6208462c584
--- /dev/null
+++ b/drivers/input/touchscreen/da9052_tsi_calibrate.c
@@ -0,0 +1,107 @@
+/*
+ * da9052_tsi_calibrate.c  --  TSI Calibration driver for Dialog DA9052
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * Author: Dialog Semiconductor Ltd <dchen@diasemi.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/mfd/da9052/tsi.h>
+
+static struct Calib_xform_matrix_t xform = {
+		.An = DA9052_TSI_CALIB_AN,
+		.Bn = DA9052_TSI_CALIB_BN,
+		.Cn = DA9052_TSI_CALIB_CN,
+		.Dn = DA9052_TSI_CALIB_DN,
+		.En = DA9052_TSI_CALIB_EN,
+		.Fn = DA9052_TSI_CALIB_FN,
+		.Divider = DA9052_TSI_CALIB_DIVIDER
+};
+
+static struct calib_cfg_t calib = {
+	.calibrate_flag = TSI_USE_CALIBRATION,
+};
+
+struct calib_cfg_t *get_calib_config(void)
+{
+	return &calib;
+}
+
+ssize_t da9052_tsi_set_calib_matrix(struct da9052_tsi_data *displayPtr,
+				struct da9052_tsi_data *screenPtr)
+{
+
+	int  retValue = SUCCESS ;
+
+	xform.Divider = ((screenPtr[0].x - screenPtr[1].x)
+			* (screenPtr[1].y - screenPtr[2].y))
+			- ((screenPtr[1].x - screenPtr[2].x)
+			* (screenPtr[0].y - screenPtr[1].y));
+
+	if (xform.Divider == 0)
+		retValue = -FAILURE;
+	else	{
+		xform.An = ((displayPtr[0].x - displayPtr[1].x)
+			* (screenPtr[1].y - screenPtr[2].y))
+			- ((displayPtr[1].x - displayPtr[2].x)
+			* (screenPtr[0].y - screenPtr[1].y));
+
+		xform.Bn = ((displayPtr[1].x - displayPtr[2].x)
+			* (screenPtr[0].x - screenPtr[1].x))
+			- ((screenPtr[1].x - screenPtr[2].x)
+			* (displayPtr[0].x - displayPtr[1].x));
+
+		 xform.Cn = (displayPtr[0].x * xform.Divider)
+			- (screenPtr[0].x * xform.An)
+			- (screenPtr[0].y * xform.Bn);
+
+		xform.Dn = ((displayPtr[0].y - displayPtr[1].y)
+			* (screenPtr[1].y - screenPtr[2].y))
+			- ((displayPtr[1].y - displayPtr[2].y)
+			* (screenPtr[0].y - screenPtr[1].y));
+
+		xform.En = ((displayPtr[1].y - displayPtr[2].y)
+			* (screenPtr[0].x - screenPtr[1].x))
+			- ((screenPtr[1].x - screenPtr[2].x)
+			* (displayPtr[0].y - displayPtr[1].y));
+
+		xform.Fn = (displayPtr[0].y * xform.Divider)
+			- (screenPtr[0].x * xform.Dn)
+			- (screenPtr[0].y * xform.En);
+	}
+
+	return retValue;
+}
+
+ssize_t da9052_tsi_get_calib_display_point(struct da9052_tsi_data *displayPtr)
+{
+	int  retValue = TRUE;
+	struct da9052_tsi_data screen_coord;
+
+	screen_coord = *displayPtr;
+	if (xform.Divider != 0)	{
+		displayPtr->x = ((xform.An * screen_coord.x) +
+			(xform.Bn * screen_coord.y) +
+				xform.Cn
+			) / xform.Divider;
+
+	displayPtr->y = ((xform.Dn * screen_coord.x) +
+			(xform.En * screen_coord.y) +
+				xform.Fn
+			) / xform.Divider;
+	} else
+		retValue = FALSE;
+
+#if DA9052_TSI_CALIB_DATA_PROFILING
+	printk(KERN_DEBUG "C\tX\t%4d\tY\t%4d\n",
+					displayPtr->x,
+					displayPtr->y);
+#endif
+	return retValue;
+}
diff --git a/drivers/input/touchscreen/da9052_tsi_filter.c b/drivers/input/touchscreen/da9052_tsi_filter.c
new file mode 100644
index 00000000000..c29dd016c34
--- /dev/null
+++ b/drivers/input/touchscreen/da9052_tsi_filter.c
@@ -0,0 +1,489 @@
+/*
+ * da9052_tsi_filter.c  --  TSI filter driver for Dialog DA9052
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * Author: Dialog Semiconductor Ltd <dchen@diasemi.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/input.h>
+#include <linux/freezer.h>
+#include <linux/mfd/da9052/tsi.h>
+
+#define get_abs(x)	(x < 0 ? ((-1) * x) : (x))
+
+#define WITHIN_WINDOW(x, y)	((get_abs(x) <= TSI_X_WINDOW_SIZE) && \
+				(get_abs(y) <= TSI_Y_WINDOW_SIZE))
+
+#define FIRST_SAMPLE					0
+
+#define incr_with_wrap_raw_fifo(x)			\
+		if (++x >= TSI_RAW_DATA_BUF_SIZE)	\
+			x = 0
+
+#define decr_with_wrap_raw_fifo(x)			\
+		if (--x < 0)				\
+			x = (TSI_RAW_DATA_BUF_SIZE-1)
+
+static u32 get_raw_data_cnt(struct da9052_ts_priv *priv);
+static void da9052_tsi_convert_reg_to_coord(struct da9052_ts_priv *priv,
+					struct da9052_tsi_data *raw_data);
+static inline void clean_tsi_reg_fifo(struct da9052_ts_priv *priv);
+static inline void clean_tsi_raw_fifo(struct da9052_ts_priv *priv);
+
+#if (ENABLE_AVERAGE_FILTER)
+static void da9052_tsi_avrg_filter(struct da9052_ts_priv *priv,
+					struct da9052_tsi_data *tsi_avg_data);
+
+#endif
+#if (ENABLE_TSI_DEBOUNCE)
+static s32 da9052_tsi_calc_debounce_data(struct da9052_ts_priv *priv,
+					struct da9052_tsi_data *raw_data);
+
+#endif
+# if (ENABLE_WINDOW_FILTER)
+static s32 diff_within_window(struct da9052_tsi_data *prev_raw_data,
+			      struct da9052_tsi_data *cur_raw_data);
+#endif
+static s32 da9052_tsi_window_filter(struct da9052_ts_priv *ts,
+					struct da9052_tsi_data *raw_data);
+
+void clean_tsi_fifos(struct da9052_ts_priv *priv)
+{
+	clean_tsi_raw_fifo(priv);
+	clean_tsi_reg_fifo(priv);
+}
+
+void __init da9052_init_tsi_fifos(struct da9052_ts_priv *priv)
+{
+	sema_init(&priv->tsi_raw_fifo.lock, 1);
+	sema_init(&priv->tsi_reg_fifo.lock, 1);
+
+	clean_tsi_raw_fifo(priv);
+	clean_tsi_reg_fifo(priv);
+}
+
+u32 get_reg_data_cnt(struct da9052_ts_priv *priv)
+{
+	u8 reg_data_cnt;
+
+	if (priv->tsi_reg_fifo.head <= priv->tsi_reg_fifo.tail) {
+		reg_data_cnt = (priv->tsi_reg_fifo.tail -
+				priv->tsi_reg_fifo.head);
+	} else {
+		reg_data_cnt = (priv->tsi_reg_fifo.tail +
+				(TSI_REG_DATA_BUF_SIZE -
+				priv->tsi_reg_fifo.head));
+	}
+
+	return reg_data_cnt;
+}
+
+u32 get_reg_free_space_cnt(struct da9052_ts_priv *priv)
+{
+	u32 free_cnt;
+
+	if (priv->tsi_reg_fifo.head <= priv->tsi_reg_fifo.tail) {
+		free_cnt = ((TSI_REG_DATA_BUF_SIZE - 1) -
+			(priv->tsi_reg_fifo.tail - priv->tsi_reg_fifo.head));
+	} else
+		free_cnt = ((priv->tsi_reg_fifo.head - priv->tsi_reg_fifo.tail)
+				- 1);
+
+	return free_cnt;
+}
+
+void da9052_tsi_process_reg_data(struct da9052_ts_priv *priv)
+{
+	s32 ret;
+	struct da9052_tsi_data tmp_raw_data;
+	u32 reg_data_cnt;
+
+	if (down_interruptible(&priv->tsi_reg_fifo.lock))
+		return;
+
+	reg_data_cnt = get_reg_data_cnt(priv);
+
+	while (reg_data_cnt-- > 0) {
+
+		ret = 0;
+
+		if (get_raw_data_cnt(priv) >= (TSI_RAW_DATA_BUF_SIZE - 1)) {
+			DA9052_DEBUG("%s: RAW data FIFO is full\n",
+							__func__);
+			break;
+		}
+
+		da9052_tsi_convert_reg_to_coord(priv, &tmp_raw_data);
+
+		if ((tmp_raw_data.x < TS_X_MIN) ||
+			(tmp_raw_data.x > TS_X_MAX) ||
+			(tmp_raw_data.y < TS_Y_MIN) ||
+			(tmp_raw_data.y > TS_Y_MAX)) {
+			DA9052_DEBUG("%s: ", __func__);
+			DA9052_DEBUG("sample beyond touchscreen panel ");
+			DA9052_DEBUG("dimensions\n");
+			continue;
+		}
+
+#if (ENABLE_TSI_DEBOUNCE)
+		if (debounce_over == FALSE) {
+			ret =
+			da9052_tsi_calc_debounce_data(priv, &tmp_raw_data);
+			if (ret != SUCCESS)
+				continue;
+		}
+#endif
+
+# if (ENABLE_WINDOW_FILTER)
+		ret = da9052_tsi_window_filter(priv, &tmp_raw_data);
+		if (ret != SUCCESS)
+			continue;
+#endif
+		priv->early_data_flag = FALSE;
+
+		if (down_interruptible(&priv->tsi_raw_fifo.lock)) {
+			DA9052_DEBUG("%s: Failed to ", __func__);
+			DA9052_DEBUG("acquire RAW FIFO Lock!\n");
+
+			up(&priv->tsi_reg_fifo.lock);
+			return;
+		}
+
+		priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.tail] = tmp_raw_data;
+		incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.tail);
+
+		up(&priv->tsi_raw_fifo.lock);
+	}
+
+
+	up(&priv->tsi_reg_fifo.lock);
+
+	return;
+}
+
+static u32 get_raw_data_cnt(struct da9052_ts_priv *priv)
+{
+	u32 raw_data_cnt;
+
+	if (priv->tsi_raw_fifo.head <= priv->tsi_raw_fifo.tail)
+		raw_data_cnt =
+			(priv->tsi_raw_fifo.tail - priv->tsi_raw_fifo.head);
+	else
+		raw_data_cnt =
+			(priv->tsi_raw_fifo.tail + (TSI_RAW_DATA_BUF_SIZE -
+			priv->tsi_raw_fifo.head));
+
+	return raw_data_cnt;
+}
+
+static void da9052_tsi_convert_reg_to_coord(struct da9052_ts_priv *priv,
+					struct da9052_tsi_data *raw_data)
+{
+
+	struct da9052_tsi_reg *src;
+	struct da9052_tsi_data *dst = raw_data;
+
+	src = &priv->tsi_reg_fifo.data[priv->tsi_reg_fifo.head];
+
+	dst->x = (src->x_msb << X_MSB_SHIFT);
+	dst->x |= (src->lsb & X_LSB_MASK) >> X_LSB_SHIFT;
+
+	dst->y = (src->y_msb << Y_MSB_SHIFT);
+	dst->y |= (src->lsb & Y_LSB_MASK) >> Y_LSB_SHIFT;
+
+	dst->z = (src->z_msb << Z_MSB_SHIFT);
+	dst->z |= (src->lsb & Z_LSB_MASK) >> Z_LSB_SHIFT;
+
+#if DA9052_TSI_RAW_DATA_PROFILING
+	printk(KERN_DEBUG "R\tX\t%4d\tY\t%4d\tZ\t%4d\n",
+					(u16)dst->x,
+					(u16)dst->y,
+					(u16)dst->z);
+#endif
+	priv->raw_data_cnt++;
+	incr_with_wrap_reg_fifo(priv->tsi_reg_fifo.head);
+}
+
+#if (ENABLE_AVERAGE_FILTER)
+static void da9052_tsi_avrg_filter(struct da9052_ts_priv *priv,
+					struct da9052_tsi_data *tsi_avg_data)
+{
+	u8 cnt;
+
+	if (down_interruptible(&priv->tsi_raw_fifo.lock)) {
+		printk(KERN_DEBUG "%s: No RAW Lock !\n", __func__);
+		return;
+	}
+
+	(*tsi_avg_data) = priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head];
+	incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.head);
+
+	for (cnt = 2; cnt <= TSI_AVERAGE_FILTER_SIZE; cnt++) {
+
+		tsi_avg_data->x +=
+			priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].x;
+		tsi_avg_data->y +=
+			priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].y;
+		tsi_avg_data->z +=
+			priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].z;
+
+		incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.head);
+	}
+
+	up(&priv->tsi_raw_fifo.lock);
+
+	tsi_avg_data->x /= TSI_AVERAGE_FILTER_SIZE;
+	tsi_avg_data->y /= TSI_AVERAGE_FILTER_SIZE;
+	tsi_avg_data->z /= TSI_AVERAGE_FILTER_SIZE;
+
+#if DA9052_TSI_AVG_FLT_DATA_PROFILING
+	printk(KERN_DEBUG "A\tX\t%4d\tY\t%4d\tZ\t%4d\n",
+			(u16)tsi_avg_data->x,
+			(u16)tsi_avg_data->y,
+			(u16)tsi_avg_data->z);
+#endif
+
+	return;
+}
+#endif
+
+s32 da9052_tsi_raw_proc_thread(void *ptr)
+{
+	struct da9052_tsi_data coord;
+	u8 calib_ok, range_ok;
+	struct calib_cfg_t *tsi_calib = get_calib_config();
+	struct input_dev *ip_dev = (struct input_dev *)
+				da9052_tsi_get_input_dev(
+						(u8)TSI_INPUT_DEVICE_OFF);
+	struct da9052_ts_priv *priv = (struct da9052_ts_priv *)ptr;
+
+	set_freezable();
+
+	while (priv->tsi_raw_proc_thread.state == ACTIVE) {
+
+		try_to_freeze();
+
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(
+			msecs_to_jiffies(priv->tsi_raw_data_poll_interval));
+
+		if (priv->early_data_flag || (get_raw_data_cnt(priv) == 0))
+			continue;
+
+		calib_ok = TRUE;
+		range_ok = TRUE;
+
+#if (ENABLE_AVERAGE_FILTER)
+
+		if (get_raw_data_cnt(priv) < TSI_AVERAGE_FILTER_SIZE)
+			continue;
+
+		da9052_tsi_avrg_filter(priv, &coord);
+
+#else
+
+		if (down_interruptible(&priv->tsi_raw_fifo.lock))
+			continue;
+
+		coord = priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head];
+		incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.head);
+
+		up(&priv->tsi_raw_fifo.lock);
+
+#endif
+
+		if (tsi_calib->calibrate_flag) {
+			calib_ok = da9052_tsi_get_calib_display_point(&coord);
+
+			if ((coord.x < DISPLAY_X_MIN) ||
+				(coord.x > DISPLAY_X_MAX) ||
+				(coord.y < DISPLAY_Y_MIN) ||
+						(coord.y > DISPLAY_Y_MAX))
+				range_ok = FALSE;
+		}
+
+		if (calib_ok && range_ok) {
+			input_report_abs(ip_dev, BTN_TOUCH, 1);
+			input_report_abs(ip_dev, ABS_X, coord.x);
+			input_report_abs(ip_dev, ABS_Y, coord.y);
+			input_sync(ip_dev);
+
+			priv->os_data_cnt++;
+
+#if DA9052_TSI_OS_DATA_PROFILING
+		printk(KERN_DEBUG "O\tX\t%4d\tY\t%4d\tZ\t%4d\n",  (u16)coord.x,
+						(u16)coord.y, (u16)coord.z);
+#endif
+		} else {
+			if (!calib_ok) {
+				DA9052_DEBUG("%s: ", __func__);
+				DA9052_DEBUG("calibration Failed\n");
+			}
+			if (!range_ok) {
+				DA9052_DEBUG("%s: ", __func__);
+				DA9052_DEBUG("sample beyond display ");
+				DA9052_DEBUG("panel dimension\n");
+			}
+		}
+	}
+	priv->tsi_raw_proc_thread.thread_task = NULL;
+	complete_and_exit(&priv->tsi_raw_proc_thread.notifier, 0);
+	return 0;
+
+}
+
+#if (ENABLE_TSI_DEBOUNCE)
+static s32 da9052_tsi_calc_debounce_data(struct da9052_tsi_data *raw_data)
+{
+#if (TSI_DEBOUNCE_DATA_CNT)
+	u8 cnt;
+	struct da9052_tsi_data	temp = {.x = 0, .y = 0, .z = 0};
+
+	priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.tail] = (*raw_data);
+	incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.tail);
+
+	if (get_raw_data_cnt(priv) <= TSI_DEBOUNCE_DATA_CNT)
+		return -FAILURE;
+
+	for (cnt = 1; cnt <= TSI_DEBOUNCE_DATA_CNT; cnt++) {
+		temp.x += priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].x;
+		temp.y += priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].y;
+		temp.z += priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].z;
+
+		incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.head);
+	}
+
+	temp.x /= TSI_DEBOUNCE_DATA_CNT;
+	temp.y /= TSI_DEBOUNCE_DATA_CNT;
+	temp.z /= TSI_DEBOUNCE_DATA_CNT;
+
+	priv->tsi_raw_fifo.tail = priv->tsi_raw_fifo.head;
+	priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.tail] = temp;
+	incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.tail);
+
+#if DA9052_TSI_PRINT_DEBOUNCED_DATA
+	printk(KERN_DEBUG "D: X: %d Y: %d Z: %d\n",
+	       (u16)temp.x, (u16)temp.y, (u16)temp.z);
+#endif
+
+#endif
+	priv->debounce_over = TRUE;
+
+	return 0;
+}
+#endif
+
+# if (ENABLE_WINDOW_FILTER)
+static s32 diff_within_window(struct da9052_tsi_data *prev_raw_data,
+				struct da9052_tsi_data *cur_raw_data)
+{
+	s32 ret = -EINVAL;
+	s32 x, y;
+	x = ((cur_raw_data->x) - (prev_raw_data->x));
+	y = ((cur_raw_data->y) - (prev_raw_data->y));
+
+	if (WITHIN_WINDOW(x, y)) {
+
+#if DA9052_TSI_WIN_FLT_DATA_PROFILING
+		printk(KERN_DEBUG "W\tX\t%4d\tY\t%4d\tZ\t%4d\n",
+					(u16)cur_raw_data->x,
+					(u16)cur_raw_data->y,
+					(u16)cur_raw_data->z);
+#endif
+		ret = 0;
+	}
+	return ret;
+}
+
+static s32 da9052_tsi_window_filter(struct da9052_ts_priv *priv,
+					struct da9052_tsi_data *raw_data)
+{
+	u8 ref_found;
+	u32 cur, next;
+	s32 ret = -EINVAL;
+	static struct da9052_tsi_data prev_raw_data;
+
+	if (priv->win_reference_valid == TRUE) {
+
+#if DA9052_TSI_PRINT_PREVIOUS_DATA
+		printk(KERN_DEBUG "P: X: %d Y: %d Z: %d\n",
+		(u16)prev_raw_data.x, (u16)prev_raw_data.y,
+		(u16)prev_raw_data.z);
+#endif
+		ret = diff_within_window(&prev_raw_data, raw_data);
+		if (!ret)
+			prev_raw_data = (*raw_data);
+	} else {
+		priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.tail] = (*raw_data);
+		incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.tail);
+
+		if (get_raw_data_cnt(priv) == SAMPLE_CNT_FOR_WIN_REF) {
+
+			ref_found = FALSE;
+
+			next = cur = priv->tsi_raw_fifo.head;
+			incr_with_wrap_raw_fifo(next);
+
+			while (next <= priv->tsi_raw_fifo.tail) {
+				ret = diff_within_window(
+						&priv->tsi_raw_fifo.data[cur],
+						&priv->tsi_raw_fifo.data[next]
+						);
+				if (ret == SUCCESS) {
+					ref_found = TRUE;
+					break;
+				}
+				incr_with_wrap_raw_fifo(cur);
+				incr_with_wrap_raw_fifo(next);
+
+			}
+
+			if (ref_found == FALSE)
+				priv->tsi_raw_fifo.tail =
+					priv->tsi_raw_fifo.head;
+			else {
+				prev_raw_data = priv->tsi_raw_fifo.data[cur];
+
+				prev_raw_data.x +=
+					priv->tsi_raw_fifo.data[next].x;
+				prev_raw_data.y +=
+					priv->tsi_raw_fifo.data[next].y;
+				prev_raw_data.z +=
+					priv->tsi_raw_fifo.data[next].z;
+
+				prev_raw_data.x = prev_raw_data.x / 2;
+				prev_raw_data.y = prev_raw_data.y / 2;
+				prev_raw_data.z = prev_raw_data.z / 2;
+
+				(*raw_data) = prev_raw_data;
+
+				priv->tsi_raw_fifo.tail =
+						priv->tsi_raw_fifo.head;
+
+				priv->win_reference_valid = TRUE;
+				ret = SUCCESS;
+			}
+		}
+	}
+	return ret;
+}
+#endif
+static inline void clean_tsi_reg_fifo(struct da9052_ts_priv *priv)
+{
+	priv->tsi_reg_fifo.head = FIRST_SAMPLE;
+	priv->tsi_reg_fifo.tail = FIRST_SAMPLE;
+}
+
+static inline void clean_tsi_raw_fifo(struct da9052_ts_priv *priv)
+{
+	priv->tsi_raw_fifo.head = FIRST_SAMPLE;
+	priv->tsi_raw_fifo.tail = FIRST_SAMPLE;
+}
+
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index ff203a42186..7dc65559c56 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -457,4 +457,14 @@ config LEDS_TRIGGER_DEFAULT_ON
 comment "iptables trigger is under Netfilter config (LED target)"
 	depends on LEDS_TRIGGERS
 
+config LEDS_DA9052
+	tristate "Dialog DA9052 LEDS"
+	depends on PMIC_DIALOG
+	select LEDS_CLASS
+	help
+	  This option enables support for on-chip LED drivers found
+	  on Dialog Semiconductor DA9052 PMICs.
+
+comment "LED Triggers"
+
 endif # NEW_LEDS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index e4f6bf56888..33ffdaa8211 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_LEDS_NS2)			+= leds-ns2.o
 obj-$(CONFIG_LEDS_NETXBIG)		+= leds-netxbig.o
 obj-$(CONFIG_LEDS_ASIC3)		+= leds-asic3.o
 obj-$(CONFIG_LEDS_RENESAS_TPU)		+= leds-renesas-tpu.o
+obj-$(CONFIG_LEDS_DA9052)		+= leds-da9052.o
 
 # LED SPI Drivers
 obj-$(CONFIG_LEDS_DAC124S085)		+= leds-dac124s085.o
diff --git a/drivers/leds/leds-da9052.c b/drivers/leds/leds-da9052.c
new file mode 100644
index 00000000000..f829a0e66a6
--- /dev/null
+++ b/drivers/leds/leds-da9052.c
@@ -0,0 +1,308 @@
+/*
+ * leds-da9052.c  --  LED Driver for Dialog DA9052
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * Author: Dialog Semiconductor Ltd <dchen@diasemi.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/workqueue.h>
+#include <linux/slab.h>
+
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/led.h>
+
+#define DRIVER_NAME		"da9052-leds"
+
+#define DA9052_LED4_PRESENT	1
+#define DA9052_LED5_PRESENT	1
+
+
+struct da9052_led_data {
+	struct led_classdev cdev;
+	struct work_struct work;
+	struct da9052 *da9052;
+	int id;
+	int new_brightness;
+	int is_led4_present;
+	int is_led5_present;
+};
+
+#define GPIO14_PIN		2 /* GPO Open Drain */
+#define GPIO14_TYPE		0 /* VDD_IO1 */
+#define GPIO14_MODE		1 /* Output High */
+
+#define GPIO15_PIN		2 /* GPO Open Drain */
+#define GPIO15_TYPE		0 /* VDD_IO1 */
+#define GPIO15_MODE		1 /* Output High */
+
+#define MAXIMUM_PWM		95
+#define MASK_GPIO14		0x0F
+#define MASK_GPIO15		0xF0
+#define GPIO15_PIN_BIT_POSITION	4
+
+static void da9052_led_work(struct work_struct *work)
+{
+	struct da9052_led_data *led = container_of(work,
+				 struct da9052_led_data, work);
+	int reg = 0;
+	int led_dim_bit = 0;
+	struct da9052_ssc_msg msg;
+	int ret = 0;
+
+	switch (led->id) {
+	case DA9052_LED_4:
+		reg = DA9052_LED4CONT_REG;
+		led_dim_bit = DA9052_LED4CONT_LED4DIM;
+	break;
+	case DA9052_LED_5:
+		reg = DA9052_LED5CONT_REG;
+		led_dim_bit = DA9052_LED5CONT_LED5DIM;
+	break;
+	}
+
+	if (led->new_brightness > MAXIMUM_PWM)
+		led->new_brightness = MAXIMUM_PWM;
+
+	/* Always enable DIM feature
+	 * This feature can be disabled if required
+	 */
+	msg.addr = reg;
+	msg.data = led->new_brightness | led_dim_bit;
+	da9052_lock(led->da9052);
+	ret = led->da9052->write(led->da9052, &msg);
+	if (ret) {
+		da9052_unlock(led->da9052);
+		return;
+	}
+	da9052_unlock(led->da9052);
+}
+
+static void da9052_led_set(struct led_classdev *led_cdev,
+			   enum led_brightness value)
+{
+	struct da9052_led_data *led;
+
+	led = container_of(led_cdev, struct da9052_led_data, cdev);
+	led->new_brightness = value;
+	schedule_work(&led->work);
+}
+
+static int __devinit da9052_led_setup(struct da9052_led_data *led)
+{
+	int reg = 0;
+	int ret = 0;
+
+	struct da9052_ssc_msg msg;
+
+	switch (led->id) {
+	case DA9052_LED_4:
+		reg = DA9052_LED4CONT_REG;
+	break;
+	case DA9052_LED_5:
+		reg = DA9052_LED5CONT_REG;
+	break;
+	}
+
+	msg.addr = reg;
+	msg.data = 0;
+
+	da9052_lock(led->da9052);
+	ret = led->da9052->write(led->da9052, &msg);
+	if (ret) {
+		da9052_unlock(led->da9052);
+		return ret;
+	}
+	da9052_unlock(led->da9052);
+	return ret;
+}
+
+static int da9052_leds_prepare(struct da9052_led_data *led)
+{
+	int ret = 0;
+	struct da9052_ssc_msg msg;
+
+	da9052_lock(led->da9052);
+
+	if (1 == led->is_led4_present) {
+		msg.addr = DA9052_GPIO1415_REG;
+		msg.data = 0;
+
+		ret = led->da9052->read(led->da9052, &msg);
+		if (ret)
+			goto out;
+		msg.data = msg.data & ~(MASK_GPIO14);
+		msg.data = msg.data | (
+				GPIO14_PIN |
+				(GPIO14_TYPE ? DA9052_GPIO1415_GPIO14TYPE : 0) |
+				(GPIO14_MODE ? DA9052_GPIO1415_GPIO14MODE : 0));
+
+		ret = led->da9052->write(led->da9052, &msg);
+		if (ret)
+			goto out;
+	}
+
+	if (1 == led->is_led5_present) {
+		msg.addr = DA9052_GPIO1415_REG;
+		msg.data = 0;
+
+		ret = led->da9052->read(led->da9052, &msg);
+		if (ret)
+			goto out;
+		msg.data = msg.data & ~(MASK_GPIO15);
+		msg.data = msg.data |
+			(((GPIO15_PIN << GPIO15_PIN_BIT_POSITION) |
+				(GPIO15_TYPE ? DA9052_GPIO1415_GPIO15TYPE : 0) |
+				(GPIO15_MODE ? DA9052_GPIO1415_GPIO15MODE : 0))
+				);
+		ret = led->da9052->write(led->da9052, &msg);
+		if (ret)
+			goto out;
+	}
+
+	da9052_unlock(led->da9052);
+	return ret;
+out:
+	da9052_unlock(led->da9052);
+	return ret;
+}
+
+static int __devinit da9052_led_probe(struct platform_device *pdev)
+{
+	struct da9052_leds_platform_data *pdata = (pdev->dev.platform_data);
+	struct da9052_led_platform_data *led_cur;
+	struct da9052_led_data *led, *led_dat;
+	int ret, i;
+	int init_led = 0;
+
+	if (pdata->num_leds < 1 || pdata->num_leds > DA9052_LED_MAX) {
+		dev_err(&pdev->dev, "Invalid led count %d\n", pdata->num_leds);
+		return -EINVAL;
+	}
+
+	led = kzalloc(sizeof(*led) * pdata->num_leds, GFP_KERNEL);
+	if (led == NULL) {
+		dev_err(&pdev->dev, "failed to alloc memory\n");
+		return -ENOMEM;
+	}
+
+	led->is_led4_present = DA9052_LED4_PRESENT;
+	led->is_led5_present = DA9052_LED5_PRESENT;
+
+	for (i = 0; i < pdata->num_leds; i++) {
+		led_dat = &led[i];
+		led_cur = &pdata->led[i];
+		if (led_cur->id < 0) {
+			dev_err(&pdev->dev, "invalid id %d\n", led_cur->id);
+			ret = -EINVAL;
+			goto err_register;
+		}
+
+		if (init_led & (1 << led_cur->id)) {
+			dev_err(&pdev->dev, "led %d already initialized\n",
+					led_cur->id);
+			ret = -EINVAL;
+			goto err_register;
+		}
+
+		init_led |= 1 << led_cur->id;
+
+		led_dat->cdev.name = led_cur->name;
+		/* led_dat->cdev.default_trigger =
+		   led_cur[i]->default_trigger; */
+		led_dat->cdev.brightness_set = da9052_led_set;
+		led_dat->cdev.brightness = LED_OFF;
+		led_dat->id = led_cur->id;
+		led_dat->da9052 = dev_get_drvdata(pdev->dev.parent);
+
+		INIT_WORK(&led_dat->work, da9052_led_work);
+
+		ret = led_classdev_register(pdev->dev.parent, &led_dat->cdev);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to register led %d\n",
+					led_dat->id);
+			goto err_register;
+
+		}
+		ret = da9052_led_setup(led_dat);
+		if (ret) {
+			dev_err(&pdev->dev, "unable to init led %d\n",
+					led_dat->id);
+			i++;
+			goto err_register;
+		}
+	}
+	ret = da9052_leds_prepare(led);
+	if (ret) {
+		dev_err(&pdev->dev, "unable to init led driver\n");
+		goto err_free;
+	}
+
+	platform_set_drvdata(pdev, led);
+	return 0;
+
+err_register:
+	for (i = i - 1; i >= 0; i--) {
+		led_classdev_unregister(&led[i].cdev);
+		cancel_work_sync(&led[i].work);
+	}
+
+err_free:
+	kfree(led);
+	return ret;
+}
+
+static int __devexit da9052_led_remove(struct platform_device *pdev)
+{
+	struct da9052_leds_platform_data *pdata =
+		(struct da9052_leds_platform_data *)pdev->dev.platform_data;
+	struct da9052_led_data *led = platform_get_drvdata(pdev);
+	int i;
+
+	for (i = 0; i < pdata->num_leds; i++) {
+		da9052_led_setup(&led[i]);
+		led_classdev_unregister(&led[i].cdev);
+		cancel_work_sync(&led[i].work);
+	}
+
+	kfree(led);
+	return 0;
+}
+
+static struct platform_driver da9052_led_driver = {
+	.driver	= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+	},
+	.probe		= da9052_led_probe,
+	.remove		= __devexit_p(da9052_led_remove),
+};
+
+static int __init da9052_led_init(void)
+{
+	return platform_driver_register(&da9052_led_driver);
+}
+module_init(da9052_led_init);
+
+static void __exit da9052_led_exit(void)
+{
+	platform_driver_unregister(&da9052_led_driver);
+}
+module_exit(da9052_led_exit);
+
+MODULE_AUTHOR("Dialog Semiconductor Ltd <dchen@diasemi.com>	");
+MODULE_DESCRIPTION("LED driver for Dialog DA9052 PMIC");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index b303a3f8a9f..78b1b00f895 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -1002,6 +1002,17 @@ config VIDEO_S5P_MIPI_CSIS
 
 source "drivers/media/video/s5p-tv/Kconfig"
 
+config VIDEO_MXC_OUTPUT
+        tristate "MXC Video For Linux Video Output"
+        depends on VIDEO_DEV && ARCH_MXC
+	select VIDEOBUF_DMA_CONTIG
+        default y
+        ---help---
+          This is the video4linux2 output driver based on MXC IPU/eMMA module.
+
+source "drivers/media/video/mxc/output/Kconfig"
+
+
 #
 # USB Multimedia device configuration
 #
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index 117f9c4b4cb..ec5a18758f8 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_SOC_CAMERA_TW9910)		+= tw9910.o
 
 # And now the v4l2 drivers:
 
+obj-$(CONFIG_VIDEO_MXC_IPU_OUTPUT) += mxc/output/
 obj-$(CONFIG_VIDEO_BT848) += bt8xx/
 obj-$(CONFIG_VIDEO_ZORAN) += zoran/
 obj-$(CONFIG_VIDEO_CQCAM) += c-qcam.o
diff --git a/drivers/media/video/mxc/output/Kconfig b/drivers/media/video/mxc/output/Kconfig
new file mode 100644
index 00000000000..72b32879697
--- /dev/null
+++ b/drivers/media/video/mxc/output/Kconfig
@@ -0,0 +1,7 @@
+config VIDEO_MXC_IPU_OUTPUT
+	bool "IPU v4l2 support"
+	depends on VIDEO_MXC_OUTPUT && MXC_IPU && FB_MXC
+	default y
+	---help---
+	  This is the video4linux2 driver for IPU post processing video output.
+
diff --git a/drivers/media/video/mxc/output/Makefile b/drivers/media/video/mxc/output/Makefile
new file mode 100644
index 00000000000..9b66e059b26
--- /dev/null
+++ b/drivers/media/video/mxc/output/Makefile
@@ -0,0 +1,3 @@
+ifeq ($(CONFIG_VIDEO_MXC_IPU_OUTPUT),y)
+	obj-$(CONFIG_VIDEO_MXC_OUTPUT)	+= mxc_vout.o
+endif
diff --git a/drivers/media/video/mxc/output/mxc_vout.c b/drivers/media/video/mxc/output/mxc_vout.c
new file mode 100644
index 00000000000..08edfb3087e
--- /dev/null
+++ b/drivers/media/video/mxc/output/mxc_vout.c
@@ -0,0 +1,1651 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/videodev2.h>
+#include <linux/mxcfb.h>
+#include <linux/console.h>
+#include <linux/mxc_v4l2.h>
+#include <mach/ipu-v3.h>
+
+#include <media/videobuf-dma-contig.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+
+#define MAX_FB_NUM	6
+#define FB_BUFS		3
+
+struct mxc_vout_fb {
+	char *name;
+	int ipu_id;
+	struct v4l2_rect crop_bounds;
+	unsigned int disp_fmt;
+	bool disp_support_csc;
+	bool disp_support_windows;
+};
+
+struct mxc_vout_output {
+	int open_cnt;
+	struct fb_info *fbi;
+	struct video_device *vfd;
+	struct mutex mutex;
+	struct mutex task_lock;
+	enum v4l2_buf_type type;
+
+	struct videobuf_queue vbq;
+	spinlock_t vbq_lock;
+
+	struct list_head queue_list;
+	struct list_head active_list;
+
+	struct v4l2_rect crop_bounds;
+	unsigned int disp_fmt;
+	struct mxcfb_pos win_pos;
+	bool disp_support_windows;
+	bool disp_support_csc;
+
+	bool fmt_init;
+	bool bypass_pp;
+	struct ipu_task	task;
+
+	bool timer_stop;
+	struct timer_list timer;
+	struct workqueue_struct *v4l_wq;
+	struct work_struct disp_work;
+	unsigned long frame_count;
+	unsigned long start_jiffies;
+
+	int ctrl_rotate;
+	int ctrl_vflip;
+	int ctrl_hflip;
+
+	dma_addr_t disp_bufs[FB_BUFS];
+
+	struct videobuf_buffer *pre_vb;
+};
+
+struct mxc_vout_dev {
+	struct device	*dev;
+	struct v4l2_device v4l2_dev;
+	struct mxc_vout_output *out[MAX_FB_NUM];
+	int out_num;
+};
+
+/* Driver Configuration macros */
+#define VOUT_NAME		"mxc_vout"
+
+/* Variables configurable through module params*/
+static int debug;
+static int video_nr = 16;
+
+/* Module parameters */
+module_param(video_nr, int, S_IRUGO);
+MODULE_PARM_DESC(video_nr, "video device numbers");
+module_param(debug, bool, S_IRUGO);
+MODULE_PARM_DESC(debug, "Debug level (0-1)");
+
+const static struct v4l2_fmtdesc mxc_formats[] = {
+	{
+		.description = "RGB565",
+		.pixelformat = V4L2_PIX_FMT_RGB565,
+	},
+	{
+		.description = "BGR24",
+		.pixelformat = V4L2_PIX_FMT_BGR24,
+	},
+	{
+		.description = "RGB24",
+		.pixelformat = V4L2_PIX_FMT_RGB24,
+	},
+	{
+		.description = "RGB32",
+		.pixelformat = V4L2_PIX_FMT_RGB32,
+	},
+	{
+		.description = "BGR32",
+		.pixelformat = V4L2_PIX_FMT_BGR32,
+	},
+	{
+		.description = "NV12",
+		.pixelformat = V4L2_PIX_FMT_NV12,
+	},
+	{
+		.description = "UYVY",
+		.pixelformat = V4L2_PIX_FMT_UYVY,
+	},
+	{
+		.description = "YUYV",
+		.pixelformat = V4L2_PIX_FMT_YUYV,
+	},
+	{
+		.description = "YUV422 planar",
+		.pixelformat = V4L2_PIX_FMT_YUV422P,
+	},
+	{
+		.description = "YUV444",
+		.pixelformat = V4L2_PIX_FMT_YUV444,
+	},
+	{
+		.description = "YUV420",
+		.pixelformat = V4L2_PIX_FMT_YUV420,
+	},
+};
+
+#define NUM_MXC_VOUT_FORMATS (ARRAY_SIZE(mxc_formats))
+
+#define DEF_INPUT_WIDTH		320
+#define DEF_INPUT_HEIGHT	240
+
+static int mxc_vidioc_streamoff(struct file *file, void *fh, enum v4l2_buf_type i);
+
+static struct mxc_vout_fb g_fb_setting[MAX_FB_NUM];
+static int config_disp_output(struct mxc_vout_output *vout);
+static void release_disp_output(struct mxc_vout_output *vout);
+
+static ipu_channel_t get_ipu_channel(struct fb_info *fbi)
+{
+	ipu_channel_t ipu_ch = CHAN_NONE;
+	mm_segment_t old_fs;
+
+	if (fbi->fbops->fb_ioctl) {
+		old_fs = get_fs();
+		set_fs(KERNEL_DS);
+		fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN,
+				(unsigned long)&ipu_ch);
+		set_fs(old_fs);
+	}
+
+	return ipu_ch;
+}
+
+static unsigned int get_ipu_fmt(struct fb_info *fbi)
+{
+	mm_segment_t old_fs;
+	unsigned int fb_fmt;
+
+	if (fbi->fbops->fb_ioctl) {
+		old_fs = get_fs();
+		set_fs(KERNEL_DS);
+		fbi->fbops->fb_ioctl(fbi, MXCFB_GET_DIFMT,
+				(unsigned long)&fb_fmt);
+		set_fs(old_fs);
+	}
+
+	return fb_fmt;
+}
+
+static void update_display_setting(void)
+{
+	int i;
+	struct fb_info *fbi;
+	struct v4l2_rect bg_crop_bounds[2];
+
+	for (i = 0; i < num_registered_fb; i++) {
+		fbi = registered_fb[i];
+
+		memset(&g_fb_setting[i], 0, sizeof(struct mxc_vout_fb));
+
+		if (!strncmp(fbi->fix.id, "DISP3", 5))
+			g_fb_setting[i].ipu_id = 0;
+		else
+			g_fb_setting[i].ipu_id = 1;
+
+		g_fb_setting[i].name = fbi->fix.id;
+		g_fb_setting[i].crop_bounds.left = 0;
+		g_fb_setting[i].crop_bounds.top = 0;
+		g_fb_setting[i].crop_bounds.width = fbi->var.xres;
+		g_fb_setting[i].crop_bounds.height = fbi->var.yres;
+		g_fb_setting[i].disp_fmt = get_ipu_fmt(fbi);
+
+		if (get_ipu_channel(fbi) == MEM_BG_SYNC) {
+			bg_crop_bounds[g_fb_setting[i].ipu_id] =
+				g_fb_setting[i].crop_bounds;
+			g_fb_setting[i].disp_support_csc = true;
+		} else if (get_ipu_channel(fbi) == MEM_FG_SYNC) {
+			g_fb_setting[i].disp_support_csc = true;
+			g_fb_setting[i].disp_support_windows = true;
+		}
+	}
+
+	for (i = 0; i < num_registered_fb; i++) {
+		fbi = registered_fb[i];
+
+		if (get_ipu_channel(fbi) == MEM_FG_SYNC)
+			g_fb_setting[i].crop_bounds =
+				bg_crop_bounds[g_fb_setting[i].ipu_id];
+	}
+}
+
+/* called after g_fb_setting filled by update_display_setting */
+static int update_setting_from_fbi(struct mxc_vout_output *vout,
+			struct fb_info *fbi)
+{
+	int i;
+	bool found = false;
+
+	for (i = 0; i < MAX_FB_NUM; i++) {
+		if (g_fb_setting[i].name) {
+			if (!strcmp(fbi->fix.id, g_fb_setting[i].name)) {
+				vout->crop_bounds = g_fb_setting[i].crop_bounds;
+				vout->disp_fmt = g_fb_setting[i].disp_fmt;
+				vout->disp_support_csc = g_fb_setting[i].disp_support_csc;
+				vout->disp_support_windows =
+					g_fb_setting[i].disp_support_windows;
+				found = true;
+				break;
+			}
+		}
+	}
+
+	if (!found) {
+		v4l2_err(vout->vfd->v4l2_dev, "can not find output\n");
+		return -EINVAL;
+	}
+	strlcpy(vout->vfd->name, fbi->fix.id, sizeof(vout->vfd->name));
+
+	memset(&vout->task, 0, sizeof(struct ipu_task));
+
+	vout->task.input.width = DEF_INPUT_WIDTH;
+	vout->task.input.height = DEF_INPUT_HEIGHT;
+	vout->task.input.crop.pos.x = 0;
+	vout->task.input.crop.pos.y = 0;
+	vout->task.input.crop.w = DEF_INPUT_WIDTH;
+	vout->task.input.crop.h = DEF_INPUT_HEIGHT;
+
+	vout->task.output.width = vout->crop_bounds.width;
+	vout->task.output.height = vout->crop_bounds.height;
+	vout->task.output.crop.pos.x = 0;
+	vout->task.output.crop.pos.y = 0;
+	vout->task.output.crop.w = vout->crop_bounds.width;
+	vout->task.output.crop.h = vout->crop_bounds.height;
+	if (colorspaceofpixel(vout->disp_fmt) == YUV_CS)
+		vout->task.output.format = IPU_PIX_FMT_UYVY;
+	else
+		vout->task.output.format = IPU_PIX_FMT_RGB565;
+
+	return 0;
+}
+
+static inline unsigned long get_jiffies(struct timeval *t)
+{
+	struct timeval cur;
+
+	if (t->tv_usec >= 1000000) {
+		t->tv_sec += t->tv_usec / 1000000;
+		t->tv_usec = t->tv_usec % 1000000;
+	}
+
+	do_gettimeofday(&cur);
+	if ((t->tv_sec < cur.tv_sec)
+	    || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec)))
+		return jiffies;
+
+	if (t->tv_usec < cur.tv_usec) {
+		cur.tv_sec = t->tv_sec - cur.tv_sec - 1;
+		cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec;
+	} else {
+		cur.tv_sec = t->tv_sec - cur.tv_sec;
+		cur.tv_usec = t->tv_usec - cur.tv_usec;
+	}
+
+	return jiffies + timeval_to_jiffies(&cur);
+}
+
+static bool deinterlace_3_field(struct mxc_vout_output *vout)
+{
+	return (vout->task.input.deinterlace.enable &&
+		(vout->task.input.deinterlace.motion != HIGH_MOTION));
+}
+
+static bool is_pp_bypass(struct mxc_vout_output *vout)
+{
+	if ((vout->task.input.width == vout->task.output.width) &&
+		(vout->task.input.height == vout->task.output.height) &&
+		(vout->task.input.crop.w == vout->task.output.crop.w) &&
+		(vout->task.input.crop.h == vout->task.output.crop.h) &&
+		(vout->task.output.rotate < IPU_ROTATE_HORIZ_FLIP) &&
+		!vout->task.input.deinterlace.enable) {
+		if (vout->disp_support_csc)
+			return true;
+		else if (!need_csc(vout->task.input.format, vout->disp_fmt))
+			return true;
+	/* input crop show to full output which can show based on xres_virtual/yres_virtual */
+	} else if ((vout->task.input.crop.w == vout->task.output.crop.w) &&
+			(vout->task.output.crop.w == vout->task.output.width) &&
+			(vout->task.input.crop.h == vout->task.output.crop.h) &&
+			(vout->task.output.crop.h == vout->task.output.height) &&
+			(vout->task.output.rotate < IPU_ROTATE_HORIZ_FLIP) &&
+			!vout->task.input.deinterlace.enable) {
+		if (vout->disp_support_csc)
+			return true;
+		else if (!need_csc(vout->task.input.format, vout->disp_fmt))
+			return true;
+	}
+	return false;
+}
+
+static void setup_buf_timer(struct mxc_vout_output *vout,
+			struct videobuf_buffer *vb)
+{
+	unsigned long timeout;
+
+	/* if timestamp is 0, then default to 30fps */
+	if ((vb->ts.tv_sec == 0)
+			&& (vb->ts.tv_usec == 0)
+			&& vout->start_jiffies)
+		timeout =
+			vout->start_jiffies + vout->frame_count * HZ / 30;
+	else
+		timeout = get_jiffies(&vb->ts);
+
+	if (jiffies >= timeout) {
+		v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
+				"warning: timer timeout already expired.\n");
+	}
+
+	if (mod_timer(&vout->timer, timeout)) {
+		v4l2_warn(vout->vfd->v4l2_dev,
+				"warning: timer was already set\n");
+	}
+
+	v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
+			"timer handler next schedule: %lu\n", timeout);
+}
+
+static int show_buf(struct mxc_vout_output *vout, int idx,
+	struct ipu_pos *ipos)
+{
+	struct fb_info *fbi = vout->fbi;
+	struct fb_var_screeninfo var;
+	int ret;
+
+	memcpy(&var, &fbi->var, sizeof(var));
+
+	if (vout->bypass_pp) {
+		/*
+		 * crack fb base
+		 * NOTE: should not do other fb operation during v4l2
+		 */
+		console_lock();
+		fbi->fix.smem_start = vout->task.output.paddr;
+		fbi->var.yoffset = ipos->y + 1;
+		var.xoffset = ipos->x;
+		var.yoffset = ipos->y;
+		ret = fb_pan_display(fbi, &var);
+		console_unlock();
+	} else {
+		var.yoffset = idx * fbi->var.yres;
+		console_lock();
+		ret = fb_pan_display(fbi, &var);
+		console_unlock();
+	}
+
+	return ret;
+}
+
+static void disp_work_func(struct work_struct *work)
+{
+	struct mxc_vout_output *vout =
+		container_of(work, struct mxc_vout_output, disp_work);
+	struct videobuf_queue *q = &vout->vbq;
+	struct videobuf_buffer *vb, *vb_next = NULL;
+	unsigned long flags = 0;
+	struct ipu_pos ipos;
+	int ret = 0;
+
+	v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "disp work begin one frame\n");
+
+	spin_lock_irqsave(q->irqlock, flags);
+
+	if (deinterlace_3_field(vout)) {
+		if (list_is_singular(&vout->active_list)) {
+			v4l2_warn(vout->vfd->v4l2_dev,
+					"deinterlacing: no enough entry in active_list\n");
+			spin_unlock_irqrestore(q->irqlock, flags);
+			return;
+		}
+	} else {
+		if (list_empty(&vout->active_list)) {
+			v4l2_warn(vout->vfd->v4l2_dev,
+					"no entry in active_list, should not be here\n");
+			spin_unlock_irqrestore(q->irqlock, flags);
+			return;
+		}
+	}
+	vb = list_first_entry(&vout->active_list,
+			struct videobuf_buffer, queue);
+
+	if (deinterlace_3_field(vout))
+		vb_next = list_first_entry(vout->active_list.next,
+				struct videobuf_buffer, queue);
+
+	spin_unlock_irqrestore(q->irqlock, flags);
+
+	mutex_lock(&vout->task_lock);
+
+	if (vb->memory == V4L2_MEMORY_USERPTR)
+		vout->task.input.paddr = vb->baddr;
+	else
+		vout->task.input.paddr = videobuf_to_dma_contig(vb);
+
+	if (vout->bypass_pp) {
+		vout->task.output.paddr = vout->task.input.paddr;
+		ipos.x = vout->task.input.crop.pos.x;
+		ipos.y = vout->task.input.crop.pos.y;
+	} else {
+		if (deinterlace_3_field(vout)) {
+			if (vb->memory == V4L2_MEMORY_USERPTR)
+				vout->task.input.paddr_n = vb_next->baddr;
+			else
+				vout->task.input.paddr_n =
+					videobuf_to_dma_contig(vb_next);
+		}
+		vout->task.output.paddr =
+			vout->disp_bufs[vout->frame_count % FB_BUFS];
+		ret = ipu_queue_task(&vout->task);
+		if (ret < 0) {
+			mutex_unlock(&vout->task_lock);
+			goto err;
+		}
+	}
+
+	mutex_unlock(&vout->task_lock);
+
+	ret = show_buf(vout, vout->frame_count % FB_BUFS, &ipos);
+	if (ret < 0)
+		v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "show buf with ret %d\n", ret);
+
+	spin_lock_irqsave(q->irqlock, flags);
+
+	list_del(&vb->queue);
+
+	/*
+	 * previous videobuf finish show, set VIDEOBUF_DONE state here
+	 * to avoid tearing issue in pp bypass case, which make sure
+	 * showing buffer will not be dequeue to write new data. It also
+	 * bring side-effect that the last buffer can not be dequeue
+	 * correctly, app need take care about it.
+	 */
+	if (vout->pre_vb) {
+		vout->pre_vb->state = VIDEOBUF_DONE;
+		wake_up_interruptible(&vout->pre_vb->done);
+	}
+
+	if (vout->bypass_pp)
+		vout->pre_vb = vb;
+	else {
+		vout->pre_vb = NULL;
+		vb->state = VIDEOBUF_DONE;
+		wake_up_interruptible(&vb->done);
+	}
+
+	vout->frame_count++;
+
+	/* pick next queue buf to setup timer */
+	if (list_empty(&vout->queue_list))
+		vout->timer_stop = true;
+	else {
+		vb = list_first_entry(&vout->queue_list,
+				struct videobuf_buffer, queue);
+		setup_buf_timer(vout, vb);
+	}
+
+	spin_unlock_irqrestore(q->irqlock, flags);
+
+	v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "disp work finish one frame\n");
+
+	return;
+err:
+	v4l2_err(vout->vfd->v4l2_dev, "display work fail ret = %d\n", ret);
+	vout->timer_stop = true;
+	vb->state = VIDEOBUF_ERROR;
+	return;
+}
+
+static void mxc_vout_timer_handler(unsigned long arg)
+{
+	struct mxc_vout_output *vout =
+			(struct mxc_vout_output *) arg;
+	struct videobuf_queue *q = &vout->vbq;
+	struct videobuf_buffer *vb;
+	unsigned long flags = 0;
+
+	spin_lock_irqsave(q->irqlock, flags);
+
+	/*
+	 * put first queued entry into active, if previous entry did not
+	 * finish, setup current entry's timer again.
+	 */
+	if (list_empty(&vout->queue_list)) {
+		spin_unlock_irqrestore(q->irqlock, flags);
+		return;
+	}
+
+	/* move videobuf from queued list to active list */
+	vb = list_first_entry(&vout->queue_list,
+			struct videobuf_buffer, queue);
+	list_del(&vb->queue);
+	list_add_tail(&vb->queue, &vout->active_list);
+
+	if (queue_work(vout->v4l_wq, &vout->disp_work) == 0) {
+		v4l2_warn(vout->vfd->v4l2_dev,
+			"disp work was in queue already, queue buf again next time\n");
+		list_del(&vb->queue);
+		list_add(&vb->queue, &vout->queue_list);
+		spin_unlock_irqrestore(q->irqlock, flags);
+		return;
+	}
+
+	vb->state = VIDEOBUF_ACTIVE;
+
+	spin_unlock_irqrestore(q->irqlock, flags);
+}
+
+/* Video buffer call backs */
+
+/*
+ * Buffer setup function is called by videobuf layer when REQBUF ioctl is
+ * called. This is used to setup buffers and return size and count of
+ * buffers allocated. After the call to this buffer, videobuf layer will
+ * setup buffer queue depending on the size and count of buffers
+ */
+static int mxc_vout_buffer_setup(struct videobuf_queue *q, unsigned int *count,
+			  unsigned int *size)
+{
+	struct mxc_vout_output *vout = q->priv_data;
+
+	if (!vout)
+		return -EINVAL;
+
+	if (V4L2_BUF_TYPE_VIDEO_OUTPUT != q->type)
+		return -EINVAL;
+
+	*size = PAGE_ALIGN(vout->task.input.width * vout->task.input.height *
+			fmt_to_bpp(vout->task.input.format)/8);
+
+	return 0;
+}
+
+/*
+ * This function will be called when VIDIOC_QBUF ioctl is called.
+ * It prepare buffers before give out for the display. This function
+ * converts user space virtual address into physical address if userptr memory
+ * exchange mechanism is used.
+ */
+static int mxc_vout_buffer_prepare(struct videobuf_queue *q,
+			    struct videobuf_buffer *vb,
+			    enum v4l2_field field)
+{
+	vb->state = VIDEOBUF_PREPARED;
+	return 0;
+}
+
+/*
+ * Buffer queue funtion will be called from the videobuf layer when _QBUF
+ * ioctl is called. It is used to enqueue buffer, which is ready to be
+ * displayed.
+ * This function is protected by q->irqlock.
+ */
+static void mxc_vout_buffer_queue(struct videobuf_queue *q,
+			  struct videobuf_buffer *vb)
+{
+	struct mxc_vout_output *vout = q->priv_data;
+
+	list_add_tail(&vb->queue, &vout->queue_list);
+	vb->state = VIDEOBUF_QUEUED;
+
+	if (vout->timer_stop) {
+		if (deinterlace_3_field(vout) &&
+			list_empty(&vout->active_list)) {
+			vb = list_first_entry(&vout->queue_list,
+					struct videobuf_buffer, queue);
+			list_del(&vb->queue);
+			list_add_tail(&vb->queue, &vout->active_list);
+		} else {
+			setup_buf_timer(vout, vb);
+			vout->timer_stop = false;
+		}
+	}
+}
+
+/*
+ * Buffer release function is called from videobuf layer to release buffer
+ * which are already allocated
+ */
+static void mxc_vout_buffer_release(struct videobuf_queue *q,
+			    struct videobuf_buffer *vb)
+{
+	vb->state = VIDEOBUF_NEEDS_INIT;
+}
+
+static int mxc_vout_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	int ret;
+	struct mxc_vout_output *vout = file->private_data;
+
+	if (!vout)
+		return -ENODEV;
+
+	ret = videobuf_mmap_mapper(&vout->vbq, vma);
+	if (ret < 0)
+		v4l2_err(vout->vfd->v4l2_dev,
+				"offset invalid [offset=0x%lx]\n",
+				(vma->vm_pgoff << PAGE_SHIFT));
+
+	return ret;
+}
+
+static int mxc_vout_release(struct file *file)
+{
+	unsigned int ret = 0;
+	struct videobuf_queue *q;
+	struct mxc_vout_output *vout = file->private_data;
+
+	if (!vout)
+		return 0;
+
+	if (--vout->open_cnt == 0) {
+		q = &vout->vbq;
+		if (q->streaming)
+			mxc_vidioc_streamoff(file, vout, vout->type);
+		else {
+			release_disp_output(vout);
+			videobuf_queue_cancel(q);
+		}
+		destroy_workqueue(vout->v4l_wq);
+		ret = videobuf_mmap_free(q);
+	}
+
+	return ret;
+}
+
+static int mxc_vout_open(struct file *file)
+{
+	struct mxc_vout_output *vout = NULL;
+	int ret;
+
+	vout = video_drvdata(file);
+
+	if (vout == NULL)
+		return -ENODEV;
+
+	if (vout->open_cnt++ == 0) {
+		vout->ctrl_rotate = 0;
+		vout->ctrl_vflip = 0;
+		vout->ctrl_hflip = 0;
+		update_display_setting();
+		ret = update_setting_from_fbi(vout, vout->fbi);
+		if (ret < 0)
+			goto err;
+
+		vout->v4l_wq = create_singlethread_workqueue("v4l2q");
+		if (!vout->v4l_wq) {
+			v4l2_err(vout->vfd->v4l2_dev,
+					"Could not create work queue\n");
+			ret = -ENOMEM;
+			goto err;
+		}
+
+		INIT_WORK(&vout->disp_work, disp_work_func);
+
+		INIT_LIST_HEAD(&vout->queue_list);
+		INIT_LIST_HEAD(&vout->active_list);
+
+		vout->fmt_init = false;
+		vout->frame_count = 0;
+
+		vout->win_pos.x = 0;
+		vout->win_pos.y = 0;
+	}
+
+	file->private_data = vout;
+
+err:
+	return ret;
+}
+
+/*
+ * V4L2 ioctls
+ */
+static int mxc_vidioc_querycap(struct file *file, void *fh,
+		struct v4l2_capability *cap)
+{
+	struct mxc_vout_output *vout = fh;
+
+	strlcpy(cap->driver, VOUT_NAME, sizeof(cap->driver));
+	strlcpy(cap->card, vout->vfd->name, sizeof(cap->card));
+	cap->bus_info[0] = '\0';
+	cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_OUTPUT;
+
+	return 0;
+}
+
+static int mxc_vidioc_enum_fmt_vid_out(struct file *file, void *fh,
+			struct v4l2_fmtdesc *fmt)
+{
+	if (fmt->index >= NUM_MXC_VOUT_FORMATS)
+		return -EINVAL;
+
+	strlcpy(fmt->description, mxc_formats[fmt->index].description,
+			sizeof(fmt->description));
+	fmt->pixelformat = mxc_formats[fmt->index].pixelformat;
+
+	return 0;
+}
+
+static int mxc_vidioc_g_fmt_vid_out(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	struct mxc_vout_output *vout = fh;
+	struct v4l2_rect *rect = NULL;
+
+	f->fmt.pix.width = vout->task.input.width;
+	f->fmt.pix.height = vout->task.input.height;
+	f->fmt.pix.pixelformat = vout->task.input.format;
+	f->fmt.pix.sizeimage = vout->task.input.width * vout->task.input.height *
+			fmt_to_bpp(vout->task.input.format)/8;
+
+	if (f->fmt.pix.priv) {
+		rect = (struct v4l2_rect *)f->fmt.pix.priv;
+		rect->left = vout->task.input.crop.pos.x;
+		rect->top = vout->task.input.crop.pos.y;
+		rect->width = vout->task.input.crop.w;
+		rect->height = vout->task.input.crop.h;
+	}
+
+	return 0;
+}
+
+static inline int ipu_try_task(struct ipu_task *task)
+{
+	int ret;
+
+again:
+	ret = ipu_check_task(task);
+	if (ret != IPU_CHECK_OK) {
+		if (ret > IPU_CHECK_ERR_MIN) {
+			if (ret == IPU_CHECK_ERR_SPLIT_INPUTW_OVER) {
+				task->input.crop.w -= 8;
+				goto again;
+			}
+			if (ret == IPU_CHECK_ERR_SPLIT_INPUTH_OVER) {
+				task->input.crop.h -= 8;
+				goto again;
+			}
+			if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
+				task->output.crop.w -= 8;
+				goto again;
+			}
+			if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
+				task->output.crop.h -= 8;
+				goto again;
+			}
+			ret = -EINVAL;
+		}
+	} else
+		ret = 0;
+
+	return ret;
+}
+
+static int mxc_vout_try_task(struct mxc_vout_output *vout)
+{
+	int ret = 0;
+
+	vout->task.input.crop.w -= vout->task.input.crop.w%8;
+	vout->task.input.crop.h -= vout->task.input.crop.h%8;
+
+	/* assume task.output already set by S_CROP */
+	if (is_pp_bypass(vout)) {
+		v4l2_info(vout->vfd->v4l2_dev, "Bypass IC.\n");
+		vout->bypass_pp = true;
+		vout->task.output.format = vout->task.input.format;
+	} else {
+		/* if need CSC, choose IPU-DP or IPU_IC do it */
+		vout->bypass_pp = false;
+		if (vout->disp_support_csc) {
+			if (colorspaceofpixel(vout->task.input.format) == YUV_CS)
+				vout->task.output.format = IPU_PIX_FMT_UYVY;
+			else
+				vout->task.output.format = IPU_PIX_FMT_RGB565;
+		} else {
+			if (colorspaceofpixel(vout->disp_fmt) == YUV_CS)
+				vout->task.output.format = IPU_PIX_FMT_UYVY;
+			else
+				vout->task.output.format = IPU_PIX_FMT_RGB565;
+		}
+		ret = ipu_try_task(&vout->task);
+	}
+
+	return ret;
+}
+
+static int mxc_vout_try_format(struct mxc_vout_output *vout, struct v4l2_format *f)
+{
+	int ret = 0;
+	struct v4l2_rect *rect = NULL;
+
+	vout->task.input.width = f->fmt.pix.width;
+	vout->task.input.height = f->fmt.pix.height;
+	vout->task.input.format = f->fmt.pix.pixelformat;
+
+	switch (f->fmt.pix.field) {
+	/* Images are in progressive format, not interlaced */
+	case V4L2_FIELD_NONE:
+		break;
+	/* The two fields of a frame are passed in separate buffers,
+	   in temporal order, i. e. the older one first. */
+	case V4L2_FIELD_ALTERNATE:
+		v4l2_err(vout->vfd->v4l2_dev,
+			"V4L2_FIELD_ALTERNATE field format not supported yet!\n");
+		break;
+	case V4L2_FIELD_INTERLACED_TB:
+		v4l2_info(vout->vfd->v4l2_dev, "Enable deinterlace.\n");
+		vout->task.input.deinterlace.enable = true;
+		vout->task.input.deinterlace.field_fmt =
+				IPU_DEINTERLACE_FIELD_TOP;
+		break;
+	case V4L2_FIELD_INTERLACED_BT:
+		v4l2_info(vout->vfd->v4l2_dev, "Enable deinterlace.\n");
+		vout->task.input.deinterlace.enable = true;
+		vout->task.input.deinterlace.field_fmt =
+				IPU_DEINTERLACE_FIELD_BOTTOM;
+		break;
+	default:
+		break;
+	}
+
+	if (f->fmt.pix.priv) {
+		rect = (struct v4l2_rect *)f->fmt.pix.priv;
+		vout->task.input.crop.pos.x = rect->left;
+		vout->task.input.crop.pos.y = rect->top;
+		vout->task.input.crop.w = rect->width;
+		vout->task.input.crop.h = rect->height;
+	} else {
+		vout->task.input.crop.pos.x = 0;
+		vout->task.input.crop.pos.y = 0;
+		vout->task.input.crop.w = f->fmt.pix.width;
+		vout->task.input.crop.h = f->fmt.pix.height;
+	}
+
+	ret = mxc_vout_try_task(vout);
+	if (!ret) {
+		if (rect) {
+			rect->width = vout->task.input.crop.w;
+			rect->height = vout->task.input.crop.h;
+		} else {
+			f->fmt.pix.width = vout->task.input.crop.w;
+			f->fmt.pix.height = vout->task.input.crop.h;
+		}
+	}
+
+	return ret;
+}
+
+static int mxc_vidioc_s_fmt_vid_out(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	struct mxc_vout_output *vout = fh;
+	int ret = 0;
+
+	if (vout->vbq.streaming)
+		return -EBUSY;
+
+	mutex_lock(&vout->task_lock);
+	ret = mxc_vout_try_format(vout, f);
+	if (ret >= 0)
+		vout->fmt_init = true;
+	mutex_unlock(&vout->task_lock);
+
+	return ret;
+}
+
+static int mxc_vidioc_cropcap(struct file *file, void *fh,
+		struct v4l2_cropcap *cropcap)
+{
+	struct mxc_vout_output *vout = fh;
+
+	if (cropcap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+		return -EINVAL;
+
+	cropcap->bounds = vout->crop_bounds;
+	cropcap->defrect = vout->crop_bounds;
+
+	return 0;
+}
+
+static int mxc_vidioc_g_crop(struct file *file, void *fh, struct v4l2_crop *crop)
+{
+	struct mxc_vout_output *vout = fh;
+
+	if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+		return -EINVAL;
+
+	if (vout->disp_support_windows) {
+		crop->c.left = vout->win_pos.x;
+		crop->c.top = vout->win_pos.y;
+		crop->c.width = vout->task.output.width;
+		crop->c.height = vout->task.output.height;
+	} else {
+		if (vout->task.output.crop.w && vout->task.output.crop.h) {
+			crop->c.left = vout->task.output.crop.pos.x;
+			crop->c.top = vout->task.output.crop.pos.y;
+			crop->c.width = vout->task.output.crop.w;
+			crop->c.height = vout->task.output.crop.h;
+		} else {
+			crop->c.left = 0;
+			crop->c.top = 0;
+			crop->c.width = vout->task.output.width;
+			crop->c.height = vout->task.output.height;
+		}
+	}
+
+	return 0;
+}
+
+static int mxc_vidioc_s_crop(struct file *file, void *fh, struct v4l2_crop *crop)
+{
+	struct mxc_vout_output *vout = fh;
+	struct v4l2_rect *b = &vout->crop_bounds;
+	int ret = 0;
+
+	if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+		return -EINVAL;
+
+	if (crop->c.width < 0 || crop->c.height < 0)
+		return -EINVAL;
+
+	if (crop->c.width == 0)
+		crop->c.width = b->width - b->left;
+	if (crop->c.height == 0)
+		crop->c.height = b->height - b->top;
+
+	if (crop->c.top < b->top)
+		crop->c.top = b->top;
+	if (crop->c.top >= b->top + b->height)
+		crop->c.top = b->top + b->height - 1;
+	if (crop->c.height > b->top - crop->c.top + b->height)
+		crop->c.height =
+			b->top - crop->c.top + b->height;
+
+	if (crop->c.left < b->left)
+		crop->c.left = b->left;
+	if (crop->c.left >= b->left + b->width)
+		crop->c.left = b->left + b->width - 1;
+	if (crop->c.width > b->left - crop->c.left + b->width)
+		crop->c.width =
+			b->left - crop->c.left + b->width;
+
+	/* stride line limitation */
+	crop->c.height -= crop->c.height % 8;
+	crop->c.width -= crop->c.width % 8;
+
+	/* the same setting, return */
+	if (vout->disp_support_windows) {
+		if ((vout->win_pos.x == crop->c.left) &&
+			(vout->win_pos.y == crop->c.top) &&
+			(vout->task.output.crop.w == crop->c.width) &&
+			(vout->task.output.crop.h == crop->c.height))
+			return 0;
+	} else {
+		if ((vout->task.output.crop.pos.x == crop->c.left) &&
+			(vout->task.output.crop.pos.y == crop->c.top) &&
+			(vout->task.output.crop.w == crop->c.width) &&
+			(vout->task.output.crop.h == crop->c.height))
+			return 0;
+	}
+
+	/* wait current work finish */
+	if (vout->vbq.streaming)
+		cancel_work_sync(&vout->disp_work);
+
+	mutex_lock(&vout->task_lock);
+
+	if (vout->disp_support_windows) {
+		vout->task.output.crop.pos.x = 0;
+		vout->task.output.crop.pos.y = 0;
+		vout->win_pos.x = crop->c.left;
+		vout->win_pos.y = crop->c.top;
+		vout->task.output.width = crop->c.width;
+		vout->task.output.height = crop->c.height;
+	} else {
+		vout->task.output.crop.pos.x = crop->c.left;
+		vout->task.output.crop.pos.y = crop->c.top;
+	}
+
+	vout->task.output.crop.w = crop->c.width;
+	vout->task.output.crop.h = crop->c.height;
+
+	/*
+	 * must S_CROP before S_FMT, for fist time S_CROP, will not check
+	 * ipu task, it will check in S_FMT, after S_FMT, S_CROP should
+	 * check ipu task too.
+	 */
+	if (vout->fmt_init) {
+		if (vout->vbq.streaming)
+			release_disp_output(vout);
+
+		ret = mxc_vout_try_task(vout);
+		if (ret < 0) {
+			v4l2_err(vout->vfd->v4l2_dev,
+					"vout check task failed\n");
+			goto done;
+		}
+		if (vout->vbq.streaming) {
+			ret = config_disp_output(vout);
+			if (ret < 0) {
+				v4l2_err(vout->vfd->v4l2_dev,
+						"Config display output failed\n");
+				goto done;
+			}
+		}
+	}
+
+done:
+	mutex_unlock(&vout->task_lock);
+
+	return ret;
+}
+
+static int mxc_vidioc_queryctrl(struct file *file, void *fh,
+		struct v4l2_queryctrl *ctrl)
+{
+	int ret = 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_ROTATE:
+		ret = v4l2_ctrl_query_fill(ctrl, 0, 270, 90, 0);
+		break;
+	case V4L2_CID_VFLIP:
+		ret = v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0);
+		break;
+	case V4L2_CID_HFLIP:
+		ret = v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0);
+		break;
+	case V4L2_CID_MXC_MOTION:
+		ret = v4l2_ctrl_query_fill(ctrl, 0, 2, 1, 0);
+		break;
+	default:
+		ctrl->name[0] = '\0';
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+static int mxc_vidioc_g_ctrl(struct file *file, void *fh, struct v4l2_control *ctrl)
+{
+	int ret = 0;
+	struct mxc_vout_output *vout = fh;
+
+	switch (ctrl->id) {
+	case V4L2_CID_ROTATE:
+		ctrl->value = vout->ctrl_rotate;
+		break;
+	case V4L2_CID_VFLIP:
+		ctrl->value = vout->ctrl_vflip;
+		break;
+	case V4L2_CID_HFLIP:
+		ctrl->value = vout->ctrl_hflip;
+		break;
+	case V4L2_CID_MXC_MOTION:
+		if (vout->task.input.deinterlace.enable)
+			ctrl->value = vout->task.input.deinterlace.motion;
+		else
+			ctrl->value = 0;
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+static void setup_task_rotation(struct mxc_vout_output *vout)
+{
+	if (vout->ctrl_rotate == 0) {
+		if (vout->ctrl_vflip && vout->ctrl_hflip)
+			vout->task.output.rotate = IPU_ROTATE_180;
+		else if (vout->ctrl_vflip)
+			vout->task.output.rotate = IPU_ROTATE_VERT_FLIP;
+		else if (vout->ctrl_hflip)
+			vout->task.output.rotate = IPU_ROTATE_HORIZ_FLIP;
+		else
+			vout->task.output.rotate = IPU_ROTATE_NONE;
+	} else if (vout->ctrl_rotate == 90) {
+		if (vout->ctrl_vflip && vout->ctrl_hflip)
+			vout->task.output.rotate = IPU_ROTATE_90_LEFT;
+		else if (vout->ctrl_vflip)
+			vout->task.output.rotate = IPU_ROTATE_90_RIGHT_VFLIP;
+		else if (vout->ctrl_hflip)
+			vout->task.output.rotate = IPU_ROTATE_90_RIGHT_HFLIP;
+		else
+			vout->task.output.rotate = IPU_ROTATE_90_RIGHT;
+	} else if (vout->ctrl_rotate == 180) {
+		if (vout->ctrl_vflip && vout->ctrl_hflip)
+			vout->task.output.rotate = IPU_ROTATE_NONE;
+		else if (vout->ctrl_vflip)
+			vout->task.output.rotate = IPU_ROTATE_HORIZ_FLIP;
+		else if (vout->ctrl_hflip)
+			vout->task.output.rotate = IPU_ROTATE_VERT_FLIP;
+		else
+			vout->task.output.rotate = IPU_ROTATE_180;
+	} else if (vout->ctrl_rotate == 270) {
+		if (vout->ctrl_vflip && vout->ctrl_hflip)
+			vout->task.output.rotate = IPU_ROTATE_90_RIGHT;
+		else if (vout->ctrl_vflip)
+			vout->task.output.rotate = IPU_ROTATE_90_RIGHT_HFLIP;
+		else if (vout->ctrl_hflip)
+			vout->task.output.rotate = IPU_ROTATE_90_RIGHT_VFLIP;
+		else
+			vout->task.output.rotate = IPU_ROTATE_90_LEFT;
+	}
+}
+
+static int mxc_vidioc_s_ctrl(struct file *file, void *fh, struct v4l2_control *ctrl)
+{
+	int ret = 0;
+	struct mxc_vout_output *vout = fh;
+
+	/* wait current work finish */
+	if (vout->vbq.streaming)
+		cancel_work_sync(&vout->disp_work);
+
+	mutex_lock(&vout->task_lock);
+	switch (ctrl->id) {
+	case V4L2_CID_ROTATE:
+	{
+		vout->ctrl_rotate = (ctrl->value/90) * 90;
+		if (vout->ctrl_rotate > 270)
+			vout->ctrl_rotate = 270;
+		setup_task_rotation(vout);
+		break;
+	}
+	case V4L2_CID_VFLIP:
+	{
+		vout->ctrl_vflip = ctrl->value;
+		setup_task_rotation(vout);
+		break;
+	}
+	case V4L2_CID_HFLIP:
+	{
+		vout->ctrl_hflip = ctrl->value;
+		setup_task_rotation(vout);
+		break;
+	}
+	case V4L2_CID_MXC_MOTION:
+	{
+		vout->task.input.deinterlace.motion = ctrl->value;
+		break;
+	}
+	default:
+		ret = -EINVAL;
+		goto done;
+	}
+
+	if (vout->fmt_init) {
+		if (vout->vbq.streaming)
+			release_disp_output(vout);
+
+		ret = mxc_vout_try_task(vout);
+		if (ret < 0) {
+			v4l2_err(vout->vfd->v4l2_dev,
+					"vout check task failed\n");
+			goto done;
+		}
+		if (vout->vbq.streaming) {
+			ret = config_disp_output(vout);
+			if (ret < 0) {
+				v4l2_err(vout->vfd->v4l2_dev,
+						"Config display output failed\n");
+				goto done;
+			}
+		}
+	}
+
+done:
+	mutex_unlock(&vout->task_lock);
+
+	return ret;
+}
+
+static int mxc_vidioc_reqbufs(struct file *file, void *fh,
+			struct v4l2_requestbuffers *req)
+{
+	int ret = 0;
+	struct mxc_vout_output *vout = fh;
+	struct videobuf_queue *q = &vout->vbq;
+
+	if (req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+		return -EINVAL;
+
+	/* should not be here after streaming, videobuf_reqbufs will control */
+	mutex_lock(&vout->task_lock);
+
+	ret = videobuf_reqbufs(q, req);
+
+	mutex_unlock(&vout->task_lock);
+	return ret;
+}
+
+static int mxc_vidioc_querybuf(struct file *file, void *fh,
+			struct v4l2_buffer *b)
+{
+	int ret;
+	struct mxc_vout_output *vout = fh;
+
+	ret = videobuf_querybuf(&vout->vbq, b);
+	if (!ret) {
+		/* return physical address */
+		struct videobuf_buffer *vb = vout->vbq.bufs[b->index];
+		if (b->flags & V4L2_BUF_FLAG_MAPPED)
+			b->m.offset = videobuf_to_dma_contig(vb);
+	}
+
+	return ret;
+}
+
+static int mxc_vidioc_qbuf(struct file *file, void *fh,
+			struct v4l2_buffer *buffer)
+{
+	struct mxc_vout_output *vout = fh;
+
+	return videobuf_qbuf(&vout->vbq, buffer);
+}
+
+static int mxc_vidioc_dqbuf(struct file *file, void *fh, struct v4l2_buffer *b)
+{
+	struct mxc_vout_output *vout = fh;
+
+	if (!vout->vbq.streaming)
+		return -EINVAL;
+
+	if (file->f_flags & O_NONBLOCK)
+		return videobuf_dqbuf(&vout->vbq, (struct v4l2_buffer *)b, 1);
+	else
+		return videobuf_dqbuf(&vout->vbq, (struct v4l2_buffer *)b, 0);
+}
+
+static int set_window_position(struct mxc_vout_output *vout, struct mxcfb_pos *pos)
+{
+	struct fb_info *fbi = vout->fbi;
+	mm_segment_t old_fs;
+	int ret;
+
+	if (vout->disp_support_windows) {
+		old_fs = get_fs();
+		set_fs(KERNEL_DS);
+		ret = fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS,
+				(unsigned long)pos);
+		set_fs(old_fs);
+	}
+
+	return ret;
+}
+
+static int config_disp_output(struct mxc_vout_output *vout)
+{
+	struct fb_info *fbi = vout->fbi;
+	struct fb_var_screeninfo var;
+	int i, display_buf_size, fb_num, ret;
+
+	memcpy(&var, &fbi->var, sizeof(var));
+
+	var.xres = vout->task.output.width;
+	var.yres = vout->task.output.height;
+	if (vout->bypass_pp) {
+		fb_num = 1;
+		/* input crop */
+		if (vout->task.input.width > vout->task.output.width)
+			var.xres_virtual = vout->task.input.width;
+		else
+			var.xres_virtual = var.xres;
+		if (vout->task.input.height > vout->task.output.height)
+			var.yres_virtual = vout->task.input.height;
+		else
+			var.yres_virtual = var.yres;
+		var.rotate = vout->task.output.rotate;
+	} else {
+		fb_num = FB_BUFS;
+		var.xres_virtual = var.xres;
+		var.yres_virtual = fb_num * var.yres;
+	}
+	var.bits_per_pixel = fmt_to_bpp(vout->task.output.format);
+	var.nonstd = vout->task.output.format;
+
+	v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
+			"set display fb to %d %d\n",
+			var.xres, var.yres);
+
+	ret = set_window_position(vout, &vout->win_pos);
+	if (ret < 0)
+		return ret;
+
+	/* Init display channel through fb API */
+	var.yoffset = 0;
+	var.activate |= FB_ACTIVATE_FORCE;
+	console_lock();
+	fbi->flags |= FBINFO_MISC_USEREVENT;
+	ret = fb_set_var(fbi, &var);
+	fbi->flags &= ~FBINFO_MISC_USEREVENT;
+	console_unlock();
+	if (ret < 0)
+		return ret;
+
+	display_buf_size = fbi->fix.line_length * fbi->var.yres;
+	for (i = 0; i < fb_num; i++)
+		vout->disp_bufs[i] = fbi->fix.smem_start + i * display_buf_size;
+
+	console_lock();
+	fbi->flags |= FBINFO_MISC_USEREVENT;
+	ret = fb_blank(fbi, FB_BLANK_UNBLANK);
+	fbi->flags &= ~FBINFO_MISC_USEREVENT;
+	console_unlock();
+
+	return ret;
+}
+
+static void release_disp_output(struct mxc_vout_output *vout)
+{
+	struct fb_info *fbi = vout->fbi;
+	struct mxcfb_pos pos;
+
+	console_lock();
+	fbi->flags |= FBINFO_MISC_USEREVENT;
+	fb_blank(fbi, FB_BLANK_POWERDOWN);
+	fbi->flags &= ~FBINFO_MISC_USEREVENT;
+	console_unlock();
+
+	/* restore pos to 0,0 avoid fb pan display hang? */
+	pos.x = 0;
+	pos.y = 0;
+	set_window_position(vout, &pos);
+
+	/* fix if ic bypass crack smem_start */
+	if (vout->bypass_pp) {
+		console_lock();
+		fbi->fix.smem_start = vout->disp_bufs[0];
+		console_unlock();
+	}
+
+	if (get_ipu_channel(fbi) == MEM_BG_SYNC) {
+		console_lock();
+		fbi->flags |= FBINFO_MISC_USEREVENT;
+		fb_blank(fbi, FB_BLANK_UNBLANK);
+		fbi->flags &= ~FBINFO_MISC_USEREVENT;
+		console_unlock();
+	}
+}
+
+static int mxc_vidioc_streamon(struct file *file, void *fh, enum v4l2_buf_type i)
+{
+	struct mxc_vout_output *vout = fh;
+	struct videobuf_queue *q = &vout->vbq;
+	int ret;
+
+	if (q->streaming) {
+		v4l2_err(vout->vfd->v4l2_dev,
+				"video output already run\n");
+		ret = -EBUSY;
+		goto done;
+	}
+
+	if (deinterlace_3_field(vout) && list_is_singular(&q->stream)) {
+		v4l2_err(vout->vfd->v4l2_dev,
+				"deinterlacing: need queue 2 frame before streamon\n");
+		ret = -EINVAL;
+		goto done;
+	}
+
+	ret = config_disp_output(vout);
+	if (ret < 0) {
+		v4l2_err(vout->vfd->v4l2_dev,
+				"Config display output failed\n");
+		goto done;
+	}
+
+	init_timer(&vout->timer);
+	vout->timer.function = mxc_vout_timer_handler;
+	vout->timer.data = (unsigned long)vout;
+	vout->timer_stop = true;
+
+	vout->start_jiffies = jiffies;
+
+	vout->pre_vb = NULL;
+
+	ret = videobuf_streamon(q);
+done:
+	return ret;
+}
+
+static int mxc_vidioc_streamoff(struct file *file, void *fh, enum v4l2_buf_type i)
+{
+	struct mxc_vout_output *vout = fh;
+	struct videobuf_queue *q = &vout->vbq;
+	int ret = 0;
+
+	if (q->streaming) {
+		cancel_work_sync(&vout->disp_work);
+		flush_workqueue(vout->v4l_wq);
+
+		del_timer_sync(&vout->timer);
+
+		release_disp_output(vout);
+
+		ret = videobuf_streamoff(&vout->vbq);
+	}
+
+	return ret;
+}
+
+static const struct v4l2_ioctl_ops mxc_vout_ioctl_ops = {
+	.vidioc_querycap      			= mxc_vidioc_querycap,
+	.vidioc_enum_fmt_vid_out 		= mxc_vidioc_enum_fmt_vid_out,
+	.vidioc_g_fmt_vid_out			= mxc_vidioc_g_fmt_vid_out,
+	.vidioc_s_fmt_vid_out			= mxc_vidioc_s_fmt_vid_out,
+	.vidioc_cropcap				= mxc_vidioc_cropcap,
+	.vidioc_g_crop				= mxc_vidioc_g_crop,
+	.vidioc_s_crop				= mxc_vidioc_s_crop,
+	.vidioc_queryctrl    			= mxc_vidioc_queryctrl,
+	.vidioc_g_ctrl       			= mxc_vidioc_g_ctrl,
+	.vidioc_s_ctrl       			= mxc_vidioc_s_ctrl,
+	.vidioc_reqbufs				= mxc_vidioc_reqbufs,
+	.vidioc_querybuf			= mxc_vidioc_querybuf,
+	.vidioc_qbuf				= mxc_vidioc_qbuf,
+	.vidioc_dqbuf				= mxc_vidioc_dqbuf,
+	.vidioc_streamon			= mxc_vidioc_streamon,
+	.vidioc_streamoff			= mxc_vidioc_streamoff,
+};
+
+static const struct v4l2_file_operations mxc_vout_fops = {
+	.owner 		= THIS_MODULE,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap 		= mxc_vout_mmap,
+	.open 		= mxc_vout_open,
+	.release 	= mxc_vout_release,
+};
+
+static struct video_device mxc_vout_template = {
+	.name 		= "MXC Video Output",
+	.fops           = &mxc_vout_fops,
+	.ioctl_ops 	= &mxc_vout_ioctl_ops,
+	.release	= video_device_release,
+};
+
+static struct videobuf_queue_ops mxc_vout_vbq_ops = {
+	.buf_setup = mxc_vout_buffer_setup,
+	.buf_prepare = mxc_vout_buffer_prepare,
+	.buf_release = mxc_vout_buffer_release,
+	.buf_queue = mxc_vout_buffer_queue,
+};
+
+static void mxc_vout_free_output(struct mxc_vout_dev *dev)
+{
+	int i;
+	struct mxc_vout_output *vout;
+	struct video_device *vfd;
+
+	for (i = 0; i < dev->out_num; i++) {
+		vout = dev->out[i];
+		vfd = vout->vfd;
+		if (vfd) {
+			if (!video_is_registered(vfd))
+				video_device_release(vfd);
+			else
+				video_unregister_device(vfd);
+		}
+		kfree(vout);
+	}
+}
+
+static int __init mxc_vout_setup_output(struct mxc_vout_dev *dev)
+{
+	struct videobuf_queue *q;
+	struct fb_info *fbi;
+	struct mxc_vout_output *vout;
+	int i, ret = 0;
+
+	update_display_setting();
+
+	/* all output/overlay based on fb */
+	for (i = 0; i < num_registered_fb; i++) {
+		fbi = registered_fb[i];
+
+		vout = kzalloc(sizeof(struct mxc_vout_output), GFP_KERNEL);
+		if (!vout) {
+			ret = -ENOMEM;
+			break;
+		}
+
+		dev->out[dev->out_num] = vout;
+		dev->out_num++;
+
+		vout->fbi = fbi;
+		vout->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
+		vout->vfd = video_device_alloc();
+		if (!vout->vfd) {
+			ret = -ENOMEM;
+			break;
+		}
+
+		*vout->vfd = mxc_vout_template;
+		vout->vfd->debug = debug;
+		vout->vfd->v4l2_dev = &dev->v4l2_dev;
+		vout->vfd->lock = &vout->mutex;
+
+		mutex_init(&vout->mutex);
+		mutex_init(&vout->task_lock);
+
+		strlcpy(vout->vfd->name, fbi->fix.id, sizeof(vout->vfd->name));
+
+		video_set_drvdata(vout->vfd, vout);
+
+		if (video_register_device(vout->vfd,
+			VFL_TYPE_GRABBER, video_nr + i) < 0) {
+			ret = -ENODEV;
+			break;
+		}
+
+		q = &vout->vbq;
+		q->dev = dev->dev;
+		spin_lock_init(&vout->vbq_lock);
+		videobuf_queue_dma_contig_init(q, &mxc_vout_vbq_ops, q->dev,
+				&vout->vbq_lock, vout->type, V4L2_FIELD_NONE,
+				sizeof(struct videobuf_buffer), vout, NULL);
+
+		v4l2_info(vout->vfd->v4l2_dev, "V4L2 device registered as %s\n",
+				video_device_node_name(vout->vfd));
+
+	}
+
+	return ret;
+}
+
+static int __init mxc_vout_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct mxc_vout_dev *dev;
+
+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	dev->dev = &pdev->dev;
+	dev->dev->dma_mask = kmalloc(sizeof(*dev->dev->dma_mask), GFP_KERNEL);
+	*dev->dev->dma_mask = DMA_BIT_MASK(32);
+	dev->dev->coherent_dma_mask = DMA_BIT_MASK(32);
+
+	ret = v4l2_device_register(dev->dev, &dev->v4l2_dev);
+	if (ret) {
+		dev_err(dev->dev, "v4l2_device_register failed\n");
+		goto free_dev;
+	}
+
+	ret = mxc_vout_setup_output(dev);
+	if (ret < 0)
+		goto rel_vdev;
+
+	return 0;
+
+rel_vdev:
+	mxc_vout_free_output(dev);
+	v4l2_device_unregister(&dev->v4l2_dev);
+free_dev:
+	kfree(dev);
+	return ret;
+}
+
+static int mxc_vout_remove(struct platform_device *pdev)
+{
+	struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
+	struct mxc_vout_dev *dev = container_of(v4l2_dev, struct
+			mxc_vout_dev, v4l2_dev);
+
+	mxc_vout_free_output(dev);
+	v4l2_device_unregister(v4l2_dev);
+	kfree(dev);
+	return 0;
+}
+
+static struct platform_driver mxc_vout_driver = {
+	.driver = {
+		.name = "mxc_v4l2_output",
+	},
+	.probe = mxc_vout_probe,
+	.remove = mxc_vout_remove,
+};
+
+static int __init mxc_vout_init(void)
+{
+	if (platform_driver_register(&mxc_vout_driver) != 0) {
+		printk(KERN_ERR VOUT_NAME ":Could not register Video driver\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static void mxc_vout_cleanup(void)
+{
+	platform_driver_unregister(&mxc_vout_driver);
+}
+
+module_init(mxc_vout_init);
+module_exit(mxc_vout_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("V4L2-driver for MXC video output");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/videobuf-core.c b/drivers/media/video/videobuf-core.c
index de4fa4eb884..2149f4dbfba 100644
--- a/drivers/media/video/videobuf-core.c
+++ b/drivers/media/video/videobuf-core.c
@@ -600,6 +600,7 @@ int videobuf_qbuf(struct videobuf_queue *q, struct v4l2_buffer *b)
 		    buf->baddr != b->m.userptr)
 			q->ops->buf_release(q, buf);
 		buf->baddr = b->m.userptr;
+		buf->ts = b->timestamp;
 		break;
 	case V4L2_MEMORY_OVERLAY:
 		buf->boff = b->m.offset;
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index f1391c21ef2..7726c728a7f 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -510,6 +510,43 @@ config PCF50633_GPIO
 	 Say yes here if you want to include support GPIO for pins on
 	 the PCF50633 chip.
 
+config PMIC_DIALOG
+	bool "Support Dialog Semiconductor PMIC"
+	depends on I2C=y
+	depends on SPI=y
+	select MFD_CORE
+	help
+	Support for Dialog semiconductor PMIC chips.
+	Use the options provided to support the desired PMIC's.
+choice
+	prompt "Chip Type"
+	depends on PMIC_DIALOG
+config PMIC_DA9052
+	bool "Support Dialog Semiconductor DA9052 PMIC"
+	help
+	Support for Dialog semiconductor DA9052 PMIC with inbuilt
+	SPI & I2C connectivities.
+	This driver provides common support for accessing  the device,
+	additional drivers must be enabled in order to use the
+	functionality of the device.
+config PMIC_DA9053AA
+	bool "Support Dialog Semiconductor DA9053 AA PMIC"
+	help
+	Support for Dialog semiconductor DA9053 AA PMIC with inbuilt
+	SPI & I2C connectivities.
+	This driver provides common support for accessing  the device,
+	additional drivers must be enabled in order to use the
+	functionality of the device.
+config PMIC_DA9053Bx
+	bool "Support Dialog Semiconductor DA9053 BA/BB PMIC"
+	help
+	Support for Dialog semiconductor DA9053 BA/BB PMIC with inbuilt
+	SPI & I2C connectivities.
+	This driver provides common support for accessing  the device,
+	additional drivers must be enabled in order to use the
+	functionality of the device.
+endchoice
+
 config MFD_MC13783
 	tristate
 
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b2292eb7524..abad5831ac5 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -41,6 +41,8 @@ tps65912-objs                   := tps65912-core.o tps65912-irq.o
 obj-$(CONFIG_MFD_TPS65912)	+= tps65912.o
 obj-$(CONFIG_MFD_TPS65912_I2C)	+= tps65912-i2c.o
 obj-$(CONFIG_MFD_TPS65912_SPI)  += tps65912-spi.o
+da9052-objs			:= da9052-spi.o da9052-i2c.o da9052-core.o
+obj-$(CONFIG_PMIC_DIALOG)	+= da9052.o
 obj-$(CONFIG_MENELAUS)		+= menelaus.o
 
 obj-$(CONFIG_TWL4030_CORE)	+= twl-core.o twl4030-irq.o twl6030-irq.o
diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c
new file mode 100644
index 00000000000..82699cd64da
--- /dev/null
+++ b/drivers/mfd/da9052-core.c
@@ -0,0 +1,555 @@
+/*
+ * da9052-core.c  --  Device access for Dialog DA9052
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * Author: Dialog Semiconductor Ltd <dchen@diasemi.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/irq.h>
+#include <linux/list.h>
+#include <linux/mfd/core.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c.h>
+#include <linux/semaphore.h>
+
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/adc.h>
+
+#define SUCCESS		0
+#define FAILURE		1
+
+struct da9052_eh_nb eve_nb_array[EVE_CNT];
+static struct da9052_ssc_ops ssc_ops;
+struct mutex manconv_lock;
+static struct semaphore eve_nb_array_lock;
+static struct da9052 *da9052_data;
+
+void da9052_lock(struct da9052 *da9052)
+{
+	mutex_lock(&da9052->ssc_lock);
+}
+EXPORT_SYMBOL(da9052_lock);
+
+void da9052_unlock(struct da9052 *da9052)
+{
+	mutex_unlock(&da9052->ssc_lock);
+}
+EXPORT_SYMBOL(da9052_unlock);
+
+int da9052_ssc_write(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg)
+{
+	int ret = 0;
+
+	/* Reg address should be a valid address on PAGE0 or PAGE1 */
+	if ((sscmsg->addr < DA9052_PAGE0_REG_START) ||
+	(sscmsg->addr > DA9052_PAGE1_REG_END) ||
+	((sscmsg->addr > DA9052_PAGE0_REG_END) &&
+	(sscmsg->addr < DA9052_PAGE1_REG_START)))
+		return INVALID_REGISTER;
+
+	ret = ssc_ops.write(da9052, sscmsg);
+
+	/* Update local cache if required */
+	if (!ret) {
+		/* Check if this register is Non-volatile*/
+		if (da9052->ssc_cache[sscmsg->addr].type != VOLATILE) {
+			/* Update value */
+			da9052->ssc_cache[sscmsg->addr].val = sscmsg->data;
+			/* Make this cache entry valid */
+			da9052->ssc_cache[sscmsg->addr].status = VALID;
+		}
+	}
+
+	return ret;
+}
+
+int da9052_ssc_read(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg)
+{
+	int ret = 0;
+
+	/* Reg addr should be a valid address on PAGE0 or PAGE1 */
+	if ((sscmsg->addr < DA9052_PAGE0_REG_START) ||
+	(sscmsg->addr > DA9052_PAGE1_REG_END) ||
+	((sscmsg->addr > DA9052_PAGE0_REG_END) &&
+	(sscmsg->addr < DA9052_PAGE1_REG_START)))
+		return INVALID_REGISTER;
+
+	/*
+	 * Check if this is a Non-volatile register, if yes then return value -
+	 * from cache instead of actual reading from hardware. Before reading -
+	 * cache entry, make sure that the entry is valid
+	 */
+	/* The read request is for Non-volatile register */
+	/* Check if we have valid cached value for this */
+	if (da9052->ssc_cache[sscmsg->addr].status == VALID) {
+		/* We have valid cached value, copy this value */
+		sscmsg->data = da9052->ssc_cache[sscmsg->addr].val;
+
+		return 0;
+	}
+
+	ret = ssc_ops.read(da9052, sscmsg);
+
+	/* Update local cache if required */
+	if (!ret) {
+		/* Check if this register is Non-volatile*/
+		if (da9052->ssc_cache[sscmsg->addr].type != VOLATILE) {
+			/* Update value */
+			da9052->ssc_cache[sscmsg->addr].val = sscmsg->data;
+			/* Make this cache entry valid */
+			da9052->ssc_cache[sscmsg->addr].status = VALID;
+		}
+	}
+
+	return ret;
+}
+
+int da9052_ssc_write_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg,
+				int msg_no)
+{
+	int ret = 0;
+	int cnt = 0;
+
+	/* Check request size */
+	if (msg_no > MAX_READ_WRITE_CNT)
+		return -EIO;
+
+	ret = ssc_ops.write_many(da9052, sscmsg, msg_no);
+	/* Update local cache, if required */
+	for (cnt = 0; cnt < msg_no; cnt++) {
+		/* Check if this register is Non-volatile*/
+		if (da9052->ssc_cache[sscmsg[cnt].addr].type != VOLATILE) {
+			/* Update value */
+			da9052->ssc_cache[sscmsg[cnt].addr].val =
+			sscmsg[cnt].data;
+			/* Make this cache entry valid */
+			da9052->ssc_cache[sscmsg[cnt].addr].status = VALID;
+		}
+	}
+	return ret;
+}
+
+int da9052_ssc_read_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg,
+			int msg_no)
+{
+	int ret = 0;
+	int cnt = 0;
+
+	/* Check request size */
+	if (msg_no > MAX_READ_WRITE_CNT)
+		return -EIO;
+
+	ret = ssc_ops.read_many(da9052, sscmsg, msg_no);
+	/* Update local cache, if required */
+	for (cnt = 0; cnt < msg_no; cnt++) {
+		/* Check if this register is Non-volatile*/
+		if (da9052->ssc_cache[sscmsg[cnt].addr].type
+			!= VOLATILE) {
+			/* Update value */
+			da9052->ssc_cache[sscmsg[cnt].addr].val =
+			sscmsg[cnt].data;
+			/* Make this cache entry valid */
+			da9052->ssc_cache[sscmsg[cnt].addr].status = VALID;
+		}
+	}
+	return ret;
+}
+
+static irqreturn_t da9052_eh_isr(int irq, void *dev_id)
+{
+	struct da9052 *da9052 = dev_id;
+	/* Schedule work to be done */
+	schedule_work(&da9052->eh_isr_work);
+	/* Disable IRQ */
+	disable_irq_nosync(da9052->irq);
+	return IRQ_HANDLED;
+}
+
+int eh_register_nb(struct da9052 *da9052, struct da9052_eh_nb *nb)
+{
+
+	if (nb == NULL) {
+		printk(KERN_INFO "EH REGISTER FUNCTION FAILED\n");
+		return -EINVAL;
+	}
+
+	if (nb->eve_type >= EVE_CNT) {
+		printk(KERN_INFO "Invalid DA9052 Event Type\n");
+		return -EINVAL;
+	}
+
+	/* Initialize list head inside notifier block */
+	INIT_LIST_HEAD(&nb->nb_list);
+
+	/* Acquire NB array lock */
+	if (down_interruptible(&eve_nb_array_lock))
+		return -EAGAIN;
+
+	/* Add passed NB to corresponding EVENT list */
+	list_add_tail(&nb->nb_list, &(eve_nb_array[nb->eve_type].nb_list));
+
+	/* Release NB array lock */
+	up(&eve_nb_array_lock);
+
+	return 0;
+}
+
+int eh_unregister_nb(struct da9052 *da9052, struct da9052_eh_nb *nb)
+{
+
+	if (nb == NULL)
+		return -EINVAL;
+
+	/* Acquire nb array lock */
+	if (down_interruptible(&eve_nb_array_lock))
+		return -EAGAIN;
+
+	/* Remove passed NB from list */
+	list_del_init(&(nb->nb_list));
+
+	/* Release NB array lock */
+	up(&eve_nb_array_lock);
+
+	return 0;
+}
+
+static int process_events(struct da9052 *da9052, int events_sts)
+{
+
+	int cnt = 0;
+	int tmp_events_sts = 0;
+	unsigned char event = 0;
+
+	struct list_head *ptr;
+	struct da9052_eh_nb *nb_ptr;
+
+	/* Now we have retrieved all events, process them one by one */
+	for (cnt = 0; cnt < EVE_CNT; cnt++) {
+		/*
+		 * Starting with highest priority event,
+		 * traverse through all event
+		 */
+		tmp_events_sts = events_sts;
+
+		/* Find the event associated with higher priority */
+		event = cnt;
+
+		/* Check if interrupt is received for this event */
+		if (!((tmp_events_sts >> cnt) & 0x1))
+			/* Event bit is not set for this event */
+			/* Move to next event */
+			continue;
+
+		if (event == PEN_DOWN_EVE) {
+			if (list_empty(&(eve_nb_array[event].nb_list)))
+				continue;
+		}
+
+		/* Event bit is set, execute all registered call backs */
+		if (down_interruptible(&eve_nb_array_lock)) {
+			printk(KERN_CRIT "Can't acquire eve_nb_array_lock\n");
+			return -EIO;
+		}
+
+		list_for_each(ptr, &(eve_nb_array[event].nb_list)) {
+			/*
+			 * nb_ptr will point to the structure in which
+			 * nb_list is embedded
+			 */
+			nb_ptr = list_entry(ptr, struct da9052_eh_nb, nb_list);
+			nb_ptr->call_back(nb_ptr, events_sts);
+		}
+		up(&eve_nb_array_lock);
+	}
+	return 0;
+}
+
+void eh_workqueue_isr(struct work_struct *work)
+{
+	struct da9052 *da9052 =
+		container_of(work, struct da9052, eh_isr_work);
+
+	struct da9052_ssc_msg eve_data[4];
+	struct da9052_ssc_msg eve_mask_data[4];
+	int events_sts, ret;
+	u32 mask;
+	unsigned char cnt = 0;
+
+	/* nIRQ is asserted, read event registeres to know what happened */
+	events_sts = 0;
+	mask = 0;
+
+	/* Prepare ssc message to read all four event registers */
+	for (cnt = 0; cnt < DA9052_EVE_REGISTERS; cnt++) {
+		eve_data[cnt].addr = (DA9052_EVENTA_REG + cnt);
+		eve_data[cnt].data = 0;
+	}
+
+	/* Prepare ssc message to read all four event registers */
+	for (cnt = 0; cnt < DA9052_EVE_REGISTERS; cnt++) {
+		eve_mask_data[cnt].addr = (DA9052_IRQMASKA_REG + cnt);
+		eve_mask_data[cnt].data = 0;
+	}
+
+	/* Now read all event and mask registers */
+	da9052_lock(da9052);
+
+	ret = da9052_ssc_read_many(da9052, eve_data, DA9052_EVE_REGISTERS);
+	if (ret) {
+		enable_irq(da9052->irq);
+		da9052_unlock(da9052);
+		return;
+	}
+
+	ret = da9052_ssc_read_many(da9052, eve_mask_data, DA9052_EVE_REGISTERS);
+	if (ret) {
+		enable_irq(da9052->irq);
+		da9052_unlock(da9052);
+		return;
+	}
+	/* Collect all events */
+	for (cnt = 0; cnt < DA9052_EVE_REGISTERS; cnt++)
+		events_sts |= (eve_data[cnt].data << (DA9052_EVE_REGISTER_SIZE
+							* cnt));
+	/* Collect all mask */
+	for (cnt = 0; cnt < DA9052_EVE_REGISTERS; cnt++)
+		mask |= (eve_mask_data[cnt].data << (DA9052_EVE_REGISTER_SIZE
+						* cnt));
+	events_sts &= ~mask;
+	da9052_unlock(da9052);
+
+	/* Check if we really got any event */
+	if (events_sts == 0) {
+		enable_irq(da9052->irq);
+		da9052_unlock(da9052);
+		return;
+	}
+
+	/* Process all events occurred */
+	process_events(da9052, events_sts);
+
+	da9052_lock(da9052);
+	/* Now clear EVENT registers */
+	for (cnt = 0; cnt < 4; cnt++) {
+		if (eve_data[cnt].data) {
+			ret = da9052_ssc_write(da9052, &eve_data[cnt]);
+			if (ret) {
+				enable_irq(da9052->irq);
+				da9052_unlock(da9052);
+				return;
+			}
+		}
+	}
+	da9052_unlock(da9052);
+
+	/*
+	* This delay is necessary to avoid hardware fake interrupts
+	* from DA9052.
+	*/
+#if defined  CONFIG_PMIC_DA9052 || defined  CONFIG_PMIC_DA9053AA
+	udelay(50);
+#endif
+	/* Enable HOST interrupt */
+	enable_irq(da9052->irq);
+}
+
+static void da9052_eh_restore_irq(struct da9052 *da9052)
+{
+	/* Put your platform and board specific code here */
+	free_irq(da9052->irq, NULL);
+}
+
+static int da9052_add_subdevice_pdata(struct da9052 *da9052,
+		const char *name, void *pdata, size_t pdata_size)
+{
+	struct mfd_cell cell = {
+		.name = name,
+		.platform_data = pdata,
+		.pdata_size = pdata_size,
+	};
+	return mfd_add_devices(da9052->dev, -1, &cell, 1, NULL, 0);
+}
+
+static int da9052_add_subdevice(struct da9052 *da9052, const char *name)
+{
+	return da9052_add_subdevice_pdata(da9052, name, NULL, 0);
+}
+
+static int add_da9052_devices(struct da9052 *da9052)
+{
+	s32 ret = 0;
+	struct da9052_platform_data *pdata = da9052->dev->platform_data;
+	struct da9052_leds_platform_data leds_data = {
+			.num_leds = pdata->led_data->num_leds,
+			.led = pdata->led_data->led,
+	};
+	struct da9052_regulator_platform_data regulator_pdata = {
+		.regulators = pdata->regulators,
+	};
+
+	struct da9052_tsi_platform_data tsi_data = *(pdata->tsi_data);
+
+	if (pdata && pdata->init) {
+		ret = pdata->init(da9052);
+		if (ret != 0)
+			return ret;
+	} else
+		pr_err("No platform initialisation supplied\n");
+
+	ret = da9052_add_subdevice(da9052, "da9052-rtc");
+	if (ret)
+		return ret;
+	ret = da9052_add_subdevice(da9052, "da9052-onkey");
+	if (ret)
+		return ret;
+
+	ret = da9052_add_subdevice(da9052, "WLED-1");
+	if (ret)
+		return ret;
+
+	ret = da9052_add_subdevice(da9052, "WLED-2");
+	if (ret)
+		return ret;
+
+	ret = da9052_add_subdevice(da9052, "WLED-3");
+	if (ret)
+		return ret;
+
+	ret = da9052_add_subdevice(da9052, "da9052-adc");
+	if (ret)
+		return ret;
+
+	ret = da9052_add_subdevice(da9052, "da9052-wdt");
+	if (ret)
+		return ret;
+
+	ret = da9052_add_subdevice_pdata(da9052, "da9052-leds",
+				&leds_data, sizeof(leds_data));
+	if (ret)
+		return ret;
+
+	ret = da9052_add_subdevice_pdata(da9052, "da9052-regulator",
+		&regulator_pdata, sizeof(regulator_pdata));
+	if (ret)
+		return ret;
+
+	ret = da9052_add_subdevice_pdata(da9052, "da9052-tsi",
+				&tsi_data, sizeof(tsi_data));
+	if (ret)
+		return ret;
+
+	ret = da9052_add_subdevice(da9052, "da9052-bat");
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+int da9052_ssc_init(struct da9052 *da9052)
+{
+	int cnt;
+	struct da9052_platform_data *pdata;
+	struct da9052_ssc_msg ssc_msg;
+
+	/* Initialize eve_nb_array */
+	for (cnt = 0; cnt < EVE_CNT; cnt++)
+		INIT_LIST_HEAD(&(eve_nb_array[cnt].nb_list));
+
+	/* Initialize mutex required for ADC Manual read */
+	mutex_init(&manconv_lock);
+
+	/* Initialize NB array lock */
+	sema_init(&eve_nb_array_lock, 1);
+
+	/* Assign the read-write function pointers */
+	da9052->read = da9052_ssc_read;
+	da9052->write = da9052_ssc_write;
+	da9052->read_many = da9052_ssc_read_many;
+	da9052->write_many = da9052_ssc_write_many;
+
+	if (SPI  == da9052->connecting_device && ssc_ops.write == NULL) {
+		/* Assign the read/write pointers to SPI/read/write */
+		ssc_ops.write = da9052_spi_write;
+		ssc_ops.read = da9052_spi_read;
+		ssc_ops.write_many = da9052_spi_write_many;
+		ssc_ops.read_many = da9052_spi_read_many;
+	} else if (I2C  == da9052->connecting_device
+		   && ssc_ops.write == NULL) {
+		/* Assign the read/write pointers to SPI/read/write */
+		ssc_ops.write = da9052_i2c_write;
+		ssc_ops.read = da9052_i2c_read;
+		ssc_ops.write_many = da9052_i2c_write_many;
+		ssc_ops.read_many = da9052_i2c_read_many;
+	} else
+		return -1;
+	/* Assign the EH notifier block register/de-register functions */
+	da9052->register_event_notifier = eh_register_nb;
+	da9052->unregister_event_notifier = eh_unregister_nb;
+
+	/* Initialize ssc lock */
+	mutex_init(&da9052->ssc_lock);
+
+	pdata = da9052->dev->platform_data;
+	add_da9052_devices(da9052);
+
+	INIT_WORK(&da9052->eh_isr_work, eh_workqueue_isr);
+	ssc_msg.addr = DA9052_IRQMASKA_REG;
+	ssc_msg.data = 0xff;
+	da9052->write(da9052, &ssc_msg);
+	ssc_msg.addr = DA9052_IRQMASKC_REG;
+	ssc_msg.data = 0xff;
+	da9052->write(da9052, &ssc_msg);
+	if (request_irq(da9052->irq, da9052_eh_isr, IRQ_TYPE_LEVEL_LOW,
+		DA9052_EH_DEVICE_NAME, da9052))
+		return -EIO;
+	enable_irq_wake(da9052->irq);
+	da9052_data = da9052;
+
+	return 0;
+}
+
+void da9052_ssc_exit(struct da9052 *da9052)
+{
+	printk(KERN_INFO "DA9052: Unregistering SSC device.\n");
+	mutex_destroy(&manconv_lock);
+	/* Restore IRQ line */
+	da9052_eh_restore_irq(da9052);
+	free_irq(da9052->irq, NULL);
+	mutex_destroy(&da9052->ssc_lock);
+	mutex_destroy(&da9052->eve_nb_lock);
+	return;
+}
+
+void da9053_power_off(void)
+{
+  struct da9052_ssc_msg ssc_msg;
+  if (!da9052_data)
+    return;
+
+  ssc_msg.addr = DA9052_CONTROLB_REG;
+  da9052_data->read(da9052_data, &ssc_msg);
+  ssc_msg.data |= DA9052_CONTROLB_SHUTDOWN;
+  pr_info("da9052 shutdown: DA9052_CONTROLB_REG=%x\n", ssc_msg.data);
+  da9052_data->write(da9052_data, &ssc_msg);
+  ssc_msg.addr = DA9052_GPID9_REG;
+  ssc_msg.data = 0;
+  da9052_data->read(da9052_data, &ssc_msg);
+}
+
+MODULE_AUTHOR("Dialog Semiconductor Ltd <dchen@diasemi.com>");
+MODULE_DESCRIPTION("DA9052 MFD Core");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DA9052_SSC_DEVICE_NAME);
diff --git a/drivers/mfd/da9052-i2c.c b/drivers/mfd/da9052-i2c.c
new file mode 100644
index 00000000000..dba23f16188
--- /dev/null
+++ b/drivers/mfd/da9052-i2c.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * da9052-i2c.c: I2C SSC (Synchronous Serial Communication) driver for DA9052
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/mfd/core.h>
+#include <linux/i2c.h>
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/reg.h>
+
+static struct da9052 *da9052_i2c;
+
+#define I2C_CONNECTED 0
+
+static int da9052_i2c_is_connected(void)
+{
+
+	struct da9052_ssc_msg msg;
+
+	/* printk("Entered da9052_i2c_is_connected.............\n"); */
+
+	msg.addr = DA9052_INTERFACE_REG;
+
+	/* Test spi connectivity by performing read of the GPIO_0-1 register */
+	if (0 != da9052_i2c_read(da9052_i2c, &msg)) {
+		printk(KERN_DEBUG "da9052_i2c_is_connected - "\
+		       "i2c read failed.............\n");
+		return -1;
+	} else {
+		printk(KERN_DEBUG "da9052_i2c_is_connected - "\
+		       "i2c read success..............\n");
+		return 0;
+	}
+
+}
+
+static int __devinit da9052_i2c_probe(struct i2c_client *client,
+	const struct i2c_device_id *id)
+{
+	struct i2c_adapter *adapter;
+	/* printk("\n\tEntered da9052_i2c_is_probe.............\n"); */
+
+	da9052_i2c = kzalloc(sizeof(struct da9052), GFP_KERNEL);
+
+	if (!da9052_i2c)
+		return -ENOMEM;
+
+	/* Get the bus driver handler */
+	adapter = to_i2c_adapter(client->dev.parent);
+
+	/* Check i2c bus driver supports byte data transfer */
+	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
+		dev_info(&client->dev,\
+		"Error in %s:i2c_check_functionality\n", __func__);
+		return -ENODEV;
+	}
+
+	/* Store handle to i2c client */
+	da9052_i2c->i2c_client = client;
+	da9052_i2c->irq = client->irq;
+
+	da9052_i2c->dev = &client->dev;
+
+	/* Initialize i2c data structure here*/
+	da9052_i2c->adapter = adapter;
+
+	/* host i2c driver looks only first 7 bits for the slave address */
+	da9052_i2c->slave_addr = DA9052_I2C_ADDR >> 1;
+
+	/* Store the i2c client data */
+	i2c_set_clientdata(client, da9052_i2c);
+
+	/* Validate I2C connectivity */
+	if (I2C_CONNECTED  == da9052_i2c_is_connected()) {
+		/* I2C is connected */
+		da9052_i2c->connecting_device = I2C;
+		if (0 != da9052_ssc_init(da9052_i2c))
+			return -ENODEV;
+	} else {
+		return -ENODEV;
+	}
+
+	/* printk("Exiting da9052_i2c_probe.....\n"); */
+
+	return 0;
+}
+
+static int da9052_i2c_remove(struct i2c_client *client)
+{
+
+	struct da9052 *da9052 = i2c_get_clientdata(client);
+
+	mfd_remove_devices(da9052->dev);
+	kfree(da9052);
+	return 0;
+}
+
+int da9052_i2c_write(struct da9052 *da9052, struct da9052_ssc_msg *msg)
+{
+	struct i2c_msg i2cmsg;
+	unsigned char buf[2] = {0};
+	int ret = 0;
+
+	/* Copy the ssc msg to local character buffer */
+	buf[0] = msg->addr;
+	buf[1] = msg->data;
+
+	/*Construct a i2c msg for a da9052 driver ssc message request */
+	i2cmsg.addr  = da9052->slave_addr;
+	i2cmsg.len   = 2;
+	i2cmsg.buf   = buf;
+
+	/* To write the data on I2C set flag to zero */
+	i2cmsg.flags = 0;
+
+	/* Start the i2c transfer by calling host i2c driver function */
+	ret = i2c_transfer(da9052->adapter, &i2cmsg, 1);
+
+	if (ret < 0) {
+		dev_info(&da9052->i2c_client->dev,\
+		"_%s:master_xfer Failed!!\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+int da9052_i2c_read(struct da9052 *da9052, struct da9052_ssc_msg *msg)
+{
+
+	/*Get the da9052_i2c client details*/
+	unsigned char buf[2] = {0, 0};
+	struct i2c_msg i2cmsg[2];
+	int ret = 0;
+
+	/* Copy SSC Msg to local character buffer */
+	buf[0] = msg->addr;
+
+	/*Construct a i2c msg for a da9052 driver ssc message request */
+	i2cmsg[0].addr  = da9052->slave_addr ;
+	i2cmsg[0].len   = 1;
+	i2cmsg[0].buf   = &buf[0];
+
+	/*To write the data on I2C set flag to zero */
+	i2cmsg[0].flags = 0;
+
+	/* Read the data from da9052*/
+	/*Construct a i2c msg for a da9052 driver ssc message request */
+	i2cmsg[1].addr  = da9052->slave_addr ;
+	i2cmsg[1].len   = 1;
+	i2cmsg[1].buf   = &buf[1];
+
+	/*To read the data on I2C set flag to I2C_M_RD */
+	i2cmsg[1].flags = I2C_M_RD;
+
+	/* Start the i2c transfer by calling host i2c driver function */
+	ret = i2c_transfer(da9052->adapter, i2cmsg, 2);
+	if (ret < 0) {
+		dev_info(&da9052->i2c_client->dev,\
+		"2 - %s:master_xfer Failed!!\n", __func__);
+		return ret;
+	}
+
+	msg->data = *i2cmsg[1].buf;
+
+	return 0;
+}
+
+int da9052_i2c_write_many(struct da9052 *da9052,
+	struct da9052_ssc_msg *sscmsg, int msg_no)
+{
+
+	struct i2c_msg i2cmsg;
+	unsigned char data_buf[MAX_READ_WRITE_CNT+1];
+	struct da9052_ssc_msg ctrlb_msg;
+	struct da9052_ssc_msg *msg_queue = sscmsg;
+	int ret = 0;
+	/* Flag to check if requested registers are contiguous */
+	unsigned char cont_data = 1;
+	unsigned char cnt = 0;
+
+	/* Check if requested registers are contiguous */
+	for (cnt = 1; cnt < msg_no; cnt++) {
+		if ((msg_queue[cnt].addr - msg_queue[cnt-1].addr) != 1) {
+			/* Difference is not 1, i.e. non-contiguous registers */
+			cont_data = 0;
+			break;
+		}
+	}
+
+	if (cont_data == 0) {
+		/* Requested registers are non-contiguous */
+		for (cnt = 0; cnt < msg_no; cnt++) {
+			ret = da9052->write(da9052, &msg_queue[cnt]);
+			if (ret != 0)
+				return ret;
+		}
+		return 0;
+	}
+	/*
+	*  Requested registers are contiguous
+	* or PAGE WRITE sequence of I2C transactions is as below
+	* (slave_addr + reg_addr + data_1 + data_2 + ...)
+	* First read current WRITE MODE via CONTROL_B register of DA9052
+	*/
+	ctrlb_msg.addr = DA9052_CONTROLB_REG;
+	ctrlb_msg.data = 0x0;
+	ret = da9052->read(da9052, &ctrlb_msg);
+
+	if (ret != 0)
+		return ret;
+
+	/* Check if PAGE WRITE mode is set */
+	if (ctrlb_msg.data & DA9052_CONTROLB_WRITEMODE) {
+		/* REPEAT WRITE mode is configured */
+		/* Now set DA9052 into PAGE WRITE mode */
+		ctrlb_msg.data &= ~DA9052_CONTROLB_WRITEMODE;
+		ret = da9052->write(da9052, &ctrlb_msg);
+
+		if (ret != 0)
+			return ret;
+	}
+
+	 /* Put first register address */
+	data_buf[0] = msg_queue[0].addr;
+
+	for (cnt = 0; cnt < msg_no; cnt++)
+		data_buf[cnt+1] = msg_queue[cnt].data;
+
+	/* Construct a i2c msg for PAGE WRITE */
+	i2cmsg.addr  = da9052->slave_addr ;
+	/* First register address + all data*/
+	i2cmsg.len   = (msg_no + 1);
+	i2cmsg.buf   = data_buf;
+
+	/*To write the data on I2C set flag to zero */
+	i2cmsg.flags = 0;
+
+	/* Start the i2c transfer by calling host i2c driver function */
+	ret = i2c_transfer(da9052->adapter, &i2cmsg, 1);
+	if (ret < 0) {
+		dev_info(&da9052->i2c_client->dev,\
+		"1 - i2c_transfer function falied in [%s]!!!\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+int da9052_i2c_read_many(struct da9052 *da9052,
+	struct da9052_ssc_msg *sscmsg, int msg_no)
+{
+
+	struct i2c_msg i2cmsg;
+	unsigned char data_buf[MAX_READ_WRITE_CNT];
+	struct da9052_ssc_msg *msg_queue = sscmsg;
+	int ret = 0;
+	/* Flag to check if requested registers are contiguous */
+	unsigned char cont_data = 1;
+	unsigned char cnt = 0;
+
+	/* Check if requested registers are contiguous */
+	for (cnt = 1; cnt < msg_no; cnt++) {
+		if ((msg_queue[cnt].addr - msg_queue[cnt-1].addr) != 1) {
+			/* Difference is not 1, i.e. non-contiguous registers */
+			cont_data = 0;
+			break;
+		}
+	}
+
+	if (cont_data == 0) {
+		/* Requested registers are non-contiguous */
+		for (cnt = 0; cnt < msg_no; cnt++) {
+			ret = da9052->read(da9052, &msg_queue[cnt]);
+			if (ret != 0) {
+				dev_info(&da9052->i2c_client->dev,\
+				"Error in %s", __func__);
+				return ret;
+			}
+		}
+		return 0;
+	}
+
+	/*
+	* We want to perform PAGE READ via I2C
+	* For PAGE READ sequence of I2C transactions is as below
+	* (slave_addr + reg_addr) + (slave_addr + data_1 + data_2 + ...)
+	*/
+	/* Copy address of first register */
+	data_buf[0] = msg_queue[0].addr;
+
+	/* Construct a i2c msg for first transaction of PAGE READ i.e. write */
+	i2cmsg.addr  = da9052->slave_addr ;
+	i2cmsg.len   = 1;
+	i2cmsg.buf   = data_buf;
+
+	/*To write the data on I2C set flag to zero */
+	i2cmsg.flags = 0;
+
+	/* Start the i2c transfer by calling host i2c driver function */
+	ret = i2c_transfer(da9052->adapter, &i2cmsg, 1);
+	if (ret < 0) {
+		dev_info(&da9052->i2c_client->dev,\
+		"1 - i2c_transfer function falied in [%s]!!!\n", __func__);
+		return ret;
+	}
+
+	/* Now Read the data from da9052 */
+	/* Construct a i2c msg for second transaction of PAGE READ i.e. read */
+	i2cmsg.addr  = da9052->slave_addr ;
+	i2cmsg.len   = msg_no;
+	i2cmsg.buf   = data_buf;
+
+	/*To read the data on I2C set flag to I2C_M_RD */
+	i2cmsg.flags = I2C_M_RD;
+
+	/* Start the i2c transfer by calling host i2c driver function */
+	ret = i2c_transfer(da9052->adapter,
+		&i2cmsg, 1);
+	if (ret < 0) {
+		dev_info(&da9052->i2c_client->dev,\
+		"2 - i2c_transfer function falied in [%s]!!!\n", __func__);
+		return ret;
+	}
+
+	/* Gather READ data */
+	for (cnt = 0; cnt < msg_no; cnt++)
+		sscmsg[cnt].data = data_buf[cnt];
+
+	return 0;
+}
+
+static struct i2c_device_id da9052_ssc_id[] = {
+	{ DA9052_SSC_I2C_DEVICE_NAME, 0},
+	{}
+};
+
+static struct i2c_driver da9052_i2c_driver =  {
+	.driver = {
+		.name	= DA9052_SSC_I2C_DEVICE_NAME,
+		.owner	= THIS_MODULE,
+	},
+	.probe	= da9052_i2c_probe,
+	.remove	= da9052_i2c_remove,
+	.id_table	= da9052_ssc_id,
+};
+
+static int __init da9052_i2c_init(void)
+{
+	int ret = 0;
+	/* printk("\n\nEntered da9052_i2c_init................\n\n"); */
+	ret = i2c_add_driver(&da9052_i2c_driver);
+	if (ret != 0) {
+		printk(KERN_ERR "Unable to register %s\n",
+		       DA9052_SSC_I2C_DEVICE_NAME);
+		return ret;
+	}
+	return 0;
+}
+subsys_initcall(da9052_i2c_init);
+
+static void  __exit da9052_i2c_exit(void)
+{
+	i2c_del_driver(&da9052_i2c_driver);
+}
+module_exit(da9052_i2c_exit);
+
+MODULE_AUTHOR("Dialog Semiconductor Ltd <dchen@diasemi.com>");
+MODULE_DESCRIPTION("I2C driver for Dialog DA9052 PMIC");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DA9052_SSC_I2C_DEVICE_NAME);
diff --git a/drivers/mfd/da9052-spi.c b/drivers/mfd/da9052-spi.c
new file mode 100644
index 00000000000..9769811c643
--- /dev/null
+++ b/drivers/mfd/da9052-spi.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * da9052-spi.c: SPI SSC (Synchronous Serial Communication) driver for DA9052
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/mfd/core.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/reg.h>
+
+
+struct da9052 *da9052_spi;
+
+#define SPI_CONNECTED 0
+
+static int da9052_spi_is_connected(void)
+{
+
+	struct da9052_ssc_msg msg;
+
+	/* printk("Entered da9052_spi_is_connected.............\n"); */
+
+	msg.addr = DA9052_INTERFACE_REG;
+
+	/* Test spi connectivity by performing read of the GPIO_0-1 register
+	   and then verify the read value*/
+	if (0 != da9052_spi_read(da9052_spi, &msg)) {
+		printk(KERN_DEBUG "da9052_spi_is_connected - "\
+		       "spi read failed.............\n");
+		return -1;
+	} else if (0x88 != msg.data) {
+		printk(KERN_DEBUG "da9052_spi_is_connected - "		\
+		       "spi read failed. Msg data =%x ..............\n",
+		       msg.data);
+		return -1;
+	}
+
+	return 0;
+
+}
+
+static int da9052_spi_probe(struct spi_device *spi)
+{
+	/* printk("\n\tEntered da9052_spi_probe.....\n"); */
+
+	da9052_spi = kzalloc(sizeof(struct da9052), GFP_KERNEL);
+
+	if (!da9052_spi)
+		return -ENOMEM;
+
+
+	spi->mode = SPI_MODE_0 | SPI_CPOL;
+	spi->bits_per_word = 8;
+	spi_setup(spi);
+
+	da9052_spi->dev = &spi->dev;
+
+	da9052_spi->spi_dev = spi;
+
+	/*
+	 * Allocate memory for RX/TX bufferes used in single register
+	 * read/write
+	 */
+	da9052_spi->spi_rx_buf = kmalloc(2, GFP_KERNEL | GFP_DMA);
+	if (!da9052_spi->spi_rx_buf)
+		return -ENOMEM;
+
+	da9052_spi->spi_tx_buf = kmalloc(2, GFP_KERNEL | GFP_DMA);
+	if (!da9052_spi->spi_tx_buf)
+		return -ENOMEM;
+
+	da9052_spi->spi_active_page  = PAGECON_0;
+	da9052_spi->rw_pol = 1;
+
+
+	dev_set_drvdata(&spi->dev, da9052_spi);
+
+
+	/* Validate SPI connectivity */
+	if (SPI_CONNECTED  == da9052_spi_is_connected()) {
+		/* SPI is connected */
+		da9052_spi->connecting_device = SPI;
+		if (0 != da9052_ssc_init(da9052_spi))
+			return -ENODEV;
+	} else {
+		return -ENODEV;
+	}
+
+	/* printk("Exiting da9052_spi_probe.....\n"); */
+
+	return 0;
+}
+
+static int da9052_spi_remove(struct spi_device *spi)
+{
+	struct da9052 *da9052 = dev_get_drvdata(&spi->dev);
+
+	printk("Entered da9052_spi_remove()\n");
+	if (SPI == da9052->connecting_device)
+		da9052_ssc_exit(da9052);
+	mfd_remove_devices(&spi->dev);
+	kfree(da9052->spi_rx_buf);
+	kfree(da9052->spi_tx_buf);
+	kfree(da9052);
+	return 0;
+}
+
+static struct spi_driver da9052_spi_driver = {
+	.driver = {
+		.name	 = DA9052_SSC_SPI_DEVICE_NAME,
+		.bus	= &spi_bus_type,
+		.owner	= THIS_MODULE,
+	},
+	.probe		= da9052_spi_probe,
+	.remove		= __devexit_p(da9052_spi_remove),
+};
+
+
+static int da9052_spi_set_page(struct da9052 *da9052, unsigned char page)
+{
+
+	struct da9052_ssc_msg sscmsg;
+	struct spi_message message;
+	struct spi_transfer xfer;
+	int ret = 0;
+
+	printk(KERN_DEBUG "Entered da9052_spi_set_page.....\n");
+	if ((page != PAGECON_0) && ((page != PAGECON_128)))
+		return INVALID_PAGE;
+
+	/* Current configuration is PAGE-0 and write request for PAGE-1 */
+	/* set register address */
+	sscmsg.addr = DA9052_PAGECON0_REG;
+	/* set value */
+	sscmsg.data = page;
+
+	/* Check value of R/W_POL bit of INTERFACE register */
+	if (!da9052->rw_pol) {
+		/* We need to set 0th bit for write operation */
+		sscmsg.addr = ((sscmsg.addr << 1) | RW_POL);
+	} else {
+		/* We need to reset 0th bit for write operation */
+		sscmsg.addr = (sscmsg.addr << 1);
+	}
+
+	/* SMDK-6410 host SPI driver specific stuff */
+
+	/* Build our spi message */
+	printk(KERN_DEBUG "da9052_spi_set_page - "\
+	       "Calling spi_message_init.....\n");
+	spi_message_init(&message);
+	memset(&xfer, 0, sizeof(xfer));
+
+	xfer.len = 2;
+	xfer.tx_buf = da9052->spi_tx_buf;
+	xfer.rx_buf = da9052->spi_rx_buf;
+
+	da9052->spi_tx_buf[0] = sscmsg.addr;
+	da9052->spi_tx_buf[1] = sscmsg.data;
+
+	printk(KERN_DEBUG "da9052_spi_set_page - "\
+	       "Calling spi_message_add_tail.....\n");
+	spi_message_add_tail(&xfer, &message);
+
+	/* Now, do the i/o */
+	printk(KERN_DEBUG "da9052_spi_set_page - Calling spi_sync.....\n");
+	ret = spi_sync(da9052->spi_dev, &message);
+
+	if (ret == 0) {
+		/* Active Page set successfully */
+		da9052->spi_active_page = page;
+		return 0;
+	} else {
+		/* Error in setting Active Page */
+		return ret;
+	}
+
+	return 0;
+}
+
+int da9052_spi_write(struct da9052 *da9052, struct da9052_ssc_msg *msg)
+{
+
+	struct spi_message message;
+	struct spi_transfer xfer;
+	int ret;
+
+	/*
+	 * We need a seperate copy of da9052_ssc_msg so that caller's
+	 * copy remains intact
+	*/
+	struct da9052_ssc_msg sscmsg;
+
+	/* Copy callers data in to our local copy */
+	sscmsg.addr = msg->addr;
+	sscmsg.data = msg->data;
+
+	if ((sscmsg.addr > PAGE_0_END) &&
+		(da9052->spi_active_page == PAGECON_0)) {
+		/*
+		* Current configuration is PAGE-0 and write request
+		* for PAGE-1
+		*/
+		da9052_spi_set_page(da9052, PAGECON_128);
+		/* Set register address accordindly */
+		sscmsg.addr = (sscmsg.addr - PAGE_1_START);
+	} else if ((sscmsg.addr < PAGE_1_START) &&
+		(da9052->spi_active_page == PAGECON_128)) {
+		/*
+		* Current configuration is PAGE-1 and write request
+		* for PAGE-0
+		*/
+		da9052_spi_set_page(da9052, PAGECON_0);
+	} else if (sscmsg.addr > PAGE_0_END) {
+		/*
+		* Current configuration is PAGE-1 and write request
+		* for PAGE-1. Just need to adjust register address
+		*/
+		sscmsg.addr = (sscmsg.addr - PAGE_1_START);
+	}
+
+	/* Check value of R/W_POL bit of INTERFACE register */
+	if (!da9052->rw_pol) {
+		/* We need to set 0th bit for write operation */
+		sscmsg.addr = ((sscmsg.addr << 1) | RW_POL);
+	} else {
+		/* We need to reset 0th bit for write operation */
+		sscmsg.addr = (sscmsg.addr << 1);
+	}
+
+	/* SMDK-6410 host SPI driver specific stuff */
+
+	/* Build our spi message */
+	spi_message_init(&message);
+	memset(&xfer, 0, sizeof(xfer));
+
+	xfer.len = 2;
+	xfer.tx_buf = da9052->spi_tx_buf;
+	xfer.rx_buf = da9052->spi_rx_buf;
+
+	da9052->spi_tx_buf[0] = sscmsg.addr;
+	da9052->spi_tx_buf[1] = sscmsg.data;
+
+	spi_message_add_tail(&xfer, &message);
+
+	/* Now, do the i/o */
+	ret = spi_sync(da9052->spi_dev, &message);
+
+	return ret;
+}
+
+int da9052_spi_write_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg,
+			  int msg_no)
+{
+	int cnt, ret = 0;
+
+	for (cnt = 0; cnt < msg_no; cnt++, sscmsg++) {
+		ret = da9052_ssc_write(da9052, sscmsg);
+		if (ret != 0) {
+			printk(KERN_DEBUG "Error in %s\n", __func__);
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+int da9052_spi_read(struct da9052 *da9052, struct da9052_ssc_msg *msg)
+{
+
+	struct spi_message message;
+	struct spi_transfer xfer;
+	int ret;
+
+	/*
+	* We need a seperate copy of da9052_ssc_msg so that
+	* caller's copy remains intact
+	*/
+	struct da9052_ssc_msg sscmsg;
+
+
+	/* Copy callers data in to our local copy */
+	sscmsg.addr = msg->addr;
+	sscmsg.data = msg->data;
+
+	if ((sscmsg.addr > PAGE_0_END) &&
+		(da9052->spi_active_page == PAGECON_0)) {
+		/*
+		* Current configuration is PAGE-0 and
+		* read request for PAGE-1
+		*/
+		printk(KERN_DEBUG "da9052_spi_read - if PAGECON_128.....\n");
+		da9052_spi_set_page(da9052, PAGECON_128);
+		/* Set register address accordindly */
+		sscmsg.addr = (sscmsg.addr - PAGE_1_START);
+	} else if ((sscmsg.addr < PAGE_1_START) &&
+		(da9052->spi_active_page == PAGECON_128)) {
+		/*
+		* Current configuration is PAGE-1 and
+		* write request for PAGE-0
+		*/
+		printk(KERN_DEBUG "da9052_spi_read - if PAGECON_0.....\n");
+		da9052_spi_set_page(da9052, PAGECON_0);
+	} else if (sscmsg.addr > PAGE_0_END) {
+		/*
+		* Current configuration is PAGE-1 and write
+		* request for PAGE-1
+		* Just need to adjust register address
+		*/
+		sscmsg.addr = (sscmsg.addr - PAGE_1_START);
+	}
+
+	/* Check value of R/W_POL bit of INTERFACE register */
+	if (da9052->rw_pol) {
+		/* We need to set 0th bit for read operation */
+		sscmsg.addr = ((sscmsg.addr << 1) | RW_POL);
+	} else {
+		/* We need to reset 0th bit for write operation */
+		sscmsg.addr = (sscmsg.addr << 1);
+	}
+
+	/* SMDK-6410 host SPI driver specific stuff */
+
+	/* Build our spi message */
+	spi_message_init(&message);
+	memset(&xfer, 0, sizeof(xfer));
+
+	xfer.len = 2;
+	xfer.tx_buf = da9052->spi_tx_buf;
+	xfer.rx_buf = da9052->spi_rx_buf;
+
+	da9052->spi_tx_buf[0] = sscmsg.addr;
+	da9052->spi_tx_buf[1] = 0xff;
+
+	da9052->spi_rx_buf[0] = 0;
+	da9052->spi_rx_buf[1] = 0;
+
+	spi_message_add_tail(&xfer, &message);
+
+	/* Now, do the i/o */
+	ret = spi_sync(da9052->spi_dev, &message);
+
+	if (ret == 0) {
+		/* Update read value in callers copy */
+		msg->data = da9052->spi_rx_buf[1];
+		return 0;
+	} else {
+		return ret;
+	}
+
+
+	return 0;
+}
+
+int da9052_spi_read_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg,
+			 int msg_no)
+{
+	int cnt, ret = 0;
+
+	for (cnt = 0; cnt < msg_no; cnt++, sscmsg++) {
+		ret = da9052_ssc_read(da9052, sscmsg);
+		if (ret != 0) {
+			printk(KERN_DEBUG "Error in %s\n", __func__);
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+static int __init da9052_spi_init(void)
+{
+	int ret = 0;
+	/*printk("Entered da9052_spi_init.....\n");*/
+	ret = spi_register_driver(&da9052_spi_driver);
+	if (ret != 0) {
+		printk(KERN_ERR "Unable to register %s\n",
+		       DA9052_SSC_SPI_DEVICE_NAME);
+		return ret;
+	}
+	return 0;
+}
+module_init(da9052_spi_init);
+
+static void __exit da9052_spi_exit(void)
+{
+	spi_unregister_driver(&da9052_spi_driver);
+}
+
+module_exit(da9052_spi_exit);
+
+MODULE_AUTHOR("Dialog Semiconductor Ltd <dchen@diasemi.com>");
+MODULE_DESCRIPTION("SPI driver for Dialog DA9052 PMIC");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DA9052_SSC_SPI_DEVICE_NAME);
diff --git a/drivers/mxc/Kconfig b/drivers/mxc/Kconfig
new file mode 100644
index 00000000000..d2b05814832
--- /dev/null
+++ b/drivers/mxc/Kconfig
@@ -0,0 +1,27 @@
+# drivers/mxc/Kconfig
+
+if ARCH_MXC
+
+menu "MXC support drivers"
+
+config MXC_IPU
+	bool "Image Processing Unit Driver"
+	depends on !ARCH_MX21
+	depends on !ARCH_MX27
+	depends on !ARCH_MX25
+	select MXC_IPU_V1 if !ARCH_MX37 && !ARCH_MX5
+	select MXC_IPU_V3 if ARCH_MX37 || ARCH_MX5
+	select MXC_IPU_V3D if ARCH_MX37
+	select MXC_IPU_V3EX if ARCH_MX5
+	help
+	  If you plan to use the Image Processing unit, say
+	  Y here. IPU is needed by Framebuffer and V4L2 drivers.
+
+source "drivers/mxc/ipu3/Kconfig"
+
+source "drivers/mxc/vpu/Kconfig"
+source "drivers/mxc/amd-gpu/Kconfig"
+
+endmenu
+
+endif
diff --git a/drivers/mxc/Makefile b/drivers/mxc/Makefile
new file mode 100644
index 00000000000..8955170b43c
--- /dev/null
+++ b/drivers/mxc/Makefile
@@ -0,0 +1,5 @@
+# drivers/mxc/Makefile
+obj-$(CONFIG_MXC_IPU_V3)		+= ipu3/
+obj-$(CONFIG_MXC_VPU)                   += vpu/
+obj-$(CONFIG_MXC_AMD_GPU)              += amd-gpu/
+
diff --git a/drivers/mxc/amd-gpu/Kconfig b/drivers/mxc/amd-gpu/Kconfig
new file mode 100644
index 00000000000..629d8cbbc98
--- /dev/null
+++ b/drivers/mxc/amd-gpu/Kconfig
@@ -0,0 +1,13 @@
+#
+# Bluetooth configuration
+#
+
+menu "MXC GPU support"
+
+config MXC_AMD_GPU
+	tristate "MXC GPU support"
+	depends on ARCH_MX35 || ARCH_MX51 || ARCH_MX53 || ARCH_MX50
+	---help---
+         Say Y to get the GPU driver support.
+
+endmenu
diff --git a/drivers/mxc/amd-gpu/Makefile b/drivers/mxc/amd-gpu/Makefile
new file mode 100644
index 00000000000..84cf02e5b3a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/Makefile
@@ -0,0 +1,31 @@
+EXTRA_CFLAGS := \
+	-D_LINUX \
+	-I$(obj)/include \
+	-I$(obj)/include/api \
+	-I$(obj)/include/ucode \
+	-I$(obj)/platform/hal/linux \
+	-I$(obj)/os/include \
+	-I$(obj)/os/kernel/include \
+	-I$(obj)/os/user/include
+
+obj-$(CONFIG_MXC_AMD_GPU) += gpu.o
+gpu-objs += 	common/gsl_cmdstream.o \
+		common/gsl_cmdwindow.o \
+		common/gsl_context.o \
+		common/gsl_debug_pm4.o \
+		common/gsl_device.o \
+		common/gsl_drawctxt.o \
+		common/gsl_driver.o \
+		common/gsl_g12.o \
+		common/gsl_intrmgr.o \
+		common/gsl_memmgr.o \
+		common/gsl_mmu.o \
+		common/gsl_ringbuffer.o \
+		common/gsl_sharedmem.o \
+		common/gsl_yamato.o \
+		platform/hal/linux/gsl_linux_map.o \
+		platform/hal/linux/gsl_kmod.o \
+		platform/hal/linux/gsl_hal.o \
+		platform/hal/linux/gsl_kmod_cleanup.o \
+		platform/hal/linux/misc.o \
+		os/kernel/src/linux/kos_lib.o
diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdstream.c b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c
new file mode 100644
index 00000000000..4f0d107f2f6
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c
@@ -0,0 +1,267 @@
+/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "gsl_cmdstream.h"
+
+#ifdef GSL_LOCKING_FINEGRAIN
+#define GSL_CMDSTREAM_MUTEX_CREATE()        device->cmdstream_mutex = kos_mutex_create("gsl_cmdstream"); \
+                                            if (!device->cmdstream_mutex) return (GSL_FAILURE);
+#define GSL_CMDSTREAM_MUTEX_LOCK()          kos_mutex_lock(device->cmdstream_mutex)
+#define GSL_CMDSTREAM_MUTEX_UNLOCK()        kos_mutex_unlock(device->cmdstream_mutex)
+#define GSL_CMDSTREAM_MUTEX_FREE()          kos_mutex_free(device->cmdstream_mutex); device->cmdstream_mutex = 0;
+#else
+#define GSL_CMDSTREAM_MUTEX_CREATE()
+#define GSL_CMDSTREAM_MUTEX_LOCK()
+#define GSL_CMDSTREAM_MUTEX_UNLOCK()
+#define GSL_CMDSTREAM_MUTEX_FREE()
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_cmdstream_init(gsl_device_t *device)
+{
+    GSL_CMDSTREAM_MUTEX_CREATE();
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_cmdstream_close(gsl_device_t *device)
+{
+    GSL_CMDSTREAM_MUTEX_FREE();
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+gsl_timestamp_t
+kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type)
+{
+    gsl_timestamp_t   timestamp = -1;
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_timestamp_t kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id=%d gsl_timestamp_type_t type=%d)\n", device_id, type );
+#if (defined(GSL_BLD_G12) && defined(IRQTHREAD_POLL))
+    kos_event_signal(device->irqthread_event);
+#endif
+    if (type == GSL_TIMESTAMP_CONSUMED)
+    {
+        // start-of-pipeline timestamp
+        GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, (unsigned int*)&timestamp);
+    }
+    else if (type == GSL_TIMESTAMP_RETIRED)
+    {
+		// end-of-pipeline timestamp
+		GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (unsigned int*)&timestamp);
+    }
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_readtimestamp. Return value %d\n", timestamp );
+    return (timestamp);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API gsl_timestamp_t
+kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type)
+{
+	gsl_timestamp_t timestamp = -1;
+	GSL_API_MUTEX_LOCK();
+	timestamp = kgsl_cmdstream_readtimestamp0(device_id, type);
+	GSL_API_MUTEX_UNLOCK();
+	return timestamp;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status = GSL_FAILURE;
+    GSL_API_MUTEX_LOCK();
+    
+    kgsl_device_active(device);
+     
+    if (device->ftbl.cmdstream_issueibcmds)
+    {
+        status = device->ftbl.cmdstream_issueibcmds(device, drawctxt_index, ibaddr, sizedwords, timestamp, flags);
+    }
+    GSL_API_MUTEX_UNLOCK();
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status = GSL_FAILURE;
+    GSL_API_MUTEX_LOCK();
+    if (device->ftbl.device_addtimestamp)
+    {
+        status = device->ftbl.device_addtimestamp(device, timestamp);
+    }
+    GSL_API_MUTEX_UNLOCK();
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API
+int kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+	int status = GSL_FAILURE;
+	if (device->ftbl.device_waittimestamp)
+    {
+        status = device->ftbl.device_waittimestamp(device, timestamp, timeout);
+    }
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_cmdstream_memqueue_drain(gsl_device_t *device)
+{
+    gsl_memnode_t     *memnode, *nextnode, *freehead;
+    gsl_timestamp_t   timestamp, ts_processed;
+    gsl_memqueue_t    *memqueue = &device->memqueue;
+
+    GSL_CMDSTREAM_MUTEX_LOCK();
+
+    // check head
+    if (memqueue->head == NULL)
+    {
+        GSL_CMDSTREAM_MUTEX_UNLOCK();
+        return;
+    }
+    // get current EOP timestamp
+    ts_processed = kgsl_cmdstream_readtimestamp0(device->id, GSL_TIMESTAMP_RETIRED);
+    timestamp = memqueue->head->timestamp;
+    // check head timestamp
+    if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -GSL_TIMESTAMP_EPSILON)))
+    {
+        GSL_CMDSTREAM_MUTEX_UNLOCK();
+        return;
+    }
+    memnode  = memqueue->head;
+    freehead = memqueue->head;
+    // get node list to free
+    for(;;)
+    {
+        nextnode  = memnode->next;
+        if (nextnode == NULL)
+        {
+            // entire queue drained
+            memqueue->head = NULL;
+            memqueue->tail = NULL;
+            break;
+        }
+        timestamp = nextnode->timestamp;
+        if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -GSL_TIMESTAMP_EPSILON)))
+        {
+            // drained up to a point
+            memqueue->head = nextnode;
+            memnode->next  = NULL;
+            break;
+        }
+        memnode = nextnode;
+    }
+    // free nodes
+    while (freehead)
+    {
+        memnode  = freehead;
+        freehead = memnode->next;
+        kgsl_sharedmem_free0(&memnode->memdesc, memnode->pid);
+        kos_free(memnode);
+    }
+
+    GSL_CMDSTREAM_MUTEX_UNLOCK();
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type)
+{
+    gsl_memnode_t  *memnode;
+    gsl_device_t   *device = &gsl_driver.device[device_id-1];
+    gsl_memqueue_t *memqueue;
+    (void)type; // unref. For now just use EOP timestamp
+
+	GSL_API_MUTEX_LOCK();
+	GSL_CMDSTREAM_MUTEX_LOCK();
+
+	memqueue = &device->memqueue;
+
+    memnode  = kos_malloc(sizeof(gsl_memnode_t));
+
+    if (!memnode)
+    {
+        // other solution is to idle and free which given that the upper level driver probably wont check, probably a better idea
+		GSL_CMDSTREAM_MUTEX_UNLOCK();
+		GSL_API_MUTEX_UNLOCK();
+        return (GSL_FAILURE);
+    }
+
+    memnode->timestamp = timestamp;
+    memnode->pid       = GSL_CALLER_PROCESSID_GET();
+    memnode->next      = NULL;
+    kos_memcpy(&memnode->memdesc, memdesc, sizeof(gsl_memdesc_t));
+
+    // add to end of queue
+    if (memqueue->tail != NULL)
+    {
+        memqueue->tail->next = memnode;
+        memqueue->tail       = memnode;
+    }
+    else
+    {
+        KOS_ASSERT(memqueue->head == NULL);
+        memqueue->head = memnode;
+        memqueue->tail = memnode;
+    }
+
+    GSL_CMDSTREAM_MUTEX_UNLOCK();
+	GSL_API_MUTEX_UNLOCK();
+
+    return (GSL_SUCCESS);
+}
+
+static int kgsl_cmdstream_timestamp_cmp(gsl_timestamp_t ts_new, gsl_timestamp_t ts_old)
+{
+	gsl_timestamp_t ts_diff = ts_new - ts_old;
+	return (ts_diff >= 0) || (ts_diff < -GSL_TIMESTAMP_EPSILON);
+}
+
+int kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp)
+{
+	gsl_timestamp_t ts_processed;
+	ts_processed = kgsl_cmdstream_readtimestamp0(device_id, GSL_TIMESTAMP_RETIRED);
+	return kgsl_cmdstream_timestamp_cmp(ts_processed, timestamp);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c
new file mode 100644
index 00000000000..d19832d8da4
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c
@@ -0,0 +1,161 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+#ifdef GSL_BLD_G12
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_CMDWINDOW_TARGET_MASK       0x000000FF
+#define GSL_CMDWINDOW_ADDR_MASK         0x00FFFF00
+#define GSL_CMDWINDOW_TARGET_SHIFT      0
+#define GSL_CMDWINDOW_ADDR_SHIFT        8
+
+
+//////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_LOCKING_FINEGRAIN
+#define GSL_CMDWINDOW_MUTEX_CREATE()        device->cmdwindow_mutex = kos_mutex_create("gsl_cmdwindow"); \
+                                            if (!device->cmdwindow_mutex) return (GSL_FAILURE);
+#define GSL_CMDWINDOW_MUTEX_LOCK()          kos_mutex_lock(device->cmdwindow_mutex)
+#define GSL_CMDWINDOW_MUTEX_UNLOCK()        kos_mutex_unlock(device->cmdwindow_mutex)
+#define GSL_CMDWINDOW_MUTEX_FREE()          kos_mutex_free(device->cmdwindow_mutex); device->cmdwindow_mutex = 0;
+#else
+#define GSL_CMDWINDOW_MUTEX_CREATE()
+#define GSL_CMDWINDOW_MUTEX_LOCK()
+#define GSL_CMDWINDOW_MUTEX_UNLOCK()
+#define GSL_CMDWINDOW_MUTEX_FREE()
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_cmdwindow_init(gsl_device_t *device)
+{
+    GSL_CMDWINDOW_MUTEX_CREATE();
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int 
+kgsl_cmdwindow_close(gsl_device_t *device)
+{
+    GSL_CMDWINDOW_MUTEX_FREE();
+
+    return (GSL_SUCCESS);
+}
+
+#endif // GSL_BLD_G12
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data)
+{
+#ifdef GSL_BLD_G12
+    gsl_device_t  *device;
+    unsigned int  cmdwinaddr;
+    unsigned int  cmdstream;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_cmdwindow_write( gsl_device_id_t device_id=%d, gsl_cmdwindow_t target=%d, unsigned int addr=0x%08x, unsigned int data=0x%08x)\n", device_id, target, addr, data );
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (target < GSL_CMDWINDOW_MIN || target > GSL_CMDWINDOW_MAX)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid target.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    if ((!(device->flags & GSL_FLAGS_INITIALIZED) && target == GSL_CMDWINDOW_MMU) ||
+        (!(device->flags & GSL_FLAGS_STARTED)     && target != GSL_CMDWINDOW_MMU))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device state to write to selected targer.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // set command stream
+    if (target == GSL_CMDWINDOW_MMU)
+    {
+#ifdef GSL_NO_MMU
+        return (GSL_SUCCESS);
+#endif
+        cmdstream = ADDR_VGC_MMUCOMMANDSTREAM;
+    }
+    else
+    {
+        cmdstream = ADDR_VGC_COMMANDSTREAM;
+    }
+
+
+    // set command window address
+    cmdwinaddr  = ((target << GSL_CMDWINDOW_TARGET_SHIFT) & GSL_CMDWINDOW_TARGET_MASK);
+    cmdwinaddr |= ((addr   << GSL_CMDWINDOW_ADDR_SHIFT)   & GSL_CMDWINDOW_ADDR_MASK);
+
+    GSL_CMDWINDOW_MUTEX_LOCK();
+
+#ifndef GSL_NO_MMU
+    // set mmu pagetable
+	kgsl_mmu_setpagetable(device, GSL_CALLER_PROCESSID_GET());
+#endif
+
+    // write command window address
+    device->ftbl.device_regwrite(device, (cmdstream)>>2, cmdwinaddr);
+
+    // write data
+    device->ftbl.device_regwrite(device, (cmdstream)>>2, data);
+
+    GSL_CMDWINDOW_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+#else
+    // unreferenced formal parameter
+    (void) device_id;
+    (void) target;
+    (void) addr;
+    (void) data;
+
+    return (GSL_FAILURE);
+#endif // GSL_BLD_G12
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_cmdwindow_write0(device_id, target, addr, data);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_context.c b/drivers/mxc/amd-gpu/common/gsl_context.c
new file mode 100644
index 00000000000..c999247b3af
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_context.c
@@ -0,0 +1,74 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "gsl_context.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+KGSL_API int
+kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status;
+
+    GSL_API_MUTEX_LOCK();
+
+    if (device->ftbl.context_create)
+    {
+        status = device->ftbl.context_create(device, type, drawctxt_id, flags);
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id)
+{
+    gsl_device_t* device  = &gsl_driver.device[device_id-1];
+    int status;
+
+    GSL_API_MUTEX_LOCK();
+
+    if (device->ftbl.context_destroy)
+    {
+        status = device->ftbl.context_destroy(device, drawctxt_id);
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c
new file mode 100644
index 00000000000..847df8dbe38
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c
@@ -0,0 +1,1015 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+#if defined(_WIN32) && defined (GSL_BLD_YAMATO)
+
+#include <stdio.h>
+#include <string.h>
+#include <stdarg.h>
+
+//#define PM4_DEBUG_USE_MEMBUF
+
+#ifdef PM4_DEBUG_USE_MEMBUF
+
+#define MEMBUF_SIZE 100000
+#define BUFFER_END_MARGIN 1000
+char memBuf[MEMBUF_SIZE];
+static int writePtr = 0;
+static unsigned int lineNumber = 0;
+//#define fprintf(A,...); writePtr += sprintf( memBuf+writePtr, __VA_ARGS__ ); sprintf( memBuf+writePtr, "###" ); if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) { memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); writePtr = 0; }
+#define FILE char
+#define fopen(X,Y) 0
+#define fclose(X)
+
+int printString( FILE *_File, const char * _Format, ...)
+{
+    int ret;
+    va_list ap;
+    (void)_File;
+
+    va_start(ap, _Format);
+    if( writePtr > 0 && memBuf[writePtr-1] == '\n' )
+    {
+        // Add line number if last written character was newline
+        writePtr += sprintf( memBuf+writePtr, "%d: ", lineNumber++ );
+    }
+    ret = vsprintf(memBuf+writePtr, _Format, ap);
+    writePtr += ret;
+    sprintf( memBuf+writePtr, "###" );
+    if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) 
+    { 
+        memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); 
+        writePtr = 0;
+    }
+
+    va_end(ap);
+
+    return ret;
+}
+
+#else
+
+int printString( FILE *_File, const char * _Format, ...)
+{
+    int ret;
+    va_list ap;
+    va_start(ap, _Format);
+    ret = vfprintf(_File, _Format, ap);
+    va_end(ap);
+    fflush(_File);
+    return ret;
+}
+
+#endif
+
+#ifndef    _WIN32_WCE
+#define PM4_DUMPFILE    "pm4dump.txt"
+#else
+#define PM4_DUMPFILE    "\\Release\\pm4dump.txt"
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#define EXPAND_OPCODE(opcode) ((opcode << 8) | PM4_PKT_MASK)
+
+#define GetString_uint                       GetString_int
+#define GetString_fixed12_4(val, szValue)    GetString_fixed(val, 12, 4, szValue)
+#define GetString_signedint15(val, szValue)  GetString_signedint(val, 15, szValue)
+
+// Need a prototype for this function
+void WritePM4Packet_Type3(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer);
+
+static int indirectionLevel = 0;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+void WriteDWORD(FILE* pFile, unsigned int dwValue)
+{
+    printString(pFile, "    0x%08x", dwValue);
+}
+
+void WriteDWORD2(FILE* pFile, unsigned int dwValue)
+{
+    printString(pFile, "    0x%08x\n", dwValue);
+}
+
+//----------------------------------------------------------------------------
+
+// Generate the GetString_## functions for enumerated types
+#define START_ENUMTYPE(__type)                      \
+void GetString_##__type(unsigned int val, char* szValue)   \
+{                                                   \
+    switch(val)                                     \
+    {
+
+#define GENERATE_ENUM(__enumname, __val)            \
+        case __val:                                 \
+            kos_strcpy(szValue, #__enumname);        \
+            break;
+
+#define END_ENUMTYPE(__type)                        \
+        default:                                    \
+            sprintf(szValue, "Unknown: %d", val);   \
+            break;                                  \
+    }                                               \
+}
+
+#include _YAMATO_GENENUM_H
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_hex(unsigned int val, char* szValue)
+{
+    sprintf(szValue, "0x%x", val);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_float(unsigned int val, char* szValue)
+{
+    float fval = *((float*) &val);
+    sprintf(szValue, "%.4f", fval);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_bool(unsigned int val, char* szValue)
+{
+    if (val)
+    {
+        kos_strcpy(szValue, "TRUE");
+    }
+    else
+    {
+        kos_strcpy(szValue, "FALSE");
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void GetString_int(unsigned int val, char* szValue)
+{
+    sprintf(szValue, "%d", val);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_intMinusOne(unsigned int val, char* szValue)
+{
+    sprintf(szValue, "%d+1", val);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_signedint(unsigned int val, unsigned int dwNumBits, char* szValue)
+{
+    int nValue = val;
+
+    if (val & (1<<(dwNumBits-1)))
+    {
+        nValue |= 0xffffffff << dwNumBits;
+    }
+
+    sprintf(szValue, "%d", nValue);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_fixed(unsigned int val, unsigned int dwNumInt, unsigned int dwNumFrac, char* szValue)
+{
+
+   (void) dwNumInt;     // unreferenced formal parameter
+
+    if (val>>dwNumFrac == 0)
+    {
+        // Integer part is 0 - just print out the fractional part
+        sprintf(szValue, "%d/%d",
+            val&((1<<dwNumFrac)-1),
+            1<<dwNumFrac);
+    }
+    else
+    {
+        // Print out as a mixed fraction
+        sprintf(szValue, "%d %d/%d",
+            val>>dwNumFrac,
+            val&((1<<dwNumFrac)-1),
+            1<<dwNumFrac);
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_Register(unsigned int dwBaseIndex, unsigned int dwValue, char* pszString)
+{
+    char szValue[64];
+    char szField[128];
+
+    // Empty the string
+    pszString[0] = '\0';
+
+    switch(dwBaseIndex)
+    {
+#define START_REGISTER(__reg)               \
+        case mm##__reg:                     \
+            {                               \
+                reg##__reg reg;             \
+                reg.u32All = dwValue;       \
+                strcat(pszString, #__reg ", (");
+
+#define GENERATE_FIELD(__name, __type)                                \
+                GetString_##__type(reg.bitfields.__name, szValue);    \
+                sprintf(szField, #__name " = %s, ", szValue);         \
+                strcat(pszString, szField);
+
+#define END_REGISTER(__reg)                           \
+                pszString[strlen(pszString)-2]='\0';  \
+                strcat(pszString, ")");               \
+            }                                         \
+            break;
+
+#include _YAMATO_GENREG_H
+
+        default:
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void 
+GetString_Type3Opcode(unsigned int opcode, char* pszValue)
+{
+switch(EXPAND_OPCODE(opcode))
+    {
+#define TYPE3SWITCH(__opcode)                  \
+        case PM4_PACKET3_##__opcode:           \
+            kos_strcpy(pszValue, #__opcode);    \
+            break;
+
+        TYPE3SWITCH(NOP)
+        TYPE3SWITCH(IB_PREFETCH_END)
+        TYPE3SWITCH(SUBBLK_PREFETCH)
+
+        TYPE3SWITCH(INSTR_PREFETCH)
+        TYPE3SWITCH(REG_RMW)
+        TYPE3SWITCH(DRAW_INDX)
+        TYPE3SWITCH(VIZ_QUERY)
+        TYPE3SWITCH(SET_STATE)
+        TYPE3SWITCH(WAIT_FOR_IDLE)
+        TYPE3SWITCH(IM_LOAD)
+        TYPE3SWITCH(IM_LOAD_IMMEDIATE)
+        TYPE3SWITCH(SET_CONSTANT)
+        TYPE3SWITCH(LOAD_CONSTANT_CONTEXT)
+        TYPE3SWITCH(LOAD_ALU_CONSTANT)
+
+        TYPE3SWITCH(DRAW_INDX_BIN)
+        TYPE3SWITCH(3D_DRAW_INDX_2_BIN)
+        TYPE3SWITCH(3D_DRAW_INDX_2)
+        TYPE3SWITCH(INDIRECT_BUFFER_PFD)
+        TYPE3SWITCH(INVALIDATE_STATE)
+        TYPE3SWITCH(WAIT_REG_MEM)
+        TYPE3SWITCH(MEM_WRITE)
+        TYPE3SWITCH(REG_TO_MEM)
+        TYPE3SWITCH(INDIRECT_BUFFER)
+
+        TYPE3SWITCH(CP_INTERRUPT)
+        TYPE3SWITCH(COND_EXEC)
+        TYPE3SWITCH(COND_WRITE)
+        TYPE3SWITCH(EVENT_WRITE)
+        TYPE3SWITCH(INSTR_MATCH)
+        TYPE3SWITCH(ME_INIT)
+        TYPE3SWITCH(CONST_PREFETCH)
+        TYPE3SWITCH(MEM_WRITE_CNTR)
+
+        TYPE3SWITCH(SET_BIN_MASK)
+        TYPE3SWITCH(SET_BIN_SELECT)
+        TYPE3SWITCH(WAIT_REG_EQ)
+        TYPE3SWITCH(WAIT_REG_GTE)
+        TYPE3SWITCH(INCR_UPDT_STATE)
+        TYPE3SWITCH(INCR_UPDT_CONST)
+        TYPE3SWITCH(INCR_UPDT_INSTR)
+        TYPE3SWITCH(EVENT_WRITE_SHD)
+        TYPE3SWITCH(EVENT_WRITE_CFL)
+        TYPE3SWITCH(EVENT_WRITE_ZPD)
+        TYPE3SWITCH(WAIT_UNTIL_READ)
+        TYPE3SWITCH(WAIT_IB_PFD_COMPLETE)
+        TYPE3SWITCH(CONTEXT_UPDATE)
+
+        default:
+            sprintf(pszValue, "Unknown: %d", opcode);
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void 
+WritePM4Packet_Type0(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer)
+{
+    pm4_type0 header = *((pm4_type0*) &dwHeader);
+    unsigned int* pBuffer = *ppBuffer;
+    unsigned int dwIndex;
+
+    WriteDWORD(pFile, dwHeader);
+    printString(pFile, "    // Type-0 packet (BASE_INDEX = 0x%x, ONE_REG_WR = %d, COUNT = %d+1)\n",
+        header.base_index, header.one_reg_wr, header.count);   
+
+    // Now go through and write the dwNumDWORDs 
+    for (dwIndex = 0; dwIndex < header.count+1; dwIndex++)
+    {
+        char szRegister[1024];
+        unsigned int dwRegIndex;
+        unsigned int dwRegValue = *(pBuffer++);
+
+        if (header.one_reg_wr)
+        {
+            dwRegIndex = header.base_index;
+        }
+        else
+        {
+            dwRegIndex = header.base_index + dwIndex;
+        }
+
+        WriteDWORD(pFile, dwRegValue);
+        // Write register string based on fields
+        GetString_Register(dwRegIndex, dwRegValue, szRegister);
+        printString(pFile, "    // %s\n", szRegister);
+
+        // Write actual unsigned int
+        
+    }
+
+    *ppBuffer = pBuffer;
+}
+
+//----------------------------------------------------------------------------
+
+void 
+WritePM4Packet_Type2(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer)
+{
+    unsigned int* pBuffer = *ppBuffer;
+
+    WriteDWORD(pFile, dwHeader);
+    printString(pFile, "    // Type-2 packet\n");
+    
+    *ppBuffer = pBuffer;
+}
+
+//----------------------------------------------------------------------------
+
+void
+AnalyzePacketType(FILE *pFile, unsigned int dwHeader, unsigned int**ppBuffer)
+{
+    switch(dwHeader & PM4_PKT_MASK)
+    {
+    case PM4_TYPE0_PKT:
+        WritePM4Packet_Type0(pFile, dwHeader, ppBuffer);
+        break;
+
+    case PM4_TYPE1_PKT:
+        break;
+
+    case PM4_TYPE2_PKT:
+        WritePM4Packet_Type2(pFile, dwHeader, ppBuffer);
+        break;
+
+    case PM4_TYPE3_PKT:
+        WritePM4Packet_Type3(pFile, dwHeader, ppBuffer);
+        break;
+    }
+}
+
+void 
+WritePM4Packet_Type3(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer)
+{
+    pm4_type3 header = *((pm4_type3*) &dwHeader);
+    unsigned int* pBuffer = *ppBuffer;
+    unsigned int dwIndex;
+    char szOpcode[64];
+
+    if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) ||
+       (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD))
+    {
+        unsigned int *pIndirectBuffer = (unsigned int *) *(pBuffer++); // ordinal 2 of IB packet is an address
+        unsigned int *pIndirectBufferEnd = pIndirectBuffer + *(pBuffer++); // ordinal 3 of IB packet is size
+        unsigned int gpuaddr = kgsl_sharedmem_convertaddr((unsigned int) pIndirectBuffer, 1);
+
+        indirectionLevel++;
+
+        WriteDWORD2(pFile, dwHeader);
+        WriteDWORD2(pFile, gpuaddr);
+        WriteDWORD2(pFile, (unsigned int) (pIndirectBufferEnd-pIndirectBuffer));
+
+        if (indirectionLevel == 1)
+        {
+            printString(pFile, "Start_IB1, base=0x%x, size=%d\n", gpuaddr, (unsigned int)(pIndirectBufferEnd - pIndirectBuffer));
+        }
+        else
+        {
+            printString(pFile, "Start_IB2, base=0x%x, size=%d\n", gpuaddr, (unsigned int)(pIndirectBufferEnd - pIndirectBuffer));
+        }
+
+        while(pIndirectBuffer < pIndirectBufferEnd)
+        {
+            unsigned int _dwHeader = *(pIndirectBuffer++);
+
+            AnalyzePacketType(pFile, _dwHeader, &pIndirectBuffer);
+        }
+
+        if (indirectionLevel == 1)
+        {
+            printString(pFile, "End_IB1\n");
+        }
+        else
+        {
+            printString(pFile, "End_IB2\n");
+        }
+
+        indirectionLevel--;
+    }
+    else
+    {
+        unsigned int registerAddr = 0xffffffff;
+        char szRegister[1024];
+
+        GetString_Type3Opcode(header.it_opcode, szOpcode);
+
+        WriteDWORD(pFile, dwHeader);
+        printString(pFile, "    // Type-3 packet (PREDICATE = %d, IT_OPCODE = %s, COUNT = %d+1)\n",
+            header.predicate, szOpcode, header.count);
+        
+        // Go through each command
+        for (dwIndex = 0; dwIndex < header.count+1; dwIndex++)
+        {
+            // Check for a register write
+            if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_SET_CONSTANT) && (((*pBuffer) >> 16) == 0x4))
+                registerAddr = (*pBuffer) & 0xffff;
+
+            // Write unsigned int
+            WriteDWORD(pFile, *pBuffer);
+
+            // Starting at Ordinal 2 is actual register values
+            if((dwIndex > 0) && (registerAddr != 0xffffffff))
+            {
+                // Write register string based on address
+                GetString_Register(registerAddr + 0x2000, *pBuffer, szRegister);
+                printString(pFile, "    // %s\n", szRegister);
+                registerAddr++;
+            }
+            else
+            {
+                // Write out newline if we aren't augmenting with register fields
+                printString(pFile, "\n");
+            }
+
+            pBuffer++;
+        }
+    }
+    *ppBuffer = pBuffer;
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpInitParams(unsigned int dwEDRAMBase, unsigned int dwEDRAMSize)
+{
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "InitParams, edrambase=0x%x, edramsize=%d\n",
+        dwEDRAMBase, dwEDRAMSize);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpSwapBuffers(unsigned int dwAddress, unsigned int dwWidth,
+    unsigned int dwHeight, unsigned int dwPitch, unsigned int dwAlignedHeight, unsigned int dwBitsPerPixel)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "SwapBuffers, address=0x%08x, width=%d, height=%d, pitch=%d, alignedheight=%d, bpp=%d\n",
+        dwAddress, dwWidth, dwHeight, dwPitch, dwAlignedHeight, dwBitsPerPixel);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpRegSpace(gsl_device_t *device)
+{
+    int           regsPerLine = 0x20;
+    unsigned int  dwOffset;
+    unsigned int  value;
+
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "Start_RegisterSpace\n");
+    
+    for (dwOffset = 0; dwOffset < device->regspace.sizebytes; dwOffset += 4)
+    {
+        if (dwOffset % regsPerLine == 0)
+        {
+           printString(pFile, "    0x%08x   ", dwOffset);
+        }
+
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (dwOffset >> 2), &value);
+
+        printString(pFile, " 0x%08x", value);
+
+        if (((dwOffset + 4) % regsPerLine == 0) && ((dwOffset + 4) < device->regspace.sizebytes))
+        {
+           printString(pFile, "\n");
+        }
+    }
+
+    printString(pFile, "\nEnd_RegisterSpace\n");
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+Yamato_DumpAllocateMemory(unsigned int dwSize, unsigned int dwFlags, unsigned int dwAddress,
+    unsigned int dwActualSize)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "AllocateMemory, size=%d, flags=0x%x, address=0x%x, actualSize=%d\n",
+        dwSize, dwFlags, dwAddress, dwActualSize);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpFreeMemory(unsigned int dwAddress)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "FreeMemory, address=0x%x\n", dwAddress);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void 
+Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+    unsigned int dwNumDWORDs;
+    unsigned int dwIndex;
+    unsigned int *pDataPtr;
+
+    printString(pFile, "StartWriteMemory, address=0x%x, size=%d\n", dwAddress, dwSize);
+
+    // Now write the data, in dwNumDWORDs
+    dwNumDWORDs = dwSize >> 2;
+
+    // If there are spillover bytes into the next dword, increment the amount dumped out here.
+    // The reader needs to take care of not overwriting the nonvalid bytes
+    if((dwSize % 4) != 0)
+        dwNumDWORDs++;
+
+    for (dwIndex = 0, pDataPtr = (unsigned int *)pData; dwIndex < dwNumDWORDs; dwIndex++, pDataPtr++)
+    {
+        WriteDWORD2(pFile, *pDataPtr);
+    }
+
+    printString(pFile, "EndWriteMemory\n");
+
+    fclose(pFile);
+}
+
+void 
+Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData)
+{
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+//    unsigned int* pDataPtr;
+
+    printString(pFile, "SetMemory, address=0x%x, size=%d, value=0x%x\n",
+        dwAddress, dwSize, pData);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+void 
+Yamato_ConvertIBAddr(unsigned int dwHeader, unsigned int *pBuffer, int gpuToHost)
+{
+    unsigned int hostaddr;
+    unsigned int *ibend;
+    unsigned int *addr;
+    unsigned int *ib    = pBuffer;
+    pm4_type3    header = *((pm4_type3*) &dwHeader);
+
+    // convert ib1 base address
+    if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) ||
+       (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD))
+    {
+        if (gpuToHost)
+        {
+            // from gpu to host
+            *ib = kgsl_sharedmem_convertaddr(*ib, 0);
+
+            hostaddr = *ib;
+        }
+        else
+        {
+            // from host to gpu
+            hostaddr = *ib;
+            *ib = kgsl_sharedmem_convertaddr(*ib, 1);
+        }
+
+        // walk through ib1 and convert any ib2 base address
+
+        ib    = (unsigned int *) hostaddr;
+        ibend = (unsigned int *) (ib + *(++pBuffer));
+
+        while (ib < ibend)
+        {
+            dwHeader = *(ib);
+            header   = *((pm4_type3*) (&dwHeader));
+
+            switch(dwHeader & PM4_PKT_MASK)
+            {
+            case PM4_TYPE0_PKT:
+                ib += header.count + 2;
+                break;
+
+            case PM4_TYPE1_PKT:
+                break;
+
+            case PM4_TYPE2_PKT:
+                ib++;
+                break;
+
+            case PM4_TYPE3_PKT:
+                if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) ||
+                   (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD))
+                {
+                    addr = ib + 1;
+                    if (gpuToHost)
+                    {
+                        // from gpu to host
+                        *addr = kgsl_sharedmem_convertaddr(*addr, 0);
+                    }
+                    else
+                    {
+                        // from host to gpu
+                        *addr = kgsl_sharedmem_convertaddr(*addr, 1);
+                    }
+                }
+                ib += header.count + 2;
+                break;
+            }
+        }
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpPM4(unsigned int* pBuffer, unsigned int sizeDWords)
+{
+    unsigned int *pBufferEnd = pBuffer + sizeDWords;
+    unsigned int *tmp;
+
+    // Open file
+    FILE* pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "Start_PM4Buffer\n");//, count=%d\n", sizeDWords);
+
+    // So look at the first unsigned int - should be a header
+    while(pBuffer < pBufferEnd)
+    {
+        unsigned int dwHeader = *(pBuffer++);
+
+        //printString(pFile, "  Start_Packet\n");
+        switch(dwHeader & PM4_PKT_MASK)
+        {
+            case PM4_TYPE0_PKT:
+                WritePM4Packet_Type0(pFile, dwHeader, &pBuffer);
+                break;
+
+            case PM4_TYPE1_PKT:
+                break;
+
+            case PM4_TYPE2_PKT:
+                WritePM4Packet_Type2(pFile, dwHeader, &pBuffer);
+                break;
+
+            case PM4_TYPE3_PKT:
+                indirectionLevel = 0;
+                tmp = pBuffer;
+                Yamato_ConvertIBAddr(dwHeader, tmp, 1);
+                WritePM4Packet_Type3(pFile, dwHeader, &pBuffer);
+                Yamato_ConvertIBAddr(dwHeader, tmp, 0);
+                break;
+        }
+        //printString(pFile, "  End_Packet\n");
+    }
+
+    printString(pFile, "End_PM4Buffer\n");
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value)
+{
+    FILE *pFile;
+
+    // Build a Type-0 packet that maps to this register write
+    unsigned int pBuffer[100], *pBuf = &pBuffer[1];
+
+    // Don't dump CP_RB_WPTR (switch statement may be necessary here for future additions)
+    if(dwAddress == mmCP_RB_WPTR)
+        return;
+
+    pFile = fopen(PM4_DUMPFILE, "a");
+
+    pBuffer[0] = dwAddress;
+    pBuffer[1] = value;
+
+    printString(pFile, "StartRegisterWrite\n");
+    WritePM4Packet_Type0(pFile, pBuffer[0], &pBuf);
+    printString(pFile, "EndRegisterWrite\n");
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpFbStart(gsl_device_t *device)
+{
+    FILE *pFile;
+
+    static int firstCall = 0;
+
+    // We only want to call this once
+    if(firstCall)
+        return;
+
+    pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "FbStart, value=0x%x\n", device->mmu.mpu_base);
+    printString(pFile, "FbSize, value=0x%x\n", device->mmu.mpu_range);
+
+    fclose(pFile);
+
+    firstCall = 1;
+}
+
+//----------------------------------------------------------------------------
+
+void
+Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height)
+{
+    FILE *pFile;
+
+    pFile = fopen(PM4_DUMPFILE, "a");
+
+    printString(pFile, "DumpWindow, addr=0x%x, width=0x%x, height=0x%x\n", addr, width, height);
+
+    fclose(pFile);
+}
+
+//----------------------------------------------------------------------------
+#ifdef _DEBUG
+
+#define ADDRESS_STACK_SIZE 256
+#define GET_PM4_TYPE3_OPCODE(x) ((*(x) >> 8) & 0xFF)
+#define IF_REGISTER_IN_RANGE(reg, base, count)         \
+    offset = (reg) - (base);                           \
+    if(offset >= 0 && offset <= (count) - 2)
+#define GET_CP_CONSTANT_DATA(x) (*((x) + offset + 2))
+
+static const char format2bpp[] =
+{
+    2,  // COLORX_4_4_4_4 
+    2,  // COLORX_1_5_5_5 
+    2,  // COLORX_5_6_5 
+    1,  // COLORX_8 
+    2,  // COLORX_8_8 
+    4,  // COLORX_8_8_8_8 
+    4,  // COLORX_S8_8_8_8 
+    2,  // COLORX_16_FLOAT 
+    4,  // COLORX_16_16_FLOAT 
+    8,  // COLORX_16_16_16_16_FLOAT 
+    4,  // COLORX_32_FLOAT 
+    8,  // COLORX_32_32_FLOAT 
+    16, // COLORX_32_32_32_32_FLOAT ,
+    1,  // COLORX_2_3_3 
+    3,  // COLORX_8_8_8
+};
+
+static unsigned int kgsl_dumpx_addr_count = 0; //unique command buffer addresses encountered
+static int kgsl_dumpx_handle_type3(unsigned int* hostaddr, int count)
+{
+    // For swap detection we need to find the below declared static values, and detect DI during EDRAM copy
+    static unsigned int width = 0, height = 0, format = 0, baseaddr = 0, iscopy = 0;
+
+    static unsigned int addr_stack[ADDRESS_STACK_SIZE];
+    static unsigned int size_stack[ADDRESS_STACK_SIZE];
+    int swap = 0; // have we encountered a swap during recursion (return value)
+
+    switch(GET_PM4_TYPE3_OPCODE(hostaddr))
+    {
+        case PM4_INDIRECT_BUFFER_PFD:
+        case PM4_INDIRECT_BUFFER:
+        {
+            // traverse indirect buffers
+            unsigned int i;
+            unsigned int ibaddr = *(hostaddr+1);
+            unsigned int ibsize = *(hostaddr+2);
+            
+            // is this address already in encountered?
+            for(i = 0; i < kgsl_dumpx_addr_count && addr_stack[i] != ibaddr; i++);
+            
+            if(kgsl_dumpx_addr_count == i)
+            {
+                // yes it was, store the address so we don't dump this buffer twice
+                addr_stack[kgsl_dumpx_addr_count] = ibaddr;
+                // just for sanity checking
+                size_stack[kgsl_dumpx_addr_count++] = ibsize; 
+                KOS_ASSERT(kgsl_dumpx_addr_count < ADDRESS_STACK_SIZE);
+
+                // recursively follow the indirect link and update swap if indirect buffer had resolve
+                swap |= kgsl_dumpx_parse_ibs(ibaddr, ibsize); 
+            }
+            else
+            {
+                KOS_ASSERT(size_stack[i] == ibsize);
+            }
+        } 
+        break;
+
+        case PM4_SET_CONSTANT:
+        if((*(hostaddr+1) >> 16) == 0x4)
+        {   
+            // parse register writes, and figure out framebuffer configuration
+
+            unsigned int regaddr = (*(hostaddr + 1) & 0xFFFF) + 0x2000; //dword address in register space
+            int offset; // used by the macros
+
+            IF_REGISTER_IN_RANGE(mmPA_SC_WINDOW_SCISSOR_BR, regaddr, count)
+            {
+                // found write to PA_SC_WINDOW_SCISSOR_BR, we use this to detect current
+                // width and height of the framebuffer (TODO: find more reliable way of achieving this)
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                width  = data & 0xFFFF;
+                height = data >> 16;
+            }
+            
+            IF_REGISTER_IN_RANGE(mmRB_MODECONTROL, regaddr, count)
+            {
+                // found write to RB_MODECONTROL, we use this to find out if next DI is resolve
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                iscopy = (data & RB_MODECONTROL__EDRAM_MODE_MASK) == (EDRAM_COPY << RB_MODECONTROL__EDRAM_MODE__SHIFT);
+            }
+
+            IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_BASE, regaddr, count)
+            {
+                // found write to RB_COPY_DEST_BASE, we use this to find out the framebuffer base address
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                baseaddr = (data & RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK);
+            }
+
+            IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_INFO, regaddr, count)
+            {
+               // found write to RB_COPY_DEST_INFO, we use this to find out the framebuffer format
+                unsigned int data = GET_CP_CONSTANT_DATA(hostaddr);
+                format = (data & RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT;
+            }             
+        }
+        break;
+
+        case PM4_DRAW_INDX:
+        case PM4_DRAW_INDX_2:
+        {
+            // DI found
+            // check if it is resolve
+            if(iscopy && !swap)
+            {
+                // printf("resolve: %ix%i @ 0x%08x, format = 0x%08x\n", width, height, baseaddr, format);
+                KOS_ASSERT(format < 15);
+
+                // yes it was and we need to update color buffer config because this is the first bin
+                // dumpx framebuffer base address, and dimensions
+                KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_AWH, (unsigned int)baseaddr, width, height, " ");
+
+                // find aligned width
+                width = (width + 31) & ~31;
+
+                //dump bytes-per-pixel and aligned width
+                KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_FS, format2bpp[format], width, 0, " ");
+                swap = 1;
+            }
+            
+        }
+        break;
+
+        default:
+        break;
+    }
+    return swap;
+}
+           
+// Traverse IBs and dump them to test vector. Detect swap by inspecting register 
+// writes, keeping note of the current state, and dump framebuffer config to test vector 
+int kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords)
+{
+    static unsigned int level = 0; //recursion level
+
+    int swap = 0; // have we encountered a swap during recursion (return value)
+    unsigned int *hostaddr;
+    int dwords_left = sizedwords; //dwords left in the current command buffer
+
+    level++;
+
+    KOS_ASSERT(sizeof(unsigned int *) == sizeof(unsigned int));
+    KOS_ASSERT(level <= 2);
+    hostaddr = (unsigned int *)kgsl_sharedmem_convertaddr(gpuaddr, 0);    
+
+    // dump the IB to test vector
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, gpuaddr, (unsigned int)hostaddr, sizedwords*4, "kgsl_dumpx_write_ibs"));
+
+    while(dwords_left)
+    {
+        int count = 0; //dword count including packet header
+
+        switch(*hostaddr >> 30)
+        {
+        case 0x0: // type-0
+            count = (*hostaddr >> 16)+2;
+            break;
+        case 0x1: // type-1
+            count = 2;
+            break;
+        case 0x3: // type-3
+            count = ((*hostaddr >> 16) & 0x3fff) + 2;
+            swap |= kgsl_dumpx_handle_type3(hostaddr, count);
+            break; // type-3
+        default:
+            KOS_ASSERT(!"unknown packet type");
+        }
+        
+        // jump to next packet
+        dwords_left -= count;
+        hostaddr += count;
+        KOS_ASSERT(dwords_left >= 0 && "PM4 parsing error");
+    }
+
+    level--;
+
+    // if this is the starting level of recursion, we are done. clean-up
+    if(level == 0) kgsl_dumpx_addr_count = 0;
+
+    return swap;
+}
+#endif
+
+#endif // WIN32
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_device.c b/drivers/mxc/amd-gpu/common/gsl_device.c
new file mode 100644
index 00000000000..6c41d3dd6dc
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_device.c
@@ -0,0 +1,694 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+#include "gsl_hal.h"
+#ifdef _LINUX
+#include <linux/sched.h>
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+//  inline functions
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE void
+kgsl_device_getfunctable(gsl_deviceid_t device_id, gsl_functable_t *ftbl)
+{
+    switch (device_id)
+    {
+#ifdef GSL_BLD_YAMATO
+    case GSL_DEVICE_YAMATO:
+        kgsl_yamato_getfunctable(ftbl);
+        break;
+#endif // GSL_BLD_YAMATO
+#ifdef GSL_BLD_G12
+    case GSL_DEVICE_G12:
+        kgsl_g12_getfunctable(ftbl);
+        break;
+#endif // GSL_BLD_G12
+    default:
+        break;
+    }
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id)
+{
+    int              status = GSL_SUCCESS;
+    gsl_devconfig_t  config;
+    gsl_hal_t        *hal = (gsl_hal_t *)gsl_driver.hal;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_init(gsl_device_t *device=0x%08x, gsl_deviceid_t device_id=%D )\n", device, device_id );
+
+    if ((GSL_DEVICE_YAMATO == device_id) && !(hal->has_z430)) {
+	return GSL_FAILURE_NOTSUPPORTED;
+    }
+
+    if ((GSL_DEVICE_G12 == device_id) && !(hal->has_z160)) {
+	return GSL_FAILURE_NOTSUPPORTED;
+    }
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    kos_memset(device, 0, sizeof(gsl_device_t));
+
+    // if device configuration is present
+    if (kgsl_hal_getdevconfig(device_id, &config) == GSL_SUCCESS)
+    {
+        kgsl_device_getfunctable(device_id, &device->ftbl);
+
+        kos_memcpy(&device->regspace,  &config.regspace,  sizeof(gsl_memregion_t));
+#ifdef GSL_BLD_YAMATO
+        kos_memcpy(&device->gmemspace, &config.gmemspace, sizeof(gsl_memregion_t));
+#endif // GSL_BLD_YAMATO
+
+        device->refcnt        = 0;
+        device->id            = device_id;
+
+#ifndef GSL_NO_MMU
+        device->mmu.config    = config.mmu_config;
+        device->mmu.mpu_base  = config.mpu_base;
+        device->mmu.mpu_range = config.mpu_range;
+        device->mmu.va_base   = config.va_base;
+        device->mmu.va_range  = config.va_range;
+#endif
+
+        if (device->ftbl.device_init)
+        {
+            status = device->ftbl.device_init(device);
+        }
+        else
+        {
+            status = GSL_FAILURE_NOTINITIALIZED;
+        }
+
+        // allocate memory store
+        status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS, sizeof(gsl_devmemstore_t), &device->memstore);
+
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+        {
+            // dumpx needs this to be in EMEM0 aperture
+            kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET());
+            status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE, sizeof(gsl_devmemstore_t), &device->memstore);
+        });
+
+        if (status != GSL_SUCCESS)
+        {
+            kgsl_device_stop(device->id);
+            return (status);
+        }
+        kgsl_sharedmem_set0(&device->memstore, 0, 0, device->memstore.size);
+
+        // init memqueue
+        device->memqueue.head = NULL;
+        device->memqueue.tail = NULL;
+
+        // init cmdstream
+        status = kgsl_cmdstream_init(device);
+        if (status != GSL_SUCCESS)
+        {
+            kgsl_device_stop(device->id);
+            return (status);
+        }
+
+#ifndef _LINUX		
+        // Create timestamp event
+        device->timestamp_event = kos_event_create(0);
+        if( !device->timestamp_event )
+        {
+            kgsl_device_stop(device->id);
+            return (status);
+        }
+#else
+		// Create timestamp wait queue
+		init_waitqueue_head(&device->timestamp_waitq);
+#endif	
+
+        //
+        //  Read the chip ID after the device has been initialized.
+        //
+        device->chip_id       = kgsl_hal_getchipid(device->id);
+    }
+
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_close(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE_NOTINITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_close(gsl_device_t *device=0x%08x )\n", device );
+
+    if (!(device->flags & GSL_FLAGS_INITIALIZED)) {
+	return status;
+    }
+
+    /* make sure the device is stopped before close
+       kgsl_device_close is only called for last running caller process
+    */
+    while (device->refcnt > 0) {
+	GSL_API_MUTEX_UNLOCK();
+	kgsl_device_stop(device->id);
+	GSL_API_MUTEX_LOCK();
+    }
+
+    // close cmdstream
+    status = kgsl_cmdstream_close(device);
+    if( status != GSL_SUCCESS ) return status;
+
+    if (device->ftbl.device_close) {
+	status = device->ftbl.device_close(device);
+    }
+
+    // DumpX allocates memstore from MMU aperture
+    if ((device->refcnt == 0) && device->memstore.hostptr
+	&& !(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX))
+    {
+	kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET());
+    }
+
+#ifndef _LINUX	
+    // destroy timestamp event
+    if(device->timestamp_event)
+    {
+        kos_event_signal(device->timestamp_event);  // wake up waiting threads before destroying the structure
+        kos_event_destroy( device->timestamp_event );
+        device->timestamp_event = 0;
+    }
+#else
+    wake_up_interruptible_all(&(device->timestamp_waitq));
+#endif	
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_close. Return value %B\n", status );
+    
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_destroy(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE_NOTINITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_destroy(gsl_device_t *device=0x%08x )\n", device );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_destroy)
+        {
+            status = device->ftbl.device_destroy(device);
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_destroy. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid)
+{
+    int  status = GSL_SUCCESS;
+    int  pindex;
+
+#ifndef GSL_NO_MMU
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_attachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS)
+        {
+            device->callerprocess[pindex] = pid;
+
+            status = kgsl_mmu_attachcallback(&device->mmu, pid);
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_attachcallback. Return value: %B\n", status );
+
+#else
+    (void)pid;
+    (void)device;
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid)
+{
+    int  status = GSL_SUCCESS;
+    int  pindex;
+
+#ifndef GSL_NO_MMU
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_detachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS)
+        {
+            status |= kgsl_mmu_detachcallback(&device->mmu, pid);
+
+            device->callerprocess[pindex] = 0;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_detachcallback. Return value: %B\n", status );
+
+#else
+    (void)pid;
+    (void)device;
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int           status  = GSL_SUCCESS;
+    gsl_device_t  *device = &gsl_driver.device[device_id-1];        // device_id is 1 based
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_getproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes );
+
+    KOS_ASSERT(value);
+
+#ifndef _DEBUG
+    (void) sizebytes;       // unreferenced formal parameter
+#endif
+
+    switch (type)
+    {
+    case GSL_PROP_SHMEM:
+        {
+        gsl_shmemprop_t  *shem = (gsl_shmemprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_shmemprop_t));
+
+        shem->numapertures   = gsl_driver.shmem.numapertures;
+        shem->aperture_mask  = GSL_APERTURE_MASK;
+        shem->aperture_shift = GSL_APERTURE_SHIFT;
+
+        break;
+        }
+
+    case GSL_PROP_SHMEM_APERTURES:
+        {
+        int i;
+        gsl_apertureprop_t  *aperture = (gsl_apertureprop_t *) value;
+
+        KOS_ASSERT(sizebytes == (sizeof(gsl_apertureprop_t) * gsl_driver.shmem.numapertures));
+
+        for (i = 0; i < gsl_driver.shmem.numapertures; i++)
+        {
+            if (gsl_driver.shmem.apertures[i].memarena)
+            {
+                aperture->gpuaddr  = GSL_APERTURE_GETGPUADDR(gsl_driver.shmem, i);
+                aperture->hostaddr = GSL_APERTURE_GETHOSTADDR(gsl_driver.shmem, i);
+            }
+            else
+            {
+                aperture->gpuaddr  = 0x0;
+                aperture->hostaddr = 0x0;
+            }
+            aperture++;
+        }
+
+        break;
+        }
+
+    case GSL_PROP_DEVICE_SHADOW:
+        {
+        gsl_shadowprop_t  *shadowprop = (gsl_shadowprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_shadowprop_t));
+
+        kos_memset(shadowprop, 0, sizeof(gsl_shadowprop_t));
+
+#ifdef  GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+        if (device->memstore.hostptr)
+        {
+            shadowprop->hostaddr = (unsigned int) device->memstore.hostptr;
+            shadowprop->size     = device->memstore.size;
+            shadowprop->flags    = GSL_FLAGS_INITIALIZED;
+        }
+#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+
+        break;
+        }
+
+    default:
+        {
+        if (device->ftbl.device_getproperty)
+        {
+            status = device->ftbl.device_getproperty(device, type, value, sizebytes);
+        }
+
+        break;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_getproperty. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int           status = GSL_SUCCESS;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_setproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes );
+
+    KOS_ASSERT(value);
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_setproperty)
+        {
+            status = device->ftbl.device_setproperty(device, type, value, sizebytes);
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_setproperty. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+    gsl_hal_t     *hal = (gsl_hal_t *)gsl_driver.hal;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_start(gsl_deviceid_t device_id=%D, gsl_flags_t flags=%d)\n", device_id, flags );
+
+    GSL_API_MUTEX_LOCK();
+
+    if ((GSL_DEVICE_G12 == device_id) && !(hal->has_z160)) {
+	GSL_API_MUTEX_UNLOCK();
+	return GSL_FAILURE_NOTSUPPORTED;
+    }
+
+    if ((GSL_DEVICE_YAMATO == device_id) && !(hal->has_z430)) {
+	GSL_API_MUTEX_UNLOCK();
+	return GSL_FAILURE_NOTSUPPORTED;
+    }
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+    
+    kgsl_device_active(device);
+    
+    if (!(device->flags & GSL_FLAGS_INITIALIZED))
+    {
+        GSL_API_MUTEX_UNLOCK();
+
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_ERROR, "ERROR: Trying to start uninitialized device.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    device->refcnt++;
+
+    if (device->flags & GSL_FLAGS_STARTED)
+    {
+        GSL_API_MUTEX_UNLOCK();
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    // start device in safe mode
+    if (flags & GSL_FLAGS_SAFEMODE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_INFO, "Running the device in safe mode.\n" );
+        device->flags |= GSL_FLAGS_SAFEMODE;
+    }
+
+    if (device->ftbl.device_start)
+    {
+        status = device->ftbl.device_start(device, flags);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_stop(gsl_deviceid_t device_id)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_stop(gsl_deviceid_t device_id=%D)\n", device_id );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (device->flags & GSL_FLAGS_STARTED)
+    {
+        KOS_ASSERT(device->refcnt);
+
+        device->refcnt--;
+
+        if (device->refcnt == 0)
+        {
+            if (device->ftbl.device_stop)
+            {
+                status = device->ftbl.device_stop(device);
+            }
+        }
+        else
+        {
+            status = GSL_SUCCESS;
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_stop. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_idle(gsl_deviceid_t device_id=%D, unsigned int timeout=%d)\n", device_id, timeout );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    kgsl_device_active(device);
+    
+    if (device->ftbl.device_idle)
+    {
+        status = device->ftbl.device_idle(device, timeout);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_idle. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_isidle(gsl_deviceid_t device_id)
+{
+	gsl_timestamp_t retired = kgsl_cmdstream_readtimestamp0(device_id, GSL_TIMESTAMP_RETIRED);
+	gsl_timestamp_t consumed = kgsl_cmdstream_readtimestamp0(device_id, GSL_TIMESTAMP_CONSUMED);
+	gsl_timestamp_t ts_diff = retired - consumed;
+	return (ts_diff >= 0) || (ts_diff < -GSL_TIMESTAMP_EPSILON) ? GSL_SUCCESS : GSL_FAILURE;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+
+#ifdef GSL_LOG
+    if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR ) // Would otherwise flood the log
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                        "--> int kgsl_device_regread(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int *value=0x%08x)\n", device_id, offsetwords, value );
+#endif
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    KOS_ASSERT(value);
+    KOS_ASSERT(offsetwords < device->regspace.sizebytes);
+
+    if (device->ftbl.device_regread)
+    {
+        status = device->ftbl.device_regread(device, offsetwords, value);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+#ifdef GSL_LOG
+    if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR )
+        kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regread. Return value %B\n", status );
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_regwrite(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int value=0x%08x)\n", device_id, offsetwords, value );
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    KOS_ASSERT(offsetwords < device->regspace.sizebytes);
+
+    if (device->ftbl.device_regwrite)
+    {
+        status = device->ftbl.device_regwrite(device, offsetwords, value);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regwrite. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout)
+{
+    int           status = GSL_FAILURE_NOTINITIALIZED;
+    gsl_device_t  *device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_waitirq(gsl_deviceid_t device_id=%D, gsl_intrid_t intr_id=%d, unsigned int *count=0x%08x, unsigned int timout=0x%08x)\n", device_id, intr_id, count, timeout);
+
+    GSL_API_MUTEX_LOCK();
+
+    device = &gsl_driver.device[device_id-1];       // device_id is 1 based
+
+    if (device->ftbl.device_waitirq)
+    {
+        status = device->ftbl.device_waitirq(device, intr_id, count, timeout);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_waitirq. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_device_runpending(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE_NOTINITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_device_runpending(gsl_device_t *device=0x%08x )\n", device );
+
+    if (device->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (device->ftbl.device_runpending)
+        {
+            status = device->ftbl.device_runpending(device);
+        }
+    }
+
+    // free any pending freeontimestamps
+    kgsl_cmdstream_memqueue_drain(device);
+
+    kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_runpending. Return value %B\n", status );
+
+    return (status);
+}
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_drawctxt.c b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c
new file mode 100644
index 00000000000..1e8fa1a4962
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c
@@ -0,0 +1,1828 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#ifdef _LINUX
+#include <asm/div64.h>
+#endif
+
+#ifdef GSL_BLD_YAMATO
+
+//////////////////////////////////////////////////////////////////////////////
+//
+// Memory Map for Register, Constant & Instruction Shadow, and Command Buffers (34.5KB)
+//
+// +---------------------+------------+-------------+---+---------------------+
+// | ALU Constant Shadow | Reg Shadow | C&V Buffers |Tex| Shader Instr Shadow |
+// +---------------------+------------+-------------+---+---------------------+
+//   ________________________________'               '___________________
+//  '                                                                    '
+// +--------------+-----------+------+-----------+------------------------+
+// | Restore Regs | Save Regs | Quad | Gmem Save | Gmem Restore | unused  |
+// +--------------+-----------+------+-----------+------------------------+
+//
+//       8K - ALU Constant Shadow (8K aligned)
+//       4K - H/W Register Shadow (8K aligned)
+//       9K - Command and Vertex Buffers
+//              - Indirect command buffer : Const/Reg restore
+//                      - includes Loop & Bool const shadows
+//              - Indirect command buffer : Const/Reg save
+//              - Quad vertices & texture coordinates
+//              - Indirect command buffer : Gmem save
+//              - Indirect command buffer : Gmem restore
+//              - Unused (padding to 8KB boundary)
+//      <1K - Texture Constant Shadow (768 bytes) (8K aligned)
+//      18K - Shader Instruction Shadow
+//              - 6K vertex (32 byte aligned)
+//              - 6K pixel  (32 byte aligned)
+//              - 6K shared (32 byte aligned)
+//
+// Note: Reading constants into a shadow, one at a time using REG_TO_MEM, takes
+// 3 DWORDS per DWORD transfered, plus 1 DWORD for the shadow, for a total of
+// 16 bytes per constant.  If the texture constants were transfered this way,
+// the Command & Vertex Buffers section would extend past the 16K boundary.
+// By moving the texture constant shadow area to start at 16KB boundary, we
+// only require approximately 40 bytes more memory, but are able to use the
+// LOAD_CONSTANT_CONTEXT shadowing feature for the textures, speeding up
+// context switching.
+//
+// [Using LOAD_CONSTANT_CONTEXT shadowing feature for the Loop and/or Bool
+// constants would require an additional 8KB each, for alignment.]
+//
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// Constants
+//////////////////////////////////////////////////////////////////////////////
+
+#define ALU_CONSTANTS           2048                // DWORDS
+#define NUM_REGISTERS           1024                // DWORDS
+#ifdef DISABLE_SHADOW_WRITES
+    #define CMD_BUFFER_LEN          9216            // DWORDS
+#else
+    #define CMD_BUFFER_LEN          3072            // DWORDS
+#endif
+#define TEX_CONSTANTS           (32*6)              // DWORDS
+#define BOOL_CONSTANTS          8                   // DWORDS
+#define LOOP_CONSTANTS          56                  // DWORDS
+#define SHADER_INSTRUCT_LOG2    9U                  // 2^n == SHADER_INSTRUCTIONS
+
+#if defined(PM4_IM_STORE)
+#define SHADER_INSTRUCT         (1<<SHADER_INSTRUCT_LOG2)   // 96-bit instructions
+#else
+#define SHADER_INSTRUCT         0
+#endif
+
+// LOAD_CONSTANT_CONTEXT shadow size
+#define LCC_SHADOW_SIZE         0x2000              // 8KB
+
+#define ALU_SHADOW_SIZE         LCC_SHADOW_SIZE     // 8KB
+#define REG_SHADOW_SIZE         0x1000              // 4KB
+#ifdef DISABLE_SHADOW_WRITES
+    #define CMD_BUFFER_SIZE         0x9000          // 36KB
+#else
+    #define CMD_BUFFER_SIZE         0x3000          // 12KB
+#endif
+#define TEX_SHADOW_SIZE         (TEX_CONSTANTS*4)   // 768 bytes
+#define SHADER_SHADOW_SIZE      (SHADER_INSTRUCT*12)// 6KB
+
+#define REG_OFFSET              LCC_SHADOW_SIZE
+#define CMD_OFFSET              (REG_OFFSET + REG_SHADOW_SIZE)
+#define TEX_OFFSET              (CMD_OFFSET + CMD_BUFFER_SIZE)
+#define SHADER_OFFSET           ((TEX_OFFSET + TEX_SHADOW_SIZE + 32) & ~31)
+
+#define CONTEXT_SIZE            (SHADER_OFFSET + 3 * SHADER_SHADOW_SIZE)
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_LOCKING_FINEGRAIN
+#define GSL_CONTEXT_MUTEX_CREATE()          device->drawctxt_mutex = kos_mutex_create("gsl_drawctxt"); \
+                                            if (!device->drawctxt_mutex) {return (GSL_FAILURE);}
+#define GSL_CONTEXT_MUTEX_LOCK()            kos_mutex_lock(device->drawctxt_mutex)
+#define GSL_CONTEXT_MUTEX_UNLOCK()          kos_mutex_unlock(device->drawctxt_mutex)
+#define GSL_CONTEXT_MUTEX_FREE()            kos_mutex_free(device->drawctxt_mutex); device->drawctxt_mutex = 0;
+#else
+#define GSL_CONTEXT_MUTEX_CREATE()
+#define GSL_CONTEXT_MUTEX_LOCK()
+#define GSL_CONTEXT_MUTEX_UNLOCK()
+#define GSL_CONTEXT_MUTEX_FREE()
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// temporary work structure
+//////////////////////////////////////////////////////////////////////////////
+
+typedef struct
+{
+    unsigned int    *start;         // Command & Vertex buffer start
+    unsigned int    *cmd;           // Next available dword in C&V buffer
+
+    // address of buffers, needed when creating IB1 command buffers.
+    gpuaddr_t       bool_shadow;    // Address where bool constants are shadowed
+    gpuaddr_t       loop_shadow;    // Address where loop constants are shadowed
+
+#if defined(PM4_IM_STORE)
+    gpuaddr_t       shader_shared;  // Address of shared shader instruction shadow
+    gpuaddr_t       shader_vertex;  // Address of vertex shader instruction shadow
+    gpuaddr_t       shader_pixel;   // Address of pixel shader instruction shadow
+#endif
+
+    gpuaddr_t       reg_values[2];  // Addresses in command buffer where separately handled registers are saved
+    gpuaddr_t       chicken_restore;// Address where the TP0_CHICKEN register value is written
+    gpuaddr_t       gmem_base;      // Base gpu address of GMEM
+}
+ctx_t;
+
+//////////////////////////////////////////////////////////////////////////////
+// Helper function to calculate IEEE754 single precision float values without FPU
+//////////////////////////////////////////////////////////////////////////////
+unsigned int uint2float( unsigned int uintval )
+{
+    unsigned int exp = 0;
+    unsigned int frac = 0;
+    unsigned int u = uintval;
+
+    // Handle zero separately
+    if( uintval == 0 ) return 0;
+
+    // Find log2 of u
+    if(u>=0x10000) { exp+=16; u>>=16; }
+    if(u>=0x100  ) { exp+=8;  u>>=8;  }
+    if(u>=0x10   ) { exp+=4;  u>>=4;  }
+    if(u>=0x4    ) { exp+=2;  u>>=2;  }
+    if(u>=0x2    ) { exp+=1;  u>>=1;  }
+
+    // Calculate fraction
+    frac = ( uintval & ( ~( 1 << exp ) ) ) << ( 23 - exp );
+
+    // Exp is biased by 127 and shifted 23 bits
+    exp = ( exp + 127 ) << 23;
+
+    return ( exp | frac );
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// Helper function to divide two unsigned ints and return the result as a floating point value
+//////////////////////////////////////////////////////////////////////////////
+unsigned int uintdivide(unsigned int a, unsigned int b)
+{
+#ifdef _LINUX
+    uint64_t a_fixed = a << 16;
+    uint64_t b_fixed = b << 16;
+#else
+    unsigned int a_fixed = a << 16;
+    unsigned int b_fixed = b << 16;
+#endif
+    // Assume the result is 0.fraction
+    unsigned int fraction;
+    unsigned int exp = 126;
+
+    if( b == 0 ) return 0;
+
+#ifdef _LINUX
+    a_fixed = a_fixed << 32;
+	do_div(a_fixed, b_fixed);
+    fraction = (unsigned int)a_fixed;
+#else
+    fraction = ((unsigned int)((((__int64)a_fixed) << 32) / (__int64)b_fixed));
+#endif
+
+    if( fraction == 0 ) return 0;
+
+    // Normalize
+    while( !(fraction & (1<<31)) )
+    {
+        fraction <<= 1;
+        exp--;
+    }
+    // Remove hidden bit
+    fraction <<= 1;
+
+    // Round
+    if( ( fraction & 0x1ff ) > 256 )
+    {
+        int rounded = 0;
+        int i = 9;
+
+        // Do the bit addition
+        while( !rounded )
+        {
+            if( fraction & (1<<i) )
+            {
+                // 1b + 1b = 0b, carry = 1
+                fraction &= ~(1<<i);
+                i++;
+            }
+            else
+            {
+                fraction |= (1<<i);
+                rounded = 1;
+            }
+        }
+    }
+
+    // Use 23 most significant bits for the fraction
+    fraction >>= 9;
+
+    return ( ( exp << 23 ) | fraction );
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+//                  context save (gmem -> sys)
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled vertex shader program
+//
+// attribute vec4  P;
+// void main(void)
+// {
+//   gl_Position = P;
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define GMEM2SYS_VTX_PGM_LEN    0x12
+
+static const unsigned int gmem2sys_vtx_pgm[GMEM2SYS_VTX_PGM_LEN] = {
+    0x00011003, 0x00001000, 0xc2000000,
+    0x00001004, 0x00001000, 0xc4000000,
+    0x00001005, 0x00002000, 0x00000000,
+    0x1cb81000, 0x00398a88, 0x00000003,
+    0x140f803e, 0x00000000, 0xe2010100,
+    0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled fragment shader program
+//
+// precision highp float;
+// uniform   vec4  clear_color;
+// void main(void)
+// {
+//    gl_FragColor = clear_color;
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define GMEM2SYS_FRAG_PGM_LEN   0x0c
+
+static const unsigned int gmem2sys_frag_pgm[GMEM2SYS_FRAG_PGM_LEN] = {
+    0x00000000, 0x1002c400, 0x10000000,
+    0x00001003, 0x00002000, 0x00000000,
+    0x140f8000, 0x00000000, 0x22000000,
+    0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+//                  context restore (sys -> gmem)
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled vertex shader program
+//
+// attribute vec4 position;
+// attribute vec4 texcoord;
+// varying   vec4 texcoord0;
+// void main()
+// {
+//    gl_Position = position;
+//    texcoord0 = texcoord;
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define SYS2GMEM_VTX_PGM_LEN    0x18
+
+static const unsigned int sys2gmem_vtx_pgm[SYS2GMEM_VTX_PGM_LEN] = {
+    0x00052003, 0x00001000, 0xc2000000, 0x00001005,
+    0x00001000, 0xc4000000, 0x00001006, 0x10071000,
+    0x20000000, 0x18981000, 0x0039ba88, 0x00000003,
+    0x12982000, 0x40257b08, 0x00000002, 0x140f803e,
+    0x00000000, 0xe2010100, 0x140f8000, 0x00000000,
+    0xe2020200, 0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// pre-compiled fragment shader program
+//
+// precision mediump   float;
+// uniform   sampler2D tex0;
+// varying   vec4      texcoord0;
+// void main()
+// {
+//    gl_FragColor = texture2D(tex0, texcoord0.xy);
+// }
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#define SYS2GMEM_FRAG_PGM_LEN   0x0f
+
+static const unsigned int sys2gmem_frag_pgm[SYS2GMEM_FRAG_PGM_LEN] = {
+    0x00011002, 0x00001000, 0xc4000000, 0x00001003,
+    0x10041000, 0x20000000, 0x10000001, 0x1ffff688,
+    0x00000002, 0x140f8000, 0x00000000, 0xe2000000,
+    0x14000000, 0x00000000, 0xe2000000
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// shader texture constants (sysmem -> gmem)
+//////////////////////////////////////////////////////////////////////////////
+
+#define SYS2GMEM_TEX_CONST_LEN  6
+
+static unsigned int sys2gmem_tex_const[SYS2GMEM_TEX_CONST_LEN] =
+{
+    // Texture, FormatXYZW=Unsigned, ClampXYZ=Wrap/Repeat,RFMode=ZeroClamp-1,Dim=1:2d
+    0x00000002,  // Pitch = TBD
+
+    // Format=6:8888_WZYX, EndianSwap=0:None, ReqSize=0:256bit, DimHi=0, NearestClamp=1:OGL Mode
+    0x00000806,  // Address[31:12] = TBD
+
+    // Width, Height, EndianSwap=0:None
+    0, // Width & Height = TBD
+
+    // NumFormat=0:RF, DstSelXYZW=XYZW, ExpAdj=0, MagFilt=MinFilt=0:Point, Mip=2:BaseMap
+    0 << 1 | 1 << 4 | 2 << 7 | 3 << 10 | 2 << 23,
+
+    // VolMag=VolMin=0:Point, MinMipLvl=0, MaxMipLvl=1, LodBiasH=V=0, Dim3d=0
+    0,
+
+    // BorderColor=0:ABGRBlack, ForceBC=0:diable, TriJuice=0, Aniso=0, Dim=1:2d, MipPacking=0
+    1 << 9  // Mip Address[31:12] = TBD
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+// quad for copying GMEM to context shadow
+//////////////////////////////////////////////////////////////////////////////
+
+#define QUAD_LEN                12
+
+static unsigned int gmem_copy_quad[QUAD_LEN] = {
+    0x00000000, 0x00000000, 0x3f800000,
+    0x00000000, 0x00000000, 0x3f800000,
+    0x00000000, 0x00000000, 0x3f800000,
+    0x00000000, 0x00000000, 0x3f800000
+};
+
+#define TEXCOORD_LEN            8
+
+static unsigned int gmem_copy_texcoord[TEXCOORD_LEN] = {
+    0x00000000, 0x3f800000,
+    0x3f800000, 0x3f800000,
+    0x00000000, 0x00000000,
+    0x3f800000, 0x00000000
+};
+
+#define NUM_COLOR_FORMATS   13
+
+static SurfaceFormat surface_format_table[NUM_COLOR_FORMATS] =
+{
+	FMT_4_4_4_4,		   // COLORX_4_4_4_4
+	FMT_1_5_5_5,		   // COLORX_1_5_5_5
+	FMT_5_6_5,		       // COLORX_5_6_5
+	FMT_8,			       // COLORX_8
+	FMT_8_8,		       // COLORX_8_8
+	FMT_8_8_8_8,		   // COLORX_8_8_8_8
+	FMT_8_8_8_8,		   // COLORX_S8_8_8_8
+	FMT_16_FLOAT,		   // COLORX_16_FLOAT
+	FMT_16_16_FLOAT,	   // COLORX_16_16_FLOAT
+	FMT_16_16_16_16_FLOAT, // COLORX_16_16_16_16_FLOAT
+	FMT_32_FLOAT,		   // COLORX_32_FLOAT
+	FMT_32_32_FLOAT,	   // COLORX_32_32_FLOAT
+	FMT_32_32_32_32_FLOAT, // COLORX_32_32_32_32_FLOAT
+};
+
+static unsigned int format2bytesperpixel[NUM_COLOR_FORMATS] =
+{
+    2,  // COLORX_4_4_4_4
+	2,  // COLORX_1_5_5_5
+	2,  // COLORX_5_6_5
+	1,  // COLORX_8
+	2,  // COLORX_8_8_8
+	4,  // COLORX_8_8_8_8
+	4,  // COLORX_S8_8_8_8
+	2,  // COLORX_16_FLOAT
+	4,  // COLORX_16_16_FLOAT
+	8,  // COLORX_16_16_16_16_FLOAT
+	4,  // COLORX_32_FLOAT
+	8,  // COLORX_32_32_FLOAT
+	16, // COLORX_32_32_32_32_FLOAT
+};
+
+//////////////////////////////////////////////////////////////////////////////
+// shader linkage info
+//////////////////////////////////////////////////////////////////////////////
+
+#define SHADER_CONST_ADDR       (11 * 6 + 3)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// gmem command buffer length
+//////////////////////////////////////////////////////////////////////////////
+
+#define PM4_REG(reg)            ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg)))
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+config_gmemsize(gmem_shadow_t *shadow, int gmem_size)
+{
+    int w=64, h=64; // 16KB surface, minimum
+
+    // convert from bytes to 32-bit words
+    gmem_size = (gmem_size + 3)/4;
+
+    // find the right surface size, close to a square.
+    while (w * h < gmem_size)
+        if (w < h)
+            w *= 2;
+        else
+            h *= 2;
+
+    shadow->width  = w;
+    shadow->height = h;
+    shadow->pitch  = w;
+	shadow->format = COLORX_8_8_8_8;
+    shadow->size   = shadow->pitch * shadow->height * 4;
+
+	shadow->gmem_width  = w;
+	shadow->gmem_height = h;
+	shadow->gmem_pitch  = w;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int
+gpuaddr(unsigned int *cmd, gsl_memdesc_t *memdesc)
+{
+    return memdesc->gpuaddr + ((char *)cmd - (char *)memdesc->hostptr);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+create_ib1(gsl_drawctxt_t *drawctxt, unsigned int *cmd, unsigned int *start, unsigned int *end)
+{
+    cmd[0] = PM4_HDR_INDIRECT_BUFFER_PFD;
+    cmd[1] = gpuaddr(start, &drawctxt->gpustate);
+    cmd[2] = end - start;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int *
+program_shader(unsigned int *cmds, int vtxfrag, const unsigned int *shader_pgm, int dwords)
+{
+    // load the patched vertex shader stream
+    *cmds++ = pm4_type3_packet(PM4_IM_LOAD_IMMEDIATE, 2 + dwords);
+    *cmds++ = vtxfrag;                      // 0=vertex shader, 1=fragment shader
+    *cmds++ = ( (0 << 16) | dwords );       // instruction start & size (in 32-bit words)
+
+    kos_memcpy(cmds, shader_pgm, dwords<<2);
+    cmds += dwords;
+
+    return cmds;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int *
+reg_to_mem(unsigned int *cmds, gpuaddr_t dst, gpuaddr_t src, int dwords)
+{
+    while (dwords-- > 0)
+    {
+        *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+        *cmds++ = src++;
+        *cmds++ = dst;
+        dst += 4;
+    }
+
+    return cmds;
+}
+
+
+
+#ifdef DISABLE_SHADOW_WRITES
+
+static void build_reg_to_mem_range(unsigned int start, unsigned int end, unsigned int** cmd, gsl_drawctxt_t *drawctxt)
+{
+    unsigned int i = start;
+
+    for(i=start; i<=end; i++)
+    {
+        *(*cmd)++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+        *(*cmd)++ = i | (1<<30);
+        *(*cmd)++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) + (i-0x2000)*4;
+    }
+}
+
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+// chicken restore
+//////////////////////////////////////////////////////////////////////////////
+static unsigned int*
+build_chicken_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *start = ctx->cmd;
+    unsigned int *cmds = start;
+
+    *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmds++ = 0;
+
+    *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    ctx->chicken_restore = gpuaddr(cmds, &drawctxt->gpustate);
+    *cmds++ = 0x00000000;
+
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->chicken_restore, start, cmds);
+
+    return cmds;
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// context save
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// save h/w regs, alu constants, texture contants, etc. ...
+//   requires: bool_shadow_gpuaddr, loop_shadow_gpuaddr
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+build_regsave_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *start = ctx->cmd;
+    unsigned int *cmd = start;
+
+#ifdef DISABLE_SHADOW_WRITES
+    // Write HW registers into shadow
+    build_reg_to_mem_range(mmRB_SURFACE_INFO, mmRB_DEPTH_INFO, &cmd, drawctxt);
+    build_reg_to_mem_range(mmCOHER_DEST_BASE_0, mmPA_SC_SCREEN_SCISSOR_BR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_WINDOW_OFFSET, mmPA_SC_WINDOW_SCISSOR_BR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmVGT_MAX_VTX_INDX, mmRB_FOG_COLOR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmRB_STENCILREFMASK_BF, mmPA_CL_VPORT_ZOFFSET, &cmd, drawctxt);
+    build_reg_to_mem_range(mmSQ_PROGRAM_CNTL, mmSQ_WRAPPING_1, &cmd, drawctxt);
+    build_reg_to_mem_range(mmRB_DEPTHCONTROL, mmRB_MODECONTROL, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SU_POINT_SIZE, mmPA_SC_LINE_STIPPLE, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_VIZ_QUERY, mmPA_SC_VIZ_QUERY, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_LINE_CNTL, mmSQ_PS_CONST, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SC_AA_MASK, mmPA_SC_AA_MASK, &cmd, drawctxt);
+    build_reg_to_mem_range(mmVGT_VERTEX_REUSE_BLOCK_CNTL, mmRB_DEPTH_CLEAR, &cmd, drawctxt);
+    build_reg_to_mem_range(mmRB_SAMPLE_COUNT_CTL, mmRB_COLOR_DEST_MASK, &cmd, drawctxt);
+    build_reg_to_mem_range(mmPA_SU_POLY_OFFSET_FRONT_SCALE, mmPA_SU_POLY_OFFSET_BACK_OFFSET, &cmd, drawctxt);
+
+    // Copy ALU constants
+    cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr) & 0xFFFFE000, mmSQ_CONSTANT_0, ALU_CONSTANTS);
+
+    // Copy Tex constants
+    cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000, mmSQ_FETCH_0, TEX_CONSTANTS);
+#else
+    // H/w registers are already shadowed; just need to disable shadowing to prevent corruption.
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000;
+    *cmd++ = 4 << 16;                       // regs, start=0
+    *cmd++ = 0x0;                           // count = 0
+
+    // ALU constants are already shadowed; just need to disable shadowing to prevent corruption.
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000;
+    *cmd++ = 0 << 16;                       // ALU, start=0
+    *cmd++ = 0x0;                           // count = 0
+
+    // Tex constants are already shadowed; just need to disable shadowing to prevent corruption.
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000;
+    *cmd++ = 1 << 16;                       // Tex, start=0
+    *cmd++ = 0x0;                           // count = 0
+#endif
+
+
+
+
+    // Need to handle some of the registers separately
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSQ_GPR_MANAGEMENT;
+    *cmd++ = ctx->reg_values[0];
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmTP0_CHICKEN;
+    *cmd++ = ctx->reg_values[1];
+
+    // Copy Boolean constants
+    cmd = reg_to_mem(cmd, ctx->bool_shadow, mmSQ_CF_BOOLEANS, BOOL_CONSTANTS);
+
+    // Copy Loop constants
+    cmd = reg_to_mem(cmd, ctx->loop_shadow, mmSQ_CF_LOOP, LOOP_CONSTANTS);
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->reg_save, start, cmd);
+
+    ctx->cmd = cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// copy colour, depth, & stencil buffers from graphics memory to system memory
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int*
+build_gmem2sys_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow)
+{
+    unsigned int *cmds = shadow->gmem_save_commands;
+    unsigned int *start = cmds;
+
+    // Store TP0_CHICKEN register
+    *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmds++ = mmTP0_CHICKEN;
+    if( ctx )
+        *cmds++ = ctx->chicken_restore;
+    else
+        cmds++;
+
+    *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmds++ = 0;
+
+    // Set TP0_CHICKEN to zero
+    *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    *cmds++ = 0x00000000;
+
+    // --------------
+    // program shader
+    // --------------
+
+    // load shader vtx constants ... 5 dwords
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
+    *cmds++ = (0x1 << 16) | SHADER_CONST_ADDR;
+    *cmds++ = 0;
+    *cmds++ = shadow->quad_vertices.gpuaddr | 0x3;      // valid(?) vtx constant flag & addr
+    *cmds++ = 0x00000030;                   // limit = 12 dwords
+
+    // Invalidate L2 cache to make sure vertices are updated
+    *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1);
+    *cmds++ = 0x1;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
+    *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX);
+    *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX
+    *cmds++ = 0x0;        //mmVGT_MIN_VTX_INDX
+    *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_AA_MASK);
+    *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK
+
+
+    // load the patched vertex shader stream
+    cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN);
+
+    // Load the patched fragment shader stream
+    cmds = program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN);
+
+    // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL);
+    *cmds++ = 0x10010001;
+    *cmds++ = 0x00000008;
+
+
+    // --------------
+    // resolve
+    // --------------
+
+    // PA_CL_VTE_CNTL
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL);
+    *cmds++ = 0x00000b00;               // disable X/Y/Z transforms, X/Y/Z are premultiplied by W
+
+    // change colour buffer to RGBA8888, MSAA = 1, and matching pitch
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmRB_SURFACE_INFO);
+    *cmds++ = shadow->gmem_pitch;
+
+    // RB_COLOR_INFO        Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base
+    if( ctx )
+    {
+        KOS_ASSERT((ctx->gmem_base & 0xFFF) == 0);   // gmem base assumed 4K aligned.
+        *cmds++ = (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base;
+    }
+    else
+    {
+		unsigned int temp = *cmds;
+		*cmds++ = (temp & ~RB_COLOR_INFO__COLOR_FORMAT_MASK) | (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT);
+    }
+
+    // disable Z
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_DEPTHCONTROL);
+    *cmds++ = 0;
+
+    // set mmPA_SU_SC_MODE_CNTL
+    //      Front_ptype = draw triangles
+    //      Back_ptype = draw triangles
+    //      Provoking vertex = last
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL);
+    *cmds++ = 0x00080240;
+
+    // set the scissor to the extents of the draw surface
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL);
+    *cmds++ = (shadow->gmem_offset_y << 16) | shadow->gmem_offset_x;
+    *cmds++ = (shadow->gmem_height << 16) | shadow->gmem_width;
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL);
+    *cmds++ = (1U << 31) | (0 << 16) | 0;
+    *cmds++ = (shadow->height << 16) | shadow->width;
+
+    // load the viewport so that z scale = clear depth and z offset = 0.0f
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE);
+    *cmds++ = 0xbf800000; // -1.0f
+    *cmds++ = 0x0;
+
+    // load the COPY state
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 6);
+    *cmds++ = PM4_REG(mmRB_COPY_CONTROL);
+    *cmds++ = 0;                                                // RB_COPY_CONTROL
+
+    {
+        // Calculate the new offset based on the adjusted base
+		unsigned int bytesperpixel = format2bytesperpixel[shadow->format];
+		unsigned int addr = (shadow->gmemshadow.gpuaddr + shadow->offset * bytesperpixel);
+		unsigned int offset = (addr - (addr & 0xfffff000)) / bytesperpixel;
+
+		*cmds++ = addr & 0xfffff000;   // RB_COPY_DEST_BASE
+		*cmds++ = shadow->pitch >> 5;  // RB_COPY_DEST_PITCH
+		*cmds++ = 0x0003c008 | (shadow->format << RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT); // Endian=none, Linear, Format=RGBA8888,Swap=0,!Dither,MaskWrite:R=G=B=A=1
+
+        KOS_ASSERT( (offset & 0xfffff000) == 0 ); // Make sure we stay in offsetx field.
+		*cmds++ = offset;
+    }
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_MODECONTROL);
+    *cmds++ = 0x6;                          // EDRAM copy
+
+    // queue the draw packet
+    *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2);
+    *cmds++ = 0;                            // viz query info.
+    *cmds++ = 0x00030088;                   // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, shadow->gmem_save, start, cmds);
+
+    return cmds;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// context restore
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// copy colour, depth, & stencil buffers from system memory to graphics memory
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned int*
+build_sys2gmem_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow)
+{
+    unsigned int *cmds = shadow->gmem_restore_commands;
+    unsigned int *start = cmds;
+
+    // Store TP0_CHICKEN register
+    *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmds++ = mmTP0_CHICKEN;
+    if( ctx )
+        *cmds++ = ctx->chicken_restore;
+    else
+        cmds++;
+
+    *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmds++ = 0;
+
+    // Set TP0_CHICKEN to zero
+    *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    *cmds++ = 0x00000000;
+
+    // ----------------
+    // shader constants
+    // ----------------
+
+    // vertex buffer constants
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 7);
+
+    *cmds++ = (0x1 << 16) | (9 * 6);
+    *cmds++ = shadow->quad_vertices.gpuaddr | 0x3;          // valid(?) vtx constant flag & addr
+    *cmds++ = 0x00000030;                       // limit = 12 dwords
+    *cmds++ = shadow->quad_texcoords.gpuaddr | 0x3;         // valid(?) vtx constant flag & addr
+    *cmds++ = 0x00000020;                       // limit = 8 dwords
+    *cmds++ = 0;
+    *cmds++ = 0;
+
+    // Invalidate L2 cache to make sure vertices and texture coordinates are updated
+    *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1);
+    *cmds++ = 0x1;
+
+    // load the patched vertex shader stream
+    cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN);
+
+    // Load the patched fragment shader stream
+    cmds = program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN);
+
+    // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL);
+    *cmds++ = 0x10030002;
+    *cmds++ = 0x00000008;
+
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_AA_MASK);
+    *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_VIZ_QUERY);
+    *cmds++ = 0x0;        //mmPA_SC_VIZ_QUERY
+
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_COLORCONTROL);
+    *cmds++ = 0x00000c20; // RB_COLORCONTROL
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
+    *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX);
+    *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX
+    *cmds++ = 0x0;        //mmVGT_MIN_VTX_INDX
+    *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmVGT_VERTEX_REUSE_BLOCK_CNTL);
+    *cmds++ = 0x00000002; //mmVGT_VERTEX_REUSE_BLOCK_CNTL
+    *cmds++ = 0x00000002; //mmVGT_OUT_DEALLOC_CNTL
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmSQ_INTERPOLATOR_CNTL);
+    *cmds++ = 0xffffffff; //mmSQ_INTERPOLATOR_CNTL
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SC_AA_CONFIG);
+    *cmds++ = 0x00000000; //mmPA_SC_AA_CONFIG
+
+
+    // set mmPA_SU_SC_MODE_CNTL
+    //      Front_ptype = draw triangles
+    //      Back_ptype = draw triangles
+    //      Provoking vertex = last
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL);
+    *cmds++ = 0x00080240;
+
+    // texture constants
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1));
+    *cmds++ = (0x1 << 16) | (0 * 6);
+    kos_memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN<<2);
+    cmds[0] |= (shadow->pitch >> 5) << 22;
+    cmds[1] |= shadow->gmemshadow.gpuaddr | surface_format_table[shadow->format];
+    cmds[2] |= (shadow->width+shadow->offset_x-1) | (shadow->height+shadow->offset_y-1) << 13;
+    cmds += SYS2GMEM_TEX_CONST_LEN;
+
+    // change colour buffer to RGBA8888, MSAA = 1, and matching pitch
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmRB_SURFACE_INFO);
+    *cmds++ = shadow->gmem_pitch; // GMEM pitch is equal to context GMEM shadow pitch
+
+    // RB_COLOR_INFO        Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base
+    if( ctx )
+	{
+        *cmds++ = (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base;
+	}
+    else
+	{
+		unsigned int temp = *cmds;
+		*cmds++ = (temp & ~RB_COLOR_INFO__COLOR_FORMAT_MASK) | (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT);
+	}
+
+    // RB_DEPTHCONTROL
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_DEPTHCONTROL);
+    *cmds++ = 0;                            // disable Z
+
+    // set the scissor to the extents of the draw surface
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL);
+    *cmds++ = (0 << 16) | 0;
+    *cmds++ = (shadow->height << 16) | shadow->width;
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL);
+    *cmds++ = (1U << 31) | (shadow->gmem_offset_y << 16) | shadow->gmem_offset_x;
+    *cmds++ = (shadow->gmem_height << 16) | shadow->gmem_width;
+
+    // PA_CL_VTE_CNTL
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL);
+    *cmds++ = 0x00000b00;                   // disable X/Y/Z transforms, X/Y/Z are premultiplied by W
+
+    // load the viewport so that z scale = clear depth and z offset = 0.0f
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE);
+    *cmds++ = 0xbf800000;
+    *cmds++ = 0x0;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_COLOR_MASK);
+    *cmds++ = 0x0000000f;                   // R = G = B = 1:enabled
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_COLOR_DEST_MASK);
+    *cmds++ = 0xffffffff;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
+    *cmds++ = PM4_REG(mmSQ_WRAPPING_0);
+    *cmds++ = 0x00000000;
+    *cmds++ = 0x00000000;
+
+    *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+    *cmds++ = PM4_REG(mmRB_MODECONTROL);
+    *cmds++ = 0x4;                          // draw pixels with color and depth/stencil component
+
+    // queue the draw packet
+    *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2);
+    *cmds++ = 0;                            // viz query info.
+    *cmds++ = 0x00030088;                   // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, shadow->gmem_restore, start, cmds);
+
+    return cmds;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// restore h/w regs, alu constants, texture constants, etc. ...
+//////////////////////////////////////////////////////////////////////////////
+
+static unsigned *
+reg_range(unsigned int *cmd, unsigned int start, unsigned int end)
+{
+    *cmd++ = PM4_REG(start);                // h/w regs, start addr
+    *cmd++ = end - start + 1;               // count
+    return cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+build_regrestore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *start = ctx->cmd;
+    unsigned int *cmd = start;
+
+    // H/W Registers
+    cmd++; // deferred pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, ???);
+#ifdef DISABLE_SHADOW_WRITES
+    *cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1; // Force mismatch
+#else
+    *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000;
+#endif
+
+    cmd = reg_range(cmd, mmRB_SURFACE_INFO,                 mmPA_SC_SCREEN_SCISSOR_BR);
+    cmd = reg_range(cmd, mmPA_SC_WINDOW_OFFSET,             mmPA_SC_WINDOW_SCISSOR_BR);
+    cmd = reg_range(cmd, mmVGT_MAX_VTX_INDX,                mmPA_CL_VPORT_ZOFFSET);
+    cmd = reg_range(cmd, mmSQ_PROGRAM_CNTL,                 mmSQ_WRAPPING_1);
+    cmd = reg_range(cmd, mmRB_DEPTHCONTROL,                 mmRB_MODECONTROL);
+    cmd = reg_range(cmd, mmPA_SU_POINT_SIZE,                mmPA_SC_VIZ_QUERY);
+    cmd = reg_range(cmd, mmPA_SC_LINE_CNTL,                 mmRB_COLOR_DEST_MASK);
+    cmd = reg_range(cmd, mmPA_SU_POLY_OFFSET_FRONT_SCALE,   mmPA_SU_POLY_OFFSET_BACK_OFFSET);
+
+    // Now we know how many register blocks we have, we can compute command length
+    start[0] = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, (cmd-start)-1);
+#ifdef DISABLE_SHADOW_WRITES
+    start[2] |= (0<<24) | (4 << 16);    // Disable shadowing.
+#else
+    start[2] |= (1<<24) | (4 << 16);    // Enable shadowing for the entire register block.
+#endif
+
+    // Need to handle some of the registers separately
+    *cmd++ = pm4_type0_packet(mmSQ_GPR_MANAGEMENT, 1);
+    ctx->reg_values[0] = gpuaddr(cmd, &drawctxt->gpustate);
+    *cmd++ = 0x00040400;
+
+    *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmd++ = 0;
+    *cmd++ = pm4_type0_packet(mmTP0_CHICKEN, 1);
+    ctx->reg_values[1] = gpuaddr(cmd, &drawctxt->gpustate);
+    *cmd++ = 0x00000000;
+
+    // ALU Constants
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000;
+#ifdef DISABLE_SHADOW_WRITES
+    *cmd++ = (0<<24) | (0<<16) | 0; // Disable shadowing
+#else
+    *cmd++ = (1<<24) | (0<<16) | 0;
+#endif
+    *cmd++ = ALU_CONSTANTS;
+
+
+    // Texture Constants
+    *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3);
+    *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000;
+#ifdef DISABLE_SHADOW_WRITES
+    *cmd++ = (0<<24) | (1<<16) | 0; // Disable shadowing
+#else
+    *cmd++ = (1<<24) | (1<<16) | 0;
+#endif
+    *cmd++ = TEX_CONSTANTS;
+
+
+    // Boolean Constants
+    *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + BOOL_CONSTANTS);
+    *cmd++ = (2<<16) | 0;
+
+    // the next BOOL_CONSTANT dwords is the shadow area for boolean constants.
+    ctx->bool_shadow = gpuaddr(cmd, &drawctxt->gpustate);
+    cmd += BOOL_CONSTANTS;
+
+
+    // Loop Constants
+    *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + LOOP_CONSTANTS);
+    *cmd++ = (3<<16) | 0;
+
+    // the next LOOP_CONSTANTS dwords is the shadow area for loop constants.
+    ctx->loop_shadow = gpuaddr(cmd, &drawctxt->gpustate);
+    cmd += LOOP_CONSTANTS;
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->reg_restore, start, cmd);
+
+    ctx->cmd = cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// quad for saving/restoring gmem
+//////////////////////////////////////////////////////////////////////////////
+
+static void set_gmem_copy_quad( gmem_shadow_t* shadow )
+{
+    unsigned int tex_offset[2];
+
+    // set vertex buffer values
+
+    gmem_copy_quad[1] = uint2float( shadow->gmem_height + shadow->gmem_offset_y );
+    gmem_copy_quad[3] = uint2float( shadow->gmem_width + shadow->gmem_offset_x );
+    gmem_copy_quad[4] = uint2float( shadow->gmem_height + shadow->gmem_offset_y );
+    gmem_copy_quad[9] = uint2float( shadow->gmem_width + shadow->gmem_offset_x );
+
+    gmem_copy_quad[0] = uint2float( shadow->gmem_offset_x );
+    gmem_copy_quad[6] = uint2float( shadow->gmem_offset_x );
+    gmem_copy_quad[7] = uint2float( shadow->gmem_offset_y );
+    gmem_copy_quad[10] = uint2float( shadow->gmem_offset_y );
+
+    tex_offset[0] = uintdivide( shadow->offset_x, (shadow->offset_x+shadow->width) );
+    tex_offset[1] = uintdivide( shadow->offset_y, (shadow->offset_y+shadow->height) );
+
+    gmem_copy_texcoord[0] = gmem_copy_texcoord[4] = tex_offset[0];
+    gmem_copy_texcoord[5] = gmem_copy_texcoord[7] = tex_offset[1];
+
+    // copy quad data to vertex buffer
+    kos_memcpy(shadow->quad_vertices.hostptr, gmem_copy_quad, QUAD_LEN << 2);
+
+    // copy tex coord data to tex coord buffer
+    kos_memcpy(shadow->quad_texcoords.hostptr, gmem_copy_texcoord, TEXCOORD_LEN << 2);
+}
+
+
+static void
+build_quad_vtxbuff(gsl_drawctxt_t *drawctxt, ctx_t *ctx, gmem_shadow_t* shadow)
+{
+    unsigned int *cmd = ctx->cmd;
+
+    // quad vertex buffer location
+    shadow->quad_vertices.hostptr = cmd;
+    shadow->quad_vertices.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate);
+    cmd += QUAD_LEN;
+
+    // tex coord buffer location (in GPU space)
+    shadow->quad_texcoords.hostptr = cmd;
+    shadow->quad_texcoords.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate);
+
+
+    cmd += TEXCOORD_LEN;
+
+    set_gmem_copy_quad(shadow);
+
+
+    ctx->cmd = cmd;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+
+static void
+build_shader_save_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int *cmd = ctx->cmd;
+    unsigned int *save, *restore, *fixup;
+#if defined(PM4_IM_STORE)
+    unsigned int *startSizeVtx, *startSizePix, *startSizeShared;
+#endif
+    unsigned int *partition1;
+    unsigned int *shaderBases, *partition2;
+
+#if defined(PM4_IM_STORE)
+    // compute vertex, pixel and shared instruction shadow GPU addresses
+    ctx->shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET;
+    ctx->shader_pixel  = ctx->shader_vertex + SHADER_SHADOW_SIZE;
+    ctx->shader_shared = ctx->shader_pixel  + SHADER_SHADOW_SIZE;
+#endif
+
+
+    //-------------------------------------------------------------------
+    // restore shader partitioning and instructions
+    //-------------------------------------------------------------------
+
+    restore = cmd;  // start address
+
+    // Invalidate Vertex & Pixel instruction code address and sizes
+    *cmd++ = pm4_type3_packet(PM4_INVALIDATE_STATE, 1);
+    *cmd++ = 0x00000300;                        // 0x100 = Vertex, 0x200 = Pixel
+
+    // Restore previous shader vertex & pixel instruction bases.
+    *cmd++ = pm4_type3_packet(PM4_SET_SHADER_BASES, 1);
+    shaderBases = cmd++;                        // TBD #5: shader bases (from fixup)
+
+    // write the shader partition information to a scratch register
+    *cmd++ = pm4_type0_packet(mmSQ_INST_STORE_MANAGMENT, 1);
+    partition1 = cmd++;                         // TBD #4a: partition info (from save)
+
+#if defined(PM4_IM_STORE)
+    // load vertex shader instructions from the shadow.
+    *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2);
+    *cmd++ = ctx->shader_vertex + 0x0;          // 0x0 = Vertex
+    startSizeVtx = cmd++;                       // TBD #1: start/size (from save)
+
+    // load pixel shader instructions from the shadow.
+    *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2);
+    *cmd++ = ctx->shader_pixel + 0x1;           // 0x1 = Pixel
+    startSizePix = cmd++;                       // TBD #2: start/size (from save)
+
+    // load shared shader instructions from the shadow.
+    *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2);
+    *cmd++ = ctx->shader_shared + 0x2;          // 0x2 = Shared
+    startSizeShared = cmd++;                    // TBD #3: start/size (from save)
+#endif
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd);
+
+
+    //-------------------------------------------------------------------
+    // fixup SET_SHADER_BASES data
+    //
+    // since self-modifying PM4 code is being used here, a seperate
+    // command buffer is used for this fixup operation, to ensure the
+    // commands are not read by the PM4 engine before the data fields
+    // have been written.
+    //-------------------------------------------------------------------
+
+    fixup = cmd;        // start address
+
+    // write the shader partition information to a scratch register
+    *cmd++ = pm4_type0_packet(mmSCRATCH_REG2, 1);
+    partition2 = cmd++;                                 // TBD #4b: partition info (from save)
+
+    // mask off unused bits, then OR with shader instruction memory size
+    *cmd++ = pm4_type3_packet(PM4_REG_RMW, 3);
+    *cmd++ = mmSCRATCH_REG2;
+    *cmd++ = 0x0FFF0FFF;                                // AND off invalid bits.
+    *cmd++ = (unsigned int)((SHADER_INSTRUCT_LOG2-5U) << 29);               // OR in instruction memory size
+
+    // write the computed value to the SET_SHADER_BASES data field
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSCRATCH_REG2;
+    *cmd++ = gpuaddr(shaderBases, &drawctxt->gpustate); // TBD #5: shader bases (to restore)
+
+    // create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd);
+
+
+    //-------------------------------------------------------------------
+    // save shader partitioning and instructions
+    //-------------------------------------------------------------------
+
+    save = cmd;     // start address
+
+    *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmd++ = 0;
+
+    // Fetch the SQ_INST_STORE_MANAGMENT register value,
+    // Store the value in the data fields of the SET_CONSTANT commands above.
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSQ_INST_STORE_MANAGMENT;
+    *cmd++ = gpuaddr(partition1, &drawctxt->gpustate);      // TBD #4a: partition info (to restore)
+    *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2);
+    *cmd++ = mmSQ_INST_STORE_MANAGMENT;
+    *cmd++ = gpuaddr(partition2, &drawctxt->gpustate);      // TBD #4b: partition info (to fixup)
+
+#if defined(PM4_IM_STORE)
+    // Store the vertex shader instructions
+    *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2);
+    *cmd++ = ctx->shader_vertex + 0x0;                      // 0x0 = Vertex
+    *cmd++ = gpuaddr(startSizeVtx, &drawctxt->gpustate);    // TBD #1: start/size (to restore)
+
+    // store the pixel shader instructions
+    *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2);
+    *cmd++ = ctx->shader_pixel + 0x1;                       // 0x1 = Pixel
+    *cmd++ = gpuaddr(startSizePix, &drawctxt->gpustate);    // TBD #2: start/size (to restore)
+
+    // Store the shared shader instructions
+    *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2);
+    *cmd++ = ctx->shader_shared + 0x2;                      // 0x2 = Shared
+    *cmd++ = gpuaddr(startSizeShared, &drawctxt->gpustate); // TBD #3: start/size (to restore)
+#endif
+
+    *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    *cmd++ = 0;
+
+
+
+    // Create indirect buffer command for above command sequence
+    create_ib1(drawctxt, drawctxt->shader_save, save, cmd);
+
+
+    ctx->cmd = cmd;
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// create buffers for saving/restoring registers and constants
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+create_gpustate_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    gsl_flags_t flags;
+
+    flags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K);
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_EMEM | GSL_MEMFLAGS_ALIGN8K));
+
+    // allocate memory to allow HW to save sub-blocks for efficient context save/restore
+    if (kgsl_sharedmem_alloc0(device->id, flags, CONTEXT_SIZE, &drawctxt->gpustate) != GSL_SUCCESS)
+        return GSL_FAILURE;
+
+    drawctxt->flags |= CTXT_FLAGS_STATE_SHADOW;
+
+    // Blank out h/w register, constant, and command buffer shadows.
+    kgsl_sharedmem_set0(&drawctxt->gpustate, 0, 0, CONTEXT_SIZE);
+
+    // set-up command and vertex buffer pointers
+    ctx->cmd = ctx->start = (unsigned int *) ((char *)drawctxt->gpustate.hostptr + CMD_OFFSET);
+
+    // build indirect command buffers to save & restore regs/constants
+    build_regrestore_cmds(drawctxt, ctx);
+    build_regsave_cmds(drawctxt, ctx);
+
+    build_shader_save_restore_cmds(drawctxt, ctx);
+
+    return GSL_SUCCESS;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// Allocate GMEM shadow buffer
+//////////////////////////////////////////////////////////////////////////////
+static int
+allocate_gmem_shadow_buffer(gsl_device_t *device, gsl_drawctxt_t *drawctxt)
+{
+    // allocate memory for GMEM shadow
+    if (kgsl_sharedmem_alloc0(device->id, (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K),
+        drawctxt->context_gmem_shadow.size, &drawctxt->context_gmem_shadow.gmemshadow) != GSL_SUCCESS)
+        return GSL_FAILURE;
+
+    // blank out gmem shadow.
+    kgsl_sharedmem_set0(&drawctxt->context_gmem_shadow.gmemshadow, 0, 0, drawctxt->context_gmem_shadow.size);
+
+    return GSL_SUCCESS;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// create GMEM save/restore specific stuff
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+create_gmem_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx)
+{
+    unsigned int i;
+    config_gmemsize(&drawctxt->context_gmem_shadow, device->gmemspace.sizebytes);
+    ctx->gmem_base = device->gmemspace.gpu_base;
+
+    if( drawctxt->flags & CTXT_FLAGS_GMEM_SHADOW )
+    {
+        if( allocate_gmem_shadow_buffer(device, drawctxt) != GSL_SUCCESS )
+            return GSL_FAILURE;
+    }
+    else
+    {
+        kos_memset( &drawctxt->context_gmem_shadow.gmemshadow, 0, sizeof( gsl_memdesc_t ) );
+    }
+
+    // build quad vertex buffer
+    build_quad_vtxbuff(drawctxt, ctx, &drawctxt->context_gmem_shadow);
+
+    // build TP0_CHICKEN register restore command buffer
+    ctx->cmd = build_chicken_restore_cmds(drawctxt, ctx);
+
+    // build indirect command buffers to save & restore gmem
+    drawctxt->context_gmem_shadow.gmem_save_commands = ctx->cmd;
+    ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow);
+    drawctxt->context_gmem_shadow.gmem_restore_commands = ctx->cmd;
+    ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow);
+
+    for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+    {
+        // build quad vertex buffer
+        build_quad_vtxbuff(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]);
+
+        // build indirect command buffers to save & restore gmem
+        drawctxt->user_gmem_shadow[i].gmem_save_commands = ctx->cmd;
+        ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]);
+
+        drawctxt->user_gmem_shadow[i].gmem_restore_commands = ctx->cmd;
+        ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]);
+    }
+
+    return GSL_SUCCESS;
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// init draw context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_init(gsl_device_t *device)
+{
+    GSL_CONTEXT_MUTEX_CREATE();
+
+    return (GSL_SUCCESS);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// close draw context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_close(gsl_device_t *device)
+{
+    GSL_CONTEXT_MUTEX_FREE();
+
+    return (GSL_SUCCESS);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// create a new drawing context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags)
+{
+    gsl_drawctxt_t  *drawctxt;
+    int             index;
+    ctx_t           ctx;
+
+    kgsl_device_active(device);
+    
+    GSL_CONTEXT_MUTEX_LOCK();
+    if (device->drawctxt_count >= GSL_CONTEXT_MAX)
+    {
+        GSL_CONTEXT_MUTEX_UNLOCK();
+        return (GSL_FAILURE);
+    }
+
+    // find a free context slot
+    index = 0;
+    while (index < GSL_CONTEXT_MAX)
+    {
+        if (device->drawctxt[index].flags == CTXT_FLAGS_NOT_IN_USE)
+            break;
+
+        index++;
+    }
+
+    if (index >= GSL_CONTEXT_MAX)
+    {
+        GSL_CONTEXT_MUTEX_UNLOCK();
+        return (GSL_FAILURE);
+    }
+
+    drawctxt = &device->drawctxt[index];
+
+    kos_memset( &drawctxt->context_gmem_shadow, 0, sizeof( gmem_shadow_t ) );
+
+	drawctxt->pid   = GSL_CALLER_PROCESSID_GET();
+    drawctxt->flags = CTXT_FLAGS_IN_USE;
+    drawctxt->type  = type;
+
+    device->drawctxt_count++;
+
+    // create context shadows, when not running in safe mode
+    if (!(device->flags & GSL_FLAGS_SAFEMODE))
+    {
+        if (create_gpustate_shadow(device, drawctxt, &ctx) != GSL_SUCCESS)
+        {
+            kgsl_drawctxt_destroy(device, index);
+            GSL_CONTEXT_MUTEX_UNLOCK();
+            return (GSL_FAILURE);
+        }
+
+        // Save the shader instruction memory & GMEM on context switching
+        drawctxt->flags |= ( CTXT_FLAGS_SHADER_SAVE | CTXT_FLAGS_GMEM_SHADOW );
+
+        // Clear out user defined GMEM shadow buffer structs
+        kos_memset( drawctxt->user_gmem_shadow, 0, sizeof(gmem_shadow_t)*GSL_MAX_GMEM_SHADOW_BUFFERS );
+
+        // create gmem shadow
+        if (create_gmem_shadow(device, drawctxt, &ctx) != GSL_SUCCESS)
+        {
+            kgsl_drawctxt_destroy(device, index);
+            GSL_CONTEXT_MUTEX_UNLOCK();
+            return (GSL_FAILURE);
+        }
+
+        KOS_ASSERT(ctx.cmd - ctx.start <= CMD_BUFFER_LEN);
+    }
+
+    *drawctxt_id = index;
+
+    GSL_CONTEXT_MUTEX_UNLOCK();
+    return (GSL_SUCCESS);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// destroy a drawing context
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id)
+{
+    gsl_drawctxt_t *drawctxt;
+
+    GSL_CONTEXT_MUTEX_LOCK();
+
+    drawctxt = &device->drawctxt[drawctxt_id];
+
+    if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE)
+    {
+        // deactivate context
+        if (device->drawctxt_active == drawctxt)
+        {
+            // no need to save GMEM or shader, the context is being destroyed.
+            drawctxt->flags &= ~(CTXT_FLAGS_GMEM_SAVE | CTXT_FLAGS_SHADER_SAVE);
+
+            kgsl_drawctxt_switch(device, GSL_CONTEXT_NONE, 0);
+        }
+
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+
+        // destroy state shadow, if allocated
+        if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW)
+            kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET());
+
+
+        // destroy gmem shadow, if allocated
+        if (drawctxt->context_gmem_shadow.gmemshadow.size > 0)
+        {
+            kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET());
+            drawctxt->context_gmem_shadow.gmemshadow.size = 0;
+        }
+
+        drawctxt->flags = CTXT_FLAGS_NOT_IN_USE;
+		drawctxt->pid   = 0;
+
+        device->drawctxt_count--;
+        KOS_ASSERT(device->drawctxt_count >= 0);
+    }
+
+    GSL_CONTEXT_MUTEX_UNLOCK();
+
+    return (GSL_SUCCESS);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// Binds a user specified buffer as GMEM shadow area
+//
+// gmem_rect:   defines the rectangle that is copied from GMEM. X and Y
+//              coordinates need to be multiples of 8 after conversion to 32bpp.
+//              X, Y, width, and height need to be at 32-bit boundary to avoid
+//              rounding.
+//
+// shadow_x & shadow_y: Position in GMEM shadow buffer where the contents of
+//                      gmem_rect is copied. Both must be multiples of 8 after
+//                      conversion to 32bpp. They also need to be at 32-bit
+//                      boundary to avoid rounding.
+//
+// shadow_buffer:   Description of the GMEM shadow buffer. BPP needs to be
+//                  8, 16, 32, 64, or 128. Enabled tells if the buffer is
+//                  used or not (values 0 and 1). All the other buffer
+//                  parameters are ignored when enabled=0.
+//
+// buffer_id: Two different buffers can be defined. Use buffer IDs 0 and 1.
+//
+//
+//////////////////////////////////////////////////////////////////////////////
+KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id)
+{
+    gsl_device_t   *device = &gsl_driver.device[device_id-1];
+    gsl_drawctxt_t *drawctxt = &device->drawctxt[drawctxt_id];
+    gmem_shadow_t  *shadow = &drawctxt->user_gmem_shadow[buffer_id];
+    unsigned int    i;
+
+    GSL_API_MUTEX_LOCK();
+    GSL_CONTEXT_MUTEX_LOCK();
+
+	if( !shadow_buffer->enabled )
+    {
+        // Disable shadow
+        shadow->gmemshadow.size = 0;
+    }
+    else
+    {
+		// Sanity checks
+		KOS_ASSERT((gmem_rect->x % 2) == 0);      // Needs to be a multiple of 2
+		KOS_ASSERT((gmem_rect->y % 2) == 0);      // Needs to be a multiple of 2
+		KOS_ASSERT((gmem_rect->width % 2) == 0);  // Needs to be a multiple of 2
+		KOS_ASSERT((gmem_rect->height % 2) == 0); // Needs to be a multiple of 2
+		KOS_ASSERT((gmem_rect->pitch % 32) == 0); // Needs to be a multiple of 32
+
+		KOS_ASSERT((shadow_x % 2) == 0);  // Needs to be a multiple of 2
+		KOS_ASSERT((shadow_y % 2) == 0);  // Needs to be a multiple of 2
+
+		KOS_ASSERT(shadow_buffer->format >= COLORX_4_4_4_4);
+		KOS_ASSERT(shadow_buffer->format <= COLORX_32_32_32_32_FLOAT);
+		KOS_ASSERT((shadow_buffer->pitch % 32) == 0); // Needs to be a multiple of 32
+		KOS_ASSERT(buffer_id >= 0);
+		KOS_ASSERT(buffer_id < GSL_MAX_GMEM_SHADOW_BUFFERS);
+
+		// Set up GMEM shadow regions
+        kos_memcpy( &shadow->gmemshadow, &shadow_buffer->data, sizeof( gsl_memdesc_t ) );
+        shadow->size = shadow->gmemshadow.size;
+
+		shadow->width = shadow_buffer->width;
+		shadow->height = shadow_buffer->height;
+		shadow->pitch = shadow_buffer->pitch;
+		shadow->format = shadow_buffer->format;
+
+        shadow->offset = shadow->pitch * (shadow_y - gmem_rect->y) + shadow_x - gmem_rect->x;
+
+        shadow->offset_x = shadow_x;
+        shadow->offset_y = shadow_y;
+
+		shadow->gmem_width = gmem_rect->width;
+		shadow->gmem_height = gmem_rect->height;
+		shadow->gmem_pitch = gmem_rect->pitch;
+
+        shadow->gmem_offset_x = gmem_rect->x;
+        shadow->gmem_offset_y = gmem_rect->y;
+
+        // Modify quad vertices
+        set_gmem_copy_quad(shadow);
+
+        // Modify commands
+        build_gmem2sys_cmds(drawctxt, NULL, shadow);
+        build_sys2gmem_cmds(drawctxt, NULL, shadow);
+
+        // Release context GMEM shadow if found
+        if (drawctxt->context_gmem_shadow.gmemshadow.size > 0)
+        {
+            kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET());
+            drawctxt->context_gmem_shadow.gmemshadow.size = 0;
+        }
+    }
+
+    // Enable GMEM shadowing if we have any of the user buffers enabled
+    drawctxt->flags &= ~CTXT_FLAGS_GMEM_SHADOW;
+    for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+    {
+        if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 )
+        {
+            drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW;
+        }
+    }
+
+    GSL_CONTEXT_MUTEX_UNLOCK();
+    GSL_API_MUTEX_UNLOCK();
+
+    return (GSL_SUCCESS);
+}
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// switch drawing contexts
+//////////////////////////////////////////////////////////////////////////////
+
+void
+kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags)
+{
+    gsl_drawctxt_t *active_ctxt = device->drawctxt_active;
+
+	if (drawctxt != GSL_CONTEXT_NONE)
+	{
+		if( flags & GSL_CONTEXT_SAVE_GMEM )
+		{
+			// Set the flag in context so that the save is done when this context is switched out.
+			drawctxt->flags |= CTXT_FLAGS_GMEM_SAVE;
+		}
+		else
+		{
+			// Remove GMEM saving flag from the context
+			drawctxt->flags &= ~CTXT_FLAGS_GMEM_SAVE;
+		}
+	}
+
+    // already current?
+    if (active_ctxt == drawctxt)
+    {
+        return;
+    }
+
+    // save old context, when not running in safe mode
+    if (active_ctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE))
+    {
+        // save registers and constants.
+        kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->reg_save, 3, active_ctxt->pid);
+
+        if (active_ctxt->flags & CTXT_FLAGS_SHADER_SAVE)
+        {
+            // save shader partitioning and instructions.
+			kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->shader_save, 3, active_ctxt->pid);
+
+            // fixup shader partitioning parameter for SET_SHADER_BASES.
+			kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->shader_fixup, 3, active_ctxt->pid);
+
+            active_ctxt->flags |= CTXT_FLAGS_SHADER_RESTORE;
+        }
+
+        if (active_ctxt->flags & CTXT_FLAGS_GMEM_SHADOW && active_ctxt->flags & CTXT_FLAGS_GMEM_SAVE )
+        {
+            // save gmem.  (note: changes shader.  shader must already be saved.)
+
+            unsigned int i, numbuffers = 0;
+
+            for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+            {
+                if( active_ctxt->user_gmem_shadow[i].gmemshadow.size > 0 )
+                {
+					kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->user_gmem_shadow[i].gmem_save, 3, active_ctxt->pid);
+
+                    // Restore TP0_CHICKEN
+					kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid);
+                    numbuffers++;
+                }
+            }
+            if( numbuffers == 0 )
+            {
+                // No user defined buffers -> use context default
+				kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->context_gmem_shadow.gmem_save, 3, active_ctxt->pid);
+                // Restore TP0_CHICKEN
+				kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid);
+            }
+
+            active_ctxt->flags |= CTXT_FLAGS_GMEM_RESTORE;
+        }
+    }
+
+    device->drawctxt_active = drawctxt;
+
+    // restore new context, when not running in safe mode
+    if (drawctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE))
+    {
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, drawctxt->gpustate.gpuaddr, (unsigned int)drawctxt->gpustate.hostptr, LCC_SHADOW_SIZE + REG_SHADOW_SIZE + CMD_BUFFER_SIZE + TEX_SHADOW_SIZE , "kgsl_drawctxt_switch"));
+
+        // restore gmem.  (note: changes shader.  shader must not already be restored.)
+        if (drawctxt->flags & CTXT_FLAGS_GMEM_RESTORE)
+        {
+            unsigned int i, numbuffers = 0;
+
+            for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ )
+            {
+                if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 )
+                {
+					kgsl_ringbuffer_issuecmds(device, 1, drawctxt->user_gmem_shadow[i].gmem_restore, 3, drawctxt->pid);
+
+                    // Restore TP0_CHICKEN
+					kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid);
+                    numbuffers++;
+                }
+            }
+            if( numbuffers == 0 )
+            {
+                // No user defined buffers -> use context default
+				kgsl_ringbuffer_issuecmds(device, 1, drawctxt->context_gmem_shadow.gmem_restore, 3, drawctxt->pid);
+                // Restore TP0_CHICKEN
+				kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid);
+            }
+
+            drawctxt->flags &= ~CTXT_FLAGS_GMEM_RESTORE;
+        }
+
+        // restore registers and constants.
+		kgsl_ringbuffer_issuecmds(device, 0, drawctxt->reg_restore, 3, drawctxt->pid);
+
+        // restore shader instructions & partitioning.
+        if (drawctxt->flags & CTXT_FLAGS_SHADER_RESTORE)
+        {
+			kgsl_ringbuffer_issuecmds(device, 0, drawctxt->shader_restore, 3, drawctxt->pid);
+        }
+    }
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// destroy all drawing contexts
+//////////////////////////////////////////////////////////////////////////////
+int
+kgsl_drawctxt_destroyall(gsl_device_t *device)
+{
+    int             i;
+    gsl_drawctxt_t  *drawctxt;
+
+    GSL_CONTEXT_MUTEX_LOCK();
+
+    for (i = 0; i < GSL_CONTEXT_MAX; i++)
+    {
+        drawctxt = &device->drawctxt[i];
+
+        if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE)
+        {
+            // destroy state shadow, if allocated
+            if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW)
+                kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET());
+
+            // destroy gmem shadow, if allocated
+            if (drawctxt->context_gmem_shadow.gmemshadow.size > 0)
+            {
+                kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET());
+                drawctxt->context_gmem_shadow.gmemshadow.size = 0;
+            }
+
+            drawctxt->flags = CTXT_FLAGS_NOT_IN_USE;
+
+            device->drawctxt_count--;
+            KOS_ASSERT(device->drawctxt_count >= 0);
+        }
+    }
+
+    GSL_CONTEXT_MUTEX_UNLOCK();
+
+    return (GSL_SUCCESS);
+}
+
+#endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_driver.c b/drivers/mxc/amd-gpu/common/gsl_driver.c
new file mode 100644
index 00000000000..b8c5170a142
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_driver.c
@@ -0,0 +1,329 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_PROCESSID_NONE          0x00000000
+
+#define GSL_DRVFLAGS_EXTERNAL       0x10000000
+#define GSL_DRVFLAGS_INTERNAL       0x20000000
+
+
+//////////////////////////////////////////////////////////////////////////////
+// globals
+//////////////////////////////////////////////////////////////////////////////
+#ifndef KGSL_USER_MODE
+static gsl_flags_t  gsl_driver_initialized = 0;
+gsl_driver_t        gsl_driver;
+#else
+extern gsl_flags_t  gsl_driver_initialized;
+extern gsl_driver_t gsl_driver;
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_driver_init0(gsl_flags_t flags, gsl_flags_t flags_debug)
+{
+    int  status = GSL_SUCCESS;
+
+    if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0))
+    {
+#ifdef GSL_LOG
+        // Uncomment these to enable logging.
+        //kgsl_log_init();
+        //kgsl_log_open_stdout( KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP
+        //                      | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID );
+        //kgsl_log_open_file( "c:\\kgsl_log.txt", KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP
+        //                      | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID );
+#endif
+        kos_memset(&gsl_driver, 0, sizeof(gsl_driver_t));
+
+        GSL_API_MUTEX_CREATE();
+    }
+
+#ifdef _DEBUG
+    // set debug flags on every entry, and prior to hal initialization
+    gsl_driver.flags_debug |= flags_debug;
+#else
+    (void) flags_debug;     // unref formal parameter
+#endif // _DEBUG
+
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+    {
+        KGSL_DEBUG_DUMPX_OPEN("dumpx.tb", 0);
+        KGSL_DEBUG_DUMPX( BB_DUMP_ENABLE, 0, 0, 0, " ");
+    });
+
+    KGSL_DEBUG_TBDUMP_OPEN("tbdump.txt");
+
+    if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0))
+    {
+        GSL_API_MUTEX_LOCK();
+
+        // init hal
+        status = kgsl_hal_init();
+
+        if (status == GSL_SUCCESS)
+        {
+            gsl_driver_initialized |= flags;
+            gsl_driver_initialized |= GSL_FLAGS_INITIALIZED0;
+        }
+
+        GSL_API_MUTEX_UNLOCK();
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_driver_close0(gsl_flags_t flags)
+{
+    int  status = GSL_SUCCESS;
+
+    if ((gsl_driver_initialized & GSL_FLAGS_INITIALIZED0) && (gsl_driver_initialized & flags))
+    {
+        GSL_API_MUTEX_LOCK();
+
+        // close hall
+        status = kgsl_hal_close();
+
+        GSL_API_MUTEX_UNLOCK();
+
+        GSL_API_MUTEX_FREE();
+
+#ifdef GSL_LOG
+        kgsl_log_close();
+#endif
+
+        gsl_driver_initialized &= ~flags;
+        gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED0;
+
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+        {
+            KGSL_DEBUG_DUMPX_CLOSE();
+        });
+
+        KGSL_DEBUG_TBDUMP_CLOSE();
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_init()
+{
+    // only an external (platform specific device driver) component should call this
+
+    return(kgsl_driver_init0(GSL_DRVFLAGS_EXTERNAL, 0));
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_close()
+{
+    // only an external (platform specific device driver) component should call this
+
+    return(kgsl_driver_close0(GSL_DRVFLAGS_EXTERNAL));
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_entry(gsl_flags_t flags)
+{
+    int           status = GSL_FAILURE;
+    int           index, i;
+    unsigned int  pid;
+
+    if (kgsl_driver_init0(GSL_DRVFLAGS_INTERNAL, flags) != GSL_SUCCESS)
+    {
+        return (GSL_FAILURE);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_entry( gsl_flags_t flags=%d )\n", flags );
+
+    GSL_API_MUTEX_LOCK();
+
+    pid = GSL_CALLER_PROCESSID_GET();
+
+    // if caller process has not already opened access
+    status = kgsl_driver_getcallerprocessindex(pid, &index);
+    if (status != GSL_SUCCESS)
+    {
+        // then, add caller pid to process table
+        status = kgsl_driver_getcallerprocessindex(GSL_PROCESSID_NONE, &index);
+        if (status == GSL_SUCCESS)
+        {
+            gsl_driver.callerprocess[index] = pid;
+            gsl_driver.refcnt++;
+        }
+    }
+
+    if (status == GSL_SUCCESS)
+    {
+        if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED))
+        {
+            // init memory apertures
+            status = kgsl_sharedmem_init(&gsl_driver.shmem);
+            if (status == GSL_SUCCESS)
+            {
+                // init devices
+		status = GSL_FAILURE;
+                for (i = 0; i < GSL_DEVICE_MAX; i++)
+                {
+		    if (kgsl_device_init(&gsl_driver.device[i], (gsl_deviceid_t)(i + 1)) == GSL_SUCCESS) {
+			status = GSL_SUCCESS;
+		    }
+                }
+            }
+
+            if (status == GSL_SUCCESS)
+            {
+                gsl_driver_initialized |= GSL_FLAGS_INITIALIZED;
+            }
+        }
+
+        // walk through process attach callbacks
+        if (status == GSL_SUCCESS)
+        {
+            for (i = 0; i < GSL_DEVICE_MAX; i++)
+            {
+                status = kgsl_device_attachcallback(&gsl_driver.device[i], pid);
+                if (status != GSL_SUCCESS)
+                {
+                    break;
+                }
+            }
+        }
+
+        // if something went wrong
+        if (status != GSL_SUCCESS)
+        {
+            // then, remove caller pid from process table
+            if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS)
+            {
+                gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE;
+                gsl_driver.refcnt--;
+            }
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_entry. Return value: %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_driver_exit0(unsigned int pid)
+{
+    int  status = GSL_SUCCESS;
+    int  index, i;
+
+    GSL_API_MUTEX_LOCK();
+
+    if (gsl_driver_initialized & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS)
+        {
+            // walk through process detach callbacks
+            for (i = 0; i < GSL_DEVICE_MAX; i++)
+            {
+                // Empty the freememqueue of this device
+                kgsl_cmdstream_memqueue_drain(&gsl_driver.device[i]);
+
+                // Detach callback
+                status = kgsl_device_detachcallback(&gsl_driver.device[i], pid);
+                if (status != GSL_SUCCESS)
+                {
+                    break;
+                }
+            }
+
+            // last running caller process
+            if (gsl_driver.refcnt - 1 == 0)
+            {
+                // close devices
+                for (i = 0; i < GSL_DEVICE_MAX; i++)
+                {
+                    kgsl_device_close(&gsl_driver.device[i]);
+                }
+
+                // shutdown memory apertures
+                kgsl_sharedmem_close(&gsl_driver.shmem);
+
+                gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED;
+            }
+
+            // remove caller pid from process table
+            gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE;
+            gsl_driver.refcnt--;
+        }
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_driver_close0(GSL_DRVFLAGS_INTERNAL);
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_exit(void)
+{
+    int status;
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_exit()\n" );
+
+    status = kgsl_driver_exit0(GSL_CALLER_PROCESSID_GET());
+
+    kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_exit(). Return value: %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_driver_destroy(unsigned int pid)
+{
+    return (kgsl_driver_exit0(pid));
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_g12.c b/drivers/mxc/amd-gpu/common/gsl_g12.c
new file mode 100644
index 00000000000..8286e8e6a6a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_g12.c
@@ -0,0 +1,1025 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "kos_libapi.h"
+#include "gsl_cmdstream.h"
+#ifdef _LINUX
+#include <linux/sched.h>
+#endif
+
+#ifdef CONFIG_ARCH_MX35
+#define V3_SYNC
+#endif
+
+#ifdef GSL_BLD_G12
+#define GSL_IRQ_TIMEOUT         200
+
+
+//----------------------------------------------------------------------------
+
+#define GSL_HAL_NUMCMDBUFFERS           5
+#define GSL_HAL_CMDBUFFERSIZE           (1024 + 13) * sizeof(unsigned int)
+
+#define     ALIGN_IN_BYTES( dim, alignment ) ( ( (dim) + (alignment-1) ) & ~(alignment-1) )
+
+
+#ifdef _Z180
+#define     NUMTEXUNITS                         4
+#define     TEXUNITREGCOUNT                     25
+#define     VG_REGCOUNT                         0x39
+#define     GSL_HAL_EDGE0BUFSIZE                0x3E8+64
+#define     GSL_HAL_EDGE1BUFSIZE                0x8000+64
+#define     GSL_HAL_EDGE2BUFSIZE                0x80020+64
+#define     GSL_HAL_EDGE0REG                    ADDR_VGV1_CBUF
+#define     GSL_HAL_EDGE1REG                    ADDR_VGV1_BBUF
+#define     GSL_HAL_EDGE2REG                    ADDR_VGV1_EBUF
+#else
+#define     NUMTEXUNITS                          2
+#define     TEXUNITREGCOUNT                      24
+#define     VG_REGCOUNT                          0x3A
+#define     L1TILESIZE                           64
+#define     GSL_HAL_EDGE0BUFSIZE                 L1TILESIZE*L1TILESIZE*4+64
+#define     GSL_HAL_EDGE1BUFSIZE                 L1TILESIZE*L1TILESIZE*16+64
+#define     GSL_HAL_EDGE0REG                     ADDR_VGV1_CBASE1
+#define     GSL_HAL_EDGE1REG                     ADDR_VGV1_UBASE2
+#endif
+
+#define     PACKETSIZE_BEGIN        3
+#define     PACKETSIZE_G2DCOLOR     2
+#define     PACKETSIZE_TEXUNIT      (TEXUNITREGCOUNT*2)
+#define     PACKETSIZE_REG          (VG_REGCOUNT*2)
+#define     PACKETSIZE_STATE        (PACKETSIZE_TEXUNIT*NUMTEXUNITS + PACKETSIZE_REG + PACKETSIZE_BEGIN + PACKETSIZE_G2DCOLOR)
+#define     PACKETSIZE_STATESTREAM   ALIGN_IN_BYTES((PACKETSIZE_STATE*sizeof(unsigned int)), 32) / sizeof(unsigned int) 
+
+//----------------------------------------------------------------------------
+
+typedef struct
+{
+    unsigned int id;
+   // unsigned int regs[];
+}gsl_hal_z1xxdrawctx_t;
+
+typedef struct
+{
+  unsigned int      offs;
+  unsigned int      curr;
+  unsigned int      prevctx;
+
+  gsl_memdesc_t     e0;
+  gsl_memdesc_t     e1;
+  gsl_memdesc_t     e2;
+  unsigned int*     cmdbuf[GSL_HAL_NUMCMDBUFFERS];
+  gsl_memdesc_t     cmdbufdesc[GSL_HAL_NUMCMDBUFFERS];
+  gsl_timestamp_t   timestamp[GSL_HAL_NUMCMDBUFFERS];
+
+  unsigned int      numcontext;
+  unsigned int      nextUniqueContextID;
+}gsl_z1xx_t;
+
+static gsl_z1xx_t   g_z1xx      = {0}; 
+
+extern int z160_version;
+
+//----------------------------------------------------------------------------
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static int kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp);
+static int kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags);
+static int kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+static int kgsl_g12_context_destroy(gsl_device_t* device, unsigned int drawctxt_id);
+static unsigned int drawctx_id  = 0;
+static int kgsl_g12_idle(gsl_device_t *device, unsigned int timeout);
+#ifndef _LINUX
+static void irq_thread(void);
+#endif
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_g12_intrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_device_t  *device = (gsl_device_t *) cookie;
+
+    switch(id)
+    {
+        // non-error condition interrupt
+        case GSL_INTR_G12_G2D:
+#ifdef _LINUX
+			queue_work(device->irq_workq, &(device->irq_work));
+			break;
+#endif		
+#ifndef _Z180
+        case GSL_INTR_G12_FBC:
+#endif //_Z180
+            // signal intr completion event
+            kos_event_signal(device->intr.evnt[id]);
+            break;
+
+        // error condition interrupt
+        case GSL_INTR_G12_FIFO:
+		printk(KERN_ERR "GPU: Z160 FIFO Error\n");
+		schedule_work(&device->irq_err_work);
+		break;
+
+        case GSL_INTR_G12_MH:
+            // don't do anything. this is handled by the MMU manager
+            break;
+
+        default:
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_isr(gsl_device_t *device)
+{
+    unsigned int           status;
+#ifdef _DEBUG
+    REG_MH_MMU_PAGE_FAULT  page_fault = {0};
+    REG_MH_AXI_ERROR       axi_error  = {0};
+#endif // DEBUG
+
+    // determine if G12 is interrupting
+    device->ftbl.device_regread(device, (ADDR_VGC_IRQSTATUS >> 2), &status);
+
+    if (status)
+    {
+        // if G12 MH is interrupting, clear MH block interrupt first, then master G12 MH interrupt
+        if (status & (1 << VGC_IRQSTATUS_MH_FSHIFT))
+        {
+#ifdef _DEBUG
+            // obtain mh error information
+            device->ftbl.device_regread(device, ADDR_MH_MMU_PAGE_FAULT, (unsigned int *)&page_fault);
+            device->ftbl.device_regread(device, ADDR_MH_AXI_ERROR, (unsigned int *)&axi_error);
+#endif // DEBUG
+
+            kgsl_intr_decode(device, GSL_INTR_BLOCK_G12_MH);
+        }
+
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_G12);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid)
+{
+#ifndef GSL_NO_MMU
+    REG_MH_MMU_INVALIDATE  mh_mmu_invalidate = {0};
+
+    // unreferenced formal parameter
+	(void) pid;
+
+    mh_mmu_invalidate.INVALIDATE_ALL = 1;
+    mh_mmu_invalidate.INVALIDATE_TC  = 1;
+
+    device->ftbl.device_regwrite(device, reg_invalidate, *(unsigned int *) &mh_mmu_invalidate);
+#else
+    (void)device;
+    (void)reg_invalidate;
+#endif
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid)
+{
+	// unreferenced formal parameter
+	(void) pid;
+#ifndef GSL_NO_MMU
+    device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+	device->ftbl.device_regwrite(device, reg_ptbase, ptbase);
+#else
+    (void)device;
+    (void)reg_ptbase;
+    (void)reg_varange;
+#endif
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _LINUX
+static void kgsl_g12_updatetimestamp(gsl_device_t *device)
+{
+	unsigned int count = 0;
+	device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &count);
+	count >>= 8;
+	count &= 255;
+	device->timestamp += count;	
+#ifdef V3_SYNC
+	if (device->current_timestamp > device->timestamp)
+	{
+	    kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 2);
+	    kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
+	}
+#endif
+	kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), &device->timestamp, 4, 0);
+}
+
+//----------------------------------------------------------------------------
+
+static void kgsl_g12_irqtask(struct work_struct *work)
+{
+	gsl_device_t *device = &gsl_driver.device[GSL_DEVICE_G12-1];
+	kgsl_g12_updatetimestamp(device);
+	wake_up_interruptible_all(&device->timestamp_waitq);
+}
+
+static void kgsl_g12_irqerr(struct work_struct *work)
+{
+	gsl_device_t *device = &gsl_driver.device[GSL_DEVICE_G12-1];
+	device->ftbl.device_destroy(device);
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_init(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE; 
+
+    device->flags |= GSL_FLAGS_INITIALIZED;
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100);
+
+    // setup MH arbiter - MH offsets are considered to be dword based, therefore no down shift
+    device->ftbl.device_regwrite(device, ADDR_MH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_g12_mharb);
+
+    // init interrupt
+    status = kgsl_intr_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    // enable irq
+    device->ftbl.device_regwrite(device, (ADDR_VGC_IRQENABLE >> 2), 0x3);
+
+#ifndef GSL_NO_MMU
+    // enable master interrupt for G12 MH
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_MH, kgsl_g12_intrcallback, (void *) device);
+    kgsl_intr_enable(&device->intr, GSL_INTR_G12_MH);
+
+    // init mmu
+    status = kgsl_mmu_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+#endif
+
+#ifdef IRQTHREAD_POLL
+    // Create event to trigger IRQ polling thread
+    device->irqthread_event = kos_event_create(0);
+#endif
+
+    // enable interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_G2D,  kgsl_g12_intrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_FIFO, kgsl_g12_intrcallback, (void *) device);
+    kgsl_intr_enable(&device->intr, GSL_INTR_G12_G2D);
+    kgsl_intr_enable(&device->intr, GSL_INTR_G12_FIFO);
+
+#ifndef _Z180
+    kgsl_intr_attach(&device->intr, GSL_INTR_G12_FBC,  kgsl_g12_intrcallback, (void *) device);
+  //kgsl_intr_enable(&device->intr, GSL_INTR_G12_FBC);
+#endif //_Z180
+
+    // create thread for IRQ handling
+#if defined(__SYMBIAN32__)
+    kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) );
+#elif defined(_LINUX)
+	device->irq_workq = create_singlethread_workqueue("z1xx_workq");
+	INIT_WORK(&device->irq_work, kgsl_g12_irqtask);
+	INIT_WORK(&device->irq_err_work, kgsl_g12_irqerr);
+#else
+    #pragma warning(disable:4152)
+    device->irq_thread_handle = kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) );
+#endif
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_close(gsl_device_t *device)
+{
+    int status = GSL_FAILURE; 
+
+    if (device->refcnt == 0)
+    {
+        // wait pending interrupts before shutting down G12 intr thread to
+        // empty irq counters. Otherwise there's a possibility to have them in
+        // registers next time systems starts up and this results in a hang.
+        status = device->ftbl.device_idle(device, 1000);
+        KOS_ASSERT(status == GSL_SUCCESS);
+
+#ifndef _LINUX
+        kos_thread_destroy(device->irq_thread_handle);
+#else
+		destroy_workqueue(device->irq_workq);
+#endif
+
+        // shutdown command window
+        kgsl_cmdwindow_close(device);
+
+#ifndef GSL_NO_MMU
+        // shutdown mmu
+        kgsl_mmu_close(device);
+#endif
+        // disable interrupts
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_MH);
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_G2D);
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_FIFO);
+#ifndef _Z180
+        kgsl_intr_detach(&device->intr, GSL_INTR_G12_FBC);
+#endif //_Z180
+
+        // shutdown interrupt
+        kgsl_intr_close(device);
+
+        kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0);
+
+        device->flags &= ~GSL_FLAGS_INITIALIZED;
+
+#if defined(__SYMBIAN32__)
+        while(device->irq_thread)
+        {
+            kos_sleep(20);
+        }
+#endif
+        drawctx_id = 0;
+
+        KOS_ASSERT(g_z1xx.numcontext == 0);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_destroy(gsl_device_t *device)
+{
+    int           i;
+    unsigned int  pid;
+
+#ifdef _DEBUG
+    // for now, signal catastrophic failure in a brute force way
+    KOS_ASSERT(0);
+#endif // _DEBUG
+
+    //todo: hard reset core?
+
+    for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++)
+    {
+        pid = device->callerprocess[i];
+        if (pid)
+        {
+            device->ftbl.device_stop(device);
+            kgsl_driver_destroy(pid);
+
+            // todo: terminate client process?
+        }
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_start(gsl_device_t *device, gsl_flags_t flags)
+{
+    int  status = GSL_SUCCESS;
+
+    (void) flags;       // unreferenced formal parameter
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100);
+
+    // init command window
+    status = kgsl_cmdwindow_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    KOS_ASSERT(g_z1xx.numcontext == 0);
+
+    device->flags |= GSL_FLAGS_STARTED;
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_stop(gsl_device_t *device)
+{
+    int status;
+
+    KOS_ASSERT(device->refcnt == 0);
+
+    /* wait for device to idle before setting it's clock off */
+    status = device->ftbl.device_idle(device, 1000);
+    KOS_ASSERT(status == GSL_SUCCESS);
+
+    status = kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0);
+    device->flags &= ~GSL_FLAGS_STARTED;
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+    // unreferenced formal parameter
+    (void) sizebytes;
+
+    if (type == GSL_PROP_DEVICE_INFO)
+    {
+        gsl_devinfo_t  *devinfo = (gsl_devinfo_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t));
+
+        devinfo->device_id   = device->id;
+        devinfo->chip_id     = (gsl_chipid_t)device->chip_id;
+#ifndef GSL_NO_MMU
+        devinfo->mmu_enabled = kgsl_mmu_isenabled(&device->mmu);
+#endif
+	if (z160_version == 1)
+	    devinfo->high_precision = 1;
+	else
+	    devinfo->high_precision = 0;
+
+        status = GSL_SUCCESS;
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+
+    // unreferenced formal parameters
+    (void) device;          
+
+    if (type == GSL_PROP_DEVICE_POWER)
+    {
+        gsl_powerprop_t  *power = (gsl_powerprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t));
+
+        if (!(device->flags & GSL_FLAGS_SAFEMODE))
+        {
+            kgsl_hal_setpowerstate(device->id, power->flags, power->value);
+        }
+
+        status = GSL_SUCCESS;
+    }
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int             
+kgsl_g12_idle(gsl_device_t *device, unsigned int timeout)
+{
+	if ( device->flags & GSL_FLAGS_STARTED )
+	{
+		for ( ; ; )
+		{
+			gsl_timestamp_t retired = kgsl_cmdstream_readtimestamp0( device->id, GSL_TIMESTAMP_RETIRED );
+			gsl_timestamp_t ts_diff = retired - device->current_timestamp;
+			if ( ts_diff >= 0 || ts_diff < -GSL_TIMESTAMP_EPSILON )
+				break;
+			kos_sleep(10);
+		}
+	}
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int    
+kgsl_g12_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value)
+{
+    // G12 MH register values can only be retrieved via dedicated read registers
+    if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) ||
+        (offsetwords >= ADDR_MH_MMU_CONFIG     && offsetwords <= ADDR_MH_MMU_MPU_END))
+    {
+#ifdef _Z180
+        device->ftbl.device_regwrite(device, (ADDR_VGC_MH_READ_ADDR >> 2), offsetwords);
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_VGC_MH_READ_ADDR >> 2), value);
+#else
+        device->ftbl.device_regwrite(device, (ADDR_MMU_READ_ADDR >> 2), offsetwords);
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_MMU_READ_DATA >> 2), value);
+#endif
+    }
+    else
+    {
+        GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value)
+{
+    // G12 MH registers can only be written via the command window
+    if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) ||
+        (offsetwords >= ADDR_MH_MMU_CONFIG     && offsetwords <= ADDR_MH_MMU_MPU_END))
+    {
+        kgsl_cmdwindow_write0(device->id, GSL_CMDWINDOW_MMU, offsetwords, value);
+    }
+    else
+    {
+        GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+    }
+
+    // idle device when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout)
+{
+    int  status = GSL_FAILURE_NOTSUPPORTED;
+#ifdef VG_HDK
+    (void)timeout;
+#endif
+
+#ifndef _Z180
+    if (intr_id == GSL_INTR_G12_G2D || intr_id == GSL_INTR_G12_FBC)
+#else
+        if (intr_id == GSL_INTR_G12_G2D)
+#endif //_Z180
+        {
+#ifndef VG_HDK
+            if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS)
+#endif
+            {
+                // wait until intr completion event is received and check that 
+                // the interrupt is still enabled. If event is received, but
+                // interrupt is not enabled any more, the driver is shutting 
+                // down and event structure is not valid anymore.
+#ifndef VG_HDK
+                if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS && kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS)
+#endif
+                {
+                    unsigned int cntrs;
+                    int          i;
+                    kgsl_device_active(device);
+#ifndef VG_HDK
+                    kos_event_reset(device->intr.evnt[intr_id]);
+                    device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &cntrs);
+#else
+                    device->ftbl.device_regread(device, (0x38 >> 2), &cntrs);
+#endif
+
+                    for (i = 0; i < GSL_G12_INTR_COUNT; i++) 
+                    {
+                        int intrcnt = cntrs >> ((8 * i)) & 255;
+
+                        // maximum allowed counter value is 254. if set to 255 then something has gone wrong
+                        if (intrcnt && (intrcnt < 0xFF))
+                        {
+                            device->intrcnt[i] += intrcnt;
+                        }
+                    }
+
+                    *count = device->intrcnt[intr_id - GSL_INTR_G12_MH];
+                    device->intrcnt[intr_id - GSL_INTR_G12_MH] = 0;
+                    status = GSL_SUCCESS;
+                }
+#ifndef VG_HDK
+                else
+                {
+                    status = GSL_FAILURE_TIMEOUT;
+                }
+#endif
+            }
+        }
+    else if(intr_id == GSL_INTR_FOOBAR)
+    {
+        if (kgsl_intr_isenabled(&device->intr, GSL_INTR_G12_G2D) == GSL_SUCCESS)
+        {
+            kos_event_signal(device->intr.evnt[GSL_INTR_G12_G2D]);
+        }
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_g12_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout)
+{
+#ifndef _LINUX
+	return kos_event_wait( device->timestamp_event, timeout );
+#else
+	int status = wait_event_interruptible_timeout(device->timestamp_waitq,
+	                                              kgsl_cmdstream_check_timestamp(device->id, timestamp),
+												  msecs_to_jiffies(timeout));
+	if (status > 0)
+		return GSL_SUCCESS;
+	else
+		return GSL_FAILURE;
+#endif
+}
+
+int
+kgsl_g12_getfunctable(gsl_functable_t *ftbl)
+{
+    ftbl->device_init           = kgsl_g12_init;
+    ftbl->device_close          = kgsl_g12_close;
+    ftbl->device_destroy        = kgsl_g12_destroy;
+    ftbl->device_start          = kgsl_g12_start;
+    ftbl->device_stop           = kgsl_g12_stop;
+    ftbl->device_getproperty    = kgsl_g12_getproperty;
+    ftbl->device_setproperty    = kgsl_g12_setproperty;
+    ftbl->device_idle           = kgsl_g12_idle;
+    ftbl->device_regread        = kgsl_g12_regread;
+    ftbl->device_regwrite       = kgsl_g12_regwrite;
+    ftbl->device_waitirq        = kgsl_g12_waitirq;
+	ftbl->device_waittimestamp  = kgsl_g12_waittimestamp;
+    ftbl->device_runpending     = NULL;
+    ftbl->device_addtimestamp   = kgsl_g12_addtimestamp;
+    ftbl->intr_isr              = kgsl_g12_isr;
+    ftbl->mmu_tlbinvalidate     = kgsl_g12_tlbinvalidate;
+    ftbl->mmu_setpagetable      = kgsl_g12_setpagetable;
+    ftbl->cmdstream_issueibcmds = kgsl_g12_issueibcmds;
+    ftbl->context_create        = kgsl_g12_context_create;
+    ftbl->context_destroy       = kgsl_g12_context_destroy;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static void addmarker(gsl_z1xx_t* z1xx)
+{
+    KOS_ASSERT(z1xx);
+    {
+        unsigned int *p = z1xx->cmdbuf[z1xx->curr];
+        /* todo: use symbolic values */
+        p[z1xx->offs++] = 0x7C000176;
+        p[z1xx->offs++] = (0x8000|5);
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = 0x7C000176;
+        p[z1xx->offs++] = 5;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+        p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    }
+}
+
+//----------------------------------------------------------------------------
+static void beginpacket(gsl_z1xx_t* z1xx, gpuaddr_t cmd, unsigned int nextcnt)
+{
+    unsigned int *p = z1xx->cmdbuf[z1xx->curr];
+   
+    p[z1xx->offs++] = 0x7C000176;
+    p[z1xx->offs++] = 5;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = 0x7C000275;
+    p[z1xx->offs++] = cmd;
+    p[z1xx->offs++] = 0x1000|nextcnt;  // nextcount
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+    p[z1xx->offs++] = ADDR_VGV3_LAST<<24;
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags)
+{
+    unsigned int ofs      = PACKETSIZE_STATESTREAM*sizeof(unsigned int);
+    unsigned int cnt      = 5;
+    unsigned int cmd      = ibaddr; 
+    unsigned int nextbuf  = (g_z1xx.curr+1)%GSL_HAL_NUMCMDBUFFERS;
+    unsigned int nextaddr = g_z1xx.cmdbufdesc[nextbuf].gpuaddr;
+    unsigned int nextcnt  = 0x9000|5;
+    gsl_memdesc_t tmp     = {0};
+    gsl_timestamp_t processed_timestamp;
+
+    (void) flags;
+
+    // read what is the latest timestamp device have processed
+    GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp);
+
+	/* wait for the next buffer's timestamp to occur */
+    while(processed_timestamp < g_z1xx.timestamp[nextbuf])
+    {
+#ifndef _LINUX	
+		kos_event_wait(device->timestamp_event, 1000);
+		kos_event_reset(device->timestamp_event);
+#else
+		kgsl_cmdstream_waittimestamp(device->id, g_z1xx.timestamp[nextbuf], 1000);
+#endif		
+		GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp);
+    }
+	
+    *timestamp = g_z1xx.timestamp[nextbuf] = device->current_timestamp + 1;
+
+    /* context switch */
+    if (drawctxt_index != (int)g_z1xx.prevctx)
+    {
+        cnt = PACKETSIZE_STATESTREAM;
+        ofs = 0; 
+    }
+    g_z1xx.prevctx = drawctxt_index;
+
+    g_z1xx.offs = 10;
+    beginpacket(&g_z1xx, cmd+ofs, cnt);
+
+    tmp.gpuaddr=ibaddr+(sizedwords*sizeof(unsigned int));
+    kgsl_sharedmem_write0(&tmp, 4, &nextaddr, 4, false);
+    kgsl_sharedmem_write0(&tmp, 8, &nextcnt,  4, false);
+
+    /* sync mem */ 
+    kgsl_sharedmem_write0((const gsl_memdesc_t *)&g_z1xx.cmdbufdesc[g_z1xx.curr], 0, g_z1xx.cmdbuf[g_z1xx.curr], (512 + 13) * sizeof(unsigned int), false);
+
+    g_z1xx.offs = 0;
+    g_z1xx.curr = nextbuf;
+
+    /* increment mark counter */
+#ifdef V3_SYNC
+    if (device->timestamp == device->current_timestamp)
+    {
+		kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, flags);
+		kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
+    }
+#else
+	kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, flags);
+	kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
+#endif
+
+    /* increment consumed timestamp */
+    device->current_timestamp++;
+    kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp), &device->current_timestamp, 4, 0);
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags)
+{
+    int status = 0;
+    int i;
+    int cmd;
+	gsl_flags_t gslflags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGNPAGE);
+
+    // unreferenced formal parameters
+    (void) device;
+    (void) type;
+    //(void) drawctxt_id;
+    (void) flags;
+    
+    kgsl_device_active(device);
+    
+    if (g_z1xx.numcontext==0)
+    {
+	g_z1xx.nextUniqueContextID = 0;
+         /* todo: move this to device create or start. Error checking!! */ 
+        for (i=0;i<GSL_HAL_NUMCMDBUFFERS;i++)
+        {
+            status = kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_CMDBUFFERSIZE, &g_z1xx.cmdbufdesc[i]);
+            KOS_ASSERT(status == GSL_SUCCESS);          
+            g_z1xx.cmdbuf[i]=kos_malloc(GSL_HAL_CMDBUFFERSIZE);
+            KOS_ASSERT(g_z1xx.cmdbuf[i]);
+            kos_memset((void*)g_z1xx.cmdbuf[i], 0, GSL_HAL_CMDBUFFERSIZE);
+                  
+            g_z1xx.curr = i;
+            g_z1xx.offs = 0;
+            addmarker(&g_z1xx);
+            status = kgsl_sharedmem_write0(&g_z1xx.cmdbufdesc[i],0, g_z1xx.cmdbuf[i],  (512 + 13) * sizeof(unsigned int), false);
+            KOS_ASSERT(status == GSL_SUCCESS);
+        }
+        g_z1xx.curr = 0;
+        cmd = (int)(((VGV3_NEXTCMD_JUMP) & VGV3_NEXTCMD_NEXTCMD_FMASK)<< VGV3_NEXTCMD_NEXTCMD_FSHIFT);
+
+        /* set cmd stream buffer to hw */
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, ADDR_VGV3_MODE, 4);
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, ADDR_VGV3_NEXTADDR, g_z1xx.cmdbufdesc[0].gpuaddr );
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, ADDR_VGV3_NEXTCMD,  cmd | 5);
+
+        KOS_ASSERT(status == GSL_SUCCESS);
+
+        /* Edge buffer setup todo: move register setup to own function. 
+           This function can be then called, if power managemnet is used and clocks are turned off and then on.
+        */ 
+        status |= kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_EDGE0BUFSIZE, &g_z1xx.e0);
+        status |= kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_EDGE1BUFSIZE, &g_z1xx.e1);
+        status |= kgsl_sharedmem_set0(&g_z1xx.e0, 0, 0, GSL_HAL_EDGE0BUFSIZE);
+        status |= kgsl_sharedmem_set0(&g_z1xx.e1, 0, 0, GSL_HAL_EDGE1BUFSIZE);
+
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, GSL_HAL_EDGE0REG, g_z1xx.e0.gpuaddr);
+        status |= kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, GSL_HAL_EDGE1REG, g_z1xx.e1.gpuaddr);
+#ifdef _Z180
+        kgsl_sharedmem_alloc0(GSL_DEVICE_ANY, gslflags, GSL_HAL_EDGE2BUFSIZE, &g_z1xx.e2);
+        kgsl_sharedmem_set0(&g_z1xx.e2, 0, 0, GSL_HAL_EDGE2BUFSIZE);
+        kgsl_cmdwindow_write0(GSL_DEVICE_G12, GSL_CMDWINDOW_2D, GSL_HAL_EDGE2REG, g_z1xx.e2.gpuaddr);
+#endif  
+        KOS_ASSERT(status == GSL_SUCCESS);
+    } 
+
+    if(g_z1xx.numcontext < GSL_CONTEXT_MAX)
+    {
+        g_z1xx.numcontext++;
+	g_z1xx.nextUniqueContextID++;
+	*drawctxt_id=g_z1xx.nextUniqueContextID;
+        status = GSL_SUCCESS;
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_context_destroy(gsl_device_t* device, unsigned int drawctxt_id)
+{
+
+    // unreferenced formal parameters
+    (void) device;
+    (void) drawctxt_id;
+
+    g_z1xx.numcontext--;
+    if (g_z1xx.numcontext<0)
+    {
+        g_z1xx.numcontext=0;
+        return (GSL_FAILURE);
+    }
+
+    if (g_z1xx.numcontext==0)
+    {
+        int i;
+        for (i=0;i<GSL_HAL_NUMCMDBUFFERS;i++)
+        {
+            kgsl_sharedmem_free0(&g_z1xx.cmdbufdesc[i], GSL_CALLER_PROCESSID_GET());
+            kos_free(g_z1xx.cmdbuf[i]);
+        }
+        kgsl_sharedmem_free0(&g_z1xx.e0, GSL_CALLER_PROCESSID_GET());
+        kgsl_sharedmem_free0(&g_z1xx.e1, GSL_CALLER_PROCESSID_GET());
+#ifdef _Z180
+        kgsl_sharedmem_free0(&g_z1xx.e2, GSL_CALLER_PROCESSID_GET());
+#endif
+        kos_memset(&g_z1xx,0,sizeof(gsl_z1xx_t));
+    }
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+#if !defined GSL_BLD_YAMATO && (!defined __SYMBIAN32__ || defined __WINSCW__)
+KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id)
+{
+    (void)device_id;
+    (void)drawctxt_id;
+    (void)gmem_rect;
+    (void)shadow_x;
+    (void)shadow_y;
+    (void)shadow_buffer;
+    (void)buffer_id;
+    return (GSL_FAILURE);
+}
+#endif
+//----------------------------------------------------------------------------
+
+#ifndef _LINUX
+static void irq_thread(void)
+{
+	int error = 0;
+    unsigned int irq_count;
+    gsl_device_t* device  = &gsl_driver.device[GSL_DEVICE_G12-1];
+    gsl_timestamp_t timestamp;
+
+    while( !error )
+    {
+#ifdef IRQTHREAD_POLL
+        if(kos_event_wait(device->irqthread_event, GSL_IRQ_TIMEOUT)==GSL_SUCCESS)
+        {
+            kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT);
+#else
+
+        if( kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT) == GSL_SUCCESS )
+        {
+#endif
+            /* Read a timestamp value */
+#ifdef VG_HDK            
+            timestamp = device->timestamp;
+#else
+            GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&timestamp);
+#endif
+            /* Increase the timestamp value */
+            timestamp += irq_count;
+
+            /* Write the new timestamp value */
+            device->timestamp = timestamp;
+            kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), &timestamp, 4, false);
+
+#ifdef V3_SYNC
+        	if (device->current_timestamp > device->timestamp)
+        	{
+        	    kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 2);
+        	    kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0);
+        	}
+#endif
+
+            /* Notify timestamp event */
+#ifndef _LINUX
+            kos_event_signal( device->timestamp_event );
+#else
+            wake_up_interruptible_all(&(device->timestamp_waitq));
+#endif
+        }
+        else
+        {
+            /* Timeout */
+
+           
+            if(!(device->flags&GSL_FLAGS_INITIALIZED))
+            {
+                /* if device is closed -> thread exit */
+#if defined(__SYMBIAN32__)
+                device->irq_thread = 0;
+#endif
+                return;
+            }
+        }
+    }
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp)
+{    
+    device->current_timestamp++;
+    *timestamp = device->current_timestamp;
+ 
+    return (GSL_SUCCESS);
+}
+#endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_intrmgr.c b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c
new file mode 100644
index 00000000000..4ea3bab594d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c
@@ -0,0 +1,300 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_INTRID_VALIDATE(id) (((id) < 0) || ((id) >= GSL_INTR_COUNT))
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static const gsl_intrblock_reg_t * 
+kgsl_intr_id2block(gsl_intrid_t id)
+{
+    const gsl_intrblock_reg_t  *block;
+    int                        i;
+
+    // interrupt id to hw block
+    for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) 
+    {
+        block = &gsl_cfg_intrblock_reg[i];
+
+        if (block->first_id <= id && id <= block->last_id) 
+        {
+            return (block);
+        }
+    }
+
+    return (NULL);
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id)
+{
+    const gsl_intrblock_reg_t  *block = &gsl_cfg_intrblock_reg[block_id];
+    gsl_intrid_t               id;
+    unsigned int               status;
+
+    // read the block's interrupt status bits
+    /* exclude CP block here to avoid hang in heavy loading with VPU+GPU */
+    if ((block_id == GSL_INTR_BLOCK_YDX_CP) && (device->flags & GSL_FLAGS_STARTED)) {
+	status = 0x80000000;
+    } else {
+	device->ftbl.device_regread(device, block->status_reg, &status);
+    }
+
+    // mask off any interrupts which are disabled
+    status &= device->intr.enabled[block->id];
+
+    // acknowledge the block's interrupts
+    device->ftbl.device_regwrite(device, block->clear_reg, status);
+
+    // loop through the block's masks, determine which interrupt bits are active, and call callback (or TODO queue DPC)
+    for (id = block->first_id; id <= block->last_id; id++) 
+    {
+        if (status & gsl_cfg_intr_mask[id])
+        {
+            device->intr.handler[id].callback(id, device->intr.handler[id].cookie);
+        }
+    }
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API void
+kgsl_intr_isr(gsl_device_t *device)
+{
+    if (device->intr.flags & GSL_FLAGS_INITIALIZED) {
+	kgsl_device_active(device);
+	device->ftbl.intr_isr(device);
+    }
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_init(gsl_device_t *device)
+{
+    if (device->ftbl.intr_isr == NULL)
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (device->intr.flags & GSL_FLAGS_INITIALIZED)
+    {
+        return (GSL_SUCCESS);
+    }
+
+    device->intr.device  = device;
+    device->intr.flags  |= GSL_FLAGS_INITIALIZED;
+
+    // os_interrupt_setcallback(YAMATO_INTR, kgsl_intr_isr);
+    // os_interrupt_enable(YAMATO_INTR);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_close(gsl_device_t *device)
+{
+    const gsl_intrblock_reg_t  *block;
+    int                        i, id;
+
+    if (device->intr.flags & GSL_FLAGS_INITIALIZED)
+    {
+        // check if there are any enabled interrupts lingering around
+        for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) 
+        {
+            if (device->intr.enabled[i]) 
+            {
+                block = &gsl_cfg_intrblock_reg[i];
+
+                // loop through the block's masks, disable interrupts which active
+                for (id = block->first_id; id <= block->last_id; id++) 
+                {
+                    if (device->intr.enabled[i] & gsl_cfg_intr_mask[id])
+                    {
+                        kgsl_intr_disable(&device->intr, (gsl_intrid_t)id);
+                    }
+                }
+            }
+        }
+
+        kos_memset(&device->intr, 0, sizeof(gsl_intr_t));
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    const gsl_intrblock_reg_t  *block;
+    unsigned int               mask;
+    unsigned int               enabled;
+
+    if (GSL_INTRID_VALIDATE(id)) 
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback == NULL) 
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+
+    block = kgsl_intr_id2block(id);
+    if (block == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+    mask    = gsl_cfg_intr_mask[id];
+    enabled = intr->enabled[block->id];
+
+    if (mask && !(enabled & mask))
+    {
+        intr->evnt[id] = kos_event_create(0);
+
+        enabled                 |= mask;
+        intr->enabled[block->id] = enabled;
+        intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    const gsl_intrblock_reg_t  *block;
+    unsigned int               mask;
+    unsigned int               enabled;
+
+    if (GSL_INTRID_VALIDATE(id))
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback == NULL) 
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+
+    block = kgsl_intr_id2block(id);
+    if (block == NULL) 
+    {
+        return (GSL_FAILURE_SYSTEMERROR);
+    }
+
+    mask    = gsl_cfg_intr_mask[id];
+    enabled = intr->enabled[block->id];
+
+    if (enabled & mask) 
+    {
+        enabled                 &= ~mask;
+        intr->enabled[block->id] = enabled;
+        intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled);
+
+        kos_event_signal(intr->evnt[id]); // wake up waiting threads before destroying the event
+        kos_event_destroy(intr->evnt[id]);
+        intr->evnt[id] = 0;
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie)
+{
+    if (GSL_INTRID_VALIDATE(id) || callback == NULL) 
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback != NULL) 
+    {
+        if (intr->handler[id].callback == callback && intr->handler[id].cookie == cookie) 
+        {
+            return (GSL_FAILURE_ALREADYINITIALIZED);
+        } 
+        else 
+        {
+            return (GSL_FAILURE_NOMOREAVAILABLE);
+        }
+    }
+
+    intr->handler[id].callback = callback;
+    intr->handler[id].cookie   = cookie;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    if (GSL_INTRID_VALIDATE(id)) 
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (intr->handler[id].callback == NULL) 
+    {
+        return (GSL_FAILURE_NOTINITIALIZED);
+    }
+
+    kgsl_intr_disable(intr, id);
+
+    intr->handler[id].callback = NULL;
+    intr->handler[id].cookie   = NULL;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id)
+{
+    int                        status = GSL_FAILURE;
+    const gsl_intrblock_reg_t  *block = kgsl_intr_id2block(id);
+
+    if (block != NULL)
+    {
+        // check if interrupt is enabled
+        if (intr->enabled[block->id] & gsl_cfg_intr_mask[id])
+        {
+            status = GSL_SUCCESS;
+        }
+    }
+
+    return (status);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_log.c b/drivers/mxc/amd-gpu/common/gsl_log.c
new file mode 100644
index 00000000000..79a14a5f4b2
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_log.c
@@ -0,0 +1,591 @@
+/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#ifdef GSL_LOG
+
+#define _CRT_SECURE_NO_WARNINGS
+
+#include <stdarg.h>
+#include <stdio.h>
+#include <string.h>
+#include "gsl.h"
+
+#define KGSL_OUTPUT_TYPE_MEMBUF 0
+#define KGSL_OUTPUT_TYPE_STDOUT 1
+#define KGSL_OUTPUT_TYPE_FILE   2
+
+#define REG_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break;
+#define INTRID_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break;
+
+typedef struct log_output
+{
+    unsigned char       type;
+    unsigned int        flags;
+    oshandle_t         file;
+
+    struct log_output*  next;
+} log_output_t;
+
+static log_output_t* outputs = NULL;
+
+static oshandle_t   log_mutex = NULL;
+static char         buffer[256];
+static char         buffer2[256];
+static int          log_initialized = 0;
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_init()
+{
+    log_mutex = kos_mutex_create( "log_mutex" );
+
+    log_initialized = 1;
+    
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_close()
+{
+    if( !log_initialized ) return GSL_SUCCESS;
+
+    // Go throught output list and free every node
+    while( outputs != NULL )
+    {
+        log_output_t* temp = outputs->next;
+        
+        switch( outputs->type )
+        {
+            case KGSL_OUTPUT_TYPE_FILE:
+                kos_fclose( outputs->file );
+            break;
+        }
+
+        kos_free( outputs );
+        outputs = temp;
+    }
+
+    kos_mutex_free( log_mutex );
+
+    log_initialized = 0;
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_open_stdout( unsigned int log_flags )
+{
+    log_output_t* output;
+    
+    if( !log_initialized ) return GSL_SUCCESS;
+    
+    output = kos_malloc( sizeof( log_output_t ) );
+    output->type = KGSL_OUTPUT_TYPE_STDOUT;
+    output->flags = log_flags;
+
+    // Add to the list
+    if( outputs == NULL )    
+    {
+        // First node in the list.
+        outputs = output;
+        output->next = NULL;
+    }
+    else
+    {
+        // Add to the start of the list
+        output->next = outputs;
+        outputs = output;
+    }
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags )
+{
+    // TODO
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_open_file( char* filename, unsigned int log_flags )
+{
+    log_output_t* output;
+    
+    if( !log_initialized ) return GSL_SUCCESS;
+    
+    output = kos_malloc( sizeof( log_output_t ) );
+    output->type = KGSL_OUTPUT_TYPE_FILE;
+    output->flags = log_flags;
+    output->file = kos_fopen( filename, "w" );
+
+    // Add to the list
+    if( outputs == NULL )    
+    {
+        // First node in the list.
+        outputs = output;
+        output->next = NULL;
+    }
+    else
+    {
+        // Add to the start of the list
+        output->next = outputs;
+        outputs = output;
+    }
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+int kgsl_log_flush_membuf( char* filename, int memBufId )
+{
+    // TODO
+
+    return GSL_SUCCESS;
+}
+//----------------------------------------------------------------------------
+
+int kgsl_log_write( unsigned int log_flags, char* format, ... )
+{
+    char            *c = format;
+    char            *b = buffer;
+    char            *p1, *p2;
+    log_output_t*   output;
+    va_list         arguments;
+
+    if( !log_initialized ) return GSL_SUCCESS;
+
+    // Acquire mutex lock as we are using shared buffer for the string parsing
+    kos_mutex_lock( log_mutex );
+
+    // Add separator
+    *(b++) = '|'; *(b++) = ' ';
+
+    va_start( arguments, format );
+
+    while( 1 )
+    {
+        // Find the first occurence of %
+        p1 = strchr( c, '%' );
+        if( !p1 ) 
+        {
+            // No more % characters -> copy rest of the string
+            strcpy( b, c );
+
+            break;
+        }
+
+        // Find the second occurence of % and handle the string until that point
+        p2 = strchr( p1+1, '%' );
+
+        // If not found, just use the end of the buffer
+        if( !p2 ) p2 = strchr( p1+1, '\0' );
+
+        // Break the string to this point
+        kos_memcpy( buffer2, c, p2-c );
+        *(buffer2+(unsigned int)(p2-c)) = '\0';
+
+        switch( *(p1+1) )
+        {
+            // gsl_memdesc_t
+            case 'M':
+            {
+                gsl_memdesc_t val = va_arg( arguments, gsl_memdesc_t );
+                // Handle string before %M
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %M
+                b += sprintf( b, "[hostptr=0x%08x, gpuaddr=0x%08x]", val.hostptr, val.gpuaddr );
+                // Handle string after %M
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+            // GSL_SUCCESS/GSL_FAILURE
+            case 'B':
+            {
+                int val = va_arg( arguments, int );
+                // Handle string before %B
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %B
+                if( val == GSL_SUCCESS )
+                    b += sprintf( b, "%s", "GSL_SUCCESS" );
+                else
+                    b += sprintf( b, "%s", "GSL_FAILURE" );
+                // Handle string after %B
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+            // gsl_deviceid_t
+            case 'D':
+            {
+                gsl_deviceid_t val = va_arg( arguments, gsl_deviceid_t );
+                // Handle string before %D
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %D
+                switch( val )
+                {
+                    case GSL_DEVICE_ANY:
+                        b += sprintf( b, "%s", "GSL_DEVICE_ANY" );
+                    break;
+                    case GSL_DEVICE_YAMATO:
+                        b += sprintf( b, "%s", "GSL_DEVICE_YAMATO" );
+                    break;
+                    case GSL_DEVICE_G12:
+                        b += sprintf( b, "%s", "GSL_DEVICE_G12" );
+                    break;
+                    default:
+                        b += sprintf( b, "%s", "UNKNOWN DEVICE" );
+                    break;
+                }
+                // Handle string after %D
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+            
+            // gsl_intrid_t
+            case 'I':
+            {
+                unsigned int val = va_arg( arguments, unsigned int );
+                // Handle string before %I
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %I
+                switch( val )
+                {
+                    INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_READ_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_WRITE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_MH_MMU_PAGE_FAULT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_SW_INT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_T0_PACKET_IN_IB );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_OPCODE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_RESERVED_BIT_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_IB_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_IB2_INT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_IB1_INT );
+                    INTRID_OUTPUT( GSL_INTR_YDX_CP_RING_BUFFER );
+                    INTRID_OUTPUT( GSL_INTR_YDX_RBBM_READ_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_YDX_RBBM_DISPLAY_UPDATE );
+                    INTRID_OUTPUT( GSL_INTR_YDX_RBBM_GUI_IDLE );
+                    INTRID_OUTPUT( GSL_INTR_YDX_SQ_PS_WATCHDOG );
+                    INTRID_OUTPUT( GSL_INTR_YDX_SQ_VS_WATCHDOG );
+                    INTRID_OUTPUT( GSL_INTR_G12_MH );
+                    INTRID_OUTPUT( GSL_INTR_G12_G2D );
+                    INTRID_OUTPUT( GSL_INTR_G12_FIFO );
+#ifndef _Z180
+                    INTRID_OUTPUT( GSL_INTR_G12_FBC );
+#endif // _Z180
+                    INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_READ_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_WRITE_ERROR );
+                    INTRID_OUTPUT( GSL_INTR_G12_MH_MMU_PAGE_FAULT );
+                    INTRID_OUTPUT( GSL_INTR_COUNT );
+                    INTRID_OUTPUT( GSL_INTR_FOOBAR );
+
+                    default:
+                        b += sprintf( b, "%s", "UNKNOWN INTERRUPT ID" );
+                    break;
+                }
+                // Handle string after %I
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+            // Register offset
+            case 'R':
+            {
+                unsigned int val = va_arg( arguments, unsigned int );
+                
+                // Handle string before %R
+                kos_memcpy( b, c, p1-c );
+                b += (unsigned int)p1-(unsigned int)c;
+                // Replace %R
+                switch( val )
+                {
+                    REG_OUTPUT( mmPA_CL_VPORT_XSCALE ); REG_OUTPUT( mmPA_CL_VPORT_XOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_YSCALE );
+                    REG_OUTPUT( mmPA_CL_VPORT_YOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_ZSCALE ); REG_OUTPUT( mmPA_CL_VPORT_ZOFFSET );
+                    REG_OUTPUT( mmPA_CL_VTE_CNTL ); REG_OUTPUT( mmPA_CL_CLIP_CNTL ); REG_OUTPUT( mmPA_CL_GB_VERT_CLIP_ADJ );
+                    REG_OUTPUT( mmPA_CL_GB_VERT_DISC_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_CLIP_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_DISC_ADJ );
+                    REG_OUTPUT( mmPA_CL_ENHANCE ); REG_OUTPUT( mmPA_SC_ENHANCE ); REG_OUTPUT( mmPA_SU_VTX_CNTL );
+                    REG_OUTPUT( mmPA_SU_POINT_SIZE ); REG_OUTPUT( mmPA_SU_POINT_MINMAX ); REG_OUTPUT( mmPA_SU_LINE_CNTL );
+                    REG_OUTPUT( mmPA_SU_FACE_DATA ); REG_OUTPUT( mmPA_SU_SC_MODE_CNTL ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_SCALE );
+                    REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_OFFSET ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_SCALE ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_OFFSET );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_SELECT );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_HI );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER1_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_LOW );
+                    REG_OUTPUT( mmPA_SU_PERFCOUNTER2_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_HI );
+                    REG_OUTPUT( mmPA_SC_WINDOW_OFFSET ); REG_OUTPUT( mmPA_SC_AA_CONFIG ); REG_OUTPUT( mmPA_SC_AA_MASK );
+                    REG_OUTPUT( mmPA_SC_LINE_STIPPLE ); REG_OUTPUT( mmPA_SC_LINE_CNTL ); REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_TL );
+                    REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_BR ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_TL ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_BR );
+                    REG_OUTPUT( mmPA_SC_VIZ_QUERY ); REG_OUTPUT( mmPA_SC_VIZ_QUERY_STATUS ); REG_OUTPUT( mmPA_SC_LINE_STIPPLE_STATE );
+                    REG_OUTPUT( mmPA_SC_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_HI );
+                    REG_OUTPUT( mmPA_CL_CNTL_STATUS ); REG_OUTPUT( mmPA_SU_CNTL_STATUS ); REG_OUTPUT( mmPA_SC_CNTL_STATUS );
+                    REG_OUTPUT( mmPA_SU_DEBUG_CNTL ); REG_OUTPUT( mmPA_SU_DEBUG_DATA ); REG_OUTPUT( mmPA_SC_DEBUG_CNTL );
+                    REG_OUTPUT( mmPA_SC_DEBUG_DATA ); REG_OUTPUT( mmGFX_COPY_STATE ); REG_OUTPUT( mmVGT_DRAW_INITIATOR );
+                    REG_OUTPUT( mmVGT_EVENT_INITIATOR ); REG_OUTPUT( mmVGT_DMA_BASE ); REG_OUTPUT( mmVGT_DMA_SIZE );
+                    REG_OUTPUT( mmVGT_BIN_BASE ); REG_OUTPUT( mmVGT_BIN_SIZE ); REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MIN );
+                    REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MAX ); REG_OUTPUT( mmVGT_IMMED_DATA ); REG_OUTPUT( mmVGT_MAX_VTX_INDX );
+                    REG_OUTPUT( mmVGT_MIN_VTX_INDX ); REG_OUTPUT( mmVGT_INDX_OFFSET ); REG_OUTPUT( mmVGT_VERTEX_REUSE_BLOCK_CNTL );
+                    REG_OUTPUT( mmVGT_OUT_DEALLOC_CNTL ); REG_OUTPUT( mmVGT_MULTI_PRIM_IB_RESET_INDX ); REG_OUTPUT( mmVGT_ENHANCE );
+                    REG_OUTPUT( mmVGT_VTX_VECT_EJECT_REG ); REG_OUTPUT( mmVGT_LAST_COPY_STATE ); REG_OUTPUT( mmVGT_DEBUG_CNTL );
+                    REG_OUTPUT( mmVGT_DEBUG_DATA ); REG_OUTPUT( mmVGT_CNTL_STATUS ); REG_OUTPUT( mmVGT_CRC_SQ_DATA );
+                    REG_OUTPUT( mmVGT_CRC_SQ_CTRL ); REG_OUTPUT( mmVGT_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER0_LOW );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER1_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER2_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER3_LOW );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER0_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER1_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER2_HI );
+                    REG_OUTPUT( mmVGT_PERFCOUNTER3_HI ); REG_OUTPUT( mmTC_CNTL_STATUS ); REG_OUTPUT( mmTCR_CHICKEN );
+                    REG_OUTPUT( mmTCF_CHICKEN ); REG_OUTPUT( mmTCM_CHICKEN ); REG_OUTPUT( mmTCR_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmTCR_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTCR_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCR_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmTCR_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCR_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTP_TC_CLKGATE_CNTL );
+                    REG_OUTPUT( mmTPC_CNTL_STATUS ); REG_OUTPUT( mmTPC_DEBUG0 ); REG_OUTPUT( mmTPC_DEBUG1 );
+                    REG_OUTPUT( mmTPC_CHICKEN ); REG_OUTPUT( mmTP0_CNTL_STATUS ); REG_OUTPUT( mmTP0_DEBUG );
+                    REG_OUTPUT( mmTP0_CHICKEN ); REG_OUTPUT( mmTP0_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER0_HI );
+                    REG_OUTPUT( mmTP0_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTP0_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmTP0_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCM_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCM_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmTCM_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER1_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER0_LOW );
+                    REG_OUTPUT( mmTCM_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER4_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER5_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER6_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER7_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER8_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER9_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER10_SELECT );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER11_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER2_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER3_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER4_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER5_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER6_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER7_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER8_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER9_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER10_HI );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER11_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER1_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER2_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER3_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER4_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER5_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER6_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER7_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER8_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER9_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER10_LOW );
+                    REG_OUTPUT( mmTCF_PERFCOUNTER11_LOW ); REG_OUTPUT( mmTCF_DEBUG ); REG_OUTPUT( mmTCA_FIFO_DEBUG );
+                    REG_OUTPUT( mmTCA_PROBE_DEBUG ); REG_OUTPUT( mmTCA_TPC_DEBUG ); REG_OUTPUT( mmTCB_CORE_DEBUG );
+                    REG_OUTPUT( mmTCB_TAG0_DEBUG ); REG_OUTPUT( mmTCB_TAG1_DEBUG ); REG_OUTPUT( mmTCB_TAG2_DEBUG );
+                    REG_OUTPUT( mmTCB_TAG3_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_WALKER_DEBUG );
+                    REG_OUTPUT( mmTCB_FETCH_GEN_PIPE0_DEBUG ); REG_OUTPUT( mmTCD_INPUT0_DEBUG ); REG_OUTPUT( mmTCD_DEGAMMA_DEBUG );
+                    REG_OUTPUT( mmTCD_DXTMUX_SCTARB_DEBUG ); REG_OUTPUT( mmTCD_DXTC_ARB_DEBUG ); REG_OUTPUT( mmTCD_STALLS_DEBUG );
+                    REG_OUTPUT( mmTCO_STALLS_DEBUG ); REG_OUTPUT( mmTCO_QUAD0_DEBUG0 ); REG_OUTPUT( mmTCO_QUAD0_DEBUG1 );
+                    REG_OUTPUT( mmSQ_GPR_MANAGEMENT ); REG_OUTPUT( mmSQ_FLOW_CONTROL ); REG_OUTPUT( mmSQ_INST_STORE_MANAGMENT );
+                    REG_OUTPUT( mmSQ_RESOURCE_MANAGMENT ); REG_OUTPUT( mmSQ_EO_RT ); REG_OUTPUT( mmSQ_DEBUG_MISC );
+                    REG_OUTPUT( mmSQ_ACTIVITY_METER_CNTL ); REG_OUTPUT( mmSQ_ACTIVITY_METER_STATUS ); REG_OUTPUT( mmSQ_INPUT_ARB_PRIORITY );
+                    REG_OUTPUT( mmSQ_THREAD_ARB_PRIORITY ); REG_OUTPUT( mmSQ_VS_WATCHDOG_TIMER ); REG_OUTPUT( mmSQ_PS_WATCHDOG_TIMER );
+                    REG_OUTPUT( mmSQ_INT_CNTL ); REG_OUTPUT( mmSQ_INT_STATUS ); REG_OUTPUT( mmSQ_INT_ACK );
+                    REG_OUTPUT( mmSQ_DEBUG_INPUT_FSM ); REG_OUTPUT( mmSQ_DEBUG_CONST_MGR_FSM ); REG_OUTPUT( mmSQ_DEBUG_TP_FSM );
+                    REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_0 ); REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_1 ); REG_OUTPUT( mmSQ_DEBUG_EXP_ALLOC );
+                    REG_OUTPUT( mmSQ_DEBUG_PTR_BUFF ); REG_OUTPUT( mmSQ_DEBUG_GPR_VTX ); REG_OUTPUT( mmSQ_DEBUG_GPR_PIX );
+                    REG_OUTPUT( mmSQ_DEBUG_TB_STATUS_SEL ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_0 ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_1 );
+                    REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATUS_REG ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_0 );
+                    REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_0 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_1 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_2 );
+                    REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_3 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER3_SELECT );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER1_LOW );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER1_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER2_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER2_HI );
+                    REG_OUTPUT( mmSQ_PERFCOUNTER3_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER3_HI ); REG_OUTPUT( mmSX_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmSX_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSX_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_ALU_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_0 );
+                    REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_2 ); REG_OUTPUT( mmSQ_CONSTANT_0 );
+                    REG_OUTPUT( mmSQ_CONSTANT_1 ); REG_OUTPUT( mmSQ_CONSTANT_2 ); REG_OUTPUT( mmSQ_CONSTANT_3 );
+                    REG_OUTPUT( mmSQ_FETCH_0 ); REG_OUTPUT( mmSQ_FETCH_1 ); REG_OUTPUT( mmSQ_FETCH_2 );
+                    REG_OUTPUT( mmSQ_FETCH_3 ); REG_OUTPUT( mmSQ_FETCH_4 ); REG_OUTPUT( mmSQ_FETCH_5 );
+                    REG_OUTPUT( mmSQ_CONSTANT_VFETCH_0 ); REG_OUTPUT( mmSQ_CONSTANT_VFETCH_1 ); REG_OUTPUT( mmSQ_CONSTANT_T2 );
+                    REG_OUTPUT( mmSQ_CONSTANT_T3 ); REG_OUTPUT( mmSQ_CF_BOOLEANS ); REG_OUTPUT( mmSQ_CF_LOOP );
+                    REG_OUTPUT( mmSQ_CONSTANT_RT_0 ); REG_OUTPUT( mmSQ_CONSTANT_RT_1 ); REG_OUTPUT( mmSQ_CONSTANT_RT_2 );
+                    REG_OUTPUT( mmSQ_CONSTANT_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_0 ); REG_OUTPUT( mmSQ_FETCH_RT_1 );
+                    REG_OUTPUT( mmSQ_FETCH_RT_2 ); REG_OUTPUT( mmSQ_FETCH_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_4 );
+                    REG_OUTPUT( mmSQ_FETCH_RT_5 ); REG_OUTPUT( mmSQ_CF_RT_BOOLEANS ); REG_OUTPUT( mmSQ_CF_RT_LOOP );
+                    REG_OUTPUT( mmSQ_VS_PROGRAM ); REG_OUTPUT( mmSQ_PS_PROGRAM ); REG_OUTPUT( mmSQ_CF_PROGRAM_SIZE );
+                    REG_OUTPUT( mmSQ_INTERPOLATOR_CNTL ); REG_OUTPUT( mmSQ_PROGRAM_CNTL ); REG_OUTPUT( mmSQ_WRAPPING_0 );
+                    REG_OUTPUT( mmSQ_WRAPPING_1 ); REG_OUTPUT( mmSQ_VS_CONST ); REG_OUTPUT( mmSQ_PS_CONST );
+                    REG_OUTPUT( mmSQ_CONTEXT_MISC ); REG_OUTPUT( mmSQ_CF_RD_BASE ); REG_OUTPUT( mmSQ_DEBUG_MISC_0 );
+                    REG_OUTPUT( mmSQ_DEBUG_MISC_1 ); REG_OUTPUT( mmMH_ARBITER_CONFIG ); REG_OUTPUT( mmMH_CLNT_AXI_ID_REUSE );
+                    REG_OUTPUT( mmMH_INTERRUPT_MASK ); REG_OUTPUT( mmMH_INTERRUPT_STATUS ); REG_OUTPUT( mmMH_INTERRUPT_CLEAR );
+                    REG_OUTPUT( mmMH_AXI_ERROR ); REG_OUTPUT( mmMH_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmMH_PERFCOUNTER1_SELECT );
+                    REG_OUTPUT( mmMH_PERFCOUNTER0_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER1_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER0_LOW );
+                    REG_OUTPUT( mmMH_PERFCOUNTER1_LOW ); REG_OUTPUT( mmMH_PERFCOUNTER0_HI ); REG_OUTPUT( mmMH_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmMH_DEBUG_CTRL ); REG_OUTPUT( mmMH_DEBUG_DATA ); REG_OUTPUT( mmMH_AXI_HALT_CONTROL );
+                    REG_OUTPUT( mmMH_MMU_CONFIG ); REG_OUTPUT( mmMH_MMU_VA_RANGE ); REG_OUTPUT( mmMH_MMU_PT_BASE );
+                    REG_OUTPUT( mmMH_MMU_PAGE_FAULT ); REG_OUTPUT( mmMH_MMU_TRAN_ERROR ); REG_OUTPUT( mmMH_MMU_INVALIDATE );
+                    REG_OUTPUT( mmMH_MMU_MPU_BASE ); REG_OUTPUT( mmMH_MMU_MPU_END ); REG_OUTPUT( mmWAIT_UNTIL );
+                    REG_OUTPUT( mmRBBM_ISYNC_CNTL ); REG_OUTPUT( mmRBBM_STATUS ); REG_OUTPUT( mmRBBM_DSPLY );
+                    REG_OUTPUT( mmRBBM_RENDER_LATEST ); REG_OUTPUT( mmRBBM_RTL_RELEASE ); REG_OUTPUT( mmRBBM_PATCH_RELEASE );
+                    REG_OUTPUT( mmRBBM_AUXILIARY_CONFIG ); REG_OUTPUT( mmRBBM_PERIPHID0 ); REG_OUTPUT( mmRBBM_PERIPHID1 );
+                    REG_OUTPUT( mmRBBM_PERIPHID2 ); REG_OUTPUT( mmRBBM_PERIPHID3 ); REG_OUTPUT( mmRBBM_CNTL );
+                    REG_OUTPUT( mmRBBM_SKEW_CNTL ); REG_OUTPUT( mmRBBM_SOFT_RESET ); REG_OUTPUT( mmRBBM_PM_OVERRIDE1 );
+                    REG_OUTPUT( mmRBBM_PM_OVERRIDE2 ); REG_OUTPUT( mmGC_SYS_IDLE ); REG_OUTPUT( mmNQWAIT_UNTIL );
+                    REG_OUTPUT( mmRBBM_DEBUG_OUT ); REG_OUTPUT( mmRBBM_DEBUG_CNTL ); REG_OUTPUT( mmRBBM_DEBUG );
+                    REG_OUTPUT( mmRBBM_READ_ERROR ); REG_OUTPUT( mmRBBM_WAIT_IDLE_CLOCKS ); REG_OUTPUT( mmRBBM_INT_CNTL );
+                    REG_OUTPUT( mmRBBM_INT_STATUS ); REG_OUTPUT( mmRBBM_INT_ACK ); REG_OUTPUT( mmMASTER_INT_SIGNAL );
+                    REG_OUTPUT( mmRBBM_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_LO ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_HI );
+                    REG_OUTPUT( mmCP_RB_BASE ); REG_OUTPUT( mmCP_RB_CNTL ); REG_OUTPUT( mmCP_RB_RPTR_ADDR );
+                    REG_OUTPUT( mmCP_RB_RPTR ); REG_OUTPUT( mmCP_RB_RPTR_WR ); REG_OUTPUT( mmCP_RB_WPTR );
+                    REG_OUTPUT( mmCP_RB_WPTR_DELAY ); REG_OUTPUT( mmCP_RB_WPTR_BASE ); REG_OUTPUT( mmCP_IB1_BASE );
+                    REG_OUTPUT( mmCP_IB1_BUFSZ ); REG_OUTPUT( mmCP_IB2_BASE ); REG_OUTPUT( mmCP_IB2_BUFSZ );
+                    REG_OUTPUT( mmCP_ST_BASE ); REG_OUTPUT( mmCP_ST_BUFSZ ); REG_OUTPUT( mmCP_QUEUE_THRESHOLDS );
+                    REG_OUTPUT( mmCP_MEQ_THRESHOLDS ); REG_OUTPUT( mmCP_CSQ_AVAIL ); REG_OUTPUT( mmCP_STQ_AVAIL );
+                    REG_OUTPUT( mmCP_MEQ_AVAIL ); REG_OUTPUT( mmCP_CSQ_RB_STAT ); REG_OUTPUT( mmCP_CSQ_IB1_STAT );
+                    REG_OUTPUT( mmCP_CSQ_IB2_STAT ); REG_OUTPUT( mmCP_NON_PREFETCH_CNTRS ); REG_OUTPUT( mmCP_STQ_ST_STAT );
+                    REG_OUTPUT( mmCP_MEQ_STAT ); REG_OUTPUT( mmCP_MIU_TAG_STAT ); REG_OUTPUT( mmCP_CMD_INDEX );
+                    REG_OUTPUT( mmCP_CMD_DATA ); REG_OUTPUT( mmCP_ME_CNTL ); REG_OUTPUT( mmCP_ME_STATUS );
+                    REG_OUTPUT( mmCP_ME_RAM_WADDR ); REG_OUTPUT( mmCP_ME_RAM_RADDR ); REG_OUTPUT( mmCP_ME_RAM_DATA );
+                    REG_OUTPUT( mmCP_ME_RDADDR ); REG_OUTPUT( mmCP_DEBUG ); REG_OUTPUT( mmSCRATCH_REG0 );
+                    REG_OUTPUT( mmSCRATCH_REG1 ); REG_OUTPUT( mmSCRATCH_REG2 ); REG_OUTPUT( mmSCRATCH_REG3 );
+                    REG_OUTPUT( mmSCRATCH_REG4 ); REG_OUTPUT( mmSCRATCH_REG5 ); REG_OUTPUT( mmSCRATCH_REG6 );
+                    REG_OUTPUT( mmSCRATCH_REG7 );
+                    REG_OUTPUT( mmSCRATCH_UMSK ); REG_OUTPUT( mmSCRATCH_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_SRC );
+                    REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR_SWM );
+                    REG_OUTPUT( mmCP_ME_VS_EVENT_DATA_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_SRC ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR );
+                    REG_OUTPUT( mmCP_ME_PS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_DATA_SWM );
+                    REG_OUTPUT( mmCP_ME_CF_EVENT_SRC ); REG_OUTPUT( mmCP_ME_CF_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_CF_EVENT_DATA );
+                    REG_OUTPUT( mmCP_ME_NRT_ADDR ); REG_OUTPUT( mmCP_ME_NRT_DATA ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_SRC );
+                    REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_ADDR ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_DATA ); REG_OUTPUT( mmCP_INT_CNTL );
+                    REG_OUTPUT( mmCP_INT_STATUS ); REG_OUTPUT( mmCP_INT_ACK ); REG_OUTPUT( mmCP_PFP_UCODE_ADDR );
+                    REG_OUTPUT( mmCP_PFP_UCODE_DATA ); REG_OUTPUT( mmCP_PERFMON_CNTL ); REG_OUTPUT( mmCP_PERFCOUNTER_SELECT );
+                    REG_OUTPUT( mmCP_PERFCOUNTER_LO ); REG_OUTPUT( mmCP_PERFCOUNTER_HI ); REG_OUTPUT( mmCP_BIN_MASK_LO );
+                    REG_OUTPUT( mmCP_BIN_MASK_HI ); REG_OUTPUT( mmCP_BIN_SELECT_LO ); REG_OUTPUT( mmCP_BIN_SELECT_HI );
+                    REG_OUTPUT( mmCP_NV_FLAGS_0 ); REG_OUTPUT( mmCP_NV_FLAGS_1 ); REG_OUTPUT( mmCP_NV_FLAGS_2 );
+                    REG_OUTPUT( mmCP_NV_FLAGS_3 ); REG_OUTPUT( mmCP_STATE_DEBUG_INDEX ); REG_OUTPUT( mmCP_STATE_DEBUG_DATA );
+                    REG_OUTPUT( mmCP_PROG_COUNTER ); REG_OUTPUT( mmCP_STAT ); REG_OUTPUT( mmBIOS_0_SCRATCH );
+                    REG_OUTPUT( mmBIOS_1_SCRATCH ); REG_OUTPUT( mmBIOS_2_SCRATCH ); REG_OUTPUT( mmBIOS_3_SCRATCH );
+                    REG_OUTPUT( mmBIOS_4_SCRATCH ); REG_OUTPUT( mmBIOS_5_SCRATCH ); REG_OUTPUT( mmBIOS_6_SCRATCH );
+                    REG_OUTPUT( mmBIOS_7_SCRATCH ); REG_OUTPUT( mmBIOS_8_SCRATCH ); REG_OUTPUT( mmBIOS_9_SCRATCH );
+                    REG_OUTPUT( mmBIOS_10_SCRATCH ); REG_OUTPUT( mmBIOS_11_SCRATCH ); REG_OUTPUT( mmBIOS_12_SCRATCH );
+                    REG_OUTPUT( mmBIOS_13_SCRATCH ); REG_OUTPUT( mmBIOS_14_SCRATCH ); REG_OUTPUT( mmBIOS_15_SCRATCH );
+                    REG_OUTPUT( mmCOHER_SIZE_PM4 ); REG_OUTPUT( mmCOHER_BASE_PM4 ); REG_OUTPUT( mmCOHER_STATUS_PM4 );
+                    REG_OUTPUT( mmCOHER_SIZE_HOST ); REG_OUTPUT( mmCOHER_BASE_HOST ); REG_OUTPUT( mmCOHER_STATUS_HOST );
+                    REG_OUTPUT( mmCOHER_DEST_BASE_0 ); REG_OUTPUT( mmCOHER_DEST_BASE_1 ); REG_OUTPUT( mmCOHER_DEST_BASE_2 );
+                    REG_OUTPUT( mmCOHER_DEST_BASE_3 ); REG_OUTPUT( mmCOHER_DEST_BASE_4 ); REG_OUTPUT( mmCOHER_DEST_BASE_5 );
+                    REG_OUTPUT( mmCOHER_DEST_BASE_6 ); REG_OUTPUT( mmCOHER_DEST_BASE_7 ); REG_OUTPUT( mmRB_SURFACE_INFO );
+                    REG_OUTPUT( mmRB_COLOR_INFO ); REG_OUTPUT( mmRB_DEPTH_INFO ); REG_OUTPUT( mmRB_STENCILREFMASK );
+                    REG_OUTPUT( mmRB_ALPHA_REF ); REG_OUTPUT( mmRB_COLOR_MASK ); REG_OUTPUT( mmRB_BLEND_RED );
+                    REG_OUTPUT( mmRB_BLEND_GREEN ); REG_OUTPUT( mmRB_BLEND_BLUE ); REG_OUTPUT( mmRB_BLEND_ALPHA );
+                    REG_OUTPUT( mmRB_FOG_COLOR ); REG_OUTPUT( mmRB_STENCILREFMASK_BF ); REG_OUTPUT( mmRB_DEPTHCONTROL );
+                    REG_OUTPUT( mmRB_BLENDCONTROL ); REG_OUTPUT( mmRB_COLORCONTROL ); REG_OUTPUT( mmRB_MODECONTROL );
+                    REG_OUTPUT( mmRB_COLOR_DEST_MASK ); REG_OUTPUT( mmRB_COPY_CONTROL ); REG_OUTPUT( mmRB_COPY_DEST_BASE );
+                    REG_OUTPUT( mmRB_COPY_DEST_PITCH ); REG_OUTPUT( mmRB_COPY_DEST_INFO ); REG_OUTPUT( mmRB_COPY_DEST_PIXEL_OFFSET );
+                    REG_OUTPUT( mmRB_DEPTH_CLEAR ); REG_OUTPUT( mmRB_SAMPLE_COUNT_CTL ); REG_OUTPUT( mmRB_SAMPLE_COUNT_ADDR );
+                    REG_OUTPUT( mmRB_BC_CONTROL ); REG_OUTPUT( mmRB_EDRAM_INFO ); REG_OUTPUT( mmRB_CRC_RD_PORT );
+                    REG_OUTPUT( mmRB_CRC_CONTROL ); REG_OUTPUT( mmRB_CRC_MASK ); REG_OUTPUT( mmRB_PERFCOUNTER0_SELECT );
+                    REG_OUTPUT( mmRB_PERFCOUNTER0_LOW ); REG_OUTPUT( mmRB_PERFCOUNTER0_HI ); REG_OUTPUT( mmRB_TOTAL_SAMPLES );
+                    REG_OUTPUT( mmRB_ZPASS_SAMPLES ); REG_OUTPUT( mmRB_ZFAIL_SAMPLES ); REG_OUTPUT( mmRB_SFAIL_SAMPLES );
+                    REG_OUTPUT( mmRB_DEBUG_0 ); REG_OUTPUT( mmRB_DEBUG_1 ); REG_OUTPUT( mmRB_DEBUG_2 );
+                    REG_OUTPUT( mmRB_DEBUG_3 ); REG_OUTPUT( mmRB_DEBUG_4 ); REG_OUTPUT( mmRB_FLAG_CONTROL );
+                    REG_OUTPUT( mmRB_BC_SPARES ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_ENUMS ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_MOREENUMS );
+
+                    default:
+                        b += sprintf( b, "%s", "UNKNOWN REGISTER OFFSET" );
+                    break;
+                }
+                // Handle string after %R
+                kos_memcpy( b, p1+2, p2-(p1+2) );
+                b += (unsigned int)p2-(unsigned int)(p1+2);
+                *b = '\0';
+            }
+            break;
+
+
+            default:
+            {
+                int val = va_arg( arguments, int );
+                // Standard format. Use vsprintf.
+                b += sprintf( b, buffer2, val );
+            }
+            break;
+        }
+        
+
+        c = p2;
+    }
+
+    // Add this string to all outputs
+    output = outputs;
+
+    while( output != NULL )
+    {
+        // Filter according to the flags
+        if( ( output->flags & log_flags ) == log_flags )
+        {
+            // Passed the filter. Now commit this message.
+            switch( output->type )
+            {
+                case KGSL_OUTPUT_TYPE_MEMBUF:
+                    // TODO
+                break;
+
+                case KGSL_OUTPUT_TYPE_STDOUT:
+                    // Write timestamp if enabled
+                    if( output->flags & KGSL_LOG_TIMESTAMP )
+                        printf( "[Timestamp: %d] ", kos_timestamp() );
+                    // Write process id if enabled
+                    if( output->flags & KGSL_LOG_PROCESS_ID )
+                        printf( "[Process ID: %d] ", kos_process_getid() );
+                    // Write thread id if enabled
+                    if( output->flags & KGSL_LOG_THREAD_ID )
+                        printf( "[Thread ID: %d] ", kos_thread_getid() );
+
+                    // Write the message
+                    printf( buffer );
+                break;
+                
+                case KGSL_OUTPUT_TYPE_FILE:
+                    // Write timestamp if enabled
+                    if( output->flags & KGSL_LOG_TIMESTAMP )
+                        kos_fprintf( output->file, "[Timestamp: %d] ", kos_timestamp() );
+                    // Write process id if enabled
+                    if( output->flags & KGSL_LOG_PROCESS_ID )
+                        kos_fprintf( output->file, "[Process ID: %d] ", kos_process_getid() );
+                    // Write thread id if enabled
+                    if( output->flags & KGSL_LOG_THREAD_ID )
+                        kos_fprintf( output->file, "[Thread ID: %d] ", kos_thread_getid() );
+
+                    // Write the message
+                    kos_fprintf( output->file, buffer );
+                break;
+            }
+        }
+            
+        output = output->next;
+    }
+
+    va_end( arguments );
+
+    kos_mutex_unlock( log_mutex );
+
+    return GSL_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+#endif
diff --git a/drivers/mxc/amd-gpu/common/gsl_memmgr.c b/drivers/mxc/amd-gpu/common/gsl_memmgr.c
new file mode 100644
index 00000000000..75f250ae59b
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_memmgr.c
@@ -0,0 +1,949 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+#include "gsl_hal.h"
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENAPRIV_SIGNATURE_MASK         0x0000FFFF
+#define GSL_MEMARENAPRIV_APERTUREID_MASK        0xF0000000
+#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK    0x0F000000
+
+#define GSL_MEMARENAPRIV_SIGNATURE_SHIFT        0
+#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT   24
+#define GSL_MEMARENAPRIV_APERTUREID_SHIFT       28
+
+#define GSL_MEMARENA_INSTANCE_SIGNATURE         0x0000CAFE
+
+#ifdef GSL_STATS_MEM
+#define GSL_MEMARENA_STATS(x)   x
+#else
+#define GSL_MEMARENA_STATS(x)
+#endif // GSL_STATS_MEM
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENA_LOCK()                 kos_mutex_lock(memarena->mutex)
+#define GSL_MEMARENA_UNLOCK()               kos_mutex_unlock(memarena->mutex)
+
+#define GSL_MEMARENA_SET_SIGNATURE          (memarena->priv |= ((GSL_MEMARENA_INSTANCE_SIGNATURE << GSL_MEMARENAPRIV_SIGNATURE_SHIFT) & GSL_MEMARENAPRIV_SIGNATURE_MASK))
+#define GSL_MEMARENA_SET_MMU_VIRTUALIZED    (memarena->priv |= ((mmu_virtualized << GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT) & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK))
+#define GSL_MEMARENA_SET_ID                 (memarena->priv |= ((aperture_id << GSL_MEMARENAPRIV_APERTUREID_SHIFT) & GSL_MEMARENAPRIV_APERTUREID_MASK))
+
+#define GSL_MEMARENA_GET_SIGNATURE          ((memarena->priv & GSL_MEMARENAPRIV_SIGNATURE_MASK)   >> GSL_MEMARENAPRIV_SIGNATURE_SHIFT)
+#define GSL_MEMARENA_IS_MMU_VIRTUALIZED     ((memarena->priv & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK) >> GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT)
+#define GSL_MEMARENA_GET_ID                 ((memarena->priv & GSL_MEMARENAPRIV_APERTUREID_MASK)  >> GSL_MEMARENAPRIV_APERTUREID_SHIFT)
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  validate
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENA_VALIDATE(memarena)                                 \
+    KOS_ASSERT(memarena);                                               \
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)  \
+    {                                                                   \
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR,   \
+                        "ERROR: Memarena validation failed.\n" );       \
+        return (GSL_FAILURE);                                           \
+    }
+
+//////////////////////////////////////////////////////////////////////////////
+//  block alignment shift count
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE unsigned int
+gsl_memarena_alignmentshift(gsl_flags_t flags)
+{
+    int alignshift = ((flags & GSL_MEMFLAGS_ALIGN_MASK) >> GSL_MEMFLAGS_ALIGN_SHIFT);
+    if (alignshift == 0)
+        alignshift = 5; //  32 bytes is the minimum alignment boundary
+    return (alignshift);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  address alignment
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE unsigned int
+gsl_memarena_alignaddr(unsigned int address, int shift)
+{
+    //
+    //  the value of the returned address is guaranteed to be an even multiple
+    //  of the block alignment shift specified.
+    //
+    unsigned int alignedbaseaddr = ((address) >> shift) << shift;
+    if (alignedbaseaddr < address)
+    {
+        alignedbaseaddr += (1 << shift);
+    }
+    return (alignedbaseaddr);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//                         memory management API
+//////////////////////////////////////////////////////////////////////////////
+
+OSINLINE memblk_t*
+kgsl_memarena_getmemblknode(gsl_memarena_t *memarena)
+{
+#ifdef GSL_MEMARENA_NODE_POOL_ENABLED
+    gsl_nodepool_t  *nodepool    = memarena->nodepool;
+    memblk_t        *memblk      = NULL;
+    int             allocnewpool = 1;
+    int             i;
+
+    if (nodepool)
+    {
+        // walk through list of existing pools
+        for ( ; ; )
+        {
+            // if there is a pool with a free memblk node
+            if (nodepool->priv != (1 << GSL_MEMARENA_NODE_POOL_MAX)-1)
+            {
+                // get index of the first free memblk node
+                for (i = 0; i < GSL_MEMARENA_NODE_POOL_MAX; i++)
+                {
+                    if (((nodepool->priv >> i) & 0x1) == 0)
+                    {
+                        break;
+                    }
+                }
+
+                // mark memblk node as used
+                nodepool->priv |= 1 << i;
+
+                memblk                = &nodepool->memblk[i];
+                memblk->nodepoolindex = i;
+                memblk->blkaddr       = 0;
+                memblk->blksize       = 0;
+
+                allocnewpool = 0;
+
+                break;
+            }
+            else        
+            {
+                nodepool = nodepool->next;
+
+                if (nodepool == memarena->nodepool)
+                {
+                    // no free memblk node found
+                    break;
+                }
+            }
+        }
+    }
+
+    // if no existing pool has a free memblk node
+    if (allocnewpool)
+    {
+        // alloc new pool of memblk nodes
+        nodepool = ((gsl_nodepool_t *)kos_malloc(sizeof(gsl_nodepool_t)));
+        if (nodepool)
+        {
+            kos_memset(nodepool, 0, sizeof(gsl_nodepool_t));
+
+            if (memarena->nodepool)
+            {
+                nodepool->next                 = memarena->nodepool->next;
+                nodepool->prev                 = memarena->nodepool;
+                memarena->nodepool->next->prev = nodepool;
+                memarena->nodepool->next       = nodepool;
+            }
+            else
+            {
+                nodepool->next = nodepool;
+                nodepool->prev = nodepool;
+            }
+
+            // reposition pool head
+            memarena->nodepool = nodepool;
+
+            // mark memblk node as used
+            nodepool->priv       |= 0x1;
+
+            memblk                = &nodepool->memblk[0];
+            memblk->nodepoolindex = 0;
+        }
+    }
+
+    KOS_ASSERT(memblk);
+
+    return (memblk);
+#else
+    // unreferenced formal parameter
+    (void) memarena;
+
+    return ((memblk_t *)kos_malloc(sizeof(memblk_t)));
+#endif // GSL_MEMARENA_NODE_POOL_ENABLED
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_memarena_releasememblknode(gsl_memarena_t *memarena, memblk_t *memblk)
+{
+#ifdef GSL_MEMARENA_NODE_POOL_ENABLED
+    gsl_nodepool_t *nodepool = memarena->nodepool;
+
+    KOS_ASSERT(memblk);
+    KOS_ASSERT(nodepool);
+
+    // locate pool to which this memblk node belongs
+    while (((unsigned int) memblk) < ((unsigned int) nodepool) || 
+           ((unsigned int) memblk) > ((unsigned int) nodepool) + sizeof(gsl_nodepool_t))
+    {
+        nodepool = nodepool->prev;
+
+        KOS_ASSERT(nodepool != memarena->nodepool);
+    }
+
+    // mark memblk node as unused
+    nodepool->priv &= ~(1 << memblk->nodepoolindex);
+
+    // free pool when all its memblk nodes are unused
+    if (nodepool->priv == 0)
+    {
+        if (nodepool != nodepool->prev)
+        {
+            // reposition pool head
+            if (nodepool == memarena->nodepool)
+            {
+                memarena->nodepool = nodepool->prev;
+            }
+
+            nodepool->prev->next = nodepool->next;
+            nodepool->next->prev = nodepool->prev;
+        }
+        else
+        {
+            memarena->nodepool = NULL;
+        }
+
+        kos_free((void *)nodepool);
+    }
+    else
+    {
+        // leave pool head in last pool a memblk node was released
+        memarena->nodepool = nodepool;
+    }
+#else
+    // unreferenced formal parameter
+    (void) memarena;
+
+    kos_free((void *)memblk);
+#endif // GSL_MEMARENA_NODE_POOL_ENABLED
+}
+
+//----------------------------------------------------------------------------
+
+gsl_memarena_t*
+kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes)
+{
+    static int      count = 0;
+    char            name[100], id_str[2];
+    int             len;
+    gsl_memarena_t  *memarena;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_memarena_t* kgsl_memarena_create(int aperture_id=%d, gpuaddr_t gpubaseaddr=0x%08x, int sizebytes=%d)\n", aperture_id, gpubaseaddr, sizebytes );
+
+    memarena = (gsl_memarena_t *)kos_malloc(sizeof(gsl_memarena_t));
+
+    if (!memarena) 
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR,
+                        "ERROR: Memarena allocation failed.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "<-- kgsl_memarena_create. Return value: 0x%08x\n", NULL );
+        return (NULL);
+    }
+
+    kos_memset(memarena, 0, sizeof(gsl_memarena_t));
+
+    GSL_MEMARENA_SET_SIGNATURE;
+    GSL_MEMARENA_SET_MMU_VIRTUALIZED;
+    GSL_MEMARENA_SET_ID;
+
+    // define unique mutex for each memory arena instance
+    id_str[0] = (char) (count + '0');
+    id_str[1] = '\0';
+    kos_strcpy(name, "GSL_memory_arena_");
+    len = kos_strlen(name);
+    kos_strcpy(&name[len], id_str);
+
+    memarena->mutex = kos_mutex_create(name);
+
+    // set up the memory arena
+    memarena->hostbaseaddr = hostbaseaddr;
+    memarena->gpubaseaddr  = gpubaseaddr;
+    memarena->sizebytes    = sizebytes;
+
+    // allocate a memory block in free list which represents all memory in arena
+    memarena->freelist.head          = kgsl_memarena_getmemblknode(memarena);
+    memarena->freelist.head->blkaddr = 0;
+    memarena->freelist.head->blksize = memarena->sizebytes;
+    memarena->freelist.head->next    = memarena->freelist.head;
+    memarena->freelist.head->prev    = memarena->freelist.head;
+    memarena->freelist.allocrover    = memarena->freelist.head;
+    memarena->freelist.freerover     = memarena->freelist.head;
+
+    count++;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_create. Return value: 0x%08x\n", memarena );
+
+    return (memarena);
+}
+
+//----------------------------------------------------------------------------
+
+int         
+kgsl_memarena_destroy(gsl_memarena_t *memarena)
+{
+    int       status = GSL_SUCCESS;
+    memblk_t  *p, *next;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_destroy(gsl_memarena_t *memarena=0x%08x)\n", memarena );
+
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    GSL_MEMARENA_LOCK();
+
+#ifdef _DEBUG
+    // memory leak check
+    if (memarena->freelist.head->blksize != memarena->sizebytes)
+    {
+        if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM)
+        {
+            // external memory leak detected
+            kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL,
+                            "ERROR: External memory leak detected.\n" );
+            return (GSL_FAILURE);
+        }
+    }
+#endif // _DEBUG
+
+    p = memarena->freelist.head;
+    do
+    {
+        next = p->next;
+        kgsl_memarena_releasememblknode(memarena, p);
+        p = next;
+    } while (p != memarena->freelist.head);
+
+    GSL_MEMARENA_UNLOCK();
+
+    if (memarena->mutex)
+    {
+        kos_mutex_free(memarena->mutex);
+    }
+
+    kos_free((void *)memarena);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_destroy. Return value: %B\n", GSL_SUCCESS );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_memarena_isvirtualized(gsl_memarena_t *memarena)
+{
+    // mmu virtualization enabled
+    return (GSL_MEMARENA_IS_MMU_VIRTUALIZED);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_memarena_checkconsistency(gsl_memarena_t *memarena)
+{
+    memblk_t *p;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_checkconsistency(gsl_memarena_t *memarena=0x%08x)\n", memarena );
+
+    // go through list of free blocks and make sure there are no detectable errors
+
+    p = memarena->freelist.head;
+    do
+    {
+        if (p->next->blkaddr != memarena->freelist.head->blkaddr)
+        {
+            if (p->prev->next->blkaddr  != p->blkaddr || 
+                p->next->prev->blkaddr  != p->blkaddr ||
+                p->blkaddr + p->blksize >= p->next->blkaddr)
+            {
+                KOS_ASSERT(0);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+        }
+        p = p->next;
+
+    } while (p != memarena->freelist.head);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int             
+kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats)
+{
+#ifdef GSL_STATS_MEM
+    KOS_ASSERT(stats);
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    kos_memcpy(stats, &memarena->stats, sizeof(gsl_memarena_stats_t));
+    
+    return (GSL_SUCCESS);
+#else
+    // unreferenced formal parameters
+    (void) memarena;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_MEM
+}
+
+//----------------------------------------------------------------------------
+
+int         
+kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena, int bytesneeded)
+{
+    memblk_t  *p;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena=0x%08x, int bytesneeded=%d)\n", memarena, bytesneeded );
+
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    if (bytesneeded < 1)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal number of bytes needed.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_MEMARENA_LOCK();
+
+    p = memarena->freelist.head;
+    do
+    {
+        if (p->blksize >= (unsigned int)bytesneeded)
+        {
+            kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_SUCCESS );
+            return (GSL_SUCCESS);
+        }
+
+        p = p->next;
+    } while (p != memarena->freelist.head);
+
+    GSL_MEMARENA_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE );
+
+    return (GSL_FAILURE);
+}
+
+//----------------------------------------------------------------------------
+
+int 
+kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc)
+{
+    int           result = GSL_FAILURE_OUTOFMEM;
+    memblk_t      *ptrfree, *ptrlast, *p;
+    unsigned int  blksize;
+    unsigned int  baseaddr, alignedbaseaddr, alignfragment;
+    int           freeblk, alignmentshift;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_alloc(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x, int size=%d, gsl_memdesc_t *memdesc=%M)\n", memarena, flags, size, memdesc );
+
+    GSL_MEMARENA_VALIDATE(memarena);
+
+    if (size <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid size for memory allocation.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    //
+    // go through the list of free blocks.  check to find block which can satisfy the alloc request
+    //
+    // if no block can satisfy the alloc request this implies that the memory is too fragmented
+    // and the requestor needs to free up other memory blocks and re-request the allocation
+    //
+    // if we do find a block that can satisfy the alloc request then reduce the size of free block
+    // by blksize and return the address after allocating the memory.  if the free block size becomes
+    // 0 then remove this node from the free list
+    //
+    // there would be no node on the free list if all available memory were to be allocated.  
+    // handling an empty list would require executing error checking code in the main branch which 
+    // is not desired.  instead, the free list will have at least one node at all times. This node 
+    // could have a block size of zero
+    //
+    // we use a next fit allocation mechanism that uses a roving pointer on a circular free block list. 
+    // the pointer is advanced along the chain when searching for a fit. Thus each allocation begins
+    // looking where the previous one finished. 
+    //
+
+    // when allocating from external memory aperture, round up size of requested block to multiple of page size if needed
+    if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM)
+    {
+        if ((flags & GSL_MEMFLAGS_FORCEPAGESIZE) || GSL_MEMARENA_IS_MMU_VIRTUALIZED)
+        {
+            if (size & (GSL_PAGESIZE-1))
+            {
+                size = ((size >> GSL_PAGESIZE_SHIFT) + 1) << GSL_PAGESIZE_SHIFT;
+            }
+        }
+    }
+
+    // determine shift count for alignment requested
+    alignmentshift = gsl_memarena_alignmentshift(flags);
+
+    // adjust size of requested block to include alignment
+    blksize = (unsigned int)((size + ((1 << alignmentshift) - 1)) >> alignmentshift) << alignmentshift;
+
+    GSL_MEMARENA_LOCK();
+
+    // check consistency, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena));
+
+    ptrfree = memarena->freelist.allocrover;
+    ptrlast = memarena->freelist.head->prev;
+    freeblk = 0;
+
+    do
+    { 
+        // align base address
+        baseaddr = ptrfree->blkaddr + memarena->gpubaseaddr;
+        alignedbaseaddr = gsl_memarena_alignaddr(baseaddr, alignmentshift);
+       
+        alignfragment = alignedbaseaddr - baseaddr;
+
+        if (ptrfree->blksize >= blksize + alignfragment)
+        {
+            result  = GSL_SUCCESS;
+            freeblk = 1;
+
+            memdesc->gpuaddr = alignedbaseaddr;
+            memdesc->hostptr = kgsl_memarena_gethostptr(memarena, memdesc->gpuaddr);
+            memdesc->size    = blksize;
+
+            if (alignfragment > 0)
+            {
+                // insert new node to handle newly created (small) fragment
+                p = kgsl_memarena_getmemblknode(memarena);
+                p->blkaddr = ptrfree->blkaddr;
+                p->blksize = alignfragment;
+
+                p->next = ptrfree;
+                p->prev = ptrfree->prev;
+                ptrfree->prev->next = p;
+                ptrfree->prev       = p;
+
+                if (ptrfree == memarena->freelist.head)
+                {
+                    memarena->freelist.head = p;
+                }
+            }
+
+            ptrfree->blkaddr += alignfragment + blksize;
+            ptrfree->blksize -= alignfragment + blksize;
+
+            memarena->freelist.allocrover = ptrfree;
+
+            if (ptrfree->blksize == 0 && ptrfree != ptrlast)
+            {
+                ptrfree->prev->next = ptrfree->next;
+                ptrfree->next->prev = ptrfree->prev;
+                if (ptrfree == memarena->freelist.head)
+                {
+                    memarena->freelist.head = ptrfree->next;
+                }
+                if (ptrfree == memarena->freelist.allocrover)
+                {
+                    memarena->freelist.allocrover = ptrfree->next;
+                }
+                if (ptrfree == memarena->freelist.freerover)
+                {
+                    memarena->freelist.freerover = ptrfree->prev;
+                }
+                p       = ptrfree;
+                ptrfree = ptrfree->prev;
+                kgsl_memarena_releasememblknode(memarena, p);
+            }
+        }
+
+        ptrfree = ptrfree->next;
+
+    } while (!freeblk && ptrfree != memarena->freelist.allocrover);
+
+    GSL_MEMARENA_UNLOCK();
+
+    if (result == GSL_SUCCESS)
+    {
+        GSL_MEMARENA_STATS(
+        {   
+            int i = 0;
+            while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i))
+            {
+                i++;
+            }
+            i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i;
+            memarena->stats.allocs_pagedistribution[i]++;
+        });
+
+        GSL_MEMARENA_STATS(memarena->stats.allocs_success++);
+    }
+    else
+    {
+        GSL_MEMARENA_STATS(memarena->stats.allocs_fail++);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", result );
+        
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc)
+{
+    //
+    // request to free a malloc'ed block from the memory arena
+    // add this block to the free list
+    // adding a block to the free list requires the following:
+    // going through the list of free blocks to decide where to add this free block (based on address)
+    // coalesce free blocks
+    //
+    memblk_t      *ptrfree, *ptrend, *p;
+    int           mallocfreeblk, clockwise;
+    unsigned int  addrtofree;
+    
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_memarena_free(gsl_memarena_t *memarena=0x%08x, gsl_memdesc_t *memdesc=%M)\n", memarena, memdesc );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" );
+        return;
+    }
+
+    // check size of malloc'ed block 
+    if (memdesc->size <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal size for the memdesc.\n" );
+        KOS_ASSERT(0);
+
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" );
+        return;
+    }
+
+    // check address range
+    KOS_ASSERT( memarena->gpubaseaddr <= memdesc->gpuaddr);
+    KOS_ASSERT((memarena->gpubaseaddr + memarena->sizebytes) >= memdesc->gpuaddr + memdesc->size);
+
+    GSL_MEMARENA_LOCK();
+
+    // check consistency of memory map, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena));
+
+    addrtofree    = memdesc->gpuaddr - memarena->gpubaseaddr;
+    mallocfreeblk = 1;
+
+    if (addrtofree < memarena->freelist.head->blkaddr)
+    {
+        // add node to head of free list
+
+        if (addrtofree + memdesc->size == memarena->freelist.head->blkaddr)
+        {
+            memarena->freelist.head->blkaddr  = addrtofree;
+            memarena->freelist.head->blksize += memdesc->size;
+
+            mallocfreeblk = 0;
+        }
+
+        ptrfree = memarena->freelist.head->prev;
+    }
+    else if (addrtofree >= memarena->freelist.head->prev->blkaddr)
+    {
+        // add node to tail of free list
+
+        ptrfree = memarena->freelist.head->prev;
+
+        if (ptrfree->blkaddr + ptrfree->blksize == addrtofree)
+        {
+            ptrfree->blksize += memdesc->size;
+
+            mallocfreeblk = 0;
+        }
+    }
+    else
+    {
+        // determine range of free list nodes to traverse and orientation in which to traverse them
+        // keep this code segment unrolled for performance reasons!
+        if (addrtofree > memarena->freelist.freerover->blkaddr)
+        {
+            if (addrtofree - memarena->freelist.freerover->blkaddr < memarena->freelist.head->prev->blkaddr - addrtofree)
+            {
+                ptrfree   = memarena->freelist.freerover;       // rover
+                ptrend    = memarena->freelist.head->prev;      // tail
+                clockwise = 1;
+            }
+            else
+            {
+                ptrfree   = memarena->freelist.head->prev->prev; // tail
+                ptrend    = memarena->freelist.freerover->prev;  // rover
+                clockwise = 0;
+            }
+        }
+        else
+        {
+            if (addrtofree - memarena->freelist.head->blkaddr < memarena->freelist.freerover->blkaddr - addrtofree)
+            {
+                ptrfree   = memarena->freelist.head;            // head
+                ptrend    = memarena->freelist.freerover;       // rover
+                clockwise = 1;
+            }
+            else
+            {
+                ptrfree   = memarena->freelist.freerover->prev; // rover
+                ptrend    = memarena->freelist.head->prev;      // head
+                clockwise = 0;
+            }
+        }
+
+        // traverse the nodes
+        do
+        {
+            if ((addrtofree >= ptrfree->blkaddr + ptrfree->blksize) && 
+                (addrtofree + memdesc->size <= ptrfree->next->blkaddr))
+            {
+                if (addrtofree == ptrfree->blkaddr + ptrfree->blksize)
+                {
+                    memblk_t  *next;
+
+                    ptrfree->blksize += memdesc->size;
+                    next              = ptrfree->next;
+
+                    if (ptrfree->blkaddr + ptrfree->blksize == next->blkaddr)
+                    {
+                        ptrfree->blksize += next->blksize;
+                        ptrfree->next     = next->next;
+                        next->next->prev  = ptrfree;
+
+                        if (next == memarena->freelist.allocrover)
+                        {
+                            memarena->freelist.allocrover = ptrfree;
+                        }
+
+                        kgsl_memarena_releasememblknode(memarena, next);
+                    }
+
+                    mallocfreeblk = 0;
+                }
+                else if (addrtofree + memdesc->size == ptrfree->next->blkaddr)
+                {
+                    ptrfree->next->blkaddr  = addrtofree;
+                    ptrfree->next->blksize += memdesc->size;
+
+                    mallocfreeblk  = 0;
+                }
+
+                break;
+            }
+
+            if (clockwise)
+            {
+                ptrfree = ptrfree->next;
+            }
+            else
+            {
+                ptrfree = ptrfree->prev;
+            }
+
+        } while (ptrfree != ptrend);
+    }
+
+    // this free block could not be coalesced, so create a new free block
+    // and add it to the free list in the memory arena
+    if (mallocfreeblk)
+    {
+        p = kgsl_memarena_getmemblknode(memarena);
+        p->blkaddr = addrtofree;
+        p->blksize = memdesc->size;
+
+        p->next             = ptrfree->next;
+        p->prev             = ptrfree;
+        ptrfree->next->prev = p;
+        ptrfree->next       = p;
+
+        if (p->blkaddr < memarena->freelist.head->blkaddr)
+        {
+            memarena->freelist.head = p;
+        }
+
+        memarena->freelist.freerover = p;
+    }
+    else
+    {
+        memarena->freelist.freerover = ptrfree;
+    }
+
+    GSL_MEMARENA_UNLOCK();
+
+    GSL_MEMARENA_STATS(
+    {   
+        int i = 0;
+        while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i))
+        {
+            i++;
+        }
+        i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i;
+        memarena->stats.frees_pagedistribution[i]++;
+    });
+
+    GSL_MEMARENA_STATS(memarena->stats.frees++);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+void *          
+kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr)
+{
+    //
+    // get the host mapped address for a hardware device address
+    //
+
+    void  *hostptr = NULL;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> void* kgsl_memarena_gethostptr(gsl_memarena_t *memarena=0x%08x, gpuaddr_t gpuaddr=0x%08x)\n", memarena, gpuaddr );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", NULL );
+        return (NULL);
+    }
+
+    // check address range
+    KOS_ASSERT(gpuaddr >= memarena->gpubaseaddr);
+    KOS_ASSERT(gpuaddr <  memarena->gpubaseaddr + memarena->sizebytes);
+
+    hostptr = (void *)((gpuaddr - memarena->gpubaseaddr) + memarena->hostbaseaddr);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", hostptr );
+
+    return (hostptr);
+}
+
+//----------------------------------------------------------------------------
+
+gpuaddr_t           
+kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr)
+{
+    //
+    // get the hardware device address for a host mapped address
+    //
+
+    gpuaddr_t  gpuaddr = 0;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena=0x%08x, void *hostptr=0x%08x)\n", memarena, hostptr );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", 0 );
+        return (0);
+    }
+
+    // check address range
+    KOS_ASSERT(hostptr >= (void *)memarena->hostbaseaddr);
+    KOS_ASSERT(hostptr <  (void *)(memarena->hostbaseaddr + memarena->sizebytes));
+    
+    gpuaddr = ((unsigned int)hostptr - memarena->hostbaseaddr) + memarena->gpubaseaddr;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", gpuaddr );
+
+    return (gpuaddr);
+}
+
+//----------------------------------------------------------------------------
+
+unsigned int    
+kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags)
+{
+    memblk_t      *ptrfree;
+    unsigned int  blocksize, largestblocksize = 0;
+    int           alignmentshift; 
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> unsigned int kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x)\n", memarena, flags );
+
+    KOS_ASSERT(memarena);
+    if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) 
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", 0 );
+        return (0);
+    }
+
+    // determine shift count for alignment requested
+    alignmentshift = gsl_memarena_alignmentshift(flags);
+
+    GSL_MEMARENA_LOCK();
+
+    ptrfree = memarena->freelist.head;
+
+    do
+    {
+        blocksize = ptrfree->blksize - (ptrfree->blkaddr - ((ptrfree->blkaddr >> alignmentshift) << alignmentshift));
+
+        if (blocksize > largestblocksize)
+        {
+            largestblocksize = blocksize;
+        }
+
+        ptrfree = ptrfree->next;
+
+    } while (ptrfree != memarena->freelist.head);
+
+    GSL_MEMARENA_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", largestblocksize );
+
+    return (largestblocksize);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_mmu.c b/drivers/mxc/amd-gpu/common/gsl_mmu.c
new file mode 100644
index 00000000000..810a058a515
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_mmu.c
@@ -0,0 +1,1084 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// ---------
+// pte debug
+// ---------
+
+typedef struct _gsl_pte_debug_t
+{
+    unsigned int    write     :1;
+    unsigned int    read      :1;
+    unsigned int    reserved  :10;
+    unsigned int    phyaddr   :20;
+} gsl_pte_debug_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_PT_ENTRY_SIZEBYTES              4
+#define GSL_PT_EXTRA_ENTRIES                16
+
+#define GSL_PT_PAGE_WRITE                   0x00000001
+#define GSL_PT_PAGE_READ                    0x00000002
+
+#define GSL_PT_PAGE_AP_MASK                 0x00000003
+#define GSL_PT_PAGE_ADDR_MASK               ~(GSL_PAGESIZE-1)
+
+#define GSL_MMUFLAGS_TLBFLUSH               0x80000000
+
+#define GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS   (sizeof(unsigned char) * 8)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// constants
+//////////////////////////////////////////////////////////////////////////////
+const unsigned int GSL_PT_PAGE_AP[4] = {(GSL_PT_PAGE_READ | GSL_PT_PAGE_WRITE), GSL_PT_PAGE_READ, GSL_PT_PAGE_WRITE, 0};
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_LOCKING_FINEGRAIN
+#define GSL_MMU_MUTEX_CREATE()              mmu->mutex = kos_mutex_create("gsl_mmu"); \
+                                            if (!mmu->mutex) {return (GSL_FAILURE);}
+#define GSL_MMU_LOCK()                      kos_mutex_lock(mmu->mutex)
+#define GSL_MMU_UNLOCK()                    kos_mutex_unlock(mmu->mutex)
+#define GSL_MMU_MUTEX_FREE()                kos_mutex_free(mmu->mutex); mmu->mutex = 0;
+#else
+#define GSL_MMU_MUTEX_CREATE()
+#define GSL_MMU_LOCK()
+#define GSL_MMU_UNLOCK()
+#define GSL_MMU_MUTEX_FREE()
+#endif
+
+#define GSL_PT_ENTRY_GET(va)                ((va - pagetable->va_base) >> GSL_PAGESIZE_SHIFT)
+#define GSL_PT_VIRT_GET(pte)                (pagetable->va_base + (pte * GSL_PAGESIZE))
+
+#define GSL_PT_MAP_APDEFAULT                GSL_PT_PAGE_AP[0]
+
+#define GSL_PT_MAP_GET(pte)                 *((unsigned int *)(((unsigned int)pagetable->base.hostptr) + ((pte) * GSL_PT_ENTRY_SIZEBYTES)))
+#define GSL_PT_MAP_GETADDR(pte)             (GSL_PT_MAP_GET(pte) & GSL_PT_PAGE_ADDR_MASK)
+
+#define GSL_PT_MAP_DEBUG(pte)               ((gsl_pte_debug_t*) &GSL_PT_MAP_GET(pte))
+
+#define GSL_PT_MAP_SETBITS(pte, bits)       (GSL_PT_MAP_GET(pte) |= (((unsigned int) bits) & GSL_PT_PAGE_AP_MASK))
+#define GSL_PT_MAP_SETADDR(pte, pageaddr)   (GSL_PT_MAP_GET(pte)  = (GSL_PT_MAP_GET(pte) & ~GSL_PT_PAGE_ADDR_MASK) | (((unsigned int) pageaddr) & GSL_PT_PAGE_ADDR_MASK))
+
+#define GSL_PT_MAP_RESET(pte)               (GSL_PT_MAP_GET(pte)  = 0)
+#define GSL_PT_MAP_RESETBITS(pte, bits)     (GSL_PT_MAP_GET(pte) &= ~(((unsigned int) bits) & GSL_PT_PAGE_AP_MASK))
+
+#define GSL_MMU_VIRT_TO_PAGE(va)            *((unsigned int *)(pagetable->base.gpuaddr + (GSL_PT_ENTRY_GET(va) * GSL_PT_ENTRY_SIZEBYTES)))
+#define GSL_MMU_VIRT_TO_PHYS(va)            ((GSL_MMU_VIRT_TO_PAGE(va) & GSL_PT_PAGE_ADDR_MASK) + (va & (GSL_PAGESIZE-1)))
+
+#define GSL_TLBFLUSH_FILTER_GET(superpte)       *((unsigned char *)(((unsigned int)mmu->tlbflushfilter.base) + (superpte / GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)))
+#define GSL_TLBFLUSH_FILTER_SETDIRTY(superpte)  (GSL_TLBFLUSH_FILTER_GET((superpte)) |= 1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS))
+#define GSL_TLBFLUSH_FILTER_ISDIRTY(superpte)   (GSL_TLBFLUSH_FILTER_GET((superpte)) & (1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)))
+#define GSL_TLBFLUSH_FILTER_RESET()             kos_memset(mmu->tlbflushfilter.base, 0, mmu->tlbflushfilter.size)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// process index in pagetable object table
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_mmu_getprocessindex(unsigned int pid, int *pindex)
+{
+    int status = GSL_SUCCESS;
+#ifdef GSL_MMU_PAGETABLE_PERPROCESS
+    if (kgsl_driver_getcallerprocessindex(pid, pindex) != GSL_SUCCESS)
+    {
+        status = GSL_FAILURE;
+    }
+#else
+    (void) pid;      // unreferenced formal parameter
+    *pindex = 0;
+#endif // GSL_MMU_PAGETABLE_PERPROCESS
+    return (status);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// pagetable object for current caller process
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE gsl_pagetable_t*
+kgsl_mmu_getpagetableobject(gsl_mmu_t *mmu, unsigned int pid)
+{
+    int pindex = 0;
+    if (kgsl_mmu_getprocessindex(pid, &pindex) == GSL_SUCCESS)
+    {
+        return (mmu->pagetable[pindex]);
+    }
+    else
+    {
+        return (NULL);
+    }
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  functions
+//////////////////////////////////////////////////////////////////////////////
+
+void
+kgsl_mh_intrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_mmu_t     *mmu = (gsl_mmu_t *) cookie;
+    unsigned int   devindex = mmu->device->id-1;        // device_id is 1 based
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_mh_ntrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie );
+
+    // error condition interrupt
+    if (id == gsl_cfg_mh_intr[devindex].AXI_READ_ERROR  ||
+        id == gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR ||
+        id == gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT)
+    {
+	printk(KERN_ERR "GPU: AXI Read/Write Error or MMU page fault\n");
+	schedule_work(&mmu->device->irq_err_work);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mh_intrcallback.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+static void
+kgsl_mmu_debug(gsl_mmu_t *mmu, gsl_mmu_debug_t *regs)
+{
+    unsigned int  devindex = mmu->device->id-1;         // device_id is 1 based
+
+    kos_memset(regs, 0, sizeof(gsl_mmu_debug_t));
+
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].CONFIG,     &regs->config);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_BASE,   &regs->mpu_base);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_END,    &regs->mpu_end);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].VA_RANGE,   &regs->va_range);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE,    &regs->pt_base);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PAGE_FAULT, &regs->page_fault);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, &regs->trans_error);
+    mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, &regs->invalidate);
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable)
+{
+    unsigned int     pte;
+    unsigned int     data;
+    gsl_pte_debug_t  *pte_debug;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable=0x%08x)\n", pagetable );
+
+    if (pagetable->last_superpte % GSL_PT_SUPER_PTE != 0)
+    {
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // go through page table and make sure there are no detectable errors
+    pte = 0;
+    while (pte < pagetable->max_entries)
+    {
+        pte_debug = GSL_PT_MAP_DEBUG(pte);
+
+        if (GSL_PT_MAP_GETADDR(pte) != 0)
+        {
+            // pte is in use
+
+            // access first couple bytes of a page
+            data = *((unsigned int *)GSL_PT_VIRT_GET(pte));
+        }
+
+        pte++;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_SUCCESS );
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu, unsigned int pid)
+{
+    gsl_deviceid_t   tmp_id;
+    gsl_device_t     *tmp_device;
+    int              pindex;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    if (kgsl_mmu_getprocessindex(pid, &pindex) != GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS );
+        return (GSL_FAILURE);
+    }
+
+    pagetable = mmu->pagetable[pindex];
+
+    // if pagetable object exists for current "current device mmu"/"current caller process" combination
+    if (pagetable)
+    {
+        // no more "device mmu"/"caller process" combinations attached to current pagetable object
+        if (pagetable->refcnt == 0)
+        {
+#ifdef _DEBUG
+            // memory leak check
+            if (pagetable->last_superpte != 0 || GSL_PT_MAP_GETADDR(pagetable->last_superpte))
+            {
+                /* many dumpx test cases forcefully exit, and thus trigger this assert. */
+                /* Because it is an annoyance for HW guys, it is disabled for dumpx */
+                if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX)
+                {
+                    KOS_ASSERT(0);
+                    return (GSL_FAILURE);
+                }
+            }
+#endif // _DEBUG
+
+            if (pagetable->base.gpuaddr)
+            {
+                kgsl_sharedmem_free0(&pagetable->base, GSL_CALLER_PROCESSID_GET());
+            }
+
+            kos_free(pagetable);
+
+            // clear pagetable object reference for all "device mmu"/"current caller process" combinations
+            for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+            {
+                tmp_device = &gsl_driver.device[tmp_id-1];
+
+                if (tmp_device->mmu.flags & GSL_FLAGS_STARTED)
+                {
+                    tmp_device->mmu.pagetable[pindex] = NULL;
+                }
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+gsl_pagetable_t*
+kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu, unsigned int pid)
+{
+    //
+    // create pagetable object for "current device mmu"/"current caller
+    // process" combination. If none exists, setup a new pagetable object.
+    //
+    int              status         = GSL_SUCCESS;
+    gsl_pagetable_t  *tmp_pagetable = NULL;
+    gsl_deviceid_t   tmp_id;
+    gsl_device_t     *tmp_device;
+    int              pindex;
+    gsl_flags_t      flags;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    status = kgsl_mmu_getprocessindex(pid, &pindex);
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL );
+        return (NULL);
+    }
+    // if pagetable object does not already exists for "current device mmu"/"current caller process" combination
+    if (!mmu->pagetable[pindex])
+    {
+        // then, check if pagetable object already exists for any "other device mmu"/"current caller process" combination
+        for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+        {
+            tmp_device = &gsl_driver.device[tmp_id-1];
+
+            if (tmp_device->mmu.flags & GSL_FLAGS_STARTED)
+            {
+                if (tmp_device->mmu.pagetable[pindex])
+                {
+                    tmp_pagetable = tmp_device->mmu.pagetable[pindex];
+                    break;
+                }
+            }
+        }
+
+        // pagetable object exists
+        if (tmp_pagetable)
+        {
+            KOS_ASSERT(tmp_pagetable->va_base  == mmu->va_base);
+            KOS_ASSERT(tmp_pagetable->va_range == mmu->va_range);
+
+            // set pagetable object reference
+            mmu->pagetable[pindex] = tmp_pagetable;
+        }
+        // create new pagetable object
+        else
+        {
+            mmu->pagetable[pindex] = (void *)kos_malloc(sizeof(gsl_pagetable_t));
+            if (!mmu->pagetable[pindex])
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate pagetable object.\n" );
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL );
+                return (NULL);
+            }
+
+            kos_memset(mmu->pagetable[pindex], 0, sizeof(gsl_pagetable_t));
+
+			mmu->pagetable[pindex]->pid           = pid;
+            mmu->pagetable[pindex]->refcnt        = 0;
+            mmu->pagetable[pindex]->va_base       = mmu->va_base;
+            mmu->pagetable[pindex]->va_range      = mmu->va_range;
+            mmu->pagetable[pindex]->last_superpte = 0;
+            mmu->pagetable[pindex]->max_entries   = (mmu->va_range >> GSL_PAGESIZE_SHIFT) + GSL_PT_EXTRA_ENTRIES;
+
+            // allocate page table memory
+            flags  = (GSL_MEMFLAGS_ALIGN4K | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST);
+            status = kgsl_sharedmem_alloc0(mmu->device->id, flags, mmu->pagetable[pindex]->max_entries * GSL_PT_ENTRY_SIZEBYTES, &mmu->pagetable[pindex]->base);
+
+            if (status == GSL_SUCCESS)
+            {
+                // reset page table entries
+                kgsl_sharedmem_set0(&mmu->pagetable[pindex]->base, 0, 0, mmu->pagetable[pindex]->base.size);
+
+                KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MMU_TBLADDR, mmu->pagetable[pindex]->base.gpuaddr, 0, mmu->pagetable[pindex]->base.size, "kgsl_mmu_init"));
+            }
+            else
+            {
+                kgsl_mmu_destroypagetableobject(mmu, pid);
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", mmu->pagetable[pindex] );
+
+    return (mmu->pagetable[pindex]);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid)
+{
+    //
+    // set device mmu to use current caller process's page table
+    //
+    int              status   = GSL_SUCCESS;
+    unsigned int     devindex = device->id-1;       // device_id is 1 based
+    gsl_mmu_t        *mmu     = &device->mmu;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_pagetable_t* kgsl_mmu_setpagetable(gsl_device_t *device=0x%08x)\n", device );
+
+    GSL_MMU_LOCK();
+
+    if (mmu->flags & GSL_FLAGS_STARTED)
+    {
+#ifdef GSL_MMU_PAGETABLE_PERPROCESS
+		// page table not current, then setup mmu to use new specified page table
+		if (mmu->hwpagetable->pid != pid)
+		{
+			gsl_pagetable_t  *pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+			if (pagetable)
+			{
+				mmu->hwpagetable = pagetable;
+
+				// flag tlb flush	
+				mmu->flags |= GSL_MMUFLAGS_TLBFLUSH;
+
+				status = mmu->device->ftbl.mmu_setpagetable(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE, pagetable->base.gpuaddr, pid);
+
+				GSL_MMU_STATS(mmu->stats.pt.switches++);
+			}
+			else
+			{
+				status = GSL_FAILURE;
+			}
+		}
+#endif // GSL_MMU_PAGETABLE_PERPROCESS
+
+        // if needed, invalidate device specific tlb
+		if ((mmu->flags & GSL_MMUFLAGS_TLBFLUSH) && status == GSL_SUCCESS)
+        {
+            mmu->flags &= ~GSL_MMUFLAGS_TLBFLUSH;
+
+            GSL_TLBFLUSH_FILTER_RESET();
+
+			status = mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, pid);
+
+			GSL_MMU_STATS(mmu->stats.tlbflushes++);
+		}
+	}
+
+    GSL_MMU_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_setpagetable. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_init(gsl_device_t *device)
+{
+    //
+    // intialize device mmu
+    //
+    // call this with the global lock held
+    //
+    int              status;
+    gsl_flags_t      flags;
+    gsl_pagetable_t  *pagetable;
+    unsigned int     devindex = device->id-1;       // device_id is 1 based
+    gsl_mmu_t        *mmu     = &device->mmu;
+#ifdef _DEBUG
+    gsl_mmu_debug_t  regs;
+#endif // _DEBUG
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_init(gsl_device_t *device=0x%08x)\n", device );
+
+    if (device->ftbl.mmu_tlbinvalidate == NULL || device->ftbl.mmu_setpagetable == NULL ||
+        !(device->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_INFO, "MMU already initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    // setup backward reference
+    mmu->device = device;
+
+    // disable MMU when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        mmu->config = 0x00000000;
+    }
+
+    // setup MMU and sub-client behavior
+    device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, mmu->config);
+
+    // enable axi interrupts
+    kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR, kgsl_mh_intrcallback, (void *) mmu);
+    kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR, kgsl_mh_intrcallback, (void *) mmu);
+    kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR);
+    kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR);
+
+    mmu->refcnt  = 0;
+    mmu->flags  |= GSL_FLAGS_INITIALIZED0;
+
+    // MMU enabled
+    if (mmu->config & 0x1)
+    {
+        // idle device
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+
+        // make sure aligned to pagesize
+        KOS_ASSERT((mmu->mpu_base & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0);
+        KOS_ASSERT(((mmu->mpu_base + mmu->mpu_range) & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0);
+
+        // define physical memory range accessible by the core
+        device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_BASE, mmu->mpu_base);
+        device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_END,  mmu->mpu_base + mmu->mpu_range);
+
+        // enable page fault interrupt
+        kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT, kgsl_mh_intrcallback, (void *) mmu);
+        kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT);
+
+        mmu->flags |= GSL_FLAGS_INITIALIZED;
+
+        // sub-client MMU lookups require address translation
+        if ((mmu->config & ~0x1) > 0)
+        {
+            GSL_MMU_MUTEX_CREATE();
+
+            // make sure virtual address range is a multiple of 64Kb
+            KOS_ASSERT((mmu->va_range & ((1 << 16)-1)) == 0);
+
+            // setup pagetable object
+            pagetable = kgsl_mmu_createpagetableobject(mmu, GSL_CALLER_PROCESSID_GET());
+            if (!pagetable)
+            {
+                kgsl_mmu_close(device);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+
+            mmu->hwpagetable = pagetable;
+
+            // create tlb flush filter to track dirty superPTE's -- one bit per superPTE
+            mmu->tlbflushfilter.size = (mmu->va_range / (GSL_PAGESIZE * GSL_PT_SUPER_PTE * 8)) + 1;
+            mmu->tlbflushfilter.base = (unsigned int *)kos_malloc(mmu->tlbflushfilter.size);
+            if (!mmu->tlbflushfilter.base)
+            {
+                kgsl_mmu_close(device);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+
+            GSL_TLBFLUSH_FILTER_RESET();
+
+            // set page table base
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].PT_BASE, mmu->hwpagetable->base.gpuaddr);
+
+            // define virtual address range
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].VA_RANGE, (mmu->hwpagetable->va_base | (mmu->hwpagetable->va_range >> 16)));
+
+            // allocate memory used for completing r/w operations that cannot be mapped by the MMU
+            flags  = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST);
+            status = kgsl_sharedmem_alloc0(device->id, flags, 32, &mmu->dummyspace);
+            if (status != GSL_SUCCESS)
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate dummy space memory.\n" );
+                kgsl_mmu_close(device);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", status );
+                return (status);
+            }
+
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, mmu->dummyspace.gpuaddr);
+
+            // call device specific tlb invalidate
+			device->ftbl.mmu_tlbinvalidate(device, gsl_cfg_mmu_reg[devindex].INVALIDATE, mmu->hwpagetable->pid);
+
+			GSL_MMU_STATS(mmu->stats.tlbflushes++);
+
+            mmu->flags |= GSL_FLAGS_STARTED;
+        }
+    }
+
+    KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_debug(&device->mmu, &regs));
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid)
+{
+    //
+    // map physical pages into the gpu page table
+    //
+    int              status = GSL_SUCCESS;
+    unsigned int     i, phyaddr, ap;
+    unsigned int     pte, ptefirst, ptelast, superpte;
+    int              flushtlb;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_map(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, gsl_scatterlist_t *scatterlist=%M, gsl_flags_t flags=%d, unsigned int pid=%d)\n",
+                    mmu, gpubaseaddr, scatterlist, flags, pid );
+
+    KOS_ASSERT(scatterlist);
+
+    if (scatterlist->num <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: num pages is too small.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // get gpu access permissions
+    ap = GSL_PT_PAGE_AP[((flags & GSL_MEMFLAGS_GPUAP_MASK) >> GSL_MEMFLAGS_GPUAP_SHIFT)];
+
+    GSL_MMU_LOCK();
+
+    pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+    if (!pagetable)
+    {
+        GSL_MMU_UNLOCK();
+        return (GSL_FAILURE);
+    }
+
+    // check consistency, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable));
+
+    ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr);
+    ptelast  = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (scatterlist->num-1)));
+    flushtlb = 0;
+
+    if (!GSL_PT_MAP_GETADDR(ptefirst))
+    {
+        // tlb needs to be flushed when the first and last pte are not at superpte boundaries
+        if ((ptefirst & (GSL_PT_SUPER_PTE-1)) != 0 || ((ptelast+1) & (GSL_PT_SUPER_PTE-1)) != 0)
+        {
+            flushtlb = 1;
+        }
+
+        // create page table entries
+        for (pte = ptefirst; pte <= ptelast; pte++)
+        {
+            if (scatterlist->contiguous)
+            {
+                phyaddr = scatterlist->pages[0] + ((pte-ptefirst) * GSL_PAGESIZE);
+            }
+            else
+            {
+                phyaddr = scatterlist->pages[pte-ptefirst];
+            }
+
+            GSL_PT_MAP_SETADDR(pte, phyaddr);
+            GSL_PT_MAP_SETBITS(pte, ap);
+
+            // tlb needs to be flushed when a dirty superPTE gets backed
+            if ((pte & (GSL_PT_SUPER_PTE-1)) == 0)
+            {
+                if (GSL_TLBFLUSH_FILTER_ISDIRTY(pte / GSL_PT_SUPER_PTE))
+                {
+                    flushtlb = 1;
+                }
+            }
+
+            KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte , *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_map"));
+        }
+
+        if (flushtlb)
+        {
+            // every device's tlb needs to be flushed because the current page table is shared among all devices
+            for (i = 0; i < GSL_DEVICE_MAX; i++)
+            {
+                if (gsl_driver.device[i].flags & GSL_FLAGS_INITIALIZED)
+                {
+                    gsl_driver.device[i].mmu.flags |= GSL_MMUFLAGS_TLBFLUSH;
+                }
+            }
+        }
+
+        // determine new last mapped superPTE 
+        superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1));
+        if (superpte > pagetable->last_superpte)
+        {
+            pagetable->last_superpte = superpte;
+        }
+
+		GSL_MMU_STATS(mmu->stats.pt.maps++);
+    }
+    else
+    {
+        // this should never happen
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" );
+        KOS_ASSERT(0);
+        status = GSL_FAILURE;
+    }
+
+    GSL_MMU_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_SUCCESS );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid)
+{
+    //
+    // remove mappings in the specified address range from the gpu page table
+    //
+    int              status = GSL_SUCCESS;
+    gsl_pagetable_t  *pagetable;
+    unsigned int     numpages;
+    unsigned int     pte, ptefirst, ptelast, superpte;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_mmu_unmap(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, int range=%d, unsigned int pid=%d)\n",
+                    mmu, gpubaseaddr, range, pid );
+
+    if (range <= 0)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    numpages = (range >> GSL_PAGESIZE_SHIFT);
+    if (range & (GSL_PAGESIZE-1))
+    {
+        numpages++;
+    }
+
+    GSL_MMU_LOCK();
+
+    pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+    if (!pagetable)
+    {
+        GSL_MMU_UNLOCK();
+        return (GSL_FAILURE);
+    }
+
+    // check consistency, debug only
+    KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable));
+
+    ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr);
+    ptelast  = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1)));
+
+    if (GSL_PT_MAP_GETADDR(ptefirst))
+    {
+        superpte = ptefirst - (ptefirst & (GSL_PT_SUPER_PTE-1));
+        GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE);
+
+        // remove page table entries
+        for (pte = ptefirst; pte <= ptelast; pte++)
+        {
+            GSL_PT_MAP_RESET(pte);
+
+            superpte = pte - (pte & (GSL_PT_SUPER_PTE-1));
+            if (pte == superpte)
+            {
+                GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE);
+            }
+
+			KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte, *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_unmap, reset superPTE"));
+        }
+
+        // determine new last mapped superPTE 
+        superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1));
+        if (superpte == pagetable->last_superpte && pagetable->last_superpte >= GSL_PT_SUPER_PTE)
+        {
+            do
+            {
+                pagetable->last_superpte -= GSL_PT_SUPER_PTE;
+            } while (!GSL_PT_MAP_GETADDR(pagetable->last_superpte) && pagetable->last_superpte >= GSL_PT_SUPER_PTE);
+        }
+
+		GSL_MMU_STATS(mmu->stats.pt.unmaps++);
+    }
+    else
+    {
+        // this should never happen
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" );
+        KOS_ASSERT(0);
+        status = GSL_FAILURE;
+    }
+
+    // invalidate tlb, debug only
+	KGSL_DEBUG(GSL_DBGFLAGS_MMU, mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[mmu->device->id-1].INVALIDATE, pagetable->pid));
+
+    GSL_MMU_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_SUCCESS );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int         
+kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid)
+{
+    //
+    // obtain scatter list of physical pages for the given gpu address range.
+    // if all pages are physically contiguous they are coalesced into a single
+    // scatterlist entry.
+    //
+    gsl_pagetable_t  *pagetable;
+    unsigned int     numpages;
+    unsigned int     pte, ptefirst, ptelast;
+    unsigned int     contiguous = 1;
+
+    numpages = (range >> GSL_PAGESIZE_SHIFT);
+    if (range & (GSL_PAGESIZE-1))
+    {
+        numpages++;
+    }
+
+    if (range <= 0 || scatterlist->num != numpages)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" );
+        KOS_ASSERT(0);
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_getmap. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_MMU_LOCK();
+
+    pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+    if (!pagetable)
+    {
+        GSL_MMU_UNLOCK();
+        return (GSL_FAILURE);
+    }
+
+    ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr);
+    ptelast  = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1)));
+
+    // determine whether pages are physically contiguous
+    if (numpages > 1)
+    {
+        for (pte = ptefirst; pte <= ptelast-1; pte++)
+        {
+            if (GSL_PT_MAP_GETADDR(pte) + GSL_PAGESIZE != GSL_PT_MAP_GETADDR(pte+1))
+            {
+                contiguous = 0;
+                break;
+            }
+        }
+    }
+
+    if (!contiguous)
+    {
+        // populate scatter list
+        for (pte = ptefirst; pte <= ptelast; pte++)
+        {
+            scatterlist->pages[pte-ptefirst] = GSL_PT_MAP_GETADDR(pte);
+        }
+    }
+    else
+    {
+        // coalesce physically contiguous pages into a single scatter list entry
+        scatterlist->pages[0] = GSL_PT_MAP_GETADDR(ptefirst);
+    }
+
+    GSL_MMU_UNLOCK();
+
+    scatterlist->contiguous = contiguous;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_close(gsl_device_t *device)
+{
+    //
+    // close device mmu
+    //
+    // call this with the global lock held
+    //
+    gsl_mmu_t     *mmu     = &device->mmu;
+    unsigned int  devindex = mmu->device->id-1;         // device_id is 1 based
+#ifdef _DEBUG
+    int           i;
+#endif // _DEBUG
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_close(gsl_device_t *device=0x%08x)\n", device );
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        if (mmu->flags & GSL_FLAGS_STARTED)
+        {
+            // terminate pagetable object
+            kgsl_mmu_destroypagetableobject(mmu, GSL_CALLER_PROCESSID_GET());
+        }
+
+        // no more processes attached to current device mmu
+        if (mmu->refcnt == 0)
+        {
+#ifdef _DEBUG
+            // check if there are any orphaned pagetable objects lingering around
+            for (i = 0; i < GSL_MMU_PAGETABLE_MAX; i++)
+            {
+                if (mmu->pagetable[i])
+                {
+                    /* many dumpx test cases forcefully exit, and thus trigger this assert. */
+                    /* Because it is an annoyance for HW guys, it is disabled for dumpx */
+                    if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX)
+                    {
+                        KOS_ASSERT(0);
+                        return (GSL_FAILURE);
+                    }
+                }
+            }
+#endif // _DEBUG
+
+            // disable mh interrupts
+            kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR);
+            kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR);
+            kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT);
+
+            // disable MMU
+            device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, 0x00000000);
+
+            if (mmu->tlbflushfilter.base)
+            {
+                kos_free(mmu->tlbflushfilter.base);
+            }
+
+            if (mmu->dummyspace.gpuaddr)
+            {
+                kgsl_sharedmem_free0(&mmu->dummyspace, GSL_CALLER_PROCESSID_GET());
+            }
+
+            GSL_MMU_MUTEX_FREE();
+
+            mmu->flags &= ~GSL_FLAGS_STARTED;
+            mmu->flags &= ~GSL_FLAGS_INITIALIZED;
+            mmu->flags &= ~GSL_FLAGS_INITIALIZED0;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_close. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid)
+{
+    //
+    // attach process
+    //
+    // call this with the global lock held
+    //
+    int              status = GSL_SUCCESS;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_attachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    GSL_MMU_LOCK();
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        // attach to current device mmu
+        mmu->refcnt++;
+
+        if (mmu->flags & GSL_FLAGS_STARTED)
+        {
+            // attach to pagetable object
+            pagetable = kgsl_mmu_createpagetableobject(mmu, pid);
+            if(pagetable)
+            {
+                pagetable->refcnt++;
+            }
+            else
+            {
+                status = GSL_FAILURE;
+            }
+        }
+    }
+
+    GSL_MMU_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_attachcallback. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid)
+{
+    //
+    // detach process
+    //
+    int              status = GSL_SUCCESS;
+    gsl_pagetable_t  *pagetable;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_detachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid );
+
+    GSL_MMU_LOCK();
+
+    if (mmu->flags & GSL_FLAGS_INITIALIZED0)
+    {
+        // detach from current device mmu
+        mmu->refcnt--;
+
+        if (mmu->flags & GSL_FLAGS_STARTED)
+        {
+            // detach from pagetable object
+            pagetable = kgsl_mmu_getpagetableobject(mmu, pid);
+            if(pagetable)
+            {
+                pagetable->refcnt--;
+            }
+            else
+            {
+                status = GSL_FAILURE;
+            }
+        }
+    }
+
+    GSL_MMU_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_detachcallback. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats)
+{
+#ifdef GSL_STATS_MMU
+    int              status = GSL_SUCCESS;
+
+    KOS_ASSERT(stats);
+
+    GSL_MMU_LOCK();
+
+    if (mmu->flags & GSL_FLAGS_STARTED)
+    {
+		kos_memcpy(stats, &mmu->stats, sizeof(gsl_mmustats_t));
+    }
+    else
+    {
+		kos_memset(stats, 0, sizeof(gsl_mmustats_t));
+    }
+
+    GSL_MMU_UNLOCK();
+
+    return (status);
+#else
+    // unreferenced formal parameters
+    (void) mmu;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_MMU
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_mmu_bist(gsl_mmu_t *mmu)
+{
+    // unreferenced formal parameter
+    (void) mmu;
+
+    return (GSL_SUCCESS);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c
new file mode 100644
index 00000000000..fb05ff3cbe1
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c
@@ -0,0 +1,1163 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#include "gsl_cmdstream.h"
+
+#ifdef GSL_BLD_YAMATO
+
+//////////////////////////////////////////////////////////////////////////////
+// ucode
+//////////////////////////////////////////////////////////////////////////////
+#define uint32 unsigned int
+
+#include "pm4_microcode.inl"
+#include "pfp_microcode_nrt.inl"
+
+#undef  uint32
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_RB_NOP_SIZEDWORDS               2               // default is 2
+#define GSL_RB_PROTECTED_MODE_CONTROL       0x00000000      // protected mode error checking below register address 0x800
+                                                            // note: if CP_INTERRUPT packet is used then checking needs
+                                                            // to change to below register address 0x7C8
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  ringbuffer size log2 quadwords equivalent
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE unsigned int
+gsl_ringbuffer_sizelog2quadwords(unsigned int sizedwords)
+{
+    unsigned int sizelog2quadwords = 0;
+    int i = sizedwords >> 1;
+    while (i >>= 1)
+    {
+       sizelog2quadwords++;
+    }
+    return (sizelog2quadwords);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// private prototypes
+//////////////////////////////////////////////////////////////////////////////
+#ifdef _DEBUG
+static void     kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug);
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+void
+kgsl_cp_intrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_ringbuffer_t  *rb = (gsl_ringbuffer_t *) cookie;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_cp_intrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie );
+
+    switch(id)
+    {
+        // error condition interrupt
+        case GSL_INTR_YDX_CP_T0_PACKET_IN_IB:
+        case GSL_INTR_YDX_CP_OPCODE_ERROR:
+        case GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR:
+        case GSL_INTR_YDX_CP_RESERVED_BIT_ERROR:
+        case GSL_INTR_YDX_CP_IB_ERROR:
+	    printk(KERN_ERR "GPU: CP Error\n");
+	    schedule_work(&rb->device->irq_err_work);
+            break;
+
+        // non-error condition interrupt
+        case GSL_INTR_YDX_CP_SW_INT:
+        case GSL_INTR_YDX_CP_IB2_INT:
+        case GSL_INTR_YDX_CP_IB1_INT:
+        case GSL_INTR_YDX_CP_RING_BUFFER:
+
+            // signal intr completion event
+            kos_event_signal(rb->device->intr.evnt[id]);
+            break;
+
+        default:
+
+            break;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cp_intrcallback.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_watchdog()
+{
+    gsl_ringbuffer_t  *rb = &(gsl_driver.device[GSL_DEVICE_YAMATO-1]).ringbuffer;       // device_id is 1 based
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> void kgsl_ringbuffer_watchdog()\n" );
+
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        GSL_RB_MUTEX_LOCK();
+
+        GSL_RB_GET_READPTR(rb, &rb->rptr);
+
+        // ringbuffer is currently not empty
+        if (rb->rptr != rb->wptr)
+        {
+            // and a rptr sample was taken during interval n-1
+            if (rb->watchdog.flags & GSL_FLAGS_ACTIVE)
+            {
+                // and the rptr did not advance between interval n-1 and n
+                if (rb->rptr == rb->watchdog.rptr_sample)
+                {
+                    // then the core has hung
+                    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_FATAL,
+                                     "ERROR: Watchdog detected core hung.\n" );
+
+                    rb->device->ftbl.device_destroy(rb->device);
+                    return;
+                }
+            }
+
+            // save rptr sample for interval n
+            rb->watchdog.flags       |= GSL_FLAGS_ACTIVE;
+            rb->watchdog.rptr_sample  = rb->rptr;
+        }
+        else
+        {
+            // clear rptr sample for interval n
+            rb->watchdog.flags &= ~GSL_FLAGS_ACTIVE;
+        }
+
+        GSL_RB_MUTEX_UNLOCK();
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_watchdog.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+
+OSINLINE void
+kgsl_ringbuffer_checkregister(unsigned int reg, int pmodecheck)
+{
+	if (pmodecheck)
+	{
+		// check for register protection mode violation
+		if (reg <= (GSL_RB_PROTECTED_MODE_CONTROL & 0x3FFF))
+		{
+			kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register protection mode violation.\n" );
+			KOS_ASSERT(0);
+		}
+	}
+
+	// range check register offset 
+	if (reg > (gsl_driver.device[GSL_DEVICE_YAMATO-1].regspace.sizebytes >> 2))
+	{
+		kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register out of range.\n" );
+		KOS_ASSERT(0);
+	}
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_checkpm4type0(unsigned int header, unsigned int** cmds, int pmodeoff)
+{
+    pm4_type0     pm4header = *((pm4_type0*) &header);
+    unsigned int  reg;
+
+    if (pm4header.one_reg_wr)
+    {
+        reg = pm4header.base_index;
+    }
+    else
+    {
+        reg = pm4header.base_index + pm4header.count;
+    }
+
+	kgsl_ringbuffer_checkregister(reg, !pmodeoff);
+
+    *cmds += pm4header.count + 1;
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_checkpm4type3(unsigned int header, unsigned int** cmds, int indirection, int pmodeoff)
+{
+    pm4_type3     pm4header = *((pm4_type3*) &header);
+    unsigned int  *ordinal2 = *cmds;
+    unsigned int  *ibcmds, *end;
+    unsigned int  reg, length;
+
+	// check indirect buffer level
+	if (indirection > 2)
+	{
+		kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Only two levels of indirection supported.\n" );
+		KOS_ASSERT(0);
+	}
+
+    switch(pm4header.it_opcode)
+    {
+    case PM4_INDIRECT_BUFFER:
+    case PM4_INDIRECT_BUFFER_PFD:
+
+        // determine ib host base and end address
+        ibcmds = (unsigned int*) kgsl_sharedmem_convertaddr(*ordinal2, 0);
+        end    = ibcmds + *(ordinal2 + 1);
+
+        // walk through the ib
+        while(ibcmds < end)
+        {
+            unsigned int tmpheader = *(ibcmds++);
+
+            switch(tmpheader & PM4_PKT_MASK)
+            {
+            case PM4_TYPE0_PKT:
+                kgsl_ringbuffer_checkpm4type0(tmpheader, &ibcmds, pmodeoff);
+                break;
+
+            case PM4_TYPE1_PKT:
+            case PM4_TYPE2_PKT:
+                break;
+
+            case PM4_TYPE3_PKT:
+                kgsl_ringbuffer_checkpm4type3(tmpheader, &ibcmds, (indirection + 1), pmodeoff);
+                break;
+            }
+        }
+        break;
+
+    case PM4_ME_INIT:
+
+        if(indirection != 0)
+        {
+			kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: ME INIT packet cannot reside in an ib.\n" );
+            KOS_ASSERT(0);
+        }
+        break;
+
+    case PM4_REG_RMW:
+
+        reg = (*ordinal2) & 0x1FFF;
+
+		kgsl_ringbuffer_checkregister(reg, !pmodeoff);
+
+        break;
+
+    case PM4_SET_CONSTANT:
+
+        if((((*ordinal2) >> 16) & 0xFF) == 0x4)         // incremental register update
+        {
+            reg    = 0x2000 + ((*ordinal2) & 0x3FF);    // gfx decode space address starts at 0x2000
+            length = pm4header.count - 1;
+
+			kgsl_ringbuffer_checkregister(reg + length, 0);
+        }
+        break;
+
+    case PM4_LOAD_CONSTANT_CONTEXT:
+
+        if(((*(ordinal2 + 1) >> 16) & 0xFF) == 0x4)      // incremental register update
+        {
+            reg    = 0x2000 + (*(ordinal2 + 1) & 0x3FF); // gfx decode space address starts at 0x2000
+            length = *(ordinal2 + 2);
+
+			kgsl_ringbuffer_checkregister(reg + length, 0);
+        }
+        break;
+
+    case PM4_COND_WRITE:
+
+        if(((*ordinal2) & 0x00000100) == 0x0)           // write to register
+        {
+            reg = *(ordinal2 + 4) & 0x3FFF;
+
+			kgsl_ringbuffer_checkregister(reg, !pmodeoff);
+        }
+        break;
+    }
+
+    *cmds += pm4header.count + 1;
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_ringbuffer_checkpm4(unsigned int* cmds, unsigned int sizedwords, int pmodeoff)
+{
+    unsigned int *ringcmds = cmds;
+    unsigned int *end      = cmds + sizedwords;
+
+    while(ringcmds < end)
+    {
+        unsigned int header = *(ringcmds++);
+
+        switch(header & PM4_PKT_MASK)
+        {
+            case PM4_TYPE0_PKT:
+                kgsl_ringbuffer_checkpm4type0(header, &ringcmds, pmodeoff);
+                break;
+
+            case PM4_TYPE1_PKT:
+            case PM4_TYPE2_PKT:
+                break;
+
+            case PM4_TYPE3_PKT:
+                kgsl_ringbuffer_checkpm4type3(header, &ringcmds, 0, pmodeoff);
+                break;
+        }
+    }
+}
+
+#endif // _DEBUG
+
+//----------------------------------------------------------------------------
+
+static void
+kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb)
+{
+    unsigned int value;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static void kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    KOS_ASSERT(rb->wptr != 0);
+
+    kgsl_device_active(rb->device);
+    
+    GSL_RB_UPDATE_WPTR_POLLING(rb);
+
+    // send the wptr to the hw
+    rb->device->ftbl.device_regwrite(rb->device, mmCP_RB_WPTR, rb->wptr);
+
+    rb->flags |= GSL_FLAGS_ACTIVE;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_submit.\n" );
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb, unsigned int numcmds, int wptr_ahead)
+{
+    int           nopcount;
+    unsigned int  freecmds;
+    unsigned int  *cmds;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static int kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d, int wptr_ahead=%d)\n",
+                    rb, numcmds, wptr_ahead );
+
+
+    // if wptr ahead, fill the remaining with NOPs
+    if (wptr_ahead)
+    {
+        nopcount = rb->sizedwords - rb->wptr - 1;   // -1 for header
+
+        cmds = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
+        GSL_RB_WRITE(cmds, pm4_nop_packet(nopcount));
+        rb->wptr++;
+
+        kgsl_ringbuffer_submit(rb);
+
+        rb->wptr = 0;
+
+        GSL_RB_STATS(rb->stats.wraps++);
+    }
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RBWAIT, GSL_DEVICE_YAMATO, rb->wptr, numcmds, "kgsl_ringbuffer_waitspace"));
+
+    // wait for space in ringbuffer
+    for( ; ; )
+    {
+        GSL_RB_GET_READPTR(rb, &rb->rptr);
+
+        freecmds = rb->rptr - rb->wptr;
+
+        if ((freecmds == 0) || (freecmds > numcmds))
+        {
+            break;
+        }
+
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static unsigned int *
+kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb, unsigned int numcmds)
+{
+    unsigned int  *ptr;
+    int           status = GSL_SUCCESS;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static unsigned int* kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d)\n",
+                    rb, numcmds );
+
+    KOS_ASSERT(numcmds < rb->sizedwords);
+
+    // update host copy of read pointer when running in safe mode
+    if (rb->device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        GSL_RB_GET_READPTR(rb, &rb->rptr);
+    }
+
+    // check for available space
+    if (rb->wptr >= rb->rptr)
+    {
+        // wptr ahead or equal to rptr
+        if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS))   // reserve dwords for nop packet
+        {
+            status = kgsl_ringbuffer_waitspace(rb, numcmds, 1);
+        }
+    }
+    else
+    {
+        // wptr behind rptr
+        if ((rb->wptr + numcmds) >= rb->rptr)
+        {
+            status  = kgsl_ringbuffer_waitspace(rb, numcmds, 0);
+        }
+
+        // check for remaining space
+        if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS))   // reserve dwords for nop packet
+        {
+            status = kgsl_ringbuffer_waitspace(rb, numcmds, 1);
+        }
+    }
+
+    ptr       = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr;
+    rb->wptr += numcmds;
+
+    if (status == GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", ptr );
+        return (ptr);
+    }
+    else
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", NULL );
+        return (NULL);
+    }
+}
+
+//----------------------------------------------------------------------------
+int
+kgsl_ringbuffer_start(gsl_ringbuffer_t *rb)
+{
+    int           status;
+    cp_rb_cntl_u  cp_rb_cntl;
+    int           i;
+    unsigned int  *cmds;
+    gsl_device_t  *device = rb->device;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static int kgsl_ringbuffer_start(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    // clear memptrs values
+    kgsl_sharedmem_set0(&rb->memptrs_desc, 0, 0, sizeof(gsl_rbmemptrs_t));
+
+    // clear ringbuffer
+    kgsl_sharedmem_set0(&rb->buffer_desc, 0, 0x12341234, (rb->sizedwords << 2));
+
+    // setup WPTR polling address
+    device->ftbl.device_regwrite(device, mmCP_RB_WPTR_BASE, (rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_WPTRPOLL_OFFSET));
+
+    // setup WPTR delay
+    device->ftbl.device_regwrite(device, mmCP_RB_WPTR_DELAY, 0/*0x70000010*/);
+
+    // setup RB_CNTL
+    device->ftbl.device_regread(device, mmCP_RB_CNTL, (unsigned int *)&cp_rb_cntl);
+
+    cp_rb_cntl.f.rb_bufsz       = gsl_ringbuffer_sizelog2quadwords(rb->sizedwords); // size of ringbuffer
+    cp_rb_cntl.f.rb_blksz       = rb->blksizequadwords;                             // quadwords to read before updating mem RPTR
+    cp_rb_cntl.f.rb_poll_en     = GSL_RB_CNTL_POLL_EN;                              // WPTR polling
+    cp_rb_cntl.f.rb_no_update   = GSL_RB_CNTL_NO_UPDATE;                            // mem RPTR writebacks
+
+    device->ftbl.device_regwrite(device, mmCP_RB_CNTL, cp_rb_cntl.val);
+
+    // setup RB_BASE
+    device->ftbl.device_regwrite(device, mmCP_RB_BASE, rb->buffer_desc.gpuaddr);
+
+    // setup RPTR_ADDR
+    device->ftbl.device_regwrite(device, mmCP_RB_RPTR_ADDR, rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_RPTR_OFFSET);
+
+    // explicitly clear all cp interrupts when running in safe mode
+    if (rb->device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_regwrite(device, mmCP_INT_ACK, 0xFFFFFFFF);
+    }
+
+    // setup scratch/timestamp addr
+    device->ftbl.device_regwrite(device, mmSCRATCH_ADDR, device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp));
+
+    // setup scratch/timestamp mask
+    device->ftbl.device_regwrite(device, mmSCRATCH_UMSK, GSL_RB_MEMPTRS_SCRATCH_MASK);
+
+    // load the CP ucode
+    device->ftbl.device_regwrite(device, mmCP_DEBUG, 0x02000000);
+    device->ftbl.device_regwrite(device, mmCP_ME_RAM_WADDR, 0);
+
+    for (i = 0; i < PM4_MICROCODE_SIZE; i++ )
+    {
+        device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][0]);
+        device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][1]);
+        device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][2]);
+    }
+
+    // load the prefetch parser ucode
+    device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_ADDR, 0);
+
+    for ( i = 0; i < PFP_MICROCODE_SIZE_NRT; i++ )
+    {
+        device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_DATA, aPFP_Microcode_nrt[i]);
+    }
+
+    // queue thresholds ???
+    device->ftbl.device_regwrite(device, mmCP_QUEUE_THRESHOLDS, 0x000C0804);
+
+    // reset pointers
+    rb->rptr = 0;
+    rb->wptr = 0;
+
+    // init timestamp
+    rb->timestamp    = 0;
+    GSL_RB_INIT_TIMESTAMP(rb);
+
+    // clear ME_HALT to start micro engine
+    device->ftbl.device_regwrite(device, mmCP_ME_CNTL, 0);
+
+    // ME_INIT
+    cmds  = kgsl_ringbuffer_addcmds(rb, 19);
+
+    GSL_RB_WRITE(cmds, PM4_HDR_ME_INIT);
+    GSL_RB_WRITE(cmds, 0x000003ff);                         // All fields present (bits 9:0)
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Disable/Enable Real-Time Stream processing (present but ignored)
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Enable (2D to 3D) and (3D to 2D) implicit synchronization (present but ignored)
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_SURFACE_INFO));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_WINDOW_OFFSET));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmVGT_MAX_VTX_INDX));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmSQ_PROGRAM_CNTL));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_DEPTHCONTROL));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POINT_SIZE));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_LINE_CNTL));
+    GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POLY_OFFSET_FRONT_SCALE));
+    GSL_RB_WRITE(cmds, 0x80000180);                         // Vertex and Pixel Shader Start Addresses in instructions (3 DWORDS per instruction)
+    GSL_RB_WRITE(cmds, 0x00000001);                         // Maximum Contexts
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Write Confirm Interval and The CP will wait the wait_interval * 16 clocks between polling
+    GSL_RB_WRITE(cmds, 0x00000000);                         // NQ and External Memory Swap
+    GSL_RB_WRITE(cmds, GSL_RB_PROTECTED_MODE_CONTROL);      // Protected mode error checking
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Disable header dumping and Header dump address
+    GSL_RB_WRITE(cmds, 0x00000000);                         // Header dump size
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4((unsigned int *)rb->buffer_desc.hostptr, 19, 1));
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4((unsigned int *)rb->buffer_desc.hostptr, 19));
+
+    kgsl_ringbuffer_submit(rb);
+
+    // idle device to validate ME INIT
+    status = device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+
+    if (status == GSL_SUCCESS)
+    {
+        rb->flags |= GSL_FLAGS_STARTED;
+    }
+
+    // enable cp interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_SW_INT, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB_ERROR, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB2_INT, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB1_INT, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_cp_intrcallback, (void *) rb);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_SW_INT);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB2_INT);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB1_INT);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb)
+{
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> static int kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        // disable cp interrupts
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_SW_INT);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB_ERROR);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB2_INT);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB1_INT);
+        kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+
+        // ME_HALT
+        rb->device->ftbl.device_regwrite(rb->device, mmCP_ME_CNTL, 0x10000000);
+
+        rb->flags &= ~GSL_FLAGS_STARTED;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_stop. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_init(gsl_device_t *device)
+{
+    int               status;
+    gsl_flags_t       flags;
+    gsl_ringbuffer_t  *rb = &device->ringbuffer;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_ringbuffer_init(gsl_device_t *device=0x%08x)\n", device );
+
+    rb->device           = device;
+    rb->sizedwords       = (2 << gsl_cfg_rb_sizelog2quadwords);
+    rb->blksizequadwords = gsl_cfg_rb_blksizequadwords;
+
+    GSL_RB_MUTEX_CREATE();
+
+    // allocate memory for ringbuffer, needs to be double octword aligned
+    // align on page from contiguous physical memory
+    flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST);
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_STRICTREQUEST)); /* set MMU table for ringbuffer */
+
+    status = kgsl_sharedmem_alloc0(device->id, flags, (rb->sizedwords << 2), &rb->buffer_desc);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_SET, (unsigned int)rb->buffer_desc.gpuaddr, (unsigned int)rb->buffer_desc.hostptr, 0, "kgsl_ringbuffer_init"));
+
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_ringbuffer_close(rb);
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status );
+        return (status);
+    }
+
+    // allocate memory for polling and timestamps
+    flags = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS);
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = GSL_MEMFLAGS_ALIGN32);
+
+    status = kgsl_sharedmem_alloc0(device->id, flags, sizeof(gsl_rbmemptrs_t), &rb->memptrs_desc);
+
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_ringbuffer_close(rb);
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status );
+        return (status);
+    }
+
+    // overlay structure on memptrs memory
+    rb->memptrs = (gsl_rbmemptrs_t *)rb->memptrs_desc.hostptr;
+
+    rb->flags |= GSL_FLAGS_INITIALIZED;
+
+	// validate command stream data when running in safe mode
+	if (device->flags & GSL_FLAGS_SAFEMODE)
+	{
+		gsl_driver.flags_debug |= GSL_DBGFLAGS_PM4CHECK;
+	}
+
+    // start ringbuffer
+    status = kgsl_ringbuffer_start(rb);
+
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_ringbuffer_close(rb);
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status );
+        return (status);
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", GSL_SUCCESS );
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_close(gsl_ringbuffer_t *rb)
+{
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_ringbuffer_close(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    GSL_RB_MUTEX_LOCK();
+
+    // stop ringbuffer
+    kgsl_ringbuffer_stop(rb);
+
+    // free buffer
+    if (rb->buffer_desc.hostptr)
+    {
+        kgsl_sharedmem_free0(&rb->buffer_desc, GSL_CALLER_PROCESSID_GET());
+    }
+
+    // free memory pointers
+    if (rb->memptrs_desc.hostptr)
+    {
+        kgsl_sharedmem_free0(&rb->memptrs_desc, GSL_CALLER_PROCESSID_GET());
+    }
+
+    rb->flags &= ~GSL_FLAGS_INITIALIZED;
+
+    GSL_RB_MUTEX_UNLOCK();
+
+    GSL_RB_MUTEX_FREE();
+
+    kos_memset(rb, 0, sizeof(gsl_ringbuffer_t));
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_close. Return value %B\n", GSL_SUCCESS );
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+gsl_timestamp_t
+kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmds, int sizedwords, unsigned int pid)
+{
+    gsl_ringbuffer_t  *rb = &device->ringbuffer;
+    unsigned int      pmodesizedwords;
+    unsigned int      *ringcmds;
+    unsigned int      timestamp;
+
+    pmodeoff = 0;
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_timestamp_t kgsl_ringbuffer_issuecmds(gsl_device_t *device=0x%08x, int pmodeoff=%d, unsigned int *cmds=0x%08x, int sizedwords=%d, unsigned int pid=0x%08x)\n",
+                     device, pmodeoff, cmds, sizedwords, pid );
+
+	if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED))
+	{
+		return (0);
+	}
+
+    // set mmu pagetable
+	kgsl_mmu_setpagetable(device, pid);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4(cmds, sizedwords, pmodeoff));
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4(cmds, sizedwords));
+
+    // reserve space to temporarily turn off protected mode error checking if needed
+    pmodesizedwords = pmodeoff ? 8 : 0;
+
+#if defined GSL_RB_TIMESTAMP_INTERUPT
+    pmodesizedwords += 2;
+#endif        
+    // allocate space in ringbuffer
+    ringcmds = kgsl_ringbuffer_addcmds(rb, pmodesizedwords + sizedwords + 6);
+
+    if (pmodeoff)
+    {
+        // disable protected mode error checking
+        *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2);
+        *ringcmds++ = 0x00000080;
+        *ringcmds++ = 0x00000000;
+    }
+
+    // copy the cmds to the ringbuffer
+    kos_memcpy(ringcmds, cmds, (sizedwords << 2));
+
+    ringcmds += sizedwords;
+
+    if (pmodeoff)
+    {
+        *ringcmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+        *ringcmds++ = 0;
+
+        // re-enable protected mode error checking
+        *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2);
+        *ringcmds++ = 0x00000080;
+        *ringcmds++ = GSL_RB_PROTECTED_MODE_CONTROL;
+    }
+
+    // increment timestamp
+    rb->timestamp++;
+    timestamp = rb->timestamp;
+
+    // start-of-pipeline and end-of-pipeline timestamps
+    *ringcmds++ = pm4_type0_packet(mmCP_TIMESTAMP, 1);
+    *ringcmds++ = rb->timestamp;
+    *ringcmds++ = pm4_type3_packet(PM4_EVENT_WRITE, 3);
+    *ringcmds++ = CACHE_FLUSH_TS;
+    *ringcmds++ = device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp);
+    *ringcmds++ = rb->timestamp;
+
+#if defined GSL_RB_TIMESTAMP_INTERUPT    
+    *ringcmds++ = pm4_type3_packet(PM4_INTERRUPT, 1);
+    *ringcmds++ = 0x80000000;
+#endif
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (pmodesizedwords + sizedwords + 6) << 2, "kgsl_ringbuffer_issuecmds"));
+
+    // issue the commands
+    kgsl_ringbuffer_submit(rb);
+
+    // stats
+    GSL_RB_STATS(rb->stats.wordstotal += sizedwords);
+    GSL_RB_STATS(rb->stats.issues++);
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issuecmds. Return value %d\n", timestamp );
+
+    // return timestamp of issued commands
+    return (timestamp);
+}
+
+//----------------------------------------------------------------------------
+int
+kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags)
+{
+    unsigned int  link[3];
+    int dumpx_swap;
+    (void)dumpx_swap; // used only when BB_DUMPX is defined
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> gsl_timestamp_t kgsl_ringbuffer_issueibcmds(gsl_device_t device=%0x%08x, int drawctxt_index=%d, gpuaddr_t ibaddr=0x%08x, int sizedwords=%d, gsl_timestamp_t *timestamp=0x%08x)\n",
+                     device, drawctxt_index, ibaddr, sizedwords, timestamp );
+
+    if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(ibaddr);
+    KOS_ASSERT(sizedwords);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, dumpx_swap = kgsl_dumpx_parse_ibs(ibaddr, sizedwords));
+
+	GSL_RB_MUTEX_LOCK();
+
+	// context switch if needed
+	kgsl_drawctxt_switch(device, &device->drawctxt[drawctxt_index], flags);
+
+    link[0] = PM4_HDR_INDIRECT_BUFFER_PFD;
+    link[1] = ibaddr;
+    link[2] = sizedwords;
+
+	*timestamp = kgsl_ringbuffer_issuecmds(device, 0, &link[0], 3, GSL_CALLER_PROCESSID_GET());
+
+	GSL_RB_MUTEX_UNLOCK();
+
+    // idle device when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+    }
+    else
+    {
+        KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+        {
+            // insert wait for idle after every IB1
+            // this is conservative but works reliably and is ok even for performance simulations
+            device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+        });
+    }
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+    {
+        if(dumpx_swap)
+        {
+            KGSL_DEBUG_DUMPX( BB_DUMP_EXPORT_CBUF, 0, 0, 0, "resolve");
+            KGSL_DEBUG_DUMPX( BB_DUMP_FLUSH,0,0,0," ");
+        }
+    });
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+static void
+kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug)
+{
+    kos_memset(rb_debug, 0, sizeof(gsl_rb_debug_t));
+
+    rb_debug->pm4_ucode_rel = PM4_MICROCODE_VERSION;
+    rb_debug->pfp_ucode_rel = PFP_MICROCODE_VERSION;
+
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_BASE,      (unsigned int *)&rb_debug->cp_rb_base);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_CNTL,      (unsigned int *)&rb_debug->cp_rb_cntl);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR_ADDR, (unsigned int *)&rb_debug->cp_rb_rptr_addr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR,      (unsigned int *)&rb_debug->cp_rb_rptr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR,      (unsigned int *)&rb_debug->cp_rb_wptr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR_BASE, (unsigned int *)&rb_debug->cp_rb_wptr_base);
+    rb->device->ftbl.device_regread(rb->device, mmSCRATCH_UMSK,    (unsigned int *)&rb_debug->scratch_umsk);
+    rb->device->ftbl.device_regread(rb->device, mmSCRATCH_ADDR,    (unsigned int *)&rb_debug->scratch_addr);
+    rb->device->ftbl.device_regread(rb->device, mmCP_ME_CNTL,      (unsigned int *)&rb_debug->cp_me_cntl);
+    rb->device->ftbl.device_regread(rb->device, mmCP_ME_STATUS,    (unsigned int *)&rb_debug->cp_me_status);
+    rb->device->ftbl.device_regread(rb->device, mmCP_DEBUG,        (unsigned int *)&rb_debug->cp_debug);
+    rb->device->ftbl.device_regread(rb->device, mmCP_STAT,         (unsigned int *)&rb_debug->cp_stat);
+    rb->device->ftbl.device_regread(rb->device, mmRBBM_STATUS,     (unsigned int *)&rb_debug->rbbm_status);
+    rb_debug->sop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_CONSUMED);
+    rb_debug->eop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_RETIRED);
+}
+#endif
+
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats)
+{
+#ifdef GSL_STATS_RINGBUFFER
+    KOS_ASSERT(stats);
+
+    if (!(rb->flags & GSL_FLAGS_STARTED))
+    {
+        return (GSL_FAILURE);
+    }
+
+    kos_memcpy(stats, &rb->stats, sizeof(gsl_rbstats_t));
+
+    return (GSL_SUCCESS);
+#else
+    // unreferenced formal parameters
+    (void) rb;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_RINGBUFFER
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb)
+{
+    unsigned int    *cmds;
+    unsigned int    temp, k, j;
+    int             status;
+    int             i;
+#ifdef _DEBUG
+    gsl_rb_debug_t  rb_debug;
+#endif
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb=0x%08x)\n", rb );
+
+    if (!(rb->flags & GSL_FLAGS_STARTED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // simple nop submit
+    cmds = kgsl_ringbuffer_addcmds(rb, 2);
+    if (!cmds)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_RB_WRITE(cmds, pm4_nop_packet(1));
+    GSL_RB_WRITE(cmds, 0xDEADBEEF);
+
+    kgsl_ringbuffer_submit(rb);
+
+    status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+    if (status != GSL_SUCCESS)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+        return (status);
+    }
+
+    // simple scratch submit
+    cmds = kgsl_ringbuffer_addcmds(rb, 2);
+    if (!cmds)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1));
+    GSL_RB_WRITE(cmds, 0xFEEDF00D);
+
+    kgsl_ringbuffer_submit(rb);
+
+    status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+    if (status != GSL_SUCCESS)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+        return (status);
+    }
+
+    rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp);
+
+    if (temp != 0xFEEDF00D)
+    {
+#ifdef _DEBUG
+        kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+        kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // simple wraps
+    for (i = 0; i < 256; i+=2)
+    {
+        j    = ((rb->sizedwords >> 2) - 256) + i;
+
+        cmds = kgsl_ringbuffer_addcmds(rb, j);
+        if (!cmds)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+            return (GSL_FAILURE);
+        }
+
+        k = 0;
+
+        while (k < j)
+        {
+            k+=2;
+            GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1));
+            GSL_RB_WRITE(cmds, k);
+        }
+
+        kgsl_ringbuffer_submit(rb);
+
+        status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+        if (status != GSL_SUCCESS)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+            return (status);
+        }
+
+        rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp);
+
+        if (temp != k)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+            return (GSL_FAILURE);
+        }
+    }
+
+    // max size submits, TODO do this at least with regreads
+    for (i = 0; i < 256; i++)
+    {
+        cmds = kgsl_ringbuffer_addcmds(rb, (rb->sizedwords >> 2));
+        if (!cmds)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE );
+            return (GSL_FAILURE);
+        }
+
+        GSL_RB_WRITE(cmds, pm4_nop_packet((rb->sizedwords >> 2) - 1));
+
+        kgsl_ringbuffer_submit(rb);
+
+        status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT);
+
+        if (status != GSL_SUCCESS)
+        {
+#ifdef _DEBUG
+            kgsl_ringbuffer_debug(rb, &rb_debug);
+#endif
+            kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status );
+            return (status);
+        }
+    }
+
+    // submit load with randomness
+
+#ifdef GSL_RB_USE_MEM_TIMESTAMP
+    // scratch memptr validate
+#endif // GSL_RB_USE_MEM_TIMESTAMP
+
+#ifdef GSL_RB_USE_MEM_RPTR
+    // rptr memptr validate
+#endif // GSL_RB_USE_MEM_RPTR
+
+#ifdef  GSL_RB_USE_WPTR_POLLING
+    // wptr memptr validate
+#endif // GSL_RB_USE_WPTR_POLLING
+
+    kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+#endif
+
diff --git a/drivers/mxc/amd-gpu/common/gsl_sharedmem.c b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c
new file mode 100644
index 00000000000..51e66f97c52
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c
@@ -0,0 +1,937 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_SHMEM_APERTURE_MARK(aperture_id)    \
+    (shmem->priv |= (((aperture_id + 1) << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK))
+
+#define GSL_SHMEM_APERTURE_ISMARKED(aperture_id)    \
+    (((shmem->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT) & (aperture_id + 1))
+
+#define GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id)                                                       \
+    aperture_id = (gsl_apertureid_t)((flags & GSL_MEMFLAGS_APERTURE_MASK) >> GSL_MEMFLAGS_APERTURE_SHIFT);  \
+    KOS_ASSERT(aperture_id < GSL_APERTURE_MAX);
+
+#define GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id)                                                     \
+    channel_id = (gsl_channelid_t)((flags & GSL_MEMFLAGS_CHANNEL_MASK) >> GSL_MEMFLAGS_CHANNEL_SHIFT);  \
+    KOS_ASSERT(channel_id < GSL_CHANNEL_MAX);
+
+#define GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index)   \
+    memdesc->priv = (memdesc->priv & ~GSL_APERTURE_MASK) | ((aperture_index << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK);
+
+#define GSL_MEMDESC_DEVICE_SET(memdesc, device_id)  \
+    memdesc->priv = (memdesc->priv & ~GSL_DEVICEID_MASK) | ((device_id << GSL_DEVICEID_SHIFT) & GSL_DEVICEID_MASK);
+
+#define GSL_MEMDESC_EXTALLOC_SET(memdesc, flag) \
+    memdesc->priv = (memdesc->priv & ~GSL_EXTALLOC_MASK) | ((flag << GSL_EXTALLOC_SHIFT) & GSL_EXTALLOC_MASK);
+
+#define GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index)                           \
+    KOS_ASSERT(memdesc);                                                            \
+    aperture_index = ((memdesc->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT);   \
+    KOS_ASSERT(aperture_index < GSL_SHMEM_MAX_APERTURES);
+
+#define GSL_MEMDESC_DEVICE_GET(memdesc, device_id)                                              \
+    KOS_ASSERT(memdesc);                                                                        \
+    device_id = (gsl_deviceid_t)((memdesc->priv & GSL_DEVICEID_MASK) >> GSL_DEVICEID_SHIFT);    \
+    KOS_ASSERT(device_id <= GSL_DEVICE_MAX);
+
+#define GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)  \
+    ((memdesc->priv & GSL_EXTALLOC_MASK) >> GSL_EXTALLOC_SHIFT)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// aperture index in shared memory object
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_sharedmem_getapertureindex(gsl_sharedmem_t *shmem, gsl_apertureid_t aperture_id, gsl_channelid_t channel_id)
+{
+    KOS_ASSERT(shmem->aperturelookup[aperture_id][channel_id] < shmem->numapertures);
+
+    return (shmem->aperturelookup[aperture_id][channel_id]);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+int
+kgsl_sharedmem_init(gsl_sharedmem_t *shmem)
+{
+    int                i;
+    int                status;
+    gsl_shmemconfig_t  config;
+    int                mmu_virtualized;
+    gsl_apertureid_t   aperture_id;
+    gsl_channelid_t    channel_id;
+    unsigned int       hostbaseaddr;
+    gpuaddr_t          gpubaseaddr;
+    int                sizebytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_init(gsl_sharedmem_t *shmem=0x%08x)\n", shmem );
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS );
+        return (GSL_SUCCESS);
+    }
+
+    status = kgsl_hal_getshmemconfig(&config);
+    if (status != GSL_SUCCESS)
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to get sharedmem config.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", status );
+        return (status);
+    }
+
+    shmem->numapertures = config.numapertures;
+
+    for (i = 0; i < shmem->numapertures; i++)
+    {
+        aperture_id     = config.apertures[i].id;
+        channel_id      = config.apertures[i].channel;
+        hostbaseaddr    = config.apertures[i].hostbase;
+        gpubaseaddr     = config.apertures[i].gpubase;
+        sizebytes       = config.apertures[i].sizebytes;
+        mmu_virtualized = 0;
+
+        // handle mmu virtualized aperture
+        if (aperture_id == GSL_APERTURE_MMU)
+        {
+            mmu_virtualized = 1;
+            aperture_id     = GSL_APERTURE_EMEM;
+        }
+
+        // make sure aligned to page size
+        KOS_ASSERT((gpubaseaddr & ((1 << GSL_PAGESIZE_SHIFT) - 1)) == 0);
+
+        // make a multiple of page size
+        sizebytes = (sizebytes & ~((1 << GSL_PAGESIZE_SHIFT) - 1));
+
+        if (sizebytes > 0)
+        {
+            shmem->apertures[i].memarena = kgsl_memarena_create(aperture_id, mmu_virtualized, hostbaseaddr, gpubaseaddr, sizebytes);
+
+            if (!shmem->apertures[i].memarena)
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate memarena.\n" );
+                kgsl_sharedmem_close(shmem);
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+
+            shmem->apertures[i].id       = aperture_id;
+            shmem->apertures[i].channel  = channel_id;
+            shmem->apertures[i].numbanks = 1;
+
+            // create aperture lookup table
+            if (GSL_SHMEM_APERTURE_ISMARKED(aperture_id))
+            {
+                // update "current aperture_id"/"current channel_id" index
+                shmem->aperturelookup[aperture_id][channel_id] = i;
+            }
+            else
+            {
+                // initialize "current aperture_id"/"channel_id" indexes
+                for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++)
+                {
+                    shmem->aperturelookup[aperture_id][channel_id] = i;
+                }
+
+                GSL_SHMEM_APERTURE_MARK(aperture_id);
+            }
+        }
+    }
+
+    shmem->flags |= GSL_FLAGS_INITIALIZED;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_close(gsl_sharedmem_t *shmem)
+{
+    int  i;
+    int  result = GSL_SUCCESS;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_close(gsl_sharedmem_t *shmem=0x%08x)\n", shmem );
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        for (i = 0; i < shmem->numapertures; i++)
+        {
+            if (shmem->apertures[i].memarena)
+            {
+                result = kgsl_memarena_destroy(shmem->apertures[i].memarena);
+            }
+        }
+
+        kos_memset(shmem, 0, sizeof(gsl_sharedmem_t));
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_close. Return value %B\n", result );
+
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc)
+{
+    gsl_apertureid_t  aperture_id;
+    gsl_channelid_t   channel_id;
+    gsl_deviceid_t    tmp_id;
+    int               aperture_index, org_index;
+    int               result  = GSL_FAILURE;
+    gsl_mmu_t         *mmu    = NULL;
+    gsl_sharedmem_t   *shmem  = &gsl_driver.shmem;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_alloc(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, int sizebytes=%d, gsl_memdesc_t *memdesc=%M)\n",
+                    device_id, flags, sizebytes, memdesc );
+
+    KOS_ASSERT(sizebytes);
+    KOS_ASSERT(memdesc);
+
+    GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id);
+    GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id);
+
+    kos_memset(memdesc, 0, sizeof(gsl_memdesc_t));
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    // execute pending device action
+    tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1;
+    for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+    {
+        if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED)
+        {
+            kgsl_device_runpending(&gsl_driver.device[tmp_id-1]);
+
+            if (tmp_id == device_id)
+            {
+                break;
+            }
+        }
+    }
+
+    // convert any device to an actual existing device
+    if (device_id == GSL_DEVICE_ANY)
+    {
+        for ( ; ; )
+        {
+            device_id++;
+
+            if (device_id <= GSL_DEVICE_MAX)
+            {
+                if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED)
+                {
+                    break;
+                }
+            }
+            else
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" );
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+        }
+    }
+
+    KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX);
+
+    // get mmu reference
+    mmu = &gsl_driver.device[device_id-1].mmu;
+
+    aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+    //do not proceed if it is a strict request, the aperture requested is not present, and the MMU is enabled
+    if (!((flags & GSL_MEMFLAGS_STRICTREQUEST) && aperture_id != shmem->apertures[aperture_index].id && kgsl_mmu_isenabled(mmu)))
+    {
+        // do allocation
+        result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc);
+
+        // if allocation failed
+        if (result != GSL_SUCCESS)
+        {
+            org_index = aperture_index;
+
+            // then failover to other channels within the current aperture
+            for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++)
+            {
+                aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+                if (aperture_index != org_index)
+                {
+                    // do allocation
+                    result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc);
+
+                    if (result == GSL_SUCCESS)
+                    {
+                        break;
+                    }
+                }
+            }
+
+            // if allocation still has not succeeded, then failover to EMEM/MMU aperture, but
+            // not if it's a strict request and the MMU is enabled
+            if (result != GSL_SUCCESS && aperture_id != GSL_APERTURE_EMEM
+                && !((flags & GSL_MEMFLAGS_STRICTREQUEST) && kgsl_mmu_isenabled(mmu)))
+            {
+                aperture_id = GSL_APERTURE_EMEM;
+
+                // try every channel
+                for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++)
+                {
+                    aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+                    if (aperture_index != org_index)
+                    {
+                        // do allocation
+                        result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc);
+
+                        if (result == GSL_SUCCESS)
+                        {
+                            break;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    if (result == GSL_SUCCESS)
+    {
+        GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index);
+        GSL_MEMDESC_DEVICE_SET(memdesc, device_id);
+
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            gsl_scatterlist_t scatterlist;
+
+            scatterlist.contiguous = 0;
+            scatterlist.num        = memdesc->size / GSL_PAGESIZE;
+
+            if (memdesc->size & (GSL_PAGESIZE-1))
+            {
+                scatterlist.num++;
+            }
+
+            scatterlist.pages = kos_malloc(sizeof(unsigned int) * scatterlist.num);
+            if (scatterlist.pages)
+            {
+                // allocate physical pages
+                result = kgsl_hal_allocphysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages);
+                if (result == GSL_SUCCESS)
+                {
+                    result = kgsl_mmu_map(mmu, memdesc->gpuaddr, &scatterlist, flags, GSL_CALLER_PROCESSID_GET());
+                    if (result != GSL_SUCCESS)
+                    {
+                        kgsl_hal_freephysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages);
+                    }
+                }
+
+                kos_free(scatterlist.pages);
+            }
+            else
+            {
+                result = GSL_FAILURE;
+            }
+
+            if (result != GSL_SUCCESS)
+            {
+                kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc);
+            }
+        }
+    }
+
+    KGSL_DEBUG_TBDUMP_SETMEM( memdesc->gpuaddr, 0, memdesc->size );
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", result );
+
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_alloc0(device_id, flags, sizebytes, memdesc);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid)
+{
+    int              status = GSL_SUCCESS;
+    int              aperture_index;
+    gsl_deviceid_t   device_id;
+    gsl_sharedmem_t  *shmem;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_free(gsl_memdesc_t *memdesc=%M)\n", memdesc );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+    GSL_MEMDESC_DEVICE_GET(memdesc, device_id);
+
+    shmem = &gsl_driver.shmem;
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            status |= kgsl_mmu_unmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, pid);
+
+            if (!GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+            {
+                status |= kgsl_hal_freephysical(memdesc->gpuaddr, memdesc->size / GSL_PAGESIZE, NULL);
+            }
+        }
+
+        kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc);
+
+        // clear descriptor
+        kos_memset(memdesc, 0, sizeof(gsl_memdesc_t));
+    }
+    else
+    {
+        status = GSL_FAILURE;
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_free. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_free(gsl_memdesc_t *memdesc)
+{
+	int status = GSL_SUCCESS;
+    GSL_API_MUTEX_LOCK();
+    status = kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET());
+    GSL_API_MUTEX_UNLOCK();
+    return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace)
+{
+    int              aperture_index;
+    gsl_sharedmem_t  *shmem;
+    unsigned int     gpuoffsetbytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_read(gsl_memdesc_t *memdesc=%M, void *dst=0x%08x, unsigned int offsetbytes=%d, unsigned int sizebytes=%d)\n",
+                    memdesc, dst, offsetbytes, sizebytes );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+
+    if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE_BADPARAM );
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(dst);
+    KOS_ASSERT(sizebytes);
+
+    if (memdesc->gpuaddr < shmem->apertures[aperture_index].memarena->gpubaseaddr)
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    if (memdesc->gpuaddr + sizebytes > shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes)
+    {
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes;
+
+    GSL_HAL_MEM_READ(dst, shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, sizebytes, touserspace);
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_read0(memdesc, dst, offsetbytes, sizebytes, touserspace);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace)
+{
+    int              aperture_index;
+    gsl_sharedmem_t  *shmem;
+    unsigned int     gpuoffsetbytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_write(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, void *src=0x%08x, unsigned int sizebytes=%d)\n",
+                    memdesc, offsetbytes, src, sizebytes );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+
+    if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE_BADPARAM );
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(src);
+    KOS_ASSERT(sizebytes);
+    KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr);
+    KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes));
+
+    gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes;
+
+    GSL_HAL_MEM_WRITE(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, src, sizebytes, fromuserspace);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMWRITE((memdesc->gpuaddr + offsetbytes), sizebytes, src));
+
+    KGSL_DEBUG_TBDUMP_SYNCMEM( (memdesc->gpuaddr + offsetbytes), src, sizebytes );
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_write0(memdesc, offsetbytes, src, sizebytes, fromuserspace);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes)
+{
+    int              aperture_index;
+    gsl_sharedmem_t  *shmem;
+    unsigned int     gpuoffsetbytes;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_set(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, unsigned int value=0x%08x, unsigned int sizebytes=%d)\n",
+                    memdesc, offsetbytes, value, sizebytes );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+
+    if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE_BADPARAM );
+        return (GSL_FAILURE_BADPARAM);
+    }
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE );
+        return (GSL_FAILURE);
+    }
+
+    KOS_ASSERT(sizebytes);
+    KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr);
+    KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes));
+
+    gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes;
+
+    GSL_HAL_MEM_SET(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, value, sizebytes);
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMSET((memdesc->gpuaddr + offsetbytes), sizebytes, value));
+
+    KGSL_DEBUG_TBDUMP_SETMEM( (memdesc->gpuaddr + offsetbytes), value, sizebytes );
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_SUCCESS );
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes)
+{
+	int status = GSL_SUCCESS;
+	GSL_API_MUTEX_LOCK();
+	status = kgsl_sharedmem_set0(memdesc, offsetbytes, value, sizebytes);
+	GSL_API_MUTEX_UNLOCK();
+	return status;
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API unsigned int
+kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags)
+{
+    gsl_apertureid_t  aperture_id;
+    gsl_channelid_t   channel_id;
+    int               aperture_index;
+    unsigned int      result = 0;
+    gsl_sharedmem_t   *shmem;
+
+    // device_id is ignored at this level, it would be used with per-device memarena's
+
+    // unreferenced formal parameter
+    (void) device_id;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x)\n",
+                    device_id, flags );
+
+    GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id);
+    GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id);
+
+    GSL_API_MUTEX_LOCK();
+
+    shmem = &gsl_driver.shmem;
+
+    if (!(shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" );
+        GSL_API_MUTEX_UNLOCK();
+        kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", 0 );
+        return (0);
+    }
+
+    aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id);
+
+    if (aperture_id == shmem->apertures[aperture_index].id)
+    {
+        result = kgsl_memarena_getlargestfreeblock(shmem->apertures[aperture_index].memarena, flags);
+    }
+
+    GSL_API_MUTEX_UNLOCK();
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", result );
+
+    return (result);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc)
+{
+    int              status = GSL_FAILURE;
+    gsl_sharedmem_t  *shmem = &gsl_driver.shmem;
+    int              aperture_index;
+    gsl_deviceid_t   tmp_id;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_map(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, gsl_scatterlist_t scatterlist=%M, gsl_memdesc_t *memdesc=%M)\n",
+                    device_id, flags, memdesc, scatterlist );
+
+    // execute pending device action
+    tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1;
+    for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++)
+    {
+        if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED)
+        {
+            kgsl_device_runpending(&gsl_driver.device[tmp_id-1]);
+
+            if (tmp_id == device_id)
+            {
+                break;
+            }
+        }
+    }
+
+    // convert any device to an actual existing device
+    if (device_id == GSL_DEVICE_ANY)
+    {
+        for ( ; ; )
+        {
+            device_id++;
+
+            if (device_id <= GSL_DEVICE_MAX)
+            {
+                if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED)
+                {
+                    break;
+                }
+            }
+            else
+            {
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" );
+                kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", GSL_FAILURE );
+                return (GSL_FAILURE);
+            }
+        }
+    }
+
+    KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX);
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        aperture_index = kgsl_sharedmem_getapertureindex(shmem, GSL_APERTURE_EMEM, GSL_CHANNEL_1);
+
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            KOS_ASSERT(scatterlist->num);
+            KOS_ASSERT(scatterlist->pages);
+
+            status = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, scatterlist->num *GSL_PAGESIZE, memdesc);
+            if (status == GSL_SUCCESS)
+            {
+                GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index);
+                GSL_MEMDESC_DEVICE_SET(memdesc, device_id);
+
+                // mark descriptor's memory as externally allocated -- i.e. outside GSL
+                GSL_MEMDESC_EXTALLOC_SET(memdesc, 1);
+
+                status = kgsl_mmu_map(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, scatterlist, flags, GSL_CALLER_PROCESSID_GET());
+                if (status != GSL_SUCCESS)
+                {
+                    kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc);
+                }
+            }
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc)
+{
+    return (kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET()));
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist)
+{
+    int              status = GSL_SUCCESS;
+    int              aperture_index;
+    gsl_deviceid_t   device_id;
+    gsl_sharedmem_t  *shmem;
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE,
+                    "--> int kgsl_sharedmem_getmap(gsl_memdesc_t *memdesc=%M, gsl_scatterlist_t scatterlist=%M)\n",
+                    memdesc, scatterlist );
+
+    GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index);
+    GSL_MEMDESC_DEVICE_GET(memdesc, device_id);
+
+    shmem = &gsl_driver.shmem;
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        KOS_ASSERT(scatterlist->num);
+        KOS_ASSERT(scatterlist->pages);
+        KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr);
+        KOS_ASSERT((memdesc->gpuaddr + memdesc->size) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes));
+
+        kos_memset(scatterlist->pages, 0, sizeof(unsigned int) * scatterlist->num);
+
+        if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena))
+        {
+            status = kgsl_mmu_getmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, scatterlist, GSL_CALLER_PROCESSID_GET());
+        }
+        else
+        {
+            // coalesce physically contiguous pages into a single scatter list entry
+            scatterlist->pages[0]   = memdesc->gpuaddr;
+            scatterlist->contiguous = 1;
+        }
+    }
+
+    kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_getmap. Return value %B\n", status );
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats)
+{
+#ifdef GSL_STATS_MEM
+    int  status = GSL_SUCCESS;
+    int  i;
+
+    KOS_ASSERT(stats);
+
+    if (shmem->flags & GSL_FLAGS_INITIALIZED)
+    {
+        for (i = 0; i < shmem->numapertures; i++)
+        {
+            if (shmem->apertures[i].memarena)
+            {
+                stats->apertures[i].id      = shmem->apertures[i].id;
+                stats->apertures[i].channel = shmem->apertures[i].channel;
+
+                status |= kgsl_memarena_querystats(shmem->apertures[i].memarena, &stats->apertures[i].memarena);
+            }
+        }
+    }
+    else
+    {
+        kos_memset(stats, 0, sizeof(gsl_sharedmem_stats_t));
+    }
+
+    return (status);
+#else
+    // unreferenced formal parameters
+    (void) shmem;
+    (void) stats;
+
+    return (GSL_FAILURE_NOTSUPPORTED);
+#endif // GSL_STATS_MEM
+}
+
+//----------------------------------------------------------------------------
+
+unsigned int
+kgsl_sharedmem_convertaddr(unsigned int addr, int type)
+{
+    gsl_sharedmem_t  *shmem  = &gsl_driver.shmem;
+    unsigned int     cvtaddr = 0;
+    unsigned int     gpubaseaddr, hostbaseaddr, sizebytes;
+    int              i;
+
+    if ((shmem->flags & GSL_FLAGS_INITIALIZED))
+    {
+        for (i = 0; i < shmem->numapertures; i++)
+        {
+            hostbaseaddr = shmem->apertures[i].memarena->hostbaseaddr;
+            gpubaseaddr  = shmem->apertures[i].memarena->gpubaseaddr;
+            sizebytes    = shmem->apertures[i].memarena->sizebytes;
+
+            // convert from gpu to host
+            if (type == 0)
+            {
+                if (addr >= gpubaseaddr && addr < (gpubaseaddr + sizebytes))
+                {
+                    cvtaddr = hostbaseaddr + (addr - gpubaseaddr);
+                    break;
+                }
+            }
+            // convert from host to gpu
+            else if (type == 1)
+            {
+                if (addr >= hostbaseaddr && addr < (hostbaseaddr + sizebytes))
+                {
+                    cvtaddr = gpubaseaddr + (addr - hostbaseaddr);
+                    break;
+                }
+            }
+        }
+    }
+
+    return (cvtaddr);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation)
+{
+    int status  = GSL_FAILURE;
+
+    /* unreferenced formal parameter */
+    (void)memdesc;
+    (void)offsetbytes;
+    (void)sizebytes;
+    (void)operation;
+
+    /* do cache operation */
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+KGSL_API int
+kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr)
+{
+    int status  = GSL_FAILURE;
+
+    memdesc->gpuaddr = (gpuaddr_t)hostptr;  /* map physical address with hostptr    */
+    memdesc->hostptr = hostptr;             /* set virtual address also in memdesc  */
+
+    /* unreferenced formal parameter */
+    (void)device_id;
+
+    return (status);
+}
diff --git a/drivers/mxc/amd-gpu/common/gsl_tbdump.c b/drivers/mxc/amd-gpu/common/gsl_tbdump.c
new file mode 100644
index 00000000000..e22cf894f7b
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_tbdump.c
@@ -0,0 +1,228 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <stdio.h>
+#ifdef WIN32
+#include <windows.h>
+#endif
+#include "gsl.h"
+#include "gsl_tbdump.h"
+#include "kos_libapi.h"
+
+#ifdef TBDUMP
+
+typedef struct TBDump_
+{
+    void* file;
+} TBDump;
+
+
+static TBDump g_tb;
+static oshandle_t tbdump_mutex = 0;
+#define TBDUMP_MUTEX_LOCK() if( tbdump_mutex ) kos_mutex_lock( tbdump_mutex )
+#define TBDUMP_MUTEX_UNLOCK() if( tbdump_mutex ) kos_mutex_unlock( tbdump_mutex )
+
+/* ------------------------------------------------------------------------ */
+/* ------------------------------------------------------------------------ */
+/* ------------------------------------------------------------------------ */
+
+static void tbdump_printline(const char* format, ...)
+{
+    if(g_tb.file)
+    {
+        va_list va;
+        va_start(va, format);
+        vfprintf((FILE*)g_tb.file, format, va);
+        va_end(va);
+        fprintf((FILE*)g_tb.file, "\n");
+    }
+}
+
+static void tbdump_printinfo(const char* message )
+{
+    tbdump_printline("15 %s", message);
+}
+
+static void tbdump_getmemhex(char* buffer, unsigned int addr, unsigned int sizewords)
+{
+    unsigned int i = 0;
+    static const char* hexChars = "0123456789abcdef";
+    unsigned char* ptr = (unsigned char*)addr;
+
+    for (i = 0; i < sizewords; i++)
+    {
+        buffer[(sizewords - i) * 2 - 1] = hexChars[ptr[i] & 0x0f];
+        buffer[(sizewords - i) * 2 - 2] = hexChars[ptr[i] >> 4];
+    }
+    buffer[sizewords * 2] = '\0';
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_open(char* filename)
+{
+    if( !tbdump_mutex ) tbdump_mutex = kos_mutex_create( "TBDUMP_MUTEX" );
+
+    kos_memset( &g_tb, 0, sizeof( g_tb ) );
+
+    g_tb.file = kos_fopen( filename, "wt" );
+
+    tbdump_printinfo("reset");
+    tbdump_printline("0");
+    tbdump_printline("1 00000000 00000eff");
+
+    /* Enable interrupts */
+    tbdump_printline("1 00000000 00000003");
+}
+
+void tbdump_close()
+{
+    TBDUMP_MUTEX_LOCK();
+
+    kos_fclose( g_tb.file );
+    g_tb.file = 0;
+
+    TBDUMP_MUTEX_UNLOCK();
+
+    if( tbdump_mutex ) kos_mutex_free( tbdump_mutex );
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes)
+{
+    /* Align starting address and size */
+    unsigned int beg = addr;
+    unsigned int end = addr+sizebytes;
+    char buffer[65];
+
+    TBDUMP_MUTEX_LOCK();
+
+    beg = (beg+15) & ~15;
+    end &= ~15;
+
+    if( sizebytes <= 16 )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("19 %08x %i 1 %s", addr, sizebytes, buffer);
+
+        TBDUMP_MUTEX_UNLOCK();
+        return;
+    }
+
+    /* Handle unaligned start */
+    if( beg != addr )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("19 %08x %i 1 %s", addr, beg-addr, buffer);
+
+        src += beg-addr;
+    }
+
+    /* Dump the memory writes */
+    while( beg < end )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("2 %08x %s", beg, buffer);
+
+        beg += 16;
+        src += 16;
+    }
+
+    /* Handle unaligned end */
+    if( end != addr+sizebytes )
+    {
+        tbdump_getmemhex(buffer, src, 16);
+
+        tbdump_printline("19 %08x %i 1 %s", end, (addr+sizebytes)-end, buffer);
+    }
+
+    TBDUMP_MUTEX_UNLOCK();
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes)
+{
+    TBDUMP_MUTEX_LOCK();
+
+    tbdump_printline("19 %08x 4 %i %032x", addr, (sizebytes+3)/4, value );
+
+    TBDUMP_MUTEX_UNLOCK();
+}
+
+/* ------------------------------------------------------------------------ */
+
+void tbdump_slavewrite(unsigned int addr, unsigned int value)
+{
+    TBDUMP_MUTEX_LOCK();
+
+    tbdump_printline("1 %08x %08x", addr, value);
+
+    TBDUMP_MUTEX_UNLOCK();
+}
+
+/* ------------------------------------------------------------------------ */
+
+
+KGSL_API int
+kgsl_tbdump_waitirq()
+{
+    if(!g_tb.file) return GSL_FAILURE;
+
+    TBDUMP_MUTEX_LOCK();
+
+    tbdump_printinfo("wait irq");
+    tbdump_printline("10");
+
+    /* ACK IRQ */
+    tbdump_printline("1 00000418 00000003");
+    tbdump_printline("18 00000018 00000000 # slave read & assert");
+
+    TBDUMP_MUTEX_UNLOCK();
+
+    return GSL_SUCCESS;
+}
+
+/* ------------------------------------------------------------------------ */
+
+KGSL_API int
+kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height)
+{
+    static char filename[20];
+    static int numframe = 0;
+
+    if(!g_tb.file) return GSL_FAILURE;
+
+    TBDUMP_MUTEX_LOCK();
+    #pragma warning(disable:4996)
+    sprintf( filename, "tbdump_%08d.bmp", numframe++ );
+
+    tbdump_printline("13 %s %d %08x %d %d %d 0", filename, format, (unsigned int)addr, stride, width, height);
+
+    TBDUMP_MUTEX_UNLOCK();
+
+    return GSL_SUCCESS;
+}
+
+/* ------------------------------------------------------------------------ */
+
+#endif /* TBDUMP */
diff --git a/drivers/mxc/amd-gpu/common/gsl_yamato.c b/drivers/mxc/amd-gpu/common/gsl_yamato.c
new file mode 100644
index 00000000000..07c651f57f4
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/gsl_yamato.c
@@ -0,0 +1,924 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include "gsl.h"
+#include "gsl_hal.h"
+#ifdef _LINUX
+#include <linux/delay.h>
+#include <linux/sched.h>
+#endif
+
+#ifdef GSL_BLD_YAMATO
+
+#include "gsl_ringbuffer.h"
+#include "gsl_drawctxt.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+kgsl_yamato_gmeminit(gsl_device_t *device)
+{
+    rb_edram_info_u rb_edram_info = {0};
+    unsigned int    gmem_size;
+    unsigned int    edram_value = 0;
+
+    // make sure edram range is aligned to size
+    KOS_ASSERT((device->gmemspace.gpu_base  & (device->gmemspace.sizebytes - 1)) == 0);
+
+    // get edram_size value equivalent
+    gmem_size = (device->gmemspace.sizebytes >> 14);
+    while (gmem_size >>= 1)
+    {
+       edram_value++;
+    }
+
+    rb_edram_info.f.edram_size         = edram_value;
+    rb_edram_info.f.edram_mapping_mode = 0;                                     // EDRAM_MAP_UPPER
+    rb_edram_info.f.edram_range        = (device->gmemspace.gpu_base >> 14);    // must be aligned to size
+
+    device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, (unsigned int)rb_edram_info.val);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static int
+kgsl_yamato_gmemclose(gsl_device_t *device)
+{
+    device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, 0x00000000);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_yamato_rbbmintrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_device_t  *device = (gsl_device_t *) cookie;
+
+    switch(id)
+    {
+        // error condition interrupt
+        case GSL_INTR_YDX_RBBM_READ_ERROR:
+	    printk(KERN_ERR "GPU: Z430 RBBM Read Error\n");
+	    schedule_work(&device->irq_err_work);
+            break;
+
+        // non-error condition interrupt
+        case GSL_INTR_YDX_RBBM_DISPLAY_UPDATE:
+        case GSL_INTR_YDX_RBBM_GUI_IDLE:
+
+            kos_event_signal(device->intr.evnt[id]);
+            break;
+
+        default:
+
+            break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+void
+kgsl_yamato_cpintrcallback(gsl_intrid_t id, void *cookie)
+{
+    gsl_device_t  *device = (gsl_device_t *) cookie;
+
+    switch(id)
+    {
+        case GSL_INTR_YDX_CP_RING_BUFFER:
+#ifndef _LINUX		
+              kos_event_signal(device->timestamp_event);
+#else
+			  wake_up_interruptible_all(&(device->timestamp_waitq));
+#endif
+            break;
+        default:
+            break;
+    }
+}
+//----------------------------------------------------------------------------
+
+void
+kgsl_yamato_sqintrcallback(gsl_intrid_t id, void *cookie)
+{
+    (void) cookie;      // unreferenced formal parameter
+	/*gsl_device_t  *device = (gsl_device_t *) cookie;*/
+
+    switch(id)
+    {
+        // error condition interrupt
+        case GSL_INTR_YDX_SQ_PS_WATCHDOG:
+        case GSL_INTR_YDX_SQ_VS_WATCHDOG:
+
+			// todo: take appropriate action
+
+			break;
+
+		default:
+
+			break;
+    }
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef _DEBUG
+
+static int
+kgsl_yamato_bist(gsl_device_t *device)
+{
+    int           status = GSL_FAILURE;
+    unsigned int  link[2];
+
+    if (!(device->flags & GSL_FLAGS_STARTED))
+    {
+        return (GSL_FAILURE);
+    }
+
+    status = kgsl_ringbuffer_bist(&device->ringbuffer);
+    if (status != GSL_SUCCESS)
+    {
+        return (status);
+    }
+
+    // interrupt bist
+    link[0] = pm4_type3_packet(PM4_INTERRUPT, 1);
+    link[1] = CP_INT_CNTL__RB_INT_MASK;
+	kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, GSL_CALLER_PROCESSID_GET());
+
+    status = kgsl_mmu_bist(&device->mmu);
+    if (status != GSL_SUCCESS)
+    {
+        return (status);
+    }
+
+    return (status);
+}
+#endif
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_isr(gsl_device_t *device)
+{
+    unsigned int            status;
+#ifdef _DEBUG
+    mh_mmu_page_fault_u     page_fault        = {0};
+    mh_axi_error_u          axi_error         = {0};
+    mh_clnt_axi_id_reuse_u  clnt_axi_id_reuse = {0};
+    rbbm_read_error_u       read_error        = {0};
+#endif // DEBUG
+
+    // determine if yamato is interrupting, and if so, which block
+    device->ftbl.device_regread(device, mmMASTER_INT_SIGNAL, &status);
+
+    if (status & MASTER_INT_SIGNAL__MH_INT_STAT)
+    {
+#ifdef _DEBUG
+        // obtain mh error information
+        device->ftbl.device_regread(device, mmMH_MMU_PAGE_FAULT, (unsigned int *)&page_fault);
+        device->ftbl.device_regread(device, mmMH_AXI_ERROR, (unsigned int *)&axi_error);
+        device->ftbl.device_regread(device, mmMH_CLNT_AXI_ID_REUSE, (unsigned int *)&clnt_axi_id_reuse);
+#endif // DEBUG
+
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_MH);
+    }
+
+    if (status & MASTER_INT_SIGNAL__CP_INT_STAT)
+    {
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_CP);
+    }
+
+    if (status & MASTER_INT_SIGNAL__RBBM_INT_STAT)
+    {
+#ifdef _DEBUG
+        // obtain rbbm error information
+        device->ftbl.device_regread(device, mmRBBM_READ_ERROR, (unsigned int *)&read_error);
+#endif // DEBUG
+
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_RBBM);
+    }
+
+    if (status & MASTER_INT_SIGNAL__SQ_INT_STAT)
+    {
+        kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_SQ);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid)
+{
+	unsigned int		 link[2];
+    mh_mmu_invalidate_u  mh_mmu_invalidate = {0};
+
+    mh_mmu_invalidate.f.invalidate_all = 1;
+    mh_mmu_invalidate.f.invalidate_tc  = 1;
+
+	// if possible, invalidate via command stream, otherwise via direct register writes
+	if (device->flags & GSL_FLAGS_STARTED)
+	{
+		link[0] = pm4_type0_packet(reg_invalidate, 1);
+		link[1] = mh_mmu_invalidate.val;
+
+		kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, pid);
+	}
+	else
+	{
+
+        device->ftbl.device_regwrite(device, reg_invalidate, mh_mmu_invalidate.val);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid)
+{
+	unsigned int  link[25];
+
+    // if there is an active draw context, set via command stream,
+	if (device->flags & GSL_FLAGS_STARTED)
+    {
+        // wait for graphics pipe to be idle
+        link[0] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+        link[1] = 0x00000000;
+
+        // set page table base
+        link[2] = pm4_type0_packet(reg_ptbase, 1);
+		link[3] = ptbase;
+
+        // HW workaround: to resolve MMU page fault interrupts caused by the VGT. It prevents 
+		// the CP PFP from filling the VGT DMA request fifo too early, thereby ensuring that 
+		// the VGT will not fetch vertex/bin data until after the page table base register 
+		// has been updated.
+		//
+		// Two null DRAW_INDX_BIN packets are inserted right after the page table base update, 
+		// followed by a wait for idle. The null packets will fill up the VGT DMA request 
+		// fifo and prevent any further vertex/bin updates from occurring until the wait 
+		// has finished.
+		link[4]  = pm4_type3_packet(PM4_SET_CONSTANT, 2);
+		link[5]  = (0x4 << 16) | (mmPA_SU_SC_MODE_CNTL - 0x2000);
+		link[6]  = 0;          // disable faceness generation
+		link[7]  = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1);
+		link[8]  = device->mmu.dummyspace.gpuaddr;
+		link[9]  = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6);
+		link[10] = 0;          // viz query info
+		link[11] = 0x0003C004; // draw indicator
+		link[12] = 0;          // bin base
+		link[13] = 3;          // bin size
+		link[14] = device->mmu.dummyspace.gpuaddr; // dma base
+		link[15] = 6;          // dma size
+		link[16] = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6);
+		link[17] = 0;          // viz query info
+		link[18] = 0x0003C004; // draw indicator
+		link[19] = 0;          // bin base
+		link[20] = 3;          // bin size
+		link[21] = device->mmu.dummyspace.gpuaddr; // dma base
+		link[22] = 6;          // dma size
+		link[23] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+		link[24] = 0x00000000;
+
+		kgsl_ringbuffer_issuecmds(device, 1, &link[0], 25, pid);
+	}
+	else
+	{
+		device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+		device->ftbl.device_regwrite(device, reg_ptbase, ptbase);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+static void kgsl_yamato_irqerr(struct work_struct *work)
+{
+	gsl_device_t *device = &gsl_driver.device[GSL_DEVICE_YAMATO-1];
+	device->ftbl.device_destroy(device);
+}
+
+int
+kgsl_yamato_init(gsl_device_t *device)
+{
+    int  status = GSL_FAILURE;
+
+    device->flags |= GSL_FLAGS_INITIALIZED;
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100);
+
+    //We need to make sure all blocks are powered up and clocked before
+    //issuing a soft reset.  The overrides will be turned off (set to 0)
+    //later in kgsl_yamato_start.
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe);
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff);
+
+    // soft reset
+    device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0xFFFFFFFF);
+    kos_sleep(50);
+    device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0x00000000);
+
+    // RBBM control
+    device->ftbl.device_regwrite(device, mmRBBM_CNTL, 0x00004442);
+
+    // setup MH arbiter
+    device->ftbl.device_regwrite(device, mmMH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_yamato_mharb);
+
+    // SQ_*_PROGRAM
+    device->ftbl.device_regwrite(device, mmSQ_VS_PROGRAM, 0x00000000);
+    device->ftbl.device_regwrite(device, mmSQ_PS_PROGRAM, 0x00000000);
+
+    // init interrupt
+    status = kgsl_intr_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    // init mmu
+    status = kgsl_mmu_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    /* handle error condition */
+    INIT_WORK(&device->irq_err_work, kgsl_yamato_irqerr);
+
+    return(status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_close(gsl_device_t *device)
+{
+    if (device->refcnt == 0)
+    {
+        // shutdown mmu
+        kgsl_mmu_close(device);
+
+        // shutdown interrupt
+        kgsl_intr_close(device);
+
+        kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0);
+
+        device->flags &= ~GSL_FLAGS_INITIALIZED;
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_destroy(gsl_device_t *device)
+{
+    int           i;
+    unsigned int  pid;
+
+#ifdef _DEBUG
+    // for now, signal catastrophic failure in a brute force way
+    KOS_ASSERT(0);
+#endif // _DEBUG
+
+    // todo: - hard reset core?
+
+    kgsl_drawctxt_destroyall(device);
+
+    for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++)
+    {
+        pid = device->callerprocess[i];
+        if (pid)
+        {
+            device->ftbl.device_stop(device);
+            kgsl_driver_destroy(pid);
+
+            // todo: terminate client process?
+        }
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_start(gsl_device_t *device, gsl_flags_t flags)
+{
+    int           status = GSL_FAILURE;
+    unsigned int  pm1, pm2;
+
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPFBSTART(device));
+
+    (void) flags;      // unreferenced formal parameter
+
+    kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100);
+
+    // default power management override when running in safe mode
+    pm1 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0xFFFFFFFE : 0x00000000;
+    pm2 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0x000000FF : 0x00000000;
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, pm1);
+    device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, pm2);
+
+    // enable rbbm interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR, kgsl_yamato_rbbmintrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE, kgsl_yamato_rbbmintrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE, kgsl_yamato_rbbmintrcallback, (void *) device);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR);
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE);
+#if defined GSL_RB_TIMESTAMP_INTERUPT	
+	kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_yamato_cpintrcallback, (void *) device);    
+    kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+#endif
+
+  //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE);
+
+    // enable sq interrupts
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device);
+    kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device);
+  //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG);
+  //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG);
+
+    // init gmem
+    kgsl_yamato_gmeminit(device);
+
+    // init ring buffer
+    status = kgsl_ringbuffer_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    // init draw context
+    status = kgsl_drawctxt_init(device);
+    if (status != GSL_SUCCESS)
+    {
+        device->ftbl.device_stop(device);
+        return (status);
+    }
+
+    device->flags |= GSL_FLAGS_STARTED;
+
+    KGSL_DEBUG(GSL_DBGFLAGS_BIST, kgsl_yamato_bist(device));
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_stop(gsl_device_t *device)
+{
+	// HW WORKAROUND: Ringbuffer hangs during next start if it is stopped without any
+	// commands ever being submitted. To avoid this, submit a dummy wait packet.
+	unsigned int cmds[2];
+    cmds[0] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1);
+    cmds[0] = 0;
+	kgsl_ringbuffer_issuecmds(device, 0, cmds, 2, GSL_CALLER_PROCESSID_GET());
+
+    // disable rbbm interrupts
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR);
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE);
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE);
+#if defined GSL_RB_TIMESTAMP_INTERUPT	
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER);
+#endif
+
+    // disable sq interrupts
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG);
+    kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG);
+
+    kgsl_drawctxt_close(device);
+
+    // shutdown ringbuffer
+    kgsl_ringbuffer_close(&device->ringbuffer);
+
+    // shutdown gmem
+    kgsl_yamato_gmemclose(device);
+
+    if(device->refcnt == 0)
+    {
+        kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0);
+    }
+
+    device->flags &= ~GSL_FLAGS_STARTED;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+
+#ifndef _DEBUG
+    (void) sizebytes;       // unreferenced formal parameter
+#endif
+
+    if (type == GSL_PROP_DEVICE_INFO)
+    {
+        gsl_devinfo_t  *devinfo = (gsl_devinfo_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t));
+
+        devinfo->device_id         = device->id;
+        devinfo->chip_id           = (gsl_chipid_t)device->chip_id;
+        devinfo->mmu_enabled       = kgsl_mmu_isenabled(&device->mmu);
+        devinfo->gmem_hostbaseaddr = device->gmemspace.mmio_virt_base;
+        devinfo->gmem_gpubaseaddr  = device->gmemspace.gpu_base;
+        devinfo->gmem_sizebytes    = device->gmemspace.sizebytes;
+	devinfo->high_precision    = 0;
+
+        status = GSL_SUCCESS;
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes)
+{
+    int  status = GSL_FAILURE;
+
+#ifndef _DEBUG
+    (void) sizebytes;           // unreferenced formal parameter
+#endif
+
+    if (type == GSL_PROP_DEVICE_POWER)
+    {
+        gsl_powerprop_t  *power = (gsl_powerprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t));
+
+        if (!(device->flags & GSL_FLAGS_SAFEMODE))
+        {
+            if (power->flags & GSL_PWRFLAGS_OVERRIDE_ON)
+            {
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe);
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff);
+            }
+            else if (power->flags & GSL_PWRFLAGS_OVERRIDE_OFF)
+            {
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0x00000000);
+                device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0x00000000);
+            }
+            else
+            {
+                kgsl_hal_setpowerstate(device->id, power->flags, power->value);
+            }
+        }
+
+        status = GSL_SUCCESS;
+    }
+    else if (type == GSL_PROP_DEVICE_DMI)
+    {
+        gsl_dmiprop_t  *dmi = (gsl_dmiprop_t *) value;
+
+        KOS_ASSERT(sizebytes == sizeof(gsl_dmiprop_t));
+
+        //
+        //  In order to enable DMI, it must not already be enabled.
+        //
+        switch (dmi->flags)
+        {
+            case GSL_DMIFLAGS_ENABLE_SINGLE:
+            case GSL_DMIFLAGS_ENABLE_DOUBLE:
+                if (!gsl_driver.dmi_state)
+                {
+                    gsl_driver.dmi_state = OS_TRUE;
+                    gsl_driver.dmi_mode  = dmi->flags;
+                    gsl_driver.dmi_frame = -1;
+                    status = GSL_SUCCESS;
+                }
+                break;
+            case GSL_DMIFLAGS_DISABLE:
+                //
+                //  To disable, we must be enabled.
+                //
+                if (gsl_driver.dmi_state)
+                {
+                    gsl_driver.dmi_state = OS_FALSE;
+                    gsl_driver.dmi_mode  = -1;
+                    gsl_driver.dmi_frame = -2;
+                    status = GSL_SUCCESS;
+                }
+                break;
+            case GSL_DMIFLAGS_NEXT_BUFFER:
+                //
+                //  Going to the next buffer is dependent upon what mod we are in with respect to single, double, or triple buffering.
+                //  DMI must also be enabled.
+                //
+                if (gsl_driver.dmi_state)
+                {
+                    unsigned int    cmdbuf[10];
+                    unsigned int    *cmds = &cmdbuf[0];
+                    int             size;
+
+                    if (gsl_driver.dmi_frame == -1)
+                    {
+                        size = 8;
+
+                        *cmds++ =  pm4_type0_packet(mmRBBM_DSPLY, 1);
+                        switch (gsl_driver.dmi_mode)
+                        {
+                            case GSL_DMIFLAGS_ENABLE_SINGLE:
+                                gsl_driver.dmi_max_frame = 1;
+                                *cmds++ = 0x041000410;
+                                break;
+                            case GSL_DMIFLAGS_ENABLE_DOUBLE:
+                                gsl_driver.dmi_max_frame = 2;
+                                *cmds++ = 0x041000510;
+                                break;
+                            case GSL_DMIFLAGS_ENABLE_TRIPLE:
+                                gsl_driver.dmi_max_frame = 3;
+                                *cmds++ = 0x041000610;
+                                break;
+                        }
+                    }
+                    else
+                    {
+                        size = 6;
+                    }
+
+
+                    //
+                    //  Wait for 3D core to be idle and wait for vsync
+                    //
+                    *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                    *cmds++ = 0x00008000;           //  3d idle
+                    // *cmds++ = 0x00008008;         //  3d idle & vsync
+
+                    //
+                    //  Update the render latest register.
+                    //
+                    *cmds++ =  pm4_type0_packet(mmRBBM_RENDER_LATEST, 1);
+                    switch (gsl_driver.dmi_frame)
+                    {
+                        case 0:
+                            //
+                            //  Render frame 0
+                            //
+                            *cmds++ = 0;
+                            //
+                            //  Wait for our max frame # indicator to be de-asserted
+                            //
+                            *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                            *cmds++ = 0x00000008 << gsl_driver.dmi_max_frame;
+                            gsl_driver.dmi_frame = 1;
+                            break;
+                        case -1:
+                        case 1:
+                            //
+                            //  Render frame 1
+                            //
+                            *cmds++ = 1;
+                            *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                            *cmds++ = 0x00000010;   //  Wait for frame 0 to be deasserted
+                            gsl_driver.dmi_frame = 2;
+                            break;
+                        case 2:
+                            //
+                            //  Render frame 2
+                            //
+                            *cmds++ = 2;
+                            *cmds++ =  pm4_type0_packet(mmWAIT_UNTIL, 1);
+                            *cmds++ = 0x00000020;   //  Wait for frame 1 to be deasserted
+                            gsl_driver.dmi_frame = 0;
+                            break;
+                    }
+                    
+                    // issue the commands
+                    kgsl_ringbuffer_issuecmds(device, 1, &cmdbuf[0], size, GSL_CALLER_PROCESSID_GET());
+
+                    gsl_driver.dmi_frame %= gsl_driver.dmi_max_frame;
+                    status = GSL_SUCCESS;
+                }
+                break;
+            default:
+                status = GSL_FAILURE;
+                break;
+        }
+    }
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_idle(gsl_device_t *device, unsigned int timeout)
+{
+    int               status  = GSL_FAILURE;
+    gsl_ringbuffer_t  *rb     = &device->ringbuffer;
+    rbbm_status_u     rbbm_status;
+
+    (void) timeout;      // unreferenced formal parameter
+
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_REGPOLL, device->id, mmRBBM_STATUS, 0x80000000, "kgsl_yamato_idle"));
+
+    GSL_RB_MUTEX_LOCK();
+
+    // first, wait until the CP has consumed all the commands in the ring buffer
+    if (rb->flags & GSL_FLAGS_STARTED)
+    {
+        do
+        {
+            GSL_RB_GET_READPTR(rb, &rb->rptr);
+
+        } while (rb->rptr != rb->wptr);
+    }
+
+    // now, wait for the GPU to finish its operations
+    for ( ; ; )
+    {
+        device->ftbl.device_regread(device, mmRBBM_STATUS, (unsigned int *)&rbbm_status);
+
+        if (!(rbbm_status.val & 0x80000000))
+        {
+            status = GSL_SUCCESS;
+            break;
+        }
+
+    }
+	
+    GSL_RB_MUTEX_UNLOCK();
+
+    return (status);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value)
+{
+    KGSL_DEBUG(GSL_DBGFLAGS_DUMPX,
+            {
+                if (!(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX_WITHOUT_IFH))
+                {
+                    if(offsetwords == mmCP_RB_RPTR || offsetwords == mmCP_RB_WPTR)
+                    {
+                        *value = device->ringbuffer.wptr;
+                        return (GSL_SUCCESS);
+                    }
+                }
+            });
+
+    GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value)
+{
+    KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPREGWRITE(offsetwords, value));
+
+    GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value);
+
+    // idle device when running in safe mode
+    if (device->flags & GSL_FLAGS_SAFEMODE)
+    {
+        device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT);
+    }
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout)
+{
+    int  status = GSL_FAILURE_NOTSUPPORTED;
+
+    if (intr_id == GSL_INTR_YDX_CP_IB1_INT || intr_id == GSL_INTR_YDX_CP_IB2_INT ||
+        intr_id == GSL_INTR_YDX_CP_SW_INT  || intr_id == GSL_INTR_YDX_RBBM_DISPLAY_UPDATE)
+    {
+        if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS)
+        {
+            // wait until intr completion event is received
+            if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS)
+            {
+                *count = 1;
+                status = GSL_SUCCESS;
+            }
+            else
+            {
+                status = GSL_FAILURE_TIMEOUT;
+            }
+        }
+    }
+
+    return (status);
+}
+
+int kgsl_yamato_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp)
+{
+	int i;
+	/* Reason to use a wait loop:
+	 * When bus is busy, for example vpu is working too, the timestamp is
+	 * possiblly not yet refreshed to memory by yamato. For most cases, it
+	 * will hit on first loop cycle. So it don't effect performance.
+	 */
+	for (i = 0; i < 10; i++) {
+		if (kgsl_cmdstream_check_timestamp(device_id, timestamp))
+			return 1;
+		udelay(10);
+	}
+	return 0;
+}
+
+int
+kgsl_yamato_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout)
+{
+#if defined GSL_RB_TIMESTAMP_INTERUPT
+#ifndef _LINUX
+	return kos_event_wait( device->timestamp_event, timeout );
+#else
+	int status = wait_event_interruptible_timeout(device->timestamp_waitq,
+							kgsl_yamato_check_timestamp(device->id, timestamp),
+							msecs_to_jiffies(timeout));
+	if (status > 0)
+		return GSL_SUCCESS;
+	else
+		return GSL_FAILURE;
+#endif
+#else
+	return (GSL_SUCCESS);
+#endif
+}
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_runpending(gsl_device_t *device)
+{
+    (void) device;
+
+    return (GSL_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+int
+kgsl_yamato_getfunctable(gsl_functable_t *ftbl)
+{
+    ftbl->device_init           = kgsl_yamato_init;
+    ftbl->device_close          = kgsl_yamato_close;
+    ftbl->device_destroy        = kgsl_yamato_destroy;
+    ftbl->device_start          = kgsl_yamato_start;
+    ftbl->device_stop           = kgsl_yamato_stop;
+    ftbl->device_getproperty    = kgsl_yamato_getproperty;
+    ftbl->device_setproperty    = kgsl_yamato_setproperty;
+    ftbl->device_idle           = kgsl_yamato_idle;
+	ftbl->device_waittimestamp  = kgsl_yamato_waittimestamp;
+    ftbl->device_regread        = kgsl_yamato_regread;
+    ftbl->device_regwrite       = kgsl_yamato_regwrite;
+    ftbl->device_waitirq        = kgsl_yamato_waitirq;
+    ftbl->device_runpending     = kgsl_yamato_runpending;
+    ftbl->intr_isr              = kgsl_yamato_isr;
+    ftbl->mmu_tlbinvalidate     = kgsl_yamato_tlbinvalidate;
+    ftbl->mmu_setpagetable      = kgsl_yamato_setpagetable;
+    ftbl->cmdstream_issueibcmds = kgsl_ringbuffer_issueibcmds;
+    ftbl->context_create        = kgsl_drawctxt_create;
+    ftbl->context_destroy       = kgsl_drawctxt_destroy;
+
+    return (GSL_SUCCESS);
+}
+
+#endif
+
diff --git a/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl
new file mode 100644
index 00000000000..dfe61295e9e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl
@@ -0,0 +1,327 @@
+/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of QUALCOMM Incorporated nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef PFP_MICROCODE_NRT_H
+#define PFP_MICROCODE_NRT_H
+
+#define PFP_MICROCODE_VERSION 308308
+
+#define PFP_MICROCODE_SIZE_NRT 288
+
+uint32 aPFP_Microcode_nrt[PFP_MICROCODE_SIZE_NRT]={
+0xc60400,
+0x7e424b,
+0xa00000,
+0x7e828b,
+0x800001,
+0xc60400,
+0xcc4003,
+0x800000,
+0xd60003,
+0x800000,
+0xc62c00,
+0xc80c35,
+0x98c000,
+0xc80c35,
+0x880000,
+0xc80c1d,
+0x84000b,
+0xc60800,
+0x98c007,
+0xc61000,
+0x978003,
+0xcc4003,
+0xd60004,
+0x800000,
+0xcd0003,
+0x9783e8,
+0xc60400,
+0x800000,
+0xc60400,
+0x84000b,
+0xc60800,
+0x98c00c,
+0xc61000,
+0xcc4003,
+0xc61400,
+0xc61800,
+0x7d6d40,
+0xcd401e,
+0x978003,
+0xcd801e,
+0xd60004,
+0x800000,
+0xcd0003,
+0x800000,
+0xd6001f,
+0x84000b,
+0xc60800,
+0x98c007,
+0xc60c00,
+0xcc4003,
+0xcc8003,
+0xccc003,
+0x800000,
+0xd60003,
+0x800000,
+0xd6001f,
+0xc60800,
+0x348c08,
+0x98c006,
+0xc80c1e,
+0x98c000,
+0xc80c1e,
+0x800041,
+0xcc8007,
+0xcc8008,
+0xcc4003,
+0x800000,
+0xcc8003,
+0xc60400,
+0x1a9c07,
+0xca8821,
+0x95c3b9,
+0xc8102c,
+0x98800a,
+0x329418,
+0x9a4004,
+0xcc6810,
+0x042401,
+0xd00143,
+0xd00162,
+0xcd0002,
+0x7d514c,
+0xcd4003,
+0x9b8007,
+0x06a801,
+0x964003,
+0xc28000,
+0xcf4003,
+0x800001,
+0xc60400,
+0x800045,
+0xc60400,
+0x800001,
+0xc60400,
+0xc60800,
+0xc60c00,
+0xc8102d,
+0x349402,
+0x99000b,
+0xc8182e,
+0xcd4002,
+0xcd8002,
+0xd001e3,
+0xd001c3,
+0xccc003,
+0xcc801c,
+0xcd801d,
+0x800001,
+0xc60400,
+0xd00203,
+0x800000,
+0xd001c3,
+0xc8081f,
+0xc60c00,
+0xc80c20,
+0x988000,
+0xc8081f,
+0xcc4003,
+0xccc003,
+0xd60003,
+0xccc022,
+0xcc001f,
+0x800000,
+0xcc001f,
+0xc81c2f,
+0xc60400,
+0xc60800,
+0xc60c00,
+0xc81030,
+0x99c000,
+0xc81c2f,
+0xcc8021,
+0xcc4020,
+0x990011,
+0xc107ff,
+0xd00223,
+0xd00243,
+0x345402,
+0x7cb18b,
+0x7d95cc,
+0xcdc002,
+0xccc002,
+0xd00263,
+0x978005,
+0xccc003,
+0xc60800,
+0x80008a,
+0xc60c00,
+0x800000,
+0xd00283,
+0x97836b,
+0xc60400,
+0xd6001f,
+0x800001,
+0xc60400,
+0xd2000d,
+0xcc000d,
+0x800000,
+0xcc000d,
+0xc60800,
+0xc60c00,
+0xca1433,
+0xd022a0,
+0xcce000,
+0x99435c,
+0xcce005,
+0x800000,
+0x062001,
+0xc60800,
+0xc60c00,
+0xd202c3,
+0xcc8003,
+0xccc003,
+0xcce027,
+0x800000,
+0x062001,
+0xca0831,
+0x9883ff,
+0xca0831,
+0xd6001f,
+0x800001,
+0xc60400,
+0x0a2001,
+0x800001,
+0xc60400,
+0xd20009,
+0xd2000a,
+0xcc001f,
+0x800000,
+0xcc001f,
+0xd2000b,
+0xd2000c,
+0xcc001f,
+0x800000,
+0xcc001f,
+0xcc0023,
+0xcc4003,
+0xce0003,
+0x800000,
+0xd60003,
+0xd00303,
+0xcc0024,
+0xcc4003,
+0x800000,
+0xd60003,
+0xd00323,
+0xcc0025,
+0xcc4003,
+0x800000,
+0xd60003,
+0xd00343,
+0xcc0026,
+0xcc4003,
+0x800000,
+0xd60003,
+0x800000,
+0xd6001f,
+0x280401,
+0xd20001,
+0xcc4001,
+0xcc4006,
+0x8400e7,
+0xc40802,
+0xc40c02,
+0xcc402b,
+0x98831f,
+0xc63800,
+0x8400e7,
+0xcf802b,
+0x800000,
+0xd6001f,
+0xcc001f,
+0x880000,
+0xcc001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x0100c8,
+0x0200cd,
+0x0300d2,
+0x050004,
+0x1000d7,
+0x1700b6,
+0x220010,
+0x230038,
+0x250044,
+0x27005e,
+0x2d0070,
+0x2e007c,
+0x4b0009,
+0x34001d,
+0x36002d,
+0x3700a8,
+0x3b009b,
+0x3f009f,
+0x4400d9,
+0x4800c3,
+0x5000b9,
+0x5100be,
+0x5500c9,
+0x5600ce,
+0x5700d3,
+0x5d00b0,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+};
+
+#endif
diff --git a/drivers/mxc/amd-gpu/common/pm4_microcode.inl b/drivers/mxc/amd-gpu/common/pm4_microcode.inl
new file mode 100644
index 00000000000..03f6f4cd35e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/common/pm4_microcode.inl
@@ -0,0 +1,815 @@
+/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of QUALCOMM Incorporated nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef PM4_MICROCODE_H
+#define PM4_MICROCODE_H
+
+#define PM4_MICROCODE_VERSION 300684
+
+#define PM4_MICROCODE_SIZE 768
+
+
+#ifdef _PRIMLIB_INCLUDE
+extern uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3];
+#else
+uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x000001f3, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x004 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x34e00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x0000ffff, 0xc0280a20, 0x000 },
+    { 0x00000000, 0x00294582, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x0000ffff, 0xc0284620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a8 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x000021fc, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404803, 0x021 },
+    { 0x00000000, 0x00600000, 0x2a8 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x000021fc, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x0000a1fd, 0x0029462c, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x021 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00001000, 0x00281223, 0x000 },
+    { 0x00001000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x0000000e, 0x00404811, 0x000 },
+    { 0x00000394, 0x00204411, 0x000 },
+    { 0x00000001, 0xc0404811, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a8 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000008, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x14e00000, 0x02d },
+    { 0x00000007, 0x00404811, 0x000 },
+    { 0x00000008, 0x00404811, 0x000 },
+    { 0x0000001f, 0x40280a20, 0x000 },
+    { 0x0000001b, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x043 },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04a },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x051 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x058 },
+    { 0x00000014, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x058 },
+    { 0x00000015, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x060 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0xc0404802, 0x000 },
+    { 0x0000001f, 0x40280a20, 0x000 },
+    { 0x0000001b, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x043 },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04a },
+    { 0x00000000, 0x00400000, 0x051 },
+    { 0x0000001f, 0xc0210e20, 0x000 },
+    { 0x00000612, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001e, 0xc0210e20, 0x000 },
+    { 0x00000600, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001e, 0xc0210e20, 0x000 },
+    { 0x00000605, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001f, 0x40280a20, 0x000 },
+    { 0x0000001f, 0xc0210e20, 0x000 },
+    { 0x0000060a, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000001f, 0xc0680a20, 0x2a8 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00001fff, 0x40280a20, 0x000 },
+    { 0x80000000, 0x40280e20, 0x000 },
+    { 0x40000000, 0xc0281220, 0x000 },
+    { 0x00040000, 0x00694622, 0x2b2 },
+    { 0x00000000, 0x00201410, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x06d },
+    { 0x00000000, 0xc0401800, 0x070 },
+    { 0x00001fff, 0xc0281a20, 0x000 },
+    { 0x00040000, 0x00694626, 0x2b2 },
+    { 0x00000000, 0x00201810, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x073 },
+    { 0x00000000, 0xc0401c00, 0x076 },
+    { 0x00001fff, 0xc0281e20, 0x000 },
+    { 0x00040000, 0x00694627, 0x2b2 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0x002820c5, 0x000 },
+    { 0x00000000, 0x004948e8, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x00000010, 0x40210a20, 0x000 },
+    { 0x000000ff, 0x00280a22, 0x000 },
+    { 0x000007ff, 0x40280e20, 0x000 },
+    { 0x00000002, 0x00221e23, 0x000 },
+    { 0x00000005, 0xc0211220, 0x000 },
+    { 0x00080000, 0x00281224, 0x000 },
+    { 0x00000013, 0x00210224, 0x000 },
+    { 0x00000000, 0x14c00000, 0x084 },
+    { 0xa100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x088 },
+    { 0x00000000, 0x0020162d, 0x000 },
+    { 0x00004000, 0x00500e23, 0x097 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x08c },
+    { 0x00000001, 0x0020162d, 0x000 },
+    { 0x00004800, 0x00500e23, 0x097 },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x090 },
+    { 0x00000003, 0x0020162d, 0x000 },
+    { 0x00004900, 0x00500e23, 0x097 },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x094 },
+    { 0x00000002, 0x0020162d, 0x000 },
+    { 0x00004908, 0x00500e23, 0x097 },
+    { 0x00000012, 0x0020162d, 0x000 },
+    { 0x00002000, 0x00300e23, 0x000 },
+    { 0x00000000, 0x00290d83, 0x000 },
+    { 0x9400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e5, 0x000 },
+    { 0x00000000, 0x00294483, 0x000 },
+    { 0x00000000, 0x40201800, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000013, 0x00210224, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x9400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e5, 0x000 },
+    { 0x9300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404806, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x0000001f, 0x00211a25, 0x000 },
+    { 0x00000000, 0x14e00000, 0x000 },
+    { 0x000007ff, 0x00280e25, 0x000 },
+    { 0x00000010, 0x00211225, 0x000 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0ae },
+    { 0x00000000, 0x00203622, 0x000 },
+    { 0x00004000, 0x00504a23, 0x0bd },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b2 },
+    { 0x00000001, 0x00203622, 0x000 },
+    { 0x00004800, 0x00504a23, 0x0bd },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b6 },
+    { 0x00000003, 0x00203622, 0x000 },
+    { 0x00004900, 0x00504a23, 0x0bd },
+    { 0x00000003, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0ba },
+    { 0x00000002, 0x00203622, 0x000 },
+    { 0x00004908, 0x00504a23, 0x0bd },
+    { 0x00000012, 0x00203622, 0x000 },
+    { 0x00000000, 0x00290d83, 0x000 },
+    { 0x00002000, 0x00304a23, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x0a4 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040578, 0x00604411, 0x2b2 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x00000000, 0xc0201800, 0x000 },
+    { 0x00007f00, 0x00280a21, 0x000 },
+    { 0x00004500, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0cd },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x00000010, 0x00280a23, 0x000 },
+    { 0x00000010, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d5 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0x00694624, 0x2b2 },
+    { 0x00000000, 0x00400000, 0x0d6 },
+    { 0x00000000, 0x00600000, 0x135 },
+    { 0x00000000, 0x002820d0, 0x000 },
+    { 0x00000007, 0x00280a23, 0x000 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0dd },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x04e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000002, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0e2 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x02e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0e7 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0ec },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000005, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0f1 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x06e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00000006, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0f6 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x08e00000, 0x0f6 },
+    { 0x00000000, 0x00400000, 0x0fd },
+    { 0x00007f00, 0x00280a21, 0x000 },
+    { 0x00004500, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x000 },
+    { 0x00000008, 0x00210a23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x11b },
+    { 0x00000000, 0xc0204400, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00007f00, 0x00280a21, 0x000 },
+    { 0x00004500, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x102 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x00404c07, 0x0cd },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x00000000, 0xc0201800, 0x000 },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0x00694624, 0x2b2 },
+    { 0x00000000, 0x002820d0, 0x000 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00404c07, 0x107 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x00000000, 0xc0201400, 0x000 },
+    { 0x00000000, 0xc0201800, 0x000 },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0x00694624, 0x2b2 },
+    { 0x00000000, 0x002820d0, 0x000 },
+    { 0x00000000, 0x002f00a8, 0x000 },
+    { 0x00000000, 0x06e00000, 0x000 },
+    { 0x00000000, 0x00404c07, 0x113 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000860e, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000009, 0x00204811, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x00404810, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00007fff, 0x00281a22, 0x000 },
+    { 0x00040000, 0x00694626, 0x2b2 },
+    { 0x00000000, 0x00200c10, 0x000 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x80000000, 0x00281a22, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x132 },
+    { 0x00000000, 0x00600000, 0x135 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x00300c67, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0xa400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x000001ea, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x13b },
+    { 0x9e00ffff, 0x00204411, 0x000 },
+    { 0xdeadbeef, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x13e },
+    { 0xa400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x0080480b, 0x000 },
+    { 0x000001f3, 0x00204411, 0x000 },
+    { 0xe0000000, 0xc0484a20, 0x000 },
+    { 0x00000000, 0xd9000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x8c00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000fff, 0x00281223, 0x000 },
+    { 0x0000000f, 0x00203624, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000e, 0x00203624, 0x000 },
+    { 0x8700ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000001, 0x00331224, 0x000 },
+    { 0x8600ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x0000001d, 0x00211223, 0x000 },
+    { 0x00000020, 0x00222091, 0x000 },
+    { 0x00000003, 0x00381228, 0x000 },
+    { 0x8800ffff, 0x00204411, 0x000 },
+    { 0x00004fff, 0x00304a24, 0x000 },
+    { 0x00000010, 0x00211623, 0x000 },
+    { 0x00000fff, 0x00281625, 0x000 },
+    { 0x00000fff, 0x00281a23, 0x000 },
+    { 0x00000000, 0x00331ca6, 0x000 },
+    { 0x8f00ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00000010, 0x00211223, 0x000 },
+    { 0x00000fff, 0x00281224, 0x000 },
+    { 0x0000000d, 0x00203624, 0x000 },
+    { 0x8b00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000c, 0x00203624, 0x000 },
+    { 0x8500ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00331cc8, 0x000 },
+    { 0x9000ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00300000, 0x00493a2e, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000001, 0x00303e2f, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x172 },
+    { 0x00000000, 0xd9000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x175 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000009, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x17d },
+    { 0x00000000, 0x00600000, 0x2af },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000016, 0x00203623, 0x000 },
+    { 0x00000000, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x180 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x183 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000002, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x18d },
+    { 0x00000004, 0xc0203620, 0x000 },
+    { 0x00000005, 0xc0203620, 0x000 },
+    { 0x00000006, 0xc0203620, 0x000 },
+    { 0x00000007, 0xc0203620, 0x000 },
+    { 0x00000008, 0xc0203620, 0x000 },
+    { 0x00000009, 0xc0203620, 0x000 },
+    { 0x0000000a, 0xc0203620, 0x000 },
+    { 0x0000000b, 0xc0203620, 0x000 },
+    { 0x00000003, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1b5 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x8c00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000fff, 0x00281223, 0x000 },
+    { 0x0000000f, 0x00203624, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000e, 0x00203624, 0x000 },
+    { 0x8700ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000001, 0x00331224, 0x000 },
+    { 0x8600ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x0000001d, 0x00211223, 0x000 },
+    { 0x00000020, 0x00222091, 0x000 },
+    { 0x00000003, 0x00381228, 0x000 },
+    { 0x8800ffff, 0x00204411, 0x000 },
+    { 0x00004fff, 0x00304a24, 0x000 },
+    { 0x00000010, 0x00211623, 0x000 },
+    { 0x00000fff, 0x00281625, 0x000 },
+    { 0x00000fff, 0x00281a23, 0x000 },
+    { 0x00000000, 0x00331ca6, 0x000 },
+    { 0x8f00ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00000010, 0x00211223, 0x000 },
+    { 0x00000fff, 0x00281224, 0x000 },
+    { 0x0000000d, 0x00203624, 0x000 },
+    { 0x8b00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00301224, 0x000 },
+    { 0x0000000c, 0x00203624, 0x000 },
+    { 0x8500ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00331cc8, 0x000 },
+    { 0x9000ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a27, 0x000 },
+    { 0x00300000, 0x00293a2e, 0x000 },
+    { 0x00000004, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1bd },
+    { 0xa300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x0000000a, 0xc0220e20, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x000021f4, 0x00204411, 0x000 },
+    { 0x0000000a, 0x00614a2c, 0x2af },
+    { 0x00000005, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1c0 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000006, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1c6 },
+    { 0x9c00ffff, 0x00204411, 0x000 },
+    { 0x0000001f, 0x40214a20, 0x000 },
+    { 0x9600ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000007, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1d0 },
+    { 0x3fffffff, 0x00283a2e, 0x000 },
+    { 0xc0000000, 0x40280e20, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x18000000, 0x40280e20, 0x000 },
+    { 0x00000016, 0x00203623, 0x000 },
+    { 0xa400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0202c00, 0x000 },
+    { 0x00000000, 0x0020480b, 0x000 },
+    { 0x00000008, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1dc },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000015, 0x00203623, 0x000 },
+    { 0x00000002, 0x40221220, 0x000 },
+    { 0x00000000, 0x00301083, 0x000 },
+    { 0x00000014, 0x00203624, 0x000 },
+    { 0x00000003, 0xc0210e20, 0x000 },
+    { 0x10000000, 0x00280e23, 0x000 },
+    { 0xefffffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14e00000, 0x000 },
+    { 0x000003ff, 0x00280e22, 0x000 },
+    { 0x00000018, 0x00211222, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x0020108d, 0x000 },
+    { 0x00002000, 0x00291224, 0x000 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00294984, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x00000000, 0x00400000, 0x1de },
+    { 0x8200ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00003fff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x1fb },
+    { 0x00000000, 0x2ae00000, 0x205 },
+    { 0x20000080, 0x00281e2e, 0x000 },
+    { 0x00000080, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1f8 },
+    { 0x00000000, 0x00401c0c, 0x1f9 },
+    { 0x00000010, 0x00201e2d, 0x000 },
+    { 0x000021f9, 0x00294627, 0x000 },
+    { 0x00000000, 0x00404811, 0x205 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x23a },
+    { 0x00000000, 0x28e00000, 0x205 },
+    { 0x00800080, 0x00281e2e, 0x000 },
+    { 0x00000080, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x202 },
+    { 0x00000000, 0x00401c0c, 0x203 },
+    { 0x00000010, 0x00201e2d, 0x000 },
+    { 0x000021f9, 0x00294627, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x20c },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000000c, 0x0020162d, 0x000 },
+    { 0x0000000d, 0x00201a2d, 0x000 },
+    { 0xffdfffff, 0x00483a2e, 0x210 },
+    { 0x00000004, 0x00204811, 0x000 },
+    { 0x0000000e, 0x0020162d, 0x000 },
+    { 0x0000000f, 0x00201a2d, 0x000 },
+    { 0xffefffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x002f0067, 0x000 },
+    { 0x00000000, 0x04e00000, 0x205 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x8900ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x00000000, 0x00601010, 0x28c },
+    { 0x0000000c, 0x00221e24, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x22d },
+    { 0x20000000, 0x00293a2e, 0x000 },
+    { 0x000021f7, 0x0029462c, 0x000 },
+    { 0x00000000, 0x002948c7, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00203630, 0x000 },
+    { 0x00000007, 0x00204811, 0x000 },
+    { 0x0000000d, 0x00203630, 0x000 },
+    { 0x9100ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x23000000, 0x000 },
+    { 0x8d00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x240 },
+    { 0x00800000, 0x00293a2e, 0x000 },
+    { 0x000021f6, 0x0029462c, 0x000 },
+    { 0x00000000, 0x002948c7, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000000e, 0x00203630, 0x000 },
+    { 0x00000007, 0x00204811, 0x000 },
+    { 0x0000000f, 0x00203630, 0x000 },
+    { 0x9200ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x25000000, 0x000 },
+    { 0x8e00ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x240 },
+    { 0x8300ffff, 0x00204411, 0x000 },
+    { 0x00000003, 0x00381224, 0x000 },
+    { 0x00005000, 0x00304a24, 0x000 },
+    { 0x8400ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x21000000, 0x000 },
+    { 0x8200ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000003, 0x40280a20, 0x000 },
+    { 0xffffffe0, 0xc0280e20, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x24a },
+    { 0x000021f6, 0x0029122c, 0x000 },
+    { 0x00040000, 0x00494624, 0x24c },
+    { 0x000021f7, 0x0029122c, 0x000 },
+    { 0x00040000, 0x00294624, 0x000 },
+    { 0x00000000, 0x00600000, 0x2b2 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x252 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x252 },
+    { 0x00000000, 0x00481630, 0x258 },
+    { 0x00000fff, 0x00281630, 0x000 },
+    { 0x0000000c, 0x00211a30, 0x000 },
+    { 0x00000fff, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x258 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00040d02, 0x00604411, 0x2b2 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x25d },
+    { 0x00000010, 0x00211e30, 0x000 },
+    { 0x00000fff, 0x00482630, 0x267 },
+    { 0x00000001, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x261 },
+    { 0x00000fff, 0x00281e30, 0x000 },
+    { 0x00000200, 0x00402411, 0x267 },
+    { 0x00000000, 0x00281e30, 0x000 },
+    { 0x00000010, 0x00212630, 0x000 },
+    { 0x00000010, 0x00211a30, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x258 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000003, 0x00381625, 0x000 },
+    { 0x00000003, 0x00381a26, 0x000 },
+    { 0x00000003, 0x00381e27, 0x000 },
+    { 0x00000003, 0x00382629, 0x000 },
+    { 0x00005000, 0x00302629, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00005000, 0x00302225, 0x000 },
+    { 0x00040000, 0x00694628, 0x2b2 },
+    { 0x00000001, 0x00302228, 0x000 },
+    { 0x00000000, 0x00202810, 0x000 },
+    { 0x00040000, 0x00694628, 0x2b2 },
+    { 0x00000001, 0x00302228, 0x000 },
+    { 0x00000000, 0x00200810, 0x000 },
+    { 0x00040000, 0x00694628, 0x2b2 },
+    { 0x00000001, 0x00302228, 0x000 },
+    { 0x00000000, 0x00201410, 0x000 },
+    { 0x0000060d, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x0000860e, 0x00204411, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x002f0128, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x282 },
+    { 0x00005000, 0x00302227, 0x000 },
+    { 0x0000000c, 0x00300e23, 0x000 },
+    { 0x00000003, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x270 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x000001f3, 0x00204411, 0x000 },
+    { 0x04000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x289 },
+    { 0x00000000, 0xc0600000, 0x28c },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0x0ec00000, 0x28e },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x000021f9, 0x0029462c, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x00000000, 0x0020280c, 0x000 },
+    { 0x00000011, 0x0020262d, 0x000 },
+    { 0x00000000, 0x002f012c, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x295 },
+    { 0x00000000, 0x00403011, 0x296 },
+    { 0x00000400, 0x0030322c, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x0000000a, 0x0021262c, 0x000 },
+    { 0x00000000, 0x00210130, 0x000 },
+    { 0x00000000, 0x14c00000, 0x29d },
+    { 0xa500ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00404811, 0x299 },
+    { 0xa500ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x000021f4, 0x0029462c, 0x000 },
+    { 0x0000000a, 0x00214a2a, 0x000 },
+    { 0xa200ffff, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x00000000, 0x00210130, 0x000 },
+    { 0xdf7fffff, 0x00283a2e, 0x000 },
+    { 0x00000010, 0x0080362a, 0x000 },
+    { 0x9700ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x0020480c, 0x000 },
+    { 0xa200ffff, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8100ffff, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x00000000, 0x00810130, 0x000 },
+    { 0x00000000, 0x00203011, 0x000 },
+    { 0x00000010, 0x0080362c, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x2b2 },
+    { 0x9f00ffff, 0x00204411, 0x000 },
+    { 0xdeadbeef, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x2b5 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00020143, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x01dd0002, 0x000 },
+    { 0x006301ee, 0x00280012, 0x000 },
+    { 0x00020002, 0x00020026, 0x000 },
+    { 0x00020002, 0x01ec0002, 0x000 },
+    { 0x00790242, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00200012, 0x00020016, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x011b00c5, 0x00020125, 0x000 },
+    { 0x00020141, 0x00020002, 0x000 },
+    { 0x00c50002, 0x0143002e, 0x000 },
+    { 0x00a2016b, 0x00020145, 0x000 },
+    { 0x00020002, 0x01200002, 0x000 },
+    { 0x00020002, 0x010f0103, 0x000 },
+    { 0x00090002, 0x000e000e, 0x000 },
+    { 0x0058003d, 0x00600002, 0x000 },
+    { 0x000200c1, 0x0002028a, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x00020002, 0x00020002, 0x000 },
+    { 0x000502b1, 0x00020008, 0x000 },
+};
+
+#endif
+static const uint32 ME_JUMP_TABLE_START = 740;
+static const uint32 ME_JUMP_TABLE_END   = 768;
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h
new file mode 100644
index 00000000000..7ec10b0c255
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h
@@ -0,0 +1,86 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+	
+#ifndef __GSL_DISPLAYAPI_H
+#define __GSL_DISPLAYAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+//////////////////////////////////////////////////////////////////////////////
+//  entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __GSLDISPLAY_EXPORTS
+#define DISP_API                    OS_DLLEXPORT
+#else
+#define DISP_API                    OS_DLLIMPORT
+#endif // __GSLDISPLAY_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_DISPLAY_PANEL_TOSHIBA_640x480     0
+#define GSL_DISPLAY_PANEL_HITACHI_240x320     1
+#define GSL_DISPLAY_PANEL_DEFAULT             GSL_DISPLAY_PANEL_TOSHIBA_640x480
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+typedef int     gsl_display_id_t;
+typedef int     gsl_surface_id_t;
+
+typedef struct _gsl_displaymode_t {
+    int panel_id;
+    int width;
+    int height;
+    int bpp;
+    int orientation;
+    int frequency;
+} gsl_displaymode_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+DISP_API gsl_display_id_t   gsl_display_open(gsl_devhandle_t devhandle, int panel_id);
+DISP_API int                gsl_display_close(gsl_display_id_t display_id);
+DISP_API int                gsl_display_getcount(void);
+DISP_API int                gsl_display_setmode(gsl_display_id_t display_id, gsl_displaymode_t displaymode);
+DISP_API int                gsl_display_getmode(gsl_display_id_t display_id, gsl_displaymode_t *displaymode);
+DISP_API gsl_surface_id_t   gsl_display_setsurface(gsl_display_id_t display_id, void *buffer);
+DISP_API int                gsl_display_getactivesurface(gsl_display_id_t display_id, void **buffer);
+DISP_API int                gsl_display_flipsurface(gsl_display_id_t display_id, gsl_surface_id_t surface_id);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __GSL_DISPLAYAPI_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h
new file mode 100644
index 00000000000..c8831840ad1
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h
@@ -0,0 +1,136 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_KLIBAPI_H
+#define __GSL_KLIBAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "gsl_types.h"
+#include "gsl_properties.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __KGSLLIB_EXPORTS
+#define KGSL_API                    OS_DLLEXPORT
+#else
+#ifdef __KERNEL_MODE__
+#define KGSL_API                    extern
+#else
+#define KGSL_API                    OS_DLLIMPORT
+#endif
+#endif // __KGSLLIB_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  version control                    
+//////////////////////////////////////////////////////////////////////////////
+#define KGSLLIB_NAME            "AMD GSL Kernel Library"
+#define KGSLLIB_VERSION         "0.1"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  library API
+//////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_driver_init(void);
+KGSL_API int                kgsl_driver_close(void);
+KGSL_API int                kgsl_driver_entry(gsl_flags_t flags);
+KGSL_API int                kgsl_driver_exit(void);
+KGSL_API int                kgsl_driver_destroy(unsigned int pid);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  device API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags);
+KGSL_API int                kgsl_device_stop(gsl_deviceid_t device_id);
+KGSL_API int                kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout);
+KGSL_API int                kgsl_device_isidle(gsl_deviceid_t device_id);
+KGSL_API int                kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes);
+KGSL_API int                kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes);
+KGSL_API int                kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value);
+KGSL_API int                kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value);
+KGSL_API int                kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  command API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+KGSL_API gsl_timestamp_t    kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type);
+KGSL_API int                kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type);
+KGSL_API int                kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout);
+KGSL_API int                kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data);
+KGSL_API int                kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp);
+KGSL_API int                kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp);
+
+////////////////////////////////////////////////////////////////////////////
+//  context API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+KGSL_API int                kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id);
+KGSL_API int                kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  sharedmem API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_free(gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace);
+KGSL_API int                kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace);
+KGSL_API int                kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes);
+KGSL_API unsigned int       kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags);
+KGSL_API int                kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc);
+KGSL_API int                kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist);
+KGSL_API int                kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation);
+KGSL_API int                kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  interrupt API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API void               kgsl_intr_isr(gsl_device_t *device);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  TB dump API
+////////////////////////////////////////////////////////////////////////////
+KGSL_API int                kgsl_tbdump_waitirq(void);
+KGSL_API int                kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif  // __GSL_KLIBAPI_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_libapi.h b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h
new file mode 100644
index 00000000000..3d359e24f57
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h
@@ -0,0 +1,143 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_LIBAPI_H
+#define __GSL_LIBAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "gsl_types.h"
+
+//////////////////////////////////////////////////////////////////////////////
+//  entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __GSLLIB_EXPORTS
+#define GSL_API                 OS_DLLEXPORT
+#else
+#define GSL_API                 OS_DLLIMPORT
+#endif // __GSLLIB_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSLLIB_NAME            "AMD GSL User Library"
+#define GSLLIB_VERSION         "0.1"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  libary API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_library_open(gsl_flags_t flags);
+GSL_API int                     gsl_library_close(void);
+
+
+////////////////////////////////////////////////////////////////////////////
+//  device API
+////////////////////////////////////////////////////////////////////////////
+GSL_API gsl_devhandle_t         gsl_device_open(gsl_deviceid_t device_id, gsl_flags_t flags);
+GSL_API int                     gsl_device_close(gsl_devhandle_t devhandle);
+GSL_API int                     gsl_device_idle(gsl_devhandle_t devhandle, unsigned int timeout);
+GSL_API int                     gsl_device_isidle(gsl_devhandle_t devhandle);
+GSL_API int                     gsl_device_getcount(void);
+GSL_API int                     gsl_device_getinfo(gsl_devhandle_t devhandle, gsl_devinfo_t *devinfo);
+GSL_API int                     gsl_device_setpowerstate(gsl_devhandle_t devhandle, gsl_flags_t flags);
+GSL_API int                     gsl_device_setdmistate(gsl_devhandle_t devhandle,  gsl_flags_t flags);
+GSL_API int                     gsl_device_waitirq(gsl_devhandle_t devhandle, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout);
+GSL_API int                     gsl_device_waittimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, unsigned int timeout);
+GSL_API int                     gsl_device_addtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t *timestamp);
+
+//////////////////////////////////////////////////////////////////////////////
+//  direct register API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_register_read(gsl_devhandle_t devhandle, unsigned int offsetwords, unsigned int *data);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  command API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_cp_issueibcommands(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, gpuaddr_t ibaddr, unsigned int sizewords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+GSL_API gsl_timestamp_t         gsl_cp_readtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_type_t type);
+GSL_API int                     gsl_cp_checktimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, gsl_timestamp_type_t type);
+GSL_API int                     gsl_cp_freememontimestamp(gsl_devhandle_t devhandle, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type);
+GSL_API int                     gsl_v3_issuecommand(gsl_devhandle_t devhandle, gsl_cmdwindow_t target, unsigned int addr, unsigned int data);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  context API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API gsl_ctxthandle_t        gsl_context_create(gsl_devhandle_t devhandle, gsl_context_type_t type, gsl_flags_t flags);
+GSL_API int                     gsl_context_destroy(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle);
+GSL_API int                     gsl_context_bind_gmem_shadow(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id);
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  sharedmem API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_memory_alloc(gsl_deviceid_t device_id, unsigned int sizebytes, gsl_flags_t flags, gsl_memdesc_t *memdesc);
+GSL_API int                     gsl_memory_free(gsl_memdesc_t *memdesc);
+GSL_API int                     gsl_memory_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int sizebytes, unsigned int offsetbytes);
+GSL_API int                     gsl_memory_write(const gsl_memdesc_t *memdesc, void *src, unsigned int sizebytes, unsigned int offsetbytes);
+GSL_API int                     gsl_memory_write_multiple(const gsl_memdesc_t *memdesc, void *src, unsigned int srcstridebytes, unsigned int dststridebytes, unsigned int blocksizebytes, unsigned int numblocks, unsigned int offsetbytes);
+GSL_API unsigned int            gsl_memory_getlargestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags);
+GSL_API int                     gsl_memory_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes);
+GSL_API int                     gsl_memory_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation);
+GSL_API int                     gsl_memory_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr);
+
+#ifdef _DIRECT_MAPPED
+GSL_API unsigned int            gsl_sharedmem_gethostaddr(const gsl_memdesc_t *memdesc);
+#endif // _DIRECT_MAPPED
+
+//////////////////////////////////////////////////////////////////////////////
+//  address translation API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_translate_physaddr(void* virtAddr, unsigned int* physAddr);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  TB dump API
+//////////////////////////////////////////////////////////////////////////////
+GSL_API int                     gsl_tbdump_waitirq();
+GSL_API int                     gsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height);
+
+//////////////////////////////////////////////////////////////////////////////
+//  OS specific APIs - need to go into their own gsl_libapi_platform.h file
+//////////////////////////////////////////////////////////////////////////////
+#ifdef WM7
+GSL_API int                     gsl_kos_wm7_surfobjfromhbitmap(HBITMAP hbitmap, SURFOBJ *surfobj);
+#endif // WM7
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif  // __GSL_LIBAPI_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h
new file mode 100644
index 00000000000..891c7b645ad
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h
@@ -0,0 +1,157 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_PM4TYPES_H
+#define __GSL_PM4TYPES_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet mask
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_PKT_MASK                0xc0000000
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet types
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_TYPE0_PKT               ((unsigned int)0 << 30)
+#define PM4_TYPE1_PKT               ((unsigned int)1 << 30)
+#define PM4_TYPE2_PKT               ((unsigned int)2 << 30)
+#define PM4_TYPE3_PKT               ((unsigned int)3 << 30)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// type3 packets
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_ME_INIT                 0x48    // initialize CP's micro-engine
+
+#define PM4_NOP                     0x10    // skip N 32-bit words to get to the next packet
+
+#define PM4_INDIRECT_BUFFER         0x3f    // indirect buffer dispatch.  prefetch parser uses this packet type to determine whether to pre-fetch the IB
+#define PM4_INDIRECT_BUFFER_PFD     0x37    // indirect buffer dispatch.  same as IB, but init is pipelined
+
+#define PM4_WAIT_FOR_IDLE           0x26    // wait for the IDLE state of the engine
+#define PM4_WAIT_REG_MEM            0x3c    // wait until a register or memory location is a specific value
+#define PM4_WAIT_REG_EQ             0x52    // wait until a register location is equal to a specific value
+#define PM4_WAT_REG_GTE             0x53    // wait until a register location is >= a specific value
+#define PM4_WAIT_UNTIL_READ         0x5c    // wait until a read completes
+#define PM4_WAIT_IB_PFD_COMPLETE    0x5d    // wait until all base/size writes from an IB_PFD packet have completed
+
+#define PM4_REG_RMW                 0x21    // register read/modify/write
+#define PM4_REG_TO_MEM              0x3e    // reads register in chip and writes to memory
+#define PM4_MEM_WRITE               0x3d    // write N 32-bit words to memory
+#define PM4_MEM_WRITE_CNTR          0x4f    // write CP_PROG_COUNTER value to memory
+#define PM4_COND_EXEC               0x44    // conditional execution of a sequence of packets
+#define PM4_COND_WRITE              0x45    // conditional write to memory or register
+
+#define PM4_EVENT_WRITE             0x46    // generate an event that creates a write to memory when completed
+#define PM4_EVENT_WRITE_SHD         0x58    // generate a VS|PS_done event
+#define PM4_EVENT_WRITE_CFL         0x59    // generate a cache flush done event
+#define PM4_EVENT_WRITE_ZPD         0x5b    // generate a z_pass done event
+
+#define PM4_DRAW_INDX               0x22    // initiate fetch of index buffer and draw
+#define PM4_DRAW_INDX_2             0x36    // draw using supplied indices in packet
+#define PM4_DRAW_INDX_BIN           0x34    // initiate fetch of index buffer and binIDs and draw
+#define PM4_DRAW_INDX_2_BIN         0x35    // initiate fetch of bin IDs and draw using supplied indices
+
+#define PM4_VIZ_QUERY               0x23    // begin/end initiator for viz query extent processing
+#define PM4_SET_STATE               0x25    // fetch state sub-blocks and initiate shader code DMAs
+#define PM4_SET_CONSTANT            0x2d    // load constant into chip and to memory
+#define PM4_IM_LOAD                 0x27    // load sequencer instruction memory (pointer-based)
+#define PM4_IM_LOAD_IMMEDIATE       0x2b    // load sequencer instruction memory (code embedded in packet)
+#define PM4_LOAD_CONSTANT_CONTEXT   0x2e    // load constants from a location in memory
+#define PM4_INVALIDATE_STATE        0x3b    // selective invalidation of state pointers
+
+#define PM4_SET_SHADER_BASES        0x4A    // dynamically changes shader instruction memory partition
+#define PM4_SET_BIN_BASE_OFFSET     0x4B    // program an offset that will added to the BIN_BASE value of the 3D_DRAW_INDX_BIN packet
+#define PM4_SET_BIN_MASK            0x50    // sets the 64-bit BIN_MASK register in the PFP
+#define PM4_SET_BIN_SELECT          0x51    // sets the 64-bit BIN_SELECT register in the PFP
+
+#define PM4_CONTEXT_UPDATE          0x5e    // updates the current context, if needed
+#define PM4_INTERRUPT               0x40    // generate interrupt from the command stream
+
+#define PM4_IM_STORE                0x2c    // copy sequencer instruction memory to system memory
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet header building macros
+//////////////////////////////////////////////////////////////////////////////
+#define pm4_type0_packet(regindx, cnt)                      (PM4_TYPE0_PKT | (((cnt)-1) << 16)  | ((regindx) & 0x7FFF))
+#define pm4_type0_packet_for_sameregister(regindx, cnt)     (PM4_TYPE0_PKT | (((cnt)-1) << 16)  | ((1 << 15) | ((regindx) & 0x7FFF))
+#define pm4_type1_packet(reg0, reg1)                        (PM4_TYPE1_PKT                      | ((reg1) << 12) | (reg0))
+#define pm4_type3_packet(opcode, cnt)                       (PM4_TYPE3_PKT | (((cnt)-1) << 16)  | (((opcode) & 0xFF) << 8))
+#define pm4_predicated_type3_packet(opcode, cnt)            (PM4_TYPE3_PKT | (((cnt)-1) << 16)  | (((opcode) & 0xFF) << 8) | 0x1))
+#define pm4_nop_packet(cnt)                                 (PM4_TYPE3_PKT | (((cnt)-1) << 16)  | (PM4_NOP << 8))
+
+
+//////////////////////////////////////////////////////////////////////////////
+// packet headers
+//////////////////////////////////////////////////////////////////////////////
+#define PM4_HDR_ME_INIT                 pm4_type3_packet(PM4_ME_INIT, 18)
+#define PM4_HDR_INDIRECT_BUFFER_PFD     pm4_type3_packet(PM4_INDIRECT_BUFFER_PFD, 2)
+#define PM4_HDR_INDIRECT_BUFFER         pm4_type3_packet(PM4_INDIRECT_BUFFER, 2)
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// -----------------------
+// pm4 type0 packet header
+// -----------------------
+typedef struct __pm4_type0
+{
+    unsigned int       base_index  :15;
+    unsigned int       one_reg_wr  :1;
+    unsigned int       count       :14;
+    unsigned int       type        :2;
+} pm4_type0;
+
+// -----------------------
+// pm4 type2 packet header
+// -----------------------
+typedef struct __pm4_type2
+{
+    unsigned int       reserved    :30;
+    unsigned int       type        :2;
+} pm4_type2;
+
+// -----------------------
+// pm4 type3 packet header
+// -----------------------
+typedef struct __pm4_type3
+{
+    unsigned int       predicate   :1;
+    unsigned int       reserved1   :7;
+    unsigned int       it_opcode   :7;
+    unsigned int       reserved2   :1;
+    unsigned int       count       :14;
+    unsigned int       type        :2;
+} pm4_type3;
+
+#endif  // __GSL_PM4TYPES_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_properties.h b/drivers/mxc/amd-gpu/include/api/gsl_properties.h
new file mode 100644
index 00000000000..520761fe349
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_properties.h
@@ -0,0 +1,94 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_PROPERTIES_H
+#define __GSL_PROPERTIES_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// --------------
+// property types
+// --------------
+typedef enum _gsl_property_type_t
+{
+    GSL_PROP_DEVICE_INFO      = 0x00000001,
+    GSL_PROP_DEVICE_SHADOW    = 0x00000002,
+    GSL_PROP_DEVICE_POWER     = 0x00000003,
+    GSL_PROP_SHMEM            = 0x00000004,
+    GSL_PROP_SHMEM_APERTURES  = 0x00000005,
+    GSL_PROP_DEVICE_DMI       = 0x00000006
+} gsl_property_type_t;
+
+// -----------------
+// aperture property
+// -----------------
+typedef struct _gsl_apertureprop_t {
+    unsigned int  gpuaddr;
+    unsigned int  hostaddr;
+} gsl_apertureprop_t;
+
+// --------------
+// shmem property
+// --------------
+typedef struct _gsl_shmemprop_t {
+    int                 numapertures;
+    unsigned int        aperture_mask;
+    unsigned int        aperture_shift;
+    gsl_apertureprop_t  *aperture;
+} gsl_shmemprop_t;
+
+// -----------------------------
+// device shadow memory property
+// -----------------------------
+typedef struct _gsl_shadowprop_t {
+    unsigned int  hostaddr;
+    unsigned int  size;
+    gsl_flags_t   flags;
+} gsl_shadowprop_t;
+
+// ---------------------
+// device power property
+// ---------------------
+typedef struct _gsl_powerprop_t {
+    unsigned int  value;
+    gsl_flags_t   flags;
+} gsl_powerprop_t;
+
+
+// ---------------------
+// device DMI property
+// ---------------------
+typedef struct _gsl_dmiprop_t {
+    unsigned int  value;
+    gsl_flags_t   flags;
+} gsl_dmiprop_t;
+
+#endif  // __GSL_PROPERTIES_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_types.h b/drivers/mxc/amd-gpu/include/api/gsl_types.h
new file mode 100644
index 00000000000..99d98496611
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_types.h
@@ -0,0 +1,479 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_TYPES_H
+#define __GSL_TYPES_H
+
+#include "stddef.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+// status
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_SUCCESS                     OS_SUCCESS                  
+#define GSL_FAILURE                     OS_FAILURE                  
+#define GSL_FAILURE_SYSTEMERROR         OS_FAILURE_SYSTEMERROR      
+#define GSL_FAILURE_DEVICEERROR         OS_FAILURE_DEVICEERROR  
+#define GSL_FAILURE_OUTOFMEM            OS_FAILURE_OUTOFMEM         
+#define GSL_FAILURE_BADPARAM            OS_FAILURE_BADPARAM         
+#define GSL_FAILURE_OFFSETINVALID       OS_FAILURE_OFFSETINVALID
+#define GSL_FAILURE_NOTSUPPORTED        OS_FAILURE_NOTSUPPORTED     
+#define GSL_FAILURE_NOMOREAVAILABLE     OS_FAILURE_NOMOREAVAILABLE  
+#define GSL_FAILURE_NOTINITIALIZED      OS_FAILURE_NOTINITIALIZED 
+#define GSL_FAILURE_ALREADYINITIALIZED  OS_FAILURE_ALREADYINITIALIZED
+#define GSL_FAILURE_TIMEOUT             OS_FAILURE_TIMEOUT
+
+
+//////////////////////////////////////////////////////////////////////////////
+// memory allocation flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMFLAGS_ANY                0x00000000      // dont care
+
+#define GSL_MEMFLAGS_CHANNELANY         0x00000000
+#define GSL_MEMFLAGS_CHANNEL1           0x00000000
+#define GSL_MEMFLAGS_CHANNEL2           0x00000001
+#define GSL_MEMFLAGS_CHANNEL3           0x00000002
+#define GSL_MEMFLAGS_CHANNEL4           0x00000003
+                                        
+#define GSL_MEMFLAGS_BANKANY            0x00000000
+#define GSL_MEMFLAGS_BANK1              0x00000010
+#define GSL_MEMFLAGS_BANK2              0x00000020
+#define GSL_MEMFLAGS_BANK3              0x00000040
+#define GSL_MEMFLAGS_BANK4              0x00000080
+                                        
+#define GSL_MEMFLAGS_DIRANY             0x00000000
+#define GSL_MEMFLAGS_DIRTOP             0x00000100
+#define GSL_MEMFLAGS_DIRBOT             0x00000200
+                                        
+#define GSL_MEMFLAGS_APERTUREANY        0x00000000
+#define GSL_MEMFLAGS_EMEM               0x00000000
+#define GSL_MEMFLAGS_CONPHYS            0x00001000
+                                        
+#define GSL_MEMFLAGS_ALIGNANY           0x00000000      // minimum alignment is 32 bytes 
+#define GSL_MEMFLAGS_ALIGN32            0x00000000
+#define GSL_MEMFLAGS_ALIGN64            0x00060000
+#define GSL_MEMFLAGS_ALIGN128           0x00070000
+#define GSL_MEMFLAGS_ALIGN256           0x00080000
+#define GSL_MEMFLAGS_ALIGN512           0x00090000
+#define GSL_MEMFLAGS_ALIGN1K            0x000A0000
+#define GSL_MEMFLAGS_ALIGN2K            0x000B0000
+#define GSL_MEMFLAGS_ALIGN4K            0x000C0000
+#define GSL_MEMFLAGS_ALIGN8K            0x000D0000
+#define GSL_MEMFLAGS_ALIGN16K           0x000E0000
+#define GSL_MEMFLAGS_ALIGN32K           0x000F0000
+#define GSL_MEMFLAGS_ALIGN64K           0x00100000
+#define GSL_MEMFLAGS_ALIGNPAGE          GSL_MEMFLAGS_ALIGN4K
+
+#define GSL_MEMFLAGS_GPUREADWRITE       0x00000000
+#define GSL_MEMFLAGS_GPUREADONLY        0x01000000
+#define GSL_MEMFLAGS_GPUWRITEONLY       0x02000000
+#define GSL_MEMFLAGS_GPUNOACCESS        0x04000000
+
+#define GSL_MEMFLAGS_FORCEPAGESIZE      0x40000000
+#define GSL_MEMFLAGS_STRICTREQUEST      0x80000000      // fail the alloc if the flags cannot be honored 
+                    
+#define GSL_MEMFLAGS_CHANNEL_MASK       0x0000000F
+#define GSL_MEMFLAGS_BANK_MASK          0x000000F0
+#define GSL_MEMFLAGS_DIR_MASK           0x00000F00
+#define GSL_MEMFLAGS_APERTURE_MASK      0x0000F000
+#define GSL_MEMFLAGS_ALIGN_MASK         0x00FF0000
+#define GSL_MEMFLAGS_GPUAP_MASK         0x0F000000
+
+#define GSL_MEMFLAGS_CHANNEL_SHIFT      0
+#define GSL_MEMFLAGS_BANK_SHIFT         4
+#define GSL_MEMFLAGS_DIR_SHIFT          8
+#define GSL_MEMFLAGS_APERTURE_SHIFT     12
+#define GSL_MEMFLAGS_ALIGN_SHIFT        16
+#define GSL_MEMFLAGS_GPUAP_SHIFT        24
+
+
+//////////////////////////////////////////////////////////////////////////////
+// debug flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_DBGFLAGS_ALL                0xFFFFFFFF
+#define GSL_DBGFLAGS_DEVICE             0x00000001
+#define GSL_DBGFLAGS_CTXT               0x00000002
+#define GSL_DBGFLAGS_MEMMGR             0x00000004
+#define GSL_DBGFLAGS_MMU                0x00000008
+#define GSL_DBGFLAGS_POWER              0x00000010
+#define GSL_DBGFLAGS_IRQ                0x00000020
+#define GSL_DBGFLAGS_BIST               0x00000040
+#define GSL_DBGFLAGS_PM4                0x00000080
+#define GSL_DBGFLAGS_PM4MEM             0x00000100
+#define GSL_DBGFLAGS_PM4CHECK           0x00000200
+#define GSL_DBGFLAGS_DUMPX              0x00000400
+#define GSL_DBGFLAGS_DUMPX_WITHOUT_IFH  0x00000800
+#define GSL_DBGFLAGS_IFH                0x00001000
+#define GSL_DBGFLAGS_NULL               0x00002000
+
+
+//////////////////////////////////////////////////////////////////////////////
+// generic flag values
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_FLAGS_NORMALMODE            0x00000000
+#define GSL_FLAGS_SAFEMODE              0x00000001
+#define GSL_FLAGS_INITIALIZED0          0x00000002
+#define GSL_FLAGS_INITIALIZED           0x00000004
+#define GSL_FLAGS_STARTED               0x00000008
+#define GSL_FLAGS_ACTIVE                0x00000010
+#define GSL_FLAGS_RESERVED0             0x00000020
+#define GSL_FLAGS_RESERVED1             0x00000040
+#define GSL_FLAGS_RESERVED2             0x00000080
+
+
+//////////////////////////////////////////////////////////////////////////////
+// power flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_PWRFLAGS_POWER_OFF          0x00000001
+#define GSL_PWRFLAGS_POWER_ON           0x00000002
+#define GSL_PWRFLAGS_CLK_ON             0x00000004
+#define GSL_PWRFLAGS_CLK_OFF            0x00000008
+#define GSL_PWRFLAGS_OVERRIDE_ON        0x00000010
+#define GSL_PWRFLAGS_OVERRIDE_OFF       0x00000020
+
+//////////////////////////////////////////////////////////////////////////////
+// DMI flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_DMIFLAGS_ENABLE_SINGLE      0x00000001  //  Single buffered DMI
+#define GSL_DMIFLAGS_ENABLE_DOUBLE      0x00000002  //  Double buffered DMI
+#define GSL_DMIFLAGS_ENABLE_TRIPLE      0x00000004  //  Triple buffered DMI
+#define GSL_DMIFLAGS_DISABLE            0x00000008
+#define GSL_DMIFLAGS_NEXT_BUFFER        0x00000010
+
+//////////////////////////////////////////////////////////////////////////////
+// cache flags
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_CACHEFLAGS_CLEAN            0x00000001  /* flush cache          */
+#define GSL_CACHEFLAGS_INVALIDATE       0x00000002  /* invalidate cache     */
+#define GSL_CACHEFLAGS_WRITECLEAN       0x00000004  /* flush write cache    */
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  context
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_CONTEXT_MAX             20
+#define GSL_CONTEXT_NONE            0
+#define GSL_CONTEXT_SAVE_GMEM       1
+#define GSL_CONTEXT_NO_GMEM_ALLOC   2
+
+
+//////////////////////////////////////////////////////////////////////////////
+// other
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_TIMEOUT_NONE                        0
+#define GSL_TIMEOUT_DEFAULT                     0xFFFFFFFF
+
+#define GSL_PAGESIZE                            0x1000
+#define GSL_PAGESIZE_SHIFT                      12
+
+#define GSL_TIMESTAMP_EPSILON           20000
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+typedef unsigned int        gsl_devhandle_t;
+typedef unsigned int        gsl_ctxthandle_t;
+typedef int                 gsl_timestamp_t;
+typedef unsigned int        gsl_flags_t;
+typedef unsigned int        gpuaddr_t;
+
+// ---------
+// device id
+// ---------
+typedef enum _gsl_deviceid_t
+{
+    GSL_DEVICE_ANY    = 0,
+    GSL_DEVICE_YAMATO = 1,
+    GSL_DEVICE_G12    = 2,
+    GSL_DEVICE_MAX    = 2,
+
+    GSL_DEVICE_FOOBAR = 0x7FFFFFFF
+} gsl_deviceid_t;
+
+// ----------------
+// chip revision id
+// ----------------
+//
+// coreid:8 majorrev:8 minorrev:8 patch:8
+// 
+// coreid = 0x00 = YAMATO_DX
+// coreid = 0x80 = G12
+//
+
+#define COREID(x)   ((((unsigned int)x & 0xFF) << 24))
+#define MAJORID(x)  ((((unsigned int)x & 0xFF) << 16))
+#define MINORID(x)  ((((unsigned int)x & 0xFF) <<  8))
+#define PATCHID(x)  ((((unsigned int)x & 0xFF) <<  0))
+
+typedef enum _gsl_chipid_t
+{
+    GSL_CHIPID_YAMATODX_REV13   = (COREID(0x00) | MAJORID(0x01) | MINORID(0x03) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV14   = (COREID(0x00) | MAJORID(0x01) | MINORID(0x04) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV20   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x00) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV21   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV211  = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x01)),
+    GSL_CHIPID_YAMATODX_REV22   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x02) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV23   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV231  = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x01)),
+    GSL_CHIPID_YAMATODX_REV24   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x04) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV25   = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x00)),
+    GSL_CHIPID_YAMATODX_REV251  = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x01)),
+    GSL_CHIPID_G12_REV00        = (int)(COREID(0x80) | MAJORID(0x00) | MINORID(0x00) | PATCHID(0x00)),
+    GSL_CHIPID_ERROR            = (int)0xFFFFFFFF
+
+} gsl_chipid_t;
+
+#undef COREID
+#undef MAJORID
+#undef MINORID
+#undef PATCHID
+
+// -----------
+// device info
+// -----------
+typedef struct _gsl_devinfo_t {
+
+    gsl_deviceid_t  device_id;          // ID of this device
+    gsl_chipid_t    chip_id;
+    int             mmu_enabled;        // mmu address translation enabled
+    unsigned int    gmem_gpubaseaddr;
+    void *          gmem_hostbaseaddr;  // if gmem_hostbaseaddr is NULL, we would know its not mapped into mmio space
+    unsigned int    gmem_sizebytes;
+    unsigned int    high_precision; /* mx50 z160 has higher gradient/texture precision */
+
+} gsl_devinfo_t;
+
+// -------------------
+// device memory store
+// -------------------
+typedef struct _gsl_devmemstore_t {
+    volatile unsigned int  soptimestamp;
+    unsigned int           sbz;
+    volatile unsigned int  eoptimestamp;
+    unsigned int           sbz2;
+} gsl_devmemstore_t;
+
+#define GSL_DEVICE_MEMSTORE_OFFSET(field)       offsetof(gsl_devmemstore_t, field)
+
+// -----------
+// aperture id
+// -----------
+typedef enum _gsl_apertureid_t
+{
+    GSL_APERTURE_EMEM   = (GSL_MEMFLAGS_EMEM),
+    GSL_APERTURE_PHYS   = (GSL_MEMFLAGS_CONPHYS >> GSL_MEMFLAGS_APERTURE_SHIFT),
+    GSL_APERTURE_MMU    = (GSL_APERTURE_EMEM | 0x10000000),
+    GSL_APERTURE_MAX    = 2,
+
+    GSL_APERTURE_FOOBAR = 0x7FFFFFFF
+} gsl_apertureid_t;
+
+// ----------
+// channel id
+// ----------
+typedef enum _gsl_channelid_t
+{
+    GSL_CHANNEL_1      = (GSL_MEMFLAGS_CHANNEL1 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_2      = (GSL_MEMFLAGS_CHANNEL2 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_3      = (GSL_MEMFLAGS_CHANNEL3 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_4      = (GSL_MEMFLAGS_CHANNEL4 >> GSL_MEMFLAGS_CHANNEL_SHIFT),
+    GSL_CHANNEL_MAX    = 4,
+
+    GSL_CHANNEL_FOOBAR = 0x7FFFFFFF
+} gsl_channelid_t;
+
+// ----------------------
+// page access permission
+// ----------------------
+typedef enum _gsl_ap_t
+{
+    GSL_AP_NULL   = 0x0,
+    GSL_AP_R      = 0x1,
+    GSL_AP_W      = 0x2,
+    GSL_AP_RW     = 0x3,
+    GSL_AP_X      = 0x4,
+    GSL_AP_RWX    = 0x5,
+    GSL_AP_MAX    = 0x6,
+
+    GSL_AP_FOOBAR = 0x7FFFFFFF
+} gsl_ap_t;
+
+// -------------
+// memory region
+// -------------
+typedef struct _gsl_memregion_t {
+    unsigned char  *mmio_virt_base;
+    unsigned int   mmio_phys_base;
+    gpuaddr_t      gpu_base;
+    unsigned int   sizebytes;
+} gsl_memregion_t;
+
+// ------------------------
+// shared memory allocation
+// ------------------------
+typedef struct _gsl_memdesc_t {
+    void          *hostptr;
+    gpuaddr_t      gpuaddr;
+    int            size;
+    unsigned int   priv;                // private
+    unsigned int   priv2;               // private
+
+} gsl_memdesc_t;
+
+// ---------------------------------
+// physical page scatter/gatter list
+// ---------------------------------
+typedef struct _gsl_scatterlist_t {
+    int           contiguous;       // flag whether pages on the list are physically contiguous
+    unsigned int  num;
+    unsigned int  *pages;
+} gsl_scatterlist_t;
+
+// --------------
+// mem free queue
+// --------------
+//
+// this could be compressed down into the just the memdesc for the node
+//
+typedef struct _gsl_memnode_t {
+    gsl_timestamp_t       timestamp;
+    gsl_memdesc_t         memdesc;
+    unsigned int          pid;
+    struct _gsl_memnode_t *next;
+} gsl_memnode_t;
+
+typedef struct _gsl_memqueue_t {
+    gsl_memnode_t   *head;
+    gsl_memnode_t   *tail;
+} gsl_memqueue_t;
+
+// ------------
+// timestamp id
+// ------------
+typedef enum _gsl_timestamp_type_t
+{
+    GSL_TIMESTAMP_CONSUMED = 1, // start-of-pipeline timestamp
+    GSL_TIMESTAMP_RETIRED  = 2, // end-of-pipeline timestamp
+    GSL_TIMESTAMP_MAX      = 2,
+
+    GSL_TIMESTAMP_FOOBAR   = 0x7FFFFFFF
+} gsl_timestamp_type_t;
+
+// ------------
+// context type
+// ------------
+typedef enum _gsl_context_type_t
+{
+    GSL_CONTEXT_TYPE_GENERIC = 1,
+    GSL_CONTEXT_TYPE_OPENGL  = 2,
+    GSL_CONTEXT_TYPE_OPENVG  = 3,
+
+    GSL_CONTEXT_TYPE_FOOBAR  = 0x7FFFFFFF
+} gsl_context_type_t;
+
+// ---------
+// rectangle
+// ---------
+typedef struct _gsl_rect_t {
+    unsigned int x;
+    unsigned int y;
+    unsigned int width;
+    unsigned int height;
+	unsigned int pitch;
+} gsl_rect_t;
+
+// -----------------------
+// pixel buffer descriptor
+// -----------------------
+typedef struct _gsl_buffer_desc_t {
+    gsl_memdesc_t data;
+	unsigned int width;
+	unsigned int height;
+	unsigned int pitch;
+	unsigned int format;
+    unsigned int enabled;
+} gsl_buffer_desc_t;
+
+// ---------------------
+// command window target
+// ---------------------
+typedef enum _gsl_cmdwindow_t
+{
+    GSL_CMDWINDOW_MIN     = 0x00000000,
+    GSL_CMDWINDOW_2D      = 0x00000000,
+    GSL_CMDWINDOW_3D      = 0x00000001,     // legacy
+    GSL_CMDWINDOW_MMU     = 0x00000002,
+    GSL_CMDWINDOW_ARBITER = 0x000000FF,
+    GSL_CMDWINDOW_MAX     = 0x000000FF,
+
+    GSL_CMDWINDOW_FOOBAR  = 0x7FFFFFFF
+} gsl_cmdwindow_t;
+
+// ------------
+// interrupt id
+// ------------
+typedef enum _gsl_intrid_t
+{
+  GSL_INTR_YDX_MH_AXI_READ_ERROR = 0,
+  GSL_INTR_YDX_MH_AXI_WRITE_ERROR,
+  GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
+
+  GSL_INTR_YDX_CP_SW_INT,
+  GSL_INTR_YDX_CP_T0_PACKET_IN_IB,
+  GSL_INTR_YDX_CP_OPCODE_ERROR,
+  GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR,
+  GSL_INTR_YDX_CP_RESERVED_BIT_ERROR,
+  GSL_INTR_YDX_CP_IB_ERROR,
+  GSL_INTR_YDX_CP_IB2_INT,
+  GSL_INTR_YDX_CP_IB1_INT,
+  GSL_INTR_YDX_CP_RING_BUFFER,
+
+  GSL_INTR_YDX_RBBM_READ_ERROR,
+  GSL_INTR_YDX_RBBM_DISPLAY_UPDATE,
+  GSL_INTR_YDX_RBBM_GUI_IDLE,
+
+  GSL_INTR_YDX_SQ_PS_WATCHDOG,
+  GSL_INTR_YDX_SQ_VS_WATCHDOG,
+
+  GSL_INTR_G12_MH,
+  GSL_INTR_G12_G2D,
+  GSL_INTR_G12_FIFO,
+#ifndef _Z180
+  GSL_INTR_G12_FBC,
+#endif // _Z180
+
+  GSL_INTR_G12_MH_AXI_READ_ERROR,
+  GSL_INTR_G12_MH_AXI_WRITE_ERROR,
+  GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+
+  GSL_INTR_COUNT,
+
+  GSL_INTR_FOOBAR = 0x7FFFFFFF
+} gsl_intrid_t;
+
+#endif  // __GSL_TYPES_H
diff --git a/drivers/mxc/amd-gpu/include/api/gsl_utils.h b/drivers/mxc/amd-gpu/include/api/gsl_utils.h
new file mode 100644
index 00000000000..1078b634173
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/api/gsl_utils.h
@@ -0,0 +1,43 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_UTILS_H
+#define __GSL_UTILS_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_QUADPOW2_TO_SIZEBYTES(quadpow2)     (8 << (quadpow2))
+#define GSL_QUADPOW2_TO_SIZEDWORDS(quadpow2)    (2 << (quadpow2))
+#define GSL_POW2TEST(size)                      ((size) && !((size) & ((size) - 1)))
+#define GSL_POW2ALIGN_DOWN(addr, alignsize)     ((addr) & ~((alignsize) - 1));
+#define GSL_POW2ALIGN_UP(addr, alignsize)       (((addr) + ((alignsize) - 1)) & ~((alignsize) - 1))
+
+
+#endif  // __GSL_UTILS_H
diff --git a/drivers/mxc/amd-gpu/include/gsl.h b/drivers/mxc/amd-gpu/include/gsl.h
new file mode 100644
index 00000000000..07d8e97dcee
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl.h
@@ -0,0 +1,79 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_H
+#define __GSL_H
+
+//#define __KGSLLIB_EXPORTS
+#define __KERNEL_MODE__
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  forward typedefs
+//////////////////////////////////////////////////////////////////////////////
+//struct _gsl_device_t;
+typedef struct _gsl_device_t    gsl_device_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  includes
+//////////////////////////////////////////////////////////////////////////////
+#include "gsl_buildconfig.h"
+
+#include "kos_libapi.h"
+
+#include "gsl_klibapi.h"
+
+#ifdef GSL_BLD_YAMATO
+#include <reg/yamato.h>
+
+#include "gsl_pm4types.h"
+#include "gsl_utils.h"
+#include "gsl_drawctxt.h"
+#include "gsl_ringbuffer.h"
+#endif
+
+#ifdef GSL_BLD_G12
+#include <reg/g12_reg.h>
+
+#include "gsl_cmdwindow.h"
+#endif
+
+#include "gsl_debug.h"
+#include "gsl_mmu.h"
+#include "gsl_memmgr.h"
+#include "gsl_sharedmem.h"
+#include "gsl_intrmgr.h"
+#include "gsl_cmdstream.h"
+#include "gsl_device.h"
+#include "gsl_driver.h"
+#include "gsl_log.h"
+
+#include "gsl_config.h"
+
+#endif // __GSL_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_buildconfig.h b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h
new file mode 100644
index 00000000000..4e6be4da7dc
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h
@@ -0,0 +1,55 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __GSL__BUILDCONFIG_H
+#define __GSL__BUILDCONFIG_H
+
+#define GSL_BLD_YAMATO
+#define GSL_BLD_G12
+
+#define GSL_LOCKING_COARSEGRAIN
+
+#define GSL_STATS_MEM
+#define GSL_STATS_RINGBUFFER
+#define GSL_STATS_MMU
+
+#define GSL_RB_USE_MEM_RPTR
+#define GSL_RB_USE_MEM_TIMESTAMP
+#define GSL_RB_TIMESTAMP_INTERUPT
+/* #define GSL_RB_USE_WPTR_POLLING */
+
+/* #define GSL_MMU_PAGETABLE_PERPROCESS */
+
+#define GSL_CALLER_PROCESS_MAX      10
+#define GSL_SHMEM_MAX_APERTURES     3
+
+#endif /* __GSL__BUILDCONFIG_H */
diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdstream.h b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h
new file mode 100644
index 00000000000..550d5d0005a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_CMDSTREAM_H
+#define __GSL_CMDSTREAM_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef VG_HDK
+#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data)
+#else
+#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data)   kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp), 4, false)
+#endif
+
+#ifdef VG_HDK
+#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data)   (*((int*)data) = (gsl_driver.device[GSL_DEVICE_G12-1]).timestamp)
+#else
+#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data)   kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), 4, false)
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+gsl_timestamp_t kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type);
+void kgsl_cmdstream_memqueue_drain(gsl_device_t *device);
+int kgsl_cmdstream_init(gsl_device_t *device);
+int kgsl_cmdstream_close(gsl_device_t *device);
+
+#endif  // __GSL_CMDSTREAM_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h
new file mode 100644
index 00000000000..0152dd75a63
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_CMDWINDOW_H
+#define __GSL_CMDWINDOW_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#ifndef _Z180
+#define GSL_G12_INTR_COUNT                  4
+#else
+#define GSL_G12_INTR_COUNT                  3
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     kgsl_cmdwindow_init(gsl_device_t *device);
+int     kgsl_cmdwindow_close(gsl_device_t *device);
+int     kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data);
+
+#endif // __GSL_CMDWINDOW_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_config.h b/drivers/mxc/amd-gpu/include/gsl_config.h
new file mode 100644
index 00000000000..aa911b4096a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_config.h
@@ -0,0 +1,221 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __GSL__CONFIG_H
+#define __GSL__CONFIG_H
+
+/* ------------------------
+ * Yamato ringbuffer config
+ * ------------------------ */
+static const unsigned int gsl_cfg_rb_sizelog2quadwords = GSL_RB_SIZE_32K;
+static const unsigned int gsl_cfg_rb_blksizequadwords  = GSL_RB_SIZE_16;
+
+/* ------------------------
+ * Yamato MH arbiter config
+ * ------------------------ */
+static const mh_arbiter_config_t  gsl_cfg_yamato_mharb = {
+    0x10,   /* same_page_limit */
+    0,      /* same_page_granularity  */
+    1,      /* l1_arb_enable */
+    1,      /* l1_arb_hold_enable */
+    0,      /* l2_arb_control */
+    1,      /* page_size */
+    1,      /* tc_reorder_enable */
+    1,      /* tc_arb_hold_enable */
+    1,      /* in_flight_limit_enable */
+    0x8,    /* in_flight_limit */
+    1,      /* cp_clnt_enable */
+    1,      /* vgt_clnt_enable */
+    1,      /* tc_clnt_enable */
+    1,      /* rb_clnt_enable */
+    1,      /* pa_clnt_enable */
+};
+
+/* ---------------------
+ * G12 MH arbiter config
+ * --------------------- */
+static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = {
+    0x10,   /* SAME_PAGE_LIMIT */
+    0,      /* SAME_PAGE_GRANULARITY */
+    1,      /* L1_ARB_ENABLE */
+    1,      /* L1_ARB_HOLD_ENABLE */
+    0,      /* L2_ARB_CONTROL */
+    1,      /* PAGE_SIZE */
+    1,      /* TC_REORDER_ENABLE */
+    1,      /* TC_ARB_HOLD_ENABLE */
+    0,      /* IN_FLIGHT_LIMIT_ENABLE */
+    0x8,    /* IN_FLIGHT_LIMIT */
+    1,      /* CP_CLNT_ENABLE */
+    1,      /* VGT_CLNT_ENABLE */
+    1,      /* TC_CLNT_ENABLE */
+    1,      /* RB_CLNT_ENABLE */
+    1,      /* PA_CLNT_ENABLE */
+};
+
+/* -----------------------------
+ * interrupt block register data
+ * ----------------------------- */
+static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] = {
+    {   /* Yamato MH */
+	GSL_INTR_BLOCK_YDX_MH,
+	GSL_INTR_YDX_MH_AXI_READ_ERROR,
+	GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
+	mmMH_INTERRUPT_STATUS,
+	mmMH_INTERRUPT_CLEAR,
+	mmMH_INTERRUPT_MASK
+    },
+    {   /* Yamato CP */
+	GSL_INTR_BLOCK_YDX_CP,
+	GSL_INTR_YDX_CP_SW_INT,
+	GSL_INTR_YDX_CP_RING_BUFFER,
+	mmCP_INT_STATUS,
+	mmCP_INT_ACK,
+	mmCP_INT_CNTL
+    },
+    {   /* Yamato RBBM */
+	GSL_INTR_BLOCK_YDX_RBBM,
+	GSL_INTR_YDX_RBBM_READ_ERROR,
+	GSL_INTR_YDX_RBBM_GUI_IDLE,
+	mmRBBM_INT_STATUS,
+	mmRBBM_INT_ACK,
+	mmRBBM_INT_CNTL
+    },
+    {   /* Yamato SQ */
+	GSL_INTR_BLOCK_YDX_SQ,
+	GSL_INTR_YDX_SQ_PS_WATCHDOG,
+	GSL_INTR_YDX_SQ_VS_WATCHDOG,
+	mmSQ_INT_STATUS,
+	mmSQ_INT_ACK,
+	mmSQ_INT_CNTL
+    },
+    {   /* G12 */
+	GSL_INTR_BLOCK_G12,
+	GSL_INTR_G12_MH,
+#ifndef _Z180
+	GSL_INTR_G12_FBC,
+#else
+	GSL_INTR_G12_FIFO,
+#endif /* _Z180 */
+	(ADDR_VGC_IRQSTATUS >> 2),
+	(ADDR_VGC_IRQSTATUS >> 2),
+	(ADDR_VGC_IRQENABLE >> 2)
+    },
+    {   /* G12 MH */
+	GSL_INTR_BLOCK_G12_MH,
+	GSL_INTR_G12_MH_AXI_READ_ERROR,
+	GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+	ADDR_MH_INTERRUPT_STATUS,       /* G12 MH offsets are considered to be dword based, therefore no down shift */
+	ADDR_MH_INTERRUPT_CLEAR,
+	ADDR_MH_INTERRUPT_MASK
+    },
+};
+
+/* -----------------------
+ * interrupt mask bit data
+ * ----------------------- */
+static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] = {
+    MH_INTERRUPT_MASK__AXI_READ_ERROR,
+    MH_INTERRUPT_MASK__AXI_WRITE_ERROR,
+    MH_INTERRUPT_MASK__MMU_PAGE_FAULT,
+
+    CP_INT_CNTL__SW_INT_MASK,
+    CP_INT_CNTL__T0_PACKET_IN_IB_MASK,
+    CP_INT_CNTL__OPCODE_ERROR_MASK,
+    CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK,
+    CP_INT_CNTL__RESERVED_BIT_ERROR_MASK,
+    CP_INT_CNTL__IB_ERROR_MASK,
+    CP_INT_CNTL__IB2_INT_MASK,
+    CP_INT_CNTL__IB1_INT_MASK,
+    CP_INT_CNTL__RB_INT_MASK,
+
+    RBBM_INT_CNTL__RDERR_INT_MASK,
+    RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK,
+    RBBM_INT_CNTL__GUI_IDLE_INT_MASK,
+
+    SQ_INT_CNTL__PS_WATCHDOG_MASK,
+    SQ_INT_CNTL__VS_WATCHDOG_MASK,
+
+    (1 << VGC_IRQENABLE_MH_FSHIFT),
+    (1 << VGC_IRQENABLE_G2D_FSHIFT),
+    (1 << VGC_IRQENABLE_FIFO_FSHIFT),
+#ifndef _Z180
+    (1 << VGC_IRQENABLE_FBC_FSHIFT),
+#endif
+    (1 << MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT),
+    (1 << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT),
+    (1 << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT),
+};
+
+/* -----------------
+ * mmu register data
+ * ----------------- */
+static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] = {
+    {   /* Yamato */
+	mmMH_MMU_CONFIG,
+	mmMH_MMU_MPU_BASE,
+	mmMH_MMU_MPU_END,
+	mmMH_MMU_VA_RANGE,
+	mmMH_MMU_PT_BASE,
+	mmMH_MMU_PAGE_FAULT,
+	mmMH_MMU_TRAN_ERROR,
+	mmMH_MMU_INVALIDATE,
+    },
+    {   /* G12 - MH offsets are considered to be dword based, therefore no down shift */
+	ADDR_MH_MMU_CONFIG,
+	ADDR_MH_MMU_MPU_BASE,
+	ADDR_MH_MMU_MPU_END,
+	ADDR_MH_MMU_VA_RANGE,
+	ADDR_MH_MMU_PT_BASE,
+	ADDR_MH_MMU_PAGE_FAULT,
+	ADDR_MH_MMU_TRAN_ERROR,
+	ADDR_MH_MMU_INVALIDATE,
+    },
+};
+
+/* -----------------
+ * mh interrupt data
+ * ----------------- */
+static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] =
+{
+    {   /* Yamato */
+	GSL_INTR_YDX_MH_AXI_READ_ERROR,
+	GSL_INTR_YDX_MH_AXI_WRITE_ERROR,
+	GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
+    },
+    {   /* G12 */
+	GSL_INTR_G12_MH_AXI_READ_ERROR,
+	GSL_INTR_G12_MH_AXI_WRITE_ERROR,
+	GSL_INTR_G12_MH_MMU_PAGE_FAULT,
+    }
+};
+
+#endif /* __GSL__CONFIG_H */
diff --git a/drivers/mxc/amd-gpu/include/gsl_context.h b/drivers/mxc/amd-gpu/include/gsl_context.h
new file mode 100644
index 00000000000..6e83bdb3403
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_context.h
@@ -0,0 +1,45 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_CONTEXT_H
+#define __GSL_CONTEXT_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+//////////////////////////////////////////////////////////////////////////////
+// functions
+//////////////////////////////////////////////////////////////////////////////
+
+#endif  // __GSL_CONTEXT_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_debug.h b/drivers/mxc/amd-gpu/include/gsl_debug.h
new file mode 100644
index 00000000000..1275278f9ea
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_debug.h
@@ -0,0 +1,126 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DEBUG_H
+#define __GSL_DEBUG_H
+
+#ifdef BB_DUMPX
+#include "dumpx.h"
+#endif
+
+#ifdef TBDUMP
+#include "gsl_tbdump.h"
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#ifdef _DEBUG
+#define KGSL_DEBUG(flag, action)                            if (gsl_driver.flags_debug & flag) {action;}
+#ifdef GSL_BLD_YAMATO
+#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords)                Yamato_DumpPM4((cmds), (sizedwords))
+#define KGSL_DEBUG_DUMPREGWRITE(addr, value)                Yamato_DumpRegisterWrite((addr), (value))
+#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data)      Yamato_DumpWriteMemory(addr, sizebytes, data)
+#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value)       Yamato_DumpSetMemory(addr, sizebytes, value)
+#define KGSL_DEBUG_DUMPFBSTART(device)                      Yamato_DumpFbStart(device)
+#define KGSL_DEBUG_DUMPREGSPACE(device)                     Yamato_DumpRegSpace(device)
+#define KGSL_DEBUG_DUMPWINDOW(addr, width, height)          Yamato_DumpWindow(addr, width, height)
+#else
+#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords)                
+#define KGSL_DEBUG_DUMPREGWRITE(addr, value)                
+#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data)      
+#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value)       
+#define KGSL_DEBUG_DUMPFBSTART(device)                      
+#define KGSL_DEBUG_DUMPREGSPACE(device)
+#define KGSL_DEBUG_DUMPWINDOW(addr, width, height)          
+#endif
+#ifdef TBDUMP
+
+#define KGSL_DEBUG_TBDUMP_OPEN(filename)                    tbdump_open(filename)
+#define KGSL_DEBUG_TBDUMP_CLOSE()                           tbdump_close()
+#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes)     tbdump_syncmem((unsigned int)addr, (unsigned int)src, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes)    tbdump_setmem((unsigned int)addr, value, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value)           tbdump_slavewrite(addr, value)
+#define KGSL_DEBUG_TBDUMP_WAITIRQ()                         tbdump_waitirq()
+
+#else
+#define KGSL_DEBUG_TBDUMP_OPEN(file)
+#define KGSL_DEBUG_TBDUMP_CLOSE()
+#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value)
+#define KGSL_DEBUG_TBDUMP_WAITIRQ()
+#endif
+#ifdef BB_DUMPX
+#define KGSL_DEBUG_DUMPX_OPEN(filename, param)              dumpx_open((filename), (param))
+#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment)    dumpx(cmd, (par1), (par2), (par3), (comment))
+#define KGSL_DEBUG_DUMPX_CLOSE()                            dumpx_close()
+#else
+#define KGSL_DEBUG_DUMPX_OPEN(filename, param)
+#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment)
+#define KGSL_DEBUG_DUMPX_CLOSE()
+#endif
+#else
+#define KGSL_DEBUG(flag, action)
+#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords)
+#define KGSL_DEBUG_DUMPREGWRITE(addr, value)
+#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data)
+#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value)
+#define KGSL_DEBUG_DUMPFBSTART(device)
+#define KGSL_DEBUG_DUMPREGSPACE(device)
+#define KGSL_DEBUG_DUMPWINDOW(addr, width, height)
+#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment)
+
+#define KGSL_DEBUG_TBDUMP_OPEN(file)
+#define KGSL_DEBUG_TBDUMP_CLOSE()
+#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes)
+#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value)
+#define KGSL_DEBUG_TBDUMP_WAITIRQ()
+#endif // _DEBUG
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_BLD_YAMATO
+void            Yamato_DumpPM4(unsigned int *cmds, unsigned int sizedwords);
+void            Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value);
+void            Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData);
+void            Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData);
+void            Yamato_DumpFbStart(gsl_device_t *device);
+void            Yamato_DumpRegSpace(gsl_device_t *device);
+#ifdef _WIN32
+void            Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height);
+#endif
+#endif
+#ifdef _DEBUG
+int             kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords);
+#endif //_DEBUG
+#endif // __GSL_DRIVER_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_device.h b/drivers/mxc/amd-gpu/include/gsl_device.h
new file mode 100644
index 00000000000..07c1438994f
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_device.h
@@ -0,0 +1,152 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DEVICE_H
+#define __GSL_DEVICE_H
+
+#ifdef _LINUX
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// --------------
+// function table
+// --------------
+typedef struct _gsl_functable_t {
+    int (*device_init)            (gsl_device_t *device);
+    int (*device_close)           (gsl_device_t *device);
+    int (*device_destroy)         (gsl_device_t *device);
+    int (*device_start)           (gsl_device_t *device, gsl_flags_t flags);
+    int (*device_stop)            (gsl_device_t *device);
+    int (*device_getproperty)     (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes);
+    int (*device_setproperty)     (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes);
+    int (*device_idle)            (gsl_device_t *device, unsigned int timeout);
+    int (*device_regread)         (gsl_device_t *device, unsigned int offsetwords, unsigned int *value);
+    int (*device_regwrite)        (gsl_device_t *device, unsigned int offsetwords, unsigned int value);
+    int (*device_waitirq)         (gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout);
+	int (*device_waittimestamp)   (gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout);
+    int (*device_runpending)      (gsl_device_t *device);
+    int (*device_addtimestamp)    (gsl_device_t *device_id, gsl_timestamp_t *timestamp);
+    int (*intr_isr)               (gsl_device_t *device);
+	int (*mmu_tlbinvalidate)      (gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid);
+	int (*mmu_setpagetable)       (gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid);
+    int (*cmdstream_issueibcmds)  (gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+    int (*context_create)         (gsl_device_t *device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+    int (*context_destroy)        (gsl_device_t *device_id, unsigned int drawctxt_id);
+} gsl_functable_t;
+
+// -------------
+// device object 
+// -------------
+struct _gsl_device_t {
+
+    unsigned int      refcnt;
+    unsigned int      callerprocess[GSL_CALLER_PROCESS_MAX];    // caller process table
+    gsl_functable_t   ftbl;
+    gsl_flags_t       flags;
+    gsl_deviceid_t    id;
+    unsigned int      chip_id;
+    gsl_memregion_t   regspace;
+    gsl_intr_t        intr;
+    gsl_memdesc_t     memstore;
+    gsl_memqueue_t    memqueue; // queue of memfrees pending timestamp elapse 
+
+#ifdef  GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+    unsigned int      memstoreshadow[GSL_CALLER_PROCESS_MAX];
+#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+
+#ifndef GSL_NO_MMU
+    gsl_mmu_t         mmu;
+#endif // GSL_NO_MMU
+
+#ifdef GSL_BLD_YAMATO
+    gsl_memregion_t   gmemspace;
+    gsl_ringbuffer_t  ringbuffer;
+#ifdef GSL_LOCKING_FINEGRAIN
+    oshandle_t        drawctxt_mutex;
+#endif
+    unsigned int      drawctxt_count;
+    gsl_drawctxt_t    *drawctxt_active;
+    gsl_drawctxt_t    drawctxt[GSL_CONTEXT_MAX];
+#endif // GSL_BLD_YAMATO
+
+#ifdef GSL_BLD_G12
+#ifdef GSL_LOCKING_FINEGRAIN
+    oshandle_t        cmdwindow_mutex;
+#endif
+    unsigned int      intrcnt[GSL_G12_INTR_COUNT];
+    gsl_timestamp_t   current_timestamp;
+    gsl_timestamp_t   timestamp;
+#ifndef _LINUX	
+    unsigned int      irq_thread;
+    oshandle_t        irq_thread_handle;
+#endif
+#ifdef IRQTHREAD_POLL
+    oshandle_t        irqthread_event;
+#endif
+#endif // GSL_BLD_G12
+#ifdef GSL_LOCKING_FINEGRAIN
+    oshandle_t        cmdstream_mutex;
+#endif
+#ifndef _LINUX	
+    oshandle_t        timestamp_event;
+#else
+	wait_queue_head_t timestamp_waitq;
+	struct workqueue_struct	*irq_workq;
+	struct work_struct irq_work;	
+	struct work_struct irq_err_work;
+#endif
+    void              *autogate;
+};
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id);
+int     kgsl_device_close(gsl_device_t *device);
+int     kgsl_device_destroy(gsl_device_t *device);
+int     kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid);
+int     kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid);
+int     kgsl_device_runpending(gsl_device_t *device);
+
+int     kgsl_yamato_getfunctable(gsl_functable_t *ftbl);
+int     kgsl_g12_getfunctable(gsl_functable_t *ftbl);
+
+int kgsl_clock(gsl_deviceid_t dev, int enable);
+int kgsl_device_active(gsl_device_t *dev);
+int kgsl_device_clock(gsl_deviceid_t id, int enable);
+int kgsl_device_autogate_init(gsl_device_t *dev);
+void kgsl_device_autogate_exit(gsl_device_t *dev);
+
+
+#endif  // __GSL_DEVICE_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_display.h b/drivers/mxc/amd-gpu/include/gsl_display.h
new file mode 100644
index 00000000000..82300647b3e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_display.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DISPLAY_H
+#define __GSL_DISPLAY_H
+
+#define __GSLDISPLAY_EXPORTS
+
+#include "gsl_libapi.h"
+#include "gsl_klibapi.h"    // hack to enable direct reg write
+#include "gsl_displayapi.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines                    
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_LIB_MAXDISPLAYS     1
+#define GSL_LIB_MAXSURFACES     3
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+typedef struct _gsl_display_t {
+    int                   numdisplays;
+    gsl_displaymode_t     mode[GSL_LIB_MAXDISPLAYS];
+    gsl_devhandle_t       devhandle;
+} gsl_display_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     gsl_display_hitachi_240x320_tft_init(int display_id);
+int     gsl_display_toshiba_640x480_tft_init(int display_id);
+
+#endif // __GSL_DISPLAY_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_drawctxt.h b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h
new file mode 100644
index 00000000000..f3bc8c37f4f
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h
@@ -0,0 +1,118 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DRAWCTXT_H
+#define __GSL_DRAWCTXT_H
+
+//////////////////////////////////////////////////////////////////////////////
+// Flags
+//////////////////////////////////////////////////////////////////////////////
+
+#define CTXT_FLAGS_NOT_IN_USE       0x00000000
+#define CTXT_FLAGS_IN_USE           0x00000001
+
+#define CTXT_FLAGS_STATE_SHADOW     0x00000010  // state shadow memory allocated
+
+#define CTXT_FLAGS_GMEM_SHADOW      0x00000100  // gmem shadow memory allocated
+#define CTXT_FLAGS_GMEM_SAVE        0x00000200  // gmem must be copied to shadow
+#define CTXT_FLAGS_GMEM_RESTORE     0x00000400  // gmem can be restored from shadow
+
+#define CTXT_FLAGS_SHADER_SAVE      0x00002000  // shader must be copied to shadow
+#define CTXT_FLAGS_SHADER_RESTORE   0x00004000  // shader can be restored from shadow
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// ------------
+// draw context
+// ------------
+
+typedef struct _gmem_shadow_t
+{
+    gsl_memdesc_t   gmemshadow;     // Shadow buffer address
+
+    // 256 KB GMEM surface = 4 bytes-per-pixel x 256 pixels/row x 256 rows.
+    // width & height must be a multiples of 32, in case tiled textures are used.
+    unsigned int    size;           // Size of surface used to store GMEM
+    unsigned int    width;          // Width of surface used to store GMEM
+    unsigned int    height;         // Height of surface used to store GMEM
+    unsigned int    pitch;          // Pitch of surface used to store GMEM
+	unsigned int    format;         // Format of surface used to store GMEM
+
+    int             offset;
+
+    unsigned int    offset_x;    
+	unsigned int    offset_y;
+
+	unsigned int	gmem_width;     // GMEM width
+	unsigned int	gmem_height;    // GMEM height
+	unsigned int    gmem_pitch;     // GMEM pitch
+
+    unsigned int    gmem_offset_x;
+    unsigned int    gmem_offset_y;
+
+    unsigned int*   gmem_save_commands;
+    unsigned int*   gmem_restore_commands;
+    unsigned int    gmem_save[3];
+    unsigned int    gmem_restore[3];
+
+    gsl_memdesc_t   quad_vertices;
+    gsl_memdesc_t   quad_texcoords;
+} gmem_shadow_t;
+
+#define GSL_MAX_GMEM_SHADOW_BUFFERS 2
+
+typedef struct _gsl_drawctxt_t {
+	unsigned int        pid;
+    gsl_flags_t         flags;
+    gsl_context_type_t  type;
+    gsl_memdesc_t       gpustate;
+    
+    unsigned int        reg_save[3];
+    unsigned int        reg_restore[3];
+    unsigned int        shader_save[3];
+    unsigned int        shader_fixup[3];
+    unsigned int        shader_restore[3];
+    unsigned int        chicken_restore[3];
+    gmem_shadow_t       context_gmem_shadow;    // Information of the GMEM shadow that is created in context create
+    gmem_shadow_t       user_gmem_shadow[GSL_MAX_GMEM_SHADOW_BUFFERS]; // User defined GMEM shadow buffers
+} gsl_drawctxt_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int     kgsl_drawctxt_init(gsl_device_t *device);
+int     kgsl_drawctxt_close(gsl_device_t *device);
+int     kgsl_drawctxt_destroyall(gsl_device_t *device);
+void    kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags);
+int     kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags);
+int     kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id);
+
+#endif  // __GSL_DRAWCTXT_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_driver.h b/drivers/mxc/amd-gpu/include/gsl_driver.h
new file mode 100644
index 00000000000..9c908ce4696
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_driver.h
@@ -0,0 +1,106 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_DRIVER_H
+#define __GSL_DRIVER_H
+
+
+/////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_DEDICATED_PROCESS
+#define GSL_CALLER_PROCESSID_GET()      kos_callerprocess_getid()
+#else
+#define GSL_CALLER_PROCESSID_GET()      kos_process_getid()
+#endif // GSL_DEDICATED_PROCESS
+
+#ifdef GSL_LOCKING_COARSEGRAIN
+#define GSL_API_MUTEX_CREATE()          gsl_driver.mutex = kos_mutex_create("gsl_global"); \
+                                        if (!gsl_driver.mutex) {return (GSL_FAILURE);}
+#define GSL_API_MUTEX_LOCK()            kos_mutex_lock(gsl_driver.mutex)
+#define GSL_API_MUTEX_UNLOCK()          kos_mutex_unlock(gsl_driver.mutex)
+#define GSL_API_MUTEX_FREE()            kos_mutex_free(gsl_driver.mutex); gsl_driver.mutex = 0;
+#else
+#define GSL_API_MUTEX_CREATE()
+#define GSL_API_MUTEX_LOCK()        
+#define GSL_API_MUTEX_UNLOCK()      
+#define GSL_API_MUTEX_FREE()
+#endif
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+// -------------
+// driver object 
+// -------------
+typedef struct _gsl_driver_t {
+    gsl_flags_t      flags_debug;
+    int              refcnt;
+    unsigned int     callerprocess[GSL_CALLER_PROCESS_MAX]; // caller process table
+    oshandle_t       mutex;                                 // global API mutex
+    void             *hal;
+    gsl_sharedmem_t  shmem;
+    gsl_device_t     device[GSL_DEVICE_MAX];
+    int              dmi_state;     //  OS_TRUE = enabled, OS_FALSE otherwise
+    gsl_flags_t      dmi_mode;      //  single, double, or triple buffering
+    int              dmi_frame;     //  set to -1 when DMI is enabled
+    int              dmi_max_frame; //  indicates the maximum frame # that we will support
+    int              enable_mmu;
+} gsl_driver_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// external variable declarations
+//////////////////////////////////////////////////////////////////////////////
+extern gsl_driver_t  gsl_driver;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  inline functions
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_driver_getcallerprocessindex(unsigned int pid, int *index)
+{
+    int  i;
+
+    // obtain index in caller process table
+    for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++)
+    {
+        if (gsl_driver.callerprocess[i] == pid)
+        {
+            *index = i;            
+            return (GSL_SUCCESS);
+        }
+    }
+
+    return (GSL_FAILURE);
+}
+
+#endif // __GSL_DRIVER_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_hal.h b/drivers/mxc/amd-gpu/include/gsl_hal.h
new file mode 100644
index 00000000000..fcf9f0891f1
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_hal.h
@@ -0,0 +1,151 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_HALAPI_H
+#define __GSL_HALAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+/*
+#include "gsl_buildconfig.h"
+#include "kos_libapi.h"
+#include "gsl_klibapi.h"
+#ifdef GSL_BLD_YAMATO
+#include <reg/yamato.h>
+#endif
+#ifdef GSL_BLD_G12
+#include <reg/g12_reg.h>
+#endif
+#include "gsl_hwaccess.h"
+*/
+
+#include "gsl.h"
+#include "gsl_hwaccess.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+// linkage
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __KGSLHAL_EXPORTS
+#define KGSLHAL_API                 OS_DLLEXPORT
+#else
+#define KGSLHAL_API
+#endif // __KGSLLIB_EXPORTS
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  version control                    
+//////////////////////////////////////////////////////////////////////////////
+#define KGSLHAL_NAME            "AMD GSL Kernel HAL"
+#define KGSLHAL_VERSION         "0.1"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_HAL_REG_READ(device_id, gpubase, offsetwords, value)    kgsl_hwaccess_regread(device_id, gpubase, (offsetwords), (value))
+#define GSL_HAL_REG_WRITE(device_id, gpubase, offsetwords, value)   kgsl_hwaccess_regwrite(device_id, gpubase, (offsetwords), (value))
+
+#define GSL_HAL_MEM_READ(dst, gpubase, gpuoffset, sizebytes, touserspace)        kgsl_hwaccess_memread(dst, gpubase, (gpuoffset), (sizebytes), touserspace)
+#define GSL_HAL_MEM_WRITE(gpubase, gpuoffset, src, sizebytes, fromuserspace)     kgsl_hwaccess_memwrite(gpubase, (gpuoffset), src, (sizebytes), fromuserspace)
+#define GSL_HAL_MEM_SET(gpubase, gpuoffset, value, sizebytes)                    kgsl_hwaccess_memset(gpubase, (gpuoffset), (value), (sizebytes))
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// -------------
+// device config
+// -------------
+typedef struct _gsl_devconfig_t {
+
+    gsl_memregion_t  regspace;
+
+    unsigned int     mmu_config;
+    gpuaddr_t        mpu_base;
+    int              mpu_range;
+    gpuaddr_t        va_base;
+    unsigned int     va_range;
+
+#ifdef GSL_BLD_YAMATO
+    gsl_memregion_t  gmemspace;
+#endif // GSL_BLD_YAMATO
+
+} gsl_devconfig_t;
+
+// ----------------------
+// memory aperture config
+// ----------------------
+typedef struct _gsl_apertureconfig_t
+{
+    gsl_apertureid_t  id;
+    gsl_channelid_t   channel;
+    unsigned int      hostbase;
+    unsigned int      gpubase;
+    unsigned int      sizebytes;
+} gsl_apertureconfig_t;
+
+// --------------------
+// shared memory config
+// --------------------
+typedef struct _gsl_shmemconfig_t 
+{
+    int                   numapertures;
+    gsl_apertureconfig_t  apertures[GSL_SHMEM_MAX_APERTURES];
+} gsl_shmemconfig_t;
+
+typedef struct _gsl_hal_t {
+     gsl_memregion_t z160_regspace;
+     gsl_memregion_t z430_regspace;
+     gsl_memregion_t memchunk;
+     gsl_memregion_t memspace[GSL_SHMEM_MAX_APERTURES];
+     unsigned int has_z160;
+     unsigned int has_z430;
+} gsl_hal_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  HAL API
+//////////////////////////////////////////////////////////////////////////////
+KGSLHAL_API int             kgsl_hal_init(void);
+KGSLHAL_API int             kgsl_hal_close(void);
+KGSLHAL_API int             kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config);
+KGSLHAL_API int             kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config);
+KGSLHAL_API int             kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value);
+KGSLHAL_API gsl_chipid_t    kgsl_hal_getchipid(gsl_deviceid_t device_id);
+KGSLHAL_API int             kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]);
+KGSLHAL_API int             kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif  // __GSL_HALAPI_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_halconfig.h b/drivers/mxc/amd-gpu/include/gsl_halconfig.h
new file mode 100644
index 00000000000..363474b7a6b
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_halconfig.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __GSL_HALCONFIG_H
+#define __GSL_HALCONFIG_H
+
+#define GSL_HAL_GPUBASE_REG_YDX         0x30000000
+#define GSL_HAL_SIZE_REG_YDX            0x00020000            /* 128KB */
+
+#define GSL_HAL_SIZE_REG_G12            0x00001000            /* 4KB */
+
+#define GSL_HAL_SHMEM_SIZE_EMEM1_MMU    0x01800000            /* 24MB */
+#define GSL_HAL_SHMEM_SIZE_EMEM2_MMU    0x00400000            /* 4MB */
+#define GSL_HAL_SHMEM_SIZE_PHYS_MMU     0x00400000            /* 4MB */
+
+#define GSL_HAL_SHMEM_SIZE_EMEM1_NOMMU  0x00A00000            /* 10MB */
+#define GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU  0x00200000            /* 2MB */
+#define GSL_HAL_SHMEM_SIZE_PHYS_NOMMU   0x00100000            /* 1MB */
+
+#endif  /* __GSL_HALCONFIG_H */
diff --git a/drivers/mxc/amd-gpu/include/gsl_intrmgr.h b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h
new file mode 100644
index 00000000000..f46f6d8e6a8
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h
@@ -0,0 +1,104 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_INTRMGR_H
+#define __GSL_INTRMGR_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// -------------------------------------
+// block which can generate an interrupt
+// -------------------------------------
+typedef enum _gsl_intrblock_t
+{
+    GSL_INTR_BLOCK_YDX_MH = 0,
+    GSL_INTR_BLOCK_YDX_CP,
+    GSL_INTR_BLOCK_YDX_RBBM,
+    GSL_INTR_BLOCK_YDX_SQ,
+    GSL_INTR_BLOCK_G12,
+    GSL_INTR_BLOCK_G12_MH,
+
+    GSL_INTR_BLOCK_COUNT,
+} gsl_intrblock_t;
+
+// ------------------------
+// interrupt block register
+// ------------------------
+typedef struct _gsl_intrblock_reg_t
+{
+    gsl_intrblock_t  id;
+    gsl_intrid_t     first_id;
+    gsl_intrid_t     last_id;
+    unsigned int     status_reg;
+    unsigned int     clear_reg;
+    unsigned int     mask_reg;
+} gsl_intrblock_reg_t;
+
+// --------
+// callback
+// --------
+typedef void (*gsl_intr_callback_t)(gsl_intrid_t id, void *cookie);
+
+// -----------------
+// interrupt routine
+// -----------------
+typedef struct _gsl_intr_handler_t
+{
+    gsl_intr_callback_t callback;
+    void *              cookie;
+} gsl_intr_handler_t;
+
+// -----------------
+// interrupt manager
+// -----------------
+typedef struct _gsl_intr_t
+{
+    gsl_flags_t         flags;
+    gsl_device_t        *device;
+    unsigned int        enabled[GSL_INTR_BLOCK_COUNT];
+    gsl_intr_handler_t  handler[GSL_INTR_COUNT];
+    oshandle_t          evnt[GSL_INTR_COUNT];
+} gsl_intr_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int             kgsl_intr_init(gsl_device_t *device);
+int             kgsl_intr_close(gsl_device_t *device);
+int             kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie);
+int             kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id);
+int             kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id);
+int             kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id);
+int             kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id);
+void            kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id);
+
+#endif  // __GSL_INTMGR_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_ioctl.h b/drivers/mxc/amd-gpu/include/gsl_ioctl.h
new file mode 100644
index 00000000000..6a06f3e0aec
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_ioctl.h
@@ -0,0 +1,243 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _GSL_IOCTL_H
+#define _GSL_IOCTL_H
+
+#include "gsl_types.h"
+#include "gsl_properties.h"
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+typedef struct _kgsl_device_start_t {
+    gsl_deviceid_t  device_id;
+    gsl_flags_t flags;
+} kgsl_device_start_t;
+
+typedef struct _kgsl_device_stop_t {
+    gsl_deviceid_t  device_id;
+} kgsl_device_stop_t;
+
+typedef struct _kgsl_device_idle_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    timeout;
+} kgsl_device_idle_t;
+
+typedef struct _kgsl_device_isidle_t {
+    gsl_deviceid_t  device_id;
+} kgsl_device_isidle_t;
+
+typedef struct _kgsl_device_getproperty_t {
+    gsl_deviceid_t  device_id;
+    gsl_property_type_t type;
+    unsigned int    *value;
+    unsigned int    sizebytes;
+} kgsl_device_getproperty_t;
+
+typedef struct _kgsl_device_setproperty_t {
+    gsl_deviceid_t  device_id;
+    gsl_property_type_t type;
+    void        *value;
+    unsigned int    sizebytes;
+} kgsl_device_setproperty_t;
+
+typedef struct _kgsl_device_regread_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    offsetwords;
+    unsigned int    *value;
+} kgsl_device_regread_t;
+
+typedef struct _kgsl_device_regwrite_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    offsetwords;
+    unsigned int    value;
+} kgsl_device_regwrite_t;
+
+typedef struct _kgsl_device_waitirq_t {
+    gsl_deviceid_t  device_id;
+    gsl_intrid_t    intr_id;
+    unsigned int    *count;
+    unsigned int    timeout;
+} kgsl_device_waitirq_t;
+
+typedef struct _kgsl_cmdstream_issueibcmds_t {
+    gsl_deviceid_t  device_id;
+    int     drawctxt_index;
+    gpuaddr_t   ibaddr;
+    int     sizedwords;
+    gsl_timestamp_t *timestamp;
+    gsl_flags_t flags;
+} kgsl_cmdstream_issueibcmds_t;
+
+typedef struct _kgsl_cmdstream_readtimestamp_t {
+    gsl_deviceid_t  device_id;
+    gsl_timestamp_type_t    type;
+    gsl_timestamp_t *timestamp;
+} kgsl_cmdstream_readtimestamp_t;
+
+typedef struct _kgsl_cmdstream_freememontimestamp_t {
+    gsl_deviceid_t  device_id;
+    gsl_memdesc_t   *memdesc;
+    gsl_timestamp_t timestamp;
+    gsl_timestamp_type_t    type;
+} kgsl_cmdstream_freememontimestamp_t;
+
+typedef struct _kgsl_cmdstream_waittimestamp_t {
+    gsl_deviceid_t  device_id;
+	gsl_timestamp_t timestamp;
+    unsigned int    timeout;
+} kgsl_cmdstream_waittimestamp_t;
+
+typedef struct _kgsl_cmdwindow_write_t {
+    gsl_deviceid_t  device_id;
+    gsl_cmdwindow_t target;
+    unsigned int    addr;
+    unsigned int    data;
+} kgsl_cmdwindow_write_t;
+
+typedef struct _kgsl_context_create_t {
+    gsl_deviceid_t  device_id;
+    gsl_context_type_t  type;
+    unsigned int    *drawctxt_id;
+    gsl_flags_t flags;
+} kgsl_context_create_t;
+
+typedef struct _kgsl_context_destroy_t {
+    gsl_deviceid_t  device_id;
+    unsigned int    drawctxt_id;
+} kgsl_context_destroy_t;
+
+typedef struct _kgsl_drawctxt_bind_gmem_shadow_t {
+    gsl_deviceid_t device_id;
+    unsigned int drawctxt_id;
+    const gsl_rect_t* gmem_rect;
+    unsigned int shadow_x;
+    unsigned int shadow_y;
+    const gsl_buffer_desc_t* shadow_buffer;
+    unsigned int buffer_id;
+} kgsl_drawctxt_bind_gmem_shadow_t;
+
+typedef struct _kgsl_sharedmem_alloc_t {
+    gsl_deviceid_t  device_id;
+    gsl_flags_t flags;
+    int     sizebytes;
+    gsl_memdesc_t   *memdesc;
+} kgsl_sharedmem_alloc_t;
+
+typedef struct _kgsl_sharedmem_free_t {
+    gsl_memdesc_t   *memdesc;
+} kgsl_sharedmem_free_t;
+
+typedef struct _kgsl_sharedmem_read_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    *dst;
+    unsigned int    offsetbytes;
+    unsigned int    sizebytes;
+} kgsl_sharedmem_read_t;
+
+typedef struct _kgsl_sharedmem_write_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    offsetbytes;
+    unsigned int    *src;
+    unsigned int    sizebytes;
+} kgsl_sharedmem_write_t;
+
+typedef struct _kgsl_sharedmem_set_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    offsetbytes;
+    unsigned int    value;
+    unsigned int    sizebytes;
+} kgsl_sharedmem_set_t;
+
+typedef struct _kgsl_sharedmem_largestfreeblock_t {
+    gsl_deviceid_t  device_id;
+    gsl_flags_t flags;
+    unsigned int    *largestfreeblock;
+} kgsl_sharedmem_largestfreeblock_t;
+
+typedef struct _kgsl_sharedmem_cacheoperation_t {
+    const gsl_memdesc_t *memdesc;
+    unsigned int    offsetbytes;
+    unsigned int    sizebytes;
+    unsigned int    operation;
+} kgsl_sharedmem_cacheoperation_t;
+
+typedef struct _kgsl_sharedmem_fromhostpointer_t {
+    gsl_deviceid_t  device_id;
+    gsl_memdesc_t   *memdesc;
+    void        *hostptr;
+} kgsl_sharedmem_fromhostpointer_t;
+
+typedef struct _kgsl_add_timestamp_t {
+    gsl_deviceid_t device_id;
+    gsl_timestamp_t *timestamp;
+} kgsl_add_timestamp_t;
+
+typedef struct _kgsl_device_clock_t {
+    gsl_deviceid_t device; /* GSL_DEVICE_YAMATO = 1, GSL_DEVICE_G12 = 2 */
+    int enable; /* 0: disable, 1: enable */
+} kgsl_device_clock_t;
+
+//////////////////////////////////////////////////////////////////////////////
+// ioctl numbers
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_MAGIC                               0xF9
+#define IOCTL_KGSL_DEVICE_START                 _IOW(GSL_MAGIC, 0x20, struct _kgsl_device_start_t)
+#define IOCTL_KGSL_DEVICE_STOP                  _IOW(GSL_MAGIC, 0x21, struct _kgsl_device_stop_t)
+#define IOCTL_KGSL_DEVICE_IDLE                  _IOW(GSL_MAGIC, 0x22, struct _kgsl_device_idle_t)
+#define IOCTL_KGSL_DEVICE_ISIDLE                _IOR(GSL_MAGIC, 0x23, struct _kgsl_device_isidle_t)
+#define IOCTL_KGSL_DEVICE_GETPROPERTY           _IOWR(GSL_MAGIC, 0x24, struct _kgsl_device_getproperty_t)
+#define IOCTL_KGSL_DEVICE_SETPROPERTY           _IOW(GSL_MAGIC, 0x25, struct _kgsl_device_setproperty_t)
+#define IOCTL_KGSL_DEVICE_REGREAD               _IOWR(GSL_MAGIC, 0x26, struct _kgsl_device_regread_t)
+#define IOCTL_KGSL_DEVICE_REGWRITE              _IOW(GSL_MAGIC, 0x27, struct _kgsl_device_regwrite_t)
+#define IOCTL_KGSL_DEVICE_WAITIRQ               _IOWR(GSL_MAGIC, 0x28, struct _kgsl_device_waitirq_t)
+#define IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS        _IOWR(GSL_MAGIC, 0x29, struct _kgsl_cmdstream_issueibcmds_t)
+#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP      _IOWR(GSL_MAGIC, 0x2A, struct _kgsl_cmdstream_readtimestamp_t)
+#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(GSL_MAGIC, 0x2B, struct _kgsl_cmdstream_freememontimestamp_t)
+#define IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP      _IOW(GSL_MAGIC, 0x2C, struct _kgsl_cmdstream_waittimestamp_t)
+#define IOCTL_KGSL_CMDWINDOW_WRITE              _IOW(GSL_MAGIC, 0x2D, struct _kgsl_cmdwindow_write_t)
+#define IOCTL_KGSL_CONTEXT_CREATE               _IOWR(GSL_MAGIC, 0x2E, struct _kgsl_context_create_t)
+#define IOCTL_KGSL_CONTEXT_DESTROY              _IOW(GSL_MAGIC, 0x2F, struct _kgsl_context_destroy_t)
+#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW    _IOW(GSL_MAGIC, 0x30, struct _kgsl_drawctxt_bind_gmem_shadow_t)
+#define IOCTL_KGSL_SHAREDMEM_ALLOC              _IOWR(GSL_MAGIC, 0x31, struct _kgsl_sharedmem_alloc_t)
+#define IOCTL_KGSL_SHAREDMEM_FREE               _IOW(GSL_MAGIC, 0x32, struct _kgsl_sharedmem_free_t)
+#define IOCTL_KGSL_SHAREDMEM_READ               _IOWR(GSL_MAGIC, 0x33, struct _kgsl_sharedmem_read_t)
+#define IOCTL_KGSL_SHAREDMEM_WRITE              _IOW(GSL_MAGIC, 0x34, struct _kgsl_sharedmem_write_t)
+#define IOCTL_KGSL_SHAREDMEM_SET                _IOW(GSL_MAGIC, 0x35, struct _kgsl_sharedmem_set_t)
+#define IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK   _IOWR(GSL_MAGIC, 0x36, struct _kgsl_sharedmem_largestfreeblock_t)
+#define IOCTL_KGSL_SHAREDMEM_CACHEOPERATION     _IOW(GSL_MAGIC, 0x37, struct _kgsl_sharedmem_cacheoperation_t)
+#define IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER    _IOW(GSL_MAGIC, 0x38, struct _kgsl_sharedmem_fromhostpointer_t)
+#define IOCTL_KGSL_ADD_TIMESTAMP                _IOWR(GSL_MAGIC, 0x39, struct _kgsl_add_timestamp_t)
+#define IOCTL_KGSL_DRIVER_EXIT		        _IOWR(GSL_MAGIC, 0x3A, NULL)
+#define IOCTL_KGSL_DEVICE_CLOCK			_IOWR(GSL_MAGIC, 0x60, struct _kgsl_device_clock_t)
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/gsl_log.h b/drivers/mxc/amd-gpu/include/gsl_log.h
new file mode 100644
index 00000000000..dbb7e4c6ef9
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_log.h
@@ -0,0 +1,74 @@
+/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_LOG_H
+#define __GSL_LOG_H
+
+#define KGSL_LOG_GROUP_DRIVER       0x00000001
+#define KGSL_LOG_GROUP_DEVICE       0x00000002
+#define KGSL_LOG_GROUP_COMMAND      0x00000004
+#define KGSL_LOG_GROUP_CONTEXT      0x00000008
+#define KGSL_LOG_GROUP_MEMORY       0x00000010
+#define KGSL_LOG_GROUP_ALL          0x000000ff
+
+#define KGSL_LOG_LEVEL_ALL          0x0000ff00
+#define KGSL_LOG_LEVEL_TRACE        0x00003f00
+#define KGSL_LOG_LEVEL_DEBUG        0x00001f00
+#define KGSL_LOG_LEVEL_INFO         0x00000f00
+#define KGSL_LOG_LEVEL_WARN         0x00000700
+#define KGSL_LOG_LEVEL_ERROR        0x00000300
+#define KGSL_LOG_LEVEL_FATAL        0x00000100
+
+#define KGSL_LOG_TIMESTAMP          0x00010000
+#define KGSL_LOG_THREAD_ID          0x00020000
+#define KGSL_LOG_PROCESS_ID         0x00040000
+
+#ifdef GSL_LOG
+
+int kgsl_log_init(void);
+int kgsl_log_close(void);
+int kgsl_log_open_stdout( unsigned int log_flags );
+int kgsl_log_write( unsigned int log_flags, char* format, ... );
+int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags );
+int kgsl_log_open_file( char* filename, unsigned int log_flags );
+int kgsl_log_flush_membuf( char* filename, int memBufId );
+
+#else
+
+// Empty function definitions
+OSINLINE int kgsl_log_init(void) { return GSL_SUCCESS; }
+OSINLINE int kgsl_log_close(void) { return GSL_SUCCESS; }
+OSINLINE int kgsl_log_open_stdout( unsigned int log_flags ) { (void)log_flags; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_write( unsigned int log_flags, char* format, ... ) { (void)log_flags; (void)format; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags ) { (void)memBufId; (void)log_flags; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_open_file( char* filename, unsigned int log_flags ) { (void)filename; (void)log_flags; return GSL_SUCCESS; }
+OSINLINE int kgsl_log_flush_membuf( char* filename, int memBufId ) { (void) filename; (void) memBufId; return GSL_SUCCESS; }
+
+#endif
+
+#endif // __GSL_LOG_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_memmgr.h b/drivers/mxc/amd-gpu/include/gsl_memmgr.h
new file mode 100644
index 00000000000..ef9ad93ea96
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_memmgr.h
@@ -0,0 +1,122 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_MEMMGR_H
+#define __GSL_MEMMGR_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#define GSL_MEMARENA_NODE_POOL_MAX      32                              // max is 32
+
+#define GSL_MEMARENA_PAGE_DIST_MAX      12                              // 4MB
+
+//#define GSL_MEMARENA_NODE_POOL_ENABLED
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// ------------------
+// memory arena stats
+// ------------------
+typedef struct _gsl_memarena_stats_t {
+    __int64  bytes_read;
+    __int64  bytes_written;
+    __int64  allocs_success;
+    __int64  allocs_fail;
+    __int64  frees;
+    __int64  allocs_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX]; // 0=0--(4K-1), 1=4--(8K-1), 2=8--(16K-1),... max-1=(GSL_PAGESIZE<<(max-1))--infinity
+    __int64  frees_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX];
+} gsl_memarena_stats_t;
+
+// ------------
+// memory block
+// ------------
+typedef struct _memblk_t {
+    unsigned int      blkaddr;
+    unsigned int      blksize;
+    struct _memblk_t  *next;
+    struct _memblk_t  *prev;
+    int               nodepoolindex;
+} memblk_t;
+
+// ----------------------
+// memory block free list
+// ----------------------
+typedef struct _gsl_freelist_t {
+    memblk_t  *head;
+    memblk_t  *allocrover;
+    memblk_t  *freerover;
+} gsl_freelist_t;
+
+// ----------------------
+// memory block node pool
+// ----------------------
+typedef struct _gsl_nodepool_t {
+    unsigned int            priv;
+    memblk_t                memblk[GSL_MEMARENA_NODE_POOL_MAX];
+    struct _gsl_nodepool_t  *next;
+    struct _gsl_nodepool_t  *prev;
+} gsl_nodepool_t;
+
+// -------------------
+// memory arena object
+// -------------------
+typedef struct _gsl_memarena_t {
+    oshandle_t      mutex;
+    unsigned int    gpubaseaddr;
+    unsigned int    hostbaseaddr;
+    unsigned int    sizebytes;
+    gsl_nodepool_t  *nodepool;
+    gsl_freelist_t  freelist;
+    unsigned int    priv;
+
+#ifdef GSL_STATS_MEM
+    gsl_memarena_stats_t  stats;
+#endif // GSL_STATS_MEM
+
+} gsl_memarena_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+gsl_memarena_t* kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes);
+int             kgsl_memarena_destroy(gsl_memarena_t *memarena);
+int             kgsl_memarena_isvirtualized(gsl_memarena_t *memarena);
+int             kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats);
+int             kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc);
+void            kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc);
+void*           kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr);
+unsigned int    kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr);
+unsigned int    kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags);
+
+#endif  // __GSL_MEMMGR_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_mmu.h b/drivers/mxc/amd-gpu/include/gsl_mmu.h
new file mode 100644
index 00000000000..ddb2243b58d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_mmu.h
@@ -0,0 +1,186 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_MMU_H
+#define __GSL_MMU_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+// defines
+//////////////////////////////////////////////////////////////////////////////
+#ifdef GSL_STATS_MMU
+#define GSL_MMU_STATS(x) x
+#else
+#define GSL_MMU_STATS(x)
+#endif // GSL_STATS_MMU
+
+#ifdef GSL_MMU_PAGETABLE_PERPROCESS
+#define GSL_MMU_PAGETABLE_MAX               GSL_CALLER_PROCESS_MAX      // all device mmu's share a single page table per process
+#else
+#define GSL_MMU_PAGETABLE_MAX               1                           // all device mmu's share a single global page table
+#endif // GSL_MMU_PAGETABLE_PERPROCESS
+
+#define GSL_PT_SUPER_PTE                    8
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef _DEBUG
+// ---------
+// mmu debug
+// ---------
+typedef struct _gsl_mmu_debug_t {
+    unsigned int  config;
+    unsigned int  mpu_base;
+    unsigned int  mpu_end;
+    unsigned int  va_range;
+    unsigned int  pt_base;
+    unsigned int  page_fault;
+    unsigned int  trans_error;
+    unsigned int  invalidate;
+} gsl_mmu_debug_t;
+#endif // _DEBUG
+
+// ------------
+// mmu register
+// ------------
+typedef struct _gsl_mmu_reg_t
+{
+    unsigned int  CONFIG;
+    unsigned int  MPU_BASE;
+    unsigned int  MPU_END;
+    unsigned int  VA_RANGE;
+    unsigned int  PT_BASE;
+    unsigned int  PAGE_FAULT;
+    unsigned int  TRAN_ERROR;
+    unsigned int  INVALIDATE;
+} gsl_mmu_reg_t;
+
+// ------------
+// mh interrupt
+// ------------
+typedef struct _gsl_mh_intr_t
+{
+    gsl_intrid_t  AXI_READ_ERROR;
+    gsl_intrid_t  AXI_WRITE_ERROR;
+    gsl_intrid_t  MMU_PAGE_FAULT;
+} gsl_mh_intr_t;
+
+// ----------------
+// page table stats
+// ----------------
+typedef struct _gsl_ptstats_t {
+    __int64  maps;
+    __int64  unmaps;
+	__int64  switches;
+} gsl_ptstats_t;
+
+// ---------
+// mmu stats
+// ---------
+typedef struct _gsl_mmustats_t {
+	gsl_ptstats_t  pt;
+	__int64        tlbflushes;
+} gsl_mmustats_t;
+
+// -----------------
+// page table object
+// -----------------
+typedef struct _gsl_pagetable_t {
+	unsigned int   pid;
+    unsigned int   refcnt;
+    gsl_memdesc_t  base;
+    gpuaddr_t      va_base;
+    unsigned int   va_range;
+    unsigned int   last_superpte;
+    unsigned int   max_entries;
+} gsl_pagetable_t;
+
+// -------------------------
+// tlb flush filter object
+// -------------------------
+typedef struct _gsl_tlbflushfilter_t {
+    unsigned int  *base;
+    unsigned int  size;
+} gsl_tlbflushfilter_t;
+
+// ----------
+// mmu object
+// ----------
+typedef struct _gsl_mmu_t {
+#ifdef GSL_LOCKING_FINEGRAIN
+    oshandle_t            mutex;
+#endif
+    unsigned int          refcnt;
+    gsl_flags_t           flags;
+    gsl_device_t          *device;
+    unsigned int          config;
+    gpuaddr_t             mpu_base;
+    int                   mpu_range;
+    gpuaddr_t             va_base;
+    unsigned int          va_range;
+    gsl_memdesc_t         dummyspace;
+    gsl_tlbflushfilter_t  tlbflushfilter;
+    gsl_pagetable_t       *hwpagetable;                     // current page table object being used by device mmu
+    gsl_pagetable_t       *pagetable[GSL_MMU_PAGETABLE_MAX];    // page table object table
+#ifdef GSL_STATS_MMU
+	gsl_mmustats_t        stats;
+#endif  // GSL_STATS_MMU
+} gsl_mmu_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  inline functions
+//////////////////////////////////////////////////////////////////////////////
+OSINLINE int
+kgsl_mmu_isenabled(gsl_mmu_t *mmu)
+{
+    // address translation enabled
+    int enabled = ((mmu)->flags & GSL_FLAGS_STARTED) ? 1 : 0;
+
+    return (enabled);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int    kgsl_mmu_init(gsl_device_t *device);
+int    kgsl_mmu_close(gsl_device_t *device);
+int    kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid);
+int    kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid);
+int    kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid);
+int    kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid);
+int    kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid);
+int    kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid);
+int    kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats);
+int    kgsl_mmu_bist(gsl_mmu_t *mmu);
+
+#endif // __GSL_MMU_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h
new file mode 100644
index 00000000000..57f6297735e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h
@@ -0,0 +1,250 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_RINGBUFFER_H
+#define __GSL_RINGBUFFER_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+// ringbuffer sizes log2quadword
+#define     GSL_RB_SIZE_8                        0
+#define     GSL_RB_SIZE_16                       1
+#define     GSL_RB_SIZE_32                       2
+#define     GSL_RB_SIZE_64                       3
+#define     GSL_RB_SIZE_128                      4
+#define     GSL_RB_SIZE_256                      5
+#define     GSL_RB_SIZE_512                      6
+#define     GSL_RB_SIZE_1K                       7
+#define     GSL_RB_SIZE_2K                       8
+#define     GSL_RB_SIZE_4K                       9
+#define     GSL_RB_SIZE_8K                      10
+#define     GSL_RB_SIZE_16K                     11
+#define     GSL_RB_SIZE_32K                     12
+#define     GSL_RB_SIZE_64K                     13
+#define     GSL_RB_SIZE_128K                    14
+#define     GSL_RB_SIZE_256K                    15
+#define     GSL_RB_SIZE_512K                    16
+#define     GSL_RB_SIZE_1M                      17
+#define     GSL_RB_SIZE_2M                      18
+#define     GSL_RB_SIZE_4M                      19
+
+// offsets into memptrs
+#define GSL_RB_MEMPTRS_RPTR_OFFSET              0
+#define GSL_RB_MEMPTRS_WPTRPOLL_OFFSET          (GSL_RB_MEMPTRS_RPTR_OFFSET + sizeof(unsigned int))
+
+// dword base address of the GFX decode space
+#define GSL_HAL_SUBBLOCK_OFFSET(reg)            ((unsigned int)((reg) - (0x2000)))
+
+// CP timestamp register
+#define mmCP_TIMESTAMP                          mmSCRATCH_REG0
+
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef _DEBUG
+// ----------------
+// ringbuffer debug
+// ----------------
+typedef struct _gsl_rb_debug_t {
+    unsigned int        pm4_ucode_rel;
+    unsigned int        pfp_ucode_rel;
+    unsigned int        cp_rb_base;
+    cp_rb_cntl_u        cp_rb_cntl;
+    unsigned int        cp_rb_rptr_addr;
+    unsigned int        cp_rb_rptr;
+    unsigned int        cp_rb_wptr;
+    unsigned int        cp_rb_wptr_base;
+    scratch_umsk_u      scratch_umsk;
+    unsigned int        scratch_addr;
+    cp_me_cntl_u        cp_me_cntl;
+    cp_me_status_u      cp_me_status;
+    cp_debug_u          cp_debug;
+    cp_stat_u           cp_stat;
+    rbbm_status_u       rbbm_status;
+    unsigned int        sop_timestamp;
+    unsigned int        eop_timestamp;
+} gsl_rb_debug_t;
+#endif // _DEBUG
+
+// -------------------
+// ringbuffer watchdog
+// -------------------
+typedef struct _gsl_rbwatchdog_t {
+    gsl_flags_t   flags;
+    unsigned int  rptr_sample;
+} gsl_rbwatchdog_t;
+
+// ------------------
+// memory ptr objects
+// ------------------
+#ifdef __GNUC__
+#pragma pack(push, 1)
+#else
+#pragma pack(push)
+#pragma pack(1)
+#endif
+typedef struct _gsl_rbmemptrs_t {
+    volatile int  rptr;
+    int           wptr_poll;
+} gsl_rbmemptrs_t;
+#pragma pack(pop)
+
+// -----
+// stats
+// -----
+typedef struct _gsl_rbstats_t {
+    __int64  wraps;
+    __int64  issues;
+    __int64  wordstotal;
+} gsl_rbstats_t;
+
+
+// -----------------
+// ringbuffer object
+// -----------------
+typedef struct _gsl_ringbuffer_t {
+
+    gsl_device_t      *device;
+    gsl_flags_t       flags;
+#ifdef GSL_LOCKING_FINEGRAIN
+    oshandle_t        mutex;
+#endif
+    gsl_memdesc_t     buffer_desc;              // allocated memory descriptor
+    gsl_memdesc_t     memptrs_desc;
+
+    gsl_rbmemptrs_t   *memptrs;
+
+    unsigned int      sizedwords;               // ring buffer size dwords
+    unsigned int      blksizequadwords;
+
+    unsigned int      wptr;                     // write pointer offset in dwords from baseaddr
+    unsigned int      rptr;                     // read pointer  offset in dwords from baseaddr
+    gsl_timestamp_t   timestamp;
+
+
+    gsl_rbwatchdog_t  watchdog;
+
+#ifdef GSL_STATS_RINGBUFFER
+    gsl_rbstats_t     stats;
+#endif // GSL_STATS_RINGBUFFER
+
+} gsl_ringbuffer_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+// macros
+//////////////////////////////////////////////////////////////////////////////
+
+#ifdef GSL_LOCKING_FINEGRAIN
+#define GSL_RB_MUTEX_CREATE()               rb->mutex = kos_mutex_create("gsl_ringbuffer"); \
+                                            if (!rb->mutex) {return (GSL_FAILURE);}
+#define GSL_RB_MUTEX_LOCK()                 kos_mutex_lock(rb->mutex)
+#define GSL_RB_MUTEX_UNLOCK()               kos_mutex_unlock(rb->mutex)
+#define GSL_RB_MUTEX_FREE()                 kos_mutex_free(rb->mutex); rb->mutex = 0;
+#else
+#define GSL_RB_MUTEX_CREATE()
+#define GSL_RB_MUTEX_LOCK()
+#define GSL_RB_MUTEX_UNLOCK()
+#define GSL_RB_MUTEX_FREE()
+#endif
+
+// ----------
+// ring write
+// ----------
+#define GSL_RB_WRITE(ring, data)        \
+      KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_WRT, (unsigned int)ring, data, 0, "GSL_RB_WRITE")); \
+      *(unsigned int *)(ring)++ = (unsigned int)(data);
+
+// ---------
+// timestamp
+// ---------
+#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+#define GSL_RB_USE_MEM_TIMESTAMP
+#endif //GSL_DEVICE_SHADOW_MEMSTORE_TO_USER
+
+#ifdef  GSL_RB_USE_MEM_TIMESTAMP
+#define GSL_RB_MEMPTRS_SCRATCH_MASK         0x1     // enable timestamp (...scratch0) memory shadowing
+#define GSL_RB_INIT_TIMESTAMP(rb)
+
+#else
+#define GSL_RB_MEMPTRS_SCRATCH_MASK         0x0     // disable
+#define GSL_RB_INIT_TIMESTAMP(rb)           kgsl_device_regwrite((rb)->device->id, mmCP_TIMESTAMP, 0);
+#endif // GSL_RB_USE_MEMTIMESTAMP
+
+// --------
+// mem rptr
+// --------
+#ifdef  GSL_RB_USE_MEM_RPTR
+#define GSL_RB_CNTL_NO_UPDATE               0x0     // enable
+#define GSL_RB_GET_READPTR(rb, data)        kgsl_sharedmem_read0(&(rb)->memptrs_desc, (data), GSL_RB_MEMPTRS_RPTR_OFFSET, 4, false)
+#else
+#define GSL_RB_CNTL_NO_UPDATE               0x1     // disable
+#define GSL_RB_GET_READPTR(rb, data)        (rb)->device->fbtl.device_regread((rb)->device, mmCP_RB_RPTR,(data))
+#endif // GSL_RB_USE_MEMRPTR
+
+// ------------
+// wptr polling
+// ------------
+#ifdef  GSL_RB_USE_WPTR_POLLING
+#define GSL_RB_CNTL_POLL_EN                 0x1     // enable
+#define GSL_RB_UPDATE_WPTR_POLLING(rb)      (rb)->memptrs->wptr_poll = (rb)->wptr
+#else
+#define GSL_RB_CNTL_POLL_EN                 0x0     // disable
+#define GSL_RB_UPDATE_WPTR_POLLING(rb)
+#endif  // GSL_RB_USE_WPTR_POLLING
+
+// -----
+// stats
+// -----
+#ifdef GSL_STATS_RINGBUFFER
+#define GSL_RB_STATS(x) x
+#else
+#define GSL_RB_STATS(x)
+#endif // GSL_STATS_RINGBUFFER
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int             kgsl_ringbuffer_init(gsl_device_t *device);
+int             kgsl_ringbuffer_close(gsl_ringbuffer_t *rb);
+int             kgsl_ringbuffer_start(gsl_ringbuffer_t *rb);
+int             kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb);
+gsl_timestamp_t	kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmdaddr, int sizedwords, unsigned int pid);
+int             kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags);
+void            kgsl_ringbuffer_watchdog(void);
+
+int             kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats);
+int             kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb);
+
+#endif  // __GSL_RINGBUFFER_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_sharedmem.h b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h
new file mode 100644
index 00000000000..bb9692cc1e4
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h
@@ -0,0 +1,110 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_SHAREDMEM_H
+#define __GSL_SHAREDMEM_H
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+
+#define GSL_APERTURE_MASK                   0x000000FF
+#define GSL_DEVICEID_MASK                   0x0000FF00
+#define GSL_EXTALLOC_MASK                   0x000F0000
+
+#define GSL_APERTURE_SHIFT                  0
+#define GSL_DEVICEID_SHIFT                  8
+#define GSL_EXTALLOC_SHIFT                  16
+
+#define GSL_APERTURE_GETGPUADDR(shmem, aperture_index)  \
+    shmem.apertures[aperture_index].memarena->gpubaseaddr;
+
+#define GSL_APERTURE_GETHOSTADDR(shmem, aperture_index) \
+    shmem.apertures[aperture_index].memarena->hostbaseaddr;
+
+//////////////////////////////////////////////////////////////////////////////
+//  types
+//////////////////////////////////////////////////////////////////////////////
+
+// ---------------------
+// memory aperture stats
+// ---------------------
+typedef struct _gsl_aperture_stats_t
+{
+    gsl_apertureid_t      id;
+    gsl_channelid_t       channel;
+    gsl_memarena_stats_t  memarena;
+} gsl_aperture_stats_t;
+
+// -------------------
+// shared memory stats
+// -------------------
+typedef struct _gsl_sharedmem_stats_t
+{
+    gsl_aperture_stats_t  apertures[GSL_SHMEM_MAX_APERTURES];
+} gsl_sharedmem_stats_t;
+
+// ---------------
+// memory aperture
+// ---------------
+typedef struct _gsl_aperture_t
+{
+    gsl_apertureid_t  id;
+    gsl_channelid_t   channel;
+    int               numbanks;
+    gsl_memarena_t    *memarena;
+} gsl_aperture_t;
+
+// --------------------
+// shared memory object
+// --------------------
+typedef struct _gsl_sharedmem_t
+{
+    gsl_flags_t     flags;
+    unsigned int    priv;
+    int             numapertures;
+    gsl_aperture_t  apertures[GSL_SHMEM_MAX_APERTURES]; 
+    int             aperturelookup[GSL_APERTURE_MAX][GSL_CHANNEL_MAX];
+} gsl_sharedmem_t;
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  prototypes
+//////////////////////////////////////////////////////////////////////////////
+int             kgsl_sharedmem_init(gsl_sharedmem_t *shmem);
+int             kgsl_sharedmem_close(gsl_sharedmem_t *shmem);
+int             kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc);
+int             kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid);
+int             kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace);
+int             kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace);
+int             kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes);
+int             kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats);
+unsigned int    kgsl_sharedmem_convertaddr(unsigned int addr, int type);
+
+#endif // __GSL_SHAREDMEM_H
diff --git a/drivers/mxc/amd-gpu/include/gsl_tbdump.h b/drivers/mxc/amd-gpu/include/gsl_tbdump.h
new file mode 100644
index 00000000000..53b30a8442e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/gsl_tbdump.h
@@ -0,0 +1,38 @@
+/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora Forum nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_TBDUMP_H
+#define __GSL_TBDUMP_H
+
+void tbdump_open(char* filename);
+void tbdump_close();
+void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes);
+void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes);
+void tbdump_slavewrite(unsigned int addr, unsigned int value);
+
+#endif // __GSL_TBDUMP_H
diff --git a/drivers/mxc/amd-gpu/include/reg/g12_reg.h b/drivers/mxc/amd-gpu/include/reg/g12_reg.h
new file mode 100644
index 00000000000..d12d419822a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/g12_reg.h
@@ -0,0 +1,41 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _G12_H
+#define _G12_H
+
+#ifdef _Z180
+#include "vgc/vgregs_z180.h"
+#include "vgc/vgenums_z180.h"
+#else
+#include "vgc/vgregs_z160.h"
+#include "vgc/vgenums_z160.h"
+#endif
+
+#endif // _G12_H
diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h
new file mode 100644
index 00000000000..911c22fbbba
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h
@@ -0,0 +1,291 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __REGS_ENUMS_H
+#define __REGS_ENUMS_H
+
+typedef enum _BB_CULL {
+    BB_CULL_NONE                     = 0,
+    BB_CULL_CW                       = 1,
+    BB_CULL_CCW                      = 2,
+} BB_CULL;
+
+typedef enum _BB_TEXTUREADDRESS {
+    BB_TADDRESS_WRAP                 = 0,
+    BB_TADDRESS_CLAMP                = 1,
+    BB_TADDRESS_BORDER               = 2,
+    BB_TADDRESS_MIRROR               = 4,
+    BB_TADDRESS_MIRRORCLAMP          = 5,   // Not supported on G3x cores
+    BB_TADDRESS_MIRRORBORDER         = 6,   // Not supported on G3x cores
+} BB_TEXTUREADDRESS;
+
+typedef enum _BB_TEXTYPE {
+    BB_TEXTYPE_4444                  = 0,
+    BB_TEXTYPE_1555                  = 1,
+    BB_TEXTYPE_5551                  = 2,
+    BB_TEXTYPE_565                   = 3,
+    BB_TEXTYPE_8888                  = 4,
+    BB_TEXTYPE_8                     = 5,
+    BB_TEXTYPE_88                    = 6,
+    BB_TEXTYPE_4                     = 7,
+    BB_TEXTYPE_44                    = 8,
+    BB_TEXTYPE_UYVY                  = 9,
+    BB_TEXTYPE_YUY2                  = 10,
+    BB_TEXTYPE_YVYU                  = 11,
+    BB_TEXTYPE_DXT1                  = 12,
+    BB_TEXTYPE_PACKMAN               = 13,
+    BB_TEXTYPE_PACKMAN_ALPHA4        = 14,
+    BB_TEXTYPE_1F16                  = 15,
+    BB_TEXTYPE_2F16                  = 16,
+    BB_TEXTYPE_4F16                  = 17,
+    BB_TEXTYPE_IPACKMAN_RGB          = 18,
+    BB_TEXTYPE_IPACKMAN_RGBA         = 19,
+} BB_TEXTYPE;
+
+typedef enum _BB_CMPFUNC {
+    BB_CMP_NEVER                     = 0,
+    BB_CMP_LESS                      = 1,
+    BB_CMP_EQUAL                     = 2,
+    BB_CMP_LESSEQUAL                 = 3,
+    BB_CMP_GREATER                   = 4,
+    BB_CMP_NOTEQUAL                  = 5,
+    BB_CMP_GREATEREQUAL              = 6,
+    BB_CMP_ALWAYS                    = 7,
+} BB_CMPFUNC;
+
+typedef enum _BB_STENCILOP {
+    BB_STENCILOP_KEEP                = 0,
+    BB_STENCILOP_ZERO                = 1,
+    BB_STENCILOP_REPLACE             = 2,
+    BB_STENCILOP_INCRSAT             = 3,
+    BB_STENCILOP_DECRSAT             = 4,
+    BB_STENCILOP_INVERT              = 5,
+    BB_STENCILOP_INCR                = 6,
+    BB_STENCILOP_DECR                = 7,
+} BB_STENCILOP;
+
+typedef enum _BB_PRIMITIVETYPE {
+    BB_PT_POINTLIST                  = 0,
+    BB_PT_LINELIST                   = 1,
+    BB_PT_LINESTRIP                  = 2,
+    BB_PT_TRIANGLELIST               = 3,
+    BB_PT_TRIANGLESTRIP              = 4,
+    BB_PT_TRIANGLEFAN                = 5,
+} BB_PRIMITIVETYPE;
+
+typedef enum _BB_TEXTUREFILTERTYPE {
+    BB_TEXF_NONE                     = 0,   // filtering disabled (valid for mip filter only)
+    BB_TEXF_POINT                    = 1,   // nearest
+    BB_TEXF_LINEAR                   = 2,   // linear interpolation
+} BB_TEXTUREFILTERTYPE;
+
+typedef enum _BB_BUFFER {
+    BB_BUFFER_PPCODE                 = 0,   // Pixel processor code
+    BB_BUFFER_UNUSED                 = 1,   // Unused
+    BB_BUFFER_CBUF                   = 2,   // Color buffer
+    BB_BUFFER_ZBUF                   = 3,   // Z buffer
+    BB_BUFFER_AUXBUF0                = 4,   // AUX0 buffer
+    BB_BUFFER_AUXBUF1                = 5,   // AUX1 buffer
+    BB_BUFFER_AUXBUF2                = 6,   // AUX2 buffer
+    BB_BUFFER_AUXBUF3                = 7,   // AUX3 buffer
+} BB_BUFFER;
+
+typedef enum _BB_COLORFORMAT {
+    BB_COLOR_ARGB4444                = 0,
+    BB_COLOR_ARGB0565                = 1,
+    BB_COLOR_ARGB1555                = 2,
+    BB_COLOR_RGBA5551                = 3,
+    BB_COLOR_ARGB8888                = 4,
+    BB_COLOR_R16                     = 5,
+    BB_COLOR_RG1616                  = 6,
+    BB_COLOR_ARGB16161616            = 7,
+    BB_COLOR_D16                     = 8,
+    BB_COLOR_S4D12                   = 9,
+    BB_COLOR_S1D15                   = 10,
+    BB_COLOR_X8D24                   = 11,
+    BB_COLOR_S8D24                   = 12,
+    BB_COLOR_X2D30                   = 13,
+} BB_COLORFORMAT;
+
+typedef enum _BB_PP_REGCONFIG {
+    BB_PP_REGCONFIG_1                = 0,
+    BB_PP_REGCONFIG_2                = 1,
+    BB_PP_REGCONFIG_3                = 8,
+    BB_PP_REGCONFIG_4                = 2,
+    BB_PP_REGCONFIG_6                = 9,
+    BB_PP_REGCONFIG_8                = 3,
+    BB_PP_REGCONFIG_12               = 10,
+    BB_PP_REGCONFIG_16               = 4,
+    BB_PP_REGCONFIG_24               = 11,
+    BB_PP_REGCONFIG_32               = 5,
+} BB_PP_REGCONFIG;
+
+typedef enum _G2D_read_t {
+    G2D_READ_DST                     = 0,
+    G2D_READ_SRC1                    = 1,
+    G2D_READ_SRC2                    = 2,
+    G2D_READ_SRC3                    = 3,
+} G2D_read_t;
+
+typedef enum _G2D_format_t {
+    G2D_1                            = 0,   // foreground & background
+    G2D_1BW                          = 1,   // black & white
+    G2D_4                            = 2,
+    G2D_8                            = 3,   // alpha
+    G2D_4444                         = 4,
+    G2D_1555                         = 5,
+    G2D_0565                         = 6,
+    G2D_8888                         = 7,
+    G2D_YUY2                         = 8,
+    G2D_UYVY                         = 9,
+    G2D_YVYU                         = 10,
+    G2D_4444_RGBA                    = 11,
+    G2D_5551_RGBA                    = 12,
+    G2D_8888_RGBA                    = 13,
+    G2D_A8                           = 14,  // for alpha texture only
+} G2D_format_t;
+
+typedef enum _G2D_wrap_t {
+    G2D_WRAP_CLAMP                   = 0,
+    G2D_WRAP_REPEAT                  = 1,
+    G2D_WRAP_MIRROR                  = 2,
+    G2D_WRAP_BORDER                  = 3,
+} G2D_wrap_t;
+
+typedef enum _G2D_BLEND_OP {
+    G2D_BLENDOP_ADD                  = 0,
+    G2D_BLENDOP_SUB                  = 1,
+    G2D_BLENDOP_MIN                  = 2,
+    G2D_BLENDOP_MAX                  = 3,
+} G2D_BLEND_OP;
+
+typedef enum _G2D_GRAD_OP {
+    G2D_GRADOP_DOT                   = 0,
+    G2D_GRADOP_RCP                   = 1,
+    G2D_GRADOP_SQRTMUL               = 2,
+    G2D_GRADOP_SQRTADD               = 3,
+} G2D_GRAD_OP;
+
+typedef enum _G2D_BLEND_SRC {
+    G2D_BLENDSRC_ZERO                = 0,   // One with invert
+    G2D_BLENDSRC_SOURCE              = 1,   // Paint with coverage alpha applied
+    G2D_BLENDSRC_DESTINATION         = 2,
+    G2D_BLENDSRC_IMAGE               = 3,   // Second texture
+    G2D_BLENDSRC_TEMP0               = 4,
+    G2D_BLENDSRC_TEMP1               = 5,
+    G2D_BLENDSRC_TEMP2               = 6,
+} G2D_BLEND_SRC;
+
+typedef enum _G2D_BLEND_DST {
+    G2D_BLENDDST_IGNORE              = 0,   // Ignore destination
+    G2D_BLENDDST_TEMP0               = 1,
+    G2D_BLENDDST_TEMP1               = 2,
+    G2D_BLENDDST_TEMP2               = 3,
+} G2D_BLEND_DST;
+
+typedef enum _G2D_BLEND_CONST {
+    G2D_BLENDSRC_CONST0              = 0,
+    G2D_BLENDSRC_CONST1              = 1,
+    G2D_BLENDSRC_CONST2              = 2,
+    G2D_BLENDSRC_CONST3              = 3,
+    G2D_BLENDSRC_CONST4              = 4,
+    G2D_BLENDSRC_CONST5              = 5,
+    G2D_BLENDSRC_CONST6              = 6,
+    G2D_BLENDSRC_CONST7              = 7,
+} G2D_BLEND_CONST;
+
+typedef enum _V3_NEXTCMD {
+    VGV3_NEXTCMD_CONTINUE            = 0,   // Continue reading at current address, COUNT gives size of next packet.
+    VGV3_NEXTCMD_JUMP                = 1,   // Jump to CALLADDR, COUNT gives size of next packet.
+    VGV3_NEXTCMD_CALL                = 2,   // First call a sub-stream at CALLADDR for CALLCOUNT dwords. Then perform a continue.
+    VGV3_NEXTCMD_CALLV2TRUE          = 3,   // Not supported.
+    VGV3_NEXTCMD_CALLV2FALSE         = 4,   // Not supported.
+    VGV3_NEXTCMD_ABORT               = 5,   // Abort reading. This ends the stream. Normally stream can just be paused (or automatically pauses at the end) which avoids any data being lost.
+} V3_NEXTCMD;
+
+typedef enum _V3_FORMAT {
+    VGV3_FORMAT_S8                   = 0,   // Signed 8 bit data (4 writes per data dword) => VGV2-float
+    VGV3_FORMAT_S16                  = 1,   // Signed 16 bit data (2 writes per data dword) => VGV2-float
+    VGV3_FORMAT_S32                  = 2,   // Signed 32 bit data => VGV2-float
+    VGV3_FORMAT_F32                  = 3,   // IEEE 32-bit floating point => VGV2-float
+    VGV3_FORMAT_RAW                  = 4,   // No conversion
+} V3_FORMAT;
+
+typedef enum _V2_ACTION {
+    VGV2_ACTION_END                  = 0,   // end previous path
+    VGV2_ACTION_MOVETOOPEN           = 1,   // end previous path, C1=C4, start new open subpath
+    VGV2_ACTION_MOVETOCLOSED         = 2,   // end previous path, C1=C4, start new closed subpath
+    VGV2_ACTION_LINETO               = 3,   // line C1,C4
+    VGV2_ACTION_CUBICTO              = 4,   // cubic C1,C2,C3,C4.
+    VGV2_ACTION_QUADTO               = 5,   // quadratic C1,C3,C4.
+    VGV2_ACTION_SCUBICTO             = 6,   // smooth cubic C1,C4.
+    VGV2_ACTION_SQUADTO              = 7,   // smooth quadratic C1,C3,C4.
+    VGV2_ACTION_VERTEXTO             = 8,   // half lineto C4=pos, C3=normal.
+    VGV2_ACTION_VERTEXTOOPEN         = 9,   // moveto open + half lineto C4=pos, C3=normal.
+    VGV2_ACTION_VERTEXTOCLOSED       = 10,  // moveto closed + half lineto C4=pos, C3=normal.
+    VGV2_ACTION_MOVETOMOVE           = 11,  // end previous path, C1=C4, move but do not start a subpath
+    VGV2_ACTION_FLUSH                = 15,  // end previous path and block following regwrites until all lines sent
+} V2_ACTION;
+
+typedef enum _V2_CAP {
+    VGV2_CAP_BUTT                    = 0,   // butt caps (straight line overlappin starting point
+    VGV2_CAP_ROUND                   = 1,   // round caps (smoothness depends on ARCSIN/ARCCOS registers)
+    VGV2_CAP_SQUARE                  = 2,   // square caps (square centered on starting point)
+} V2_CAP;
+
+typedef enum _V2_JOIN {
+    VGV2_JOIN_MITER                  = 0,   // miter joins (both sides extended towards intersection. If angle is too small (compared to STMITER register) the miter is converted into a BEVEL.
+    VGV2_JOIN_ROUND                  = 1,   // round joins (smoothness depends on ARCSIN/ARCCOS registers)
+    VGV2_JOIN_BEVEL                  = 2,   // bevel joins (ends of both sides are connected with a single line)
+} V2_JOIN;
+
+enum
+{
+    G2D_GRADREG_X        = 0,  // also usable as temp
+    G2D_GRADREG_Y        = 1,  // also usable as temp
+    G2D_GRADREG_OUTX     = 8,
+    G2D_GRADREG_OUTY     = 9,
+    G2D_GRADREG_C0       = 16,
+    G2D_GRADREG_C1       = 17,
+    G2D_GRADREG_C2       = 18,
+    G2D_GRADREG_C3       = 19,
+    G2D_GRADREG_C4       = 20,
+    G2D_GRADREG_C5       = 21,
+    G2D_GRADREG_C6       = 22,
+    G2D_GRADREG_C7       = 23,
+    G2D_GRADREG_C8       = 24,
+    G2D_GRADREG_C9       = 25,
+    G2D_GRADREG_C10      = 26,
+    G2D_GRADREG_C11      = 27,
+    G2D_GRADREG_ZERO     = 28,
+    G2D_GRADREG_ONE      = 29,
+    G2D_GRADREG_MINUSONE = 30,
+};
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h
new file mode 100644
index 00000000000..1660bc1c12a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h
@@ -0,0 +1,3775 @@
+/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __REGS_G4X_DRIVER_H
+#define __REGS_G4X_DRIVER_H
+
+#ifndef _LINUX
+#include <assert.h>
+#else
+#ifndef assert
+#define assert(expr)
+#endif
+#endif
+
+//-----------------------------------------------------
+// REGISTER ADDRESSES
+//-----------------------------------------------------
+
+#define ADDR_FBC_BASE                    0x84
+#define ADDR_FBC_DATA                    0x86
+#define ADDR_FBC_HEIGHT                  0x8a
+#define ADDR_FBC_START                   0x8e
+#define ADDR_FBC_STRIDE                  0x8c
+#define ADDR_FBC_WIDTH                   0x88
+#define ADDR_VGC_CLOCKEN                 0x508
+#define ADDR_VGC_COMMANDSTREAM           0x0
+#define ADDR_VGC_FIFOFREE                0x7c0
+#define ADDR_VGC_IRQENABLE               0x438
+#define ADDR_VGC_IRQSTATUS               0x418
+#define ADDR_VGC_IRQ_ACTIVE_CNT          0x4e0
+#define ADDR_VGC_MMUCOMMANDSTREAM        0x3fc
+#define ADDR_VGC_REVISION                0x400
+#define ADDR_VGC_SYSSTATUS               0x410
+#define ADDR_G2D_ALPHABLEND              0xc
+#define ADDR_G2D_BACKGROUND              0xb
+#define ADDR_G2D_BASE0                   0x0
+#define ADDR_G2D_BASE1                   0x2
+#define ADDR_G2D_BASE2                   0x4
+#define ADDR_G2D_BASE3                   0x6
+#define ADDR_G2D_BLENDERCFG              0x11
+#define ADDR_G2D_BLEND_A0                0x14
+#define ADDR_G2D_BLEND_A1                0x15
+#define ADDR_G2D_BLEND_A2                0x16
+#define ADDR_G2D_BLEND_A3                0x17
+#define ADDR_G2D_BLEND_C0                0x18
+#define ADDR_G2D_BLEND_C1                0x19
+#define ADDR_G2D_BLEND_C2                0x1a
+#define ADDR_G2D_BLEND_C3                0x1b
+#define ADDR_G2D_BLEND_C4                0x1c
+#define ADDR_G2D_BLEND_C5                0x1d
+#define ADDR_G2D_BLEND_C6                0x1e
+#define ADDR_G2D_BLEND_C7                0x1f
+#define ADDR_G2D_CFG0                    0x1
+#define ADDR_G2D_CFG1                    0x3
+#define ADDR_G2D_CFG2                    0x5
+#define ADDR_G2D_CFG3                    0x7
+#define ADDR_G2D_COLOR                   0xff
+#define ADDR_G2D_CONFIG                  0xe
+#define ADDR_G2D_CONST0                  0xb0
+#define ADDR_G2D_CONST1                  0xb1
+#define ADDR_G2D_CONST2                  0xb2
+#define ADDR_G2D_CONST3                  0xb3
+#define ADDR_G2D_CONST4                  0xb4
+#define ADDR_G2D_CONST5                  0xb5
+#define ADDR_G2D_CONST6                  0xb6
+#define ADDR_G2D_CONST7                  0xb7
+#define ADDR_G2D_FOREGROUND              0xa
+#define ADDR_G2D_GRADIENT                0xd0
+#define ADDR_G2D_IDLE                    0xfe
+#define ADDR_G2D_INPUT                   0xf
+#define ADDR_G2D_MASK                    0x10
+#define ADDR_G2D_ROP                     0xd
+#define ADDR_G2D_SCISSORX                0x8
+#define ADDR_G2D_SCISSORY                0x9
+#define ADDR_G2D_SXY                     0xf2
+#define ADDR_G2D_SXY2                    0xf3
+#define ADDR_G2D_VGSPAN                  0xf4
+#define ADDR_G2D_WIDTHHEIGHT             0xf1
+#define ADDR_G2D_XY                      0xf0
+#define ADDR_GRADW_BORDERCOLOR           0xd4
+#define ADDR_GRADW_CONST0                0xc0
+#define ADDR_GRADW_CONST1                0xc1
+#define ADDR_GRADW_CONST2                0xc2
+#define ADDR_GRADW_CONST3                0xc3
+#define ADDR_GRADW_CONST4                0xc4
+#define ADDR_GRADW_CONST5                0xc5
+#define ADDR_GRADW_CONST6                0xc6
+#define ADDR_GRADW_CONST7                0xc7
+#define ADDR_GRADW_CONST8                0xc8
+#define ADDR_GRADW_CONST9                0xc9
+#define ADDR_GRADW_CONSTA                0xca
+#define ADDR_GRADW_CONSTB                0xcb
+#define ADDR_GRADW_INST0                 0xe0
+#define ADDR_GRADW_INST1                 0xe1
+#define ADDR_GRADW_INST2                 0xe2
+#define ADDR_GRADW_INST3                 0xe3
+#define ADDR_GRADW_INST4                 0xe4
+#define ADDR_GRADW_INST5                 0xe5
+#define ADDR_GRADW_INST6                 0xe6
+#define ADDR_GRADW_INST7                 0xe7
+#define ADDR_GRADW_TEXBASE               0xd3
+#define ADDR_GRADW_TEXCFG                0xd1
+#define ADDR_GRADW_TEXSIZE               0xd2
+#define ADDR_MH_ARBITER_CONFIG           0xa40
+#define ADDR_MH_AXI_ERROR                0xa45
+#define ADDR_MH_AXI_HALT_CONTROL         0xa50
+#define ADDR_MH_CLNT_AXI_ID_REUSE        0xa41
+#define ADDR_MH_DEBUG_CTRL               0xa4e
+#define ADDR_MH_DEBUG_DATA               0xa4f
+#define ADDR_MH_INTERRUPT_CLEAR          0xa44
+#define ADDR_MH_INTERRUPT_MASK           0xa42
+#define ADDR_MH_INTERRUPT_STATUS         0xa43
+#define ADDR_MH_MMU_CONFIG               0x40
+#define ADDR_MH_MMU_INVALIDATE           0x45
+#define ADDR_MH_MMU_MPU_BASE             0x46
+#define ADDR_MH_MMU_MPU_END              0x47
+#define ADDR_MH_MMU_PAGE_FAULT           0x43
+#define ADDR_MH_MMU_PT_BASE              0x42
+#define ADDR_MH_MMU_TRAN_ERROR           0x44
+#define ADDR_MH_MMU_VA_RANGE             0x41
+#define ADDR_MH_PERFCOUNTER0_CONFIG      0xa47
+#define ADDR_MH_PERFCOUNTER0_HI          0xa49
+#define ADDR_MH_PERFCOUNTER0_LOW         0xa48
+#define ADDR_MH_PERFCOUNTER0_SELECT      0xa46
+#define ADDR_MH_PERFCOUNTER1_CONFIG      0xa4b
+#define ADDR_MH_PERFCOUNTER1_HI          0xa4d
+#define ADDR_MH_PERFCOUNTER1_LOW         0xa4c
+#define ADDR_MH_PERFCOUNTER1_SELECT      0xa4a
+#define ADDR_MMU_READ_ADDR               0x510
+#define ADDR_MMU_READ_DATA               0x518
+#define ADDR_VGV1_CBASE1                 0x2a
+#define ADDR_VGV1_CFG1                   0x27
+#define ADDR_VGV1_CFG2                   0x28
+#define ADDR_VGV1_DIRTYBASE              0x29
+#define ADDR_VGV1_FILL                   0x23
+#define ADDR_VGV1_SCISSORX               0x24
+#define ADDR_VGV1_SCISSORY               0x25
+#define ADDR_VGV1_TILEOFS                0x22
+#define ADDR_VGV1_UBASE2                 0x2b
+#define ADDR_VGV1_VTX0                   0x20
+#define ADDR_VGV1_VTX1                   0x21
+#define ADDR_VGV2_ACCURACY               0x60
+#define ADDR_VGV2_ACTION                 0x6f
+#define ADDR_VGV2_ARCCOS                 0x62
+#define ADDR_VGV2_ARCSIN                 0x63
+#define ADDR_VGV2_ARCTAN                 0x64
+#define ADDR_VGV2_BBOXMAXX               0x5c
+#define ADDR_VGV2_BBOXMAXY               0x5d
+#define ADDR_VGV2_BBOXMINX               0x5a
+#define ADDR_VGV2_BBOXMINY               0x5b
+#define ADDR_VGV2_BIAS                   0x5f
+#define ADDR_VGV2_C1X                    0x40
+#define ADDR_VGV2_C1XREL                 0x48
+#define ADDR_VGV2_C1Y                    0x41
+#define ADDR_VGV2_C1YREL                 0x49
+#define ADDR_VGV2_C2X                    0x42
+#define ADDR_VGV2_C2XREL                 0x4a
+#define ADDR_VGV2_C2Y                    0x43
+#define ADDR_VGV2_C2YREL                 0x4b
+#define ADDR_VGV2_C3X                    0x44
+#define ADDR_VGV2_C3XREL                 0x4c
+#define ADDR_VGV2_C3Y                    0x45
+#define ADDR_VGV2_C3YREL                 0x4d
+#define ADDR_VGV2_C4X                    0x46
+#define ADDR_VGV2_C4XREL                 0x4e
+#define ADDR_VGV2_C4Y                    0x47
+#define ADDR_VGV2_C4YREL                 0x4f
+#define ADDR_VGV2_CLIP                   0x68
+#define ADDR_VGV2_FIRST                  0x40
+#define ADDR_VGV2_LAST                   0x6f
+#define ADDR_VGV2_MITER                  0x66
+#define ADDR_VGV2_MODE                   0x6e
+#define ADDR_VGV2_RADIUS                 0x65
+#define ADDR_VGV2_SCALE                  0x5e
+#define ADDR_VGV2_THINRADIUS             0x61
+#define ADDR_VGV2_XFSTXX                 0x56
+#define ADDR_VGV2_XFSTXY                 0x58
+#define ADDR_VGV2_XFSTYX                 0x57
+#define ADDR_VGV2_XFSTYY                 0x59
+#define ADDR_VGV2_XFXA                   0x54
+#define ADDR_VGV2_XFXX                   0x50
+#define ADDR_VGV2_XFXY                   0x52
+#define ADDR_VGV2_XFYA                   0x55
+#define ADDR_VGV2_XFYX                   0x51
+#define ADDR_VGV2_XFYY                   0x53
+#define ADDR_VGV3_CONTROL                0x70
+#define ADDR_VGV3_FIRST                  0x70
+#define ADDR_VGV3_LAST                   0x7f
+#define ADDR_VGV3_MODE                   0x71
+#define ADDR_VGV3_NEXTADDR               0x75
+#define ADDR_VGV3_NEXTCMD                0x76
+#define ADDR_VGV3_VGBYPASS               0x77
+#define ADDR_VGV3_WRITE                  0x73
+#define ADDR_VGV3_WRITEADDR              0x72
+#define ADDR_VGV3_WRITEDMI               0x7d
+#define ADDR_VGV3_WRITEF32               0x7b
+#define ADDR_VGV3_WRITEIFPAUSED          0x74
+#define ADDR_VGV3_WRITERAW               0x7c
+#define ADDR_VGV3_WRITES16               0x79
+#define ADDR_VGV3_WRITES32               0x7a
+#define ADDR_VGV3_WRITES8                0x78
+
+// FBC_BASE
+typedef struct _REG_FBC_BASE {
+    unsigned BASE                : 32;
+} REG_FBC_BASE;
+
+// FBC_DATA
+typedef struct _REG_FBC_DATA {
+    unsigned DATA                : 32;
+} REG_FBC_DATA;
+
+// FBC_HEIGHT
+typedef struct _REG_FBC_HEIGHT {
+    unsigned HEIGHT              : 11;
+} REG_FBC_HEIGHT;
+
+// FBC_START
+typedef struct _REG_FBC_START {
+    unsigned DUMMY               : 1;
+} REG_FBC_START;
+
+// FBC_STRIDE
+typedef struct _REG_FBC_STRIDE {
+    unsigned STRIDE              : 11;
+} REG_FBC_STRIDE;
+
+// FBC_WIDTH
+typedef struct _REG_FBC_WIDTH {
+    unsigned WIDTH               : 11;
+} REG_FBC_WIDTH;
+
+// VGC_CLOCKEN
+typedef struct _REG_VGC_CLOCKEN {
+    unsigned BCACHE              : 1;
+    unsigned G2D_VGL3            : 1;
+    unsigned VG_L1L2             : 1;
+    unsigned RESERVED            : 3;
+} REG_VGC_CLOCKEN;
+
+// VGC_COMMANDSTREAM
+typedef struct _REG_VGC_COMMANDSTREAM {
+    unsigned DATA                : 32;
+} REG_VGC_COMMANDSTREAM;
+
+// VGC_FIFOFREE
+typedef struct _REG_VGC_FIFOFREE {
+    unsigned FREE                : 1;
+} REG_VGC_FIFOFREE;
+
+// VGC_IRQENABLE
+typedef struct _REG_VGC_IRQENABLE {
+    unsigned MH                  : 1;
+    unsigned G2D                 : 1;
+    unsigned FIFO                : 1;
+    unsigned FBC                 : 1;
+} REG_VGC_IRQENABLE;
+
+// VGC_IRQSTATUS
+typedef struct _REG_VGC_IRQSTATUS {
+    unsigned MH                  : 1;
+    unsigned G2D                 : 1;
+    unsigned FIFO                : 1;
+    unsigned FBC                 : 1;
+} REG_VGC_IRQSTATUS;
+
+// VGC_IRQ_ACTIVE_CNT
+typedef struct _REG_VGC_IRQ_ACTIVE_CNT {
+    unsigned MH                  : 8;
+    unsigned G2D                 : 8;
+    unsigned ERRORS              : 8;
+    unsigned FBC                 : 8;
+} REG_VGC_IRQ_ACTIVE_CNT;
+
+// VGC_MMUCOMMANDSTREAM
+typedef struct _REG_VGC_MMUCOMMANDSTREAM {
+    unsigned DATA                : 32;
+} REG_VGC_MMUCOMMANDSTREAM;
+
+// VGC_REVISION
+typedef struct _REG_VGC_REVISION {
+    unsigned MINOR_REVISION      : 4;
+    unsigned MAJOR_REVISION      : 4;
+} REG_VGC_REVISION;
+
+// VGC_SYSSTATUS
+typedef struct _REG_VGC_SYSSTATUS {
+    unsigned RESET               : 1;
+} REG_VGC_SYSSTATUS;
+
+// G2D_ALPHABLEND
+typedef struct _REG_G2D_ALPHABLEND {
+    unsigned ALPHA               : 8;
+    unsigned OBS_ENABLE          : 1;
+    unsigned CONSTANT            : 1;
+    unsigned INVERT              : 1;
+    unsigned OPTIMIZE            : 1;
+    unsigned MODULATE            : 1;
+    unsigned INVERTMASK          : 1;
+    unsigned PREMULTIPLYDST      : 1;
+    unsigned MASKTOALPHA         : 1;
+} REG_G2D_ALPHABLEND;
+
+// G2D_BACKGROUND
+typedef struct _REG_G2D_BACKGROUND {
+    unsigned COLOR               : 32;
+} REG_G2D_BACKGROUND;
+
+// G2D_BASE0
+typedef struct _REG_G2D_BASE0 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE0;
+
+// G2D_BASE1
+typedef struct _REG_G2D_BASE1 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE1;
+
+// G2D_BASE2
+typedef struct _REG_G2D_BASE2 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE2;
+
+// G2D_BASE3
+typedef struct _REG_G2D_BASE3 {
+    unsigned ADDR                : 32;
+} REG_G2D_BASE3;
+
+// G2D_BLENDERCFG
+typedef struct _REG_G2D_BLENDERCFG {
+    unsigned PASSES              : 3;
+    unsigned ALPHAPASSES         : 2;
+    unsigned ENABLE              : 1;
+    unsigned OOALPHA             : 1;
+    unsigned OBS_DIVALPHA        : 1;
+    unsigned NOMASK              : 1;
+} REG_G2D_BLENDERCFG;
+
+// G2D_BLEND_A0
+typedef struct _REG_G2D_BLEND_A0 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A0;
+
+// G2D_BLEND_A1
+typedef struct _REG_G2D_BLEND_A1 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A1;
+
+// G2D_BLEND_A2
+typedef struct _REG_G2D_BLEND_A2 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A2;
+
+// G2D_BLEND_A3
+typedef struct _REG_G2D_BLEND_A3 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_A3;
+
+// G2D_BLEND_C0
+typedef struct _REG_G2D_BLEND_C0 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C0;
+
+// G2D_BLEND_C1
+typedef struct _REG_G2D_BLEND_C1 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C1;
+
+// G2D_BLEND_C2
+typedef struct _REG_G2D_BLEND_C2 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C2;
+
+// G2D_BLEND_C3
+typedef struct _REG_G2D_BLEND_C3 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C3;
+
+// G2D_BLEND_C4
+typedef struct _REG_G2D_BLEND_C4 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C4;
+
+// G2D_BLEND_C5
+typedef struct _REG_G2D_BLEND_C5 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C5;
+
+// G2D_BLEND_C6
+typedef struct _REG_G2D_BLEND_C6 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C6;
+
+// G2D_BLEND_C7
+typedef struct _REG_G2D_BLEND_C7 {
+    unsigned OPERATION           : 2;
+    unsigned DST_A               : 2;
+    unsigned DST_B               : 2;
+    unsigned DST_C               : 2;
+    unsigned AR_A                : 1;
+    unsigned AR_B                : 1;
+    unsigned AR_C                : 1;
+    unsigned AR_D                : 1;
+    unsigned INV_A               : 1;
+    unsigned INV_B               : 1;
+    unsigned INV_C               : 1;
+    unsigned INV_D               : 1;
+    unsigned SRC_A               : 3;
+    unsigned SRC_B               : 3;
+    unsigned SRC_C               : 3;
+    unsigned SRC_D               : 3;
+    unsigned CONST_A             : 1;
+    unsigned CONST_B             : 1;
+    unsigned CONST_C             : 1;
+    unsigned CONST_D             : 1;
+} REG_G2D_BLEND_C7;
+
+// G2D_CFG0
+typedef struct _REG_G2D_CFG0 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG0;
+
+// G2D_CFG1
+typedef struct _REG_G2D_CFG1 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG1;
+
+// G2D_CFG2
+typedef struct _REG_G2D_CFG2 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG2;
+
+// G2D_CFG3
+typedef struct _REG_G2D_CFG3 {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned SRGB                : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned SWAPBITS            : 1;
+    unsigned STRIDESIGN          : 1;
+} REG_G2D_CFG3;
+
+// G2D_COLOR
+typedef struct _REG_G2D_COLOR {
+    unsigned ARGB                : 32;
+} REG_G2D_COLOR;
+
+// G2D_CONFIG
+typedef struct _REG_G2D_CONFIG {
+    unsigned DST                 : 1;
+    unsigned SRC1                : 1;
+    unsigned SRC2                : 1;
+    unsigned SRC3                : 1;
+    unsigned SRCCK               : 1;
+    unsigned DSTCK               : 1;
+    unsigned ROTATE              : 2;
+    unsigned OBS_GAMMA           : 1;
+    unsigned IGNORECKALPHA       : 1;
+    unsigned DITHER              : 1;
+    unsigned WRITESRGB           : 1;
+    unsigned ARGBMASK            : 4;
+    unsigned ALPHATEX            : 1;
+    unsigned PALMLINES           : 1;
+    unsigned NOLASTPIXEL         : 1;
+    unsigned NOPROTECT           : 1;
+} REG_G2D_CONFIG;
+
+// G2D_CONST0
+typedef struct _REG_G2D_CONST0 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST0;
+
+// G2D_CONST1
+typedef struct _REG_G2D_CONST1 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST1;
+
+// G2D_CONST2
+typedef struct _REG_G2D_CONST2 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST2;
+
+// G2D_CONST3
+typedef struct _REG_G2D_CONST3 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST3;
+
+// G2D_CONST4
+typedef struct _REG_G2D_CONST4 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST4;
+
+// G2D_CONST5
+typedef struct _REG_G2D_CONST5 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST5;
+
+// G2D_CONST6
+typedef struct _REG_G2D_CONST6 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST6;
+
+// G2D_CONST7
+typedef struct _REG_G2D_CONST7 {
+    unsigned ARGB                : 32;
+} REG_G2D_CONST7;
+
+// G2D_FOREGROUND
+typedef struct _REG_G2D_FOREGROUND {
+    unsigned COLOR               : 32;
+} REG_G2D_FOREGROUND;
+
+// G2D_GRADIENT
+typedef struct _REG_G2D_GRADIENT {
+    unsigned INSTRUCTIONS        : 3;
+    unsigned INSTRUCTIONS2       : 3;
+    unsigned ENABLE              : 1;
+    unsigned ENABLE2             : 1;
+    unsigned SEL                 : 1;
+} REG_G2D_GRADIENT;
+
+// G2D_IDLE
+typedef struct _REG_G2D_IDLE {
+    unsigned IRQ                 : 1;
+    unsigned BCFLUSH             : 1;
+    unsigned V3                  : 1;
+} REG_G2D_IDLE;
+
+// G2D_INPUT
+typedef struct _REG_G2D_INPUT {
+    unsigned COLOR               : 1;
+    unsigned SCOORD1             : 1;
+    unsigned SCOORD2             : 1;
+    unsigned COPYCOORD           : 1;
+    unsigned VGMODE              : 1;
+    unsigned LINEMODE            : 1;
+} REG_G2D_INPUT;
+
+// G2D_MASK
+typedef struct _REG_G2D_MASK {
+    unsigned YMASK               : 12;
+    unsigned XMASK               : 12;
+} REG_G2D_MASK;
+
+// G2D_ROP
+typedef struct _REG_G2D_ROP {
+    unsigned ROP                 : 16;
+} REG_G2D_ROP;
+
+// G2D_SCISSORX
+typedef struct _REG_G2D_SCISSORX {
+    unsigned LEFT                : 11;
+    unsigned RIGHT               : 11;
+} REG_G2D_SCISSORX;
+
+// G2D_SCISSORY
+typedef struct _REG_G2D_SCISSORY {
+    unsigned TOP                 : 11;
+    unsigned BOTTOM              : 11;
+} REG_G2D_SCISSORY;
+
+// G2D_SXY
+typedef struct _REG_G2D_SXY {
+    unsigned Y                   : 11;
+    unsigned PAD                 : 5;
+    unsigned X                   : 11;
+} REG_G2D_SXY;
+
+// G2D_SXY2
+typedef struct _REG_G2D_SXY2 {
+    unsigned Y                   : 11;
+    unsigned PAD                 : 5;
+    unsigned X                   : 11;
+} REG_G2D_SXY2;
+
+// G2D_VGSPAN
+typedef struct _REG_G2D_VGSPAN {
+    int WIDTH               : 12;
+    unsigned PAD                 : 4;
+    unsigned COVERAGE            : 4;
+} REG_G2D_VGSPAN;
+
+// G2D_WIDTHHEIGHT
+typedef struct _REG_G2D_WIDTHHEIGHT {
+    int HEIGHT              : 12;
+    unsigned PAD                 : 4;
+    int WIDTH               : 12;
+} REG_G2D_WIDTHHEIGHT;
+
+// G2D_XY
+typedef struct _REG_G2D_XY {
+    int Y                   : 12;
+    unsigned PAD                 : 4;
+    int X                   : 12;
+} REG_G2D_XY;
+
+// GRADW_BORDERCOLOR
+typedef struct _REG_GRADW_BORDERCOLOR {
+    unsigned COLOR               : 32;
+} REG_GRADW_BORDERCOLOR;
+
+// GRADW_CONST0
+typedef struct _REG_GRADW_CONST0 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST0;
+
+// GRADW_CONST1
+typedef struct _REG_GRADW_CONST1 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST1;
+
+// GRADW_CONST2
+typedef struct _REG_GRADW_CONST2 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST2;
+
+// GRADW_CONST3
+typedef struct _REG_GRADW_CONST3 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST3;
+
+// GRADW_CONST4
+typedef struct _REG_GRADW_CONST4 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST4;
+
+// GRADW_CONST5
+typedef struct _REG_GRADW_CONST5 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST5;
+
+// GRADW_CONST6
+typedef struct _REG_GRADW_CONST6 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST6;
+
+// GRADW_CONST7
+typedef struct _REG_GRADW_CONST7 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST7;
+
+// GRADW_CONST8
+typedef struct _REG_GRADW_CONST8 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST8;
+
+// GRADW_CONST9
+typedef struct _REG_GRADW_CONST9 {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONST9;
+
+// GRADW_CONSTA
+typedef struct _REG_GRADW_CONSTA {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONSTA;
+
+// GRADW_CONSTB
+typedef struct _REG_GRADW_CONSTB {
+    unsigned VALUE               : 16;
+} REG_GRADW_CONSTB;
+
+// GRADW_INST0
+typedef struct _REG_GRADW_INST0 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST0;
+
+// GRADW_INST1
+typedef struct _REG_GRADW_INST1 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST1;
+
+// GRADW_INST2
+typedef struct _REG_GRADW_INST2 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST2;
+
+// GRADW_INST3
+typedef struct _REG_GRADW_INST3 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST3;
+
+// GRADW_INST4
+typedef struct _REG_GRADW_INST4 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST4;
+
+// GRADW_INST5
+typedef struct _REG_GRADW_INST5 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST5;
+
+// GRADW_INST6
+typedef struct _REG_GRADW_INST6 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST6;
+
+// GRADW_INST7
+typedef struct _REG_GRADW_INST7 {
+    unsigned SRC_E               : 5;
+    unsigned SRC_D               : 5;
+    unsigned SRC_C               : 5;
+    unsigned SRC_B               : 5;
+    unsigned SRC_A               : 5;
+    unsigned DST                 : 4;
+    unsigned OPCODE              : 2;
+} REG_GRADW_INST7;
+
+// GRADW_TEXBASE
+typedef struct _REG_GRADW_TEXBASE {
+    unsigned ADDR                : 32;
+} REG_GRADW_TEXBASE;
+
+// GRADW_TEXCFG
+typedef struct _REG_GRADW_TEXCFG {
+    unsigned STRIDE              : 12;
+    unsigned FORMAT              : 4;
+    unsigned TILED               : 1;
+    unsigned WRAPU               : 2;
+    unsigned WRAPV               : 2;
+    unsigned BILIN               : 1;
+    unsigned SRGB                : 1;
+    unsigned PREMULTIPLY         : 1;
+    unsigned SWAPWORDS           : 1;
+    unsigned SWAPBYTES           : 1;
+    unsigned SWAPALL             : 1;
+    unsigned SWAPRB              : 1;
+    unsigned TEX2D               : 1;
+    unsigned SWAPBITS            : 1;
+} REG_GRADW_TEXCFG;
+
+// GRADW_TEXSIZE
+typedef struct _REG_GRADW_TEXSIZE {
+    unsigned WIDTH               : 11;
+    unsigned HEIGHT              : 11;
+} REG_GRADW_TEXSIZE;
+
+// MH_ARBITER_CONFIG
+typedef struct _REG_MH_ARBITER_CONFIG {
+    unsigned SAME_PAGE_LIMIT     : 6;
+    unsigned SAME_PAGE_GRANULARITY : 1;
+    unsigned L1_ARB_ENABLE       : 1;
+    unsigned L1_ARB_HOLD_ENABLE  : 1;
+    unsigned L2_ARB_CONTROL      : 1;
+    unsigned PAGE_SIZE           : 3;
+    unsigned TC_REORDER_ENABLE   : 1;
+    unsigned TC_ARB_HOLD_ENABLE  : 1;
+    unsigned IN_FLIGHT_LIMIT_ENABLE : 1;
+    unsigned IN_FLIGHT_LIMIT     : 6;
+    unsigned CP_CLNT_ENABLE      : 1;
+    unsigned VGT_CLNT_ENABLE     : 1;
+    unsigned TC_CLNT_ENABLE      : 1;
+    unsigned RB_CLNT_ENABLE      : 1;
+    unsigned PA_CLNT_ENABLE      : 1;
+} REG_MH_ARBITER_CONFIG;
+
+// MH_AXI_ERROR
+typedef struct _REG_MH_AXI_ERROR {
+    unsigned AXI_READ_ID         : 3;
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ID        : 3;
+    unsigned AXI_WRITE_ERROR     : 1;
+} REG_MH_AXI_ERROR;
+
+// MH_AXI_HALT_CONTROL
+typedef struct _REG_MH_AXI_HALT_CONTROL {
+    unsigned AXI_HALT            : 1;
+} REG_MH_AXI_HALT_CONTROL;
+
+// MH_CLNT_AXI_ID_REUSE
+typedef struct _REG_MH_CLNT_AXI_ID_REUSE {
+    unsigned CPW_ID              : 3;
+    unsigned PAD                 : 1;
+    unsigned RBW_ID              : 3;
+    unsigned PAD2                : 1;
+    unsigned MMUR_ID             : 3;
+    unsigned PAD3                : 1;
+    unsigned PAW_ID              : 3;
+} REG_MH_CLNT_AXI_ID_REUSE;
+
+// MH_DEBUG_CTRL
+typedef struct _REG_MH_DEBUG_CTRL {
+    unsigned INDEX               : 6;
+} REG_MH_DEBUG_CTRL;
+
+// MH_DEBUG_DATA
+typedef struct _REG_MH_DEBUG_DATA {
+    unsigned DATA                : 32;
+} REG_MH_DEBUG_DATA;
+
+// MH_INTERRUPT_CLEAR
+typedef struct _REG_MH_INTERRUPT_CLEAR {
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ERROR     : 1;
+    unsigned MMU_PAGE_FAULT      : 1;
+} REG_MH_INTERRUPT_CLEAR;
+
+// MH_INTERRUPT_MASK
+typedef struct _REG_MH_INTERRUPT_MASK {
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ERROR     : 1;
+    unsigned MMU_PAGE_FAULT      : 1;
+} REG_MH_INTERRUPT_MASK;
+
+// MH_INTERRUPT_STATUS
+typedef struct _REG_MH_INTERRUPT_STATUS {
+    unsigned AXI_READ_ERROR      : 1;
+    unsigned AXI_WRITE_ERROR     : 1;
+    unsigned MMU_PAGE_FAULT      : 1;
+} REG_MH_INTERRUPT_STATUS;
+
+// MH_MMU_CONFIG
+typedef struct _REG_MH_MMU_CONFIG {
+    unsigned MMU_ENABLE          : 1;
+    unsigned SPLIT_MODE_ENABLE   : 1;
+    unsigned PAD                 : 2;
+    unsigned RB_W_CLNT_BEHAVIOR  : 2;
+    unsigned CP_W_CLNT_BEHAVIOR  : 2;
+    unsigned CP_R0_CLNT_BEHAVIOR : 2;
+    unsigned CP_R1_CLNT_BEHAVIOR : 2;
+    unsigned CP_R2_CLNT_BEHAVIOR : 2;
+    unsigned CP_R3_CLNT_BEHAVIOR : 2;
+    unsigned CP_R4_CLNT_BEHAVIOR : 2;
+    unsigned VGT_R0_CLNT_BEHAVIOR : 2;
+    unsigned VGT_R1_CLNT_BEHAVIOR : 2;
+    unsigned TC_R_CLNT_BEHAVIOR  : 2;
+    unsigned PA_W_CLNT_BEHAVIOR  : 2;
+} REG_MH_MMU_CONFIG;
+
+// MH_MMU_INVALIDATE
+typedef struct _REG_MH_MMU_INVALIDATE {
+    unsigned INVALIDATE_ALL      : 1;
+    unsigned INVALIDATE_TC       : 1;
+} REG_MH_MMU_INVALIDATE;
+
+// MH_MMU_MPU_BASE
+typedef struct _REG_MH_MMU_MPU_BASE {
+    unsigned ZERO                : 12;
+    unsigned MPU_BASE            : 20;
+} REG_MH_MMU_MPU_BASE;
+
+// MH_MMU_MPU_END
+typedef struct _REG_MH_MMU_MPU_END {
+    unsigned ZERO                : 12;
+    unsigned MPU_END             : 20;
+} REG_MH_MMU_MPU_END;
+
+// MH_MMU_PAGE_FAULT
+typedef struct _REG_MH_MMU_PAGE_FAULT {
+    unsigned PAGE_FAULT          : 1;
+    unsigned OP_TYPE             : 1;
+    unsigned CLNT_BEHAVIOR       : 2;
+    unsigned AXI_ID              : 3;
+    unsigned PAD                 : 1;
+    unsigned MPU_ADDRESS_OUT_OF_RANGE : 1;
+    unsigned ADDRESS_OUT_OF_RANGE : 1;
+    unsigned READ_PROTECTION_ERROR : 1;
+    unsigned WRITE_PROTECTION_ERROR : 1;
+    unsigned REQ_VA              : 20;
+} REG_MH_MMU_PAGE_FAULT;
+
+// MH_MMU_PT_BASE
+typedef struct _REG_MH_MMU_PT_BASE {
+    unsigned ZERO                : 12;
+    unsigned PT_BASE             : 20;
+} REG_MH_MMU_PT_BASE;
+
+// MH_MMU_TRAN_ERROR
+typedef struct _REG_MH_MMU_TRAN_ERROR {
+    unsigned ZERO                : 5;
+    unsigned TRAN_ERROR          : 27;
+} REG_MH_MMU_TRAN_ERROR;
+
+// MH_MMU_VA_RANGE
+typedef struct _REG_MH_MMU_VA_RANGE {
+    unsigned NUM_64KB_REGIONS    : 12;
+    unsigned VA_BASE             : 20;
+} REG_MH_MMU_VA_RANGE;
+
+// MH_PERFCOUNTER0_CONFIG
+typedef struct _REG_MH_PERFCOUNTER0_CONFIG {
+    unsigned N_VALUE             : 8;
+} REG_MH_PERFCOUNTER0_CONFIG;
+
+// MH_PERFCOUNTER0_HI
+typedef struct _REG_MH_PERFCOUNTER0_HI {
+    unsigned PERF_COUNTER_HI     : 16;
+} REG_MH_PERFCOUNTER0_HI;
+
+// MH_PERFCOUNTER0_LOW
+typedef struct _REG_MH_PERFCOUNTER0_LOW {
+    unsigned PERF_COUNTER_LOW    : 32;
+} REG_MH_PERFCOUNTER0_LOW;
+
+// MH_PERFCOUNTER0_SELECT
+typedef struct _REG_MH_PERFCOUNTER0_SELECT {
+    unsigned PERF_SEL            : 8;
+} REG_MH_PERFCOUNTER0_SELECT;
+
+// MH_PERFCOUNTER1_CONFIG
+typedef struct _REG_MH_PERFCOUNTER1_CONFIG {
+    unsigned N_VALUE             : 8;
+} REG_MH_PERFCOUNTER1_CONFIG;
+
+// MH_PERFCOUNTER1_HI
+typedef struct _REG_MH_PERFCOUNTER1_HI {
+    unsigned PERF_COUNTER_HI     : 16;
+} REG_MH_PERFCOUNTER1_HI;
+
+// MH_PERFCOUNTER1_LOW
+typedef struct _REG_MH_PERFCOUNTER1_LOW {
+    unsigned PERF_COUNTER_LOW    : 32;
+} REG_MH_PERFCOUNTER1_LOW;
+
+// MH_PERFCOUNTER1_SELECT
+typedef struct _REG_MH_PERFCOUNTER1_SELECT {
+    unsigned PERF_SEL            : 8;
+} REG_MH_PERFCOUNTER1_SELECT;
+
+// MMU_READ_ADDR
+typedef struct _REG_MMU_READ_ADDR {
+    unsigned ADDR                : 15;
+} REG_MMU_READ_ADDR;
+
+// MMU_READ_DATA
+typedef struct _REG_MMU_READ_DATA {
+    unsigned DATA                : 32;
+} REG_MMU_READ_DATA;
+
+// VGV1_CBASE1
+typedef struct _REG_VGV1_CBASE1 {
+    unsigned ADDR                : 32;
+} REG_VGV1_CBASE1;
+
+// VGV1_CFG1
+typedef struct _REG_VGV1_CFG1 {
+    unsigned WINDRULE            : 1;
+} REG_VGV1_CFG1;
+
+// VGV1_CFG2
+typedef struct _REG_VGV1_CFG2 {
+    unsigned AAMODE              : 2;
+} REG_VGV1_CFG2;
+
+// VGV1_DIRTYBASE
+typedef struct _REG_VGV1_DIRTYBASE {
+    unsigned ADDR                : 32;
+} REG_VGV1_DIRTYBASE;
+
+// VGV1_FILL
+typedef struct _REG_VGV1_FILL {
+    unsigned INHERIT             : 1;
+} REG_VGV1_FILL;
+
+// VGV1_SCISSORX
+typedef struct _REG_VGV1_SCISSORX {
+    unsigned LEFT                : 11;
+    unsigned PAD                 : 5;
+    unsigned RIGHT               : 11;
+} REG_VGV1_SCISSORX;
+
+// VGV1_SCISSORY
+typedef struct _REG_VGV1_SCISSORY {
+    unsigned TOP                 : 11;
+    unsigned PAD                 : 5;
+    unsigned BOTTOM              : 11;
+} REG_VGV1_SCISSORY;
+
+// VGV1_TILEOFS
+typedef struct _REG_VGV1_TILEOFS {
+    unsigned X                   : 12;
+    unsigned Y                   : 12;
+    unsigned LEFTMOST            : 1;
+} REG_VGV1_TILEOFS;
+
+// VGV1_UBASE2
+typedef struct _REG_VGV1_UBASE2 {
+    unsigned ADDR                : 32;
+} REG_VGV1_UBASE2;
+
+// VGV1_VTX0
+typedef struct _REG_VGV1_VTX0 {
+    int X                   : 16;
+    int Y                   : 16;
+} REG_VGV1_VTX0;
+
+// VGV1_VTX1
+typedef struct _REG_VGV1_VTX1 {
+    int X                   : 16;
+    int Y                   : 16;
+} REG_VGV1_VTX1;
+
+// VGV2_ACCURACY
+typedef struct _REG_VGV2_ACCURACY {
+    unsigned F                   : 24;
+} REG_VGV2_ACCURACY;
+
+// VGV2_ACTION
+typedef struct _REG_VGV2_ACTION {
+    unsigned ACTION              : 4;
+} REG_VGV2_ACTION;
+
+// VGV2_ARCCOS
+typedef struct _REG_VGV2_ARCCOS {
+    unsigned F                   : 24;
+} REG_VGV2_ARCCOS;
+
+// VGV2_ARCSIN
+typedef struct _REG_VGV2_ARCSIN {
+    unsigned F                   : 24;
+} REG_VGV2_ARCSIN;
+
+// VGV2_ARCTAN
+typedef struct _REG_VGV2_ARCTAN {
+    unsigned F                   : 24;
+} REG_VGV2_ARCTAN;
+
+// VGV2_BBOXMAXX
+typedef struct _REG_VGV2_BBOXMAXX {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMAXX;
+
+// VGV2_BBOXMAXY
+typedef struct _REG_VGV2_BBOXMAXY {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMAXY;
+
+// VGV2_BBOXMINX
+typedef struct _REG_VGV2_BBOXMINX {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMINX;
+
+// VGV2_BBOXMINY
+typedef struct _REG_VGV2_BBOXMINY {
+    unsigned F                   : 24;
+} REG_VGV2_BBOXMINY;
+
+// VGV2_BIAS
+typedef struct _REG_VGV2_BIAS {
+    unsigned F                   : 24;
+} REG_VGV2_BIAS;
+
+// VGV2_C1X
+typedef struct _REG_VGV2_C1X {
+    unsigned F                   : 24;
+} REG_VGV2_C1X;
+
+// VGV2_C1XREL
+typedef struct _REG_VGV2_C1XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C1XREL;
+
+// VGV2_C1Y
+typedef struct _REG_VGV2_C1Y {
+    unsigned F                   : 24;
+} REG_VGV2_C1Y;
+
+// VGV2_C1YREL
+typedef struct _REG_VGV2_C1YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C1YREL;
+
+// VGV2_C2X
+typedef struct _REG_VGV2_C2X {
+    unsigned F                   : 24;
+} REG_VGV2_C2X;
+
+// VGV2_C2XREL
+typedef struct _REG_VGV2_C2XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C2XREL;
+
+// VGV2_C2Y
+typedef struct _REG_VGV2_C2Y {
+    unsigned F                   : 24;
+} REG_VGV2_C2Y;
+
+// VGV2_C2YREL
+typedef struct _REG_VGV2_C2YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C2YREL;
+
+// VGV2_C3X
+typedef struct _REG_VGV2_C3X {
+    unsigned F                   : 24;
+} REG_VGV2_C3X;
+
+// VGV2_C3XREL
+typedef struct _REG_VGV2_C3XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C3XREL;
+
+// VGV2_C3Y
+typedef struct _REG_VGV2_C3Y {
+    unsigned F                   : 24;
+} REG_VGV2_C3Y;
+
+// VGV2_C3YREL
+typedef struct _REG_VGV2_C3YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C3YREL;
+
+// VGV2_C4X
+typedef struct _REG_VGV2_C4X {
+    unsigned F                   : 24;
+} REG_VGV2_C4X;
+
+// VGV2_C4XREL
+typedef struct _REG_VGV2_C4XREL {
+    unsigned F                   : 24;
+} REG_VGV2_C4XREL;
+
+// VGV2_C4Y
+typedef struct _REG_VGV2_C4Y {
+    unsigned F                   : 24;
+} REG_VGV2_C4Y;
+
+// VGV2_C4YREL
+typedef struct _REG_VGV2_C4YREL {
+    unsigned F                   : 24;
+} REG_VGV2_C4YREL;
+
+// VGV2_CLIP
+typedef struct _REG_VGV2_CLIP {
+    unsigned F                   : 24;
+} REG_VGV2_CLIP;
+
+// VGV2_FIRST
+typedef struct _REG_VGV2_FIRST {
+    unsigned DUMMY               : 1;
+} REG_VGV2_FIRST;
+
+// VGV2_LAST
+typedef struct _REG_VGV2_LAST {
+    unsigned DUMMY               : 1;
+} REG_VGV2_LAST;
+
+// VGV2_MITER
+typedef struct _REG_VGV2_MITER {
+    unsigned F                   : 24;
+} REG_VGV2_MITER;
+
+// VGV2_MODE
+typedef struct _REG_VGV2_MODE {
+    unsigned MAXSPLIT            : 4;
+    unsigned CAP                 : 2;
+    unsigned JOIN                : 2;
+    unsigned STROKE              : 1;
+    unsigned STROKESPLIT         : 1;
+    unsigned FULLSPLIT           : 1;
+    unsigned NODOTS              : 1;
+    unsigned OPENFILL            : 1;
+    unsigned DROPLEFT            : 1;
+    unsigned DROPOTHER           : 1;
+    unsigned SYMMETRICJOINS      : 1;
+    unsigned SIMPLESTROKE        : 1;
+    unsigned SIMPLECLIP          : 1;
+    int EXPONENTADD         : 6;
+} REG_VGV2_MODE;
+
+// VGV2_RADIUS
+typedef struct _REG_VGV2_RADIUS {
+    unsigned F                   : 24;
+} REG_VGV2_RADIUS;
+
+// VGV2_SCALE
+typedef struct _REG_VGV2_SCALE {
+    unsigned F                   : 24;
+} REG_VGV2_SCALE;
+
+// VGV2_THINRADIUS
+typedef struct _REG_VGV2_THINRADIUS {
+    unsigned F                   : 24;
+} REG_VGV2_THINRADIUS;
+
+// VGV2_XFSTXX
+typedef struct _REG_VGV2_XFSTXX {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTXX;
+
+// VGV2_XFSTXY
+typedef struct _REG_VGV2_XFSTXY {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTXY;
+
+// VGV2_XFSTYX
+typedef struct _REG_VGV2_XFSTYX {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTYX;
+
+// VGV2_XFSTYY
+typedef struct _REG_VGV2_XFSTYY {
+    unsigned F                   : 24;
+} REG_VGV2_XFSTYY;
+
+// VGV2_XFXA
+typedef struct _REG_VGV2_XFXA {
+    unsigned F                   : 24;
+} REG_VGV2_XFXA;
+
+// VGV2_XFXX
+typedef struct _REG_VGV2_XFXX {
+    unsigned F                   : 24;
+} REG_VGV2_XFXX;
+
+// VGV2_XFXY
+typedef struct _REG_VGV2_XFXY {
+    unsigned F                   : 24;
+} REG_VGV2_XFXY;
+
+// VGV2_XFYA
+typedef struct _REG_VGV2_XFYA {
+    unsigned F                   : 24;
+} REG_VGV2_XFYA;
+
+// VGV2_XFYX
+typedef struct _REG_VGV2_XFYX {
+    unsigned F                   : 24;
+} REG_VGV2_XFYX;
+
+// VGV2_XFYY
+typedef struct _REG_VGV2_XFYY {
+    unsigned F                   : 24;
+} REG_VGV2_XFYY;
+
+// VGV3_CONTROL
+typedef struct _REG_VGV3_CONTROL {
+    unsigned MARKADD             : 12;
+    unsigned DMIWAITCHMASK       : 4;
+    unsigned PAUSE               : 1;
+    unsigned ABORT               : 1;
+    unsigned WRITE               : 1;
+    unsigned BCFLUSH             : 1;
+    unsigned V0SYNC              : 1;
+    unsigned DMIWAITBUF          : 3;
+} REG_VGV3_CONTROL;
+
+// VGV3_FIRST
+typedef struct _REG_VGV3_FIRST {
+    unsigned DUMMY               : 1;
+} REG_VGV3_FIRST;
+
+// VGV3_LAST
+typedef struct _REG_VGV3_LAST {
+    unsigned DUMMY               : 1;
+} REG_VGV3_LAST;
+
+// VGV3_MODE
+typedef struct _REG_VGV3_MODE {
+    unsigned FLIPENDIAN          : 1;
+    unsigned UNUSED              : 1;
+    unsigned WRITEFLUSH          : 1;
+    unsigned DMIPAUSETYPE        : 1;
+    unsigned DMIRESET            : 1;
+} REG_VGV3_MODE;
+
+// VGV3_NEXTADDR
+typedef struct _REG_VGV3_NEXTADDR {
+    unsigned CALLADDR            : 32;
+} REG_VGV3_NEXTADDR;
+
+// VGV3_NEXTCMD
+typedef struct _REG_VGV3_NEXTCMD {
+    unsigned COUNT               : 12;
+    unsigned NEXTCMD             : 3;
+    unsigned MARK                : 1;
+    unsigned CALLCOUNT           : 12;
+} REG_VGV3_NEXTCMD;
+
+// VGV3_VGBYPASS
+typedef struct _REG_VGV3_VGBYPASS {
+    unsigned BYPASS              : 1;
+} REG_VGV3_VGBYPASS;
+
+// VGV3_WRITE
+typedef struct _REG_VGV3_WRITE {
+    unsigned VALUE               : 32;
+} REG_VGV3_WRITE;
+
+// VGV3_WRITEADDR
+typedef struct _REG_VGV3_WRITEADDR {
+    unsigned ADDR                : 32;
+} REG_VGV3_WRITEADDR;
+
+// VGV3_WRITEDMI
+typedef struct _REG_VGV3_WRITEDMI {
+    unsigned CHANMASK            : 4;
+    unsigned BUFFER              : 3;
+} REG_VGV3_WRITEDMI;
+
+// VGV3_WRITEF32
+typedef struct _REG_VGV3_WRITEF32 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITEF32;
+
+// VGV3_WRITEIFPAUSED
+typedef struct _REG_VGV3_WRITEIFPAUSED {
+    unsigned VALUE               : 32;
+} REG_VGV3_WRITEIFPAUSED;
+
+// VGV3_WRITERAW
+typedef struct _REG_VGV3_WRITERAW {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITERAW;
+
+// VGV3_WRITES16
+typedef struct _REG_VGV3_WRITES16 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITES16;
+
+// VGV3_WRITES32
+typedef struct _REG_VGV3_WRITES32 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITES32;
+
+// VGV3_WRITES8
+typedef struct _REG_VGV3_WRITES8 {
+    unsigned ADDR                : 8;
+    unsigned COUNT               : 8;
+    unsigned LOOP                : 4;
+    unsigned ACTION              : 4;
+    unsigned FORMAT              : 3;
+} REG_VGV3_WRITES8;
+
+// Register address, down shift, AND mask
+#define FBC_BASE_BASE_FADDR ADDR_FBC_BASE
+#define FBC_BASE_BASE_FSHIFT 0
+#define FBC_BASE_BASE_FMASK 0xffffffff
+#define FBC_DATA_DATA_FADDR ADDR_FBC_DATA
+#define FBC_DATA_DATA_FSHIFT 0
+#define FBC_DATA_DATA_FMASK 0xffffffff
+#define FBC_HEIGHT_HEIGHT_FADDR ADDR_FBC_HEIGHT
+#define FBC_HEIGHT_HEIGHT_FSHIFT 0
+#define FBC_HEIGHT_HEIGHT_FMASK 0x7ff
+#define FBC_START_DUMMY_FADDR ADDR_FBC_START
+#define FBC_START_DUMMY_FSHIFT 0
+#define FBC_START_DUMMY_FMASK 0x1
+#define FBC_STRIDE_STRIDE_FADDR ADDR_FBC_STRIDE
+#define FBC_STRIDE_STRIDE_FSHIFT 0
+#define FBC_STRIDE_STRIDE_FMASK 0x7ff
+#define FBC_WIDTH_WIDTH_FADDR ADDR_FBC_WIDTH
+#define FBC_WIDTH_WIDTH_FSHIFT 0
+#define FBC_WIDTH_WIDTH_FMASK 0x7ff
+#define VGC_CLOCKEN_BCACHE_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_BCACHE_FSHIFT 0
+#define VGC_CLOCKEN_BCACHE_FMASK 0x1
+#define VGC_CLOCKEN_G2D_VGL3_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_G2D_VGL3_FSHIFT 1
+#define VGC_CLOCKEN_G2D_VGL3_FMASK 0x1
+#define VGC_CLOCKEN_VG_L1L2_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_VG_L1L2_FSHIFT 2
+#define VGC_CLOCKEN_VG_L1L2_FMASK 0x1
+#define VGC_CLOCKEN_RESERVED_FADDR ADDR_VGC_CLOCKEN
+#define VGC_CLOCKEN_RESERVED_FSHIFT 3
+#define VGC_CLOCKEN_RESERVED_FMASK 0x7
+#define VGC_COMMANDSTREAM_DATA_FADDR ADDR_VGC_COMMANDSTREAM
+#define VGC_COMMANDSTREAM_DATA_FSHIFT 0
+#define VGC_COMMANDSTREAM_DATA_FMASK 0xffffffff
+#define VGC_FIFOFREE_FREE_FADDR ADDR_VGC_FIFOFREE
+#define VGC_FIFOFREE_FREE_FSHIFT 0
+#define VGC_FIFOFREE_FREE_FMASK 0x1
+#define VGC_IRQENABLE_MH_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_MH_FSHIFT 0
+#define VGC_IRQENABLE_MH_FMASK 0x1
+#define VGC_IRQENABLE_G2D_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_G2D_FSHIFT 1
+#define VGC_IRQENABLE_G2D_FMASK 0x1
+#define VGC_IRQENABLE_FIFO_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_FIFO_FSHIFT 2
+#define VGC_IRQENABLE_FIFO_FMASK 0x1
+#define VGC_IRQENABLE_FBC_FADDR ADDR_VGC_IRQENABLE
+#define VGC_IRQENABLE_FBC_FSHIFT 3
+#define VGC_IRQENABLE_FBC_FMASK 0x1
+#define VGC_IRQSTATUS_MH_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_MH_FSHIFT 0
+#define VGC_IRQSTATUS_MH_FMASK 0x1
+#define VGC_IRQSTATUS_G2D_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_G2D_FSHIFT 1
+#define VGC_IRQSTATUS_G2D_FMASK 0x1
+#define VGC_IRQSTATUS_FIFO_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_FIFO_FSHIFT 2
+#define VGC_IRQSTATUS_FIFO_FMASK 0x1
+#define VGC_IRQSTATUS_FBC_FADDR ADDR_VGC_IRQSTATUS
+#define VGC_IRQSTATUS_FBC_FSHIFT 3
+#define VGC_IRQSTATUS_FBC_FMASK 0x1
+#define VGC_IRQ_ACTIVE_CNT_MH_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_MH_FSHIFT 0
+#define VGC_IRQ_ACTIVE_CNT_MH_FMASK 0xff
+#define VGC_IRQ_ACTIVE_CNT_G2D_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_G2D_FSHIFT 8
+#define VGC_IRQ_ACTIVE_CNT_G2D_FMASK 0xff
+#define VGC_IRQ_ACTIVE_CNT_ERRORS_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_ERRORS_FSHIFT 16
+#define VGC_IRQ_ACTIVE_CNT_ERRORS_FMASK 0xff
+#define VGC_IRQ_ACTIVE_CNT_FBC_FADDR ADDR_VGC_IRQ_ACTIVE_CNT
+#define VGC_IRQ_ACTIVE_CNT_FBC_FSHIFT 24
+#define VGC_IRQ_ACTIVE_CNT_FBC_FMASK 0xff
+#define VGC_MMUCOMMANDSTREAM_DATA_FADDR ADDR_VGC_MMUCOMMANDSTREAM
+#define VGC_MMUCOMMANDSTREAM_DATA_FSHIFT 0
+#define VGC_MMUCOMMANDSTREAM_DATA_FMASK 0xffffffff
+#define VGC_REVISION_MINOR_REVISION_FADDR ADDR_VGC_REVISION
+#define VGC_REVISION_MINOR_REVISION_FSHIFT 0
+#define VGC_REVISION_MINOR_REVISION_FMASK 0xf
+#define VGC_REVISION_MAJOR_REVISION_FADDR ADDR_VGC_REVISION
+#define VGC_REVISION_MAJOR_REVISION_FSHIFT 4
+#define VGC_REVISION_MAJOR_REVISION_FMASK 0xf
+#define VGC_SYSSTATUS_RESET_FADDR ADDR_VGC_SYSSTATUS
+#define VGC_SYSSTATUS_RESET_FSHIFT 0
+#define VGC_SYSSTATUS_RESET_FMASK 0x1
+#define G2D_ALPHABLEND_ALPHA_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_ALPHA_FSHIFT 0
+#define G2D_ALPHABLEND_ALPHA_FMASK 0xff
+#define G2D_ALPHABLEND_OBS_ENABLE_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_OBS_ENABLE_FSHIFT 8
+#define G2D_ALPHABLEND_OBS_ENABLE_FMASK 0x1
+#define G2D_ALPHABLEND_CONSTANT_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_CONSTANT_FSHIFT 9
+#define G2D_ALPHABLEND_CONSTANT_FMASK 0x1
+#define G2D_ALPHABLEND_INVERT_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_INVERT_FSHIFT 10
+#define G2D_ALPHABLEND_INVERT_FMASK 0x1
+#define G2D_ALPHABLEND_OPTIMIZE_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_OPTIMIZE_FSHIFT 11
+#define G2D_ALPHABLEND_OPTIMIZE_FMASK 0x1
+#define G2D_ALPHABLEND_MODULATE_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_MODULATE_FSHIFT 12
+#define G2D_ALPHABLEND_MODULATE_FMASK 0x1
+#define G2D_ALPHABLEND_INVERTMASK_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_INVERTMASK_FSHIFT 13
+#define G2D_ALPHABLEND_INVERTMASK_FMASK 0x1
+#define G2D_ALPHABLEND_PREMULTIPLYDST_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_PREMULTIPLYDST_FSHIFT 14
+#define G2D_ALPHABLEND_PREMULTIPLYDST_FMASK 0x1
+#define G2D_ALPHABLEND_MASKTOALPHA_FADDR ADDR_G2D_ALPHABLEND
+#define G2D_ALPHABLEND_MASKTOALPHA_FSHIFT 15
+#define G2D_ALPHABLEND_MASKTOALPHA_FMASK 0x1
+#define G2D_BACKGROUND_COLOR_FADDR ADDR_G2D_BACKGROUND
+#define G2D_BACKGROUND_COLOR_FSHIFT 0
+#define G2D_BACKGROUND_COLOR_FMASK 0xffffffff
+#define G2D_BASE0_ADDR_FADDR ADDR_G2D_BASE0
+#define G2D_BASE0_ADDR_FSHIFT 0
+#define G2D_BASE0_ADDR_FMASK 0xffffffff
+#define G2D_BASE1_ADDR_FADDR ADDR_G2D_BASE1
+#define G2D_BASE1_ADDR_FSHIFT 0
+#define G2D_BASE1_ADDR_FMASK 0xffffffff
+#define G2D_BASE2_ADDR_FADDR ADDR_G2D_BASE2
+#define G2D_BASE2_ADDR_FSHIFT 0
+#define G2D_BASE2_ADDR_FMASK 0xffffffff
+#define G2D_BASE3_ADDR_FADDR ADDR_G2D_BASE3
+#define G2D_BASE3_ADDR_FSHIFT 0
+#define G2D_BASE3_ADDR_FMASK 0xffffffff
+#define G2D_BLENDERCFG_PASSES_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_PASSES_FSHIFT 0
+#define G2D_BLENDERCFG_PASSES_FMASK 0x7
+#define G2D_BLENDERCFG_ALPHAPASSES_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_ALPHAPASSES_FSHIFT 3
+#define G2D_BLENDERCFG_ALPHAPASSES_FMASK 0x3
+#define G2D_BLENDERCFG_ENABLE_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_ENABLE_FSHIFT 5
+#define G2D_BLENDERCFG_ENABLE_FMASK 0x1
+#define G2D_BLENDERCFG_OOALPHA_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_OOALPHA_FSHIFT 6
+#define G2D_BLENDERCFG_OOALPHA_FMASK 0x1
+#define G2D_BLENDERCFG_OBS_DIVALPHA_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_OBS_DIVALPHA_FSHIFT 7
+#define G2D_BLENDERCFG_OBS_DIVALPHA_FMASK 0x1
+#define G2D_BLENDERCFG_NOMASK_FADDR ADDR_G2D_BLENDERCFG
+#define G2D_BLENDERCFG_NOMASK_FSHIFT 8
+#define G2D_BLENDERCFG_NOMASK_FMASK 0x1
+#define G2D_BLEND_A0_OPERATION_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_OPERATION_FSHIFT 0
+#define G2D_BLEND_A0_OPERATION_FMASK 0x3
+#define G2D_BLEND_A0_DST_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_DST_A_FSHIFT 2
+#define G2D_BLEND_A0_DST_A_FMASK 0x3
+#define G2D_BLEND_A0_DST_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_DST_B_FSHIFT 4
+#define G2D_BLEND_A0_DST_B_FMASK 0x3
+#define G2D_BLEND_A0_DST_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_DST_C_FSHIFT 6
+#define G2D_BLEND_A0_DST_C_FMASK 0x3
+#define G2D_BLEND_A0_AR_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_A_FSHIFT 8
+#define G2D_BLEND_A0_AR_A_FMASK 0x1
+#define G2D_BLEND_A0_AR_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_B_FSHIFT 9
+#define G2D_BLEND_A0_AR_B_FMASK 0x1
+#define G2D_BLEND_A0_AR_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_C_FSHIFT 10
+#define G2D_BLEND_A0_AR_C_FMASK 0x1
+#define G2D_BLEND_A0_AR_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_AR_D_FSHIFT 11
+#define G2D_BLEND_A0_AR_D_FMASK 0x1
+#define G2D_BLEND_A0_INV_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_A_FSHIFT 12
+#define G2D_BLEND_A0_INV_A_FMASK 0x1
+#define G2D_BLEND_A0_INV_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_B_FSHIFT 13
+#define G2D_BLEND_A0_INV_B_FMASK 0x1
+#define G2D_BLEND_A0_INV_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_C_FSHIFT 14
+#define G2D_BLEND_A0_INV_C_FMASK 0x1
+#define G2D_BLEND_A0_INV_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_INV_D_FSHIFT 15
+#define G2D_BLEND_A0_INV_D_FMASK 0x1
+#define G2D_BLEND_A0_SRC_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_A_FSHIFT 16
+#define G2D_BLEND_A0_SRC_A_FMASK 0x7
+#define G2D_BLEND_A0_SRC_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_B_FSHIFT 19
+#define G2D_BLEND_A0_SRC_B_FMASK 0x7
+#define G2D_BLEND_A0_SRC_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_C_FSHIFT 22
+#define G2D_BLEND_A0_SRC_C_FMASK 0x7
+#define G2D_BLEND_A0_SRC_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_SRC_D_FSHIFT 25
+#define G2D_BLEND_A0_SRC_D_FMASK 0x7
+#define G2D_BLEND_A0_CONST_A_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_A_FSHIFT 28
+#define G2D_BLEND_A0_CONST_A_FMASK 0x1
+#define G2D_BLEND_A0_CONST_B_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_B_FSHIFT 29
+#define G2D_BLEND_A0_CONST_B_FMASK 0x1
+#define G2D_BLEND_A0_CONST_C_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_C_FSHIFT 30
+#define G2D_BLEND_A0_CONST_C_FMASK 0x1
+#define G2D_BLEND_A0_CONST_D_FADDR ADDR_G2D_BLEND_A0
+#define G2D_BLEND_A0_CONST_D_FSHIFT 31
+#define G2D_BLEND_A0_CONST_D_FMASK 0x1
+#define G2D_BLEND_A1_OPERATION_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_OPERATION_FSHIFT 0
+#define G2D_BLEND_A1_OPERATION_FMASK 0x3
+#define G2D_BLEND_A1_DST_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_DST_A_FSHIFT 2
+#define G2D_BLEND_A1_DST_A_FMASK 0x3
+#define G2D_BLEND_A1_DST_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_DST_B_FSHIFT 4
+#define G2D_BLEND_A1_DST_B_FMASK 0x3
+#define G2D_BLEND_A1_DST_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_DST_C_FSHIFT 6
+#define G2D_BLEND_A1_DST_C_FMASK 0x3
+#define G2D_BLEND_A1_AR_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_A_FSHIFT 8
+#define G2D_BLEND_A1_AR_A_FMASK 0x1
+#define G2D_BLEND_A1_AR_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_B_FSHIFT 9
+#define G2D_BLEND_A1_AR_B_FMASK 0x1
+#define G2D_BLEND_A1_AR_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_C_FSHIFT 10
+#define G2D_BLEND_A1_AR_C_FMASK 0x1
+#define G2D_BLEND_A1_AR_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_AR_D_FSHIFT 11
+#define G2D_BLEND_A1_AR_D_FMASK 0x1
+#define G2D_BLEND_A1_INV_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_A_FSHIFT 12
+#define G2D_BLEND_A1_INV_A_FMASK 0x1
+#define G2D_BLEND_A1_INV_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_B_FSHIFT 13
+#define G2D_BLEND_A1_INV_B_FMASK 0x1
+#define G2D_BLEND_A1_INV_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_C_FSHIFT 14
+#define G2D_BLEND_A1_INV_C_FMASK 0x1
+#define G2D_BLEND_A1_INV_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_INV_D_FSHIFT 15
+#define G2D_BLEND_A1_INV_D_FMASK 0x1
+#define G2D_BLEND_A1_SRC_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_A_FSHIFT 16
+#define G2D_BLEND_A1_SRC_A_FMASK 0x7
+#define G2D_BLEND_A1_SRC_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_B_FSHIFT 19
+#define G2D_BLEND_A1_SRC_B_FMASK 0x7
+#define G2D_BLEND_A1_SRC_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_C_FSHIFT 22
+#define G2D_BLEND_A1_SRC_C_FMASK 0x7
+#define G2D_BLEND_A1_SRC_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_SRC_D_FSHIFT 25
+#define G2D_BLEND_A1_SRC_D_FMASK 0x7
+#define G2D_BLEND_A1_CONST_A_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_A_FSHIFT 28
+#define G2D_BLEND_A1_CONST_A_FMASK 0x1
+#define G2D_BLEND_A1_CONST_B_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_B_FSHIFT 29
+#define G2D_BLEND_A1_CONST_B_FMASK 0x1
+#define G2D_BLEND_A1_CONST_C_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_C_FSHIFT 30
+#define G2D_BLEND_A1_CONST_C_FMASK 0x1
+#define G2D_BLEND_A1_CONST_D_FADDR ADDR_G2D_BLEND_A1
+#define G2D_BLEND_A1_CONST_D_FSHIFT 31
+#define G2D_BLEND_A1_CONST_D_FMASK 0x1
+#define G2D_BLEND_A2_OPERATION_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_OPERATION_FSHIFT 0
+#define G2D_BLEND_A2_OPERATION_FMASK 0x3
+#define G2D_BLEND_A2_DST_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_DST_A_FSHIFT 2
+#define G2D_BLEND_A2_DST_A_FMASK 0x3
+#define G2D_BLEND_A2_DST_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_DST_B_FSHIFT 4
+#define G2D_BLEND_A2_DST_B_FMASK 0x3
+#define G2D_BLEND_A2_DST_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_DST_C_FSHIFT 6
+#define G2D_BLEND_A2_DST_C_FMASK 0x3
+#define G2D_BLEND_A2_AR_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_A_FSHIFT 8
+#define G2D_BLEND_A2_AR_A_FMASK 0x1
+#define G2D_BLEND_A2_AR_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_B_FSHIFT 9
+#define G2D_BLEND_A2_AR_B_FMASK 0x1
+#define G2D_BLEND_A2_AR_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_C_FSHIFT 10
+#define G2D_BLEND_A2_AR_C_FMASK 0x1
+#define G2D_BLEND_A2_AR_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_AR_D_FSHIFT 11
+#define G2D_BLEND_A2_AR_D_FMASK 0x1
+#define G2D_BLEND_A2_INV_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_A_FSHIFT 12
+#define G2D_BLEND_A2_INV_A_FMASK 0x1
+#define G2D_BLEND_A2_INV_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_B_FSHIFT 13
+#define G2D_BLEND_A2_INV_B_FMASK 0x1
+#define G2D_BLEND_A2_INV_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_C_FSHIFT 14
+#define G2D_BLEND_A2_INV_C_FMASK 0x1
+#define G2D_BLEND_A2_INV_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_INV_D_FSHIFT 15
+#define G2D_BLEND_A2_INV_D_FMASK 0x1
+#define G2D_BLEND_A2_SRC_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_A_FSHIFT 16
+#define G2D_BLEND_A2_SRC_A_FMASK 0x7
+#define G2D_BLEND_A2_SRC_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_B_FSHIFT 19
+#define G2D_BLEND_A2_SRC_B_FMASK 0x7
+#define G2D_BLEND_A2_SRC_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_C_FSHIFT 22
+#define G2D_BLEND_A2_SRC_C_FMASK 0x7
+#define G2D_BLEND_A2_SRC_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_SRC_D_FSHIFT 25
+#define G2D_BLEND_A2_SRC_D_FMASK 0x7
+#define G2D_BLEND_A2_CONST_A_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_A_FSHIFT 28
+#define G2D_BLEND_A2_CONST_A_FMASK 0x1
+#define G2D_BLEND_A2_CONST_B_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_B_FSHIFT 29
+#define G2D_BLEND_A2_CONST_B_FMASK 0x1
+#define G2D_BLEND_A2_CONST_C_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_C_FSHIFT 30
+#define G2D_BLEND_A2_CONST_C_FMASK 0x1
+#define G2D_BLEND_A2_CONST_D_FADDR ADDR_G2D_BLEND_A2
+#define G2D_BLEND_A2_CONST_D_FSHIFT 31
+#define G2D_BLEND_A2_CONST_D_FMASK 0x1
+#define G2D_BLEND_A3_OPERATION_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_OPERATION_FSHIFT 0
+#define G2D_BLEND_A3_OPERATION_FMASK 0x3
+#define G2D_BLEND_A3_DST_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_DST_A_FSHIFT 2
+#define G2D_BLEND_A3_DST_A_FMASK 0x3
+#define G2D_BLEND_A3_DST_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_DST_B_FSHIFT 4
+#define G2D_BLEND_A3_DST_B_FMASK 0x3
+#define G2D_BLEND_A3_DST_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_DST_C_FSHIFT 6
+#define G2D_BLEND_A3_DST_C_FMASK 0x3
+#define G2D_BLEND_A3_AR_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_A_FSHIFT 8
+#define G2D_BLEND_A3_AR_A_FMASK 0x1
+#define G2D_BLEND_A3_AR_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_B_FSHIFT 9
+#define G2D_BLEND_A3_AR_B_FMASK 0x1
+#define G2D_BLEND_A3_AR_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_C_FSHIFT 10
+#define G2D_BLEND_A3_AR_C_FMASK 0x1
+#define G2D_BLEND_A3_AR_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_AR_D_FSHIFT 11
+#define G2D_BLEND_A3_AR_D_FMASK 0x1
+#define G2D_BLEND_A3_INV_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_A_FSHIFT 12
+#define G2D_BLEND_A3_INV_A_FMASK 0x1
+#define G2D_BLEND_A3_INV_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_B_FSHIFT 13
+#define G2D_BLEND_A3_INV_B_FMASK 0x1
+#define G2D_BLEND_A3_INV_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_C_FSHIFT 14
+#define G2D_BLEND_A3_INV_C_FMASK 0x1
+#define G2D_BLEND_A3_INV_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_INV_D_FSHIFT 15
+#define G2D_BLEND_A3_INV_D_FMASK 0x1
+#define G2D_BLEND_A3_SRC_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_A_FSHIFT 16
+#define G2D_BLEND_A3_SRC_A_FMASK 0x7
+#define G2D_BLEND_A3_SRC_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_B_FSHIFT 19
+#define G2D_BLEND_A3_SRC_B_FMASK 0x7
+#define G2D_BLEND_A3_SRC_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_C_FSHIFT 22
+#define G2D_BLEND_A3_SRC_C_FMASK 0x7
+#define G2D_BLEND_A3_SRC_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_SRC_D_FSHIFT 25
+#define G2D_BLEND_A3_SRC_D_FMASK 0x7
+#define G2D_BLEND_A3_CONST_A_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_A_FSHIFT 28
+#define G2D_BLEND_A3_CONST_A_FMASK 0x1
+#define G2D_BLEND_A3_CONST_B_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_B_FSHIFT 29
+#define G2D_BLEND_A3_CONST_B_FMASK 0x1
+#define G2D_BLEND_A3_CONST_C_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_C_FSHIFT 30
+#define G2D_BLEND_A3_CONST_C_FMASK 0x1
+#define G2D_BLEND_A3_CONST_D_FADDR ADDR_G2D_BLEND_A3
+#define G2D_BLEND_A3_CONST_D_FSHIFT 31
+#define G2D_BLEND_A3_CONST_D_FMASK 0x1
+#define G2D_BLEND_C0_OPERATION_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_OPERATION_FSHIFT 0
+#define G2D_BLEND_C0_OPERATION_FMASK 0x3
+#define G2D_BLEND_C0_DST_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_DST_A_FSHIFT 2
+#define G2D_BLEND_C0_DST_A_FMASK 0x3
+#define G2D_BLEND_C0_DST_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_DST_B_FSHIFT 4
+#define G2D_BLEND_C0_DST_B_FMASK 0x3
+#define G2D_BLEND_C0_DST_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_DST_C_FSHIFT 6
+#define G2D_BLEND_C0_DST_C_FMASK 0x3
+#define G2D_BLEND_C0_AR_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_A_FSHIFT 8
+#define G2D_BLEND_C0_AR_A_FMASK 0x1
+#define G2D_BLEND_C0_AR_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_B_FSHIFT 9
+#define G2D_BLEND_C0_AR_B_FMASK 0x1
+#define G2D_BLEND_C0_AR_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_C_FSHIFT 10
+#define G2D_BLEND_C0_AR_C_FMASK 0x1
+#define G2D_BLEND_C0_AR_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_AR_D_FSHIFT 11
+#define G2D_BLEND_C0_AR_D_FMASK 0x1
+#define G2D_BLEND_C0_INV_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_A_FSHIFT 12
+#define G2D_BLEND_C0_INV_A_FMASK 0x1
+#define G2D_BLEND_C0_INV_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_B_FSHIFT 13
+#define G2D_BLEND_C0_INV_B_FMASK 0x1
+#define G2D_BLEND_C0_INV_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_C_FSHIFT 14
+#define G2D_BLEND_C0_INV_C_FMASK 0x1
+#define G2D_BLEND_C0_INV_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_INV_D_FSHIFT 15
+#define G2D_BLEND_C0_INV_D_FMASK 0x1
+#define G2D_BLEND_C0_SRC_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_A_FSHIFT 16
+#define G2D_BLEND_C0_SRC_A_FMASK 0x7
+#define G2D_BLEND_C0_SRC_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_B_FSHIFT 19
+#define G2D_BLEND_C0_SRC_B_FMASK 0x7
+#define G2D_BLEND_C0_SRC_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_C_FSHIFT 22
+#define G2D_BLEND_C0_SRC_C_FMASK 0x7
+#define G2D_BLEND_C0_SRC_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_SRC_D_FSHIFT 25
+#define G2D_BLEND_C0_SRC_D_FMASK 0x7
+#define G2D_BLEND_C0_CONST_A_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_A_FSHIFT 28
+#define G2D_BLEND_C0_CONST_A_FMASK 0x1
+#define G2D_BLEND_C0_CONST_B_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_B_FSHIFT 29
+#define G2D_BLEND_C0_CONST_B_FMASK 0x1
+#define G2D_BLEND_C0_CONST_C_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_C_FSHIFT 30
+#define G2D_BLEND_C0_CONST_C_FMASK 0x1
+#define G2D_BLEND_C0_CONST_D_FADDR ADDR_G2D_BLEND_C0
+#define G2D_BLEND_C0_CONST_D_FSHIFT 31
+#define G2D_BLEND_C0_CONST_D_FMASK 0x1
+#define G2D_BLEND_C1_OPERATION_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_OPERATION_FSHIFT 0
+#define G2D_BLEND_C1_OPERATION_FMASK 0x3
+#define G2D_BLEND_C1_DST_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_DST_A_FSHIFT 2
+#define G2D_BLEND_C1_DST_A_FMASK 0x3
+#define G2D_BLEND_C1_DST_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_DST_B_FSHIFT 4
+#define G2D_BLEND_C1_DST_B_FMASK 0x3
+#define G2D_BLEND_C1_DST_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_DST_C_FSHIFT 6
+#define G2D_BLEND_C1_DST_C_FMASK 0x3
+#define G2D_BLEND_C1_AR_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_A_FSHIFT 8
+#define G2D_BLEND_C1_AR_A_FMASK 0x1
+#define G2D_BLEND_C1_AR_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_B_FSHIFT 9
+#define G2D_BLEND_C1_AR_B_FMASK 0x1
+#define G2D_BLEND_C1_AR_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_C_FSHIFT 10
+#define G2D_BLEND_C1_AR_C_FMASK 0x1
+#define G2D_BLEND_C1_AR_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_AR_D_FSHIFT 11
+#define G2D_BLEND_C1_AR_D_FMASK 0x1
+#define G2D_BLEND_C1_INV_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_A_FSHIFT 12
+#define G2D_BLEND_C1_INV_A_FMASK 0x1
+#define G2D_BLEND_C1_INV_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_B_FSHIFT 13
+#define G2D_BLEND_C1_INV_B_FMASK 0x1
+#define G2D_BLEND_C1_INV_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_C_FSHIFT 14
+#define G2D_BLEND_C1_INV_C_FMASK 0x1
+#define G2D_BLEND_C1_INV_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_INV_D_FSHIFT 15
+#define G2D_BLEND_C1_INV_D_FMASK 0x1
+#define G2D_BLEND_C1_SRC_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_A_FSHIFT 16
+#define G2D_BLEND_C1_SRC_A_FMASK 0x7
+#define G2D_BLEND_C1_SRC_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_B_FSHIFT 19
+#define G2D_BLEND_C1_SRC_B_FMASK 0x7
+#define G2D_BLEND_C1_SRC_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_C_FSHIFT 22
+#define G2D_BLEND_C1_SRC_C_FMASK 0x7
+#define G2D_BLEND_C1_SRC_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_SRC_D_FSHIFT 25
+#define G2D_BLEND_C1_SRC_D_FMASK 0x7
+#define G2D_BLEND_C1_CONST_A_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_A_FSHIFT 28
+#define G2D_BLEND_C1_CONST_A_FMASK 0x1
+#define G2D_BLEND_C1_CONST_B_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_B_FSHIFT 29
+#define G2D_BLEND_C1_CONST_B_FMASK 0x1
+#define G2D_BLEND_C1_CONST_C_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_C_FSHIFT 30
+#define G2D_BLEND_C1_CONST_C_FMASK 0x1
+#define G2D_BLEND_C1_CONST_D_FADDR ADDR_G2D_BLEND_C1
+#define G2D_BLEND_C1_CONST_D_FSHIFT 31
+#define G2D_BLEND_C1_CONST_D_FMASK 0x1
+#define G2D_BLEND_C2_OPERATION_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_OPERATION_FSHIFT 0
+#define G2D_BLEND_C2_OPERATION_FMASK 0x3
+#define G2D_BLEND_C2_DST_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_DST_A_FSHIFT 2
+#define G2D_BLEND_C2_DST_A_FMASK 0x3
+#define G2D_BLEND_C2_DST_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_DST_B_FSHIFT 4
+#define G2D_BLEND_C2_DST_B_FMASK 0x3
+#define G2D_BLEND_C2_DST_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_DST_C_FSHIFT 6
+#define G2D_BLEND_C2_DST_C_FMASK 0x3
+#define G2D_BLEND_C2_AR_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_A_FSHIFT 8
+#define G2D_BLEND_C2_AR_A_FMASK 0x1
+#define G2D_BLEND_C2_AR_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_B_FSHIFT 9
+#define G2D_BLEND_C2_AR_B_FMASK 0x1
+#define G2D_BLEND_C2_AR_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_C_FSHIFT 10
+#define G2D_BLEND_C2_AR_C_FMASK 0x1
+#define G2D_BLEND_C2_AR_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_AR_D_FSHIFT 11
+#define G2D_BLEND_C2_AR_D_FMASK 0x1
+#define G2D_BLEND_C2_INV_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_A_FSHIFT 12
+#define G2D_BLEND_C2_INV_A_FMASK 0x1
+#define G2D_BLEND_C2_INV_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_B_FSHIFT 13
+#define G2D_BLEND_C2_INV_B_FMASK 0x1
+#define G2D_BLEND_C2_INV_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_C_FSHIFT 14
+#define G2D_BLEND_C2_INV_C_FMASK 0x1
+#define G2D_BLEND_C2_INV_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_INV_D_FSHIFT 15
+#define G2D_BLEND_C2_INV_D_FMASK 0x1
+#define G2D_BLEND_C2_SRC_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_A_FSHIFT 16
+#define G2D_BLEND_C2_SRC_A_FMASK 0x7
+#define G2D_BLEND_C2_SRC_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_B_FSHIFT 19
+#define G2D_BLEND_C2_SRC_B_FMASK 0x7
+#define G2D_BLEND_C2_SRC_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_C_FSHIFT 22
+#define G2D_BLEND_C2_SRC_C_FMASK 0x7
+#define G2D_BLEND_C2_SRC_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_SRC_D_FSHIFT 25
+#define G2D_BLEND_C2_SRC_D_FMASK 0x7
+#define G2D_BLEND_C2_CONST_A_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_A_FSHIFT 28
+#define G2D_BLEND_C2_CONST_A_FMASK 0x1
+#define G2D_BLEND_C2_CONST_B_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_B_FSHIFT 29
+#define G2D_BLEND_C2_CONST_B_FMASK 0x1
+#define G2D_BLEND_C2_CONST_C_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_C_FSHIFT 30
+#define G2D_BLEND_C2_CONST_C_FMASK 0x1
+#define G2D_BLEND_C2_CONST_D_FADDR ADDR_G2D_BLEND_C2
+#define G2D_BLEND_C2_CONST_D_FSHIFT 31
+#define G2D_BLEND_C2_CONST_D_FMASK 0x1
+#define G2D_BLEND_C3_OPERATION_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_OPERATION_FSHIFT 0
+#define G2D_BLEND_C3_OPERATION_FMASK 0x3
+#define G2D_BLEND_C3_DST_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_DST_A_FSHIFT 2
+#define G2D_BLEND_C3_DST_A_FMASK 0x3
+#define G2D_BLEND_C3_DST_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_DST_B_FSHIFT 4
+#define G2D_BLEND_C3_DST_B_FMASK 0x3
+#define G2D_BLEND_C3_DST_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_DST_C_FSHIFT 6
+#define G2D_BLEND_C3_DST_C_FMASK 0x3
+#define G2D_BLEND_C3_AR_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_A_FSHIFT 8
+#define G2D_BLEND_C3_AR_A_FMASK 0x1
+#define G2D_BLEND_C3_AR_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_B_FSHIFT 9
+#define G2D_BLEND_C3_AR_B_FMASK 0x1
+#define G2D_BLEND_C3_AR_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_C_FSHIFT 10
+#define G2D_BLEND_C3_AR_C_FMASK 0x1
+#define G2D_BLEND_C3_AR_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_AR_D_FSHIFT 11
+#define G2D_BLEND_C3_AR_D_FMASK 0x1
+#define G2D_BLEND_C3_INV_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_A_FSHIFT 12
+#define G2D_BLEND_C3_INV_A_FMASK 0x1
+#define G2D_BLEND_C3_INV_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_B_FSHIFT 13
+#define G2D_BLEND_C3_INV_B_FMASK 0x1
+#define G2D_BLEND_C3_INV_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_C_FSHIFT 14
+#define G2D_BLEND_C3_INV_C_FMASK 0x1
+#define G2D_BLEND_C3_INV_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_INV_D_FSHIFT 15
+#define G2D_BLEND_C3_INV_D_FMASK 0x1
+#define G2D_BLEND_C3_SRC_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_A_FSHIFT 16
+#define G2D_BLEND_C3_SRC_A_FMASK 0x7
+#define G2D_BLEND_C3_SRC_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_B_FSHIFT 19
+#define G2D_BLEND_C3_SRC_B_FMASK 0x7
+#define G2D_BLEND_C3_SRC_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_C_FSHIFT 22
+#define G2D_BLEND_C3_SRC_C_FMASK 0x7
+#define G2D_BLEND_C3_SRC_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_SRC_D_FSHIFT 25
+#define G2D_BLEND_C3_SRC_D_FMASK 0x7
+#define G2D_BLEND_C3_CONST_A_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_A_FSHIFT 28
+#define G2D_BLEND_C3_CONST_A_FMASK 0x1
+#define G2D_BLEND_C3_CONST_B_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_B_FSHIFT 29
+#define G2D_BLEND_C3_CONST_B_FMASK 0x1
+#define G2D_BLEND_C3_CONST_C_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_C_FSHIFT 30
+#define G2D_BLEND_C3_CONST_C_FMASK 0x1
+#define G2D_BLEND_C3_CONST_D_FADDR ADDR_G2D_BLEND_C3
+#define G2D_BLEND_C3_CONST_D_FSHIFT 31
+#define G2D_BLEND_C3_CONST_D_FMASK 0x1
+#define G2D_BLEND_C4_OPERATION_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_OPERATION_FSHIFT 0
+#define G2D_BLEND_C4_OPERATION_FMASK 0x3
+#define G2D_BLEND_C4_DST_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_DST_A_FSHIFT 2
+#define G2D_BLEND_C4_DST_A_FMASK 0x3
+#define G2D_BLEND_C4_DST_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_DST_B_FSHIFT 4
+#define G2D_BLEND_C4_DST_B_FMASK 0x3
+#define G2D_BLEND_C4_DST_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_DST_C_FSHIFT 6
+#define G2D_BLEND_C4_DST_C_FMASK 0x3
+#define G2D_BLEND_C4_AR_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_A_FSHIFT 8
+#define G2D_BLEND_C4_AR_A_FMASK 0x1
+#define G2D_BLEND_C4_AR_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_B_FSHIFT 9
+#define G2D_BLEND_C4_AR_B_FMASK 0x1
+#define G2D_BLEND_C4_AR_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_C_FSHIFT 10
+#define G2D_BLEND_C4_AR_C_FMASK 0x1
+#define G2D_BLEND_C4_AR_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_AR_D_FSHIFT 11
+#define G2D_BLEND_C4_AR_D_FMASK 0x1
+#define G2D_BLEND_C4_INV_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_A_FSHIFT 12
+#define G2D_BLEND_C4_INV_A_FMASK 0x1
+#define G2D_BLEND_C4_INV_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_B_FSHIFT 13
+#define G2D_BLEND_C4_INV_B_FMASK 0x1
+#define G2D_BLEND_C4_INV_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_C_FSHIFT 14
+#define G2D_BLEND_C4_INV_C_FMASK 0x1
+#define G2D_BLEND_C4_INV_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_INV_D_FSHIFT 15
+#define G2D_BLEND_C4_INV_D_FMASK 0x1
+#define G2D_BLEND_C4_SRC_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_A_FSHIFT 16
+#define G2D_BLEND_C4_SRC_A_FMASK 0x7
+#define G2D_BLEND_C4_SRC_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_B_FSHIFT 19
+#define G2D_BLEND_C4_SRC_B_FMASK 0x7
+#define G2D_BLEND_C4_SRC_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_C_FSHIFT 22
+#define G2D_BLEND_C4_SRC_C_FMASK 0x7
+#define G2D_BLEND_C4_SRC_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_SRC_D_FSHIFT 25
+#define G2D_BLEND_C4_SRC_D_FMASK 0x7
+#define G2D_BLEND_C4_CONST_A_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_A_FSHIFT 28
+#define G2D_BLEND_C4_CONST_A_FMASK 0x1
+#define G2D_BLEND_C4_CONST_B_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_B_FSHIFT 29
+#define G2D_BLEND_C4_CONST_B_FMASK 0x1
+#define G2D_BLEND_C4_CONST_C_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_C_FSHIFT 30
+#define G2D_BLEND_C4_CONST_C_FMASK 0x1
+#define G2D_BLEND_C4_CONST_D_FADDR ADDR_G2D_BLEND_C4
+#define G2D_BLEND_C4_CONST_D_FSHIFT 31
+#define G2D_BLEND_C4_CONST_D_FMASK 0x1
+#define G2D_BLEND_C5_OPERATION_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_OPERATION_FSHIFT 0
+#define G2D_BLEND_C5_OPERATION_FMASK 0x3
+#define G2D_BLEND_C5_DST_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_DST_A_FSHIFT 2
+#define G2D_BLEND_C5_DST_A_FMASK 0x3
+#define G2D_BLEND_C5_DST_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_DST_B_FSHIFT 4
+#define G2D_BLEND_C5_DST_B_FMASK 0x3
+#define G2D_BLEND_C5_DST_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_DST_C_FSHIFT 6
+#define G2D_BLEND_C5_DST_C_FMASK 0x3
+#define G2D_BLEND_C5_AR_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_A_FSHIFT 8
+#define G2D_BLEND_C5_AR_A_FMASK 0x1
+#define G2D_BLEND_C5_AR_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_B_FSHIFT 9
+#define G2D_BLEND_C5_AR_B_FMASK 0x1
+#define G2D_BLEND_C5_AR_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_C_FSHIFT 10
+#define G2D_BLEND_C5_AR_C_FMASK 0x1
+#define G2D_BLEND_C5_AR_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_AR_D_FSHIFT 11
+#define G2D_BLEND_C5_AR_D_FMASK 0x1
+#define G2D_BLEND_C5_INV_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_A_FSHIFT 12
+#define G2D_BLEND_C5_INV_A_FMASK 0x1
+#define G2D_BLEND_C5_INV_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_B_FSHIFT 13
+#define G2D_BLEND_C5_INV_B_FMASK 0x1
+#define G2D_BLEND_C5_INV_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_C_FSHIFT 14
+#define G2D_BLEND_C5_INV_C_FMASK 0x1
+#define G2D_BLEND_C5_INV_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_INV_D_FSHIFT 15
+#define G2D_BLEND_C5_INV_D_FMASK 0x1
+#define G2D_BLEND_C5_SRC_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_A_FSHIFT 16
+#define G2D_BLEND_C5_SRC_A_FMASK 0x7
+#define G2D_BLEND_C5_SRC_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_B_FSHIFT 19
+#define G2D_BLEND_C5_SRC_B_FMASK 0x7
+#define G2D_BLEND_C5_SRC_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_C_FSHIFT 22
+#define G2D_BLEND_C5_SRC_C_FMASK 0x7
+#define G2D_BLEND_C5_SRC_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_SRC_D_FSHIFT 25
+#define G2D_BLEND_C5_SRC_D_FMASK 0x7
+#define G2D_BLEND_C5_CONST_A_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_A_FSHIFT 28
+#define G2D_BLEND_C5_CONST_A_FMASK 0x1
+#define G2D_BLEND_C5_CONST_B_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_B_FSHIFT 29
+#define G2D_BLEND_C5_CONST_B_FMASK 0x1
+#define G2D_BLEND_C5_CONST_C_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_C_FSHIFT 30
+#define G2D_BLEND_C5_CONST_C_FMASK 0x1
+#define G2D_BLEND_C5_CONST_D_FADDR ADDR_G2D_BLEND_C5
+#define G2D_BLEND_C5_CONST_D_FSHIFT 31
+#define G2D_BLEND_C5_CONST_D_FMASK 0x1
+#define G2D_BLEND_C6_OPERATION_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_OPERATION_FSHIFT 0
+#define G2D_BLEND_C6_OPERATION_FMASK 0x3
+#define G2D_BLEND_C6_DST_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_DST_A_FSHIFT 2
+#define G2D_BLEND_C6_DST_A_FMASK 0x3
+#define G2D_BLEND_C6_DST_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_DST_B_FSHIFT 4
+#define G2D_BLEND_C6_DST_B_FMASK 0x3
+#define G2D_BLEND_C6_DST_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_DST_C_FSHIFT 6
+#define G2D_BLEND_C6_DST_C_FMASK 0x3
+#define G2D_BLEND_C6_AR_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_A_FSHIFT 8
+#define G2D_BLEND_C6_AR_A_FMASK 0x1
+#define G2D_BLEND_C6_AR_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_B_FSHIFT 9
+#define G2D_BLEND_C6_AR_B_FMASK 0x1
+#define G2D_BLEND_C6_AR_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_C_FSHIFT 10
+#define G2D_BLEND_C6_AR_C_FMASK 0x1
+#define G2D_BLEND_C6_AR_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_AR_D_FSHIFT 11
+#define G2D_BLEND_C6_AR_D_FMASK 0x1
+#define G2D_BLEND_C6_INV_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_A_FSHIFT 12
+#define G2D_BLEND_C6_INV_A_FMASK 0x1
+#define G2D_BLEND_C6_INV_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_B_FSHIFT 13
+#define G2D_BLEND_C6_INV_B_FMASK 0x1
+#define G2D_BLEND_C6_INV_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_C_FSHIFT 14
+#define G2D_BLEND_C6_INV_C_FMASK 0x1
+#define G2D_BLEND_C6_INV_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_INV_D_FSHIFT 15
+#define G2D_BLEND_C6_INV_D_FMASK 0x1
+#define G2D_BLEND_C6_SRC_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_A_FSHIFT 16
+#define G2D_BLEND_C6_SRC_A_FMASK 0x7
+#define G2D_BLEND_C6_SRC_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_B_FSHIFT 19
+#define G2D_BLEND_C6_SRC_B_FMASK 0x7
+#define G2D_BLEND_C6_SRC_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_C_FSHIFT 22
+#define G2D_BLEND_C6_SRC_C_FMASK 0x7
+#define G2D_BLEND_C6_SRC_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_SRC_D_FSHIFT 25
+#define G2D_BLEND_C6_SRC_D_FMASK 0x7
+#define G2D_BLEND_C6_CONST_A_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_A_FSHIFT 28
+#define G2D_BLEND_C6_CONST_A_FMASK 0x1
+#define G2D_BLEND_C6_CONST_B_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_B_FSHIFT 29
+#define G2D_BLEND_C6_CONST_B_FMASK 0x1
+#define G2D_BLEND_C6_CONST_C_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_C_FSHIFT 30
+#define G2D_BLEND_C6_CONST_C_FMASK 0x1
+#define G2D_BLEND_C6_CONST_D_FADDR ADDR_G2D_BLEND_C6
+#define G2D_BLEND_C6_CONST_D_FSHIFT 31
+#define G2D_BLEND_C6_CONST_D_FMASK 0x1
+#define G2D_BLEND_C7_OPERATION_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_OPERATION_FSHIFT 0
+#define G2D_BLEND_C7_OPERATION_FMASK 0x3
+#define G2D_BLEND_C7_DST_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_DST_A_FSHIFT 2
+#define G2D_BLEND_C7_DST_A_FMASK 0x3
+#define G2D_BLEND_C7_DST_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_DST_B_FSHIFT 4
+#define G2D_BLEND_C7_DST_B_FMASK 0x3
+#define G2D_BLEND_C7_DST_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_DST_C_FSHIFT 6
+#define G2D_BLEND_C7_DST_C_FMASK 0x3
+#define G2D_BLEND_C7_AR_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_A_FSHIFT 8
+#define G2D_BLEND_C7_AR_A_FMASK 0x1
+#define G2D_BLEND_C7_AR_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_B_FSHIFT 9
+#define G2D_BLEND_C7_AR_B_FMASK 0x1
+#define G2D_BLEND_C7_AR_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_C_FSHIFT 10
+#define G2D_BLEND_C7_AR_C_FMASK 0x1
+#define G2D_BLEND_C7_AR_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_AR_D_FSHIFT 11
+#define G2D_BLEND_C7_AR_D_FMASK 0x1
+#define G2D_BLEND_C7_INV_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_A_FSHIFT 12
+#define G2D_BLEND_C7_INV_A_FMASK 0x1
+#define G2D_BLEND_C7_INV_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_B_FSHIFT 13
+#define G2D_BLEND_C7_INV_B_FMASK 0x1
+#define G2D_BLEND_C7_INV_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_C_FSHIFT 14
+#define G2D_BLEND_C7_INV_C_FMASK 0x1
+#define G2D_BLEND_C7_INV_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_INV_D_FSHIFT 15
+#define G2D_BLEND_C7_INV_D_FMASK 0x1
+#define G2D_BLEND_C7_SRC_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_A_FSHIFT 16
+#define G2D_BLEND_C7_SRC_A_FMASK 0x7
+#define G2D_BLEND_C7_SRC_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_B_FSHIFT 19
+#define G2D_BLEND_C7_SRC_B_FMASK 0x7
+#define G2D_BLEND_C7_SRC_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_C_FSHIFT 22
+#define G2D_BLEND_C7_SRC_C_FMASK 0x7
+#define G2D_BLEND_C7_SRC_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_SRC_D_FSHIFT 25
+#define G2D_BLEND_C7_SRC_D_FMASK 0x7
+#define G2D_BLEND_C7_CONST_A_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_A_FSHIFT 28
+#define G2D_BLEND_C7_CONST_A_FMASK 0x1
+#define G2D_BLEND_C7_CONST_B_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_B_FSHIFT 29
+#define G2D_BLEND_C7_CONST_B_FMASK 0x1
+#define G2D_BLEND_C7_CONST_C_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_C_FSHIFT 30
+#define G2D_BLEND_C7_CONST_C_FMASK 0x1
+#define G2D_BLEND_C7_CONST_D_FADDR ADDR_G2D_BLEND_C7
+#define G2D_BLEND_C7_CONST_D_FSHIFT 31
+#define G2D_BLEND_C7_CONST_D_FMASK 0x1
+#define G2D_CFG0_STRIDE_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_STRIDE_FSHIFT 0
+#define G2D_CFG0_STRIDE_FMASK 0xfff
+#define G2D_CFG0_FORMAT_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_FORMAT_FSHIFT 12
+#define G2D_CFG0_FORMAT_FMASK 0xf
+#define G2D_CFG0_TILED_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_TILED_FSHIFT 16
+#define G2D_CFG0_TILED_FMASK 0x1
+#define G2D_CFG0_SRGB_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SRGB_FSHIFT 17
+#define G2D_CFG0_SRGB_FMASK 0x1
+#define G2D_CFG0_SWAPWORDS_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPWORDS_FSHIFT 18
+#define G2D_CFG0_SWAPWORDS_FMASK 0x1
+#define G2D_CFG0_SWAPBYTES_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPBYTES_FSHIFT 19
+#define G2D_CFG0_SWAPBYTES_FMASK 0x1
+#define G2D_CFG0_SWAPALL_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPALL_FSHIFT 20
+#define G2D_CFG0_SWAPALL_FMASK 0x1
+#define G2D_CFG0_SWAPRB_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPRB_FSHIFT 21
+#define G2D_CFG0_SWAPRB_FMASK 0x1
+#define G2D_CFG0_SWAPBITS_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_SWAPBITS_FSHIFT 22
+#define G2D_CFG0_SWAPBITS_FMASK 0x1
+#define G2D_CFG0_STRIDESIGN_FADDR ADDR_G2D_CFG0
+#define G2D_CFG0_STRIDESIGN_FSHIFT 23
+#define G2D_CFG0_STRIDESIGN_FMASK 0x1
+#define G2D_CFG1_STRIDE_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_STRIDE_FSHIFT 0
+#define G2D_CFG1_STRIDE_FMASK 0xfff
+#define G2D_CFG1_FORMAT_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_FORMAT_FSHIFT 12
+#define G2D_CFG1_FORMAT_FMASK 0xf
+#define G2D_CFG1_TILED_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_TILED_FSHIFT 16
+#define G2D_CFG1_TILED_FMASK 0x1
+#define G2D_CFG1_SRGB_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SRGB_FSHIFT 17
+#define G2D_CFG1_SRGB_FMASK 0x1
+#define G2D_CFG1_SWAPWORDS_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPWORDS_FSHIFT 18
+#define G2D_CFG1_SWAPWORDS_FMASK 0x1
+#define G2D_CFG1_SWAPBYTES_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPBYTES_FSHIFT 19
+#define G2D_CFG1_SWAPBYTES_FMASK 0x1
+#define G2D_CFG1_SWAPALL_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPALL_FSHIFT 20
+#define G2D_CFG1_SWAPALL_FMASK 0x1
+#define G2D_CFG1_SWAPRB_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPRB_FSHIFT 21
+#define G2D_CFG1_SWAPRB_FMASK 0x1
+#define G2D_CFG1_SWAPBITS_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_SWAPBITS_FSHIFT 22
+#define G2D_CFG1_SWAPBITS_FMASK 0x1
+#define G2D_CFG1_STRIDESIGN_FADDR ADDR_G2D_CFG1
+#define G2D_CFG1_STRIDESIGN_FSHIFT 23
+#define G2D_CFG1_STRIDESIGN_FMASK 0x1
+#define G2D_CFG2_STRIDE_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_STRIDE_FSHIFT 0
+#define G2D_CFG2_STRIDE_FMASK 0xfff
+#define G2D_CFG2_FORMAT_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_FORMAT_FSHIFT 12
+#define G2D_CFG2_FORMAT_FMASK 0xf
+#define G2D_CFG2_TILED_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_TILED_FSHIFT 16
+#define G2D_CFG2_TILED_FMASK 0x1
+#define G2D_CFG2_SRGB_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SRGB_FSHIFT 17
+#define G2D_CFG2_SRGB_FMASK 0x1
+#define G2D_CFG2_SWAPWORDS_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPWORDS_FSHIFT 18
+#define G2D_CFG2_SWAPWORDS_FMASK 0x1
+#define G2D_CFG2_SWAPBYTES_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPBYTES_FSHIFT 19
+#define G2D_CFG2_SWAPBYTES_FMASK 0x1
+#define G2D_CFG2_SWAPALL_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPALL_FSHIFT 20
+#define G2D_CFG2_SWAPALL_FMASK 0x1
+#define G2D_CFG2_SWAPRB_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPRB_FSHIFT 21
+#define G2D_CFG2_SWAPRB_FMASK 0x1
+#define G2D_CFG2_SWAPBITS_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_SWAPBITS_FSHIFT 22
+#define G2D_CFG2_SWAPBITS_FMASK 0x1
+#define G2D_CFG2_STRIDESIGN_FADDR ADDR_G2D_CFG2
+#define G2D_CFG2_STRIDESIGN_FSHIFT 23
+#define G2D_CFG2_STRIDESIGN_FMASK 0x1
+#define G2D_CFG3_STRIDE_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_STRIDE_FSHIFT 0
+#define G2D_CFG3_STRIDE_FMASK 0xfff
+#define G2D_CFG3_FORMAT_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_FORMAT_FSHIFT 12
+#define G2D_CFG3_FORMAT_FMASK 0xf
+#define G2D_CFG3_TILED_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_TILED_FSHIFT 16
+#define G2D_CFG3_TILED_FMASK 0x1
+#define G2D_CFG3_SRGB_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SRGB_FSHIFT 17
+#define G2D_CFG3_SRGB_FMASK 0x1
+#define G2D_CFG3_SWAPWORDS_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPWORDS_FSHIFT 18
+#define G2D_CFG3_SWAPWORDS_FMASK 0x1
+#define G2D_CFG3_SWAPBYTES_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPBYTES_FSHIFT 19
+#define G2D_CFG3_SWAPBYTES_FMASK 0x1
+#define G2D_CFG3_SWAPALL_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPALL_FSHIFT 20
+#define G2D_CFG3_SWAPALL_FMASK 0x1
+#define G2D_CFG3_SWAPRB_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPRB_FSHIFT 21
+#define G2D_CFG3_SWAPRB_FMASK 0x1
+#define G2D_CFG3_SWAPBITS_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_SWAPBITS_FSHIFT 22
+#define G2D_CFG3_SWAPBITS_FMASK 0x1
+#define G2D_CFG3_STRIDESIGN_FADDR ADDR_G2D_CFG3
+#define G2D_CFG3_STRIDESIGN_FSHIFT 23
+#define G2D_CFG3_STRIDESIGN_FMASK 0x1
+#define G2D_COLOR_ARGB_FADDR ADDR_G2D_COLOR
+#define G2D_COLOR_ARGB_FSHIFT 0
+#define G2D_COLOR_ARGB_FMASK 0xffffffff
+#define G2D_CONFIG_DST_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_DST_FSHIFT 0
+#define G2D_CONFIG_DST_FMASK 0x1
+#define G2D_CONFIG_SRC1_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRC1_FSHIFT 1
+#define G2D_CONFIG_SRC1_FMASK 0x1
+#define G2D_CONFIG_SRC2_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRC2_FSHIFT 2
+#define G2D_CONFIG_SRC2_FMASK 0x1
+#define G2D_CONFIG_SRC3_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRC3_FSHIFT 3
+#define G2D_CONFIG_SRC3_FMASK 0x1
+#define G2D_CONFIG_SRCCK_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_SRCCK_FSHIFT 4
+#define G2D_CONFIG_SRCCK_FMASK 0x1
+#define G2D_CONFIG_DSTCK_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_DSTCK_FSHIFT 5
+#define G2D_CONFIG_DSTCK_FMASK 0x1
+#define G2D_CONFIG_ROTATE_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_ROTATE_FSHIFT 6
+#define G2D_CONFIG_ROTATE_FMASK 0x3
+#define G2D_CONFIG_OBS_GAMMA_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_OBS_GAMMA_FSHIFT 8
+#define G2D_CONFIG_OBS_GAMMA_FMASK 0x1
+#define G2D_CONFIG_IGNORECKALPHA_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_IGNORECKALPHA_FSHIFT 9
+#define G2D_CONFIG_IGNORECKALPHA_FMASK 0x1
+#define G2D_CONFIG_DITHER_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_DITHER_FSHIFT 10
+#define G2D_CONFIG_DITHER_FMASK 0x1
+#define G2D_CONFIG_WRITESRGB_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_WRITESRGB_FSHIFT 11
+#define G2D_CONFIG_WRITESRGB_FMASK 0x1
+#define G2D_CONFIG_ARGBMASK_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_ARGBMASK_FSHIFT 12
+#define G2D_CONFIG_ARGBMASK_FMASK 0xf
+#define G2D_CONFIG_ALPHATEX_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_ALPHATEX_FSHIFT 16
+#define G2D_CONFIG_ALPHATEX_FMASK 0x1
+#define G2D_CONFIG_PALMLINES_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_PALMLINES_FSHIFT 17
+#define G2D_CONFIG_PALMLINES_FMASK 0x1
+#define G2D_CONFIG_NOLASTPIXEL_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_NOLASTPIXEL_FSHIFT 18
+#define G2D_CONFIG_NOLASTPIXEL_FMASK 0x1
+#define G2D_CONFIG_NOPROTECT_FADDR ADDR_G2D_CONFIG
+#define G2D_CONFIG_NOPROTECT_FSHIFT 19
+#define G2D_CONFIG_NOPROTECT_FMASK 0x1
+#define G2D_CONST0_ARGB_FADDR ADDR_G2D_CONST0
+#define G2D_CONST0_ARGB_FSHIFT 0
+#define G2D_CONST0_ARGB_FMASK 0xffffffff
+#define G2D_CONST1_ARGB_FADDR ADDR_G2D_CONST1
+#define G2D_CONST1_ARGB_FSHIFT 0
+#define G2D_CONST1_ARGB_FMASK 0xffffffff
+#define G2D_CONST2_ARGB_FADDR ADDR_G2D_CONST2
+#define G2D_CONST2_ARGB_FSHIFT 0
+#define G2D_CONST2_ARGB_FMASK 0xffffffff
+#define G2D_CONST3_ARGB_FADDR ADDR_G2D_CONST3
+#define G2D_CONST3_ARGB_FSHIFT 0
+#define G2D_CONST3_ARGB_FMASK 0xffffffff
+#define G2D_CONST4_ARGB_FADDR ADDR_G2D_CONST4
+#define G2D_CONST4_ARGB_FSHIFT 0
+#define G2D_CONST4_ARGB_FMASK 0xffffffff
+#define G2D_CONST5_ARGB_FADDR ADDR_G2D_CONST5
+#define G2D_CONST5_ARGB_FSHIFT 0
+#define G2D_CONST5_ARGB_FMASK 0xffffffff
+#define G2D_CONST6_ARGB_FADDR ADDR_G2D_CONST6
+#define G2D_CONST6_ARGB_FSHIFT 0
+#define G2D_CONST6_ARGB_FMASK 0xffffffff
+#define G2D_CONST7_ARGB_FADDR ADDR_G2D_CONST7
+#define G2D_CONST7_ARGB_FSHIFT 0
+#define G2D_CONST7_ARGB_FMASK 0xffffffff
+#define G2D_FOREGROUND_COLOR_FADDR ADDR_G2D_FOREGROUND
+#define G2D_FOREGROUND_COLOR_FSHIFT 0
+#define G2D_FOREGROUND_COLOR_FMASK 0xffffffff
+#define G2D_GRADIENT_INSTRUCTIONS_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_INSTRUCTIONS_FSHIFT 0
+#define G2D_GRADIENT_INSTRUCTIONS_FMASK 0x7
+#define G2D_GRADIENT_INSTRUCTIONS2_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_INSTRUCTIONS2_FSHIFT 3
+#define G2D_GRADIENT_INSTRUCTIONS2_FMASK 0x7
+#define G2D_GRADIENT_ENABLE_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_ENABLE_FSHIFT 6
+#define G2D_GRADIENT_ENABLE_FMASK 0x1
+#define G2D_GRADIENT_ENABLE2_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_ENABLE2_FSHIFT 7
+#define G2D_GRADIENT_ENABLE2_FMASK 0x1
+#define G2D_GRADIENT_SEL_FADDR ADDR_G2D_GRADIENT
+#define G2D_GRADIENT_SEL_FSHIFT 8
+#define G2D_GRADIENT_SEL_FMASK 0x1
+#define G2D_IDLE_IRQ_FADDR ADDR_G2D_IDLE
+#define G2D_IDLE_IRQ_FSHIFT 0
+#define G2D_IDLE_IRQ_FMASK 0x1
+#define G2D_IDLE_BCFLUSH_FADDR ADDR_G2D_IDLE
+#define G2D_IDLE_BCFLUSH_FSHIFT 1
+#define G2D_IDLE_BCFLUSH_FMASK 0x1
+#define G2D_IDLE_V3_FADDR ADDR_G2D_IDLE
+#define G2D_IDLE_V3_FSHIFT 2
+#define G2D_IDLE_V3_FMASK 0x1
+#define G2D_INPUT_COLOR_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_COLOR_FSHIFT 0
+#define G2D_INPUT_COLOR_FMASK 0x1
+#define G2D_INPUT_SCOORD1_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_SCOORD1_FSHIFT 1
+#define G2D_INPUT_SCOORD1_FMASK 0x1
+#define G2D_INPUT_SCOORD2_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_SCOORD2_FSHIFT 2
+#define G2D_INPUT_SCOORD2_FMASK 0x1
+#define G2D_INPUT_COPYCOORD_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_COPYCOORD_FSHIFT 3
+#define G2D_INPUT_COPYCOORD_FMASK 0x1
+#define G2D_INPUT_VGMODE_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_VGMODE_FSHIFT 4
+#define G2D_INPUT_VGMODE_FMASK 0x1
+#define G2D_INPUT_LINEMODE_FADDR ADDR_G2D_INPUT
+#define G2D_INPUT_LINEMODE_FSHIFT 5
+#define G2D_INPUT_LINEMODE_FMASK 0x1
+#define G2D_MASK_YMASK_FADDR ADDR_G2D_MASK
+#define G2D_MASK_YMASK_FSHIFT 0
+#define G2D_MASK_YMASK_FMASK 0xfff
+#define G2D_MASK_XMASK_FADDR ADDR_G2D_MASK
+#define G2D_MASK_XMASK_FSHIFT 12
+#define G2D_MASK_XMASK_FMASK 0xfff
+#define G2D_ROP_ROP_FADDR ADDR_G2D_ROP
+#define G2D_ROP_ROP_FSHIFT 0
+#define G2D_ROP_ROP_FMASK 0xffff
+#define G2D_SCISSORX_LEFT_FADDR ADDR_G2D_SCISSORX
+#define G2D_SCISSORX_LEFT_FSHIFT 0
+#define G2D_SCISSORX_LEFT_FMASK 0x7ff
+#define G2D_SCISSORX_RIGHT_FADDR ADDR_G2D_SCISSORX
+#define G2D_SCISSORX_RIGHT_FSHIFT 11
+#define G2D_SCISSORX_RIGHT_FMASK 0x7ff
+#define G2D_SCISSORY_TOP_FADDR ADDR_G2D_SCISSORY
+#define G2D_SCISSORY_TOP_FSHIFT 0
+#define G2D_SCISSORY_TOP_FMASK 0x7ff
+#define G2D_SCISSORY_BOTTOM_FADDR ADDR_G2D_SCISSORY
+#define G2D_SCISSORY_BOTTOM_FSHIFT 11
+#define G2D_SCISSORY_BOTTOM_FMASK 0x7ff
+#define G2D_SXY_Y_FADDR ADDR_G2D_SXY
+#define G2D_SXY_Y_FSHIFT 0
+#define G2D_SXY_Y_FMASK 0x7ff
+#define G2D_SXY_PAD_FADDR ADDR_G2D_SXY
+#define G2D_SXY_PAD_FSHIFT 11
+#define G2D_SXY_PAD_FMASK 0x1f
+#define G2D_SXY_X_FADDR ADDR_G2D_SXY
+#define G2D_SXY_X_FSHIFT 16
+#define G2D_SXY_X_FMASK 0x7ff
+#define G2D_SXY2_Y_FADDR ADDR_G2D_SXY2
+#define G2D_SXY2_Y_FSHIFT 0
+#define G2D_SXY2_Y_FMASK 0x7ff
+#define G2D_SXY2_PAD_FADDR ADDR_G2D_SXY2
+#define G2D_SXY2_PAD_FSHIFT 11
+#define G2D_SXY2_PAD_FMASK 0x1f
+#define G2D_SXY2_X_FADDR ADDR_G2D_SXY2
+#define G2D_SXY2_X_FSHIFT 16
+#define G2D_SXY2_X_FMASK 0x7ff
+#define G2D_VGSPAN_WIDTH_FADDR ADDR_G2D_VGSPAN
+#define G2D_VGSPAN_WIDTH_FSHIFT 0
+#define G2D_VGSPAN_WIDTH_FMASK 0xfff
+#define G2D_VGSPAN_PAD_FADDR ADDR_G2D_VGSPAN
+#define G2D_VGSPAN_PAD_FSHIFT 12
+#define G2D_VGSPAN_PAD_FMASK 0xf
+#define G2D_VGSPAN_COVERAGE_FADDR ADDR_G2D_VGSPAN
+#define G2D_VGSPAN_COVERAGE_FSHIFT 16
+#define G2D_VGSPAN_COVERAGE_FMASK 0xf
+#define G2D_WIDTHHEIGHT_HEIGHT_FADDR ADDR_G2D_WIDTHHEIGHT
+#define G2D_WIDTHHEIGHT_HEIGHT_FSHIFT 0
+#define G2D_WIDTHHEIGHT_HEIGHT_FMASK 0xfff
+#define G2D_WIDTHHEIGHT_PAD_FADDR ADDR_G2D_WIDTHHEIGHT
+#define G2D_WIDTHHEIGHT_PAD_FSHIFT 12
+#define G2D_WIDTHHEIGHT_PAD_FMASK 0xf
+#define G2D_WIDTHHEIGHT_WIDTH_FADDR ADDR_G2D_WIDTHHEIGHT
+#define G2D_WIDTHHEIGHT_WIDTH_FSHIFT 16
+#define G2D_WIDTHHEIGHT_WIDTH_FMASK 0xfff
+#define G2D_XY_Y_FADDR ADDR_G2D_XY
+#define G2D_XY_Y_FSHIFT 0
+#define G2D_XY_Y_FMASK 0xfff
+#define G2D_XY_PAD_FADDR ADDR_G2D_XY
+#define G2D_XY_PAD_FSHIFT 12
+#define G2D_XY_PAD_FMASK 0xf
+#define G2D_XY_X_FADDR ADDR_G2D_XY
+#define G2D_XY_X_FSHIFT 16
+#define G2D_XY_X_FMASK 0xfff
+#define GRADW_BORDERCOLOR_COLOR_FADDR ADDR_GRADW_BORDERCOLOR
+#define GRADW_BORDERCOLOR_COLOR_FSHIFT 0
+#define GRADW_BORDERCOLOR_COLOR_FMASK 0xffffffff
+#define GRADW_CONST0_VALUE_FADDR ADDR_GRADW_CONST0
+#define GRADW_CONST0_VALUE_FSHIFT 0
+#define GRADW_CONST0_VALUE_FMASK 0xffff
+#define GRADW_CONST1_VALUE_FADDR ADDR_GRADW_CONST1
+#define GRADW_CONST1_VALUE_FSHIFT 0
+#define GRADW_CONST1_VALUE_FMASK 0xffff
+#define GRADW_CONST2_VALUE_FADDR ADDR_GRADW_CONST2
+#define GRADW_CONST2_VALUE_FSHIFT 0
+#define GRADW_CONST2_VALUE_FMASK 0xffff
+#define GRADW_CONST3_VALUE_FADDR ADDR_GRADW_CONST3
+#define GRADW_CONST3_VALUE_FSHIFT 0
+#define GRADW_CONST3_VALUE_FMASK 0xffff
+#define GRADW_CONST4_VALUE_FADDR ADDR_GRADW_CONST4
+#define GRADW_CONST4_VALUE_FSHIFT 0
+#define GRADW_CONST4_VALUE_FMASK 0xffff
+#define GRADW_CONST5_VALUE_FADDR ADDR_GRADW_CONST5
+#define GRADW_CONST5_VALUE_FSHIFT 0
+#define GRADW_CONST5_VALUE_FMASK 0xffff
+#define GRADW_CONST6_VALUE_FADDR ADDR_GRADW_CONST6
+#define GRADW_CONST6_VALUE_FSHIFT 0
+#define GRADW_CONST6_VALUE_FMASK 0xffff
+#define GRADW_CONST7_VALUE_FADDR ADDR_GRADW_CONST7
+#define GRADW_CONST7_VALUE_FSHIFT 0
+#define GRADW_CONST7_VALUE_FMASK 0xffff
+#define GRADW_CONST8_VALUE_FADDR ADDR_GRADW_CONST8
+#define GRADW_CONST8_VALUE_FSHIFT 0
+#define GRADW_CONST8_VALUE_FMASK 0xffff
+#define GRADW_CONST9_VALUE_FADDR ADDR_GRADW_CONST9
+#define GRADW_CONST9_VALUE_FSHIFT 0
+#define GRADW_CONST9_VALUE_FMASK 0xffff
+#define GRADW_CONSTA_VALUE_FADDR ADDR_GRADW_CONSTA
+#define GRADW_CONSTA_VALUE_FSHIFT 0
+#define GRADW_CONSTA_VALUE_FMASK 0xffff
+#define GRADW_CONSTB_VALUE_FADDR ADDR_GRADW_CONSTB
+#define GRADW_CONSTB_VALUE_FSHIFT 0
+#define GRADW_CONSTB_VALUE_FMASK 0xffff
+#define GRADW_INST0_SRC_E_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_E_FSHIFT 0
+#define GRADW_INST0_SRC_E_FMASK 0x1f
+#define GRADW_INST0_SRC_D_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_D_FSHIFT 5
+#define GRADW_INST0_SRC_D_FMASK 0x1f
+#define GRADW_INST0_SRC_C_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_C_FSHIFT 10
+#define GRADW_INST0_SRC_C_FMASK 0x1f
+#define GRADW_INST0_SRC_B_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_B_FSHIFT 15
+#define GRADW_INST0_SRC_B_FMASK 0x1f
+#define GRADW_INST0_SRC_A_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_SRC_A_FSHIFT 20
+#define GRADW_INST0_SRC_A_FMASK 0x1f
+#define GRADW_INST0_DST_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_DST_FSHIFT 25
+#define GRADW_INST0_DST_FMASK 0xf
+#define GRADW_INST0_OPCODE_FADDR ADDR_GRADW_INST0
+#define GRADW_INST0_OPCODE_FSHIFT 29
+#define GRADW_INST0_OPCODE_FMASK 0x3
+#define GRADW_INST1_SRC_E_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_E_FSHIFT 0
+#define GRADW_INST1_SRC_E_FMASK 0x1f
+#define GRADW_INST1_SRC_D_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_D_FSHIFT 5
+#define GRADW_INST1_SRC_D_FMASK 0x1f
+#define GRADW_INST1_SRC_C_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_C_FSHIFT 10
+#define GRADW_INST1_SRC_C_FMASK 0x1f
+#define GRADW_INST1_SRC_B_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_B_FSHIFT 15
+#define GRADW_INST1_SRC_B_FMASK 0x1f
+#define GRADW_INST1_SRC_A_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_SRC_A_FSHIFT 20
+#define GRADW_INST1_SRC_A_FMASK 0x1f
+#define GRADW_INST1_DST_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_DST_FSHIFT 25
+#define GRADW_INST1_DST_FMASK 0xf
+#define GRADW_INST1_OPCODE_FADDR ADDR_GRADW_INST1
+#define GRADW_INST1_OPCODE_FSHIFT 29
+#define GRADW_INST1_OPCODE_FMASK 0x3
+#define GRADW_INST2_SRC_E_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_E_FSHIFT 0
+#define GRADW_INST2_SRC_E_FMASK 0x1f
+#define GRADW_INST2_SRC_D_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_D_FSHIFT 5
+#define GRADW_INST2_SRC_D_FMASK 0x1f
+#define GRADW_INST2_SRC_C_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_C_FSHIFT 10
+#define GRADW_INST2_SRC_C_FMASK 0x1f
+#define GRADW_INST2_SRC_B_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_B_FSHIFT 15
+#define GRADW_INST2_SRC_B_FMASK 0x1f
+#define GRADW_INST2_SRC_A_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_SRC_A_FSHIFT 20
+#define GRADW_INST2_SRC_A_FMASK 0x1f
+#define GRADW_INST2_DST_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_DST_FSHIFT 25
+#define GRADW_INST2_DST_FMASK 0xf
+#define GRADW_INST2_OPCODE_FADDR ADDR_GRADW_INST2
+#define GRADW_INST2_OPCODE_FSHIFT 29
+#define GRADW_INST2_OPCODE_FMASK 0x3
+#define GRADW_INST3_SRC_E_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_E_FSHIFT 0
+#define GRADW_INST3_SRC_E_FMASK 0x1f
+#define GRADW_INST3_SRC_D_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_D_FSHIFT 5
+#define GRADW_INST3_SRC_D_FMASK 0x1f
+#define GRADW_INST3_SRC_C_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_C_FSHIFT 10
+#define GRADW_INST3_SRC_C_FMASK 0x1f
+#define GRADW_INST3_SRC_B_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_B_FSHIFT 15
+#define GRADW_INST3_SRC_B_FMASK 0x1f
+#define GRADW_INST3_SRC_A_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_SRC_A_FSHIFT 20
+#define GRADW_INST3_SRC_A_FMASK 0x1f
+#define GRADW_INST3_DST_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_DST_FSHIFT 25
+#define GRADW_INST3_DST_FMASK 0xf
+#define GRADW_INST3_OPCODE_FADDR ADDR_GRADW_INST3
+#define GRADW_INST3_OPCODE_FSHIFT 29
+#define GRADW_INST3_OPCODE_FMASK 0x3
+#define GRADW_INST4_SRC_E_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_E_FSHIFT 0
+#define GRADW_INST4_SRC_E_FMASK 0x1f
+#define GRADW_INST4_SRC_D_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_D_FSHIFT 5
+#define GRADW_INST4_SRC_D_FMASK 0x1f
+#define GRADW_INST4_SRC_C_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_C_FSHIFT 10
+#define GRADW_INST4_SRC_C_FMASK 0x1f
+#define GRADW_INST4_SRC_B_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_B_FSHIFT 15
+#define GRADW_INST4_SRC_B_FMASK 0x1f
+#define GRADW_INST4_SRC_A_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_SRC_A_FSHIFT 20
+#define GRADW_INST4_SRC_A_FMASK 0x1f
+#define GRADW_INST4_DST_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_DST_FSHIFT 25
+#define GRADW_INST4_DST_FMASK 0xf
+#define GRADW_INST4_OPCODE_FADDR ADDR_GRADW_INST4
+#define GRADW_INST4_OPCODE_FSHIFT 29
+#define GRADW_INST4_OPCODE_FMASK 0x3
+#define GRADW_INST5_SRC_E_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_E_FSHIFT 0
+#define GRADW_INST5_SRC_E_FMASK 0x1f
+#define GRADW_INST5_SRC_D_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_D_FSHIFT 5
+#define GRADW_INST5_SRC_D_FMASK 0x1f
+#define GRADW_INST5_SRC_C_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_C_FSHIFT 10
+#define GRADW_INST5_SRC_C_FMASK 0x1f
+#define GRADW_INST5_SRC_B_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_B_FSHIFT 15
+#define GRADW_INST5_SRC_B_FMASK 0x1f
+#define GRADW_INST5_SRC_A_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_SRC_A_FSHIFT 20
+#define GRADW_INST5_SRC_A_FMASK 0x1f
+#define GRADW_INST5_DST_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_DST_FSHIFT 25
+#define GRADW_INST5_DST_FMASK 0xf
+#define GRADW_INST5_OPCODE_FADDR ADDR_GRADW_INST5
+#define GRADW_INST5_OPCODE_FSHIFT 29
+#define GRADW_INST5_OPCODE_FMASK 0x3
+#define GRADW_INST6_SRC_E_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_E_FSHIFT 0
+#define GRADW_INST6_SRC_E_FMASK 0x1f
+#define GRADW_INST6_SRC_D_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_D_FSHIFT 5
+#define GRADW_INST6_SRC_D_FMASK 0x1f
+#define GRADW_INST6_SRC_C_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_C_FSHIFT 10
+#define GRADW_INST6_SRC_C_FMASK 0x1f
+#define GRADW_INST6_SRC_B_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_B_FSHIFT 15
+#define GRADW_INST6_SRC_B_FMASK 0x1f
+#define GRADW_INST6_SRC_A_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_SRC_A_FSHIFT 20
+#define GRADW_INST6_SRC_A_FMASK 0x1f
+#define GRADW_INST6_DST_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_DST_FSHIFT 25
+#define GRADW_INST6_DST_FMASK 0xf
+#define GRADW_INST6_OPCODE_FADDR ADDR_GRADW_INST6
+#define GRADW_INST6_OPCODE_FSHIFT 29
+#define GRADW_INST6_OPCODE_FMASK 0x3
+#define GRADW_INST7_SRC_E_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_E_FSHIFT 0
+#define GRADW_INST7_SRC_E_FMASK 0x1f
+#define GRADW_INST7_SRC_D_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_D_FSHIFT 5
+#define GRADW_INST7_SRC_D_FMASK 0x1f
+#define GRADW_INST7_SRC_C_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_C_FSHIFT 10
+#define GRADW_INST7_SRC_C_FMASK 0x1f
+#define GRADW_INST7_SRC_B_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_B_FSHIFT 15
+#define GRADW_INST7_SRC_B_FMASK 0x1f
+#define GRADW_INST7_SRC_A_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_SRC_A_FSHIFT 20
+#define GRADW_INST7_SRC_A_FMASK 0x1f
+#define GRADW_INST7_DST_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_DST_FSHIFT 25
+#define GRADW_INST7_DST_FMASK 0xf
+#define GRADW_INST7_OPCODE_FADDR ADDR_GRADW_INST7
+#define GRADW_INST7_OPCODE_FSHIFT 29
+#define GRADW_INST7_OPCODE_FMASK 0x3
+#define GRADW_TEXBASE_ADDR_FADDR ADDR_GRADW_TEXBASE
+#define GRADW_TEXBASE_ADDR_FSHIFT 0
+#define GRADW_TEXBASE_ADDR_FMASK 0xffffffff
+#define GRADW_TEXCFG_STRIDE_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_STRIDE_FSHIFT 0
+#define GRADW_TEXCFG_STRIDE_FMASK 0xfff
+#define GRADW_TEXCFG_FORMAT_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_FORMAT_FSHIFT 12
+#define GRADW_TEXCFG_FORMAT_FMASK 0xf
+#define GRADW_TEXCFG_TILED_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_TILED_FSHIFT 16
+#define GRADW_TEXCFG_TILED_FMASK 0x1
+#define GRADW_TEXCFG_WRAPU_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_WRAPU_FSHIFT 17
+#define GRADW_TEXCFG_WRAPU_FMASK 0x3
+#define GRADW_TEXCFG_WRAPV_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_WRAPV_FSHIFT 19
+#define GRADW_TEXCFG_WRAPV_FMASK 0x3
+#define GRADW_TEXCFG_BILIN_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_BILIN_FSHIFT 21
+#define GRADW_TEXCFG_BILIN_FMASK 0x1
+#define GRADW_TEXCFG_SRGB_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SRGB_FSHIFT 22
+#define GRADW_TEXCFG_SRGB_FMASK 0x1
+#define GRADW_TEXCFG_PREMULTIPLY_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_PREMULTIPLY_FSHIFT 23
+#define GRADW_TEXCFG_PREMULTIPLY_FMASK 0x1
+#define GRADW_TEXCFG_SWAPWORDS_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPWORDS_FSHIFT 24
+#define GRADW_TEXCFG_SWAPWORDS_FMASK 0x1
+#define GRADW_TEXCFG_SWAPBYTES_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPBYTES_FSHIFT 25
+#define GRADW_TEXCFG_SWAPBYTES_FMASK 0x1
+#define GRADW_TEXCFG_SWAPALL_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPALL_FSHIFT 26
+#define GRADW_TEXCFG_SWAPALL_FMASK 0x1
+#define GRADW_TEXCFG_SWAPRB_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPRB_FSHIFT 27
+#define GRADW_TEXCFG_SWAPRB_FMASK 0x1
+#define GRADW_TEXCFG_TEX2D_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_TEX2D_FSHIFT 28
+#define GRADW_TEXCFG_TEX2D_FMASK 0x1
+#define GRADW_TEXCFG_SWAPBITS_FADDR ADDR_GRADW_TEXCFG
+#define GRADW_TEXCFG_SWAPBITS_FSHIFT 29
+#define GRADW_TEXCFG_SWAPBITS_FMASK 0x1
+#define GRADW_TEXSIZE_WIDTH_FADDR ADDR_GRADW_TEXSIZE
+#define GRADW_TEXSIZE_WIDTH_FSHIFT 0
+#define GRADW_TEXSIZE_WIDTH_FMASK 0x7ff
+#define GRADW_TEXSIZE_HEIGHT_FADDR ADDR_GRADW_TEXSIZE
+#define GRADW_TEXSIZE_HEIGHT_FSHIFT 11
+#define GRADW_TEXSIZE_HEIGHT_FMASK 0x7ff
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FSHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FMASK 0x3f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FSHIFT 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FMASK 0x1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FSHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FSHIFT 8
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FSHIFT 9
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FMASK 0x1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_PAGE_SIZE_FSHIFT 10
+#define MH_ARBITER_CONFIG_PAGE_SIZE_FMASK 0x7
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FSHIFT 13
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FSHIFT 14
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FSHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FSHIFT 16
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FMASK 0x3f
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FSHIFT 22
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FSHIFT 23
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FSHIFT 24
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FSHIFT 25
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FMASK 0x1
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FSHIFT 26
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FMASK 0x1
+#define MH_AXI_ERROR_AXI_READ_ID_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_READ_ID_FSHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ID_FMASK 0x7
+#define MH_AXI_ERROR_AXI_READ_ERROR_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_READ_ERROR_FSHIFT 3
+#define MH_AXI_ERROR_AXI_READ_ERROR_FMASK 0x1
+#define MH_AXI_ERROR_AXI_WRITE_ID_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_WRITE_ID_FSHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ID_FMASK 0x7
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_FADDR ADDR_MH_AXI_ERROR
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_FSHIFT 7
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_AXI_HALT_CONTROL_AXI_HALT_FADDR ADDR_MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL_AXI_HALT_FSHIFT 0
+#define MH_AXI_HALT_CONTROL_AXI_HALT_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FSHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FMASK 0x7
+#define MH_CLNT_AXI_ID_REUSE_PAD_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAD_FSHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_PAD_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FSHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FMASK 0x7
+#define MH_CLNT_AXI_ID_REUSE_PAD2_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAD2_FSHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_PAD2_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FSHIFT 8
+#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FMASK 0x7
+#define MH_CLNT_AXI_ID_REUSE_PAD3_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAD3_FSHIFT 11
+#define MH_CLNT_AXI_ID_REUSE_PAD3_FMASK 0x1
+#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FSHIFT 12
+#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FMASK 0x7
+#define MH_DEBUG_CTRL_INDEX_FADDR ADDR_MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL_INDEX_FSHIFT 0
+#define MH_DEBUG_CTRL_INDEX_FMASK 0x3f
+#define MH_DEBUG_DATA_DATA_FADDR ADDR_MH_DEBUG_DATA
+#define MH_DEBUG_DATA_DATA_FSHIFT 0
+#define MH_DEBUG_DATA_DATA_FMASK 0xffffffff
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FSHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FMASK 0x1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FSHIFT 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FSHIFT 2
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FMASK 0x1
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT 0
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FMASK 0x1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT 2
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FMASK 0x1
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FSHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FMASK 0x1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FSHIFT 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FMASK 0x1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FSHIFT 2
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FMASK 0x1
+#define MH_MMU_CONFIG_MMU_ENABLE_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_MMU_ENABLE_FSHIFT 0
+#define MH_MMU_CONFIG_MMU_ENABLE_FMASK 0x1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FSHIFT 1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FMASK 0x1
+#define MH_MMU_CONFIG_PAD_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_PAD_FSHIFT 2
+#define MH_MMU_CONFIG_PAD_FMASK 0x3
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FSHIFT 4
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FSHIFT 6
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FSHIFT 8
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FSHIFT 10
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FSHIFT 12
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FSHIFT 14
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FSHIFT 16
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FSHIFT 18
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FSHIFT 20
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FSHIFT 22
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FSHIFT 24
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FADDR ADDR_MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FSHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FMASK 0x1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_FADDR ADDR_MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_FSHIFT 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_FMASK 0x1
+#define MH_MMU_MPU_BASE_ZERO_FADDR ADDR_MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE_ZERO_FSHIFT 0
+#define MH_MMU_MPU_BASE_ZERO_FMASK 0xfff
+#define MH_MMU_MPU_BASE_MPU_BASE_FADDR ADDR_MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE_MPU_BASE_FSHIFT 12
+#define MH_MMU_MPU_BASE_MPU_BASE_FMASK 0xfffff
+#define MH_MMU_MPU_END_ZERO_FADDR ADDR_MH_MMU_MPU_END
+#define MH_MMU_MPU_END_ZERO_FSHIFT 0
+#define MH_MMU_MPU_END_ZERO_FMASK 0xfff
+#define MH_MMU_MPU_END_MPU_END_FADDR ADDR_MH_MMU_MPU_END
+#define MH_MMU_MPU_END_MPU_END_FSHIFT 12
+#define MH_MMU_MPU_END_MPU_END_FMASK 0xfffff
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FSHIFT 0
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_OP_TYPE_FSHIFT 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FSHIFT 2
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FMASK 0x3
+#define MH_MMU_PAGE_FAULT_AXI_ID_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_AXI_ID_FSHIFT 4
+#define MH_MMU_PAGE_FAULT_AXI_ID_FMASK 0x7
+#define MH_MMU_PAGE_FAULT_PAD_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_PAD_FSHIFT 7
+#define MH_MMU_PAGE_FAULT_PAD_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FSHIFT 8
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FSHIFT 9
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FSHIFT 10
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FSHIFT 11
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FMASK 0x1
+#define MH_MMU_PAGE_FAULT_REQ_VA_FADDR ADDR_MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT_REQ_VA_FSHIFT 12
+#define MH_MMU_PAGE_FAULT_REQ_VA_FMASK 0xfffff
+#define MH_MMU_PT_BASE_ZERO_FADDR ADDR_MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE_ZERO_FSHIFT 0
+#define MH_MMU_PT_BASE_ZERO_FMASK 0xfff
+#define MH_MMU_PT_BASE_PT_BASE_FADDR ADDR_MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE_PT_BASE_FSHIFT 12
+#define MH_MMU_PT_BASE_PT_BASE_FMASK 0xfffff
+#define MH_MMU_TRAN_ERROR_ZERO_FADDR ADDR_MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR_ZERO_FSHIFT 0
+#define MH_MMU_TRAN_ERROR_ZERO_FMASK 0x1f
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FADDR ADDR_MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FSHIFT 5
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FMASK 0x7ffffff
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FADDR ADDR_MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FSHIFT 0
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FMASK 0xfff
+#define MH_MMU_VA_RANGE_VA_BASE_FADDR ADDR_MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE_VA_BASE_FSHIFT 12
+#define MH_MMU_VA_RANGE_VA_BASE_FMASK 0xfffff
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FSHIFT 0
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FMASK 0xff
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FSHIFT 0
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FMASK 0xffff
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FSHIFT 0
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FSHIFT 0
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FMASK 0xff
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FSHIFT 0
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FMASK 0xff
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FSHIFT 0
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FMASK 0xffff
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FSHIFT 0
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FSHIFT 0
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FMASK 0xff
+#define MMU_READ_ADDR_ADDR_FADDR ADDR_MMU_READ_ADDR
+#define MMU_READ_ADDR_ADDR_FSHIFT 0
+#define MMU_READ_ADDR_ADDR_FMASK 0x7fff
+#define MMU_READ_DATA_DATA_FADDR ADDR_MMU_READ_DATA
+#define MMU_READ_DATA_DATA_FSHIFT 0
+#define MMU_READ_DATA_DATA_FMASK 0xffffffff
+#define VGV1_CBASE1_ADDR_FADDR ADDR_VGV1_CBASE1
+#define VGV1_CBASE1_ADDR_FSHIFT 0
+#define VGV1_CBASE1_ADDR_FMASK 0xffffffff
+#define VGV1_CFG1_WINDRULE_FADDR ADDR_VGV1_CFG1
+#define VGV1_CFG1_WINDRULE_FSHIFT 0
+#define VGV1_CFG1_WINDRULE_FMASK 0x1
+#define VGV1_CFG2_AAMODE_FADDR ADDR_VGV1_CFG2
+#define VGV1_CFG2_AAMODE_FSHIFT 0
+#define VGV1_CFG2_AAMODE_FMASK 0x3
+#define VGV1_DIRTYBASE_ADDR_FADDR ADDR_VGV1_DIRTYBASE
+#define VGV1_DIRTYBASE_ADDR_FSHIFT 0
+#define VGV1_DIRTYBASE_ADDR_FMASK 0xffffffff
+#define VGV1_FILL_INHERIT_FADDR ADDR_VGV1_FILL
+#define VGV1_FILL_INHERIT_FSHIFT 0
+#define VGV1_FILL_INHERIT_FMASK 0x1
+#define VGV1_SCISSORX_LEFT_FADDR ADDR_VGV1_SCISSORX
+#define VGV1_SCISSORX_LEFT_FSHIFT 0
+#define VGV1_SCISSORX_LEFT_FMASK 0x7ff
+#define VGV1_SCISSORX_PAD_FADDR ADDR_VGV1_SCISSORX
+#define VGV1_SCISSORX_PAD_FSHIFT 11
+#define VGV1_SCISSORX_PAD_FMASK 0x1f
+#define VGV1_SCISSORX_RIGHT_FADDR ADDR_VGV1_SCISSORX
+#define VGV1_SCISSORX_RIGHT_FSHIFT 16
+#define VGV1_SCISSORX_RIGHT_FMASK 0x7ff
+#define VGV1_SCISSORY_TOP_FADDR ADDR_VGV1_SCISSORY
+#define VGV1_SCISSORY_TOP_FSHIFT 0
+#define VGV1_SCISSORY_TOP_FMASK 0x7ff
+#define VGV1_SCISSORY_PAD_FADDR ADDR_VGV1_SCISSORY
+#define VGV1_SCISSORY_PAD_FSHIFT 11
+#define VGV1_SCISSORY_PAD_FMASK 0x1f
+#define VGV1_SCISSORY_BOTTOM_FADDR ADDR_VGV1_SCISSORY
+#define VGV1_SCISSORY_BOTTOM_FSHIFT 16
+#define VGV1_SCISSORY_BOTTOM_FMASK 0x7ff
+#define VGV1_TILEOFS_X_FADDR ADDR_VGV1_TILEOFS
+#define VGV1_TILEOFS_X_FSHIFT 0
+#define VGV1_TILEOFS_X_FMASK 0xfff
+#define VGV1_TILEOFS_Y_FADDR ADDR_VGV1_TILEOFS
+#define VGV1_TILEOFS_Y_FSHIFT 12
+#define VGV1_TILEOFS_Y_FMASK 0xfff
+#define VGV1_TILEOFS_LEFTMOST_FADDR ADDR_VGV1_TILEOFS
+#define VGV1_TILEOFS_LEFTMOST_FSHIFT 24
+#define VGV1_TILEOFS_LEFTMOST_FMASK 0x1
+#define VGV1_UBASE2_ADDR_FADDR ADDR_VGV1_UBASE2
+#define VGV1_UBASE2_ADDR_FSHIFT 0
+#define VGV1_UBASE2_ADDR_FMASK 0xffffffff
+#define VGV1_VTX0_X_FADDR ADDR_VGV1_VTX0
+#define VGV1_VTX0_X_FSHIFT 0
+#define VGV1_VTX0_X_FMASK 0xffff
+#define VGV1_VTX0_Y_FADDR ADDR_VGV1_VTX0
+#define VGV1_VTX0_Y_FSHIFT 16
+#define VGV1_VTX0_Y_FMASK 0xffff
+#define VGV1_VTX1_X_FADDR ADDR_VGV1_VTX1
+#define VGV1_VTX1_X_FSHIFT 0
+#define VGV1_VTX1_X_FMASK 0xffff
+#define VGV1_VTX1_Y_FADDR ADDR_VGV1_VTX1
+#define VGV1_VTX1_Y_FSHIFT 16
+#define VGV1_VTX1_Y_FMASK 0xffff
+#define VGV2_ACCURACY_F_FADDR ADDR_VGV2_ACCURACY
+#define VGV2_ACCURACY_F_FSHIFT 0
+#define VGV2_ACCURACY_F_FMASK 0xffffff
+#define VGV2_ACTION_ACTION_FADDR ADDR_VGV2_ACTION
+#define VGV2_ACTION_ACTION_FSHIFT 0
+#define VGV2_ACTION_ACTION_FMASK 0xf
+#define VGV2_ARCCOS_F_FADDR ADDR_VGV2_ARCCOS
+#define VGV2_ARCCOS_F_FSHIFT 0
+#define VGV2_ARCCOS_F_FMASK 0xffffff
+#define VGV2_ARCSIN_F_FADDR ADDR_VGV2_ARCSIN
+#define VGV2_ARCSIN_F_FSHIFT 0
+#define VGV2_ARCSIN_F_FMASK 0xffffff
+#define VGV2_ARCTAN_F_FADDR ADDR_VGV2_ARCTAN
+#define VGV2_ARCTAN_F_FSHIFT 0
+#define VGV2_ARCTAN_F_FMASK 0xffffff
+#define VGV2_BBOXMAXX_F_FADDR ADDR_VGV2_BBOXMAXX
+#define VGV2_BBOXMAXX_F_FSHIFT 0
+#define VGV2_BBOXMAXX_F_FMASK 0xffffff
+#define VGV2_BBOXMAXY_F_FADDR ADDR_VGV2_BBOXMAXY
+#define VGV2_BBOXMAXY_F_FSHIFT 0
+#define VGV2_BBOXMAXY_F_FMASK 0xffffff
+#define VGV2_BBOXMINX_F_FADDR ADDR_VGV2_BBOXMINX
+#define VGV2_BBOXMINX_F_FSHIFT 0
+#define VGV2_BBOXMINX_F_FMASK 0xffffff
+#define VGV2_BBOXMINY_F_FADDR ADDR_VGV2_BBOXMINY
+#define VGV2_BBOXMINY_F_FSHIFT 0
+#define VGV2_BBOXMINY_F_FMASK 0xffffff
+#define VGV2_BIAS_F_FADDR ADDR_VGV2_BIAS
+#define VGV2_BIAS_F_FSHIFT 0
+#define VGV2_BIAS_F_FMASK 0xffffff
+#define VGV2_C1X_F_FADDR ADDR_VGV2_C1X
+#define VGV2_C1X_F_FSHIFT 0
+#define VGV2_C1X_F_FMASK 0xffffff
+#define VGV2_C1XREL_F_FADDR ADDR_VGV2_C1XREL
+#define VGV2_C1XREL_F_FSHIFT 0
+#define VGV2_C1XREL_F_FMASK 0xffffff
+#define VGV2_C1Y_F_FADDR ADDR_VGV2_C1Y
+#define VGV2_C1Y_F_FSHIFT 0
+#define VGV2_C1Y_F_FMASK 0xffffff
+#define VGV2_C1YREL_F_FADDR ADDR_VGV2_C1YREL
+#define VGV2_C1YREL_F_FSHIFT 0
+#define VGV2_C1YREL_F_FMASK 0xffffff
+#define VGV2_C2X_F_FADDR ADDR_VGV2_C2X
+#define VGV2_C2X_F_FSHIFT 0
+#define VGV2_C2X_F_FMASK 0xffffff
+#define VGV2_C2XREL_F_FADDR ADDR_VGV2_C2XREL
+#define VGV2_C2XREL_F_FSHIFT 0
+#define VGV2_C2XREL_F_FMASK 0xffffff
+#define VGV2_C2Y_F_FADDR ADDR_VGV2_C2Y
+#define VGV2_C2Y_F_FSHIFT 0
+#define VGV2_C2Y_F_FMASK 0xffffff
+#define VGV2_C2YREL_F_FADDR ADDR_VGV2_C2YREL
+#define VGV2_C2YREL_F_FSHIFT 0
+#define VGV2_C2YREL_F_FMASK 0xffffff
+#define VGV2_C3X_F_FADDR ADDR_VGV2_C3X
+#define VGV2_C3X_F_FSHIFT 0
+#define VGV2_C3X_F_FMASK 0xffffff
+#define VGV2_C3XREL_F_FADDR ADDR_VGV2_C3XREL
+#define VGV2_C3XREL_F_FSHIFT 0
+#define VGV2_C3XREL_F_FMASK 0xffffff
+#define VGV2_C3Y_F_FADDR ADDR_VGV2_C3Y
+#define VGV2_C3Y_F_FSHIFT 0
+#define VGV2_C3Y_F_FMASK 0xffffff
+#define VGV2_C3YREL_F_FADDR ADDR_VGV2_C3YREL
+#define VGV2_C3YREL_F_FSHIFT 0
+#define VGV2_C3YREL_F_FMASK 0xffffff
+#define VGV2_C4X_F_FADDR ADDR_VGV2_C4X
+#define VGV2_C4X_F_FSHIFT 0
+#define VGV2_C4X_F_FMASK 0xffffff
+#define VGV2_C4XREL_F_FADDR ADDR_VGV2_C4XREL
+#define VGV2_C4XREL_F_FSHIFT 0
+#define VGV2_C4XREL_F_FMASK 0xffffff
+#define VGV2_C4Y_F_FADDR ADDR_VGV2_C4Y
+#define VGV2_C4Y_F_FSHIFT 0
+#define VGV2_C4Y_F_FMASK 0xffffff
+#define VGV2_C4YREL_F_FADDR ADDR_VGV2_C4YREL
+#define VGV2_C4YREL_F_FSHIFT 0
+#define VGV2_C4YREL_F_FMASK 0xffffff
+#define VGV2_CLIP_F_FADDR ADDR_VGV2_CLIP
+#define VGV2_CLIP_F_FSHIFT 0
+#define VGV2_CLIP_F_FMASK 0xffffff
+#define VGV2_FIRST_DUMMY_FADDR ADDR_VGV2_FIRST
+#define VGV2_FIRST_DUMMY_FSHIFT 0
+#define VGV2_FIRST_DUMMY_FMASK 0x1
+#define VGV2_LAST_DUMMY_FADDR ADDR_VGV2_LAST
+#define VGV2_LAST_DUMMY_FSHIFT 0
+#define VGV2_LAST_DUMMY_FMASK 0x1
+#define VGV2_MITER_F_FADDR ADDR_VGV2_MITER
+#define VGV2_MITER_F_FSHIFT 0
+#define VGV2_MITER_F_FMASK 0xffffff
+#define VGV2_MODE_MAXSPLIT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_MAXSPLIT_FSHIFT 0
+#define VGV2_MODE_MAXSPLIT_FMASK 0xf
+#define VGV2_MODE_CAP_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_CAP_FSHIFT 4
+#define VGV2_MODE_CAP_FMASK 0x3
+#define VGV2_MODE_JOIN_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_JOIN_FSHIFT 6
+#define VGV2_MODE_JOIN_FMASK 0x3
+#define VGV2_MODE_STROKE_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_STROKE_FSHIFT 8
+#define VGV2_MODE_STROKE_FMASK 0x1
+#define VGV2_MODE_STROKESPLIT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_STROKESPLIT_FSHIFT 9
+#define VGV2_MODE_STROKESPLIT_FMASK 0x1
+#define VGV2_MODE_FULLSPLIT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_FULLSPLIT_FSHIFT 10
+#define VGV2_MODE_FULLSPLIT_FMASK 0x1
+#define VGV2_MODE_NODOTS_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_NODOTS_FSHIFT 11
+#define VGV2_MODE_NODOTS_FMASK 0x1
+#define VGV2_MODE_OPENFILL_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_OPENFILL_FSHIFT 12
+#define VGV2_MODE_OPENFILL_FMASK 0x1
+#define VGV2_MODE_DROPLEFT_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_DROPLEFT_FSHIFT 13
+#define VGV2_MODE_DROPLEFT_FMASK 0x1
+#define VGV2_MODE_DROPOTHER_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_DROPOTHER_FSHIFT 14
+#define VGV2_MODE_DROPOTHER_FMASK 0x1
+#define VGV2_MODE_SYMMETRICJOINS_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_SYMMETRICJOINS_FSHIFT 15
+#define VGV2_MODE_SYMMETRICJOINS_FMASK 0x1
+#define VGV2_MODE_SIMPLESTROKE_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_SIMPLESTROKE_FSHIFT 16
+#define VGV2_MODE_SIMPLESTROKE_FMASK 0x1
+#define VGV2_MODE_SIMPLECLIP_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_SIMPLECLIP_FSHIFT 17
+#define VGV2_MODE_SIMPLECLIP_FMASK 0x1
+#define VGV2_MODE_EXPONENTADD_FADDR ADDR_VGV2_MODE
+#define VGV2_MODE_EXPONENTADD_FSHIFT 18
+#define VGV2_MODE_EXPONENTADD_FMASK 0x3f
+#define VGV2_RADIUS_F_FADDR ADDR_VGV2_RADIUS
+#define VGV2_RADIUS_F_FSHIFT 0
+#define VGV2_RADIUS_F_FMASK 0xffffff
+#define VGV2_SCALE_F_FADDR ADDR_VGV2_SCALE
+#define VGV2_SCALE_F_FSHIFT 0
+#define VGV2_SCALE_F_FMASK 0xffffff
+#define VGV2_THINRADIUS_F_FADDR ADDR_VGV2_THINRADIUS
+#define VGV2_THINRADIUS_F_FSHIFT 0
+#define VGV2_THINRADIUS_F_FMASK 0xffffff
+#define VGV2_XFSTXX_F_FADDR ADDR_VGV2_XFSTXX
+#define VGV2_XFSTXX_F_FSHIFT 0
+#define VGV2_XFSTXX_F_FMASK 0xffffff
+#define VGV2_XFSTXY_F_FADDR ADDR_VGV2_XFSTXY
+#define VGV2_XFSTXY_F_FSHIFT 0
+#define VGV2_XFSTXY_F_FMASK 0xffffff
+#define VGV2_XFSTYX_F_FADDR ADDR_VGV2_XFSTYX
+#define VGV2_XFSTYX_F_FSHIFT 0
+#define VGV2_XFSTYX_F_FMASK 0xffffff
+#define VGV2_XFSTYY_F_FADDR ADDR_VGV2_XFSTYY
+#define VGV2_XFSTYY_F_FSHIFT 0
+#define VGV2_XFSTYY_F_FMASK 0xffffff
+#define VGV2_XFXA_F_FADDR ADDR_VGV2_XFXA
+#define VGV2_XFXA_F_FSHIFT 0
+#define VGV2_XFXA_F_FMASK 0xffffff
+#define VGV2_XFXX_F_FADDR ADDR_VGV2_XFXX
+#define VGV2_XFXX_F_FSHIFT 0
+#define VGV2_XFXX_F_FMASK 0xffffff
+#define VGV2_XFXY_F_FADDR ADDR_VGV2_XFXY
+#define VGV2_XFXY_F_FSHIFT 0
+#define VGV2_XFXY_F_FMASK 0xffffff
+#define VGV2_XFYA_F_FADDR ADDR_VGV2_XFYA
+#define VGV2_XFYA_F_FSHIFT 0
+#define VGV2_XFYA_F_FMASK 0xffffff
+#define VGV2_XFYX_F_FADDR ADDR_VGV2_XFYX
+#define VGV2_XFYX_F_FSHIFT 0
+#define VGV2_XFYX_F_FMASK 0xffffff
+#define VGV2_XFYY_F_FADDR ADDR_VGV2_XFYY
+#define VGV2_XFYY_F_FSHIFT 0
+#define VGV2_XFYY_F_FMASK 0xffffff
+#define VGV3_CONTROL_MARKADD_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_MARKADD_FSHIFT 0
+#define VGV3_CONTROL_MARKADD_FMASK 0xfff
+#define VGV3_CONTROL_DMIWAITCHMASK_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_DMIWAITCHMASK_FSHIFT 12
+#define VGV3_CONTROL_DMIWAITCHMASK_FMASK 0xf
+#define VGV3_CONTROL_PAUSE_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_PAUSE_FSHIFT 16
+#define VGV3_CONTROL_PAUSE_FMASK 0x1
+#define VGV3_CONTROL_ABORT_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_ABORT_FSHIFT 17
+#define VGV3_CONTROL_ABORT_FMASK 0x1
+#define VGV3_CONTROL_WRITE_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_WRITE_FSHIFT 18
+#define VGV3_CONTROL_WRITE_FMASK 0x1
+#define VGV3_CONTROL_BCFLUSH_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_BCFLUSH_FSHIFT 19
+#define VGV3_CONTROL_BCFLUSH_FMASK 0x1
+#define VGV3_CONTROL_V0SYNC_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_V0SYNC_FSHIFT 20
+#define VGV3_CONTROL_V0SYNC_FMASK 0x1
+#define VGV3_CONTROL_DMIWAITBUF_FADDR ADDR_VGV3_CONTROL
+#define VGV3_CONTROL_DMIWAITBUF_FSHIFT 21
+#define VGV3_CONTROL_DMIWAITBUF_FMASK 0x7
+#define VGV3_FIRST_DUMMY_FADDR ADDR_VGV3_FIRST
+#define VGV3_FIRST_DUMMY_FSHIFT 0
+#define VGV3_FIRST_DUMMY_FMASK 0x1
+#define VGV3_LAST_DUMMY_FADDR ADDR_VGV3_LAST
+#define VGV3_LAST_DUMMY_FSHIFT 0
+#define VGV3_LAST_DUMMY_FMASK 0x1
+#define VGV3_MODE_FLIPENDIAN_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_FLIPENDIAN_FSHIFT 0
+#define VGV3_MODE_FLIPENDIAN_FMASK 0x1
+#define VGV3_MODE_UNUSED_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_UNUSED_FSHIFT 1
+#define VGV3_MODE_UNUSED_FMASK 0x1
+#define VGV3_MODE_WRITEFLUSH_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_WRITEFLUSH_FSHIFT 2
+#define VGV3_MODE_WRITEFLUSH_FMASK 0x1
+#define VGV3_MODE_DMIPAUSETYPE_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_DMIPAUSETYPE_FSHIFT 3
+#define VGV3_MODE_DMIPAUSETYPE_FMASK 0x1
+#define VGV3_MODE_DMIRESET_FADDR ADDR_VGV3_MODE
+#define VGV3_MODE_DMIRESET_FSHIFT 4
+#define VGV3_MODE_DMIRESET_FMASK 0x1
+#define VGV3_NEXTADDR_CALLADDR_FADDR ADDR_VGV3_NEXTADDR
+#define VGV3_NEXTADDR_CALLADDR_FSHIFT 0
+#define VGV3_NEXTADDR_CALLADDR_FMASK 0xffffffff
+#define VGV3_NEXTCMD_COUNT_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_COUNT_FSHIFT 0
+#define VGV3_NEXTCMD_COUNT_FMASK 0xfff
+#define VGV3_NEXTCMD_NEXTCMD_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_NEXTCMD_FSHIFT 12
+#define VGV3_NEXTCMD_NEXTCMD_FMASK 0x7
+#define VGV3_NEXTCMD_MARK_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_MARK_FSHIFT 15
+#define VGV3_NEXTCMD_MARK_FMASK 0x1
+#define VGV3_NEXTCMD_CALLCOUNT_FADDR ADDR_VGV3_NEXTCMD
+#define VGV3_NEXTCMD_CALLCOUNT_FSHIFT 16
+#define VGV3_NEXTCMD_CALLCOUNT_FMASK 0xfff
+#define VGV3_VGBYPASS_BYPASS_FADDR ADDR_VGV3_VGBYPASS
+#define VGV3_VGBYPASS_BYPASS_FSHIFT 0
+#define VGV3_VGBYPASS_BYPASS_FMASK 0x1
+#define VGV3_WRITE_VALUE_FADDR ADDR_VGV3_WRITE
+#define VGV3_WRITE_VALUE_FSHIFT 0
+#define VGV3_WRITE_VALUE_FMASK 0xffffffff
+#define VGV3_WRITEADDR_ADDR_FADDR ADDR_VGV3_WRITEADDR
+#define VGV3_WRITEADDR_ADDR_FSHIFT 0
+#define VGV3_WRITEADDR_ADDR_FMASK 0xffffffff
+#define VGV3_WRITEDMI_CHANMASK_FADDR ADDR_VGV3_WRITEDMI
+#define VGV3_WRITEDMI_CHANMASK_FSHIFT 0
+#define VGV3_WRITEDMI_CHANMASK_FMASK 0xf
+#define VGV3_WRITEDMI_BUFFER_FADDR ADDR_VGV3_WRITEDMI
+#define VGV3_WRITEDMI_BUFFER_FSHIFT 4
+#define VGV3_WRITEDMI_BUFFER_FMASK 0x7
+#define VGV3_WRITEF32_ADDR_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_ADDR_FSHIFT 0
+#define VGV3_WRITEF32_ADDR_FMASK 0xff
+#define VGV3_WRITEF32_COUNT_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_COUNT_FSHIFT 8
+#define VGV3_WRITEF32_COUNT_FMASK 0xff
+#define VGV3_WRITEF32_LOOP_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_LOOP_FSHIFT 16
+#define VGV3_WRITEF32_LOOP_FMASK 0xf
+#define VGV3_WRITEF32_ACTION_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_ACTION_FSHIFT 20
+#define VGV3_WRITEF32_ACTION_FMASK 0xf
+#define VGV3_WRITEF32_FORMAT_FADDR ADDR_VGV3_WRITEF32
+#define VGV3_WRITEF32_FORMAT_FSHIFT 24
+#define VGV3_WRITEF32_FORMAT_FMASK 0x7
+#define VGV3_WRITEIFPAUSED_VALUE_FADDR ADDR_VGV3_WRITEIFPAUSED
+#define VGV3_WRITEIFPAUSED_VALUE_FSHIFT 0
+#define VGV3_WRITEIFPAUSED_VALUE_FMASK 0xffffffff
+#define VGV3_WRITERAW_ADDR_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_ADDR_FSHIFT 0
+#define VGV3_WRITERAW_ADDR_FMASK 0xff
+#define VGV3_WRITERAW_COUNT_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_COUNT_FSHIFT 8
+#define VGV3_WRITERAW_COUNT_FMASK 0xff
+#define VGV3_WRITERAW_LOOP_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_LOOP_FSHIFT 16
+#define VGV3_WRITERAW_LOOP_FMASK 0xf
+#define VGV3_WRITERAW_ACTION_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_ACTION_FSHIFT 20
+#define VGV3_WRITERAW_ACTION_FMASK 0xf
+#define VGV3_WRITERAW_FORMAT_FADDR ADDR_VGV3_WRITERAW
+#define VGV3_WRITERAW_FORMAT_FSHIFT 24
+#define VGV3_WRITERAW_FORMAT_FMASK 0x7
+#define VGV3_WRITES16_ADDR_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_ADDR_FSHIFT 0
+#define VGV3_WRITES16_ADDR_FMASK 0xff
+#define VGV3_WRITES16_COUNT_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_COUNT_FSHIFT 8
+#define VGV3_WRITES16_COUNT_FMASK 0xff
+#define VGV3_WRITES16_LOOP_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_LOOP_FSHIFT 16
+#define VGV3_WRITES16_LOOP_FMASK 0xf
+#define VGV3_WRITES16_ACTION_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_ACTION_FSHIFT 20
+#define VGV3_WRITES16_ACTION_FMASK 0xf
+#define VGV3_WRITES16_FORMAT_FADDR ADDR_VGV3_WRITES16
+#define VGV3_WRITES16_FORMAT_FSHIFT 24
+#define VGV3_WRITES16_FORMAT_FMASK 0x7
+#define VGV3_WRITES32_ADDR_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_ADDR_FSHIFT 0
+#define VGV3_WRITES32_ADDR_FMASK 0xff
+#define VGV3_WRITES32_COUNT_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_COUNT_FSHIFT 8
+#define VGV3_WRITES32_COUNT_FMASK 0xff
+#define VGV3_WRITES32_LOOP_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_LOOP_FSHIFT 16
+#define VGV3_WRITES32_LOOP_FMASK 0xf
+#define VGV3_WRITES32_ACTION_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_ACTION_FSHIFT 20
+#define VGV3_WRITES32_ACTION_FMASK 0xf
+#define VGV3_WRITES32_FORMAT_FADDR ADDR_VGV3_WRITES32
+#define VGV3_WRITES32_FORMAT_FSHIFT 24
+#define VGV3_WRITES32_FORMAT_FMASK 0x7
+#define VGV3_WRITES8_ADDR_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_ADDR_FSHIFT 0
+#define VGV3_WRITES8_ADDR_FMASK 0xff
+#define VGV3_WRITES8_COUNT_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_COUNT_FSHIFT 8
+#define VGV3_WRITES8_COUNT_FMASK 0xff
+#define VGV3_WRITES8_LOOP_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_LOOP_FSHIFT 16
+#define VGV3_WRITES8_LOOP_FMASK 0xf
+#define VGV3_WRITES8_ACTION_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_ACTION_FSHIFT 20
+#define VGV3_WRITES8_ACTION_FMASK 0xf
+#define VGV3_WRITES8_FORMAT_FADDR ADDR_VGV3_WRITES8
+#define VGV3_WRITES8_FORMAT_FSHIFT 24
+#define VGV3_WRITES8_FORMAT_FMASK 0x7
+typedef struct {
+    unsigned RS[256];
+    unsigned GRADW[2][40];
+} regstate_t;
+
+#define GRADW_WINDOW_START 0xc0
+#define GRADW_WINDOW_LEN 0x28
+#define GRADW_WINDOW_NUM 0x2
+
+static unsigned __inline __getwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        assert( win < 2 );
+        return (RS->GRADW[win][addr-0xc0] >>
+                shift) & mask;
+    }
+    return ((RS->RS[addr] >> shift) & mask);
+}
+
+static void __inline __setwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & 
+                   ~(mask << shift)) | 
+                   ((mask & data) << shift);
+    }
+    RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift);
+}
+
+static void __inline __setwreg__(regstate_t* RS, unsigned win, unsigned addr, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = data;
+    }
+    RS->RS[addr] = data;
+}
+
+static unsigned __inline __getrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask) {
+    return ((RS->RS[addr] >> shift) & mask);
+}
+
+static void __inline __setrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK);
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & 
+                   ~(mask << shift)) | ((mask & data) << shift);
+    }
+    RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift);
+}
+
+static void __inline __setreg__(regstate_t* RS, unsigned addr, unsigned data) {
+    if ( addr >= 0xc0 && addr < 0xe8 ) { 
+        unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK);
+        assert( win < 2 );
+        RS->GRADW[win][addr-0xc0] = data;
+    }
+    RS->RS[addr] = data;
+}
+
+#define SETWRS(win, id, value) __setwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK, value)
+#define GETWRS(win, id) __getwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK)
+#define SETWREG(win, reg, data) __setwreg__(&RS, win, reg, data)
+#define SETRS(id, value) __setrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK, value)
+#define GETRS(id) __getrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK)
+#define SETREG(reg, data) __setreg__(&RS, reg, data)
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato.h b/drivers/mxc/amd-gpu/include/reg/yamato.h
new file mode 100644
index 00000000000..05cae6c4640
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _YAMATO_H
+#define _YAMATO_H
+
+#ifndef qLittleEndian
+#define qLittleEndian
+#endif
+
+#if defined(_YDX14)
+#if defined(_WIN32) && !defined(__SYMBIAN32__)
+#pragma message("YDX 14 header files\r\n")
+#endif
+#include "yamato/14/yamato_enum.h"
+#include "yamato/14/yamato_ipt.h"
+#include "yamato/14/yamato_mask.h"
+#include "yamato/14/yamato_offset.h"
+#include "yamato/14/yamato_registers.h"
+#include "yamato/14/yamato_shift.h"
+#include "yamato/14/yamato_struct.h"
+#include "yamato/14/yamato_typedef.h"
+#define _YAMATO_GENENUM_H           "reg/yamato/14/yamato_genenum.h"
+#define _YAMATO_GENREG_H            "reg/yamato/14/yamato_genreg.h"
+#else
+#if defined(_WIN32) && !defined(__SYMBIAN32__)
+#pragma message("YDX 22 header files\r\n")
+#endif
+#include "yamato/22/yamato_enum.h"
+#include "yamato/22/yamato_ipt.h"
+#include "yamato/22/yamato_mask.h"
+#include "yamato/22/yamato_offset.h"
+#include "yamato/22/yamato_registers.h"
+#include "yamato/22/yamato_shift.h"
+#include "yamato/22/yamato_struct.h"
+#include "yamato/22/yamato_typedef.h"
+#define _YAMATO_GENENUM_H           "reg/yamato/22/yamato_genenum.h"
+#define _YAMATO_GENREG_H            "reg/yamato/22/yamato_genreg.h"
+#endif
+
+#endif // _YAMATO_H
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h
new file mode 100644
index 00000000000..144e9151fd8
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h
@@ -0,0 +1,1895 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_ENUM_HEADER)
+#define _yamato_ENUM_HEADER
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+#ifndef ENUMS_SU_PERFCNT_SELECT_H
+#define ENUMS_SU_PERFCNT_SELECT_H
+typedef enum SU_PERFCNT_SELECT {
+ PERF_PAPC_PASX_REQ = 0,
+ UNUSED1 = 1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 3,
+ PERF_PAPC_PASX_FIRST_DEAD = 4,
+ PERF_PAPC_PASX_SECOND_DEAD = 5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+ PERF_PAPC_PA_INPUT_PRIM = 8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+ PERF_PAPC_CLPR_CULL_PRIM = 13,
+ UNUSED2 = 14,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+ UNUSED3 = 16,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+ UNUSED4 = 20,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+ UNUSED5 = 22,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+ PERF_PAPC_CLSM_NULL_PRIM = 36,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+ PERF_PAPC_CLSM_CLIP_PRIM = 38,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+ PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+ PERF_PAPC_SU_INPUT_PRIM = 47,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+ PERF_PAPC_SU_OUTPUT_PRIM = 57,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+ PERF_PAPC_PASX_REQ_IDLE = 69,
+ PERF_PAPC_PASX_REQ_BUSY = 70,
+ PERF_PAPC_PASX_REQ_STALLED = 71,
+ PERF_PAPC_PASX_REC_IDLE = 72,
+ PERF_PAPC_PASX_REC_BUSY = 73,
+ PERF_PAPC_PASX_REC_STARVED_SX = 74,
+ PERF_PAPC_PASX_REC_STALLED = 75,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+ PERF_PAPC_CCGSM_IDLE = 78,
+ PERF_PAPC_CCGSM_BUSY = 79,
+ PERF_PAPC_CCGSM_STALLED = 80,
+ PERF_PAPC_CLPRIM_IDLE = 81,
+ PERF_PAPC_CLPRIM_BUSY = 82,
+ PERF_PAPC_CLPRIM_STALLED = 83,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+ PERF_PAPC_CLIPSM_IDLE = 85,
+ PERF_PAPC_CLIPSM_BUSY = 86,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+ PERF_PAPC_CLIPGA_IDLE = 92,
+ PERF_PAPC_CLIPGA_BUSY = 93,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+ PERF_PAPC_CLIPGA_STALLED = 95,
+ PERF_PAPC_CLIP_IDLE = 96,
+ PERF_PAPC_CLIP_BUSY = 97,
+ PERF_PAPC_SU_IDLE = 98,
+ PERF_PAPC_SU_BUSY = 99,
+ PERF_PAPC_SU_STARVED_CLIP = 100,
+ PERF_PAPC_SU_STALLED_SC = 101,
+ PERF_PAPC_SU_FACENESS_CULL = 102,
+} SU_PERFCNT_SELECT;
+#endif /*ENUMS_SU_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SC_PERFCNT_SELECT_H
+#define ENUMS_SC_PERFCNT_SELECT_H
+typedef enum SC_PERFCNT_SELECT {
+ SC_SR_WINDOW_VALID = 0,
+ SC_CW_WINDOW_VALID = 1,
+ SC_QM_WINDOW_VALID = 2,
+ SC_FW_WINDOW_VALID = 3,
+ SC_EZ_WINDOW_VALID = 4,
+ SC_IT_WINDOW_VALID = 5,
+ SC_STARVED_BY_PA = 6,
+ SC_STALLED_BY_RB_TILE = 7,
+ SC_STALLED_BY_RB_SAMP = 8,
+ SC_STARVED_BY_RB_EZ = 9,
+ SC_STALLED_BY_SAMPLE_FF = 10,
+ SC_STALLED_BY_SQ = 11,
+ SC_STALLED_BY_SP = 12,
+ SC_TOTAL_NO_PRIMS = 13,
+ SC_NON_EMPTY_PRIMS = 14,
+ SC_NO_TILES_PASSING_QM = 15,
+ SC_NO_PIXELS_PRE_EZ = 16,
+ SC_NO_PIXELS_POST_EZ = 17,
+} SC_PERFCNT_SELECT;
+#endif /*ENUMS_SC_PERFCNT_SELECT_H*/
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+#ifndef ENUMS_VGT_DI_PRIM_TYPE_H
+#define ENUMS_VGT_DI_PRIM_TYPE_H
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0,
+ DI_PT_POINTLIST = 1,
+ DI_PT_LINELIST = 2,
+ DI_PT_LINESTRIP = 3,
+ DI_PT_TRILIST = 4,
+ DI_PT_TRIFAN = 5,
+ DI_PT_TRISTRIP = 6,
+ DI_PT_UNUSED_1 = 7,
+ DI_PT_RECTLIST = 8,
+ DI_PT_UNUSED_2 = 9,
+ DI_PT_UNUSED_3 = 10,
+ DI_PT_UNUSED_4 = 11,
+ DI_PT_UNUSED_5 = 12,
+ DI_PT_QUADLIST = 13,
+ DI_PT_QUADSTRIP = 14,
+ DI_PT_POLYGON = 15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+ DI_PT_2D_FILL_RECT_LIST = 20,
+ DI_PT_2D_LINE_STRIP = 21,
+ DI_PT_2D_TRI_STRIP = 22,
+} VGT_DI_PRIM_TYPE;
+#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/
+
+#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H
+#define ENUMS_VGT_DI_SOURCE_SELECT_H
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0,
+ DI_SRC_SEL_IMMEDIATE = 1,
+ DI_SRC_SEL_AUTO_INDEX = 2,
+ DI_SRC_SEL_RESERVED = 3
+} VGT_DI_SOURCE_SELECT;
+#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+typedef enum VGT_DI_FACENESS_CULL_SELECT {
+ DI_FACE_CULL_NONE = 0,
+ DI_FACE_CULL_FETCH = 1,
+ DI_FACE_BACKFACE_CULL = 2,
+ DI_FACE_FRONTFACE_CULL = 3
+} VGT_DI_FACENESS_CULL_SELECT;
+#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_INDEX_SIZE_H
+#define ENUMS_VGT_DI_INDEX_SIZE_H
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0,
+ DI_INDEX_SIZE_32_BIT = 1
+} VGT_DI_INDEX_SIZE;
+#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/
+
+#ifndef ENUMS_VGT_DI_SMALL_INDEX_H
+#define ENUMS_VGT_DI_SMALL_INDEX_H
+typedef enum VGT_DI_SMALL_INDEX {
+ DI_USE_INDEX_SIZE = 0,
+ DI_INDEX_SIZE_8_BIT = 1
+} VGT_DI_SMALL_INDEX;
+#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/
+
+#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE {
+ DISABLE_PRE_FETCH_CULL_ENABLE = 0,
+ PRE_FETCH_CULL_ENABLE = 1
+} VGT_DI_PRE_FETCH_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+typedef enum VGT_DI_GRP_CULL_ENABLE {
+ DISABLE_GRP_CULL_ENABLE = 0,
+ GRP_CULL_ENABLE = 1
+} VGT_DI_GRP_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_EVENT_TYPE_H
+#define ENUMS_VGT_EVENT_TYPE_H
+typedef enum VGT_EVENT_TYPE {
+ VS_DEALLOC = 0,
+ PS_DEALLOC = 1,
+ VS_DONE_TS = 2,
+ PS_DONE_TS = 3,
+ CACHE_FLUSH_TS = 4,
+ CONTEXT_DONE = 5,
+ CACHE_FLUSH = 6,
+ VIZQUERY_START = 7,
+ VIZQUERY_END = 8,
+ SC_WAIT_WC = 9,
+ RST_PIX_CNT = 13,
+ RST_VTX_CNT = 14,
+ TILE_FLUSH = 15,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+ ZPASS_DONE = 21,
+ CACHE_FLUSH_AND_INV_EVENT = 22,
+ PERFCOUNTER_START = 23,
+ PERFCOUNTER_STOP = 24,
+ VS_FETCH_DONE = 27,
+ FACENESS_FLUSH = 28,
+} VGT_EVENT_TYPE;
+#endif /*ENUMS_VGT_EVENT_TYPE_H*/
+
+#ifndef ENUMS_VGT_DMA_SWAP_MODE_H
+#define ENUMS_VGT_DMA_SWAP_MODE_H
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0,
+ VGT_DMA_SWAP_16_BIT = 1,
+ VGT_DMA_SWAP_32_BIT = 2,
+ VGT_DMA_SWAP_WORD = 3
+} VGT_DMA_SWAP_MODE;
+#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/
+
+#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H
+#define ENUMS_VGT_PERFCOUNT_SELECT_H
+typedef enum VGT_PERFCOUNT_SELECT {
+ VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+ VGT_SQ_SEND = 1,
+ VGT_SQ_STALLED = 2,
+ VGT_SQ_STARVED_BUSY = 3,
+ VGT_SQ_STARVED_IDLE = 4,
+ VGT_SQ_STATIC = 5,
+ VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+ VGT_PA_CLIP_V_SEND = 7,
+ VGT_PA_CLIP_V_STALLED = 8,
+ VGT_PA_CLIP_V_STARVED_BUSY = 9,
+ VGT_PA_CLIP_V_STARVED_IDLE = 10,
+ VGT_PA_CLIP_V_STATIC = 11,
+ VGT_PA_CLIP_P_SEND = 12,
+ VGT_PA_CLIP_P_STALLED = 13,
+ VGT_PA_CLIP_P_STARVED_BUSY = 14,
+ VGT_PA_CLIP_P_STARVED_IDLE = 15,
+ VGT_PA_CLIP_P_STATIC = 16,
+ VGT_PA_CLIP_S_SEND = 17,
+ VGT_PA_CLIP_S_STALLED = 18,
+ VGT_PA_CLIP_S_STARVED_BUSY = 19,
+ VGT_PA_CLIP_S_STARVED_IDLE = 20,
+ VGT_PA_CLIP_S_STATIC = 21,
+ RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+ RBIU_IMMED_DATA_FIFO_STARVED = 23,
+ RBIU_IMMED_DATA_FIFO_STALLED = 24,
+ RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+ RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+ RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+ RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+ BIN_PRIM_NEAR_CULL = 29,
+ BIN_PRIM_ZERO_CULL = 30,
+ BIN_PRIM_FAR_CULL = 31,
+ BIN_PRIM_BIN_CULL = 32,
+ BIN_PRIM_FACE_CULL = 33,
+ SPARE34 = 34,
+ SPARE35 = 35,
+ SPARE36 = 36,
+ SPARE37 = 37,
+ SPARE38 = 38,
+ SPARE39 = 39,
+ TE_SU_IN_VALID = 40,
+ TE_SU_IN_READ = 41,
+ TE_SU_IN_PRIM = 42,
+ TE_SU_IN_EOP = 43,
+ TE_SU_IN_NULL_PRIM = 44,
+ TE_WK_IN_VALID = 45,
+ TE_WK_IN_READ = 46,
+ TE_OUT_PRIM_VALID = 47,
+ TE_OUT_PRIM_READ = 48,
+} VGT_PERFCOUNT_SELECT;
+#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H
+#define ENUMS_TCR_PERFCOUNT_SELECT_H
+typedef enum TCR_PERFCOUNT_SELECT {
+ DGMMPD_IPMUX0_STALL = 0,
+ reserved_46 = 1,
+ reserved_47 = 2,
+ reserved_48 = 3,
+ DGMMPD_IPMUX_ALL_STALL = 4,
+ OPMUX0_L2_WRITES = 5,
+ reserved_49 = 6,
+ reserved_50 = 7,
+ reserved_51 = 8,
+} TCR_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TP_PERFCOUNT_SELECT_H
+#define ENUMS_TP_PERFCOUNT_SELECT_H
+typedef enum TP_PERFCOUNT_SELECT {
+ POINT_QUADS = 0,
+ BILIN_QUADS = 1,
+ ANISO_QUADS = 2,
+ MIP_QUADS = 3,
+ VOL_QUADS = 4,
+ MIP_VOL_QUADS = 5,
+ MIP_ANISO_QUADS = 6,
+ VOL_ANISO_QUADS = 7,
+ ANISO_2_1_QUADS = 8,
+ ANISO_4_1_QUADS = 9,
+ ANISO_6_1_QUADS = 10,
+ ANISO_8_1_QUADS = 11,
+ ANISO_10_1_QUADS = 12,
+ ANISO_12_1_QUADS = 13,
+ ANISO_14_1_QUADS = 14,
+ ANISO_16_1_QUADS = 15,
+ MIP_VOL_ANISO_QUADS = 16,
+ ALIGN_2_QUADS = 17,
+ ALIGN_4_QUADS = 18,
+ PIX_0_QUAD = 19,
+ PIX_1_QUAD = 20,
+ PIX_2_QUAD = 21,
+ PIX_3_QUAD = 22,
+ PIX_4_QUAD = 23,
+ TP_MIPMAP_LOD0 = 24,
+ TP_MIPMAP_LOD1 = 25,
+ TP_MIPMAP_LOD2 = 26,
+ TP_MIPMAP_LOD3 = 27,
+ TP_MIPMAP_LOD4 = 28,
+ TP_MIPMAP_LOD5 = 29,
+ TP_MIPMAP_LOD6 = 30,
+ TP_MIPMAP_LOD7 = 31,
+ TP_MIPMAP_LOD8 = 32,
+ TP_MIPMAP_LOD9 = 33,
+ TP_MIPMAP_LOD10 = 34,
+ TP_MIPMAP_LOD11 = 35,
+ TP_MIPMAP_LOD12 = 36,
+ TP_MIPMAP_LOD13 = 37,
+ TP_MIPMAP_LOD14 = 38,
+} TP_PERFCOUNT_SELECT;
+#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H
+#define ENUMS_TCM_PERFCOUNT_SELECT_H
+typedef enum TCM_PERFCOUNT_SELECT {
+ QUAD0_RD_LAT_FIFO_EMPTY = 0,
+ reserved_01 = 1,
+ reserved_02 = 2,
+ QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+ QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+ QUAD0_RD_LAT_FIFO_FULL = 5,
+ QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+ reserved_07 = 7,
+ reserved_08 = 8,
+ reserved_09 = 9,
+ reserved_10 = 10,
+ reserved_11 = 11,
+ reserved_12 = 12,
+ reserved_13 = 13,
+ reserved_14 = 14,
+ reserved_15 = 15,
+ reserved_16 = 16,
+ reserved_17 = 17,
+ reserved_18 = 18,
+ reserved_19 = 19,
+ reserved_20 = 20,
+ reserved_21 = 21,
+ reserved_22 = 22,
+ reserved_23 = 23,
+ reserved_24 = 24,
+ reserved_25 = 25,
+ reserved_26 = 26,
+ reserved_27 = 27,
+ READ_STARVED_QUAD0 = 28,
+ reserved_29 = 29,
+ reserved_30 = 30,
+ reserved_31 = 31,
+ READ_STARVED = 32,
+ READ_STALLED_QUAD0 = 33,
+ reserved_34 = 34,
+ reserved_35 = 35,
+ reserved_36 = 36,
+ READ_STALLED = 37,
+ VALID_READ_QUAD0 = 38,
+ reserved_39 = 39,
+ reserved_40 = 40,
+ reserved_41 = 41,
+ TC_TP_STARVED_QUAD0 = 42,
+ reserved_43 = 43,
+ reserved_44 = 44,
+ reserved_45 = 45,
+ TC_TP_STARVED = 46,
+} TCM_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H
+#define ENUMS_TCF_PERFCOUNT_SELECT_H
+typedef enum TCF_PERFCOUNT_SELECT {
+ VALID_CYCLES = 0,
+ SINGLE_PHASES = 1,
+ ANISO_PHASES = 2,
+ MIP_PHASES = 3,
+ VOL_PHASES = 4,
+ MIP_VOL_PHASES = 5,
+ MIP_ANISO_PHASES = 6,
+ VOL_ANISO_PHASES = 7,
+ ANISO_2_1_PHASES = 8,
+ ANISO_4_1_PHASES = 9,
+ ANISO_6_1_PHASES = 10,
+ ANISO_8_1_PHASES = 11,
+ ANISO_10_1_PHASES = 12,
+ ANISO_12_1_PHASES = 13,
+ ANISO_14_1_PHASES = 14,
+ ANISO_16_1_PHASES = 15,
+ MIP_VOL_ANISO_PHASES = 16,
+ ALIGN_2_PHASES = 17,
+ ALIGN_4_PHASES = 18,
+ TPC_BUSY = 19,
+ TPC_STALLED = 20,
+ TPC_STARVED = 21,
+ TPC_WORKING = 22,
+ TPC_WALKER_BUSY = 23,
+ TPC_WALKER_STALLED = 24,
+ TPC_WALKER_WORKING = 25,
+ TPC_ALIGNER_BUSY = 26,
+ TPC_ALIGNER_STALLED = 27,
+ TPC_ALIGNER_STALLED_BY_BLEND = 28,
+ TPC_ALIGNER_STALLED_BY_CACHE = 29,
+ TPC_ALIGNER_WORKING = 30,
+ TPC_BLEND_BUSY = 31,
+ TPC_BLEND_SYNC = 32,
+ TPC_BLEND_STARVED = 33,
+ TPC_BLEND_WORKING = 34,
+ OPCODE_0x00 = 35,
+ OPCODE_0x01 = 36,
+ OPCODE_0x04 = 37,
+ OPCODE_0x10 = 38,
+ OPCODE_0x11 = 39,
+ OPCODE_0x12 = 40,
+ OPCODE_0x13 = 41,
+ OPCODE_0x18 = 42,
+ OPCODE_0x19 = 43,
+ OPCODE_0x1A = 44,
+ OPCODE_OTHER = 45,
+ IN_FIFO_0_EMPTY = 56,
+ IN_FIFO_0_LT_HALF_FULL = 57,
+ IN_FIFO_0_HALF_FULL = 58,
+ IN_FIFO_0_FULL = 59,
+ IN_FIFO_TPC_EMPTY = 72,
+ IN_FIFO_TPC_LT_HALF_FULL = 73,
+ IN_FIFO_TPC_HALF_FULL = 74,
+ IN_FIFO_TPC_FULL = 75,
+ TPC_TC_XFC = 76,
+ TPC_TC_STATE = 77,
+ TC_STALL = 78,
+ QUAD0_TAPS = 79,
+ QUADS = 83,
+ TCA_SYNC_STALL = 84,
+ TAG_STALL = 85,
+ TCB_SYNC_STALL = 88,
+ TCA_VALID = 89,
+ PROBES_VALID = 90,
+ MISS_STALL = 91,
+ FETCH_FIFO_STALL = 92,
+ TCO_STALL = 93,
+ ANY_STALL = 94,
+ TAG_MISSES = 95,
+ TAG_HITS = 96,
+ SUB_TAG_MISSES = 97,
+ SET0_INVALIDATES = 98,
+ SET1_INVALIDATES = 99,
+ SET2_INVALIDATES = 100,
+ SET3_INVALIDATES = 101,
+ SET0_TAG_MISSES = 102,
+ SET1_TAG_MISSES = 103,
+ SET2_TAG_MISSES = 104,
+ SET3_TAG_MISSES = 105,
+ SET0_TAG_HITS = 106,
+ SET1_TAG_HITS = 107,
+ SET2_TAG_HITS = 108,
+ SET3_TAG_HITS = 109,
+ SET0_SUB_TAG_MISSES = 110,
+ SET1_SUB_TAG_MISSES = 111,
+ SET2_SUB_TAG_MISSES = 112,
+ SET3_SUB_TAG_MISSES = 113,
+ SET0_EVICT1 = 114,
+ SET0_EVICT2 = 115,
+ SET0_EVICT3 = 116,
+ SET0_EVICT4 = 117,
+ SET0_EVICT5 = 118,
+ SET0_EVICT6 = 119,
+ SET0_EVICT7 = 120,
+ SET0_EVICT8 = 121,
+ SET1_EVICT1 = 130,
+ SET1_EVICT2 = 131,
+ SET1_EVICT3 = 132,
+ SET1_EVICT4 = 133,
+ SET1_EVICT5 = 134,
+ SET1_EVICT6 = 135,
+ SET1_EVICT7 = 136,
+ SET1_EVICT8 = 137,
+ SET2_EVICT1 = 146,
+ SET2_EVICT2 = 147,
+ SET2_EVICT3 = 148,
+ SET2_EVICT4 = 149,
+ SET2_EVICT5 = 150,
+ SET2_EVICT6 = 151,
+ SET2_EVICT7 = 152,
+ SET2_EVICT8 = 153,
+ SET3_EVICT1 = 162,
+ SET3_EVICT2 = 163,
+ SET3_EVICT3 = 164,
+ SET3_EVICT4 = 165,
+ SET3_EVICT5 = 166,
+ SET3_EVICT6 = 167,
+ SET3_EVICT7 = 168,
+ SET3_EVICT8 = 169,
+ FF_EMPTY = 178,
+ FF_LT_HALF_FULL = 179,
+ FF_HALF_FULL = 180,
+ FF_FULL = 181,
+ FF_XFC = 182,
+ FF_STALLED = 183,
+ FG_MASKS = 184,
+ FG_LEFT_MASKS = 185,
+ FG_LEFT_MASK_STALLED = 186,
+ FG_LEFT_NOT_DONE_STALL = 187,
+ FG_LEFT_FG_STALL = 188,
+ FG_LEFT_SECTORS = 189,
+ FG0_REQUESTS = 195,
+ FG0_STALLED = 196,
+ MEM_REQ512 = 199,
+ MEM_REQ_SENT = 200,
+ MEM_LOCAL_READ_REQ = 202,
+ TC0_MH_STALLED = 203,
+} TCF_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+#ifndef ENUMS_SQ_PERFCNT_SELECT_H
+#define ENUMS_SQ_PERFCNT_SELECT_H
+typedef enum SQ_PERFCNT_SELECT {
+ SQ_PIXEL_VECTORS_SUB = 0,
+ SQ_VERTEX_VECTORS_SUB = 1,
+ SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+ SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+ SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+ SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+ SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+ SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+ SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+ SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+ SQ_EXPORT_CYCLES = 10,
+ SQ_ALU_CST_WRITTEN = 11,
+ SQ_TEX_CST_WRITTEN = 12,
+ SQ_ALU_CST_STALL = 13,
+ SQ_ALU_TEX_STALL = 14,
+ SQ_INST_WRITTEN = 15,
+ SQ_BOOLEAN_WRITTEN = 16,
+ SQ_LOOPS_WRITTEN = 17,
+ SQ_PIXEL_SWAP_IN = 18,
+ SQ_PIXEL_SWAP_OUT = 19,
+ SQ_VERTEX_SWAP_IN = 20,
+ SQ_VERTEX_SWAP_OUT = 21,
+ SQ_ALU_VTX_INST_ISSUED = 22,
+ SQ_TEX_VTX_INST_ISSUED = 23,
+ SQ_VC_VTX_INST_ISSUED = 24,
+ SQ_CF_VTX_INST_ISSUED = 25,
+ SQ_ALU_PIX_INST_ISSUED = 26,
+ SQ_TEX_PIX_INST_ISSUED = 27,
+ SQ_VC_PIX_INST_ISSUED = 28,
+ SQ_CF_PIX_INST_ISSUED = 29,
+ SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+ SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+ SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+ SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+ SQ_ALU_NOPS = 34,
+ SQ_PRED_SKIP = 35,
+ SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+ SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+ SQ_SYNC_TEX_STALL_VTX = 38,
+ SQ_SYNC_VC_STALL_VTX = 39,
+ SQ_CONSTANTS_USED_SIMD0 = 40,
+ SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+ SQ_GPR_STALL_VTX = 42,
+ SQ_GPR_STALL_PIX = 43,
+ SQ_VTX_RS_STALL = 44,
+ SQ_PIX_RS_STALL = 45,
+ SQ_SX_PC_FULL   = 46,
+ SQ_SX_EXP_BUFF_FULL = 47,
+ SQ_SX_POS_BUFF_FULL = 48,
+ SQ_INTERP_QUADS = 49,
+ SQ_INTERP_ACTIVE = 50,
+ SQ_IN_PIXEL_STALL = 51,
+ SQ_IN_VTX_STALL = 52,
+ SQ_VTX_CNT = 53,
+ SQ_VTX_VECTOR2 = 54,
+ SQ_VTX_VECTOR3 = 55,
+ SQ_VTX_VECTOR4 = 56,
+ SQ_PIXEL_VECTOR1 = 57,
+ SQ_PIXEL_VECTOR23 = 58,
+ SQ_PIXEL_VECTOR4 = 59,
+ SQ_CONSTANTS_USED_SIMD1 = 60,
+ SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+ SQ_SX_MEM_EXP_FULL = 62,
+ SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+ SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+ SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+ SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+ SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+ SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
+ SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+ SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
+ SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+ SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+ SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+ SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+ SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+ SQ_PERFCOUNT_VTX_POP_THREAD = 76,
+ SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+ SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+ SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+ SQ_PERFCOUNT_PIX_POP_THREAD = 80,
+ SQ_SYNC_TEX_STALL_PIX = 81,
+ SQ_SYNC_VC_STALL_PIX = 82,
+ SQ_CONSTANTS_USED_SIMD2 = 83,
+ SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+ SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
+ SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
+ SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+ SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+ SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+ SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+ SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+ SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+ SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+ SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+ VC_PERF_STATIC = 95,
+ VC_PERF_STALLED = 96,
+ VC_PERF_STARVED = 97,
+ VC_PERF_SEND = 98,
+ VC_PERF_ACTUAL_STARVED = 99,
+ PIXEL_THREAD_0_ACTIVE   = 100,
+ VERTEX_THREAD_0_ACTIVE  = 101,
+ PIXEL_THREAD_0_NUMBER   = 102,
+ VERTEX_THREAD_0_NUMBER  = 103,
+ VERTEX_EVENT_NUMBER     = 104,
+ PIXEL_EVENT_NUMBER  = 105,
+ PTRBUFF_EF_PUSH = 106,
+ PTRBUFF_EF_POP_EVENT = 107,
+ PTRBUFF_EF_POP_NEW_VTX = 108,
+ PTRBUFF_EF_POP_DEALLOC = 109,
+ PTRBUFF_EF_POP_PVECTOR = 110,
+ PTRBUFF_EF_POP_PVECTOR_X = 111,
+ PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+ PTRBUFF_PB_DEALLOC = 113,
+ PTRBUFF_PI_STATE_PPB_POP = 114,
+ PTRBUFF_PI_RTR = 115,
+ PTRBUFF_PI_READ_EN = 116,
+ PTRBUFF_PI_BUFF_SWAP = 117,
+ PTRBUFF_SQ_FREE_BUFF = 118,
+ PTRBUFF_SQ_DEC = 119,
+ PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+ PTRBUFF_SC_VALID_IJ_XFER = 121,
+ PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+ PTRBUFF_QUAL_NEW_VECTOR = 123,
+ PTRBUFF_QUAL_EVENT = 124,
+ PTRBUFF_END_BUFFER = 125,
+ PTRBUFF_FILL_QUAD = 126,
+ VERTS_WRITTEN_SPI = 127,
+ TP_FETCH_INSTR_EXEC = 128,
+ TP_FETCH_INSTR_REQ = 129,
+ TP_DATA_RETURN = 130,
+ SPI_WRITE_CYCLES_SP = 131,
+ SPI_WRITES_SP = 132,
+ SP_ALU_INSTR_EXEC = 133,
+ SP_CONST_ADDR_TO_SQ = 134,
+ SP_PRED_KILLS_TO_SQ = 135,
+ SP_EXPORT_CYCLES_TO_SX = 136,
+ SP_EXPORTS_TO_SX = 137,
+ SQ_CYCLES_ELAPSED = 138,
+ SQ_TCFS_OPT_ALLOC_EXEC = 139,
+ SQ_TCFS_NO_OPT_ALLOC = 140,
+ SQ_ALU0_NO_OPT_ALLOC = 141,
+ SQ_ALU1_NO_OPT_ALLOC = 142,
+ SQ_TCFS_ARB_XFC_CNT = 143,
+ SQ_ALU0_ARB_XFC_CNT = 144,
+ SQ_ALU1_ARB_XFC_CNT = 145,
+ SQ_TCFS_CFS_UPDATE_CNT = 146,
+ SQ_ALU0_CFS_UPDATE_CNT = 147,
+ SQ_ALU1_CFS_UPDATE_CNT = 148,
+ SQ_VTX_PUSH_THREAD_CNT = 149,
+ SQ_VTX_POP_THREAD_CNT = 150,
+ SQ_PIX_PUSH_THREAD_CNT = 151,
+ SQ_PIX_POP_THREAD_CNT = 152,
+ SQ_PIX_TOTAL = 153,
+ SQ_PIX_KILLED = 154,
+} SQ_PERFCNT_SELECT;
+#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SX_PERFCNT_SELECT_H
+#define ENUMS_SX_PERFCNT_SELECT_H
+typedef enum SX_PERFCNT_SELECT {
+ SX_EXPORT_VECTORS = 0,
+ SX_DUMMY_QUADS  = 1,
+ SX_ALPHA_FAIL = 2,
+ SX_RB_QUAD_BUSY = 3,
+ SX_RB_COLOR_BUSY = 4,
+ SX_RB_QUAD_STALL = 5,
+ SX_RB_COLOR_STALL = 6,
+} SX_PERFCNT_SELECT;
+#endif /*ENUMS_SX_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_Abs_modifier_H
+#define ENUMS_Abs_modifier_H
+typedef enum Abs_modifier {
+ NO_ABS_MOD = 0,
+ ABS_MOD = 1
+} Abs_modifier;
+#endif /*ENUMS_Abs_modifier_H*/
+
+#ifndef ENUMS_Exporting_H
+#define ENUMS_Exporting_H
+typedef enum Exporting {
+ NOT_EXPORTING = 0,
+ EXPORTING = 1
+} Exporting;
+#endif /*ENUMS_Exporting_H*/
+
+#ifndef ENUMS_ScalarOpcode_H
+#define ENUMS_ScalarOpcode_H
+typedef enum ScalarOpcode {
+ ADDs = 0,
+ ADD_PREVs = 1,
+ MULs = 2,
+ MUL_PREVs = 3,
+ MUL_PREV2s = 4,
+ MAXs = 5,
+ MINs = 6,
+ SETEs = 7,
+ SETGTs = 8,
+ SETGTEs = 9,
+ SETNEs = 10,
+ FRACs = 11,
+ TRUNCs = 12,
+ FLOORs = 13,
+ EXP_IEEE = 14,
+ LOG_CLAMP = 15,
+ LOG_IEEE = 16,
+ RECIP_CLAMP = 17,
+ RECIP_FF = 18,
+ RECIP_IEEE = 19,
+ RECIPSQ_CLAMP = 20,
+ RECIPSQ_FF = 21,
+ RECIPSQ_IEEE = 22,
+ MOVAs = 23,
+ MOVA_FLOORs = 24,
+ SUBs = 25,
+ SUB_PREVs = 26,
+ PRED_SETEs = 27,
+ PRED_SETNEs = 28,
+ PRED_SETGTs = 29,
+ PRED_SETGTEs = 30,
+ PRED_SET_INVs = 31,
+ PRED_SET_POPs = 32,
+ PRED_SET_CLRs = 33,
+ PRED_SET_RESTOREs = 34,
+ KILLEs = 35,
+ KILLGTs = 36,
+ KILLGTEs = 37,
+ KILLNEs = 38,
+ KILLONEs = 39,
+ SQRT_IEEE = 40,
+ MUL_CONST_0 = 42,
+ MUL_CONST_1 = 43,
+ ADD_CONST_0 = 44,
+ ADD_CONST_1 = 45,
+ SUB_CONST_0 = 46,
+ SUB_CONST_1 = 47,
+ SIN = 48,
+ COS = 49,
+ RETAIN_PREV = 50,
+} ScalarOpcode;
+#endif /*ENUMS_ScalarOpcode_H*/
+
+#ifndef ENUMS_SwizzleType_H
+#define ENUMS_SwizzleType_H
+typedef enum SwizzleType {
+ NO_SWIZZLE = 0,
+ SHIFT_RIGHT_1 = 1,
+ SHIFT_RIGHT_2 = 2,
+ SHIFT_RIGHT_3 = 3
+} SwizzleType;
+#endif /*ENUMS_SwizzleType_H*/
+
+#ifndef ENUMS_InputModifier_H
+#define ENUMS_InputModifier_H
+typedef enum InputModifier {
+ NIL = 0,
+ NEGATE = 1
+} InputModifier;
+#endif /*ENUMS_InputModifier_H*/
+
+#ifndef ENUMS_PredicateSelect_H
+#define ENUMS_PredicateSelect_H
+typedef enum PredicateSelect {
+ NO_PREDICATION = 0,
+ PREDICATE_QUAD = 1,
+ PREDICATED_2 = 2,
+ PREDICATED_3 = 3
+} PredicateSelect;
+#endif /*ENUMS_PredicateSelect_H*/
+
+#ifndef ENUMS_OperandSelect1_H
+#define ENUMS_OperandSelect1_H
+typedef enum OperandSelect1 {
+ ABSOLUTE_REG = 0,
+ RELATIVE_REG = 1
+} OperandSelect1;
+#endif /*ENUMS_OperandSelect1_H*/
+
+#ifndef ENUMS_VectorOpcode_H
+#define ENUMS_VectorOpcode_H
+typedef enum VectorOpcode {
+ ADDv = 0,
+ MULv = 1,
+ MAXv = 2,
+ MINv = 3,
+ SETEv = 4,
+ SETGTv = 5,
+ SETGTEv = 6,
+ SETNEv = 7,
+ FRACv = 8,
+ TRUNCv = 9,
+ FLOORv = 10,
+ MULADDv = 11,
+ CNDEv = 12,
+ CNDGTEv = 13,
+ CNDGTv = 14,
+ DOT4v = 15,
+ DOT3v = 16,
+ DOT2ADDv = 17,
+ CUBEv = 18,
+ MAX4v = 19,
+ PRED_SETE_PUSHv = 20,
+ PRED_SETNE_PUSHv = 21,
+ PRED_SETGT_PUSHv = 22,
+ PRED_SETGTE_PUSHv = 23,
+ KILLEv = 24,
+ KILLGTv = 25,
+ KILLGTEv = 26,
+ KILLNEv = 27,
+ DSTv = 28,
+ MOVAv = 29,
+} VectorOpcode;
+#endif /*ENUMS_VectorOpcode_H*/
+
+#ifndef ENUMS_OperandSelect0_H
+#define ENUMS_OperandSelect0_H
+typedef enum OperandSelect0 {
+ CONSTANT = 0,
+ NON_CONSTANT = 1
+} OperandSelect0;
+#endif /*ENUMS_OperandSelect0_H*/
+
+#ifndef ENUMS_Ressource_type_H
+#define ENUMS_Ressource_type_H
+typedef enum Ressource_type {
+ ALU = 0,
+ TEXTURE = 1
+} Ressource_type;
+#endif /*ENUMS_Ressource_type_H*/
+
+#ifndef ENUMS_Instruction_serial_H
+#define ENUMS_Instruction_serial_H
+typedef enum Instruction_serial {
+ NOT_SERIAL = 0,
+ SERIAL = 1
+} Instruction_serial;
+#endif /*ENUMS_Instruction_serial_H*/
+
+#ifndef ENUMS_VC_type_H
+#define ENUMS_VC_type_H
+typedef enum VC_type {
+ ALU_TP_REQUEST = 0,
+ VC_REQUEST = 1
+} VC_type;
+#endif /*ENUMS_VC_type_H*/
+
+#ifndef ENUMS_Addressing_H
+#define ENUMS_Addressing_H
+typedef enum Addressing {
+ RELATIVE_ADDR = 0,
+ ABSOLUTE_ADDR = 1
+} Addressing;
+#endif /*ENUMS_Addressing_H*/
+
+#ifndef ENUMS_CFOpcode_H
+#define ENUMS_CFOpcode_H
+typedef enum CFOpcode {
+ NOP = 0,
+ EXECUTE = 1,
+ EXECUTE_END = 2,
+ COND_EXECUTE = 3,
+ COND_EXECUTE_END = 4,
+ COND_PRED_EXECUTE = 5,
+ COND_PRED_EXECUTE_END = 6,
+ LOOP_START = 7,
+ LOOP_END = 8,
+ COND_CALL = 9,
+ RETURN = 10,
+ COND_JMP = 11,
+ ALLOCATE = 12,
+ COND_EXECUTE_PRED_CLEAN = 13,
+ COND_EXECUTE_PRED_CLEAN_END = 14,
+ MARK_VS_FETCH_DONE = 15
+} CFOpcode;
+#endif /*ENUMS_CFOpcode_H*/
+
+#ifndef ENUMS_Allocation_type_H
+#define ENUMS_Allocation_type_H
+typedef enum Allocation_type {
+ SQ_NO_ALLOC = 0,
+ SQ_POSITION = 1,
+ SQ_PARAMETER_PIXEL = 2,
+ SQ_MEMORY = 3
+} Allocation_type;
+#endif /*ENUMS_Allocation_type_H*/
+
+#ifndef ENUMS_TexInstOpcode_H
+#define ENUMS_TexInstOpcode_H
+typedef enum TexInstOpcode {
+ TEX_INST_FETCH = 1,
+ TEX_INST_RESERVED_1 = 2,
+ TEX_INST_RESERVED_2 = 3,
+ TEX_INST_RESERVED_3 = 4,
+ TEX_INST_GET_BORDER_COLOR_FRAC = 16,
+ TEX_INST_GET_COMP_TEX_LOD = 17,
+ TEX_INST_GET_GRADIENTS = 18,
+ TEX_INST_GET_WEIGHTS = 19,
+ TEX_INST_SET_TEX_LOD = 24,
+ TEX_INST_SET_GRADIENTS_H = 25,
+ TEX_INST_SET_GRADIENTS_V = 26,
+ TEX_INST_RESERVED_4 = 27,
+} TexInstOpcode;
+#endif /*ENUMS_TexInstOpcode_H*/
+
+#ifndef ENUMS_Addressmode_H
+#define ENUMS_Addressmode_H
+typedef enum Addressmode {
+ LOGICAL = 0,
+ LOOP_RELATIVE = 1
+} Addressmode;
+#endif /*ENUMS_Addressmode_H*/
+
+#ifndef ENUMS_TexCoordDenorm_H
+#define ENUMS_TexCoordDenorm_H
+typedef enum TexCoordDenorm {
+ TEX_COORD_NORMALIZED = 0,
+ TEX_COORD_UNNORMALIZED = 1
+} TexCoordDenorm;
+#endif /*ENUMS_TexCoordDenorm_H*/
+
+#ifndef ENUMS_SrcSel_H
+#define ENUMS_SrcSel_H
+typedef enum SrcSel {
+ SRC_SEL_X = 0,
+ SRC_SEL_Y = 1,
+ SRC_SEL_Z = 2,
+ SRC_SEL_W = 3
+} SrcSel;
+#endif /*ENUMS_SrcSel_H*/
+
+#ifndef ENUMS_DstSel_H
+#define ENUMS_DstSel_H
+typedef enum DstSel {
+ DST_SEL_X = 0,
+ DST_SEL_Y = 1,
+ DST_SEL_Z = 2,
+ DST_SEL_W = 3,
+ DST_SEL_0 = 4,
+ DST_SEL_1 = 5,
+ DST_SEL_RSVD = 6,
+ DST_SEL_MASK = 7
+} DstSel;
+#endif /*ENUMS_DstSel_H*/
+
+#ifndef ENUMS_MagFilter_H
+#define ENUMS_MagFilter_H
+typedef enum MagFilter {
+ MAG_FILTER_POINT = 0,
+ MAG_FILTER_LINEAR = 1,
+ MAG_FILTER_RESERVED_0 = 2,
+ MAG_FILTER_USE_FETCH_CONST = 3
+} MagFilter;
+#endif /*ENUMS_MagFilter_H*/
+
+#ifndef ENUMS_MinFilter_H
+#define ENUMS_MinFilter_H
+typedef enum MinFilter {
+ MIN_FILTER_POINT = 0,
+ MIN_FILTER_LINEAR = 1,
+ MIN_FILTER_RESERVED_0 = 2,
+ MIN_FILTER_USE_FETCH_CONST = 3
+} MinFilter;
+#endif /*ENUMS_MinFilter_H*/
+
+#ifndef ENUMS_MipFilter_H
+#define ENUMS_MipFilter_H
+typedef enum MipFilter {
+ MIP_FILTER_POINT = 0,
+ MIP_FILTER_LINEAR = 1,
+ MIP_FILTER_BASEMAP = 2,
+ MIP_FILTER_USE_FETCH_CONST = 3
+} MipFilter;
+#endif /*ENUMS_MipFilter_H*/
+
+#ifndef ENUMS_AnisoFilter_H
+#define ENUMS_AnisoFilter_H
+typedef enum AnisoFilter {
+ ANISO_FILTER_DISABLED = 0,
+ ANISO_FILTER_MAX_1_1 = 1,
+ ANISO_FILTER_MAX_2_1 = 2,
+ ANISO_FILTER_MAX_4_1 = 3,
+ ANISO_FILTER_MAX_8_1 = 4,
+ ANISO_FILTER_MAX_16_1 = 5,
+ ANISO_FILTER_USE_FETCH_CONST = 7
+} AnisoFilter;
+#endif /*ENUMS_AnisoFilter_H*/
+
+#ifndef ENUMS_ArbitraryFilter_H
+#define ENUMS_ArbitraryFilter_H
+typedef enum ArbitraryFilter {
+ ARBITRARY_FILTER_2X4_SYM = 0,
+ ARBITRARY_FILTER_2X4_ASYM = 1,
+ ARBITRARY_FILTER_4X2_SYM = 2,
+ ARBITRARY_FILTER_4X2_ASYM = 3,
+ ARBITRARY_FILTER_4X4_SYM = 4,
+ ARBITRARY_FILTER_4X4_ASYM = 5,
+ ARBITRARY_FILTER_USE_FETCH_CONST = 7
+} ArbitraryFilter;
+#endif /*ENUMS_ArbitraryFilter_H*/
+
+#ifndef ENUMS_VolMagFilter_H
+#define ENUMS_VolMagFilter_H
+typedef enum VolMagFilter {
+ VOL_MAG_FILTER_POINT = 0,
+ VOL_MAG_FILTER_LINEAR = 1,
+ VOL_MAG_FILTER_USE_FETCH_CONST = 3
+} VolMagFilter;
+#endif /*ENUMS_VolMagFilter_H*/
+
+#ifndef ENUMS_VolMinFilter_H
+#define ENUMS_VolMinFilter_H
+typedef enum VolMinFilter {
+ VOL_MIN_FILTER_POINT = 0,
+ VOL_MIN_FILTER_LINEAR = 1,
+ VOL_MIN_FILTER_USE_FETCH_CONST = 3
+} VolMinFilter;
+#endif /*ENUMS_VolMinFilter_H*/
+
+#ifndef ENUMS_PredSelect_H
+#define ENUMS_PredSelect_H
+typedef enum PredSelect {
+ NOT_PREDICATED = 0,
+ PREDICATED = 1
+} PredSelect;
+#endif /*ENUMS_PredSelect_H*/
+
+#ifndef ENUMS_SampleLocation_H
+#define ENUMS_SampleLocation_H
+typedef enum SampleLocation {
+ SAMPLE_CENTROID = 0,
+ SAMPLE_CENTER = 1
+} SampleLocation;
+#endif /*ENUMS_SampleLocation_H*/
+
+#ifndef ENUMS_VertexMode_H
+#define ENUMS_VertexMode_H
+typedef enum VertexMode {
+ POSITION_1_VECTOR = 0,
+ POSITION_2_VECTORS_UNUSED = 1,
+ POSITION_2_VECTORS_SPRITE = 2,
+ POSITION_2_VECTORS_EDGE = 3,
+ POSITION_2_VECTORS_KILL = 4,
+ POSITION_2_VECTORS_SPRITE_KILL = 5,
+ POSITION_2_VECTORS_EDGE_KILL = 6,
+ MULTIPASS = 7
+} VertexMode;
+#endif /*ENUMS_VertexMode_H*/
+
+#ifndef ENUMS_Sample_Cntl_H
+#define ENUMS_Sample_Cntl_H
+typedef enum Sample_Cntl {
+ CENTROIDS_ONLY = 0,
+ CENTERS_ONLY = 1,
+ CENTROIDS_AND_CENTERS = 2,
+ UNDEF = 3
+} Sample_Cntl;
+#endif /*ENUMS_Sample_Cntl_H*/
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+#ifndef ENUMS_MhPerfEncode_H
+#define ENUMS_MhPerfEncode_H
+typedef enum MhPerfEncode {
+ CP_R0_REQUESTS = 0,
+ CP_R1_REQUESTS = 1,
+ CP_R2_REQUESTS = 2,
+ CP_R3_REQUESTS = 3,
+ CP_R4_REQUESTS = 4,
+ CP_TOTAL_READ_REQUESTS = 5,
+ CP_TOTAL_WRITE_REQUESTS = 6,
+ CP_TOTAL_REQUESTS = 7,
+ CP_DATA_BYTES_WRITTEN = 8,
+ CP_WRITE_CLEAN_RESPONSES = 9,
+ CP_R0_READ_BURSTS_RECEIVED = 10,
+ CP_R1_READ_BURSTS_RECEIVED = 11,
+ CP_R2_READ_BURSTS_RECEIVED = 12,
+ CP_R3_READ_BURSTS_RECEIVED = 13,
+ CP_R4_READ_BURSTS_RECEIVED = 14,
+ CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+ CP_R0_DATA_BEATS_READ = 16,
+ CP_R1_DATA_BEATS_READ = 17,
+ CP_R2_DATA_BEATS_READ = 18,
+ CP_R3_DATA_BEATS_READ = 19,
+ CP_R4_DATA_BEATS_READ = 20,
+ CP_TOTAL_DATA_BEATS_READ = 21,
+ VGT_R0_REQUESTS = 22,
+ VGT_R1_REQUESTS = 23,
+ VGT_TOTAL_REQUESTS = 24,
+ VGT_R0_READ_BURSTS_RECEIVED = 25,
+ VGT_R1_READ_BURSTS_RECEIVED = 26,
+ VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+ VGT_R0_DATA_BEATS_READ = 28,
+ VGT_R1_DATA_BEATS_READ = 29,
+ VGT_TOTAL_DATA_BEATS_READ = 30,
+ TC_TOTAL_REQUESTS = 31,
+ TC_ROQ_REQUESTS = 32,
+ TC_INFO_SENT = 33,
+ TC_READ_BURSTS_RECEIVED = 34,
+ TC_DATA_BEATS_READ = 35,
+ TCD_BURSTS_READ = 36,
+ RB_REQUESTS = 37,
+ RB_DATA_BYTES_WRITTEN = 38,
+ RB_WRITE_CLEAN_RESPONSES = 39,
+ AXI_READ_REQUESTS_ID_0 = 40,
+ AXI_READ_REQUESTS_ID_1 = 41,
+ AXI_READ_REQUESTS_ID_2 = 42,
+ AXI_READ_REQUESTS_ID_3 = 43,
+ AXI_READ_REQUESTS_ID_4 = 44,
+ AXI_READ_REQUESTS_ID_5 = 45,
+ AXI_READ_REQUESTS_ID_6 = 46,
+ AXI_READ_REQUESTS_ID_7 = 47,
+ AXI_TOTAL_READ_REQUESTS = 48,
+ AXI_WRITE_REQUESTS_ID_0 = 49,
+ AXI_WRITE_REQUESTS_ID_1 = 50,
+ AXI_WRITE_REQUESTS_ID_2 = 51,
+ AXI_WRITE_REQUESTS_ID_3 = 52,
+ AXI_WRITE_REQUESTS_ID_4 = 53,
+ AXI_WRITE_REQUESTS_ID_5 = 54,
+ AXI_WRITE_REQUESTS_ID_6 = 55,
+ AXI_WRITE_REQUESTS_ID_7 = 56,
+ AXI_TOTAL_WRITE_REQUESTS = 57,
+ AXI_TOTAL_REQUESTS_ID_0 = 58,
+ AXI_TOTAL_REQUESTS_ID_1 = 59,
+ AXI_TOTAL_REQUESTS_ID_2 = 60,
+ AXI_TOTAL_REQUESTS_ID_3 = 61,
+ AXI_TOTAL_REQUESTS_ID_4 = 62,
+ AXI_TOTAL_REQUESTS_ID_5 = 63,
+ AXI_TOTAL_REQUESTS_ID_6 = 64,
+ AXI_TOTAL_REQUESTS_ID_7 = 65,
+ AXI_TOTAL_REQUESTS = 66,
+ AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+ AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+ AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+ AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+ AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+ AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+ AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+ AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+ AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+ AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+ AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+ AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+ AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+ AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+ AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+ AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+ AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+ AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+ AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+ AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+ AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+ TOTAL_MMU_MISSES = 112,
+ MMU_READ_MISSES = 113,
+ MMU_WRITE_MISSES = 114,
+ TOTAL_MMU_HITS = 115,
+ MMU_READ_HITS = 116,
+ MMU_WRITE_HITS = 117,
+ SPLIT_MODE_TC_HITS = 118,
+ SPLIT_MODE_TC_MISSES = 119,
+ SPLIT_MODE_NON_TC_HITS = 120,
+ SPLIT_MODE_NON_TC_MISSES = 121,
+ STALL_AWAITING_TLB_MISS_FETCH = 122,
+ MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+ MMU_TLB_MISS_DATA_BEATS_READ = 124,
+ CP_CYCLES_HELD_OFF = 125,
+ VGT_CYCLES_HELD_OFF = 126,
+ TC_CYCLES_HELD_OFF = 127,
+ TC_ROQ_CYCLES_HELD_OFF = 128,
+ TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+ RB_CYCLES_HELD_OFF = 130,
+ TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+ TLB_MISS_CYCLES_HELD_OFF = 132,
+ AXI_READ_REQUEST_HELD_OFF = 133,
+ AXI_WRITE_REQUEST_HELD_OFF = 134,
+ AXI_REQUEST_HELD_OFF = 135,
+ AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+ AXI_WRITE_DATA_HELD_OFF = 137,
+ CP_SAME_PAGE_BANK_REQUESTS = 138,
+ VGT_SAME_PAGE_BANK_REQUESTS = 139,
+ TC_SAME_PAGE_BANK_REQUESTS = 140,
+ TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+ RB_SAME_PAGE_BANK_REQUESTS = 142,
+ TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+ CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+ VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+ TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+ RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+ TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+ TOTAL_MH_READ_REQUESTS = 149,
+ TOTAL_MH_WRITE_REQUESTS = 150,
+ TOTAL_MH_REQUESTS = 151,
+ MH_BUSY = 152,
+ CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+ VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+ TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+ RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+ TC_ROQ_N_VALID_ENTRIES = 157,
+ ARQ_N_ENTRIES = 158,
+ WDB_N_ENTRIES = 159,
+ MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+ MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+ MC_TOTAL_READ_REQUESTS = 162,
+ ELAPSED_CYCLES_MH_GATED_CLK = 163,
+ ELAPSED_CLK_CYCLES = 164,
+ CP_W_16B_REQUESTS = 165,
+ CP_W_32B_REQUESTS = 166,
+ TC_16B_REQUESTS = 167,
+ TC_32B_REQUESTS = 168,
+ PA_REQUESTS = 169,
+ PA_DATA_BYTES_WRITTEN = 170,
+ PA_WRITE_CLEAN_RESPONSES = 171,
+ PA_CYCLES_HELD_OFF = 172,
+ AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
+ AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
+ AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
+ AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
+ AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
+ AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
+ AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
+ AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
+ AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
+} MhPerfEncode;
+#endif /*ENUMS_MhPerfEncode_H*/
+
+#ifndef ENUMS_MmuClntBeh_H
+#define ENUMS_MmuClntBeh_H
+typedef enum MmuClntBeh {
+ BEH_NEVR = 0,
+ BEH_TRAN_RNG = 1,
+ BEH_TRAN_FLT = 2,
+} MmuClntBeh;
+#endif /*ENUMS_MmuClntBeh_H*/
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H
+#define ENUMS_RBBM_PERFCOUNT1_SEL_H
+typedef enum RBBM_PERFCOUNT1_SEL {
+ RBBM1_COUNT = 0,
+ RBBM1_NRT_BUSY = 1,
+ RBBM1_RB_BUSY = 2,
+ RBBM1_SQ_CNTX0_BUSY = 3,
+ RBBM1_SQ_CNTX17_BUSY = 4,
+ RBBM1_VGT_BUSY = 5,
+ RBBM1_VGT_NODMA_BUSY = 6,
+ RBBM1_PA_BUSY = 7,
+ RBBM1_SC_CNTX_BUSY = 8,
+ RBBM1_TPC_BUSY = 9,
+ RBBM1_TC_BUSY = 10,
+ RBBM1_SX_BUSY = 11,
+ RBBM1_CP_COHER_BUSY = 12,
+ RBBM1_CP_NRT_BUSY = 13,
+ RBBM1_GFX_IDLE_STALL = 14,
+ RBBM1_INTERRUPT = 15,
+} RBBM_PERFCOUNT1_SEL;
+#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+#ifndef ENUMS_CP_PERFCOUNT_SEL_H
+#define ENUMS_CP_PERFCOUNT_SEL_H
+typedef enum CP_PERFCOUNT_SEL {
+ ALWAYS_COUNT = 0,
+ TRANS_FIFO_FULL = 1,
+ TRANS_FIFO_AF = 2,
+ RCIU_PFPTRANS_WAIT = 3,
+ Reserved_04 = 4,
+ Reserved_05 = 5,
+ RCIU_NRTTRANS_WAIT = 6,
+ Reserved_07 = 7,
+ CSF_NRT_READ_WAIT = 8,
+ CSF_I1_FIFO_FULL = 9,
+ CSF_I2_FIFO_FULL = 10,
+ CSF_ST_FIFO_FULL = 11,
+ Reserved_12 = 12,
+ CSF_RING_ROQ_FULL = 13,
+ CSF_I1_ROQ_FULL = 14,
+ CSF_I2_ROQ_FULL = 15,
+ CSF_ST_ROQ_FULL = 16,
+ Reserved_17 = 17,
+ MIU_TAG_MEM_FULL = 18,
+ MIU_WRITECLEAN = 19,
+ Reserved_20 = 20,
+ Reserved_21 = 21,
+ MIU_NRT_WRITE_STALLED = 22,
+ MIU_NRT_READ_STALLED = 23,
+ ME_WRITE_CONFIRM_FIFO_FULL = 24,
+ ME_VS_DEALLOC_FIFO_FULL = 25,
+ ME_PS_DEALLOC_FIFO_FULL = 26,
+ ME_REGS_VS_EVENT_FIFO_FULL = 27,
+ ME_REGS_PS_EVENT_FIFO_FULL = 28,
+ ME_REGS_CF_EVENT_FIFO_FULL = 29,
+ ME_MICRO_RB_STARVED = 30,
+ ME_MICRO_I1_STARVED = 31,
+ ME_MICRO_I2_STARVED = 32,
+ ME_MICRO_ST_STARVED = 33,
+ Reserved_34 = 34,
+ Reserved_35 = 35,
+ Reserved_36 = 36,
+ Reserved_37 = 37,
+ Reserved_38 = 38,
+ Reserved_39 = 39,
+ RCIU_RBBM_DWORD_SENT = 40,
+ ME_BUSY_CLOCKS = 41,
+ ME_WAIT_CONTEXT_AVAIL = 42,
+ PFP_TYPE0_PACKET = 43,
+ PFP_TYPE3_PACKET = 44,
+ CSF_RB_WPTR_NEQ_RPTR = 45,
+ CSF_I1_SIZE_NEQ_ZERO = 46,
+ CSF_I2_SIZE_NEQ_ZERO = 47,
+ CSF_RBI1I2_FETCHING = 48,
+ Reserved_49 = 49,
+ Reserved_50 = 50,
+ Reserved_51 = 51,
+ Reserved_52 = 52,
+ Reserved_53 = 53,
+ Reserved_54 = 54,
+ Reserved_55 = 55,
+ Reserved_56 = 56,
+ Reserved_57 = 57,
+ Reserved_58 = 58,
+ Reserved_59 = 59,
+ Reserved_60 = 60,
+ Reserved_61 = 61,
+ Reserved_62 = 62,
+ Reserved_63 = 63
+} CP_PERFCOUNT_SEL;
+#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+#ifndef ENUMS_ColorformatX_H
+#define ENUMS_ColorformatX_H
+typedef enum ColorformatX {
+ COLORX_4_4_4_4 = 0,
+ COLORX_1_5_5_5 = 1,
+ COLORX_5_6_5 = 2,
+ COLORX_8 = 3,
+ COLORX_8_8 = 4,
+ COLORX_8_8_8_8 = 5,
+ COLORX_S8_8_8_8 = 6,
+ COLORX_16_FLOAT = 7,
+ COLORX_16_16_FLOAT = 8,
+ COLORX_16_16_16_16_FLOAT = 9,
+ COLORX_32_FLOAT = 10,
+ COLORX_32_32_FLOAT = 11,
+ COLORX_32_32_32_32_FLOAT = 12,
+ COLORX_2_3_3 = 13,
+ COLORX_8_8_8 = 14,
+} ColorformatX;
+#endif /*ENUMS_ColorformatX_H*/
+
+#ifndef ENUMS_DepthformatX_H
+#define ENUMS_DepthformatX_H
+typedef enum DepthformatX {
+ DEPTHX_16 = 0,
+ DEPTHX_24_8 = 1
+} DepthformatX;
+#endif /*ENUMS_DepthformatX_H*/
+
+#ifndef ENUMS_CompareFrag_H
+#define ENUMS_CompareFrag_H
+typedef enum CompareFrag {
+ FRAG_NEVER = 0,
+ FRAG_LESS = 1,
+ FRAG_EQUAL = 2,
+ FRAG_LEQUAL = 3,
+ FRAG_GREATER = 4,
+ FRAG_NOTEQUAL = 5,
+ FRAG_GEQUAL = 6,
+ FRAG_ALWAYS = 7
+} CompareFrag;
+#endif /*ENUMS_CompareFrag_H*/
+
+#ifndef ENUMS_CompareRef_H
+#define ENUMS_CompareRef_H
+typedef enum CompareRef {
+ REF_NEVER = 0,
+ REF_LESS = 1,
+ REF_EQUAL = 2,
+ REF_LEQUAL = 3,
+ REF_GREATER = 4,
+ REF_NOTEQUAL = 5,
+ REF_GEQUAL = 6,
+ REF_ALWAYS = 7
+} CompareRef;
+#endif /*ENUMS_CompareRef_H*/
+
+#ifndef ENUMS_StencilOp_H
+#define ENUMS_StencilOp_H
+typedef enum StencilOp {
+ STENCIL_KEEP = 0,
+ STENCIL_ZERO = 1,
+ STENCIL_REPLACE = 2,
+ STENCIL_INCR_CLAMP = 3,
+ STENCIL_DECR_CLAMP = 4,
+ STENCIL_INVERT = 5,
+ STENCIL_INCR_WRAP = 6,
+ STENCIL_DECR_WRAP = 7
+} StencilOp;
+#endif /*ENUMS_StencilOp_H*/
+
+#ifndef ENUMS_BlendOpX_H
+#define ENUMS_BlendOpX_H
+typedef enum BlendOpX {
+ BLENDX_ZERO = 0,
+ BLENDX_ONE = 1,
+ BLENDX_SRC_COLOR = 4,
+ BLENDX_ONE_MINUS_SRC_COLOR = 5,
+ BLENDX_SRC_ALPHA = 6,
+ BLENDX_ONE_MINUS_SRC_ALPHA = 7,
+ BLENDX_DST_COLOR = 8,
+ BLENDX_ONE_MINUS_DST_COLOR = 9,
+ BLENDX_DST_ALPHA = 10,
+ BLENDX_ONE_MINUS_DST_ALPHA = 11,
+ BLENDX_CONSTANT_COLOR = 12,
+ BLENDX_ONE_MINUS_CONSTANT_COLOR = 13,
+ BLENDX_CONSTANT_ALPHA = 14,
+ BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15,
+ BLENDX_SRC_ALPHA_SATURATE = 16,
+} BlendOpX;
+#endif /*ENUMS_BlendOpX_H*/
+
+#ifndef ENUMS_CombFuncX_H
+#define ENUMS_CombFuncX_H
+typedef enum CombFuncX {
+ COMB_DST_PLUS_SRC = 0,
+ COMB_SRC_MINUS_DST = 1,
+ COMB_MIN_DST_SRC = 2,
+ COMB_MAX_DST_SRC = 3,
+ COMB_DST_MINUS_SRC = 4,
+ COMB_DST_PLUS_SRC_BIAS = 5,
+} CombFuncX;
+#endif /*ENUMS_CombFuncX_H*/
+
+#ifndef ENUMS_DitherModeX_H
+#define ENUMS_DitherModeX_H
+typedef enum DitherModeX {
+ DITHER_DISABLE = 0,
+ DITHER_ALWAYS = 1,
+ DITHER_IF_ALPHA_OFF = 2,
+} DitherModeX;
+#endif /*ENUMS_DitherModeX_H*/
+
+#ifndef ENUMS_DitherTypeX_H
+#define ENUMS_DitherTypeX_H
+typedef enum DitherTypeX {
+ DITHER_PIXEL = 0,
+ DITHER_SUBPIXEL = 1,
+} DitherTypeX;
+#endif /*ENUMS_DitherTypeX_H*/
+
+#ifndef ENUMS_EdramMode_H
+#define ENUMS_EdramMode_H
+typedef enum EdramMode {
+ EDRAM_NOP = 0,
+ COLOR_DEPTH = 4,
+ DEPTH_ONLY = 5,
+ EDRAM_COPY = 6,
+} EdramMode;
+#endif /*ENUMS_EdramMode_H*/
+
+#ifndef ENUMS_SurfaceEndian_H
+#define ENUMS_SurfaceEndian_H
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0,
+ ENDIAN_8IN16 = 1,
+ ENDIAN_8IN32 = 2,
+ ENDIAN_16IN32 = 3,
+ ENDIAN_8IN64 = 4,
+ ENDIAN_8IN128 = 5,
+} SurfaceEndian;
+#endif /*ENUMS_SurfaceEndian_H*/
+
+#ifndef ENUMS_EdramSizeX_H
+#define ENUMS_EdramSizeX_H
+typedef enum EdramSizeX {
+ EDRAMSIZE_16KB = 0,
+ EDRAMSIZE_32KB = 1,
+ EDRAMSIZE_64KB = 2,
+ EDRAMSIZE_128KB = 3,
+ EDRAMSIZE_256KB = 4,
+ EDRAMSIZE_512KB = 5,
+ EDRAMSIZE_1MB = 6,
+ EDRAMSIZE_2MB = 7,
+ EDRAMSIZE_4MB = 8,
+ EDRAMSIZE_8MB = 9,
+ EDRAMSIZE_16MB = 10,
+} EdramSizeX;
+#endif /*ENUMS_EdramSizeX_H*/
+
+#ifndef ENUMS_RB_PERFCNT_SELECT_H
+#define ENUMS_RB_PERFCNT_SELECT_H
+typedef enum RB_PERFCNT_SELECT {
+ RBPERF_CNTX_BUSY = 0,
+ RBPERF_CNTX_BUSY_MAX = 1,
+ RBPERF_SX_QUAD_STARVED = 2,
+ RBPERF_SX_QUAD_STARVED_MAX = 3,
+ RBPERF_GA_GC_CH0_SYS_REQ = 4,
+ RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+ RBPERF_GA_GC_CH1_SYS_REQ = 6,
+ RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+ RBPERF_MH_STARVED = 8,
+ RBPERF_MH_STARVED_MAX = 9,
+ RBPERF_AZ_BC_COLOR_BUSY = 10,
+ RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+ RBPERF_AZ_BC_Z_BUSY = 12,
+ RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+ RBPERF_RB_SC_TILE_RTR_N = 14,
+ RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+ RBPERF_RB_SC_SAMP_RTR_N = 16,
+ RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+ RBPERF_RB_SX_QUAD_RTR_N = 18,
+ RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+ RBPERF_RB_SX_COLOR_RTR_N = 20,
+ RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+ RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+ RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+ RBPERF_ZXP_STALL = 24,
+ RBPERF_ZXP_STALL_MAX = 25,
+ RBPERF_EVENT_PENDING = 26,
+ RBPERF_EVENT_PENDING_MAX = 27,
+ RBPERF_RB_MH_VALID = 28,
+ RBPERF_RB_MH_VALID_MAX = 29,
+ RBPERF_SX_RB_QUAD_SEND = 30,
+ RBPERF_SX_RB_COLOR_SEND = 31,
+ RBPERF_SC_RB_TILE_SEND = 32,
+ RBPERF_SC_RB_SAMPLE_SEND = 33,
+ RBPERF_SX_RB_MEM_EXPORT = 34,
+ RBPERF_SX_RB_QUAD_EVENT = 35,
+ RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+ RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+ RBPERF_RB_SC_EZ_SEND = 38,
+ RBPERF_RB_SX_INDEX_SEND = 39,
+ RBPERF_GMEM_INTFO_RD = 40,
+ RBPERF_GMEM_INTF1_RD = 41,
+ RBPERF_GMEM_INTFO_WR = 42,
+ RBPERF_GMEM_INTF1_WR = 43,
+ RBPERF_RB_CP_CONTEXT_DONE = 44,
+ RBPERF_RB_CP_CACHE_FLUSH = 45,
+ RBPERF_ZPASS_DONE = 46,
+ RBPERF_ZCMD_VALID = 47,
+ RBPERF_CCMD_VALID = 48,
+ RBPERF_ACCUM_GRANT = 49,
+ RBPERF_ACCUM_C0_GRANT = 50,
+ RBPERF_ACCUM_C1_GRANT = 51,
+ RBPERF_ACCUM_FULL_BE_WR = 52,
+ RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+ RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+ RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+ RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+} RB_PERFCNT_SELECT;
+#endif /*ENUMS_RB_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_DepthFormat_H
+#define ENUMS_DepthFormat_H
+typedef enum DepthFormat {
+ DEPTH_24_8 = 22,
+ DEPTH_24_8_FLOAT = 23,
+ DEPTH_16 = 24,
+} DepthFormat;
+#endif /*ENUMS_DepthFormat_H*/
+
+#ifndef ENUMS_SurfaceSwap_H
+#define ENUMS_SurfaceSwap_H
+typedef enum SurfaceSwap {
+ SWAP_LOWRED = 0,
+ SWAP_LOWBLUE = 1
+} SurfaceSwap;
+#endif /*ENUMS_SurfaceSwap_H*/
+
+#ifndef ENUMS_DepthArray_H
+#define ENUMS_DepthArray_H
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0,
+ ARRAY_2D_DEPTH = 1,
+} DepthArray;
+#endif /*ENUMS_DepthArray_H*/
+
+#ifndef ENUMS_ColorArray_H
+#define ENUMS_ColorArray_H
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0,
+ ARRAY_2D_COLOR = 1,
+ ARRAY_3D_SLICE_COLOR = 3
+} ColorArray;
+#endif /*ENUMS_ColorArray_H*/
+
+#ifndef ENUMS_ColorFormat_H
+#define ENUMS_ColorFormat_H
+typedef enum ColorFormat {
+ COLOR_8 = 2,
+ COLOR_1_5_5_5 = 3,
+ COLOR_5_6_5 = 4,
+ COLOR_6_5_5 = 5,
+ COLOR_8_8_8_8 = 6,
+ COLOR_2_10_10_10 = 7,
+ COLOR_8_A = 8,
+ COLOR_8_B = 9,
+ COLOR_8_8 = 10,
+ COLOR_8_8_8 = 11,
+ COLOR_8_8_8_8_A = 14,
+ COLOR_4_4_4_4 = 15,
+ COLOR_10_11_11 = 16,
+ COLOR_11_11_10 = 17,
+ COLOR_16 = 24,
+ COLOR_16_16 = 25,
+ COLOR_16_16_16_16 = 26,
+ COLOR_16_FLOAT = 30,
+ COLOR_16_16_FLOAT = 31,
+ COLOR_16_16_16_16_FLOAT = 32,
+ COLOR_32_FLOAT = 36,
+ COLOR_32_32_FLOAT = 37,
+ COLOR_32_32_32_32_FLOAT = 38,
+ COLOR_2_3_3 = 39,
+} ColorFormat;
+#endif /*ENUMS_ColorFormat_H*/
+
+#ifndef ENUMS_SurfaceNumber_H
+#define ENUMS_SurfaceNumber_H
+typedef enum SurfaceNumber {
+ NUMBER_UREPEAT = 0,
+ NUMBER_SREPEAT = 1,
+ NUMBER_UINTEGER = 2,
+ NUMBER_SINTEGER = 3,
+ NUMBER_GAMMA = 4,
+ NUMBER_FIXED = 5,
+ NUMBER_FLOAT = 7
+} SurfaceNumber;
+#endif /*ENUMS_SurfaceNumber_H*/
+
+#ifndef ENUMS_SurfaceFormat_H
+#define ENUMS_SurfaceFormat_H
+typedef enum SurfaceFormat {
+ FMT_1_REVERSE = 0,
+ FMT_1 = 1,
+ FMT_8 = 2,
+ FMT_1_5_5_5 = 3,
+ FMT_5_6_5 = 4,
+ FMT_6_5_5 = 5,
+ FMT_8_8_8_8 = 6,
+ FMT_2_10_10_10 = 7,
+ FMT_8_A = 8,
+ FMT_8_B = 9,
+ FMT_8_8 = 10,
+ FMT_Cr_Y1_Cb_Y0 = 11,
+ FMT_Y1_Cr_Y0_Cb = 12,
+ FMT_5_5_5_1 = 13,
+ FMT_8_8_8_8_A = 14,
+ FMT_4_4_4_4 = 15,
+ FMT_8_8_8 = 16,
+ FMT_DXT1 = 18,
+ FMT_DXT2_3 = 19,
+ FMT_DXT4_5 = 20,
+ FMT_10_10_10_2 = 21,
+ FMT_24_8 = 22,
+ FMT_16 = 24,
+ FMT_16_16 = 25,
+ FMT_16_16_16_16 = 26,
+ FMT_16_EXPAND = 27,
+ FMT_16_16_EXPAND = 28,
+ FMT_16_16_16_16_EXPAND = 29,
+ FMT_16_FLOAT = 30,
+ FMT_16_16_FLOAT = 31,
+ FMT_16_16_16_16_FLOAT = 32,
+ FMT_32 = 33,
+ FMT_32_32 = 34,
+ FMT_32_32_32_32 = 35,
+ FMT_32_FLOAT = 36,
+ FMT_32_32_FLOAT = 37,
+ FMT_32_32_32_32_FLOAT = 38,
+ FMT_ATI_TC_RGB = 39,
+ FMT_ATI_TC_RGBA = 40,
+ FMT_ATI_TC_555_565_RGB = 41,
+ FMT_ATI_TC_555_565_RGBA = 42,
+ FMT_ATI_TC_RGBA_INTERP = 43,
+ FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+ FMT_ETC1_RGBA_INTERP = 46,
+ FMT_ETC1_RGB = 47,
+ FMT_ETC1_RGBA = 48,
+ FMT_DXN = 49,
+ FMT_2_3_3 = 51,
+ FMT_2_10_10_10_AS_16_16_16_16 = 54,
+ FMT_10_10_10_2_AS_16_16_16_16 = 55,
+ FMT_32_32_32_FLOAT = 57,
+ FMT_DXT3A = 58,
+ FMT_DXT5A = 59,
+ FMT_CTX1 = 60,
+} SurfaceFormat;
+#endif /*ENUMS_SurfaceFormat_H*/
+
+#ifndef ENUMS_SurfaceTiling_H
+#define ENUMS_SurfaceTiling_H
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0,
+ ARRAY_TILED = 1
+} SurfaceTiling;
+#endif /*ENUMS_SurfaceTiling_H*/
+
+#ifndef ENUMS_SurfaceArray_H
+#define ENUMS_SurfaceArray_H
+typedef enum SurfaceArray {
+ ARRAY_1D = 0,
+ ARRAY_2D = 1,
+ ARRAY_3D = 2,
+ ARRAY_3D_SLICE = 3
+} SurfaceArray;
+#endif /*ENUMS_SurfaceArray_H*/
+
+#ifndef ENUMS_SurfaceNumberX_H
+#define ENUMS_SurfaceNumberX_H
+typedef enum SurfaceNumberX {
+ NUMBERX_UREPEAT = 0,
+ NUMBERX_SREPEAT = 1,
+ NUMBERX_UINTEGER = 2,
+ NUMBERX_SINTEGER = 3,
+ NUMBERX_FLOAT = 7
+} SurfaceNumberX;
+#endif /*ENUMS_SurfaceNumberX_H*/
+
+#ifndef ENUMS_ColorArrayX_H
+#define ENUMS_ColorArrayX_H
+typedef enum ColorArrayX {
+ ARRAYX_2D_COLOR = 0,
+ ARRAYX_3D_SLICE_COLOR = 1,
+} ColorArrayX;
+#endif /*ENUMS_ColorArrayX_H*/
+
+#endif /*_yamato_ENUM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h
new file mode 100644
index 00000000000..87a454a1e38
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h
@@ -0,0 +1,1703 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_ENUMTYPE(SU_PERFCNT_SELECT)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0)
+    GENERATE_ENUM(UNUSED1, 1)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13)
+    GENERATE_ENUM(UNUSED2, 14)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15)
+    GENERATE_ENUM(UNUSED3, 16)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19)
+    GENERATE_ENUM(UNUSED4, 20)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21)
+    GENERATE_ENUM(UNUSED5, 22)
+    GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36)
+    GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49)
+    GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50)
+    GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51)
+    GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95)
+    GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96)
+    GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97)
+    GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98)
+    GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99)
+    GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100)
+    GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101)
+    GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102)
+END_ENUMTYPE(SU_PERFCNT_SELECT)
+
+START_ENUMTYPE(SC_PERFCNT_SELECT)
+    GENERATE_ENUM(SC_SR_WINDOW_VALID, 0)
+    GENERATE_ENUM(SC_CW_WINDOW_VALID, 1)
+    GENERATE_ENUM(SC_QM_WINDOW_VALID, 2)
+    GENERATE_ENUM(SC_FW_WINDOW_VALID, 3)
+    GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4)
+    GENERATE_ENUM(SC_IT_WINDOW_VALID, 5)
+    GENERATE_ENUM(SC_STARVED_BY_PA, 6)
+    GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7)
+    GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8)
+    GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9)
+    GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10)
+    GENERATE_ENUM(SC_STALLED_BY_SQ, 11)
+    GENERATE_ENUM(SC_STALLED_BY_SP, 12)
+    GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13)
+    GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14)
+    GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15)
+    GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16)
+    GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17)
+END_ENUMTYPE(SC_PERFCNT_SELECT)
+
+START_ENUMTYPE(VGT_DI_PRIM_TYPE)
+    GENERATE_ENUM(DI_PT_NONE, 0)
+    GENERATE_ENUM(DI_PT_POINTLIST, 1)
+    GENERATE_ENUM(DI_PT_LINELIST, 2)
+    GENERATE_ENUM(DI_PT_LINESTRIP, 3)
+    GENERATE_ENUM(DI_PT_TRILIST, 4)
+    GENERATE_ENUM(DI_PT_TRIFAN, 5)
+    GENERATE_ENUM(DI_PT_TRISTRIP, 6)
+    GENERATE_ENUM(DI_PT_UNUSED_1, 7)
+    GENERATE_ENUM(DI_PT_RECTLIST, 8)
+    GENERATE_ENUM(DI_PT_UNUSED_2, 9)
+    GENERATE_ENUM(DI_PT_UNUSED_3, 10)
+    GENERATE_ENUM(DI_PT_UNUSED_4, 11)
+    GENERATE_ENUM(DI_PT_UNUSED_5, 12)
+    GENERATE_ENUM(DI_PT_QUADLIST, 13)
+    GENERATE_ENUM(DI_PT_QUADSTRIP, 14)
+    GENERATE_ENUM(DI_PT_POLYGON, 15)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19)
+    GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20)
+    GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21)
+    GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22)
+END_ENUMTYPE(VGT_DI_PRIM_TYPE)
+
+START_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+    GENERATE_ENUM(DI_SRC_SEL_DMA, 0)
+    GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1)
+    GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2)
+    GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3)
+END_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+
+START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_ENUM(DI_FACE_CULL_NONE, 0)
+    GENERATE_ENUM(DI_FACE_CULL_FETCH, 1)
+    GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2)
+    GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3)
+END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+
+START_ENUMTYPE(VGT_DI_INDEX_SIZE)
+    GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1)
+END_ENUMTYPE(VGT_DI_INDEX_SIZE)
+
+START_ENUMTYPE(VGT_DI_SMALL_INDEX)
+    GENERATE_ENUM(DI_USE_INDEX_SIZE, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1)
+END_ENUMTYPE(VGT_DI_SMALL_INDEX)
+
+START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0)
+    GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0)
+    GENERATE_ENUM(GRP_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_EVENT_TYPE)
+    GENERATE_ENUM(VS_DEALLOC, 0)
+    GENERATE_ENUM(PS_DEALLOC, 1)
+    GENERATE_ENUM(VS_DONE_TS, 2)
+    GENERATE_ENUM(PS_DONE_TS, 3)
+    GENERATE_ENUM(CACHE_FLUSH_TS, 4)
+    GENERATE_ENUM(CONTEXT_DONE, 5)
+    GENERATE_ENUM(CACHE_FLUSH, 6)
+    GENERATE_ENUM(VIZQUERY_START, 7)
+    GENERATE_ENUM(VIZQUERY_END, 8)
+    GENERATE_ENUM(SC_WAIT_WC, 9)
+    GENERATE_ENUM(RST_PIX_CNT, 13)
+    GENERATE_ENUM(RST_VTX_CNT, 14)
+    GENERATE_ENUM(TILE_FLUSH, 15)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20)
+    GENERATE_ENUM(ZPASS_DONE, 21)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22)
+    GENERATE_ENUM(PERFCOUNTER_START, 23)
+    GENERATE_ENUM(PERFCOUNTER_STOP, 24)
+    GENERATE_ENUM(VS_FETCH_DONE, 27)
+    GENERATE_ENUM(FACENESS_FLUSH, 28)
+END_ENUMTYPE(VGT_EVENT_TYPE)
+
+START_ENUMTYPE(VGT_DMA_SWAP_MODE)
+    GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0)
+    GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1)
+    GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2)
+    GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3)
+END_ENUMTYPE(VGT_DMA_SWAP_MODE)
+
+START_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0)
+    GENERATE_ENUM(VGT_SQ_SEND, 1)
+    GENERATE_ENUM(VGT_SQ_STALLED, 2)
+    GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3)
+    GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4)
+    GENERATE_ENUM(VGT_SQ_STATIC, 5)
+    GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6)
+    GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11)
+    GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16)
+    GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21)
+    GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28)
+    GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29)
+    GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30)
+    GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31)
+    GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32)
+    GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33)
+    GENERATE_ENUM(SPARE34, 34)
+    GENERATE_ENUM(SPARE35, 35)
+    GENERATE_ENUM(SPARE36, 36)
+    GENERATE_ENUM(SPARE37, 37)
+    GENERATE_ENUM(SPARE38, 38)
+    GENERATE_ENUM(SPARE39, 39)
+    GENERATE_ENUM(TE_SU_IN_VALID, 40)
+    GENERATE_ENUM(TE_SU_IN_READ, 41)
+    GENERATE_ENUM(TE_SU_IN_PRIM, 42)
+    GENERATE_ENUM(TE_SU_IN_EOP, 43)
+    GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44)
+    GENERATE_ENUM(TE_WK_IN_VALID, 45)
+    GENERATE_ENUM(TE_WK_IN_READ, 46)
+    GENERATE_ENUM(TE_OUT_PRIM_VALID, 47)
+    GENERATE_ENUM(TE_OUT_PRIM_READ, 48)
+END_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+    GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0)
+    GENERATE_ENUM(reserved_46, 1)
+    GENERATE_ENUM(reserved_47, 2)
+    GENERATE_ENUM(reserved_48, 3)
+    GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4)
+    GENERATE_ENUM(OPMUX0_L2_WRITES, 5)
+    GENERATE_ENUM(reserved_49, 6)
+    GENERATE_ENUM(reserved_50, 7)
+    GENERATE_ENUM(reserved_51, 8)
+END_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TP_PERFCOUNT_SELECT)
+    GENERATE_ENUM(POINT_QUADS, 0)
+    GENERATE_ENUM(BILIN_QUADS, 1)
+    GENERATE_ENUM(ANISO_QUADS, 2)
+    GENERATE_ENUM(MIP_QUADS, 3)
+    GENERATE_ENUM(VOL_QUADS, 4)
+    GENERATE_ENUM(MIP_VOL_QUADS, 5)
+    GENERATE_ENUM(MIP_ANISO_QUADS, 6)
+    GENERATE_ENUM(VOL_ANISO_QUADS, 7)
+    GENERATE_ENUM(ANISO_2_1_QUADS, 8)
+    GENERATE_ENUM(ANISO_4_1_QUADS, 9)
+    GENERATE_ENUM(ANISO_6_1_QUADS, 10)
+    GENERATE_ENUM(ANISO_8_1_QUADS, 11)
+    GENERATE_ENUM(ANISO_10_1_QUADS, 12)
+    GENERATE_ENUM(ANISO_12_1_QUADS, 13)
+    GENERATE_ENUM(ANISO_14_1_QUADS, 14)
+    GENERATE_ENUM(ANISO_16_1_QUADS, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16)
+    GENERATE_ENUM(ALIGN_2_QUADS, 17)
+    GENERATE_ENUM(ALIGN_4_QUADS, 18)
+    GENERATE_ENUM(PIX_0_QUAD, 19)
+    GENERATE_ENUM(PIX_1_QUAD, 20)
+    GENERATE_ENUM(PIX_2_QUAD, 21)
+    GENERATE_ENUM(PIX_3_QUAD, 22)
+    GENERATE_ENUM(PIX_4_QUAD, 23)
+    GENERATE_ENUM(TP_MIPMAP_LOD0, 24)
+    GENERATE_ENUM(TP_MIPMAP_LOD1, 25)
+    GENERATE_ENUM(TP_MIPMAP_LOD2, 26)
+    GENERATE_ENUM(TP_MIPMAP_LOD3, 27)
+    GENERATE_ENUM(TP_MIPMAP_LOD4, 28)
+    GENERATE_ENUM(TP_MIPMAP_LOD5, 29)
+    GENERATE_ENUM(TP_MIPMAP_LOD6, 30)
+    GENERATE_ENUM(TP_MIPMAP_LOD7, 31)
+    GENERATE_ENUM(TP_MIPMAP_LOD8, 32)
+    GENERATE_ENUM(TP_MIPMAP_LOD9, 33)
+    GENERATE_ENUM(TP_MIPMAP_LOD10, 34)
+    GENERATE_ENUM(TP_MIPMAP_LOD11, 35)
+    GENERATE_ENUM(TP_MIPMAP_LOD12, 36)
+    GENERATE_ENUM(TP_MIPMAP_LOD13, 37)
+    GENERATE_ENUM(TP_MIPMAP_LOD14, 38)
+END_ENUMTYPE(TP_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0)
+    GENERATE_ENUM(reserved_01, 1)
+    GENERATE_ENUM(reserved_02, 2)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6)
+    GENERATE_ENUM(reserved_07, 7)
+    GENERATE_ENUM(reserved_08, 8)
+    GENERATE_ENUM(reserved_09, 9)
+    GENERATE_ENUM(reserved_10, 10)
+    GENERATE_ENUM(reserved_11, 11)
+    GENERATE_ENUM(reserved_12, 12)
+    GENERATE_ENUM(reserved_13, 13)
+    GENERATE_ENUM(reserved_14, 14)
+    GENERATE_ENUM(reserved_15, 15)
+    GENERATE_ENUM(reserved_16, 16)
+    GENERATE_ENUM(reserved_17, 17)
+    GENERATE_ENUM(reserved_18, 18)
+    GENERATE_ENUM(reserved_19, 19)
+    GENERATE_ENUM(reserved_20, 20)
+    GENERATE_ENUM(reserved_21, 21)
+    GENERATE_ENUM(reserved_22, 22)
+    GENERATE_ENUM(reserved_23, 23)
+    GENERATE_ENUM(reserved_24, 24)
+    GENERATE_ENUM(reserved_25, 25)
+    GENERATE_ENUM(reserved_26, 26)
+    GENERATE_ENUM(reserved_27, 27)
+    GENERATE_ENUM(READ_STARVED_QUAD0, 28)
+    GENERATE_ENUM(reserved_29, 29)
+    GENERATE_ENUM(reserved_30, 30)
+    GENERATE_ENUM(reserved_31, 31)
+    GENERATE_ENUM(READ_STARVED, 32)
+    GENERATE_ENUM(READ_STALLED_QUAD0, 33)
+    GENERATE_ENUM(reserved_34, 34)
+    GENERATE_ENUM(reserved_35, 35)
+    GENERATE_ENUM(reserved_36, 36)
+    GENERATE_ENUM(READ_STALLED, 37)
+    GENERATE_ENUM(VALID_READ_QUAD0, 38)
+    GENERATE_ENUM(reserved_39, 39)
+    GENERATE_ENUM(reserved_40, 40)
+    GENERATE_ENUM(reserved_41, 41)
+    GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42)
+    GENERATE_ENUM(reserved_43, 43)
+    GENERATE_ENUM(reserved_44, 44)
+    GENERATE_ENUM(reserved_45, 45)
+    GENERATE_ENUM(TC_TP_STARVED, 46)
+END_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VALID_CYCLES, 0)
+    GENERATE_ENUM(SINGLE_PHASES, 1)
+    GENERATE_ENUM(ANISO_PHASES, 2)
+    GENERATE_ENUM(MIP_PHASES, 3)
+    GENERATE_ENUM(VOL_PHASES, 4)
+    GENERATE_ENUM(MIP_VOL_PHASES, 5)
+    GENERATE_ENUM(MIP_ANISO_PHASES, 6)
+    GENERATE_ENUM(VOL_ANISO_PHASES, 7)
+    GENERATE_ENUM(ANISO_2_1_PHASES, 8)
+    GENERATE_ENUM(ANISO_4_1_PHASES, 9)
+    GENERATE_ENUM(ANISO_6_1_PHASES, 10)
+    GENERATE_ENUM(ANISO_8_1_PHASES, 11)
+    GENERATE_ENUM(ANISO_10_1_PHASES, 12)
+    GENERATE_ENUM(ANISO_12_1_PHASES, 13)
+    GENERATE_ENUM(ANISO_14_1_PHASES, 14)
+    GENERATE_ENUM(ANISO_16_1_PHASES, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16)
+    GENERATE_ENUM(ALIGN_2_PHASES, 17)
+    GENERATE_ENUM(ALIGN_4_PHASES, 18)
+    GENERATE_ENUM(TPC_BUSY, 19)
+    GENERATE_ENUM(TPC_STALLED, 20)
+    GENERATE_ENUM(TPC_STARVED, 21)
+    GENERATE_ENUM(TPC_WORKING, 22)
+    GENERATE_ENUM(TPC_WALKER_BUSY, 23)
+    GENERATE_ENUM(TPC_WALKER_STALLED, 24)
+    GENERATE_ENUM(TPC_WALKER_WORKING, 25)
+    GENERATE_ENUM(TPC_ALIGNER_BUSY, 26)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED, 27)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29)
+    GENERATE_ENUM(TPC_ALIGNER_WORKING, 30)
+    GENERATE_ENUM(TPC_BLEND_BUSY, 31)
+    GENERATE_ENUM(TPC_BLEND_SYNC, 32)
+    GENERATE_ENUM(TPC_BLEND_STARVED, 33)
+    GENERATE_ENUM(TPC_BLEND_WORKING, 34)
+    GENERATE_ENUM(OPCODE_0x00, 35)
+    GENERATE_ENUM(OPCODE_0x01, 36)
+    GENERATE_ENUM(OPCODE_0x04, 37)
+    GENERATE_ENUM(OPCODE_0x10, 38)
+    GENERATE_ENUM(OPCODE_0x11, 39)
+    GENERATE_ENUM(OPCODE_0x12, 40)
+    GENERATE_ENUM(OPCODE_0x13, 41)
+    GENERATE_ENUM(OPCODE_0x18, 42)
+    GENERATE_ENUM(OPCODE_0x19, 43)
+    GENERATE_ENUM(OPCODE_0x1A, 44)
+    GENERATE_ENUM(OPCODE_OTHER, 45)
+    GENERATE_ENUM(IN_FIFO_0_EMPTY, 56)
+    GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57)
+    GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58)
+    GENERATE_ENUM(IN_FIFO_0_FULL, 59)
+    GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72)
+    GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73)
+    GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74)
+    GENERATE_ENUM(IN_FIFO_TPC_FULL, 75)
+    GENERATE_ENUM(TPC_TC_XFC, 76)
+    GENERATE_ENUM(TPC_TC_STATE, 77)
+    GENERATE_ENUM(TC_STALL, 78)
+    GENERATE_ENUM(QUAD0_TAPS, 79)
+    GENERATE_ENUM(QUADS, 83)
+    GENERATE_ENUM(TCA_SYNC_STALL, 84)
+    GENERATE_ENUM(TAG_STALL, 85)
+    GENERATE_ENUM(TCB_SYNC_STALL, 88)
+    GENERATE_ENUM(TCA_VALID, 89)
+    GENERATE_ENUM(PROBES_VALID, 90)
+    GENERATE_ENUM(MISS_STALL, 91)
+    GENERATE_ENUM(FETCH_FIFO_STALL, 92)
+    GENERATE_ENUM(TCO_STALL, 93)
+    GENERATE_ENUM(ANY_STALL, 94)
+    GENERATE_ENUM(TAG_MISSES, 95)
+    GENERATE_ENUM(TAG_HITS, 96)
+    GENERATE_ENUM(SUB_TAG_MISSES, 97)
+    GENERATE_ENUM(SET0_INVALIDATES, 98)
+    GENERATE_ENUM(SET1_INVALIDATES, 99)
+    GENERATE_ENUM(SET2_INVALIDATES, 100)
+    GENERATE_ENUM(SET3_INVALIDATES, 101)
+    GENERATE_ENUM(SET0_TAG_MISSES, 102)
+    GENERATE_ENUM(SET1_TAG_MISSES, 103)
+    GENERATE_ENUM(SET2_TAG_MISSES, 104)
+    GENERATE_ENUM(SET3_TAG_MISSES, 105)
+    GENERATE_ENUM(SET0_TAG_HITS, 106)
+    GENERATE_ENUM(SET1_TAG_HITS, 107)
+    GENERATE_ENUM(SET2_TAG_HITS, 108)
+    GENERATE_ENUM(SET3_TAG_HITS, 109)
+    GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110)
+    GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111)
+    GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112)
+    GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113)
+    GENERATE_ENUM(SET0_EVICT1, 114)
+    GENERATE_ENUM(SET0_EVICT2, 115)
+    GENERATE_ENUM(SET0_EVICT3, 116)
+    GENERATE_ENUM(SET0_EVICT4, 117)
+    GENERATE_ENUM(SET0_EVICT5, 118)
+    GENERATE_ENUM(SET0_EVICT6, 119)
+    GENERATE_ENUM(SET0_EVICT7, 120)
+    GENERATE_ENUM(SET0_EVICT8, 121)
+    GENERATE_ENUM(SET1_EVICT1, 130)
+    GENERATE_ENUM(SET1_EVICT2, 131)
+    GENERATE_ENUM(SET1_EVICT3, 132)
+    GENERATE_ENUM(SET1_EVICT4, 133)
+    GENERATE_ENUM(SET1_EVICT5, 134)
+    GENERATE_ENUM(SET1_EVICT6, 135)
+    GENERATE_ENUM(SET1_EVICT7, 136)
+    GENERATE_ENUM(SET1_EVICT8, 137)
+    GENERATE_ENUM(SET2_EVICT1, 146)
+    GENERATE_ENUM(SET2_EVICT2, 147)
+    GENERATE_ENUM(SET2_EVICT3, 148)
+    GENERATE_ENUM(SET2_EVICT4, 149)
+    GENERATE_ENUM(SET2_EVICT5, 150)
+    GENERATE_ENUM(SET2_EVICT6, 151)
+    GENERATE_ENUM(SET2_EVICT7, 152)
+    GENERATE_ENUM(SET2_EVICT8, 153)
+    GENERATE_ENUM(SET3_EVICT1, 162)
+    GENERATE_ENUM(SET3_EVICT2, 163)
+    GENERATE_ENUM(SET3_EVICT3, 164)
+    GENERATE_ENUM(SET3_EVICT4, 165)
+    GENERATE_ENUM(SET3_EVICT5, 166)
+    GENERATE_ENUM(SET3_EVICT6, 167)
+    GENERATE_ENUM(SET3_EVICT7, 168)
+    GENERATE_ENUM(SET3_EVICT8, 169)
+    GENERATE_ENUM(FF_EMPTY, 178)
+    GENERATE_ENUM(FF_LT_HALF_FULL, 179)
+    GENERATE_ENUM(FF_HALF_FULL, 180)
+    GENERATE_ENUM(FF_FULL, 181)
+    GENERATE_ENUM(FF_XFC, 182)
+    GENERATE_ENUM(FF_STALLED, 183)
+    GENERATE_ENUM(FG_MASKS, 184)
+    GENERATE_ENUM(FG_LEFT_MASKS, 185)
+    GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186)
+    GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187)
+    GENERATE_ENUM(FG_LEFT_FG_STALL, 188)
+    GENERATE_ENUM(FG_LEFT_SECTORS, 189)
+    GENERATE_ENUM(FG0_REQUESTS, 195)
+    GENERATE_ENUM(FG0_STALLED, 196)
+    GENERATE_ENUM(MEM_REQ512, 199)
+    GENERATE_ENUM(MEM_REQ_SENT, 200)
+    GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202)
+    GENERATE_ENUM(TC0_MH_STALLED, 203)
+END_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(SQ_PERFCNT_SELECT)
+    GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0)
+    GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9)
+    GENERATE_ENUM(SQ_EXPORT_CYCLES, 10)
+    GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11)
+    GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12)
+    GENERATE_ENUM(SQ_ALU_CST_STALL, 13)
+    GENERATE_ENUM(SQ_ALU_TEX_STALL, 14)
+    GENERATE_ENUM(SQ_INST_WRITTEN, 15)
+    GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16)
+    GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21)
+    GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22)
+    GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23)
+    GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24)
+    GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25)
+    GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26)
+    GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27)
+    GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28)
+    GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33)
+    GENERATE_ENUM(SQ_ALU_NOPS, 34)
+    GENERATE_ENUM(SQ_PRED_SKIP, 35)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41)
+    GENERATE_ENUM(SQ_GPR_STALL_VTX, 42)
+    GENERATE_ENUM(SQ_GPR_STALL_PIX, 43)
+    GENERATE_ENUM(SQ_VTX_RS_STALL, 44)
+    GENERATE_ENUM(SQ_PIX_RS_STALL, 45)
+    GENERATE_ENUM(SQ_SX_PC_FULL, 46)
+    GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47)
+    GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48)
+    GENERATE_ENUM(SQ_INTERP_QUADS, 49)
+    GENERATE_ENUM(SQ_INTERP_ACTIVE, 50)
+    GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51)
+    GENERATE_ENUM(SQ_IN_VTX_STALL, 52)
+    GENERATE_ENUM(SQ_VTX_CNT, 53)
+    GENERATE_ENUM(SQ_VTX_VECTOR2, 54)
+    GENERATE_ENUM(SQ_VTX_VECTOR3, 55)
+    GENERATE_ENUM(SQ_VTX_VECTOR4, 56)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61)
+    GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94)
+    GENERATE_ENUM(VC_PERF_STATIC, 95)
+    GENERATE_ENUM(VC_PERF_STALLED, 96)
+    GENERATE_ENUM(VC_PERF_STARVED, 97)
+    GENERATE_ENUM(VC_PERF_SEND, 98)
+    GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99)
+    GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100)
+    GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101)
+    GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102)
+    GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103)
+    GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104)
+    GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105)
+    GENERATE_ENUM(PTRBUFF_EF_PUSH, 106)
+    GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107)
+    GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108)
+    GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112)
+    GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113)
+    GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114)
+    GENERATE_ENUM(PTRBUFF_PI_RTR, 115)
+    GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116)
+    GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117)
+    GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118)
+    GENERATE_ENUM(PTRBUFF_SQ_DEC, 119)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121)
+    GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122)
+    GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123)
+    GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124)
+    GENERATE_ENUM(PTRBUFF_END_BUFFER, 125)
+    GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126)
+    GENERATE_ENUM(VERTS_WRITTEN_SPI, 127)
+    GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128)
+    GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129)
+    GENERATE_ENUM(TP_DATA_RETURN, 130)
+    GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131)
+    GENERATE_ENUM(SPI_WRITES_SP, 132)
+    GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133)
+    GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134)
+    GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135)
+    GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136)
+    GENERATE_ENUM(SP_EXPORTS_TO_SX, 137)
+    GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138)
+    GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139)
+    GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140)
+    GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141)
+    GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142)
+    GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143)
+    GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144)
+    GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145)
+    GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146)
+    GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147)
+    GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148)
+    GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149)
+    GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150)
+    GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151)
+    GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152)
+    GENERATE_ENUM(SQ_PIX_TOTAL, 153)
+    GENERATE_ENUM(SQ_PIX_KILLED, 154)
+END_ENUMTYPE(SQ_PERFCNT_SELECT)
+
+START_ENUMTYPE(SX_PERFCNT_SELECT)
+    GENERATE_ENUM(SX_EXPORT_VECTORS, 0)
+    GENERATE_ENUM(SX_DUMMY_QUADS, 1)
+    GENERATE_ENUM(SX_ALPHA_FAIL, 2)
+    GENERATE_ENUM(SX_RB_QUAD_BUSY, 3)
+    GENERATE_ENUM(SX_RB_COLOR_BUSY, 4)
+    GENERATE_ENUM(SX_RB_QUAD_STALL, 5)
+    GENERATE_ENUM(SX_RB_COLOR_STALL, 6)
+END_ENUMTYPE(SX_PERFCNT_SELECT)
+
+START_ENUMTYPE(Abs_modifier)
+    GENERATE_ENUM(NO_ABS_MOD, 0)
+    GENERATE_ENUM(ABS_MOD, 1)
+END_ENUMTYPE(Abs_modifier)
+
+START_ENUMTYPE(Exporting)
+    GENERATE_ENUM(NOT_EXPORTING, 0)
+    GENERATE_ENUM(EXPORTING, 1)
+END_ENUMTYPE(Exporting)
+
+START_ENUMTYPE(ScalarOpcode)
+    GENERATE_ENUM(ADDs, 0)
+    GENERATE_ENUM(ADD_PREVs, 1)
+    GENERATE_ENUM(MULs, 2)
+    GENERATE_ENUM(MUL_PREVs, 3)
+    GENERATE_ENUM(MUL_PREV2s, 4)
+    GENERATE_ENUM(MAXs, 5)
+    GENERATE_ENUM(MINs, 6)
+    GENERATE_ENUM(SETEs, 7)
+    GENERATE_ENUM(SETGTs, 8)
+    GENERATE_ENUM(SETGTEs, 9)
+    GENERATE_ENUM(SETNEs, 10)
+    GENERATE_ENUM(FRACs, 11)
+    GENERATE_ENUM(TRUNCs, 12)
+    GENERATE_ENUM(FLOORs, 13)
+    GENERATE_ENUM(EXP_IEEE, 14)
+    GENERATE_ENUM(LOG_CLAMP, 15)
+    GENERATE_ENUM(LOG_IEEE, 16)
+    GENERATE_ENUM(RECIP_CLAMP, 17)
+    GENERATE_ENUM(RECIP_FF, 18)
+    GENERATE_ENUM(RECIP_IEEE, 19)
+    GENERATE_ENUM(RECIPSQ_CLAMP, 20)
+    GENERATE_ENUM(RECIPSQ_FF, 21)
+    GENERATE_ENUM(RECIPSQ_IEEE, 22)
+    GENERATE_ENUM(MOVAs, 23)
+    GENERATE_ENUM(MOVA_FLOORs, 24)
+    GENERATE_ENUM(SUBs, 25)
+    GENERATE_ENUM(SUB_PREVs, 26)
+    GENERATE_ENUM(PRED_SETEs, 27)
+    GENERATE_ENUM(PRED_SETNEs, 28)
+    GENERATE_ENUM(PRED_SETGTs, 29)
+    GENERATE_ENUM(PRED_SETGTEs, 30)
+    GENERATE_ENUM(PRED_SET_INVs, 31)
+    GENERATE_ENUM(PRED_SET_POPs, 32)
+    GENERATE_ENUM(PRED_SET_CLRs, 33)
+    GENERATE_ENUM(PRED_SET_RESTOREs, 34)
+    GENERATE_ENUM(KILLEs, 35)
+    GENERATE_ENUM(KILLGTs, 36)
+    GENERATE_ENUM(KILLGTEs, 37)
+    GENERATE_ENUM(KILLNEs, 38)
+    GENERATE_ENUM(KILLONEs, 39)
+    GENERATE_ENUM(SQRT_IEEE, 40)
+    GENERATE_ENUM(MUL_CONST_0, 42)
+    GENERATE_ENUM(MUL_CONST_1, 43)
+    GENERATE_ENUM(ADD_CONST_0, 44)
+    GENERATE_ENUM(ADD_CONST_1, 45)
+    GENERATE_ENUM(SUB_CONST_0, 46)
+    GENERATE_ENUM(SUB_CONST_1, 47)
+    GENERATE_ENUM(SIN, 48)
+    GENERATE_ENUM(COS, 49)
+    GENERATE_ENUM(RETAIN_PREV, 50)
+END_ENUMTYPE(ScalarOpcode)
+
+START_ENUMTYPE(SwizzleType)
+    GENERATE_ENUM(NO_SWIZZLE, 0)
+    GENERATE_ENUM(SHIFT_RIGHT_1, 1)
+    GENERATE_ENUM(SHIFT_RIGHT_2, 2)
+    GENERATE_ENUM(SHIFT_RIGHT_3, 3)
+END_ENUMTYPE(SwizzleType)
+
+START_ENUMTYPE(InputModifier)
+    GENERATE_ENUM(NIL, 0)
+    GENERATE_ENUM(NEGATE, 1)
+END_ENUMTYPE(InputModifier)
+
+START_ENUMTYPE(PredicateSelect)
+    GENERATE_ENUM(NO_PREDICATION, 0)
+    GENERATE_ENUM(PREDICATE_QUAD, 1)
+    GENERATE_ENUM(PREDICATED_2, 2)
+    GENERATE_ENUM(PREDICATED_3, 3)
+END_ENUMTYPE(PredicateSelect)
+
+START_ENUMTYPE(OperandSelect1)
+    GENERATE_ENUM(ABSOLUTE_REG, 0)
+    GENERATE_ENUM(RELATIVE_REG, 1)
+END_ENUMTYPE(OperandSelect1)
+
+START_ENUMTYPE(VectorOpcode)
+    GENERATE_ENUM(ADDv, 0)
+    GENERATE_ENUM(MULv, 1)
+    GENERATE_ENUM(MAXv, 2)
+    GENERATE_ENUM(MINv, 3)
+    GENERATE_ENUM(SETEv, 4)
+    GENERATE_ENUM(SETGTv, 5)
+    GENERATE_ENUM(SETGTEv, 6)
+    GENERATE_ENUM(SETNEv, 7)
+    GENERATE_ENUM(FRACv, 8)
+    GENERATE_ENUM(TRUNCv, 9)
+    GENERATE_ENUM(FLOORv, 10)
+    GENERATE_ENUM(MULADDv, 11)
+    GENERATE_ENUM(CNDEv, 12)
+    GENERATE_ENUM(CNDGTEv, 13)
+    GENERATE_ENUM(CNDGTv, 14)
+    GENERATE_ENUM(DOT4v, 15)
+    GENERATE_ENUM(DOT3v, 16)
+    GENERATE_ENUM(DOT2ADDv, 17)
+    GENERATE_ENUM(CUBEv, 18)
+    GENERATE_ENUM(MAX4v, 19)
+    GENERATE_ENUM(PRED_SETE_PUSHv, 20)
+    GENERATE_ENUM(PRED_SETNE_PUSHv, 21)
+    GENERATE_ENUM(PRED_SETGT_PUSHv, 22)
+    GENERATE_ENUM(PRED_SETGTE_PUSHv, 23)
+    GENERATE_ENUM(KILLEv, 24)
+    GENERATE_ENUM(KILLGTv, 25)
+    GENERATE_ENUM(KILLGTEv, 26)
+    GENERATE_ENUM(KILLNEv, 27)
+    GENERATE_ENUM(DSTv, 28)
+    GENERATE_ENUM(MOVAv, 29)
+END_ENUMTYPE(VectorOpcode)
+
+START_ENUMTYPE(OperandSelect0)
+    GENERATE_ENUM(CONSTANT, 0)
+    GENERATE_ENUM(NON_CONSTANT, 1)
+END_ENUMTYPE(OperandSelect0)
+
+START_ENUMTYPE(Ressource_type)
+    GENERATE_ENUM(ALU, 0)
+    GENERATE_ENUM(TEXTURE, 1)
+END_ENUMTYPE(Ressource_type)
+
+START_ENUMTYPE(Instruction_serial)
+    GENERATE_ENUM(NOT_SERIAL, 0)
+    GENERATE_ENUM(SERIAL, 1)
+END_ENUMTYPE(Instruction_serial)
+
+START_ENUMTYPE(VC_type)
+    GENERATE_ENUM(ALU_TP_REQUEST, 0)
+    GENERATE_ENUM(VC_REQUEST, 1)
+END_ENUMTYPE(VC_type)
+
+START_ENUMTYPE(Addressing)
+    GENERATE_ENUM(RELATIVE_ADDR, 0)
+    GENERATE_ENUM(ABSOLUTE_ADDR, 1)
+END_ENUMTYPE(Addressing)
+
+START_ENUMTYPE(CFOpcode)
+    GENERATE_ENUM(NOP, 0)
+    GENERATE_ENUM(EXECUTE, 1)
+    GENERATE_ENUM(EXECUTE_END, 2)
+    GENERATE_ENUM(COND_EXECUTE, 3)
+    GENERATE_ENUM(COND_EXECUTE_END, 4)
+    GENERATE_ENUM(COND_PRED_EXECUTE, 5)
+    GENERATE_ENUM(COND_PRED_EXECUTE_END, 6)
+    GENERATE_ENUM(LOOP_START, 7)
+    GENERATE_ENUM(LOOP_END, 8)
+    GENERATE_ENUM(COND_CALL, 9)
+    GENERATE_ENUM(RETURN, 10)
+    GENERATE_ENUM(COND_JMP, 11)
+    GENERATE_ENUM(ALLOCATE, 12)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14)
+    GENERATE_ENUM(MARK_VS_FETCH_DONE, 15)
+END_ENUMTYPE(CFOpcode)
+
+START_ENUMTYPE(Allocation_type)
+    GENERATE_ENUM(SQ_NO_ALLOC, 0)
+    GENERATE_ENUM(SQ_POSITION, 1)
+    GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2)
+    GENERATE_ENUM(SQ_MEMORY, 3)
+END_ENUMTYPE(Allocation_type)
+
+START_ENUMTYPE(TexInstOpcode)
+    GENERATE_ENUM(TEX_INST_FETCH, 1)
+    GENERATE_ENUM(TEX_INST_RESERVED_1, 2)
+    GENERATE_ENUM(TEX_INST_RESERVED_2, 3)
+    GENERATE_ENUM(TEX_INST_RESERVED_3, 4)
+    GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16)
+    GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17)
+    GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18)
+    GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19)
+    GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26)
+    GENERATE_ENUM(TEX_INST_RESERVED_4, 27)
+END_ENUMTYPE(TexInstOpcode)
+
+START_ENUMTYPE(Addressmode)
+    GENERATE_ENUM(LOGICAL, 0)
+    GENERATE_ENUM(LOOP_RELATIVE, 1)
+END_ENUMTYPE(Addressmode)
+
+START_ENUMTYPE(TexCoordDenorm)
+    GENERATE_ENUM(TEX_COORD_NORMALIZED, 0)
+    GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1)
+END_ENUMTYPE(TexCoordDenorm)
+
+START_ENUMTYPE(SrcSel)
+    GENERATE_ENUM(SRC_SEL_X, 0)
+    GENERATE_ENUM(SRC_SEL_Y, 1)
+    GENERATE_ENUM(SRC_SEL_Z, 2)
+    GENERATE_ENUM(SRC_SEL_W, 3)
+END_ENUMTYPE(SrcSel)
+
+START_ENUMTYPE(DstSel)
+    GENERATE_ENUM(DST_SEL_X, 0)
+    GENERATE_ENUM(DST_SEL_Y, 1)
+    GENERATE_ENUM(DST_SEL_Z, 2)
+    GENERATE_ENUM(DST_SEL_W, 3)
+    GENERATE_ENUM(DST_SEL_0, 4)
+    GENERATE_ENUM(DST_SEL_1, 5)
+    GENERATE_ENUM(DST_SEL_RSVD, 6)
+    GENERATE_ENUM(DST_SEL_MASK, 7)
+END_ENUMTYPE(DstSel)
+
+START_ENUMTYPE(MagFilter)
+    GENERATE_ENUM(MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MagFilter)
+
+START_ENUMTYPE(MinFilter)
+    GENERATE_ENUM(MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MinFilter)
+
+START_ENUMTYPE(MipFilter)
+    GENERATE_ENUM(MIP_FILTER_POINT, 0)
+    GENERATE_ENUM(MIP_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIP_FILTER_BASEMAP, 2)
+    GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MipFilter)
+
+START_ENUMTYPE(AnisoFilter)
+    GENERATE_ENUM(ANISO_FILTER_DISABLED, 0)
+    GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1)
+    GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2)
+    GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3)
+    GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4)
+    GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5)
+    GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(AnisoFilter)
+
+START_ENUMTYPE(ArbitraryFilter)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5)
+    GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(ArbitraryFilter)
+
+START_ENUMTYPE(VolMagFilter)
+    GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMagFilter)
+
+START_ENUMTYPE(VolMinFilter)
+    GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMinFilter)
+
+START_ENUMTYPE(PredSelect)
+    GENERATE_ENUM(NOT_PREDICATED, 0)
+    GENERATE_ENUM(PREDICATED, 1)
+END_ENUMTYPE(PredSelect)
+
+START_ENUMTYPE(SampleLocation)
+    GENERATE_ENUM(SAMPLE_CENTROID, 0)
+    GENERATE_ENUM(SAMPLE_CENTER, 1)
+END_ENUMTYPE(SampleLocation)
+
+START_ENUMTYPE(VertexMode)
+    GENERATE_ENUM(POSITION_1_VECTOR, 0)
+    GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3)
+    GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6)
+    GENERATE_ENUM(MULTIPASS, 7)
+END_ENUMTYPE(VertexMode)
+
+START_ENUMTYPE(Sample_Cntl)
+    GENERATE_ENUM(CENTROIDS_ONLY, 0)
+    GENERATE_ENUM(CENTERS_ONLY, 1)
+    GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2)
+    GENERATE_ENUM(UNDEF, 3)
+END_ENUMTYPE(Sample_Cntl)
+
+START_ENUMTYPE(MhPerfEncode)
+    GENERATE_ENUM(CP_R0_REQUESTS, 0)
+    GENERATE_ENUM(CP_R1_REQUESTS, 1)
+    GENERATE_ENUM(CP_R2_REQUESTS, 2)
+    GENERATE_ENUM(CP_R3_REQUESTS, 3)
+    GENERATE_ENUM(CP_R4_REQUESTS, 4)
+    GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5)
+    GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6)
+    GENERATE_ENUM(CP_TOTAL_REQUESTS, 7)
+    GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8)
+    GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9)
+    GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10)
+    GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11)
+    GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12)
+    GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13)
+    GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14)
+    GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15)
+    GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16)
+    GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17)
+    GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18)
+    GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19)
+    GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20)
+    GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21)
+    GENERATE_ENUM(VGT_R0_REQUESTS, 22)
+    GENERATE_ENUM(VGT_R1_REQUESTS, 23)
+    GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24)
+    GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25)
+    GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26)
+    GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27)
+    GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28)
+    GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29)
+    GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30)
+    GENERATE_ENUM(TC_TOTAL_REQUESTS, 31)
+    GENERATE_ENUM(TC_ROQ_REQUESTS, 32)
+    GENERATE_ENUM(TC_INFO_SENT, 33)
+    GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34)
+    GENERATE_ENUM(TC_DATA_BEATS_READ, 35)
+    GENERATE_ENUM(TCD_BURSTS_READ, 36)
+    GENERATE_ENUM(RB_REQUESTS, 37)
+    GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38)
+    GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56)
+    GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111)
+    GENERATE_ENUM(TOTAL_MMU_MISSES, 112)
+    GENERATE_ENUM(MMU_READ_MISSES, 113)
+    GENERATE_ENUM(MMU_WRITE_MISSES, 114)
+    GENERATE_ENUM(TOTAL_MMU_HITS, 115)
+    GENERATE_ENUM(MMU_READ_HITS, 116)
+    GENERATE_ENUM(MMU_WRITE_HITS, 117)
+    GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118)
+    GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121)
+    GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122)
+    GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123)
+    GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124)
+    GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125)
+    GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127)
+    GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129)
+    GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130)
+    GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131)
+    GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132)
+    GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133)
+    GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136)
+    GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140)
+    GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148)
+    GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149)
+    GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150)
+    GENERATE_ENUM(TOTAL_MH_REQUESTS, 151)
+    GENERATE_ENUM(MH_BUSY, 152)
+    GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153)
+    GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154)
+    GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155)
+    GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156)
+    GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157)
+    GENERATE_ENUM(ARQ_N_ENTRIES, 158)
+    GENERATE_ENUM(WDB_N_ENTRIES, 159)
+    GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160)
+    GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161)
+    GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162)
+    GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163)
+    GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164)
+    GENERATE_ENUM(CP_W_16B_REQUESTS, 165)
+    GENERATE_ENUM(CP_W_32B_REQUESTS, 166)
+    GENERATE_ENUM(TC_16B_REQUESTS, 167)
+    GENERATE_ENUM(TC_32B_REQUESTS, 168)
+    GENERATE_ENUM(PA_REQUESTS, 169)
+    GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170)
+    GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171)
+    GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181)
+END_ENUMTYPE(MhPerfEncode)
+
+START_ENUMTYPE(MmuClntBeh)
+    GENERATE_ENUM(BEH_NEVR, 0)
+    GENERATE_ENUM(BEH_TRAN_RNG, 1)
+    GENERATE_ENUM(BEH_TRAN_FLT, 2)
+END_ENUMTYPE(MmuClntBeh)
+
+START_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+    GENERATE_ENUM(RBBM1_COUNT, 0)
+    GENERATE_ENUM(RBBM1_NRT_BUSY, 1)
+    GENERATE_ENUM(RBBM1_RB_BUSY, 2)
+    GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3)
+    GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4)
+    GENERATE_ENUM(RBBM1_VGT_BUSY, 5)
+    GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6)
+    GENERATE_ENUM(RBBM1_PA_BUSY, 7)
+    GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8)
+    GENERATE_ENUM(RBBM1_TPC_BUSY, 9)
+    GENERATE_ENUM(RBBM1_TC_BUSY, 10)
+    GENERATE_ENUM(RBBM1_SX_BUSY, 11)
+    GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12)
+    GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13)
+    GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14)
+    GENERATE_ENUM(RBBM1_INTERRUPT, 15)
+END_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+
+START_ENUMTYPE(CP_PERFCOUNT_SEL)
+    GENERATE_ENUM(ALWAYS_COUNT, 0)
+    GENERATE_ENUM(TRANS_FIFO_FULL, 1)
+    GENERATE_ENUM(TRANS_FIFO_AF, 2)
+    GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3)
+    GENERATE_ENUM(Reserved_04, 4)
+    GENERATE_ENUM(Reserved_05, 5)
+    GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6)
+    GENERATE_ENUM(Reserved_07, 7)
+    GENERATE_ENUM(CSF_NRT_READ_WAIT, 8)
+    GENERATE_ENUM(CSF_I1_FIFO_FULL, 9)
+    GENERATE_ENUM(CSF_I2_FIFO_FULL, 10)
+    GENERATE_ENUM(CSF_ST_FIFO_FULL, 11)
+    GENERATE_ENUM(Reserved_12, 12)
+    GENERATE_ENUM(CSF_RING_ROQ_FULL, 13)
+    GENERATE_ENUM(CSF_I1_ROQ_FULL, 14)
+    GENERATE_ENUM(CSF_I2_ROQ_FULL, 15)
+    GENERATE_ENUM(CSF_ST_ROQ_FULL, 16)
+    GENERATE_ENUM(Reserved_17, 17)
+    GENERATE_ENUM(MIU_TAG_MEM_FULL, 18)
+    GENERATE_ENUM(MIU_WRITECLEAN, 19)
+    GENERATE_ENUM(Reserved_20, 20)
+    GENERATE_ENUM(Reserved_21, 21)
+    GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22)
+    GENERATE_ENUM(MIU_NRT_READ_STALLED, 23)
+    GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24)
+    GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25)
+    GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26)
+    GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27)
+    GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28)
+    GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29)
+    GENERATE_ENUM(ME_MICRO_RB_STARVED, 30)
+    GENERATE_ENUM(ME_MICRO_I1_STARVED, 31)
+    GENERATE_ENUM(ME_MICRO_I2_STARVED, 32)
+    GENERATE_ENUM(ME_MICRO_ST_STARVED, 33)
+    GENERATE_ENUM(Reserved_34, 34)
+    GENERATE_ENUM(Reserved_35, 35)
+    GENERATE_ENUM(Reserved_36, 36)
+    GENERATE_ENUM(Reserved_37, 37)
+    GENERATE_ENUM(Reserved_38, 38)
+    GENERATE_ENUM(Reserved_39, 39)
+    GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40)
+    GENERATE_ENUM(ME_BUSY_CLOCKS, 41)
+    GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42)
+    GENERATE_ENUM(PFP_TYPE0_PACKET, 43)
+    GENERATE_ENUM(PFP_TYPE3_PACKET, 44)
+    GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45)
+    GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46)
+    GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47)
+    GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48)
+    GENERATE_ENUM(Reserved_49, 49)
+    GENERATE_ENUM(Reserved_50, 50)
+    GENERATE_ENUM(Reserved_51, 51)
+    GENERATE_ENUM(Reserved_52, 52)
+    GENERATE_ENUM(Reserved_53, 53)
+    GENERATE_ENUM(Reserved_54, 54)
+    GENERATE_ENUM(Reserved_55, 55)
+    GENERATE_ENUM(Reserved_56, 56)
+    GENERATE_ENUM(Reserved_57, 57)
+    GENERATE_ENUM(Reserved_58, 58)
+    GENERATE_ENUM(Reserved_59, 59)
+    GENERATE_ENUM(Reserved_60, 60)
+    GENERATE_ENUM(Reserved_61, 61)
+    GENERATE_ENUM(Reserved_62, 62)
+    GENERATE_ENUM(Reserved_63, 63)
+END_ENUMTYPE(CP_PERFCOUNT_SEL)
+
+START_ENUMTYPE(ColorformatX)
+    GENERATE_ENUM(COLORX_4_4_4_4, 0)
+    GENERATE_ENUM(COLORX_1_5_5_5, 1)
+    GENERATE_ENUM(COLORX_5_6_5, 2)
+    GENERATE_ENUM(COLORX_8, 3)
+    GENERATE_ENUM(COLORX_8_8, 4)
+    GENERATE_ENUM(COLORX_8_8_8_8, 5)
+    GENERATE_ENUM(COLORX_S8_8_8_8, 6)
+    GENERATE_ENUM(COLORX_16_FLOAT, 7)
+    GENERATE_ENUM(COLORX_16_16_FLOAT, 8)
+    GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9)
+    GENERATE_ENUM(COLORX_32_FLOAT, 10)
+    GENERATE_ENUM(COLORX_32_32_FLOAT, 11)
+    GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12)
+    GENERATE_ENUM(COLORX_2_3_3, 13)
+    GENERATE_ENUM(COLORX_8_8_8, 14)
+END_ENUMTYPE(ColorformatX)
+
+START_ENUMTYPE(DepthformatX)
+    GENERATE_ENUM(DEPTHX_16, 0)
+    GENERATE_ENUM(DEPTHX_24_8, 1)
+END_ENUMTYPE(DepthformatX)
+
+START_ENUMTYPE(CompareFrag)
+    GENERATE_ENUM(FRAG_NEVER, 0)
+    GENERATE_ENUM(FRAG_LESS, 1)
+    GENERATE_ENUM(FRAG_EQUAL, 2)
+    GENERATE_ENUM(FRAG_LEQUAL, 3)
+    GENERATE_ENUM(FRAG_GREATER, 4)
+    GENERATE_ENUM(FRAG_NOTEQUAL, 5)
+    GENERATE_ENUM(FRAG_GEQUAL, 6)
+    GENERATE_ENUM(FRAG_ALWAYS, 7)
+END_ENUMTYPE(CompareFrag)
+
+START_ENUMTYPE(CompareRef)
+    GENERATE_ENUM(REF_NEVER, 0)
+    GENERATE_ENUM(REF_LESS, 1)
+    GENERATE_ENUM(REF_EQUAL, 2)
+    GENERATE_ENUM(REF_LEQUAL, 3)
+    GENERATE_ENUM(REF_GREATER, 4)
+    GENERATE_ENUM(REF_NOTEQUAL, 5)
+    GENERATE_ENUM(REF_GEQUAL, 6)
+    GENERATE_ENUM(REF_ALWAYS, 7)
+END_ENUMTYPE(CompareRef)
+
+START_ENUMTYPE(StencilOp)
+    GENERATE_ENUM(STENCIL_KEEP, 0)
+    GENERATE_ENUM(STENCIL_ZERO, 1)
+    GENERATE_ENUM(STENCIL_REPLACE, 2)
+    GENERATE_ENUM(STENCIL_INCR_CLAMP, 3)
+    GENERATE_ENUM(STENCIL_DECR_CLAMP, 4)
+    GENERATE_ENUM(STENCIL_INVERT, 5)
+    GENERATE_ENUM(STENCIL_INCR_WRAP, 6)
+    GENERATE_ENUM(STENCIL_DECR_WRAP, 7)
+END_ENUMTYPE(StencilOp)
+
+START_ENUMTYPE(BlendOpX)
+    GENERATE_ENUM(BLENDX_ZERO, 0)
+    GENERATE_ENUM(BLENDX_ONE, 1)
+    GENERATE_ENUM(BLENDX_SRC_COLOR, 4)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA, 6)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7)
+    GENERATE_ENUM(BLENDX_DST_COLOR, 8)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9)
+    GENERATE_ENUM(BLENDX_DST_ALPHA, 10)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11)
+    GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13)
+    GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16)
+END_ENUMTYPE(BlendOpX)
+
+START_ENUMTYPE(CombFuncX)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC, 0)
+    GENERATE_ENUM(COMB_SRC_MINUS_DST, 1)
+    GENERATE_ENUM(COMB_MIN_DST_SRC, 2)
+    GENERATE_ENUM(COMB_MAX_DST_SRC, 3)
+    GENERATE_ENUM(COMB_DST_MINUS_SRC, 4)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5)
+END_ENUMTYPE(CombFuncX)
+
+START_ENUMTYPE(DitherModeX)
+    GENERATE_ENUM(DITHER_DISABLE, 0)
+    GENERATE_ENUM(DITHER_ALWAYS, 1)
+    GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2)
+END_ENUMTYPE(DitherModeX)
+
+START_ENUMTYPE(DitherTypeX)
+    GENERATE_ENUM(DITHER_PIXEL, 0)
+    GENERATE_ENUM(DITHER_SUBPIXEL, 1)
+END_ENUMTYPE(DitherTypeX)
+
+START_ENUMTYPE(EdramMode)
+    GENERATE_ENUM(EDRAM_NOP, 0)
+    GENERATE_ENUM(COLOR_DEPTH, 4)
+    GENERATE_ENUM(DEPTH_ONLY, 5)
+    GENERATE_ENUM(EDRAM_COPY, 6)
+END_ENUMTYPE(EdramMode)
+
+START_ENUMTYPE(SurfaceEndian)
+    GENERATE_ENUM(ENDIAN_NONE, 0)
+    GENERATE_ENUM(ENDIAN_8IN16, 1)
+    GENERATE_ENUM(ENDIAN_8IN32, 2)
+    GENERATE_ENUM(ENDIAN_16IN32, 3)
+    GENERATE_ENUM(ENDIAN_8IN64, 4)
+    GENERATE_ENUM(ENDIAN_8IN128, 5)
+END_ENUMTYPE(SurfaceEndian)
+
+START_ENUMTYPE(EdramSizeX)
+    GENERATE_ENUM(EDRAMSIZE_16KB, 0)
+    GENERATE_ENUM(EDRAMSIZE_32KB, 1)
+    GENERATE_ENUM(EDRAMSIZE_64KB, 2)
+    GENERATE_ENUM(EDRAMSIZE_128KB, 3)
+    GENERATE_ENUM(EDRAMSIZE_256KB, 4)
+    GENERATE_ENUM(EDRAMSIZE_512KB, 5)
+    GENERATE_ENUM(EDRAMSIZE_1MB, 6)
+    GENERATE_ENUM(EDRAMSIZE_2MB, 7)
+    GENERATE_ENUM(EDRAMSIZE_4MB, 8)
+    GENERATE_ENUM(EDRAMSIZE_8MB, 9)
+    GENERATE_ENUM(EDRAMSIZE_16MB, 10)
+END_ENUMTYPE(EdramSizeX)
+
+START_ENUMTYPE(RB_PERFCNT_SELECT)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY, 0)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7)
+    GENERATE_ENUM(RBPERF_MH_STARVED, 8)
+    GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23)
+    GENERATE_ENUM(RBPERF_ZXP_STALL, 24)
+    GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING, 26)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID, 28)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30)
+    GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32)
+    GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33)
+    GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37)
+    GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38)
+    GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43)
+    GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44)
+    GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45)
+    GENERATE_ENUM(RBPERF_ZPASS_DONE, 46)
+    GENERATE_ENUM(RBPERF_ZCMD_VALID, 47)
+    GENERATE_ENUM(RBPERF_CCMD_VALID, 48)
+    GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49)
+    GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50)
+    GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51)
+    GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52)
+    GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53)
+    GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54)
+    GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55)
+    GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56)
+END_ENUMTYPE(RB_PERFCNT_SELECT)
+
+START_ENUMTYPE(DepthFormat)
+    GENERATE_ENUM(DEPTH_24_8, 22)
+    GENERATE_ENUM(DEPTH_24_8_FLOAT, 23)
+    GENERATE_ENUM(DEPTH_16, 24)
+END_ENUMTYPE(DepthFormat)
+
+START_ENUMTYPE(SurfaceSwap)
+    GENERATE_ENUM(SWAP_LOWRED, 0)
+    GENERATE_ENUM(SWAP_LOWBLUE, 1)
+END_ENUMTYPE(SurfaceSwap)
+
+START_ENUMTYPE(DepthArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0)
+    GENERATE_ENUM(ARRAY_2D_DEPTH, 1)
+END_ENUMTYPE(DepthArray)
+
+START_ENUMTYPE(ColorArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0)
+    GENERATE_ENUM(ARRAY_2D_COLOR, 1)
+    GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3)
+END_ENUMTYPE(ColorArray)
+
+START_ENUMTYPE(ColorFormat)
+    GENERATE_ENUM(COLOR_8, 2)
+    GENERATE_ENUM(COLOR_1_5_5_5, 3)
+    GENERATE_ENUM(COLOR_5_6_5, 4)
+    GENERATE_ENUM(COLOR_6_5_5, 5)
+    GENERATE_ENUM(COLOR_8_8_8_8, 6)
+    GENERATE_ENUM(COLOR_2_10_10_10, 7)
+    GENERATE_ENUM(COLOR_8_A, 8)
+    GENERATE_ENUM(COLOR_8_B, 9)
+    GENERATE_ENUM(COLOR_8_8, 10)
+    GENERATE_ENUM(COLOR_8_8_8, 11)
+    GENERATE_ENUM(COLOR_8_8_8_8_A, 14)
+    GENERATE_ENUM(COLOR_4_4_4_4, 15)
+    GENERATE_ENUM(COLOR_10_11_11, 16)
+    GENERATE_ENUM(COLOR_11_11_10, 17)
+    GENERATE_ENUM(COLOR_16, 24)
+    GENERATE_ENUM(COLOR_16_16, 25)
+    GENERATE_ENUM(COLOR_16_16_16_16, 26)
+    GENERATE_ENUM(COLOR_16_FLOAT, 30)
+    GENERATE_ENUM(COLOR_16_16_FLOAT, 31)
+    GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(COLOR_32_FLOAT, 36)
+    GENERATE_ENUM(COLOR_32_32_FLOAT, 37)
+    GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(COLOR_2_3_3, 39)
+END_ENUMTYPE(ColorFormat)
+
+START_ENUMTYPE(SurfaceNumber)
+    GENERATE_ENUM(NUMBER_UREPEAT, 0)
+    GENERATE_ENUM(NUMBER_SREPEAT, 1)
+    GENERATE_ENUM(NUMBER_UINTEGER, 2)
+    GENERATE_ENUM(NUMBER_SINTEGER, 3)
+    GENERATE_ENUM(NUMBER_GAMMA, 4)
+    GENERATE_ENUM(NUMBER_FIXED, 5)
+    GENERATE_ENUM(NUMBER_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumber)
+
+START_ENUMTYPE(SurfaceFormat)
+    GENERATE_ENUM(FMT_1_REVERSE, 0)
+    GENERATE_ENUM(FMT_1, 1)
+    GENERATE_ENUM(FMT_8, 2)
+    GENERATE_ENUM(FMT_1_5_5_5, 3)
+    GENERATE_ENUM(FMT_5_6_5, 4)
+    GENERATE_ENUM(FMT_6_5_5, 5)
+    GENERATE_ENUM(FMT_8_8_8_8, 6)
+    GENERATE_ENUM(FMT_2_10_10_10, 7)
+    GENERATE_ENUM(FMT_8_A, 8)
+    GENERATE_ENUM(FMT_8_B, 9)
+    GENERATE_ENUM(FMT_8_8, 10)
+    GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11)
+    GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12)
+    GENERATE_ENUM(FMT_5_5_5_1, 13)
+    GENERATE_ENUM(FMT_8_8_8_8_A, 14)
+    GENERATE_ENUM(FMT_4_4_4_4, 15)
+    GENERATE_ENUM(FMT_8_8_8, 16)
+    GENERATE_ENUM(FMT_DXT1, 18)
+    GENERATE_ENUM(FMT_DXT2_3, 19)
+    GENERATE_ENUM(FMT_DXT4_5, 20)
+    GENERATE_ENUM(FMT_10_10_10_2, 21)
+    GENERATE_ENUM(FMT_24_8, 22)
+    GENERATE_ENUM(FMT_16, 24)
+    GENERATE_ENUM(FMT_16_16, 25)
+    GENERATE_ENUM(FMT_16_16_16_16, 26)
+    GENERATE_ENUM(FMT_16_EXPAND, 27)
+    GENERATE_ENUM(FMT_16_16_EXPAND, 28)
+    GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29)
+    GENERATE_ENUM(FMT_16_FLOAT, 30)
+    GENERATE_ENUM(FMT_16_16_FLOAT, 31)
+    GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(FMT_32, 33)
+    GENERATE_ENUM(FMT_32_32, 34)
+    GENERATE_ENUM(FMT_32_32_32_32, 35)
+    GENERATE_ENUM(FMT_32_FLOAT, 36)
+    GENERATE_ENUM(FMT_32_32_FLOAT, 37)
+    GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(FMT_ATI_TC_RGB, 39)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA, 40)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44)
+    GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46)
+    GENERATE_ENUM(FMT_ETC1_RGB, 47)
+    GENERATE_ENUM(FMT_ETC1_RGBA, 48)
+    GENERATE_ENUM(FMT_DXN, 49)
+    GENERATE_ENUM(FMT_2_3_3, 51)
+    GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54)
+    GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55)
+    GENERATE_ENUM(FMT_32_32_32_FLOAT, 57)
+    GENERATE_ENUM(FMT_DXT3A, 58)
+    GENERATE_ENUM(FMT_DXT5A, 59)
+    GENERATE_ENUM(FMT_CTX1, 60)
+END_ENUMTYPE(SurfaceFormat)
+
+START_ENUMTYPE(SurfaceTiling)
+    GENERATE_ENUM(ARRAY_LINEAR, 0)
+    GENERATE_ENUM(ARRAY_TILED, 1)
+END_ENUMTYPE(SurfaceTiling)
+
+START_ENUMTYPE(SurfaceArray)
+    GENERATE_ENUM(ARRAY_1D, 0)
+    GENERATE_ENUM(ARRAY_2D, 1)
+    GENERATE_ENUM(ARRAY_3D, 2)
+    GENERATE_ENUM(ARRAY_3D_SLICE, 3)
+END_ENUMTYPE(SurfaceArray)
+
+START_ENUMTYPE(SurfaceNumberX)
+    GENERATE_ENUM(NUMBERX_UREPEAT, 0)
+    GENERATE_ENUM(NUMBERX_SREPEAT, 1)
+    GENERATE_ENUM(NUMBERX_UINTEGER, 2)
+    GENERATE_ENUM(NUMBERX_SINTEGER, 3)
+    GENERATE_ENUM(NUMBERX_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumberX)
+
+START_ENUMTYPE(ColorArrayX)
+    GENERATE_ENUM(ARRAYX_2D_COLOR, 0)
+    GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1)
+END_ENUMTYPE(ColorArrayX)
+
+
+
+
+// **************************************************************************
+// These are ones that had to be added in addition to what's generated
+// by the autoreg (in CSIM)
+// **************************************************************************
+START_ENUMTYPE(DXClipSpaceDef)
+    GENERATE_ENUM(DXCLIP_OPENGL, 0)
+    GENERATE_ENUM(DXCLIP_DIRECTX, 1)
+END_ENUMTYPE(DXClipSpaceDef)
+
+START_ENUMTYPE(PixCenter)
+    GENERATE_ENUM(PIXCENTER_D3D, 0)
+    GENERATE_ENUM(PIXCENTER_OGL, 1)
+END_ENUMTYPE(PixCenter)
+
+START_ENUMTYPE(RoundMode)
+    GENERATE_ENUM(TRUNCATE,   0)
+    GENERATE_ENUM(ROUND,      1)
+    GENERATE_ENUM(ROUNDTOEVEN,    2)
+    GENERATE_ENUM(ROUNDTOODD,     3)
+END_ENUMTYPE(RoundMode)
+
+START_ENUMTYPE(QuantMode)
+    GENERATE_ENUM(ONE_SIXTEENTH,   0)
+    GENERATE_ENUM(ONE_EIGHTH,      1)
+    GENERATE_ENUM(ONE_QUARTER,     2)
+    GENERATE_ENUM(ONE_HALF,    3)
+    GENERATE_ENUM(ONE,         4)
+END_ENUMTYPE(QuantMode)
+
+START_ENUMTYPE(FrontFace)
+    GENERATE_ENUM(FRONT_CCW,        0)
+    GENERATE_ENUM(FRONT_CW,     1)
+END_ENUMTYPE(FrontFace)
+
+START_ENUMTYPE(PolyMode)
+    GENERATE_ENUM(DISABLED,    0)
+    GENERATE_ENUM(DUALMODE,    1)
+END_ENUMTYPE(PolyMode)
+
+START_ENUMTYPE(PType)
+    GENERATE_ENUM(DRAW_POINTS,      0)
+    GENERATE_ENUM(DRAW_LINES,       1)
+    GENERATE_ENUM(DRAW_TRIANGLES,   2)
+END_ENUMTYPE(PType)
+
+START_ENUMTYPE(MSAANumSamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     3)
+END_ENUMTYPE(MSAANumSamples)
+
+START_ENUMTYPE(PatternBitOrder)
+    GENERATE_ENUM(LITTLE,   0)
+    GENERATE_ENUM(BIG,      1)
+END_ENUMTYPE(PatternBitOrder)
+
+START_ENUMTYPE(AutoResetCntl)
+    GENERATE_ENUM(NEVER,        0)
+    GENERATE_ENUM(EACHPRIMITIVE,    1)
+    GENERATE_ENUM(EACHPACKET,       2)
+END_ENUMTYPE(AutoResetCntl)
+
+START_ENUMTYPE(ParamShade)
+    GENERATE_ENUM(FLAT,     0)
+    GENERATE_ENUM(GOURAUD,  1)
+END_ENUMTYPE(ParamShade)
+
+START_ENUMTYPE(SamplingPattern)
+    GENERATE_ENUM(CENTROID, 0)
+    GENERATE_ENUM(PIXCENTER, 1)
+END_ENUMTYPE(SamplingPattern)
+
+START_ENUMTYPE(MSAASamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     2)
+END_ENUMTYPE(MSAASamples)
+
+START_ENUMTYPE(CopySampleSelect)
+    GENERATE_ENUM(SAMPLE_0, 0)
+    GENERATE_ENUM(SAMPLE_1, 1)
+    GENERATE_ENUM(SAMPLE_2, 2)
+    GENERATE_ENUM(SAMPLE_3, 3)
+    GENERATE_ENUM(SAMPLE_01,    4)
+    GENERATE_ENUM(SAMPLE_23,    5)
+    GENERATE_ENUM(SAMPLE_0123,  6)
+END_ENUMTYPE(CopySampleSelect)
+
+
+#undef START_ENUMTYPE
+#undef GENERATE_ENUM
+#undef END_ENUMTYPE
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h
new file mode 100644
index 00000000000..f7efe31bc8a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h
@@ -0,0 +1,3404 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_REGISTER(PA_CL_VPORT_XSCALE)
+    GENERATE_FIELD(VPORT_XSCALE, float)
+END_REGISTER(PA_CL_VPORT_XSCALE)
+
+START_REGISTER(PA_CL_VPORT_XOFFSET)
+    GENERATE_FIELD(VPORT_XOFFSET, float)
+END_REGISTER(PA_CL_VPORT_XOFFSET)
+
+START_REGISTER(PA_CL_VPORT_YSCALE)
+    GENERATE_FIELD(VPORT_YSCALE, float)
+END_REGISTER(PA_CL_VPORT_YSCALE)
+
+START_REGISTER(PA_CL_VPORT_YOFFSET)
+    GENERATE_FIELD(VPORT_YOFFSET, float)
+END_REGISTER(PA_CL_VPORT_YOFFSET)
+
+START_REGISTER(PA_CL_VPORT_ZSCALE)
+    GENERATE_FIELD(VPORT_ZSCALE, float)
+END_REGISTER(PA_CL_VPORT_ZSCALE)
+
+START_REGISTER(PA_CL_VPORT_ZOFFSET)
+    GENERATE_FIELD(VPORT_ZOFFSET, float)
+END_REGISTER(PA_CL_VPORT_ZOFFSET)
+
+START_REGISTER(PA_CL_VTE_CNTL)
+    GENERATE_FIELD(PERFCOUNTER_REF, bool)
+    GENERATE_FIELD(VTX_W0_FMT, bool)
+    GENERATE_FIELD(VTX_Z_FMT, bool)
+    GENERATE_FIELD(VTX_XY_FMT, bool)
+    GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_X_SCALE_ENA, bool)
+END_REGISTER(PA_CL_VTE_CNTL)
+
+START_REGISTER(PA_CL_CLIP_CNTL)
+    GENERATE_FIELD(W_NAN_RETAIN, bool)
+    GENERATE_FIELD(Z_NAN_RETAIN, bool)
+    GENERATE_FIELD(XY_NAN_RETAIN, bool)
+    GENERATE_FIELD(VTX_KILL_OR, bool)
+    GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool)
+    GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef)
+    GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool)
+    GENERATE_FIELD(CLIP_DISABLE, bool)
+END_REGISTER(PA_CL_CLIP_CNTL)
+
+START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+
+START_REGISTER(PA_CL_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE0, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool)
+END_REGISTER(PA_CL_ENHANCE)
+
+START_REGISTER(PA_SC_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE0, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE3, int)
+END_REGISTER(PA_SC_ENHANCE)
+
+START_REGISTER(PA_SU_VTX_CNTL)
+    GENERATE_FIELD(QUANT_MODE, QuantMode)
+    GENERATE_FIELD(ROUND_MODE, RoundMode)
+    GENERATE_FIELD(PIX_CENTER, PixCenter)
+END_REGISTER(PA_SU_VTX_CNTL)
+
+START_REGISTER(PA_SU_POINT_SIZE)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+    GENERATE_FIELD(HEIGHT, fixed12_4)
+END_REGISTER(PA_SU_POINT_SIZE)
+
+START_REGISTER(PA_SU_POINT_MINMAX)
+    GENERATE_FIELD(MAX_SIZE, fixed12_4)
+    GENERATE_FIELD(MIN_SIZE, fixed12_4)
+END_REGISTER(PA_SU_POINT_MINMAX)
+
+START_REGISTER(PA_SU_LINE_CNTL)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_LINE_CNTL)
+
+START_REGISTER(PA_SU_FACE_DATA)
+    GENERATE_FIELD(BASE_ADDR, int)
+END_REGISTER(PA_SU_FACE_DATA)
+
+START_REGISTER(PA_SU_SC_MODE_CNTL)
+    GENERATE_FIELD(FACE_WRITE_ENABLE, bool)
+    GENERATE_FIELD(FACE_KILL_ENABLE, bool)
+    GENERATE_FIELD(ZERO_AREA_FACENESS, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool)
+    GENERATE_FIELD(QUAD_ORDER_ENABLE, bool)
+    GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool)
+    GENERATE_FIELD(PERSP_CORR_DIS, bool)
+    GENERATE_FIELD(PROVOKING_VTX_LAST, bool)
+    GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool)
+    GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool)
+    GENERATE_FIELD(MSAA_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool)
+    GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType)
+    GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType)
+    GENERATE_FIELD(POLY_MODE, PolyMode)
+    GENERATE_FIELD(FACE, FrontFace)
+    GENERATE_FIELD(CULL_BACK, bool)
+    GENERATE_FIELD(CULL_FRONT, bool)
+END_REGISTER(PA_SU_SC_MODE_CNTL)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT)
+END_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_HI)
+
+START_REGISTER(PA_SC_WINDOW_OFFSET)
+    GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15)
+    GENERATE_FIELD(WINDOW_X_OFFSET, signedint15)
+END_REGISTER(PA_SC_WINDOW_OFFSET)
+
+START_REGISTER(PA_SC_AA_CONFIG)
+    GENERATE_FIELD(MAX_SAMPLE_DIST, int)
+    GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples)
+END_REGISTER(PA_SC_AA_CONFIG)
+
+START_REGISTER(PA_SC_AA_MASK)
+    GENERATE_FIELD(AA_MASK, hex)
+END_REGISTER(PA_SC_AA_MASK)
+
+START_REGISTER(PA_SC_LINE_STIPPLE)
+    GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl)
+    GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder)
+    GENERATE_FIELD(REPEAT_COUNT, intMinusOne)
+    GENERATE_FIELD(LINE_PATTERN, hex)
+END_REGISTER(PA_SC_LINE_STIPPLE)
+
+START_REGISTER(PA_SC_LINE_CNTL)
+    GENERATE_FIELD(LAST_PIXEL, bool)
+    GENERATE_FIELD(EXPAND_LINE_WIDTH, bool)
+    GENERATE_FIELD(USE_BRES_CNTL, bool)
+    GENERATE_FIELD(BRES_CNTL, int)
+END_REGISTER(PA_SC_LINE_CNTL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+    GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(TL_X, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+    GENERATE_FIELD(BR_Y, int)
+    GENERATE_FIELD(BR_X, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(TL_X, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+    GENERATE_FIELD(BR_Y, int)
+    GENERATE_FIELD(BR_X, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+
+START_REGISTER(PA_SC_VIZ_QUERY)
+    GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool)
+    GENERATE_FIELD(VIZ_QUERY_ID, int)
+    GENERATE_FIELD(VIZ_QUERY_ENA, bool)
+END_REGISTER(PA_SC_VIZ_QUERY)
+
+START_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+    GENERATE_FIELD(STATUS_BITS, hex)
+END_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+
+START_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+    GENERATE_FIELD(CURRENT_COUNT, int)
+    GENERATE_FIELD(CURRENT_PTR, int)
+END_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT)
+END_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_CL_CNTL_STATUS)
+    GENERATE_FIELD(CL_BUSY, int)
+END_REGISTER(PA_CL_CNTL_STATUS)
+
+START_REGISTER(PA_SU_CNTL_STATUS)
+    GENERATE_FIELD(SU_BUSY, int)
+END_REGISTER(PA_SU_CNTL_STATUS)
+
+START_REGISTER(PA_SC_CNTL_STATUS)
+    GENERATE_FIELD(SC_BUSY, int)
+END_REGISTER(PA_SC_CNTL_STATUS)
+
+START_REGISTER(PA_SU_DEBUG_CNTL)
+    GENERATE_FIELD(SU_DEBUG_INDX, int)
+END_REGISTER(PA_SU_DEBUG_CNTL)
+
+START_REGISTER(PA_SU_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(PA_SU_DEBUG_DATA)
+
+START_REGISTER(PA_SC_DEBUG_CNTL)
+    GENERATE_FIELD(SC_DEBUG_INDX, int)
+END_REGISTER(PA_SC_DEBUG_CNTL)
+
+START_REGISTER(PA_SC_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(PA_SC_DEBUG_DATA)
+
+START_REGISTER(GFX_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(GFX_COPY_STATE)
+
+START_REGISTER(VGT_DRAW_INITIATOR)
+    GENERATE_FIELD(NUM_INDICES, uint)
+    GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX)
+    GENERATE_FIELD(NOT_EOP, bool)
+    GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE)
+    GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT)
+    GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE)
+END_REGISTER(VGT_DRAW_INITIATOR)
+
+START_REGISTER(VGT_EVENT_INITIATOR)
+    GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE)
+END_REGISTER(VGT_EVENT_INITIATOR)
+
+START_REGISTER(VGT_DMA_BASE)
+    GENERATE_FIELD(BASE_ADDR, uint)
+END_REGISTER(VGT_DMA_BASE)
+
+START_REGISTER(VGT_DMA_SIZE)
+    GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+END_REGISTER(VGT_DMA_SIZE)
+
+START_REGISTER(VGT_BIN_BASE)
+    GENERATE_FIELD(BIN_BASE_ADDR, uint)
+END_REGISTER(VGT_BIN_BASE)
+
+START_REGISTER(VGT_BIN_SIZE)
+    GENERATE_FIELD(FACENESS_RESET, int)
+    GENERATE_FIELD(FACENESS_FETCH, int)
+    GENERATE_FIELD(NUM_WORDS, uint)
+END_REGISTER(VGT_BIN_SIZE)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+    GENERATE_FIELD(GUARD_BAND, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(COLUMN, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+    GENERATE_FIELD(GUARD_BAND, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(COLUMN, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+
+START_REGISTER(VGT_IMMED_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_IMMED_DATA)
+
+START_REGISTER(VGT_MAX_VTX_INDX)
+    GENERATE_FIELD(MAX_INDX, int)
+END_REGISTER(VGT_MAX_VTX_INDX)
+
+START_REGISTER(VGT_MIN_VTX_INDX)
+    GENERATE_FIELD(MIN_INDX, int)
+END_REGISTER(VGT_MIN_VTX_INDX)
+
+START_REGISTER(VGT_INDX_OFFSET)
+    GENERATE_FIELD(INDX_OFFSET, int)
+END_REGISTER(VGT_INDX_OFFSET)
+
+START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+    GENERATE_FIELD(VTX_REUSE_DEPTH, int)
+END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+
+START_REGISTER(VGT_OUT_DEALLOC_CNTL)
+    GENERATE_FIELD(DEALLOC_DIST, int)
+END_REGISTER(VGT_OUT_DEALLOC_CNTL)
+
+START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+    GENERATE_FIELD(RESET_INDX, int)
+END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+
+START_REGISTER(VGT_ENHANCE)
+    GENERATE_FIELD(MISC, hex)
+END_REGISTER(VGT_ENHANCE)
+
+START_REGISTER(VGT_VTX_VECT_EJECT_REG)
+    GENERATE_FIELD(PRIM_COUNT, int)
+END_REGISTER(VGT_VTX_VECT_EJECT_REG)
+
+START_REGISTER(VGT_LAST_COPY_STATE)
+    GENERATE_FIELD(DST_STATE_ID, int)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(VGT_LAST_COPY_STATE)
+
+START_REGISTER(VGT_DEBUG_CNTL)
+    GENERATE_FIELD(VGT_DEBUG_INDX, int)
+END_REGISTER(VGT_DEBUG_CNTL)
+
+START_REGISTER(VGT_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_DEBUG_DATA)
+
+START_REGISTER(VGT_CNTL_STATUS)
+    GENERATE_FIELD(VGT_OUT_INDX_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_BUSY, int)
+    GENERATE_FIELD(VGT_PT_BUSY, int)
+    GENERATE_FIELD(VGT_BIN_BUSY, int)
+    GENERATE_FIELD(VGT_VR_BUSY, int)
+    GENERATE_FIELD(VGT_GRP_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_REQ_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+END_REGISTER(VGT_CNTL_STATUS)
+
+START_REGISTER(VGT_CRC_SQ_DATA)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_DATA)
+
+START_REGISTER(VGT_CRC_SQ_CTRL)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_CTRL)
+
+START_REGISTER(VGT_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER0_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER1_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER2_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER3_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_HI)
+
+START_REGISTER(VGT_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_HI)
+
+START_REGISTER(VGT_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_HI)
+
+START_REGISTER(VGT_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_HI)
+
+START_REGISTER(TC_CNTL_STATUS)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(TC_L2_HIT_MISS, int)
+    GENERATE_FIELD(L2_INVALIDATE, int)
+END_REGISTER(TC_CNTL_STATUS)
+
+START_REGISTER(TCR_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCR_CHICKEN)
+
+START_REGISTER(TCF_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCF_CHICKEN)
+
+START_REGISTER(TCM_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+    GENERATE_FIELD(ETC_COLOR_ENDIAN, int)
+    GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int)
+END_REGISTER(TCM_CHICKEN)
+
+START_REGISTER(TCR_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER0_HI)
+
+START_REGISTER(TCR_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER1_HI)
+
+START_REGISTER(TCR_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCR_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER1_LOW)
+
+START_REGISTER(TP_TC_CLKGATE_CNTL)
+    GENERATE_FIELD(TC_BUSY_EXTEND, int)
+    GENERATE_FIELD(TP_BUSY_EXTEND, int)
+END_REGISTER(TP_TC_CLKGATE_CNTL)
+
+START_REGISTER(TPC_CNTL_STATUS)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(TP_SQ_DEC, int)
+    GENERATE_FIELD(TA_TF_TC_FIFO_REN, int)
+    GENERATE_FIELD(TA_TF_RTS, int)
+    GENERATE_FIELD(TA_TB_RTR, int)
+    GENERATE_FIELD(TA_TB_TT_RTS, int)
+    GENERATE_FIELD(TA_TB_RTS, int)
+    GENERATE_FIELD(TW_TA_RTR, int)
+    GENERATE_FIELD(TW_TA_LAST_RTS, int)
+    GENERATE_FIELD(TW_TA_TT_RTS, int)
+    GENERATE_FIELD(TW_TA_RTS, int)
+    GENERATE_FIELD(TF_TW_RTR, int)
+    GENERATE_FIELD(TF_TW_STATE_RTS, int)
+    GENERATE_FIELD(TF_TW_RTS, int)
+    GENERATE_FIELD(TPC_BLEND_BUSY, int)
+    GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_BUSY, int)
+    GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_INPUT_BUSY, int)
+END_REGISTER(TPC_CNTL_STATUS)
+
+START_REGISTER(TPC_DEBUG0)
+    GENERATE_FIELD(SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(TPC_CLK_EN, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(ALIGNER_STATE, int)
+    GENERATE_FIELD(WALKER_STATE, int)
+    GENERATE_FIELD(PREV_TC_STATE_VALID, int)
+    GENERATE_FIELD(ALIGNER_CNTL, int)
+    GENERATE_FIELD(WALKER_CNTL, int)
+    GENERATE_FIELD(IC_CTR, int)
+    GENERATE_FIELD(LOD_CNTL, int)
+END_REGISTER(TPC_DEBUG0)
+
+START_REGISTER(TPC_DEBUG1)
+    GENERATE_FIELD(UNUSED, int)
+END_REGISTER(TPC_DEBUG1)
+
+START_REGISTER(TPC_CHICKEN)
+    GENERATE_FIELD(SPARE, int)
+    GENERATE_FIELD(BLEND_PRECISION, int)
+END_REGISTER(TPC_CHICKEN)
+
+START_REGISTER(TP0_CNTL_STATUS)
+    GENERATE_FIELD(TP_BUSY, int)
+    GENERATE_FIELD(TB_TO_RTS, int)
+    GENERATE_FIELD(TB_TT_TT_RESET, int)
+    GENERATE_FIELD(TB_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_RTS, int)
+    GENERATE_FIELD(AL_TF_TT_RTS, int)
+    GENERATE_FIELD(AL_TF_RTS, int)
+    GENERATE_FIELD(FA_AL_TT_RTS, int)
+    GENERATE_FIELD(FA_AL_RTS, int)
+    GENERATE_FIELD(TA_FA_TT_RTS, int)
+    GENERATE_FIELD(TA_FA_RTS, int)
+    GENERATE_FIELD(FL_TA_RTS, int)
+    GENERATE_FIELD(LA_FL_RTS, int)
+    GENERATE_FIELD(LC_LA_RTS, int)
+    GENERATE_FIELD(IN_LC_RTS, int)
+    GENERATE_FIELD(TP_OUTPUT_BUSY, int)
+    GENERATE_FIELD(TP_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_HICOLOR_BUSY, int)
+    GENERATE_FIELD(TP_TT_BUSY, int)
+    GENERATE_FIELD(TP_CH_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_FETCH_BUSY, int)
+    GENERATE_FIELD(TP_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ADDR_BUSY, int)
+    GENERATE_FIELD(TP_LOD_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_LOD_BUSY, int)
+    GENERATE_FIELD(TP_INPUT_BUSY, int)
+END_REGISTER(TP0_CNTL_STATUS)
+
+START_REGISTER(TP0_DEBUG)
+    GENERATE_FIELD(Q_ALIGNER_CNTL, int)
+    GENERATE_FIELD(Q_WALKER_CNTL, int)
+    GENERATE_FIELD(TP_CLK_EN, int)
+    GENERATE_FIELD(PERF_CLK_EN, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int)
+    GENERATE_FIELD(Q_SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(Q_LOD_CNTL, int)
+END_REGISTER(TP0_DEBUG)
+
+START_REGISTER(TP0_CHICKEN)
+    GENERATE_FIELD(SPARE, int)
+    GENERATE_FIELD(VFETCH_ADDRESS_MODE, int)
+    GENERATE_FIELD(TT_MODE, int)
+END_REGISTER(TP0_CHICKEN)
+
+START_REGISTER(TP0_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT)
+END_REGISTER(TP0_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER0_HI)
+
+START_REGISTER(TP0_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER0_LOW)
+
+START_REGISTER(TP0_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, int)
+END_REGISTER(TP0_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER1_HI)
+
+START_REGISTER(TP0_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER0_HI)
+
+START_REGISTER(TCM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER1_HI)
+
+START_REGISTER(TCM_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER2_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER3_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER4_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER4_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER5_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER5_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER6_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER6_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER7_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER7_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER8_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER8_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER9_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER9_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER10_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER10_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER11_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER11_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER0_HI)
+
+START_REGISTER(TCF_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER1_HI)
+
+START_REGISTER(TCF_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER2_HI)
+
+START_REGISTER(TCF_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER3_HI)
+
+START_REGISTER(TCF_PERFCOUNTER4_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER4_HI)
+
+START_REGISTER(TCF_PERFCOUNTER5_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER5_HI)
+
+START_REGISTER(TCF_PERFCOUNTER6_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER6_HI)
+
+START_REGISTER(TCF_PERFCOUNTER7_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER7_HI)
+
+START_REGISTER(TCF_PERFCOUNTER8_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER8_HI)
+
+START_REGISTER(TCF_PERFCOUNTER9_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER9_HI)
+
+START_REGISTER(TCF_PERFCOUNTER10_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER10_HI)
+
+START_REGISTER(TCF_PERFCOUNTER11_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER11_HI)
+
+START_REGISTER(TCF_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER2_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER3_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER4_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER4_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER5_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER5_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER6_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER6_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER7_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER7_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER8_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER8_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER9_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER9_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER10_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER10_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER11_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER11_LOW)
+
+START_REGISTER(TCF_DEBUG)
+    GENERATE_FIELD(tca_rts, int)
+    GENERATE_FIELD(tca_state_rts, int)
+    GENERATE_FIELD(not_TPC_rtr, int)
+    GENERATE_FIELD(TPC_full, int)
+    GENERATE_FIELD(TP0_full, int)
+    GENERATE_FIELD(PF0_stall, int)
+    GENERATE_FIELD(TCA_TCB_stall, int)
+    GENERATE_FIELD(TCB_miss_stall, int)
+    GENERATE_FIELD(TCB_ff_stall, int)
+    GENERATE_FIELD(not_TCB_TCO_rtr, int)
+    GENERATE_FIELD(not_FG0_rtr, int)
+    GENERATE_FIELD(TC_MH_send, int)
+    GENERATE_FIELD(not_MH_TC_rtr, int)
+END_REGISTER(TCF_DEBUG)
+
+START_REGISTER(TCA_FIFO_DEBUG)
+    GENERATE_FIELD(FW_tpc_rts, int)
+    GENERATE_FIELD(not_FW_tpc_rtr, int)
+    GENERATE_FIELD(FW_rts0, int)
+    GENERATE_FIELD(not_FW_rtr0, int)
+    GENERATE_FIELD(FW_full, int)
+    GENERATE_FIELD(load_tp_fifos, int)
+    GENERATE_FIELD(load_tpc_fifo, int)
+    GENERATE_FIELD(tpc_full, int)
+    GENERATE_FIELD(tp0_full, int)
+END_REGISTER(TCA_FIFO_DEBUG)
+
+START_REGISTER(TCA_PROBE_DEBUG)
+    GENERATE_FIELD(ProbeFilter_stall, int)
+END_REGISTER(TCA_PROBE_DEBUG)
+
+START_REGISTER(TCA_TPC_DEBUG)
+    GENERATE_FIELD(capture_tca_rts, int)
+    GENERATE_FIELD(captue_state_rts, int)
+END_REGISTER(TCA_TPC_DEBUG)
+
+START_REGISTER(TCB_CORE_DEBUG)
+    GENERATE_FIELD(sector_format512, int)
+    GENERATE_FIELD(sector_format, int)
+    GENERATE_FIELD(format, int)
+    GENERATE_FIELD(opcode, int)
+    GENERATE_FIELD(tiled, int)
+    GENERATE_FIELD(access512, int)
+END_REGISTER(TCB_CORE_DEBUG)
+
+START_REGISTER(TCB_TAG0_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG0_DEBUG)
+
+START_REGISTER(TCB_TAG1_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG1_DEBUG)
+
+START_REGISTER(TCB_TAG2_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG2_DEBUG)
+
+START_REGISTER(TCB_TAG3_DEBUG)
+    GENERATE_FIELD(max_misses, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(mem_read_cycle, int)
+END_REGISTER(TCB_TAG3_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+    GENERATE_FIELD(valid_left_q, int)
+    GENERATE_FIELD(sector_mask_left_q, int)
+    GENERATE_FIELD(sector_mask_left_count_q, int)
+    GENERATE_FIELD(update_left, int)
+    GENERATE_FIELD(no_sectors_to_go, int)
+    GENERATE_FIELD(one_sector_to_go_left_q, int)
+    GENERATE_FIELD(fg0_sends_left, int)
+    GENERATE_FIELD(left_done, int)
+END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+    GENERATE_FIELD(setquads_to_send, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(ff_fg_type512, int)
+    GENERATE_FIELD(right_eq_left, int)
+    GENERATE_FIELD(set_sel_left, int)
+    GENERATE_FIELD(quad_sel_left, int)
+END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+    GENERATE_FIELD(arb_RTR, int)
+    GENERATE_FIELD(valid_q, int)
+    GENERATE_FIELD(mc_sel_q, int)
+    GENERATE_FIELD(ga_busy, int)
+    GENERATE_FIELD(fgo_busy, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(tc_arb_request_type, int)
+    GENERATE_FIELD(tc_arb_fmsopcode, int)
+    GENERATE_FIELD(tc_arb_format, int)
+    GENERATE_FIELD(ga_out_rts, int)
+    GENERATE_FIELD(tc0_arb_rts, int)
+END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+
+START_REGISTER(TCD_INPUT0_DEBUG)
+    GENERATE_FIELD(ipbuf_busy, int)
+    GENERATE_FIELD(ipbuf_dxt_send, int)
+    GENERATE_FIELD(ip_send, int)
+    GENERATE_FIELD(last_send_q1, int)
+    GENERATE_FIELD(cnt_q1, int)
+    GENERATE_FIELD(valid_q1, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(empty, int)
+END_REGISTER(TCD_INPUT0_DEBUG)
+
+START_REGISTER(TCD_DEGAMMA_DEBUG)
+    GENERATE_FIELD(dgmm_pstate, int)
+    GENERATE_FIELD(dgmm_stall, int)
+    GENERATE_FIELD(dgmm_ctrl_send, int)
+    GENERATE_FIELD(dgmm_ctrl_last_send, int)
+    GENERATE_FIELD(dgmm_ctrl_dgmm8, int)
+    GENERATE_FIELD(dgmm_ftfconv_dgmmen, int)
+END_REGISTER(TCD_DEGAMMA_DEBUG)
+
+START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+    GENERATE_FIELD(dcmp_mux_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_last_send, int)
+    GENERATE_FIELD(dxtc_sctrarb_send, int)
+    GENERATE_FIELD(sctrmx0_sctrarb_rts, int)
+    GENERATE_FIELD(sctrarb_multcyl_send, int)
+    GENERATE_FIELD(dxtc_rtr, int)
+    GENERATE_FIELD(sctrmx_rtr, int)
+    GENERATE_FIELD(pstate, int)
+END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+
+START_REGISTER(TCD_DXTC_ARB_DEBUG)
+    GENERATE_FIELD(n0_dxt2_4_types, int)
+    GENERATE_FIELD(arb_dcmp01_send, int)
+    GENERATE_FIELD(arb_dcmp01_format, int)
+    GENERATE_FIELD(arb_dcmp01_cacheline, int)
+    GENERATE_FIELD(arb_dcmp01_sector, int)
+    GENERATE_FIELD(arb_dcmp01_cnt, int)
+    GENERATE_FIELD(arb_dcmp01_last_send, int)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(n0_stall, int)
+END_REGISTER(TCD_DXTC_ARB_DEBUG)
+
+START_REGISTER(TCD_STALLS_DEBUG)
+    GENERATE_FIELD(not_incoming_rtr, int)
+    GENERATE_FIELD(not_mux_dcmp_rtr, int)
+    GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int)
+    GENERATE_FIELD(not_dcmp0_arb_rtr, int)
+    GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int)
+    GENERATE_FIELD(not_multcyl_sctrarb_rtr, int)
+END_REGISTER(TCD_STALLS_DEBUG)
+
+START_REGISTER(TCO_STALLS_DEBUG)
+    GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int)
+    GENERATE_FIELD(quad0_rl_sg_RTR, int)
+    GENERATE_FIELD(quad0_sg_crd_RTR, int)
+END_REGISTER(TCO_STALLS_DEBUG)
+
+START_REGISTER(TCO_QUAD0_DEBUG0)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(all_sectors_written_set0, int)
+    GENERATE_FIELD(all_sectors_written_set1, int)
+    GENERATE_FIELD(all_sectors_written_set2, int)
+    GENERATE_FIELD(all_sectors_written_set3, int)
+    GENERATE_FIELD(cache_read_RTR, int)
+    GENERATE_FIELD(read_cache_q, int)
+    GENERATE_FIELD(stageN1_valid_q, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_sector_format, int)
+END_REGISTER(TCO_QUAD0_DEBUG0)
+
+START_REGISTER(TCO_QUAD0_DEBUG1)
+    GENERATE_FIELD(TCO_TCB_read_xfc, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(TCB_TCO_xfc_q, int)
+    GENERATE_FIELD(TCB_TCO_rtr_d, int)
+    GENERATE_FIELD(tco_quad_pipe_busy, int)
+    GENERATE_FIELD(input_quad_busy, int)
+    GENERATE_FIELD(latency_fifo_busy, int)
+    GENERATE_FIELD(cache_read_busy, int)
+    GENERATE_FIELD(fifo_read_ptr, int)
+    GENERATE_FIELD(fifo_write_ptr, int)
+    GENERATE_FIELD(write_enable, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(fifo_busy, int)
+END_REGISTER(TCO_QUAD0_DEBUG1)
+
+START_REGISTER(SQ_GPR_MANAGEMENT)
+    GENERATE_FIELD(REG_SIZE_VTX, int)
+    GENERATE_FIELD(REG_SIZE_PIX, int)
+    GENERATE_FIELD(REG_DYNAMIC, int)
+END_REGISTER(SQ_GPR_MANAGEMENT)
+
+START_REGISTER(SQ_FLOW_CONTROL)
+    GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int)
+    GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int)
+    GENERATE_FIELD(POS_EXP_PRIORITY, int)
+    GENERATE_FIELD(NO_CFS_EJECT, int)
+    GENERATE_FIELD(NO_ARB_EJECT, int)
+    GENERATE_FIELD(ALU_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(VC_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int)
+    GENERATE_FIELD(NO_LOOP_EXIT, int)
+    GENERATE_FIELD(NO_PV_PS, int)
+    GENERATE_FIELD(CF_WR_BASE, hex)
+    GENERATE_FIELD(ONE_ALU, int)
+    GENERATE_FIELD(ONE_THREAD, int)
+    GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int)
+END_REGISTER(SQ_FLOW_CONTROL)
+
+START_REGISTER(SQ_INST_STORE_MANAGMENT)
+    GENERATE_FIELD(INST_BASE_VTX, int)
+    GENERATE_FIELD(INST_BASE_PIX, int)
+END_REGISTER(SQ_INST_STORE_MANAGMENT)
+
+START_REGISTER(SQ_RESOURCE_MANAGMENT)
+    GENERATE_FIELD(EXPORT_BUF_ENTRIES, int)
+    GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int)
+END_REGISTER(SQ_RESOURCE_MANAGMENT)
+
+START_REGISTER(SQ_EO_RT)
+    GENERATE_FIELD(EO_TSTATE_RT, int)
+    GENERATE_FIELD(EO_CONSTANTS_RT, int)
+END_REGISTER(SQ_EO_RT)
+
+START_REGISTER(SQ_DEBUG_MISC)
+    GENERATE_FIELD(DB_WEN_MEMORY_3, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_2, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_1, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_0, int)
+    GENERATE_FIELD(DB_READ_MEMORY, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DB_READ_CTX, int)
+    GENERATE_FIELD(DB_TSTATE_SIZE, int)
+    GENERATE_FIELD(DB_ALUCST_SIZE, int)
+END_REGISTER(SQ_DEBUG_MISC)
+
+START_REGISTER(SQ_ACTIVITY_METER_CNTL)
+    GENERATE_FIELD(SPARE, int)
+    GENERATE_FIELD(THRESHOLD_HIGH, int)
+    GENERATE_FIELD(THRESHOLD_LOW, int)
+    GENERATE_FIELD(TIMEBASE, int)
+END_REGISTER(SQ_ACTIVITY_METER_CNTL)
+
+START_REGISTER(SQ_ACTIVITY_METER_STATUS)
+    GENERATE_FIELD(PERCENT_BUSY, int)
+END_REGISTER(SQ_ACTIVITY_METER_STATUS)
+
+START_REGISTER(SQ_INPUT_ARB_PRIORITY)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+END_REGISTER(SQ_INPUT_ARB_PRIORITY)
+
+START_REGISTER(SQ_THREAD_ARB_PRIORITY)
+    GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int)
+    GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+END_REGISTER(SQ_THREAD_ARB_PRIORITY)
+
+START_REGISTER(SQ_VS_WATCHDOG_TIMER)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+    GENERATE_FIELD(ENABLE, int)
+END_REGISTER(SQ_VS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_PS_WATCHDOG_TIMER)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+    GENERATE_FIELD(ENABLE, int)
+END_REGISTER(SQ_PS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_INT_CNTL)
+    GENERATE_FIELD(VS_WATCHDOG_MASK, int)
+    GENERATE_FIELD(PS_WATCHDOG_MASK, int)
+END_REGISTER(SQ_INT_CNTL)
+
+START_REGISTER(SQ_INT_STATUS)
+    GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int)
+    GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int)
+END_REGISTER(SQ_INT_STATUS)
+
+START_REGISTER(SQ_INT_ACK)
+    GENERATE_FIELD(VS_WATCHDOG_ACK, int)
+    GENERATE_FIELD(PS_WATCHDOG_ACK, int)
+END_REGISTER(SQ_INT_ACK)
+
+START_REGISTER(SQ_DEBUG_INPUT_FSM)
+    GENERATE_FIELD(PC_GPR_SIZE, int)
+    GENERATE_FIELD(PC_INTERP_CNT, int)
+    GENERATE_FIELD(PC_AS, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PC_PISM, int)
+    GENERATE_FIELD(VC_GPR_LD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VC_VSR_LD, int)
+END_REGISTER(SQ_DEBUG_INPUT_FSM)
+
+START_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+    GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(TEX_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(ALU_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(ALU_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(TEX_CONST_EVENT_STATE, int)
+END_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+
+START_REGISTER(SQ_DEBUG_TP_FSM)
+    GENERATE_FIELD(ARB_TR_TP, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(FCS_TP, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(FCR_TP, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(GS_TP, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(TIS_TP, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(IF_TP, int)
+    GENERATE_FIELD(CF_TP, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(EX_TP, int)
+END_REGISTER(SQ_DEBUG_TP_FSM)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_0)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(EX_ALU_0, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_0)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_1)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(EX_ALU_0, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_1)
+
+START_REGISTER(SQ_DEBUG_EXP_ALLOC)
+    GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(EA_BUF_AVAIL, int)
+    GENERATE_FIELD(COLOR_BUF_AVAIL, int)
+    GENERATE_FIELD(POS_BUF_AVAIL, int)
+END_REGISTER(SQ_DEBUG_EXP_ALLOC)
+
+START_REGISTER(SQ_DEBUG_PTR_BUFF)
+    GENERATE_FIELD(VTX_SYNC_CNT, int)
+    GENERATE_FIELD(EF_EMPTY, int)
+    GENERATE_FIELD(PRIM_TYPE_POLYGON, int)
+    GENERATE_FIELD(QUAL_EVENT, int)
+    GENERATE_FIELD(SC_EVENT_ID, int)
+    GENERATE_FIELD(EVENT_CONTEXT_ID, int)
+    GENERATE_FIELD(QUAL_NEW_VECTOR, int)
+    GENERATE_FIELD(DEALLOC_CNT, int)
+    GENERATE_FIELD(END_OF_BUFFER, int)
+END_REGISTER(SQ_DEBUG_PTR_BUFF)
+
+START_REGISTER(SQ_DEBUG_GPR_VTX)
+    GENERATE_FIELD(VTX_FREE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(VTX_MAX, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(VTX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VTX_TAIL_PTR, int)
+END_REGISTER(SQ_DEBUG_GPR_VTX)
+
+START_REGISTER(SQ_DEBUG_GPR_PIX)
+    GENERATE_FIELD(PIX_FREE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(PIX_MAX, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(PIX_TAIL_PTR, int)
+END_REGISTER(SQ_DEBUG_GPR_PIX)
+
+START_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+    GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int)
+    GENERATE_FIELD(VC_THREAD_BUF_DLY, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int)
+END_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_0)
+    GENERATE_FIELD(BUSY_Q, int)
+    GENERATE_FIELD(SX_EVENT_FULL, int)
+    GENERATE_FIELD(NXT_PC_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_POS_ALLOC_CNT, int)
+    GENERATE_FIELD(FULL_CNT_Q, int)
+    GENERATE_FIELD(TAIL_PTR_Q, int)
+    GENERATE_FIELD(VTX_HEAD_PTR_Q, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_0)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_1)
+    GENERATE_FIELD(VS_DONE_PTR, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_1)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+    GENERATE_FIELD(VS_STATUS_REG, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+    GENERATE_FIELD(VS_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_0)
+    GENERATE_FIELD(BUSY, int)
+    GENERATE_FIELD(NXT_PIX_EXP_CNT, int)
+    GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int)
+    GENERATE_FIELD(FULL_CNT, int)
+    GENERATE_FIELD(TAIL_PTR, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_0, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_1, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_2, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_3, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+    GENERATE_FIELD(PIX_TB_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+
+START_REGISTER(SQ_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT)
+END_REGISTER(SQ_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER1_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER2_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER3_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_HI)
+
+START_REGISTER(SQ_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_HI)
+
+START_REGISTER(SQ_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_HI)
+
+START_REGISTER(SX_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT)
+END_REGISTER(SX_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SX_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_LOW)
+
+START_REGISTER(SX_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_0)
+    GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode)
+    GENERATE_FIELD(SCALAR_CLAMP, int)
+    GENERATE_FIELD(VECTOR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_WRT_MSK, int)
+    GENERATE_FIELD(VECTOR_WRT_MSK, int)
+    GENERATE_FIELD(EXPORT_DATA, Exporting)
+    GENERATE_FIELD(SCALAR_DST_REL, int)
+    GENERATE_FIELD(SCALAR_RESULT, int)
+    GENERATE_FIELD(LOW_PRECISION_16B_FP, int)
+    GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier)
+    GENERATE_FIELD(VECTOR_RESULT, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_0)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_1)
+    GENERATE_FIELD(CONST_0_REL_ABS, int)
+    GENERATE_FIELD(CONST_1_REL_ABS, int)
+    GENERATE_FIELD(RELATIVE_ADDR, int)
+    GENERATE_FIELD(PRED_SELECT, PredicateSelect)
+    GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType)
+END_REGISTER(SQ_INSTRUCTION_ALU_1)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_2)
+    GENERATE_FIELD(SRC_A_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_B_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_C_SEL, OperandSelect0)
+    GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode)
+    GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier)
+    GENERATE_FIELD(REG_SELECT_A, OperandSelect1)
+    GENERATE_FIELD(SRC_A_REG_PTR, int)
+    GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier)
+    GENERATE_FIELD(REG_SELECT_B, OperandSelect1)
+    GENERATE_FIELD(SRC_B_REG_PTR, int)
+    GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier)
+    GENERATE_FIELD(REG_SELECT_C, OperandSelect1)
+    GENERATE_FIELD(SRC_C_REG_PTR, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS, int)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(RESERVED_0, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(LOOP_ID, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(PREDICATED_JMP, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+    GENERATE_FIELD(RESERVED_2, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(RESERVED_0, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(RESERVED_0, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+    GENERATE_FIELD(SRC_SEL_Z, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Y, SrcSel)
+    GENERATE_FIELD(SRC_SEL_X, SrcSel)
+    GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(FETCH_VALID_ONLY, int)
+    GENERATE_FIELD(DST_GPR_AM, Addressmode)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, Addressmode)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(OPCODE, TexInstOpcode)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+    GENERATE_FIELD(PRED_SELECT, PredSelect)
+    GENERATE_FIELD(USE_REG_LOD, int)
+    GENERATE_FIELD(USE_COMP_LOD, int)
+    GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter)
+    GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter)
+    GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter)
+    GENERATE_FIELD(ANISO_FILTER, AnisoFilter)
+    GENERATE_FIELD(MIP_FILTER, MipFilter)
+    GENERATE_FIELD(MIN_FILTER, MinFilter)
+    GENERATE_FIELD(MAG_FILTER, MagFilter)
+    GENERATE_FIELD(DST_SEL_W, DstSel)
+    GENERATE_FIELD(DST_SEL_Z, DstSel)
+    GENERATE_FIELD(DST_SEL_Y, DstSel)
+    GENERATE_FIELD(DST_SEL_X, DstSel)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+    GENERATE_FIELD(PRED_CONDITION, int)
+    GENERATE_FIELD(OFFSET_Z, int)
+    GENERATE_FIELD(OFFSET_Y, int)
+    GENERATE_FIELD(OFFSET_X, int)
+    GENERATE_FIELD(UNUSED, int)
+    GENERATE_FIELD(LOD_BIAS, int)
+    GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation)
+    GENERATE_FIELD(USE_REG_GRADIENTS, int)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+    GENERATE_FIELD(SRC_SEL, int)
+    GENERATE_FIELD(CONST_INDEX_SEL, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(MUST_BE_ONE, int)
+    GENERATE_FIELD(DST_GPR_AM, int)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, int)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(OPCODE, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+    GENERATE_FIELD(PRED_SELECT, int)
+    GENERATE_FIELD(EXP_ADJUST_ALL, int)
+    GENERATE_FIELD(DATA_FORMAT, int)
+    GENERATE_FIELD(SIGNED_RF_MODE_ALL, int)
+    GENERATE_FIELD(NUM_FORMAT_ALL, int)
+    GENERATE_FIELD(FORMAT_COMP_ALL, int)
+    GENERATE_FIELD(DST_SEL_W, int)
+    GENERATE_FIELD(DST_SEL_Z, int)
+    GENERATE_FIELD(DST_SEL_Y, int)
+    GENERATE_FIELD(DST_SEL_X, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+    GENERATE_FIELD(PRED_CONDITION, int)
+    GENERATE_FIELD(OFFSET, int)
+    GENERATE_FIELD(STRIDE, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+
+START_REGISTER(SQ_CONSTANT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_0)
+
+START_REGISTER(SQ_CONSTANT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_1)
+
+START_REGISTER(SQ_CONSTANT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_2)
+
+START_REGISTER(SQ_CONSTANT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_3)
+
+START_REGISTER(SQ_FETCH_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_0)
+
+START_REGISTER(SQ_FETCH_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_1)
+
+START_REGISTER(SQ_FETCH_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_2)
+
+START_REGISTER(SQ_FETCH_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_3)
+
+START_REGISTER(SQ_FETCH_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_4)
+
+START_REGISTER(SQ_FETCH_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_5)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_0)
+    GENERATE_FIELD(BASE_ADDRESS, hex)
+    GENERATE_FIELD(STATE, int)
+    GENERATE_FIELD(TYPE, int)
+END_REGISTER(SQ_CONSTANT_VFETCH_0)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_1)
+    GENERATE_FIELD(LIMIT_ADDRESS, hex)
+    GENERATE_FIELD(ENDIAN_SWAP, int)
+END_REGISTER(SQ_CONSTANT_VFETCH_1)
+
+START_REGISTER(SQ_CONSTANT_T2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T2)
+
+START_REGISTER(SQ_CONSTANT_T3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T3)
+
+START_REGISTER(SQ_CF_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+END_REGISTER(SQ_CF_BOOLEANS)
+
+START_REGISTER(SQ_CF_LOOP)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+END_REGISTER(SQ_CF_LOOP)
+
+START_REGISTER(SQ_CONSTANT_RT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_RT_0)
+
+START_REGISTER(SQ_CONSTANT_RT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_RT_1)
+
+START_REGISTER(SQ_CONSTANT_RT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_RT_2)
+
+START_REGISTER(SQ_CONSTANT_RT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_0)
+
+START_REGISTER(SQ_FETCH_RT_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_1)
+
+START_REGISTER(SQ_FETCH_RT_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_2)
+
+START_REGISTER(SQ_FETCH_RT_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_4)
+
+START_REGISTER(SQ_FETCH_RT_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_5)
+
+START_REGISTER(SQ_CF_RT_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+END_REGISTER(SQ_CF_RT_BOOLEANS)
+
+START_REGISTER(SQ_CF_RT_LOOP)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+END_REGISTER(SQ_CF_RT_LOOP)
+
+START_REGISTER(SQ_VS_PROGRAM)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_VS_PROGRAM)
+
+START_REGISTER(SQ_PS_PROGRAM)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_PS_PROGRAM)
+
+START_REGISTER(SQ_CF_PROGRAM_SIZE)
+    GENERATE_FIELD(PS_CF_SIZE, int)
+    GENERATE_FIELD(VS_CF_SIZE, int)
+END_REGISTER(SQ_CF_PROGRAM_SIZE)
+
+START_REGISTER(SQ_INTERPOLATOR_CNTL)
+    GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern)
+    GENERATE_FIELD(PARAM_SHADE, ParamShade)
+END_REGISTER(SQ_INTERPOLATOR_CNTL)
+
+START_REGISTER(SQ_PROGRAM_CNTL)
+    GENERATE_FIELD(GEN_INDEX_VTX, int)
+    GENERATE_FIELD(PS_EXPORT_MODE, int)
+    GENERATE_FIELD(VS_EXPORT_MODE, VertexMode)
+    GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne)
+    GENERATE_FIELD(GEN_INDEX_PIX, int)
+    GENERATE_FIELD(PARAM_GEN, int)
+    GENERATE_FIELD(PS_RESOURCE, int)
+    GENERATE_FIELD(VS_RESOURCE, int)
+    GENERATE_FIELD(PS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(VS_NUM_REG, intMinusOne)
+END_REGISTER(SQ_PROGRAM_CNTL)
+
+START_REGISTER(SQ_WRAPPING_0)
+    GENERATE_FIELD(PARAM_WRAP_7, hex)
+    GENERATE_FIELD(PARAM_WRAP_6, hex)
+    GENERATE_FIELD(PARAM_WRAP_5, hex)
+    GENERATE_FIELD(PARAM_WRAP_4, hex)
+    GENERATE_FIELD(PARAM_WRAP_3, hex)
+    GENERATE_FIELD(PARAM_WRAP_2, hex)
+    GENERATE_FIELD(PARAM_WRAP_1, hex)
+    GENERATE_FIELD(PARAM_WRAP_0, hex)
+END_REGISTER(SQ_WRAPPING_0)
+
+START_REGISTER(SQ_WRAPPING_1)
+    GENERATE_FIELD(PARAM_WRAP_15, hex)
+    GENERATE_FIELD(PARAM_WRAP_14, hex)
+    GENERATE_FIELD(PARAM_WRAP_13, hex)
+    GENERATE_FIELD(PARAM_WRAP_12, hex)
+    GENERATE_FIELD(PARAM_WRAP_11, hex)
+    GENERATE_FIELD(PARAM_WRAP_10, hex)
+    GENERATE_FIELD(PARAM_WRAP_9, hex)
+    GENERATE_FIELD(PARAM_WRAP_8, hex)
+END_REGISTER(SQ_WRAPPING_1)
+
+START_REGISTER(SQ_VS_CONST)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_VS_CONST)
+
+START_REGISTER(SQ_PS_CONST)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(SQ_PS_CONST)
+
+START_REGISTER(SQ_CONTEXT_MISC)
+    GENERATE_FIELD(TX_CACHE_SEL, int)
+    GENERATE_FIELD(YEILD_OPTIMIZE, int)
+    GENERATE_FIELD(PERFCOUNTER_REF, int)
+    GENERATE_FIELD(PARAM_GEN_POS, int)
+    GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl)
+    GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int)
+    GENERATE_FIELD(INST_PRED_OPTIMIZE, int)
+END_REGISTER(SQ_CONTEXT_MISC)
+
+START_REGISTER(SQ_CF_RD_BASE)
+    GENERATE_FIELD(RD_BASE, hex)
+END_REGISTER(SQ_CF_RD_BASE)
+
+START_REGISTER(SQ_DEBUG_MISC_0)
+    GENERATE_FIELD(DB_PROB_COUNT, int)
+    GENERATE_FIELD(DB_PROB_ADDR, int)
+    GENERATE_FIELD(DB_PROB_BREAK, int)
+    GENERATE_FIELD(DB_PROB_ON, int)
+END_REGISTER(SQ_DEBUG_MISC_0)
+
+START_REGISTER(SQ_DEBUG_MISC_1)
+    GENERATE_FIELD(DB_BREAK_ADDR, int)
+    GENERATE_FIELD(DB_INST_COUNT, int)
+    GENERATE_FIELD(DB_ON_VTX, int)
+    GENERATE_FIELD(DB_ON_PIX, int)
+END_REGISTER(SQ_DEBUG_MISC_1)
+
+START_REGISTER(MH_ARBITER_CONFIG)
+    GENERATE_FIELD(PA_CLNT_ENABLE, bool)
+    GENERATE_FIELD(RB_CLNT_ENABLE, bool)
+    GENERATE_FIELD(TC_CLNT_ENABLE, bool)
+    GENERATE_FIELD(VGT_CLNT_ENABLE, bool)
+    GENERATE_FIELD(CP_CLNT_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT, int)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool)
+    GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool)
+    GENERATE_FIELD(TC_REORDER_ENABLE, bool)
+    GENERATE_FIELD(PAGE_SIZE, int)
+    GENERATE_FIELD(L2_ARB_CONTROL, int)
+    GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int)
+    GENERATE_FIELD(L1_ARB_ENABLE, bool)
+    GENERATE_FIELD(SAME_PAGE_GRANULARITY, int)
+    GENERATE_FIELD(SAME_PAGE_LIMIT, int)
+END_REGISTER(MH_ARBITER_CONFIG)
+
+START_REGISTER(MH_CLNT_AXI_ID_REUSE)
+    GENERATE_FIELD(PAw_ID, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(MMUr_ID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(RBw_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(CPw_ID, int)
+END_REGISTER(MH_CLNT_AXI_ID_REUSE)
+
+START_REGISTER(MH_INTERRUPT_MASK)
+    GENERATE_FIELD(MMU_PAGE_FAULT, bool)
+    GENERATE_FIELD(AXI_WRITE_ERROR, bool)
+    GENERATE_FIELD(AXI_READ_ERROR, bool)
+END_REGISTER(MH_INTERRUPT_MASK)
+
+START_REGISTER(MH_INTERRUPT_STATUS)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+END_REGISTER(MH_INTERRUPT_STATUS)
+
+START_REGISTER(MH_INTERRUPT_CLEAR)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+END_REGISTER(MH_INTERRUPT_CLEAR)
+
+START_REGISTER(MH_AXI_ERROR)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ID, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_READ_ID, int)
+END_REGISTER(MH_AXI_ERROR)
+
+START_REGISTER(MH_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER0_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER1_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER0_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER0_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER1_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER1_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER0_LOW)
+
+START_REGISTER(MH_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER1_LOW)
+
+START_REGISTER(MH_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER0_HI)
+
+START_REGISTER(MH_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER1_HI)
+
+START_REGISTER(MH_DEBUG_CTRL)
+    GENERATE_FIELD(INDEX, int)
+END_REGISTER(MH_DEBUG_CTRL)
+
+START_REGISTER(MH_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(MH_DEBUG_DATA)
+
+START_REGISTER(MH_AXI_HALT_CONTROL)
+    GENERATE_FIELD(AXI_HALT, bool)
+END_REGISTER(MH_AXI_HALT_CONTROL)
+
+START_REGISTER(MH_MMU_CONFIG)
+    GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(SPLIT_MODE_ENABLE, bool)
+    GENERATE_FIELD(MMU_ENABLE, bool)
+END_REGISTER(MH_MMU_CONFIG)
+
+START_REGISTER(MH_MMU_VA_RANGE)
+    GENERATE_FIELD(VA_BASE, int)
+    GENERATE_FIELD(NUM_64KB_REGIONS, int)
+END_REGISTER(MH_MMU_VA_RANGE)
+
+START_REGISTER(MH_MMU_PT_BASE)
+    GENERATE_FIELD(PT_BASE, int)
+END_REGISTER(MH_MMU_PT_BASE)
+
+START_REGISTER(MH_MMU_PAGE_FAULT)
+    GENERATE_FIELD(REQ_VA, int)
+    GENERATE_FIELD(WRITE_PROTECTION_ERROR, int)
+    GENERATE_FIELD(READ_PROTECTION_ERROR, int)
+    GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(AXI_ID, int)
+    GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(OP_TYPE, int)
+    GENERATE_FIELD(PAGE_FAULT, int)
+END_REGISTER(MH_MMU_PAGE_FAULT)
+
+START_REGISTER(MH_MMU_TRAN_ERROR)
+    GENERATE_FIELD(TRAN_ERROR, int)
+END_REGISTER(MH_MMU_TRAN_ERROR)
+
+START_REGISTER(MH_MMU_INVALIDATE)
+    GENERATE_FIELD(INVALIDATE_TC, int)
+    GENERATE_FIELD(INVALIDATE_ALL, int)
+END_REGISTER(MH_MMU_INVALIDATE)
+
+START_REGISTER(MH_MMU_MPU_BASE)
+    GENERATE_FIELD(MPU_BASE, int)
+END_REGISTER(MH_MMU_MPU_BASE)
+
+START_REGISTER(MH_MMU_MPU_END)
+    GENERATE_FIELD(MPU_END, int)
+END_REGISTER(MH_MMU_MPU_END)
+
+START_REGISTER(WAIT_UNTIL)
+    GENERATE_FIELD(CMDFIFO_ENTRIES, int)
+    GENERATE_FIELD(WAIT_3D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_2D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_3D_IDLE, int)
+    GENERATE_FIELD(WAIT_2D_IDLE, int)
+    GENERATE_FIELD(WAIT_CMDFIFO, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID2, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID1, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID0, int)
+    GENERATE_FIELD(WAIT_VSYNC, int)
+    GENERATE_FIELD(WAIT_FE_VSYNC, int)
+    GENERATE_FIELD(WAIT_RE_VSYNC, int)
+END_REGISTER(WAIT_UNTIL)
+
+START_REGISTER(RBBM_ISYNC_CNTL)
+    GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int)
+    GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int)
+END_REGISTER(RBBM_ISYNC_CNTL)
+
+START_REGISTER(RBBM_STATUS)
+    GENERATE_FIELD(GUI_ACTIVE, int)
+    GENERATE_FIELD(RB_CNTX_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX0_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX17_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(PA_BUSY, int)
+    GENERATE_FIELD(SC_CNTX_BUSY, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(SX_BUSY, int)
+    GENERATE_FIELD(MH_COHERENCY_BUSY, int)
+    GENERATE_FIELD(MH_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(RBBM_WU_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY_NO_DMA, int)
+    GENERATE_FIELD(PFRQ_PENDING, int)
+    GENERATE_FIELD(CFRQ_PENDING, int)
+    GENERATE_FIELD(CPRQ_PENDING, int)
+    GENERATE_FIELD(HIRQ_PENDING, int)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(CMDFIFO_AVAIL, int)
+END_REGISTER(RBBM_STATUS)
+
+START_REGISTER(RBBM_DSPLY)
+    GENERATE_FIELD(DMI_CH4_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH4_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH3_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH3_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CHANNEL_SELECT, int)
+    GENERATE_FIELD(DMI_CH2_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH2_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH1_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH1_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID0, int)
+    GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int)
+END_REGISTER(RBBM_DSPLY)
+
+START_REGISTER(RBBM_RENDER_LATEST)
+    GENERATE_FIELD(DMI_CH4_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH3_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH2_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH1_BUFFER_ID, int)
+END_REGISTER(RBBM_RENDER_LATEST)
+
+START_REGISTER(RBBM_RTL_RELEASE)
+    GENERATE_FIELD(CHANGELIST, int)
+END_REGISTER(RBBM_RTL_RELEASE)
+
+START_REGISTER(RBBM_PATCH_RELEASE)
+    GENERATE_FIELD(CUSTOMER_ID, int)
+    GENERATE_FIELD(PATCH_SELECTION, int)
+    GENERATE_FIELD(PATCH_REVISION, int)
+END_REGISTER(RBBM_PATCH_RELEASE)
+
+START_REGISTER(RBBM_AUXILIARY_CONFIG)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(RBBM_AUXILIARY_CONFIG)
+
+START_REGISTER(RBBM_PERIPHID0)
+    GENERATE_FIELD(PARTNUMBER0, int)
+END_REGISTER(RBBM_PERIPHID0)
+
+START_REGISTER(RBBM_PERIPHID1)
+    GENERATE_FIELD(DESIGNER0, int)
+    GENERATE_FIELD(PARTNUMBER1, int)
+END_REGISTER(RBBM_PERIPHID1)
+
+START_REGISTER(RBBM_PERIPHID2)
+    GENERATE_FIELD(REVISION, int)
+    GENERATE_FIELD(DESIGNER1, int)
+END_REGISTER(RBBM_PERIPHID2)
+
+START_REGISTER(RBBM_PERIPHID3)
+    GENERATE_FIELD(CONTINUATION, int)
+    GENERATE_FIELD(MH_INTERFACE, int)
+    GENERATE_FIELD(GARB_SLAVE_INTERFACE, int)
+    GENERATE_FIELD(RBBM_HOST_INTERFACE, int)
+END_REGISTER(RBBM_PERIPHID3)
+
+START_REGISTER(RBBM_CNTL)
+    GENERATE_FIELD(REGCLK_DEASSERT_TIME, int)
+    GENERATE_FIELD(READ_TIMEOUT, int)
+END_REGISTER(RBBM_CNTL)
+
+START_REGISTER(RBBM_SKEW_CNTL)
+    GENERATE_FIELD(SKEW_COUNT, int)
+    GENERATE_FIELD(SKEW_TOP_THRESHOLD, int)
+END_REGISTER(RBBM_SKEW_CNTL)
+
+START_REGISTER(RBBM_SOFT_RESET)
+    GENERATE_FIELD(SOFT_RESET_VGT, int)
+    GENERATE_FIELD(SOFT_RESET_SC, int)
+    GENERATE_FIELD(SOFT_RESET_CIB, int)
+    GENERATE_FIELD(SOFT_RESET_SX, int)
+    GENERATE_FIELD(SOFT_RESET_SQ, int)
+    GENERATE_FIELD(SOFT_RESET_BC, int)
+    GENERATE_FIELD(SOFT_RESET_MH, int)
+    GENERATE_FIELD(SOFT_RESET_PA, int)
+    GENERATE_FIELD(SOFT_RESET_CP, int)
+END_REGISTER(RBBM_SOFT_RESET)
+
+START_REGISTER(RBBM_PM_OVERRIDE1)
+    GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE1)
+
+START_REGISTER(RBBM_PM_OVERRIDE2)
+    GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int)
+    GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE2)
+
+START_REGISTER(GC_SYS_IDLE)
+    GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int)
+    GENERATE_FIELD(GC_SYS_IDLE_DELAY, int)
+END_REGISTER(GC_SYS_IDLE)
+
+START_REGISTER(NQWAIT_UNTIL)
+    GENERATE_FIELD(WAIT_GUI_IDLE, int)
+END_REGISTER(NQWAIT_UNTIL)
+
+START_REGISTER(RBBM_DEBUG_OUT)
+    GENERATE_FIELD(DEBUG_BUS_OUT, int)
+END_REGISTER(RBBM_DEBUG_OUT)
+
+START_REGISTER(RBBM_DEBUG_CNTL)
+    GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int)
+    GENERATE_FIELD(SW_ENABLE, int)
+    GENERATE_FIELD(SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(SUB_BLOCK_ADDR, int)
+END_REGISTER(RBBM_DEBUG_CNTL)
+
+START_REGISTER(RBBM_DEBUG)
+    GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int)
+    GENERATE_FIELD(SQ_RBBM_NRTRTR, int)
+    GENERATE_FIELD(VGT_RBBM_NRTRTR, int)
+    GENERATE_FIELD(CP_RBBM_NRTRTR, int)
+    GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_RTR_FOR_HI, int)
+    GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_WU, int)
+    GENERATE_FIELD(IGNORE_RTR, int)
+END_REGISTER(RBBM_DEBUG)
+
+START_REGISTER(RBBM_READ_ERROR)
+    GENERATE_FIELD(READ_ERROR, int)
+    GENERATE_FIELD(READ_REQUESTER, int)
+    GENERATE_FIELD(READ_ADDRESS, int)
+END_REGISTER(RBBM_READ_ERROR)
+
+START_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+    GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int)
+END_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+
+START_REGISTER(RBBM_INT_CNTL)
+    GENERATE_FIELD(GUI_IDLE_INT_MASK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int)
+    GENERATE_FIELD(RDERR_INT_MASK, int)
+END_REGISTER(RBBM_INT_CNTL)
+
+START_REGISTER(RBBM_INT_STATUS)
+    GENERATE_FIELD(GUI_IDLE_INT_STAT, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int)
+    GENERATE_FIELD(RDERR_INT_STAT, int)
+END_REGISTER(RBBM_INT_STATUS)
+
+START_REGISTER(RBBM_INT_ACK)
+    GENERATE_FIELD(GUI_IDLE_INT_ACK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int)
+    GENERATE_FIELD(RDERR_INT_ACK, int)
+END_REGISTER(RBBM_INT_ACK)
+
+START_REGISTER(MASTER_INT_SIGNAL)
+    GENERATE_FIELD(RBBM_INT_STAT, int)
+    GENERATE_FIELD(CP_INT_STAT, int)
+    GENERATE_FIELD(SQ_INT_STAT, int)
+    GENERATE_FIELD(MH_INT_STAT, int)
+END_REGISTER(MASTER_INT_SIGNAL)
+
+START_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL)
+END_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(RBBM_PERFCOUNTER1_LO)
+    GENERATE_FIELD(PERF_COUNT1_LO, int)
+END_REGISTER(RBBM_PERFCOUNTER1_LO)
+
+START_REGISTER(RBBM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT1_HI, int)
+END_REGISTER(RBBM_PERFCOUNTER1_HI)
+
+START_REGISTER(CP_RB_BASE)
+    GENERATE_FIELD(RB_BASE, int)
+END_REGISTER(CP_RB_BASE)
+
+START_REGISTER(CP_RB_CNTL)
+    GENERATE_FIELD(RB_RPTR_WR_ENA, int)
+    GENERATE_FIELD(RB_NO_UPDATE, int)
+    GENERATE_FIELD(RB_POLL_EN, int)
+    GENERATE_FIELD(BUF_SWAP, int)
+    GENERATE_FIELD(RB_BLKSZ, int)
+    GENERATE_FIELD(RB_BUFSZ, int)
+END_REGISTER(CP_RB_CNTL)
+
+START_REGISTER(CP_RB_RPTR_ADDR)
+    GENERATE_FIELD(RB_RPTR_ADDR, int)
+    GENERATE_FIELD(RB_RPTR_SWAP, int)
+END_REGISTER(CP_RB_RPTR_ADDR)
+
+START_REGISTER(CP_RB_RPTR)
+    GENERATE_FIELD(RB_RPTR, int)
+END_REGISTER(CP_RB_RPTR)
+
+START_REGISTER(CP_RB_RPTR_WR)
+    GENERATE_FIELD(RB_RPTR_WR, int)
+END_REGISTER(CP_RB_RPTR_WR)
+
+START_REGISTER(CP_RB_WPTR)
+    GENERATE_FIELD(RB_WPTR, int)
+END_REGISTER(CP_RB_WPTR)
+
+START_REGISTER(CP_RB_WPTR_DELAY)
+    GENERATE_FIELD(PRE_WRITE_LIMIT, int)
+    GENERATE_FIELD(PRE_WRITE_TIMER, int)
+END_REGISTER(CP_RB_WPTR_DELAY)
+
+START_REGISTER(CP_RB_WPTR_BASE)
+    GENERATE_FIELD(RB_WPTR_BASE, int)
+    GENERATE_FIELD(RB_WPTR_SWAP, int)
+END_REGISTER(CP_RB_WPTR_BASE)
+
+START_REGISTER(CP_IB1_BASE)
+    GENERATE_FIELD(IB1_BASE, int)
+END_REGISTER(CP_IB1_BASE)
+
+START_REGISTER(CP_IB1_BUFSZ)
+    GENERATE_FIELD(IB1_BUFSZ, int)
+END_REGISTER(CP_IB1_BUFSZ)
+
+START_REGISTER(CP_IB2_BASE)
+    GENERATE_FIELD(IB2_BASE, int)
+END_REGISTER(CP_IB2_BASE)
+
+START_REGISTER(CP_IB2_BUFSZ)
+    GENERATE_FIELD(IB2_BUFSZ, int)
+END_REGISTER(CP_IB2_BUFSZ)
+
+START_REGISTER(CP_ST_BASE)
+    GENERATE_FIELD(ST_BASE, int)
+END_REGISTER(CP_ST_BASE)
+
+START_REGISTER(CP_ST_BUFSZ)
+    GENERATE_FIELD(ST_BUFSZ, int)
+END_REGISTER(CP_ST_BUFSZ)
+
+START_REGISTER(CP_QUEUE_THRESHOLDS)
+    GENERATE_FIELD(CSQ_ST_START, int)
+    GENERATE_FIELD(CSQ_IB2_START, int)
+    GENERATE_FIELD(CSQ_IB1_START, int)
+END_REGISTER(CP_QUEUE_THRESHOLDS)
+
+START_REGISTER(CP_MEQ_THRESHOLDS)
+    GENERATE_FIELD(ROQ_END, int)
+    GENERATE_FIELD(MEQ_END, int)
+END_REGISTER(CP_MEQ_THRESHOLDS)
+
+START_REGISTER(CP_CSQ_AVAIL)
+    GENERATE_FIELD(CSQ_CNT_IB2, int)
+    GENERATE_FIELD(CSQ_CNT_IB1, int)
+    GENERATE_FIELD(CSQ_CNT_RING, int)
+END_REGISTER(CP_CSQ_AVAIL)
+
+START_REGISTER(CP_STQ_AVAIL)
+    GENERATE_FIELD(STQ_CNT_ST, int)
+END_REGISTER(CP_STQ_AVAIL)
+
+START_REGISTER(CP_MEQ_AVAIL)
+    GENERATE_FIELD(MEQ_CNT, int)
+END_REGISTER(CP_MEQ_AVAIL)
+
+START_REGISTER(CP_CSQ_RB_STAT)
+    GENERATE_FIELD(CSQ_WPTR_PRIMARY, int)
+    GENERATE_FIELD(CSQ_RPTR_PRIMARY, int)
+END_REGISTER(CP_CSQ_RB_STAT)
+
+START_REGISTER(CP_CSQ_IB1_STAT)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int)
+END_REGISTER(CP_CSQ_IB1_STAT)
+
+START_REGISTER(CP_CSQ_IB2_STAT)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int)
+END_REGISTER(CP_CSQ_IB2_STAT)
+
+START_REGISTER(CP_NON_PREFETCH_CNTRS)
+    GENERATE_FIELD(IB2_COUNTER, int)
+    GENERATE_FIELD(IB1_COUNTER, int)
+END_REGISTER(CP_NON_PREFETCH_CNTRS)
+
+START_REGISTER(CP_STQ_ST_STAT)
+    GENERATE_FIELD(STQ_WPTR_ST, int)
+    GENERATE_FIELD(STQ_RPTR_ST, int)
+END_REGISTER(CP_STQ_ST_STAT)
+
+START_REGISTER(CP_MEQ_STAT)
+    GENERATE_FIELD(MEQ_WPTR, int)
+    GENERATE_FIELD(MEQ_RPTR, int)
+END_REGISTER(CP_MEQ_STAT)
+
+START_REGISTER(CP_MIU_TAG_STAT)
+    GENERATE_FIELD(INVALID_RETURN_TAG, int)
+    GENERATE_FIELD(TAG_17_STAT, int)
+    GENERATE_FIELD(TAG_16_STAT, int)
+    GENERATE_FIELD(TAG_15_STAT, int)
+    GENERATE_FIELD(TAG_14_STAT, int)
+    GENERATE_FIELD(TAG_13_STAT, int)
+    GENERATE_FIELD(TAG_12_STAT, int)
+    GENERATE_FIELD(TAG_11_STAT, int)
+    GENERATE_FIELD(TAG_10_STAT, int)
+    GENERATE_FIELD(TAG_9_STAT, int)
+    GENERATE_FIELD(TAG_8_STAT, int)
+    GENERATE_FIELD(TAG_7_STAT, int)
+    GENERATE_FIELD(TAG_6_STAT, int)
+    GENERATE_FIELD(TAG_5_STAT, int)
+    GENERATE_FIELD(TAG_4_STAT, int)
+    GENERATE_FIELD(TAG_3_STAT, int)
+    GENERATE_FIELD(TAG_2_STAT, int)
+    GENERATE_FIELD(TAG_1_STAT, int)
+    GENERATE_FIELD(TAG_0_STAT, int)
+END_REGISTER(CP_MIU_TAG_STAT)
+
+START_REGISTER(CP_CMD_INDEX)
+    GENERATE_FIELD(CMD_QUEUE_SEL, int)
+    GENERATE_FIELD(CMD_INDEX, int)
+END_REGISTER(CP_CMD_INDEX)
+
+START_REGISTER(CP_CMD_DATA)
+    GENERATE_FIELD(CMD_DATA, int)
+END_REGISTER(CP_CMD_DATA)
+
+START_REGISTER(CP_ME_CNTL)
+    GENERATE_FIELD(PROG_CNT_SIZE, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(ME_HALT, int)
+    GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_STATMUX, int)
+END_REGISTER(CP_ME_CNTL)
+
+START_REGISTER(CP_ME_STATUS)
+    GENERATE_FIELD(ME_DEBUG_DATA, int)
+END_REGISTER(CP_ME_STATUS)
+
+START_REGISTER(CP_ME_RAM_WADDR)
+    GENERATE_FIELD(ME_RAM_WADDR, int)
+END_REGISTER(CP_ME_RAM_WADDR)
+
+START_REGISTER(CP_ME_RAM_RADDR)
+    GENERATE_FIELD(ME_RAM_RADDR, int)
+END_REGISTER(CP_ME_RAM_RADDR)
+
+START_REGISTER(CP_ME_RAM_DATA)
+    GENERATE_FIELD(ME_RAM_DATA, int)
+END_REGISTER(CP_ME_RAM_DATA)
+
+START_REGISTER(CP_ME_RDADDR)
+    GENERATE_FIELD(ME_RDADDR, int)
+END_REGISTER(CP_ME_RDADDR)
+
+START_REGISTER(CP_DEBUG)
+    GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int)
+    GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int)
+    GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int)
+    GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int)
+    GENERATE_FIELD(PREFETCH_PASS_NOPS, int)
+    GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int)
+    GENERATE_FIELD(PROG_END_PTR_ENABLE, int)
+    GENERATE_FIELD(PREDICATE_DISABLE, int)
+    GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int)
+END_REGISTER(CP_DEBUG)
+
+START_REGISTER(SCRATCH_REG0)
+    GENERATE_FIELD(SCRATCH_REG0, int)
+END_REGISTER(SCRATCH_REG0)
+
+START_REGISTER(SCRATCH_REG1)
+    GENERATE_FIELD(SCRATCH_REG1, int)
+END_REGISTER(SCRATCH_REG1)
+
+START_REGISTER(SCRATCH_REG2)
+    GENERATE_FIELD(SCRATCH_REG2, int)
+END_REGISTER(SCRATCH_REG2)
+
+START_REGISTER(SCRATCH_REG3)
+    GENERATE_FIELD(SCRATCH_REG3, int)
+END_REGISTER(SCRATCH_REG3)
+
+START_REGISTER(SCRATCH_REG4)
+    GENERATE_FIELD(SCRATCH_REG4, int)
+END_REGISTER(SCRATCH_REG4)
+
+START_REGISTER(SCRATCH_REG5)
+    GENERATE_FIELD(SCRATCH_REG5, int)
+END_REGISTER(SCRATCH_REG5)
+
+START_REGISTER(SCRATCH_REG6)
+    GENERATE_FIELD(SCRATCH_REG6, int)
+END_REGISTER(SCRATCH_REG6)
+
+START_REGISTER(SCRATCH_REG7)
+    GENERATE_FIELD(SCRATCH_REG7, int)
+END_REGISTER(SCRATCH_REG7)
+
+START_REGISTER(SCRATCH_UMSK)
+    GENERATE_FIELD(SCRATCH_SWAP, int)
+    GENERATE_FIELD(SCRATCH_UMSK, int)
+END_REGISTER(SCRATCH_UMSK)
+
+START_REGISTER(SCRATCH_ADDR)
+    GENERATE_FIELD(SCRATCH_ADDR, hex)
+END_REGISTER(SCRATCH_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_SRC)
+    GENERATE_FIELD(VS_DONE_CNTR, int)
+    GENERATE_FIELD(VS_DONE_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_SRC)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR)
+    GENERATE_FIELD(VS_DONE_ADDR, int)
+    GENERATE_FIELD(VS_DONE_SWAP, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA)
+    GENERATE_FIELD(VS_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(VS_DONE_ADDR_SWM, int)
+    GENERATE_FIELD(VS_DONE_SWAP_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+    GENERATE_FIELD(VS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_SRC)
+    GENERATE_FIELD(PS_DONE_CNTR, int)
+    GENERATE_FIELD(PS_DONE_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_SRC)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR)
+    GENERATE_FIELD(PS_DONE_ADDR, int)
+    GENERATE_FIELD(PS_DONE_SWAP, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA)
+    GENERATE_FIELD(PS_DONE_DATA, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(PS_DONE_ADDR_SWM, int)
+    GENERATE_FIELD(PS_DONE_SWAP_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+    GENERATE_FIELD(PS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_CF_EVENT_SRC)
+    GENERATE_FIELD(CF_DONE_SRC, int)
+END_REGISTER(CP_ME_CF_EVENT_SRC)
+
+START_REGISTER(CP_ME_CF_EVENT_ADDR)
+    GENERATE_FIELD(CF_DONE_ADDR, int)
+    GENERATE_FIELD(CF_DONE_SWAP, int)
+END_REGISTER(CP_ME_CF_EVENT_ADDR)
+
+START_REGISTER(CP_ME_CF_EVENT_DATA)
+    GENERATE_FIELD(CF_DONE_DATA, int)
+END_REGISTER(CP_ME_CF_EVENT_DATA)
+
+START_REGISTER(CP_ME_NRT_ADDR)
+    GENERATE_FIELD(NRT_WRITE_ADDR, int)
+    GENERATE_FIELD(NRT_WRITE_SWAP, int)
+END_REGISTER(CP_ME_NRT_ADDR)
+
+START_REGISTER(CP_ME_NRT_DATA)
+    GENERATE_FIELD(NRT_WRITE_DATA, int)
+END_REGISTER(CP_ME_NRT_DATA)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+    GENERATE_FIELD(VS_FETCH_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+    GENERATE_FIELD(VS_FETCH_DONE_ADDR, int)
+    GENERATE_FIELD(VS_FETCH_DONE_SWAP, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+    GENERATE_FIELD(VS_FETCH_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+
+START_REGISTER(CP_INT_CNTL)
+    GENERATE_FIELD(RB_INT_MASK, int)
+    GENERATE_FIELD(IB1_INT_MASK, int)
+    GENERATE_FIELD(IB2_INT_MASK, int)
+    GENERATE_FIELD(IB_ERROR_MASK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int)
+    GENERATE_FIELD(OPCODE_ERROR_MASK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int)
+    GENERATE_FIELD(SW_INT_MASK, int)
+END_REGISTER(CP_INT_CNTL)
+
+START_REGISTER(CP_INT_STATUS)
+    GENERATE_FIELD(RB_INT_STAT, int)
+    GENERATE_FIELD(IB1_INT_STAT, int)
+    GENERATE_FIELD(IB2_INT_STAT, int)
+    GENERATE_FIELD(IB_ERROR_STAT, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int)
+    GENERATE_FIELD(OPCODE_ERROR_STAT, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int)
+    GENERATE_FIELD(SW_INT_STAT, int)
+END_REGISTER(CP_INT_STATUS)
+
+START_REGISTER(CP_INT_ACK)
+    GENERATE_FIELD(RB_INT_ACK, int)
+    GENERATE_FIELD(IB1_INT_ACK, int)
+    GENERATE_FIELD(IB2_INT_ACK, int)
+    GENERATE_FIELD(IB_ERROR_ACK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int)
+    GENERATE_FIELD(OPCODE_ERROR_ACK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int)
+    GENERATE_FIELD(SW_INT_ACK, int)
+END_REGISTER(CP_INT_ACK)
+
+START_REGISTER(CP_PFP_UCODE_ADDR)
+    GENERATE_FIELD(UCODE_ADDR, hex)
+END_REGISTER(CP_PFP_UCODE_ADDR)
+
+START_REGISTER(CP_PFP_UCODE_DATA)
+    GENERATE_FIELD(UCODE_DATA, hex)
+END_REGISTER(CP_PFP_UCODE_DATA)
+
+START_REGISTER(CP_PERFMON_CNTL)
+    GENERATE_FIELD(PERFMON_ENABLE_MODE, int)
+    GENERATE_FIELD(PERFMON_STATE, int)
+END_REGISTER(CP_PERFMON_CNTL)
+
+START_REGISTER(CP_PERFCOUNTER_SELECT)
+    GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL)
+END_REGISTER(CP_PERFCOUNTER_SELECT)
+
+START_REGISTER(CP_PERFCOUNTER_LO)
+    GENERATE_FIELD(PERFCOUNT_LO, int)
+END_REGISTER(CP_PERFCOUNTER_LO)
+
+START_REGISTER(CP_PERFCOUNTER_HI)
+    GENERATE_FIELD(PERFCOUNT_HI, int)
+END_REGISTER(CP_PERFCOUNTER_HI)
+
+START_REGISTER(CP_BIN_MASK_LO)
+    GENERATE_FIELD(BIN_MASK_LO, int)
+END_REGISTER(CP_BIN_MASK_LO)
+
+START_REGISTER(CP_BIN_MASK_HI)
+    GENERATE_FIELD(BIN_MASK_HI, int)
+END_REGISTER(CP_BIN_MASK_HI)
+
+START_REGISTER(CP_BIN_SELECT_LO)
+    GENERATE_FIELD(BIN_SELECT_LO, int)
+END_REGISTER(CP_BIN_SELECT_LO)
+
+START_REGISTER(CP_BIN_SELECT_HI)
+    GENERATE_FIELD(BIN_SELECT_HI, int)
+END_REGISTER(CP_BIN_SELECT_HI)
+
+START_REGISTER(CP_NV_FLAGS_0)
+    GENERATE_FIELD(END_RCVD_15, int)
+    GENERATE_FIELD(DISCARD_15, int)
+    GENERATE_FIELD(END_RCVD_14, int)
+    GENERATE_FIELD(DISCARD_14, int)
+    GENERATE_FIELD(END_RCVD_13, int)
+    GENERATE_FIELD(DISCARD_13, int)
+    GENERATE_FIELD(END_RCVD_12, int)
+    GENERATE_FIELD(DISCARD_12, int)
+    GENERATE_FIELD(END_RCVD_11, int)
+    GENERATE_FIELD(DISCARD_11, int)
+    GENERATE_FIELD(END_RCVD_10, int)
+    GENERATE_FIELD(DISCARD_10, int)
+    GENERATE_FIELD(END_RCVD_9, int)
+    GENERATE_FIELD(DISCARD_9, int)
+    GENERATE_FIELD(END_RCVD_8, int)
+    GENERATE_FIELD(DISCARD_8, int)
+    GENERATE_FIELD(END_RCVD_7, int)
+    GENERATE_FIELD(DISCARD_7, int)
+    GENERATE_FIELD(END_RCVD_6, int)
+    GENERATE_FIELD(DISCARD_6, int)
+    GENERATE_FIELD(END_RCVD_5, int)
+    GENERATE_FIELD(DISCARD_5, int)
+    GENERATE_FIELD(END_RCVD_4, int)
+    GENERATE_FIELD(DISCARD_4, int)
+    GENERATE_FIELD(END_RCVD_3, int)
+    GENERATE_FIELD(DISCARD_3, int)
+    GENERATE_FIELD(END_RCVD_2, int)
+    GENERATE_FIELD(DISCARD_2, int)
+    GENERATE_FIELD(END_RCVD_1, int)
+    GENERATE_FIELD(DISCARD_1, int)
+    GENERATE_FIELD(END_RCVD_0, int)
+    GENERATE_FIELD(DISCARD_0, int)
+END_REGISTER(CP_NV_FLAGS_0)
+
+START_REGISTER(CP_NV_FLAGS_1)
+    GENERATE_FIELD(END_RCVD_31, int)
+    GENERATE_FIELD(DISCARD_31, int)
+    GENERATE_FIELD(END_RCVD_30, int)
+    GENERATE_FIELD(DISCARD_30, int)
+    GENERATE_FIELD(END_RCVD_29, int)
+    GENERATE_FIELD(DISCARD_29, int)
+    GENERATE_FIELD(END_RCVD_28, int)
+    GENERATE_FIELD(DISCARD_28, int)
+    GENERATE_FIELD(END_RCVD_27, int)
+    GENERATE_FIELD(DISCARD_27, int)
+    GENERATE_FIELD(END_RCVD_26, int)
+    GENERATE_FIELD(DISCARD_26, int)
+    GENERATE_FIELD(END_RCVD_25, int)
+    GENERATE_FIELD(DISCARD_25, int)
+    GENERATE_FIELD(END_RCVD_24, int)
+    GENERATE_FIELD(DISCARD_24, int)
+    GENERATE_FIELD(END_RCVD_23, int)
+    GENERATE_FIELD(DISCARD_23, int)
+    GENERATE_FIELD(END_RCVD_22, int)
+    GENERATE_FIELD(DISCARD_22, int)
+    GENERATE_FIELD(END_RCVD_21, int)
+    GENERATE_FIELD(DISCARD_21, int)
+    GENERATE_FIELD(END_RCVD_20, int)
+    GENERATE_FIELD(DISCARD_20, int)
+    GENERATE_FIELD(END_RCVD_19, int)
+    GENERATE_FIELD(DISCARD_19, int)
+    GENERATE_FIELD(END_RCVD_18, int)
+    GENERATE_FIELD(DISCARD_18, int)
+    GENERATE_FIELD(END_RCVD_17, int)
+    GENERATE_FIELD(DISCARD_17, int)
+    GENERATE_FIELD(END_RCVD_16, int)
+    GENERATE_FIELD(DISCARD_16, int)
+END_REGISTER(CP_NV_FLAGS_1)
+
+START_REGISTER(CP_NV_FLAGS_2)
+    GENERATE_FIELD(END_RCVD_47, int)
+    GENERATE_FIELD(DISCARD_47, int)
+    GENERATE_FIELD(END_RCVD_46, int)
+    GENERATE_FIELD(DISCARD_46, int)
+    GENERATE_FIELD(END_RCVD_45, int)
+    GENERATE_FIELD(DISCARD_45, int)
+    GENERATE_FIELD(END_RCVD_44, int)
+    GENERATE_FIELD(DISCARD_44, int)
+    GENERATE_FIELD(END_RCVD_43, int)
+    GENERATE_FIELD(DISCARD_43, int)
+    GENERATE_FIELD(END_RCVD_42, int)
+    GENERATE_FIELD(DISCARD_42, int)
+    GENERATE_FIELD(END_RCVD_41, int)
+    GENERATE_FIELD(DISCARD_41, int)
+    GENERATE_FIELD(END_RCVD_40, int)
+    GENERATE_FIELD(DISCARD_40, int)
+    GENERATE_FIELD(END_RCVD_39, int)
+    GENERATE_FIELD(DISCARD_39, int)
+    GENERATE_FIELD(END_RCVD_38, int)
+    GENERATE_FIELD(DISCARD_38, int)
+    GENERATE_FIELD(END_RCVD_37, int)
+    GENERATE_FIELD(DISCARD_37, int)
+    GENERATE_FIELD(END_RCVD_36, int)
+    GENERATE_FIELD(DISCARD_36, int)
+    GENERATE_FIELD(END_RCVD_35, int)
+    GENERATE_FIELD(DISCARD_35, int)
+    GENERATE_FIELD(END_RCVD_34, int)
+    GENERATE_FIELD(DISCARD_34, int)
+    GENERATE_FIELD(END_RCVD_33, int)
+    GENERATE_FIELD(DISCARD_33, int)
+    GENERATE_FIELD(END_RCVD_32, int)
+    GENERATE_FIELD(DISCARD_32, int)
+END_REGISTER(CP_NV_FLAGS_2)
+
+START_REGISTER(CP_NV_FLAGS_3)
+    GENERATE_FIELD(END_RCVD_63, int)
+    GENERATE_FIELD(DISCARD_63, int)
+    GENERATE_FIELD(END_RCVD_62, int)
+    GENERATE_FIELD(DISCARD_62, int)
+    GENERATE_FIELD(END_RCVD_61, int)
+    GENERATE_FIELD(DISCARD_61, int)
+    GENERATE_FIELD(END_RCVD_60, int)
+    GENERATE_FIELD(DISCARD_60, int)
+    GENERATE_FIELD(END_RCVD_59, int)
+    GENERATE_FIELD(DISCARD_59, int)
+    GENERATE_FIELD(END_RCVD_58, int)
+    GENERATE_FIELD(DISCARD_58, int)
+    GENERATE_FIELD(END_RCVD_57, int)
+    GENERATE_FIELD(DISCARD_57, int)
+    GENERATE_FIELD(END_RCVD_56, int)
+    GENERATE_FIELD(DISCARD_56, int)
+    GENERATE_FIELD(END_RCVD_55, int)
+    GENERATE_FIELD(DISCARD_55, int)
+    GENERATE_FIELD(END_RCVD_54, int)
+    GENERATE_FIELD(DISCARD_54, int)
+    GENERATE_FIELD(END_RCVD_53, int)
+    GENERATE_FIELD(DISCARD_53, int)
+    GENERATE_FIELD(END_RCVD_52, int)
+    GENERATE_FIELD(DISCARD_52, int)
+    GENERATE_FIELD(END_RCVD_51, int)
+    GENERATE_FIELD(DISCARD_51, int)
+    GENERATE_FIELD(END_RCVD_50, int)
+    GENERATE_FIELD(DISCARD_50, int)
+    GENERATE_FIELD(END_RCVD_49, int)
+    GENERATE_FIELD(DISCARD_49, int)
+    GENERATE_FIELD(END_RCVD_48, int)
+    GENERATE_FIELD(DISCARD_48, int)
+END_REGISTER(CP_NV_FLAGS_3)
+
+START_REGISTER(CP_STATE_DEBUG_INDEX)
+    GENERATE_FIELD(STATE_DEBUG_INDEX, int)
+END_REGISTER(CP_STATE_DEBUG_INDEX)
+
+START_REGISTER(CP_STATE_DEBUG_DATA)
+    GENERATE_FIELD(STATE_DEBUG_DATA, int)
+END_REGISTER(CP_STATE_DEBUG_DATA)
+
+START_REGISTER(CP_PROG_COUNTER)
+    GENERATE_FIELD(COUNTER, int)
+END_REGISTER(CP_PROG_COUNTER)
+
+START_REGISTER(CP_STAT)
+    GENERATE_FIELD(CP_BUSY, int)
+    GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_WC_BUSY, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(_3D_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(MIU_WC_STALL, int)
+    GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(MEQ_RING_BUSY, int)
+    GENERATE_FIELD(PFP_BUSY, int)
+    GENERATE_FIELD(ST_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int)
+    GENERATE_FIELD(RING_QUEUE_BUSY, int)
+    GENERATE_FIELD(CSF_BUSY, int)
+    GENERATE_FIELD(CSF_ST_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(CSF_RING_BUSY, int)
+    GENERATE_FIELD(RCIU_BUSY, int)
+    GENERATE_FIELD(RBIU_BUSY, int)
+    GENERATE_FIELD(MIU_RD_RETURN_BUSY, int)
+    GENERATE_FIELD(MIU_RD_REQ_BUSY, int)
+    GENERATE_FIELD(MIU_WR_BUSY, int)
+END_REGISTER(CP_STAT)
+
+START_REGISTER(BIOS_0_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_0_SCRATCH)
+
+START_REGISTER(BIOS_1_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_1_SCRATCH)
+
+START_REGISTER(BIOS_2_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_2_SCRATCH)
+
+START_REGISTER(BIOS_3_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_3_SCRATCH)
+
+START_REGISTER(BIOS_4_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_4_SCRATCH)
+
+START_REGISTER(BIOS_5_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_5_SCRATCH)
+
+START_REGISTER(BIOS_6_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_6_SCRATCH)
+
+START_REGISTER(BIOS_7_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_7_SCRATCH)
+
+START_REGISTER(BIOS_8_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_8_SCRATCH)
+
+START_REGISTER(BIOS_9_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_9_SCRATCH)
+
+START_REGISTER(BIOS_10_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_10_SCRATCH)
+
+START_REGISTER(BIOS_11_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_11_SCRATCH)
+
+START_REGISTER(BIOS_12_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_12_SCRATCH)
+
+START_REGISTER(BIOS_13_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_13_SCRATCH)
+
+START_REGISTER(BIOS_14_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_14_SCRATCH)
+
+START_REGISTER(BIOS_15_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_15_SCRATCH)
+
+START_REGISTER(COHER_SIZE_PM4)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_PM4)
+
+START_REGISTER(COHER_BASE_PM4)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(COHER_BASE_PM4)
+
+START_REGISTER(COHER_STATUS_PM4)
+    GENERATE_FIELD(STATUS, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+END_REGISTER(COHER_STATUS_PM4)
+
+START_REGISTER(COHER_SIZE_HOST)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_HOST)
+
+START_REGISTER(COHER_BASE_HOST)
+    GENERATE_FIELD(BASE, hex)
+END_REGISTER(COHER_BASE_HOST)
+
+START_REGISTER(COHER_STATUS_HOST)
+    GENERATE_FIELD(STATUS, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+END_REGISTER(COHER_STATUS_HOST)
+
+START_REGISTER(COHER_DEST_BASE_0)
+    GENERATE_FIELD(DEST_BASE_0, hex)
+END_REGISTER(COHER_DEST_BASE_0)
+
+START_REGISTER(COHER_DEST_BASE_1)
+    GENERATE_FIELD(DEST_BASE_1, hex)
+END_REGISTER(COHER_DEST_BASE_1)
+
+START_REGISTER(COHER_DEST_BASE_2)
+    GENERATE_FIELD(DEST_BASE_2, hex)
+END_REGISTER(COHER_DEST_BASE_2)
+
+START_REGISTER(COHER_DEST_BASE_3)
+    GENERATE_FIELD(DEST_BASE_3, hex)
+END_REGISTER(COHER_DEST_BASE_3)
+
+START_REGISTER(COHER_DEST_BASE_4)
+    GENERATE_FIELD(DEST_BASE_4, hex)
+END_REGISTER(COHER_DEST_BASE_4)
+
+START_REGISTER(COHER_DEST_BASE_5)
+    GENERATE_FIELD(DEST_BASE_5, hex)
+END_REGISTER(COHER_DEST_BASE_5)
+
+START_REGISTER(COHER_DEST_BASE_6)
+    GENERATE_FIELD(DEST_BASE_6, hex)
+END_REGISTER(COHER_DEST_BASE_6)
+
+START_REGISTER(COHER_DEST_BASE_7)
+    GENERATE_FIELD(DEST_BASE_7, hex)
+END_REGISTER(COHER_DEST_BASE_7)
+
+START_REGISTER(RB_SURFACE_INFO)
+    GENERATE_FIELD(MSAA_SAMPLES, MSAASamples)
+    GENERATE_FIELD(SURFACE_PITCH, uint)
+END_REGISTER(RB_SURFACE_INFO)
+
+START_REGISTER(RB_COLOR_INFO)
+    GENERATE_FIELD(COLOR_BASE, uint)
+    GENERATE_FIELD(COLOR_SWAP, uint)
+    GENERATE_FIELD(COLOR_ENDIAN, uint)
+    GENERATE_FIELD(COLOR_LINEAR, bool)
+    GENERATE_FIELD(COLOR_ROUND_MODE, uint)
+    GENERATE_FIELD(COLOR_FORMAT, ColorformatX)
+END_REGISTER(RB_COLOR_INFO)
+
+START_REGISTER(RB_DEPTH_INFO)
+    GENERATE_FIELD(DEPTH_BASE, uint)
+    GENERATE_FIELD(DEPTH_FORMAT, DepthformatX)
+END_REGISTER(RB_DEPTH_INFO)
+
+START_REGISTER(RB_STENCILREFMASK)
+    GENERATE_FIELD(RESERVED1, bool)
+    GENERATE_FIELD(RESERVED0, bool)
+    GENERATE_FIELD(STENCILWRITEMASK, hex)
+    GENERATE_FIELD(STENCILMASK, hex)
+    GENERATE_FIELD(STENCILREF, hex)
+END_REGISTER(RB_STENCILREFMASK)
+
+START_REGISTER(RB_ALPHA_REF)
+    GENERATE_FIELD(ALPHA_REF, float)
+END_REGISTER(RB_ALPHA_REF)
+
+START_REGISTER(RB_COLOR_MASK)
+    GENERATE_FIELD(RESERVED3, bool)
+    GENERATE_FIELD(RESERVED2, bool)
+    GENERATE_FIELD(WRITE_ALPHA, bool)
+    GENERATE_FIELD(WRITE_BLUE, bool)
+    GENERATE_FIELD(WRITE_GREEN, bool)
+    GENERATE_FIELD(WRITE_RED, bool)
+END_REGISTER(RB_COLOR_MASK)
+
+START_REGISTER(RB_BLEND_RED)
+    GENERATE_FIELD(BLEND_RED, uint)
+END_REGISTER(RB_BLEND_RED)
+
+START_REGISTER(RB_BLEND_GREEN)
+    GENERATE_FIELD(BLEND_GREEN, uint)
+END_REGISTER(RB_BLEND_GREEN)
+
+START_REGISTER(RB_BLEND_BLUE)
+    GENERATE_FIELD(BLEND_BLUE, uint)
+END_REGISTER(RB_BLEND_BLUE)
+
+START_REGISTER(RB_BLEND_ALPHA)
+    GENERATE_FIELD(BLEND_ALPHA, uint)
+END_REGISTER(RB_BLEND_ALPHA)
+
+START_REGISTER(RB_FOG_COLOR)
+    GENERATE_FIELD(FOG_BLUE, uint)
+    GENERATE_FIELD(FOG_GREEN, uint)
+    GENERATE_FIELD(FOG_RED, uint)
+END_REGISTER(RB_FOG_COLOR)
+
+START_REGISTER(RB_STENCILREFMASK_BF)
+    GENERATE_FIELD(RESERVED5, bool)
+    GENERATE_FIELD(RESERVED4, bool)
+    GENERATE_FIELD(STENCILWRITEMASK_BF, hex)
+    GENERATE_FIELD(STENCILMASK_BF, hex)
+    GENERATE_FIELD(STENCILREF_BF, hex)
+END_REGISTER(RB_STENCILREFMASK_BF)
+
+START_REGISTER(RB_DEPTHCONTROL)
+    GENERATE_FIELD(STENCILZFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILZPASS_BF, StencilOp)
+    GENERATE_FIELD(STENCILFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILFUNC_BF, CompareRef)
+    GENERATE_FIELD(STENCILZFAIL, StencilOp)
+    GENERATE_FIELD(STENCILZPASS, StencilOp)
+    GENERATE_FIELD(STENCILFAIL, StencilOp)
+    GENERATE_FIELD(STENCILFUNC, CompareRef)
+    GENERATE_FIELD(BACKFACE_ENABLE, bool)
+    GENERATE_FIELD(ZFUNC, CompareFrag)
+    GENERATE_FIELD(EARLY_Z_ENABLE, bool)
+    GENERATE_FIELD(Z_WRITE_ENABLE, bool)
+    GENERATE_FIELD(Z_ENABLE, bool)
+    GENERATE_FIELD(STENCIL_ENABLE, bool)
+END_REGISTER(RB_DEPTHCONTROL)
+
+START_REGISTER(RB_BLENDCONTROL)
+    GENERATE_FIELD(BLEND_FORCE, bool)
+    GENERATE_FIELD(BLEND_FORCE_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX)
+END_REGISTER(RB_BLENDCONTROL)
+
+START_REGISTER(RB_COLORCONTROL)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex)
+    GENERATE_FIELD(PIXEL_FOG, bool)
+    GENERATE_FIELD(DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(ROP_CODE, uint)
+    GENERATE_FIELD(VS_EXPORTS_FOG, bool)
+    GENERATE_FIELD(FOG_ENABLE, bool)
+    GENERATE_FIELD(BLEND_DISABLE, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_TEST_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_FUNC, CompareRef)
+END_REGISTER(RB_COLORCONTROL)
+
+START_REGISTER(RB_MODECONTROL)
+    GENERATE_FIELD(EDRAM_MODE, EdramMode)
+END_REGISTER(RB_MODECONTROL)
+
+START_REGISTER(RB_COLOR_DEST_MASK)
+    GENERATE_FIELD(COLOR_DEST_MASK, uint)
+END_REGISTER(RB_COLOR_DEST_MASK)
+
+START_REGISTER(RB_COPY_CONTROL)
+    GENERATE_FIELD(CLEAR_MASK, uint)
+    GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool)
+    GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect)
+END_REGISTER(RB_COPY_CONTROL)
+
+START_REGISTER(RB_COPY_DEST_BASE)
+    GENERATE_FIELD(COPY_DEST_BASE, uint)
+END_REGISTER(RB_COPY_DEST_BASE)
+
+START_REGISTER(RB_COPY_DEST_PITCH)
+    GENERATE_FIELD(COPY_DEST_PITCH, uint)
+END_REGISTER(RB_COPY_DEST_PITCH)
+
+START_REGISTER(RB_COPY_DEST_INFO)
+    GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_RED, hex)
+    GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(COPY_DEST_SWAP, uint)
+    GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX)
+    GENERATE_FIELD(COPY_DEST_LINEAR, uint)
+    GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian)
+END_REGISTER(RB_COPY_DEST_INFO)
+
+START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+    GENERATE_FIELD(OFFSET_Y, uint)
+    GENERATE_FIELD(OFFSET_X, uint)
+END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+
+START_REGISTER(RB_DEPTH_CLEAR)
+    GENERATE_FIELD(DEPTH_CLEAR, uint)
+END_REGISTER(RB_DEPTH_CLEAR)
+
+START_REGISTER(RB_SAMPLE_COUNT_CTL)
+    GENERATE_FIELD(COPY_SAMPLE_COUNT, bool)
+    GENERATE_FIELD(RESET_SAMPLE_COUNT, bool)
+END_REGISTER(RB_SAMPLE_COUNT_CTL)
+
+START_REGISTER(RB_SAMPLE_COUNT_ADDR)
+    GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint)
+END_REGISTER(RB_SAMPLE_COUNT_ADDR)
+
+START_REGISTER(RB_BC_CONTROL)
+    GENERATE_FIELD(RESERVED6, bool)
+    GENERATE_FIELD(CRC_SYSTEM, bool)
+    GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool)
+    GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_ALLOC_MASK, uint)
+    GENERATE_FIELD(DISABLE_ACCUM, bool)
+    GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool)
+    GENERATE_FIELD(CRC_MODE, bool)
+    GENERATE_FIELD(ENABLE_CRC_UPDATE, bool)
+    GENERATE_FIELD(AZ_THROTTLE_COUNT, uint)
+    GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool)
+    GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool)
+    GENERATE_FIELD(DISABLE_EDRAM_CAM, bool)
+    GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint)
+    GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool)
+END_REGISTER(RB_BC_CONTROL)
+
+START_REGISTER(RB_EDRAM_INFO)
+    GENERATE_FIELD(EDRAM_RANGE, hex)
+    GENERATE_FIELD(EDRAM_MAPPING_MODE, uint)
+    GENERATE_FIELD(EDRAM_SIZE, EdramSizeX)
+END_REGISTER(RB_EDRAM_INFO)
+
+START_REGISTER(RB_CRC_RD_PORT)
+    GENERATE_FIELD(CRC_DATA, hex)
+END_REGISTER(RB_CRC_RD_PORT)
+
+START_REGISTER(RB_CRC_CONTROL)
+    GENERATE_FIELD(CRC_RD_ADVANCE, bool)
+END_REGISTER(RB_CRC_CONTROL)
+
+START_REGISTER(RB_CRC_MASK)
+    GENERATE_FIELD(CRC_MASK, hex)
+END_REGISTER(RB_CRC_MASK)
+
+START_REGISTER(RB_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT)
+END_REGISTER(RB_PERFCOUNTER0_SELECT)
+
+START_REGISTER(RB_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_LOW)
+
+START_REGISTER(RB_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_HI)
+
+START_REGISTER(RB_TOTAL_SAMPLES)
+    GENERATE_FIELD(TOTAL_SAMPLES, int)
+END_REGISTER(RB_TOTAL_SAMPLES)
+
+START_REGISTER(RB_ZPASS_SAMPLES)
+    GENERATE_FIELD(ZPASS_SAMPLES, int)
+END_REGISTER(RB_ZPASS_SAMPLES)
+
+START_REGISTER(RB_ZFAIL_SAMPLES)
+    GENERATE_FIELD(ZFAIL_SAMPLES, int)
+END_REGISTER(RB_ZFAIL_SAMPLES)
+
+START_REGISTER(RB_SFAIL_SAMPLES)
+    GENERATE_FIELD(SFAIL_SAMPLES, int)
+END_REGISTER(RB_SFAIL_SAMPLES)
+
+START_REGISTER(RB_DEBUG_0)
+    GENERATE_FIELD(EZ_INFSAMP_FULL, bool)
+    GENERATE_FIELD(C_MASK_FULL, bool)
+    GENERATE_FIELD(C_REQ_FULL, bool)
+    GENERATE_FIELD(C_EZ_TILE_FULL, bool)
+    GENERATE_FIELD(C_SX_CMD_FULL, bool)
+    GENERATE_FIELD(C_SX_LAT_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool)
+    GENERATE_FIELD(WRREQ_C0_FULL, bool)
+    GENERATE_FIELD(WRREQ_C1_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z0_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z1_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(RDREQ_C0_FULL, bool)
+    GENERATE_FIELD(RDREQ_C1_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z0_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z1_FULL, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool)
+END_REGISTER(RB_DEBUG_0)
+
+START_REGISTER(RB_DEBUG_1)
+    GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool)
+    GENERATE_FIELD(C_MASK_EMPTY, bool)
+    GENERATE_FIELD(C_REQ_EMPTY, bool)
+    GENERATE_FIELD(C_EZ_TILE_EMPTY, bool)
+    GENERATE_FIELD(C_SX_CMD_EMPTY, bool)
+    GENERATE_FIELD(C_SX_LAT_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool)
+END_REGISTER(RB_DEBUG_1)
+
+START_REGISTER(RB_DEBUG_2)
+    GENERATE_FIELD(Z_TILE_EMPTY, bool)
+    GENERATE_FIELD(Z_SAMP_EMPTY, bool)
+    GENERATE_FIELD(Z1_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z0_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z1_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z0_MASK_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_INFTILE_EMPTY, bool)
+    GENERATE_FIELD(Z_TILE_FULL, bool)
+    GENERATE_FIELD(Z_SAMP_FULL, bool)
+    GENERATE_FIELD(Z1_REQ_FULL, bool)
+    GENERATE_FIELD(Z0_REQ_FULL, bool)
+    GENERATE_FIELD(Z1_MASK_FULL, bool)
+    GENERATE_FIELD(Z0_MASK_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_INFTILE_FULL, bool)
+    GENERATE_FIELD(CURRENT_TILE_EVENT, bool)
+    GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool)
+    GENERATE_FIELD(MEM_EXPORT_FLAG, bool)
+    GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool)
+    GENERATE_FIELD(TILE_FIFO_COUNT, bool)
+END_REGISTER(RB_DEBUG_2)
+
+START_REGISTER(RB_DEBUG_3)
+    GENERATE_FIELD(ZEXP_UPPER_FULL, bool)
+    GENERATE_FIELD(ZEXP_LOWER_FULL, bool)
+    GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool)
+    GENERATE_FIELD(SHD_EMPTY, bool)
+    GENERATE_FIELD(SHD_FULL, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool)
+    GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool)
+    GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool)
+    GENERATE_FIELD(ACCUM_FLUSHING, bool)
+    GENERATE_FIELD(ACCUM_VALID, bool)
+END_REGISTER(RB_DEBUG_3)
+
+START_REGISTER(RB_DEBUG_4)
+    GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool)
+    GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool)
+    GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool)
+END_REGISTER(RB_DEBUG_4)
+
+START_REGISTER(RB_FLAG_CONTROL)
+    GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool)
+END_REGISTER(RB_FLAG_CONTROL)
+
+START_REGISTER(RB_BC_SPARES)
+    GENERATE_FIELD(RESERVED, bool)
+END_REGISTER(RB_BC_SPARES)
+
+START_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+    GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat)
+END_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+
+START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX)
+END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h
new file mode 100644
index 00000000000..c3087908c54
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h
@@ -0,0 +1,5906 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_MASK_HEADER)
+#define _yamato_MASK_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK            0xffffffffL
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK             0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA                  0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK            0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA                 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK             0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA                  0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK            0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA                 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK             0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA                  0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK            0x00000020L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA                 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                    0x00000100L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT                         0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                     0x00000200L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT                          0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                    0x00000400L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT                         0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK               0x00000800L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF                    0x00000800L
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                 0x00010000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE                      0x00010000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK       0x00040000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA            0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK            0x00080000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF                 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK          0x00100000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT               0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                  0x00200000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR                       0x00200000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK                0x00400000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN                     0x00400000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK                 0x00800000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN                      0x00800000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK                 0x01000000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN                      0x01000000L
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK           0x00000001L
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA                0x00000001L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_CL_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_SC_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                    0x00000001L
+#define PA_SU_VTX_CNTL__PIX_CENTER                         0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                    0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                    0x00000038L
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT_MASK                      0x0000ffffL
+#define PA_SU_POINT_SIZE__WIDTH_MASK                       0xffff0000L
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                  0x0000ffffL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                  0xffff0000L
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH_MASK                        0x0000ffffL
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR_MASK                    0xffffffe0L
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT                     0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                 0x00000002L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK                      0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK                      0x00000004L
+#define PA_SU_SC_MODE_CNTL__FACE                           0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK      0x000000e0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK       0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK  0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE       0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK   0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE        0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK   0x00002000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE        0x00002000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK               0x00008000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE                    0x00008000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK  0x00010000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE       0x00010000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK       0x00040000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE            0x00040000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK        0x00080000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST             0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK            0x00100000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS                 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK         0x00200000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA              0x00200000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK         0x00800000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE              0x00800000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK      0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI           0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK        0x20000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS             0x20000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK          0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE               0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK         0x80000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE              0x80000000L
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK          0xffffffffL
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK        0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK           0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK         0xffffffffL
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK          0x00007fffL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK          0x7fff0000L
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK             0x00000007L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK              0x0001e000L
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK_MASK                        0x0000ffffL
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK              0x0000ffffL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK              0x00ff0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK         0x10000000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER              0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK           0x60000000L
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL_MASK                    0x000000ffL
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK                0x00000100L
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL                     0x00000100L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK            0x00000200L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH                 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                   0x00000400L
+#define PA_SC_LINE_CNTL__LAST_PIXEL                        0x00000400L
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                 0x3fff0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE     0x80000000L
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                 0x3fff0000L
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                 0x7fff0000L
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                 0x7fff0000L
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK                0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA                     0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK                 0x0000003eL
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK        0x00000080L
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z             0x00000080L
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK           0xffffffffL
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK         0x0000000fL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK       0x0000ff00L
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                    0x80000000L
+#define PA_CL_CNTL_STATUS__CL_BUSY                         0x80000000L
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                    0x80000000L
+#define PA_SU_CNTL_STATUS__SU_BUSY                         0x80000000L
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY_MASK                    0x80000000L
+#define PA_SC_CNTL_STATUS__SC_BUSY                         0x80000000L
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK    0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write         0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK     0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full          0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK    0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write         0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK     0x00000008L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full          0x00000008L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty   0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full    0x00000020L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty      0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK  0x00000080L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full       0x00000080L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK  0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty       0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK   0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full        0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK  0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty       0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK   0x00000800L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full        0x00000800L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty      0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK       0x00002000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full            0x00002000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty  0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full   0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty  0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full   0x00020000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty    0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full     0x00080000L
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK              0xfff00000L
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet   0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim    0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive  0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK      0x00380000L
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK              0xff000000L
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK             0x001fffffL
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK             0x7f000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK             0x000fff00L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK             0xfc000000L
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event  0x00000080L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK             0xffffff00L
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK             0x00000006L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK             0x00c00000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK             0xf0000000L
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK     0x00000001L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event          0x00000001L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK             0x000000c0L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK             0x00003000L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK             0x000c0000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK          0x00100000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid               0x00100000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait      0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK     0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty          0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK      0x20000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full           0x20000000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK             0x00000030L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK             0x00000c00L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK             0x00180000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet  0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK  0xfc000000L
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK              0xfffffff0L
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK             0x0000001cL
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK   0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty        0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK             0x00007800L
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK   0x00200000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid        0x00200000L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK             0xffc00000L
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK        0x0000000fL
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK       0x000007f0L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK             0x00003800L
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK      0x0003c000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1  0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0  0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK        0x07f00000L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK             0xf8000000L
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK             0x0000000fL
+#define SXIFCCG_DEBUG_REG0__position_address_MASK          0x00000070L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK              0x00000380L
+#define SXIFCCG_DEBUG_REG0__point_address_MASK             0x00001c00L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK              0x0000e000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx   0x00010000L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK              0x00060000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK    0x00780000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK         0x3f800000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK     0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc          0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK     0x80000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel          0x80000000L
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK              0x00000003L
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK            0x0000000cL
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK       0x00000070L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK              0x00000780L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK        0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance             0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK           0x00007000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector  0x00008000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK              0x000f0000L
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK                   0x00100000L
+#define SXIFCCG_DEBUG_REG1__aux_sel                        0x00100000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK              0x00600000L
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK              0x01800000L
+#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK          0xfe000000L
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent_MASK                   0x00000001L
+#define SXIFCCG_DEBUG_REG2__sx_sent                        0x00000001L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK              0x00000002L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3                   0x00000002L
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK                    0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_aux                         0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK           0x000001f8L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK          0x0000fe00L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK              0x00010000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2                   0x00010000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx    0x00020000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK              0x000c0000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK              0x03c00000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK   0x04000000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded        0x04000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK     0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty          0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK      0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full           0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK  0xe0000000L
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK              0x00000010L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3                   0x00000010L
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK       0x000000e0L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK              0x00000f00L
+#define SXIFCCG_DEBUG_REG3__current_state_MASK             0x00003000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK         0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty              0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK          0x00008000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full               0x00008000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK              0x00030000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK    0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty         0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK     0x00080000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full          0x00080000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK   0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty        0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK    0x00200000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full         0x00200000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK              0xffc00000L
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK               0x0000001fL
+#define SETUP_DEBUG_REG0__pmode_state_MASK                 0x000007e0L
+#define SETUP_DEBUG_REG0__ge_stallb_MASK                   0x00000800L
+#define SETUP_DEBUG_REG0__ge_stallb                        0x00000800L
+#define SETUP_DEBUG_REG0__geom_enable_MASK                 0x00001000L
+#define SETUP_DEBUG_REG0__geom_enable                      0x00001000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK           0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr                0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK                 0x00004000L
+#define SETUP_DEBUG_REG0__su_clip_rtr                      0x00004000L
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK                  0x00008000L
+#define SETUP_DEBUG_REG0__pfifo_busy                       0x00008000L
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK                0x00010000L
+#define SETUP_DEBUG_REG0__su_cntl_busy                     0x00010000L
+#define SETUP_DEBUG_REG0__geom_busy_MASK                   0x00020000L
+#define SETUP_DEBUG_REG0__geom_busy                        0x00020000L
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK             0x00000800L
+#define SETUP_DEBUG_REG4__null_prim_gated                  0x00000800L
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK            0x00001000L
+#define SETUP_DEBUG_REG4__backfacing_gated                 0x00001000L
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK               0x0000e000L
+#define SETUP_DEBUG_REG4__clipped_gated_MASK               0x00010000L
+#define SETUP_DEBUG_REG4__clipped_gated                    0x00010000L
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK          0x000e0000L
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK                0x00100000L
+#define SETUP_DEBUG_REG4__xmajor_gated                     0x00100000L
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK          0x00600000L
+#define SETUP_DEBUG_REG4__type_gated_MASK                  0x03800000L
+#define SETUP_DEBUG_REG4__fpov_gated_MASK                  0x04000000L
+#define SETUP_DEBUG_REG4__fpov_gated                       0x04000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK            0x08000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated                 0x08000000L
+#define SETUP_DEBUG_REG4__event_gated_MASK                 0x10000000L
+#define SETUP_DEBUG_REG4__event_gated                      0x10000000L
+#define SETUP_DEBUG_REG4__eop_gated_MASK                   0x20000000L
+#define SETUP_DEBUG_REG4__eop_gated                        0x20000000L
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK       0x003ff800L
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK         0x00c00000L
+#define SETUP_DEBUG_REG5__event_id_gated_MASK              0x1f000000L
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1_MASK                      0x00000001L
+#define SC_DEBUG_0__pa_freeze_b1                           0x00000001L
+#define SC_DEBUG_0__pa_sc_valid_MASK                       0x00000002L
+#define SC_DEBUG_0__pa_sc_valid                            0x00000002L
+#define SC_DEBUG_0__pa_sc_phase_MASK                       0x0000001cL
+#define SC_DEBUG_0__cntx_cnt_MASK                          0x00000fe0L
+#define SC_DEBUG_0__decr_cntx_cnt_MASK                     0x00001000L
+#define SC_DEBUG_0__decr_cntx_cnt                          0x00001000L
+#define SC_DEBUG_0__incr_cntx_cnt_MASK                     0x00002000L
+#define SC_DEBUG_0__incr_cntx_cnt                          0x00002000L
+#define SC_DEBUG_0__trigger_MASK                           0x80000000L
+#define SC_DEBUG_0__trigger                                0x80000000L
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state_MASK                          0x00000007L
+#define SC_DEBUG_1__em1_data_ready_MASK                    0x00000008L
+#define SC_DEBUG_1__em1_data_ready                         0x00000008L
+#define SC_DEBUG_1__em2_data_ready_MASK                    0x00000010L
+#define SC_DEBUG_1__em2_data_ready                         0x00000010L
+#define SC_DEBUG_1__move_em1_to_em2_MASK                   0x00000020L
+#define SC_DEBUG_1__move_em1_to_em2                        0x00000020L
+#define SC_DEBUG_1__ef_data_ready_MASK                     0x00000040L
+#define SC_DEBUG_1__ef_data_ready                          0x00000040L
+#define SC_DEBUG_1__ef_state_MASK                          0x00000180L
+#define SC_DEBUG_1__pipe_valid_MASK                        0x00000200L
+#define SC_DEBUG_1__pipe_valid                             0x00000200L
+#define SC_DEBUG_1__trigger_MASK                           0x80000000L
+#define SC_DEBUG_1__trigger                                0x80000000L
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly_MASK                        0x00000001L
+#define SC_DEBUG_2__rc_rtr_dly                             0x00000001L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK              0x00000002L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1                   0x00000002L
+#define SC_DEBUG_2__pipe_freeze_b_MASK                     0x00000008L
+#define SC_DEBUG_2__pipe_freeze_b                          0x00000008L
+#define SC_DEBUG_2__prim_rts_MASK                          0x00000010L
+#define SC_DEBUG_2__prim_rts                               0x00000010L
+#define SC_DEBUG_2__next_prim_rts_dly_MASK                 0x00000020L
+#define SC_DEBUG_2__next_prim_rts_dly                      0x00000020L
+#define SC_DEBUG_2__next_prim_rtr_dly_MASK                 0x00000040L
+#define SC_DEBUG_2__next_prim_rtr_dly                      0x00000040L
+#define SC_DEBUG_2__pre_stage1_rts_d1_MASK                 0x00000080L
+#define SC_DEBUG_2__pre_stage1_rts_d1                      0x00000080L
+#define SC_DEBUG_2__stage0_rts_MASK                        0x00000100L
+#define SC_DEBUG_2__stage0_rts                             0x00000100L
+#define SC_DEBUG_2__phase_rts_dly_MASK                     0x00000200L
+#define SC_DEBUG_2__phase_rts_dly                          0x00000200L
+#define SC_DEBUG_2__end_of_prim_s1_dly_MASK                0x00008000L
+#define SC_DEBUG_2__end_of_prim_s1_dly                     0x00008000L
+#define SC_DEBUG_2__pass_empty_prim_s1_MASK                0x00010000L
+#define SC_DEBUG_2__pass_empty_prim_s1                     0x00010000L
+#define SC_DEBUG_2__event_id_s1_MASK                       0x003e0000L
+#define SC_DEBUG_2__event_s1_MASK                          0x00400000L
+#define SC_DEBUG_2__event_s1                               0x00400000L
+#define SC_DEBUG_2__trigger_MASK                           0x80000000L
+#define SC_DEBUG_2__trigger                                0x80000000L
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1_MASK                         0x000007ffL
+#define SC_DEBUG_3__y_curr_s1_MASK                         0x003ff800L
+#define SC_DEBUG_3__trigger_MASK                           0x80000000L
+#define SC_DEBUG_3__trigger                                0x80000000L
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_4__y_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_4__y_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_4__y_dir_s1                               0x10000000L
+#define SC_DEBUG_4__trigger_MASK                           0x80000000L
+#define SC_DEBUG_4__trigger                                0x80000000L
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_5__x_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_5__x_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_5__x_dir_s1                               0x10000000L
+#define SC_DEBUG_5__trigger_MASK                           0x80000000L
+#define SC_DEBUG_5__trigger                                0x80000000L
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty_MASK                        0x00000001L
+#define SC_DEBUG_6__z_ff_empty                             0x00000001L
+#define SC_DEBUG_6__qmcntl_ff_empty_MASK                   0x00000002L
+#define SC_DEBUG_6__qmcntl_ff_empty                        0x00000002L
+#define SC_DEBUG_6__xy_ff_empty_MASK                       0x00000004L
+#define SC_DEBUG_6__xy_ff_empty                            0x00000004L
+#define SC_DEBUG_6__event_flag_MASK                        0x00000008L
+#define SC_DEBUG_6__event_flag                             0x00000008L
+#define SC_DEBUG_6__z_mask_needed_MASK                     0x00000010L
+#define SC_DEBUG_6__z_mask_needed                          0x00000010L
+#define SC_DEBUG_6__state_MASK                             0x000000e0L
+#define SC_DEBUG_6__state_delayed_MASK                     0x00000700L
+#define SC_DEBUG_6__data_valid_MASK                        0x00000800L
+#define SC_DEBUG_6__data_valid                             0x00000800L
+#define SC_DEBUG_6__data_valid_d_MASK                      0x00001000L
+#define SC_DEBUG_6__data_valid_d                           0x00001000L
+#define SC_DEBUG_6__tilex_delayed_MASK                     0x003fe000L
+#define SC_DEBUG_6__tiley_delayed_MASK                     0x7fc00000L
+#define SC_DEBUG_6__trigger_MASK                           0x80000000L
+#define SC_DEBUG_6__trigger                                0x80000000L
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag_MASK                        0x00000001L
+#define SC_DEBUG_7__event_flag                             0x00000001L
+#define SC_DEBUG_7__deallocate_MASK                        0x0000000eL
+#define SC_DEBUG_7__fposition_MASK                         0x00000010L
+#define SC_DEBUG_7__fposition                              0x00000010L
+#define SC_DEBUG_7__sr_prim_we_MASK                        0x00000020L
+#define SC_DEBUG_7__sr_prim_we                             0x00000020L
+#define SC_DEBUG_7__last_tile_MASK                         0x00000040L
+#define SC_DEBUG_7__last_tile                              0x00000040L
+#define SC_DEBUG_7__tile_ff_we_MASK                        0x00000080L
+#define SC_DEBUG_7__tile_ff_we                             0x00000080L
+#define SC_DEBUG_7__qs_data_valid_MASK                     0x00000100L
+#define SC_DEBUG_7__qs_data_valid                          0x00000100L
+#define SC_DEBUG_7__qs_q0_y_MASK                           0x00000600L
+#define SC_DEBUG_7__qs_q0_x_MASK                           0x00001800L
+#define SC_DEBUG_7__qs_q0_valid_MASK                       0x00002000L
+#define SC_DEBUG_7__qs_q0_valid                            0x00002000L
+#define SC_DEBUG_7__prim_ff_we_MASK                        0x00004000L
+#define SC_DEBUG_7__prim_ff_we                             0x00004000L
+#define SC_DEBUG_7__tile_ff_re_MASK                        0x00008000L
+#define SC_DEBUG_7__tile_ff_re                             0x00008000L
+#define SC_DEBUG_7__fw_prim_data_valid_MASK                0x00010000L
+#define SC_DEBUG_7__fw_prim_data_valid                     0x00010000L
+#define SC_DEBUG_7__last_quad_of_tile_MASK                 0x00020000L
+#define SC_DEBUG_7__last_quad_of_tile                      0x00020000L
+#define SC_DEBUG_7__first_quad_of_tile_MASK                0x00040000L
+#define SC_DEBUG_7__first_quad_of_tile                     0x00040000L
+#define SC_DEBUG_7__first_quad_of_prim_MASK                0x00080000L
+#define SC_DEBUG_7__first_quad_of_prim                     0x00080000L
+#define SC_DEBUG_7__new_prim_MASK                          0x00100000L
+#define SC_DEBUG_7__new_prim                               0x00100000L
+#define SC_DEBUG_7__load_new_tile_data_MASK                0x00200000L
+#define SC_DEBUG_7__load_new_tile_data                     0x00200000L
+#define SC_DEBUG_7__state_MASK                             0x00c00000L
+#define SC_DEBUG_7__fifos_ready_MASK                       0x01000000L
+#define SC_DEBUG_7__fifos_ready                            0x01000000L
+#define SC_DEBUG_7__trigger_MASK                           0x80000000L
+#define SC_DEBUG_7__trigger                                0x80000000L
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last_MASK                       0x00000001L
+#define SC_DEBUG_8__sample_last                            0x00000001L
+#define SC_DEBUG_8__sample_mask_MASK                       0x0000001eL
+#define SC_DEBUG_8__sample_y_MASK                          0x00000060L
+#define SC_DEBUG_8__sample_x_MASK                          0x00000180L
+#define SC_DEBUG_8__sample_send_MASK                       0x00000200L
+#define SC_DEBUG_8__sample_send                            0x00000200L
+#define SC_DEBUG_8__next_cycle_MASK                        0x00000c00L
+#define SC_DEBUG_8__ez_sample_ff_full_MASK                 0x00001000L
+#define SC_DEBUG_8__ez_sample_ff_full                      0x00001000L
+#define SC_DEBUG_8__rb_sc_samp_rtr_MASK                    0x00002000L
+#define SC_DEBUG_8__rb_sc_samp_rtr                         0x00002000L
+#define SC_DEBUG_8__num_samples_MASK                       0x0000c000L
+#define SC_DEBUG_8__last_quad_of_tile_MASK                 0x00010000L
+#define SC_DEBUG_8__last_quad_of_tile                      0x00010000L
+#define SC_DEBUG_8__last_quad_of_prim_MASK                 0x00020000L
+#define SC_DEBUG_8__last_quad_of_prim                      0x00020000L
+#define SC_DEBUG_8__first_quad_of_prim_MASK                0x00040000L
+#define SC_DEBUG_8__first_quad_of_prim                     0x00040000L
+#define SC_DEBUG_8__sample_we_MASK                         0x00080000L
+#define SC_DEBUG_8__sample_we                              0x00080000L
+#define SC_DEBUG_8__fposition_MASK                         0x00100000L
+#define SC_DEBUG_8__fposition                              0x00100000L
+#define SC_DEBUG_8__event_id_MASK                          0x03e00000L
+#define SC_DEBUG_8__event_flag_MASK                        0x04000000L
+#define SC_DEBUG_8__event_flag                             0x04000000L
+#define SC_DEBUG_8__fw_prim_data_valid_MASK                0x08000000L
+#define SC_DEBUG_8__fw_prim_data_valid                     0x08000000L
+#define SC_DEBUG_8__trigger_MASK                           0x80000000L
+#define SC_DEBUG_8__trigger                                0x80000000L
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send_MASK                        0x00000001L
+#define SC_DEBUG_9__rb_sc_send                             0x00000001L
+#define SC_DEBUG_9__rb_sc_ez_mask_MASK                     0x0000001eL
+#define SC_DEBUG_9__fifo_data_ready_MASK                   0x00000020L
+#define SC_DEBUG_9__fifo_data_ready                        0x00000020L
+#define SC_DEBUG_9__early_z_enable_MASK                    0x00000040L
+#define SC_DEBUG_9__early_z_enable                         0x00000040L
+#define SC_DEBUG_9__mask_state_MASK                        0x00000180L
+#define SC_DEBUG_9__next_ez_mask_MASK                      0x01fffe00L
+#define SC_DEBUG_9__mask_ready_MASK                        0x02000000L
+#define SC_DEBUG_9__mask_ready                             0x02000000L
+#define SC_DEBUG_9__drop_sample_MASK                       0x04000000L
+#define SC_DEBUG_9__drop_sample                            0x04000000L
+#define SC_DEBUG_9__fetch_new_sample_data_MASK             0x08000000L
+#define SC_DEBUG_9__fetch_new_sample_data                  0x08000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK          0x10000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask               0x10000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK         0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data              0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK           0x40000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data                0x40000000L
+#define SC_DEBUG_9__trigger_MASK                           0x80000000L
+#define SC_DEBUG_9__trigger                                0x80000000L
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask_MASK             0x0000ffffL
+#define SC_DEBUG_10__trigger_MASK                          0x80000000L
+#define SC_DEBUG_10__trigger                               0x80000000L
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready_MASK             0x00000001L
+#define SC_DEBUG_11__ez_sample_data_ready                  0x00000001L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK        0x00000002L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data             0x00000002L
+#define SC_DEBUG_11__ez_prim_data_ready_MASK               0x00000004L
+#define SC_DEBUG_11__ez_prim_data_ready                    0x00000004L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK          0x00000008L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data               0x00000008L
+#define SC_DEBUG_11__iterator_input_fz_MASK                0x00000010L
+#define SC_DEBUG_11__iterator_input_fz                     0x00000010L
+#define SC_DEBUG_11__packer_send_quads_MASK                0x00000020L
+#define SC_DEBUG_11__packer_send_quads                     0x00000020L
+#define SC_DEBUG_11__packer_send_cmd_MASK                  0x00000040L
+#define SC_DEBUG_11__packer_send_cmd                       0x00000040L
+#define SC_DEBUG_11__packer_send_event_MASK                0x00000080L
+#define SC_DEBUG_11__packer_send_event                     0x00000080L
+#define SC_DEBUG_11__next_state_MASK                       0x00000700L
+#define SC_DEBUG_11__state_MASK                            0x00003800L
+#define SC_DEBUG_11__stall_MASK                            0x00004000L
+#define SC_DEBUG_11__stall                                 0x00004000L
+#define SC_DEBUG_11__trigger_MASK                          0x80000000L
+#define SC_DEBUG_11__trigger                               0x80000000L
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff_MASK            0x00000001L
+#define SC_DEBUG_12__SQ_iterator_free_buff                 0x00000001L
+#define SC_DEBUG_12__event_id_MASK                         0x0000003eL
+#define SC_DEBUG_12__event_flag_MASK                       0x00000040L
+#define SC_DEBUG_12__event_flag                            0x00000040L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK          0x00000080L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly               0x00000080L
+#define SC_DEBUG_12__itercmdfifo_full_MASK                 0x00000100L
+#define SC_DEBUG_12__itercmdfifo_full                      0x00000100L
+#define SC_DEBUG_12__itercmdfifo_empty_MASK                0x00000200L
+#define SC_DEBUG_12__itercmdfifo_empty                     0x00000200L
+#define SC_DEBUG_12__iter_ds_one_clk_command_MASK          0x00000400L
+#define SC_DEBUG_12__iter_ds_one_clk_command               0x00000400L
+#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK             0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_prim0                  0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_vector_MASK            0x00001000L
+#define SC_DEBUG_12__iter_ds_end_of_vector                 0x00001000L
+#define SC_DEBUG_12__iter_qdhit0_MASK                      0x00002000L
+#define SC_DEBUG_12__iter_qdhit0                           0x00002000L
+#define SC_DEBUG_12__bc_use_centers_reg_MASK               0x00004000L
+#define SC_DEBUG_12__bc_use_centers_reg                    0x00004000L
+#define SC_DEBUG_12__bc_output_xy_reg_MASK                 0x00008000L
+#define SC_DEBUG_12__bc_output_xy_reg                      0x00008000L
+#define SC_DEBUG_12__iter_phase_out_MASK                   0x00030000L
+#define SC_DEBUG_12__iter_phase_reg_MASK                   0x000c0000L
+#define SC_DEBUG_12__iterator_SP_valid_MASK                0x00100000L
+#define SC_DEBUG_12__iterator_SP_valid                     0x00100000L
+#define SC_DEBUG_12__eopv_reg_MASK                         0x00200000L
+#define SC_DEBUG_12__eopv_reg                              0x00200000L
+#define SC_DEBUG_12__one_clk_cmd_reg_MASK                  0x00400000L
+#define SC_DEBUG_12__one_clk_cmd_reg                       0x00400000L
+#define SC_DEBUG_12__iter_dx_end_of_prim_MASK              0x00800000L
+#define SC_DEBUG_12__iter_dx_end_of_prim                   0x00800000L
+#define SC_DEBUG_12__trigger_MASK                          0x80000000L
+#define SC_DEBUG_12__trigger                               0x80000000L
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK                  0x00000001L
+#define GFX_COPY_STATE__SRC_STATE_ID                       0x00000001L
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK                 0x0000003fL
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK             0x000000c0L
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK      0x00000300L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK                0x00000800L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE                     0x00000800L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                   0x00001000L
+#define VGT_DRAW_INITIATOR__NOT_EOP                        0x00001000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK               0x00002000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX                    0x00002000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK     0x00004000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE          0x00004000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK           0x00008000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE                0x00008000L
+#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK               0xffff0000L
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK               0x0000003fL
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR_MASK                       0xffffffffL
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_DMA_SIZE__SWAP_MODE_MASK                       0xc0000000L
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK                   0xffffffffL
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_BIN_SIZE__FACENESS_FETCH_MASK                  0x40000000L
+#define VGT_BIN_SIZE__FACENESS_FETCH                       0x40000000L
+#define VGT_BIN_SIZE__FACENESS_RESET_MASK                  0x80000000L
+#define VGT_BIN_SIZE__FACENESS_RESET                       0x80000000L
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                    0x00ffffffL
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                    0x00ffffffL
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                  0x00ffffffL
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK  0x00000007L
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK            0x00000003L
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK      0x00ffffffL
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC_MASK                             0x0000ffffL
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK            0x0000001fL
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK             0x00000001L
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID                  0x00000001L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK             0x00010000L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID                  0x00010000L
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK                0x0000001fL
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK                     0x00000001L
+#define VGT_CNTL_STATUS__VGT_BUSY                          0x00000001L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK                 0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY                      0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK             0x00000004L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY                  0x00000004L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK                 0x00000008L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY                      0x00000008L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                  0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY                       0x00000010L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK                 0x00000020L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY                      0x00000020L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                  0x00000040L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY                       0x00000040L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                 0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY                      0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK            0x00000100L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY                 0x00000100L
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy_MASK                   0x00000001L
+#define VGT_DEBUG_REG0__te_grp_busy                        0x00000001L
+#define VGT_DEBUG_REG0__pt_grp_busy_MASK                   0x00000002L
+#define VGT_DEBUG_REG0__pt_grp_busy                        0x00000002L
+#define VGT_DEBUG_REG0__vr_grp_busy_MASK                   0x00000004L
+#define VGT_DEBUG_REG0__vr_grp_busy                        0x00000004L
+#define VGT_DEBUG_REG0__dma_request_busy_MASK              0x00000008L
+#define VGT_DEBUG_REG0__dma_request_busy                   0x00000008L
+#define VGT_DEBUG_REG0__out_busy_MASK                      0x00000010L
+#define VGT_DEBUG_REG0__out_busy                           0x00000010L
+#define VGT_DEBUG_REG0__grp_backend_busy_MASK              0x00000020L
+#define VGT_DEBUG_REG0__grp_backend_busy                   0x00000020L
+#define VGT_DEBUG_REG0__grp_busy_MASK                      0x00000040L
+#define VGT_DEBUG_REG0__grp_busy                           0x00000040L
+#define VGT_DEBUG_REG0__dma_busy_MASK                      0x00000080L
+#define VGT_DEBUG_REG0__dma_busy                           0x00000080L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK         0x00000100L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy              0x00000100L
+#define VGT_DEBUG_REG0__rbiu_busy_MASK                     0x00000200L
+#define VGT_DEBUG_REG0__rbiu_busy                          0x00000200L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK      0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended           0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK               0x00000800L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy                    0x00000800L
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK             0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_extended                  0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_MASK                      0x00002000L
+#define VGT_DEBUG_REG0__vgt_busy                           0x00002000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK       0x00004000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out            0x00004000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK          0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy               0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK                 0x00010000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy                      0x00010000L
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read_MASK              0x00000001L
+#define VGT_DEBUG_REG1__out_te_data_read                   0x00000001L
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK             0x00000002L
+#define VGT_DEBUG_REG1__te_out_data_valid                  0x00000002L
+#define VGT_DEBUG_REG1__out_pt_prim_read_MASK              0x00000004L
+#define VGT_DEBUG_REG1__out_pt_prim_read                   0x00000004L
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK             0x00000008L
+#define VGT_DEBUG_REG1__pt_out_prim_valid                  0x00000008L
+#define VGT_DEBUG_REG1__out_pt_data_read_MASK              0x00000010L
+#define VGT_DEBUG_REG1__out_pt_data_read                   0x00000010L
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK             0x00000020L
+#define VGT_DEBUG_REG1__pt_out_indx_valid                  0x00000020L
+#define VGT_DEBUG_REG1__out_vr_prim_read_MASK              0x00000040L
+#define VGT_DEBUG_REG1__out_vr_prim_read                   0x00000040L
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK             0x00000080L
+#define VGT_DEBUG_REG1__vr_out_prim_valid                  0x00000080L
+#define VGT_DEBUG_REG1__out_vr_indx_read_MASK              0x00000100L
+#define VGT_DEBUG_REG1__out_vr_indx_read                   0x00000100L
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK             0x00000200L
+#define VGT_DEBUG_REG1__vr_out_indx_valid                  0x00000200L
+#define VGT_DEBUG_REG1__te_grp_read_MASK                   0x00000400L
+#define VGT_DEBUG_REG1__te_grp_read                        0x00000400L
+#define VGT_DEBUG_REG1__grp_te_valid_MASK                  0x00000800L
+#define VGT_DEBUG_REG1__grp_te_valid                       0x00000800L
+#define VGT_DEBUG_REG1__pt_grp_read_MASK                   0x00001000L
+#define VGT_DEBUG_REG1__pt_grp_read                        0x00001000L
+#define VGT_DEBUG_REG1__grp_pt_valid_MASK                  0x00002000L
+#define VGT_DEBUG_REG1__grp_pt_valid                       0x00002000L
+#define VGT_DEBUG_REG1__vr_grp_read_MASK                   0x00004000L
+#define VGT_DEBUG_REG1__vr_grp_read                        0x00004000L
+#define VGT_DEBUG_REG1__grp_vr_valid_MASK                  0x00008000L
+#define VGT_DEBUG_REG1__grp_vr_valid                       0x00008000L
+#define VGT_DEBUG_REG1__grp_dma_read_MASK                  0x00010000L
+#define VGT_DEBUG_REG1__grp_dma_read                       0x00010000L
+#define VGT_DEBUG_REG1__dma_grp_valid_MASK                 0x00020000L
+#define VGT_DEBUG_REG1__dma_grp_valid                      0x00020000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK              0x00040000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read                   0x00040000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK             0x00080000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid                  0x00080000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK                    0x00100000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr                         0x00100000L
+#define VGT_DEBUG_REG1__VGT_MH_send_MASK                   0x00200000L
+#define VGT_DEBUG_REG1__VGT_MH_send                        0x00200000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK             0x00400000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr                  0x00400000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK            0x00800000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send                 0x00800000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK             0x01000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr                  0x01000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK            0x02000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send                 0x02000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK             0x04000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr                  0x04000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK            0x08000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send                 0x08000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK                    0x10000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr                         0x10000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send_MASK                   0x20000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send                        0x20000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK                0x40000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q                     0x40000000L
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en_MASK                    0x00000001L
+#define VGT_DEBUG_REG3__vgt_clk_en                         0x00000001L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK              0x00000002L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en                   0x00000002L
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK          0x0000001fL
+#define VGT_DEBUG_REG6__right_word_indx_q_MASK             0x000003e0L
+#define VGT_DEBUG_REG6__input_data_valid_MASK              0x00000400L
+#define VGT_DEBUG_REG6__input_data_valid                   0x00000400L
+#define VGT_DEBUG_REG6__input_data_xfer_MASK               0x00000800L
+#define VGT_DEBUG_REG6__input_data_xfer                    0x00000800L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK        0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q             0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK        0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d             0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK    0x00004000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d         0x00004000L
+#define VGT_DEBUG_REG6__space_avail_from_shift_MASK        0x00008000L
+#define VGT_DEBUG_REG6__space_avail_from_shift             0x00008000L
+#define VGT_DEBUG_REG6__shifter_first_load_MASK            0x00010000L
+#define VGT_DEBUG_REG6__shifter_first_load                 0x00010000L
+#define VGT_DEBUG_REG6__di_state_sel_q_MASK                0x00020000L
+#define VGT_DEBUG_REG6__di_state_sel_q                     0x00020000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q   0x00040000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK         0x00080000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q              0x00080000L
+#define VGT_DEBUG_REG6__di_event_flag_q_MASK               0x00100000L
+#define VGT_DEBUG_REG6__di_event_flag_q                    0x00100000L
+#define VGT_DEBUG_REG6__read_draw_initiator_MASK           0x00200000L
+#define VGT_DEBUG_REG6__read_draw_initiator                0x00200000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK   0x00400000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter        0x00400000L
+#define VGT_DEBUG_REG6__last_shift_of_packet_MASK          0x00800000L
+#define VGT_DEBUG_REG6__last_shift_of_packet               0x00800000L
+#define VGT_DEBUG_REG6__last_decr_of_packet_MASK           0x01000000L
+#define VGT_DEBUG_REG6__last_decr_of_packet                0x01000000L
+#define VGT_DEBUG_REG6__extract_vector_MASK                0x02000000L
+#define VGT_DEBUG_REG6__extract_vector                     0x02000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr_MASK                0x04000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr                     0x04000000L
+#define VGT_DEBUG_REG6__destination_rtr_MASK               0x08000000L
+#define VGT_DEBUG_REG6__destination_rtr                    0x08000000L
+#define VGT_DEBUG_REG6__grp_trigger_MASK                   0x10000000L
+#define VGT_DEBUG_REG6__grp_trigger                        0x10000000L
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q_MASK            0x0000ffffL
+#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK       0x000f0000L
+#define VGT_DEBUG_REG7__shift_amount_extract_MASK          0x00f00000L
+#define VGT_DEBUG_REG7__di_prim_type_q_MASK                0x3f000000L
+#define VGT_DEBUG_REG7__current_source_sel_MASK            0xc0000000L
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel_MASK            0x00000003L
+#define VGT_DEBUG_REG8__left_word_indx_q_MASK              0x0000007cL
+#define VGT_DEBUG_REG8__input_data_cnt_MASK                0x00000f80L
+#define VGT_DEBUG_REG8__input_data_lsw_MASK                0x0001f000L
+#define VGT_DEBUG_REG8__input_data_msw_MASK                0x003e0000L
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q_MASK                 0x0000001fL
+#define VGT_DEBUG_REG9__next_stride_d_MASK                 0x000003e0L
+#define VGT_DEBUG_REG9__current_shift_q_MASK               0x00007c00L
+#define VGT_DEBUG_REG9__current_shift_d_MASK               0x000f8000L
+#define VGT_DEBUG_REG9__current_stride_q_MASK              0x01f00000L
+#define VGT_DEBUG_REG9__current_stride_d_MASK              0x3e000000L
+#define VGT_DEBUG_REG9__grp_trigger_MASK                   0x40000000L
+#define VGT_DEBUG_REG9__grp_trigger                        0x40000000L
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0      0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0    0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0    0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L
+#define VGT_DEBUG_REG10__di_state_sel_q_MASK               0x00000010L
+#define VGT_DEBUG_REG10__di_state_sel_q                    0x00000010L
+#define VGT_DEBUG_REG10__last_decr_of_packet_MASK          0x00000020L
+#define VGT_DEBUG_REG10__last_decr_of_packet               0x00000020L
+#define VGT_DEBUG_REG10__bin_valid_MASK                    0x00000040L
+#define VGT_DEBUG_REG10__bin_valid                         0x00000040L
+#define VGT_DEBUG_REG10__read_block_MASK                   0x00000080L
+#define VGT_DEBUG_REG10__read_block                        0x00000080L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK       0x00000100L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read            0x00000100L
+#define VGT_DEBUG_REG10__last_bit_enable_q_MASK            0x00000200L
+#define VGT_DEBUG_REG10__last_bit_enable_q                 0x00000200L
+#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK            0x00000400L
+#define VGT_DEBUG_REG10__last_bit_end_di_q                 0x00000400L
+#define VGT_DEBUG_REG10__selected_data_MASK                0x0007f800L
+#define VGT_DEBUG_REG10__mask_input_data_MASK              0x07f80000L
+#define VGT_DEBUG_REG10__gap_q_MASK                        0x08000000L
+#define VGT_DEBUG_REG10__gap_q                             0x08000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK            0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z                 0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK            0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y                 0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK            0x40000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x                 0x40000000L
+#define VGT_DEBUG_REG10__grp_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG10__grp_trigger                       0x80000000L
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK         0x0000001fL
+#define VGT_DEBUG_REG12__right_word_indx_q_MASK            0x000003e0L
+#define VGT_DEBUG_REG12__input_data_valid_MASK             0x00000400L
+#define VGT_DEBUG_REG12__input_data_valid                  0x00000400L
+#define VGT_DEBUG_REG12__input_data_xfer_MASK              0x00000800L
+#define VGT_DEBUG_REG12__input_data_xfer                   0x00000800L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK       0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q            0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK       0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d            0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK   0x00004000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d        0x00004000L
+#define VGT_DEBUG_REG12__space_avail_from_shift_MASK       0x00008000L
+#define VGT_DEBUG_REG12__space_avail_from_shift            0x00008000L
+#define VGT_DEBUG_REG12__shifter_first_load_MASK           0x00010000L
+#define VGT_DEBUG_REG12__shifter_first_load                0x00010000L
+#define VGT_DEBUG_REG12__di_state_sel_q_MASK               0x00020000L
+#define VGT_DEBUG_REG12__di_state_sel_q                    0x00020000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q  0x00040000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK        0x00080000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q             0x00080000L
+#define VGT_DEBUG_REG12__di_event_flag_q_MASK              0x00100000L
+#define VGT_DEBUG_REG12__di_event_flag_q                   0x00100000L
+#define VGT_DEBUG_REG12__read_draw_initiator_MASK          0x00200000L
+#define VGT_DEBUG_REG12__read_draw_initiator               0x00200000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK  0x00400000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter       0x00400000L
+#define VGT_DEBUG_REG12__last_shift_of_packet_MASK         0x00800000L
+#define VGT_DEBUG_REG12__last_shift_of_packet              0x00800000L
+#define VGT_DEBUG_REG12__last_decr_of_packet_MASK          0x01000000L
+#define VGT_DEBUG_REG12__last_decr_of_packet               0x01000000L
+#define VGT_DEBUG_REG12__extract_vector_MASK               0x02000000L
+#define VGT_DEBUG_REG12__extract_vector                    0x02000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr_MASK               0x04000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr                    0x04000000L
+#define VGT_DEBUG_REG12__destination_rtr_MASK              0x08000000L
+#define VGT_DEBUG_REG12__destination_rtr                   0x08000000L
+#define VGT_DEBUG_REG12__bgrp_trigger_MASK                 0x10000000L
+#define VGT_DEBUG_REG12__bgrp_trigger                      0x10000000L
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q_MASK           0x0000ffffL
+#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK      0x000f0000L
+#define VGT_DEBUG_REG13__shift_amount_extract_MASK         0x00f00000L
+#define VGT_DEBUG_REG13__di_prim_type_q_MASK               0x3f000000L
+#define VGT_DEBUG_REG13__current_source_sel_MASK           0xc0000000L
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel_MASK           0x00000003L
+#define VGT_DEBUG_REG14__left_word_indx_q_MASK             0x0000007cL
+#define VGT_DEBUG_REG14__input_data_cnt_MASK               0x00000f80L
+#define VGT_DEBUG_REG14__input_data_lsw_MASK               0x0001f000L
+#define VGT_DEBUG_REG14__input_data_msw_MASK               0x003e0000L
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q_MASK                0x0000001fL
+#define VGT_DEBUG_REG15__next_stride_d_MASK                0x000003e0L
+#define VGT_DEBUG_REG15__current_shift_q_MASK              0x00007c00L
+#define VGT_DEBUG_REG15__current_shift_d_MASK              0x000f8000L
+#define VGT_DEBUG_REG15__current_stride_q_MASK             0x01f00000L
+#define VGT_DEBUG_REG15__current_stride_d_MASK             0x3e000000L
+#define VGT_DEBUG_REG15__bgrp_trigger_MASK                 0x40000000L
+#define VGT_DEBUG_REG15__bgrp_trigger                      0x40000000L
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK    0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full         0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK   0x00000002L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty        0x00000002L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK     0x00000004L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read          0x00000004L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK      0x00000008L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we           0x00000008L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK     0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full          0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK    0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty         0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK     0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q          0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK       0x00000080L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we            0x00000080L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK           0x00000100L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill                0x00000100L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK           0x00000200L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid                0x00000200L
+#define VGT_DEBUG_REG16__rst_last_bit_MASK                 0x00000400L
+#define VGT_DEBUG_REG16__rst_last_bit                      0x00000400L
+#define VGT_DEBUG_REG16__current_state_q_MASK              0x00000800L
+#define VGT_DEBUG_REG16__current_state_q                   0x00000800L
+#define VGT_DEBUG_REG16__old_state_q_MASK                  0x00001000L
+#define VGT_DEBUG_REG16__old_state_q                       0x00001000L
+#define VGT_DEBUG_REG16__old_state_en_MASK                 0x00002000L
+#define VGT_DEBUG_REG16__old_state_en                      0x00002000L
+#define VGT_DEBUG_REG16__prev_last_bit_q_MASK              0x00004000L
+#define VGT_DEBUG_REG16__prev_last_bit_q                   0x00004000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK               0x00008000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q                    0x00008000L
+#define VGT_DEBUG_REG16__last_bit_block_q_MASK             0x00010000L
+#define VGT_DEBUG_REG16__last_bit_block_q                  0x00010000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK             0x00020000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q                  0x00020000L
+#define VGT_DEBUG_REG16__load_empty_reg_MASK               0x00040000L
+#define VGT_DEBUG_REG16__load_empty_reg                    0x00040000L
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK     0x07f80000L
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK  0x18000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable      0x20000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK     0x40000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q          0x40000000L
+#define VGT_DEBUG_REG16__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG16__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q_MASK                  0x00000001L
+#define VGT_DEBUG_REG17__save_read_q                       0x00000001L
+#define VGT_DEBUG_REG17__extend_read_q_MASK                0x00000002L
+#define VGT_DEBUG_REG17__extend_read_q                     0x00000002L
+#define VGT_DEBUG_REG17__grp_indx_size_MASK                0x0000000cL
+#define VGT_DEBUG_REG17__cull_prim_true_MASK               0x00000010L
+#define VGT_DEBUG_REG17__cull_prim_true                    0x00000010L
+#define VGT_DEBUG_REG17__reset_bit2_q_MASK                 0x00000020L
+#define VGT_DEBUG_REG17__reset_bit2_q                      0x00000020L
+#define VGT_DEBUG_REG17__reset_bit1_q_MASK                 0x00000040L
+#define VGT_DEBUG_REG17__reset_bit1_q                      0x00000040L
+#define VGT_DEBUG_REG17__first_reg_first_q_MASK            0x00000080L
+#define VGT_DEBUG_REG17__first_reg_first_q                 0x00000080L
+#define VGT_DEBUG_REG17__check_second_reg_MASK             0x00000100L
+#define VGT_DEBUG_REG17__check_second_reg                  0x00000100L
+#define VGT_DEBUG_REG17__check_first_reg_MASK              0x00000200L
+#define VGT_DEBUG_REG17__check_first_reg                   0x00000200L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK   0x00000400L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata        0x00000400L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK      0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q           0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK      0x00001000L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q           0x00001000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK       0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q            0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK       0x00004000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q            0x00004000L
+#define VGT_DEBUG_REG17__to_second_reg_q_MASK              0x00008000L
+#define VGT_DEBUG_REG17__to_second_reg_q                   0x00008000L
+#define VGT_DEBUG_REG17__roll_over_msk_q_MASK              0x00010000L
+#define VGT_DEBUG_REG17__roll_over_msk_q                   0x00010000L
+#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK                0x00fe0000L
+#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK                0x7f000000L
+#define VGT_DEBUG_REG17__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG17__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK      0x0000003fL
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK      0x00000fc0L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK   0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re        0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK  0x00006000L
+#define VGT_DEBUG_REG18__dma_mem_full_MASK                 0x00008000L
+#define VGT_DEBUG_REG18__dma_mem_full                      0x00008000L
+#define VGT_DEBUG_REG18__dma_ram_re_MASK                   0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_re                        0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_we_MASK                   0x00020000L
+#define VGT_DEBUG_REG18__dma_ram_we                        0x00020000L
+#define VGT_DEBUG_REG18__dma_mem_empty_MASK                0x00040000L
+#define VGT_DEBUG_REG18__dma_mem_empty                     0x00040000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK         0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re              0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK         0x00100000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we              0x00100000L
+#define VGT_DEBUG_REG18__bin_mem_full_MASK                 0x00200000L
+#define VGT_DEBUG_REG18__bin_mem_full                      0x00200000L
+#define VGT_DEBUG_REG18__bin_ram_we_MASK                   0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_we                        0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_re_MASK                   0x00800000L
+#define VGT_DEBUG_REG18__bin_ram_re                        0x00800000L
+#define VGT_DEBUG_REG18__bin_mem_empty_MASK                0x01000000L
+#define VGT_DEBUG_REG18__bin_mem_empty                     0x01000000L
+#define VGT_DEBUG_REG18__start_bin_req_MASK                0x02000000L
+#define VGT_DEBUG_REG18__start_bin_req                     0x02000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK          0x04000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used               0x04000000L
+#define VGT_DEBUG_REG18__dma_req_xfer_MASK                 0x08000000L
+#define VGT_DEBUG_REG18__dma_req_xfer                      0x08000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req_MASK           0x10000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req                0x10000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req_MASK           0x20000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req                0x20000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK  0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable       0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK         0x00000001L
+#define VGT_DEBUG_REG20__prim_side_indx_valid              0x00000001L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK         0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty              0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK            0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_re                 0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK            0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_we                 0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK          0x00000010L
+#define VGT_DEBUG_REG20__indx_side_fifo_full               0x00000010L
+#define VGT_DEBUG_REG20__prim_buffer_empty_MASK            0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_empty                 0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_re_MASK               0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_re                    0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_we_MASK               0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_we                    0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_full_MASK             0x00000100L
+#define VGT_DEBUG_REG20__prim_buffer_full                  0x00000100L
+#define VGT_DEBUG_REG20__indx_buffer_empty_MASK            0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_empty                 0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_re_MASK               0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_re                    0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_we_MASK               0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_we                    0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_full_MASK             0x00001000L
+#define VGT_DEBUG_REG20__indx_buffer_full                  0x00001000L
+#define VGT_DEBUG_REG20__hold_prim_MASK                    0x00002000L
+#define VGT_DEBUG_REG20__hold_prim                         0x00002000L
+#define VGT_DEBUG_REG20__sent_cnt_MASK                     0x0003c000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK          0x00040000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector               0x00040000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK         0x00080000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim              0x00080000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK         0x00100000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim              0x00100000L
+#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK     0x03e00000L
+#define VGT_DEBUG_REG20__out_trigger_MASK                  0x04000000L
+#define VGT_DEBUG_REG20__out_trigger                       0x04000000L
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK    0x00000001L
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector         0x00000001L
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK   0x0000000eL
+#define VGT_DEBUG_REG21__alloc_counter_q_MASK              0x00000070L
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK      0x00000380L
+#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK            0x00003c00L
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK      0x0003c000L
+#define VGT_DEBUG_REG21__new_packet_q_MASK                 0x00040000L
+#define VGT_DEBUG_REG21__new_packet_q                      0x00040000L
+#define VGT_DEBUG_REG21__new_allocate_q_MASK               0x00080000L
+#define VGT_DEBUG_REG21__new_allocate_q                    0x00080000L
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK      0x00300000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK         0x00400000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q              0x00400000L
+#define VGT_DEBUG_REG21__insert_null_prim_MASK             0x00800000L
+#define VGT_DEBUG_REG21__insert_null_prim                  0x00800000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK        0x01000000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux             0x01000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK        0x02000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux             0x02000000L
+#define VGT_DEBUG_REG21__buffered_thread_size_MASK         0x04000000L
+#define VGT_DEBUG_REG21__buffered_thread_size              0x04000000L
+#define VGT_DEBUG_REG21__out_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG21__out_trigger                       0x80000000L
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC_MASK                          0xffffffffL
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC_MASK                          0xffffffffL
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE_MASK                 0x00000001L
+#define TC_CNTL_STATUS__L2_INVALIDATE                      0x00000001L
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK                0x000c0000L
+#define TC_CNTL_STATUS__TC_BUSY_MASK                       0x80000000L
+#define TC_CNTL_STATUS__TC_BUSY                            0x80000000L
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK                 0x00000100L
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN                      0x00000100L
+#define TCM_CHICKEN__SPARE_MASK                            0xfffffe00L
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK            0x00000007L
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK            0x00000038L
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK               0x00000001L
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY                    0x00000001L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK             0x00000002L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY                  0x00000002L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK          0x00000004L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY               0x00000004L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK          0x00000008L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY               0x00000008L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK         0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY              0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK           0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY                0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK              0x00000040L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY                   0x00000040L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK        0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY             0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK          0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY               0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK             0x00000400L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY                  0x00000400L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK             0x00001000L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY                  0x00001000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK          0x00002000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY               0x00002000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK            0x00004000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY                 0x00004000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK               0x00008000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY                    0x00008000L
+#define TPC_CNTL_STATUS__TF_TW_RTS_MASK                    0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_RTS                         0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK              0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS                   0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_RTR_MASK                    0x00080000L
+#define TPC_CNTL_STATUS__TF_TW_RTR                         0x00080000L
+#define TPC_CNTL_STATUS__TW_TA_RTS_MASK                    0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_RTS                         0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK                 0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS                      0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK               0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS                    0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_RTR_MASK                    0x00800000L
+#define TPC_CNTL_STATUS__TW_TA_RTR                         0x00800000L
+#define TPC_CNTL_STATUS__TA_TB_RTS_MASK                    0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_RTS                         0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK                 0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS                      0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR_MASK                    0x08000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR                         0x08000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS_MASK                    0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS                         0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK            0x20000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN                 0x20000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK                    0x40000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC                         0x40000000L
+#define TPC_CNTL_STATUS__TPC_BUSY_MASK                     0x80000000L
+#define TPC_CNTL_STATUS__TPC_BUSY                          0x80000000L
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL_MASK                          0x00000003L
+#define TPC_DEBUG0__IC_CTR_MASK                            0x0000000cL
+#define TPC_DEBUG0__WALKER_CNTL_MASK                       0x000000f0L
+#define TPC_DEBUG0__ALIGNER_CNTL_MASK                      0x00000700L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK               0x00001000L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID                    0x00001000L
+#define TPC_DEBUG0__WALKER_STATE_MASK                      0x03ff0000L
+#define TPC_DEBUG0__ALIGNER_STATE_MASK                     0x0c000000L
+#define TPC_DEBUG0__REG_CLK_EN_MASK                        0x20000000L
+#define TPC_DEBUG0__REG_CLK_EN                             0x20000000L
+#define TPC_DEBUG0__TPC_CLK_EN_MASK                        0x40000000L
+#define TPC_DEBUG0__TPC_CLK_EN                             0x40000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK                      0x80000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP                           0x80000000L
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED_MASK                            0x00000001L
+#define TPC_DEBUG1__UNUSED                                 0x00000001L
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION_MASK                  0x00000001L
+#define TPC_CHICKEN__BLEND_PRECISION                       0x00000001L
+#define TPC_CHICKEN__SPARE_MASK                            0xfffffffeL
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK                0x00000001L
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY                     0x00000001L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK                  0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY                       0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK             0x00000004L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY                  0x00000004L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK                 0x00000008L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY                      0x00000008L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK           0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY                0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK              0x00000020L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY                   0x00000020L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK              0x00000040L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY                   0x00000040L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK              0x00000080L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY                   0x00000080L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK                0x00000100L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY                     0x00000100L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK             0x00000200L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY                  0x00000200L
+#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK                   0x00000400L
+#define TP0_CNTL_STATUS__TP_TT_BUSY                        0x00000400L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK              0x00000800L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY                   0x00000800L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK                0x00001000L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY                     0x00001000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK             0x00002000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY                  0x00002000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK               0x00004000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY                    0x00004000L
+#define TP0_CNTL_STATUS__IN_LC_RTS_MASK                    0x00010000L
+#define TP0_CNTL_STATUS__IN_LC_RTS                         0x00010000L
+#define TP0_CNTL_STATUS__LC_LA_RTS_MASK                    0x00020000L
+#define TP0_CNTL_STATUS__LC_LA_RTS                         0x00020000L
+#define TP0_CNTL_STATUS__LA_FL_RTS_MASK                    0x00040000L
+#define TP0_CNTL_STATUS__LA_FL_RTS                         0x00040000L
+#define TP0_CNTL_STATUS__FL_TA_RTS_MASK                    0x00080000L
+#define TP0_CNTL_STATUS__FL_TA_RTS                         0x00080000L
+#define TP0_CNTL_STATUS__TA_FA_RTS_MASK                    0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_RTS                         0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK                 0x00200000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS                      0x00200000L
+#define TP0_CNTL_STATUS__FA_AL_RTS_MASK                    0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_RTS                         0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK                 0x00800000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS                      0x00800000L
+#define TP0_CNTL_STATUS__AL_TF_RTS_MASK                    0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_RTS                         0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK                 0x02000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS                      0x02000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS_MASK                    0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS                         0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK                 0x08000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS                      0x08000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS_MASK                    0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS                         0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK               0x20000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET                    0x20000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS_MASK                    0x40000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS                         0x40000000L
+#define TP0_CNTL_STATUS__TP_BUSY_MASK                      0x80000000L
+#define TP0_CNTL_STATUS__TP_BUSY                           0x80000000L
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL_MASK                         0x00000003L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK                     0x00000008L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP                          0x00000008L
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK               0x001ffff0L
+#define TP0_DEBUG__REG_CLK_EN_MASK                         0x00200000L
+#define TP0_DEBUG__REG_CLK_EN                              0x00200000L
+#define TP0_DEBUG__PERF_CLK_EN_MASK                        0x00400000L
+#define TP0_DEBUG__PERF_CLK_EN                             0x00400000L
+#define TP0_DEBUG__TP_CLK_EN_MASK                          0x00800000L
+#define TP0_DEBUG__TP_CLK_EN                               0x00800000L
+#define TP0_DEBUG__Q_WALKER_CNTL_MASK                      0x0f000000L
+#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK                     0x70000000L
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE_MASK                          0x00000001L
+#define TP0_CHICKEN__TT_MODE                               0x00000001L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK              0x00000002L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE                   0x00000002L
+#define TP0_CHICKEN__SPARE_MASK                            0xfffffffcL
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr_MASK                      0x00000040L
+#define TCF_DEBUG__not_MH_TC_rtr                           0x00000040L
+#define TCF_DEBUG__TC_MH_send_MASK                         0x00000080L
+#define TCF_DEBUG__TC_MH_send                              0x00000080L
+#define TCF_DEBUG__not_FG0_rtr_MASK                        0x00000100L
+#define TCF_DEBUG__not_FG0_rtr                             0x00000100L
+#define TCF_DEBUG__not_TCB_TCO_rtr_MASK                    0x00001000L
+#define TCF_DEBUG__not_TCB_TCO_rtr                         0x00001000L
+#define TCF_DEBUG__TCB_ff_stall_MASK                       0x00002000L
+#define TCF_DEBUG__TCB_ff_stall                            0x00002000L
+#define TCF_DEBUG__TCB_miss_stall_MASK                     0x00004000L
+#define TCF_DEBUG__TCB_miss_stall                          0x00004000L
+#define TCF_DEBUG__TCA_TCB_stall_MASK                      0x00008000L
+#define TCF_DEBUG__TCA_TCB_stall                           0x00008000L
+#define TCF_DEBUG__PF0_stall_MASK                          0x00010000L
+#define TCF_DEBUG__PF0_stall                               0x00010000L
+#define TCF_DEBUG__TP0_full_MASK                           0x00100000L
+#define TCF_DEBUG__TP0_full                                0x00100000L
+#define TCF_DEBUG__TPC_full_MASK                           0x01000000L
+#define TCF_DEBUG__TPC_full                                0x01000000L
+#define TCF_DEBUG__not_TPC_rtr_MASK                        0x02000000L
+#define TCF_DEBUG__not_TPC_rtr                             0x02000000L
+#define TCF_DEBUG__tca_state_rts_MASK                      0x04000000L
+#define TCF_DEBUG__tca_state_rts                           0x04000000L
+#define TCF_DEBUG__tca_rts_MASK                            0x08000000L
+#define TCF_DEBUG__tca_rts                                 0x08000000L
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full_MASK                      0x00000001L
+#define TCA_FIFO_DEBUG__tp0_full                           0x00000001L
+#define TCA_FIFO_DEBUG__tpc_full_MASK                      0x00000010L
+#define TCA_FIFO_DEBUG__tpc_full                           0x00000010L
+#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK                 0x00000020L
+#define TCA_FIFO_DEBUG__load_tpc_fifo                      0x00000020L
+#define TCA_FIFO_DEBUG__load_tp_fifos_MASK                 0x00000040L
+#define TCA_FIFO_DEBUG__load_tp_fifos                      0x00000040L
+#define TCA_FIFO_DEBUG__FW_full_MASK                       0x00000080L
+#define TCA_FIFO_DEBUG__FW_full                            0x00000080L
+#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK                   0x00000100L
+#define TCA_FIFO_DEBUG__not_FW_rtr0                        0x00000100L
+#define TCA_FIFO_DEBUG__FW_rts0_MASK                       0x00001000L
+#define TCA_FIFO_DEBUG__FW_rts0                            0x00001000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK                0x00010000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr                     0x00010000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK                    0x00020000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts                         0x00020000L
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK            0x00000001L
+#define TCA_PROBE_DEBUG__ProbeFilter_stall                 0x00000001L
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts_MASK               0x00001000L
+#define TCA_TPC_DEBUG__captue_state_rts                    0x00001000L
+#define TCA_TPC_DEBUG__capture_tca_rts_MASK                0x00002000L
+#define TCA_TPC_DEBUG__capture_tca_rts                     0x00002000L
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512_MASK                     0x00000001L
+#define TCB_CORE_DEBUG__access512                          0x00000001L
+#define TCB_CORE_DEBUG__tiled_MASK                         0x00000002L
+#define TCB_CORE_DEBUG__tiled                              0x00000002L
+#define TCB_CORE_DEBUG__opcode_MASK                        0x00000070L
+#define TCB_CORE_DEBUG__format_MASK                        0x00003f00L
+#define TCB_CORE_DEBUG__sector_format_MASK                 0x001f0000L
+#define TCB_CORE_DEBUG__sector_format512_MASK              0x07000000L
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG0_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG0_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG0_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG0_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG0_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG1_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG1_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG1_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG1_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG1_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG2_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG2_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG2_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG2_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG2_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG3_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG3_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG3_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG3_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG3_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done      0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left    0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q   0x10000000L
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK     0x00000030L
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK      0x000000c0L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK     0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left          0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK     0x00007000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK              0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy                   0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK  0x000f0000L
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK        0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts             0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK         0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts              0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK      0x0000fff0L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK   0x001f0000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK               0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy                    0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK           0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy                0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK            0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy                 0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK           0x0c000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK            0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q                 0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK            0x40000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR                 0x40000000L
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty_MASK                       0x00010000L
+#define TCD_INPUT0_DEBUG__empty                            0x00010000L
+#define TCD_INPUT0_DEBUG__full_MASK                        0x00020000L
+#define TCD_INPUT0_DEBUG__full                             0x00020000L
+#define TCD_INPUT0_DEBUG__valid_q1_MASK                    0x00100000L
+#define TCD_INPUT0_DEBUG__valid_q1                         0x00100000L
+#define TCD_INPUT0_DEBUG__cnt_q1_MASK                      0x00600000L
+#define TCD_INPUT0_DEBUG__last_send_q1_MASK                0x00800000L
+#define TCD_INPUT0_DEBUG__last_send_q1                     0x00800000L
+#define TCD_INPUT0_DEBUG__ip_send_MASK                     0x01000000L
+#define TCD_INPUT0_DEBUG__ip_send                          0x01000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK              0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send                   0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK                  0x04000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy                       0x04000000L
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK        0x00000003L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK            0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8                 0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK        0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send             0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK             0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send                  0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK                 0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall                      0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK                0x00000040L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate                     0x00000040L
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK               0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate                    0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK           0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr                0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK             0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr                  0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send      0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK  0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts       0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK    0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send         0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send     0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK     0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send          0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK        0x20000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send             0x20000000L
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK                  0x00000010L
+#define TCD_DXTC_ARB_DEBUG__n0_stall                       0x00000010L
+#define TCD_DXTC_ARB_DEBUG__pstate_MASK                    0x00000020L
+#define TCD_DXTC_ARB_DEBUG__pstate                         0x00000020L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK      0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send           0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK            0x00000180L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK         0x00000e00L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK      0x0003f000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK         0x3ffc0000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK           0x40000000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send                0x40000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK           0x80000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types                0x80000000L
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK     0x00000400L
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr          0x00000400L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK     0x00000800L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr          0x00000800L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK           0x00020000L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr                0x00020000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK         0x00040000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr              0x00040000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK            0x00080000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr                 0x00080000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK            0x80000000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr                 0x80000000L
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK            0x00000020L
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR                 0x00000020L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK             0x00000040L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR                  0x00000040L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK         0x00000080L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d              0x00000080L
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK         0x000000ffL
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK         0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample              0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK                   0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr                        0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK                   0x00000400L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts                        0x00000400L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK        0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample             0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK                  0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr                       0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK                  0x00002000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts                       0x00002000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK             0x00010000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q                  0x00010000L
+#define TCO_QUAD0_DEBUG0__read_cache_q_MASK                0x01000000L
+#define TCO_QUAD0_DEBUG0__read_cache_q                     0x01000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK              0x02000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR                   0x02000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK    0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3         0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK    0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2         0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK    0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1         0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK    0x20000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0         0x20000000L
+#define TCO_QUAD0_DEBUG0__busy_MASK                        0x40000000L
+#define TCO_QUAD0_DEBUG0__busy                             0x40000000L
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy_MASK                   0x00000001L
+#define TCO_QUAD0_DEBUG1__fifo_busy                        0x00000001L
+#define TCO_QUAD0_DEBUG1__empty_MASK                       0x00000002L
+#define TCO_QUAD0_DEBUG1__empty                            0x00000002L
+#define TCO_QUAD0_DEBUG1__full_MASK                        0x00000004L
+#define TCO_QUAD0_DEBUG1__full                             0x00000004L
+#define TCO_QUAD0_DEBUG1__write_enable_MASK                0x00000008L
+#define TCO_QUAD0_DEBUG1__write_enable                     0x00000008L
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK              0x000007f0L
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK               0x0003f800L
+#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK             0x00100000L
+#define TCO_QUAD0_DEBUG1__cache_read_busy                  0x00100000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK           0x00200000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy                0x00200000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK             0x00400000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy                  0x00400000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK          0x00800000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy               0x00800000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK               0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d                    0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK               0x02000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q                    0x02000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK                   0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr                        0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK                   0x08000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts                        0x08000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK                  0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr                       0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK                  0x20000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts                       0x20000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK            0x40000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc                 0x40000000L
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK                0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC                     0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK               0x000007f0L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK               0x0007f000L
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK     0x00000003L
+#define SQ_FLOW_CONTROL__ONE_THREAD_MASK                   0x00000010L
+#define SQ_FLOW_CONTROL__ONE_THREAD                        0x00000010L
+#define SQ_FLOW_CONTROL__ONE_ALU_MASK                      0x00000100L
+#define SQ_FLOW_CONTROL__ONE_ALU                           0x00000100L
+#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK                   0x0000f000L
+#define SQ_FLOW_CONTROL__NO_PV_PS_MASK                     0x00010000L
+#define SQ_FLOW_CONTROL__NO_PV_PS                          0x00010000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK                 0x00020000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT                      0x00020000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK            0x00040000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE                 0x00040000L
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK   0x00180000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK        0x00200000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY             0x00200000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK       0x00400000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY            0x00400000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK                 0x00800000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT                      0x00800000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK                 0x01000000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT                      0x01000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK             0x02000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY                  0x02000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK  0x04000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION       0x04000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK      0x08000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC           0x08000000L
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK        0x00000fffL
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK        0x0fff0000L
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK     0x01ff0000L
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT_MASK                     0x000000ffL
+#define SQ_EO_RT__EO_TSTATE_RT_MASK                        0x00ff0000L
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK                 0x000007ffL
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK                 0x000ff000L
+#define SQ_DEBUG_MISC__DB_READ_CTX_MASK                    0x00100000L
+#define SQ_DEBUG_MISC__DB_READ_CTX                         0x00100000L
+#define SQ_DEBUG_MISC__RESERVED_MASK                       0x00600000L
+#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK                 0x01800000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK                0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0                     0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK                0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1                     0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK                0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2                     0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK                0x10000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3                     0x10000000L
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK              0x000000ffL
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK         0x0000ff00L
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK        0x00ff0000L
+#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK                 0xff000000L
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK        0x000000ffL
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK        0x00000007L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK          0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN               0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK        0x00000070L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK          0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN               0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK              0x0003ff00L
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK       0x00000007L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK         0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN              0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK       0x00000070L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK         0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN              0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK             0x0003ff00L
+#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK              0x000c0000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK  0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL       0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK  0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL       0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK                 0x00000001L
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK                      0x00000001L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK                 0x00000002L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK                      0x00000002L
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK            0x00000001L
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT                 0x00000001L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK            0x00000002L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT                 0x00000002L
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK                   0x00000001L
+#define SQ_INT_ACK__PS_WATCHDOG_ACK                        0x00000001L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK                   0x00000002L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK                        0x00000002L
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK                 0x00000007L
+#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK                  0x00000008L
+#define SQ_DEBUG_INPUT_FSM__RESERVED                       0x00000008L
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK                 0x000000f0L
+#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK                   0x00000700L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1                      0x00000800L
+#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK                     0x00007000L
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK             0x000f8000L
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK               0x0ff00000L
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK             0x000000e0L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK             0x0000e000L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK  0x00030000L
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK  0x000c0000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK  0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE       0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK  0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE       0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK  0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE       0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK  0x00800000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE       0x00800000L
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP_MASK                        0x00000007L
+#define SQ_DEBUG_TP_FSM__RESERVED0_MASK                    0x00000008L
+#define SQ_DEBUG_TP_FSM__RESERVED0                         0x00000008L
+#define SQ_DEBUG_TP_FSM__CF_TP_MASK                        0x000000f0L
+#define SQ_DEBUG_TP_FSM__IF_TP_MASK                        0x00000700L
+#define SQ_DEBUG_TP_FSM__RESERVED1_MASK                    0x00000800L
+#define SQ_DEBUG_TP_FSM__RESERVED1                         0x00000800L
+#define SQ_DEBUG_TP_FSM__TIS_TP_MASK                       0x00003000L
+#define SQ_DEBUG_TP_FSM__RESERVED2_MASK                    0x0000c000L
+#define SQ_DEBUG_TP_FSM__GS_TP_MASK                        0x00030000L
+#define SQ_DEBUG_TP_FSM__RESERVED3_MASK                    0x000c0000L
+#define SQ_DEBUG_TP_FSM__FCR_TP_MASK                       0x00300000L
+#define SQ_DEBUG_TP_FSM__RESERVED4_MASK                    0x00c00000L
+#define SQ_DEBUG_TP_FSM__FCS_TP_MASK                       0x03000000L
+#define SQ_DEBUG_TP_FSM__RESERVED5_MASK                    0x0c000000L
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK                    0x70000000L
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK             0x0000000fL
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK           0x00000ff0L
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK              0x00007000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK                  0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED                       0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK       0x003f0000L
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK              0x00000001L
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER                   0x00000001L
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK                0x0000001eL
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK            0x00000020L
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR                 0x00000020L
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK           0x000001c0L
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK                0x00003e00L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK                 0x00004000L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT                      0x00004000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK          0x00008000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON               0x00008000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK                   0x00010000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY                        0x00010000L
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK               0x0ffe0000L
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_VTX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_VTX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_VTX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_PIX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_PIX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_PIX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN     0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN     0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK     0x60000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC    0x80000000L
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK             0x0000000fL
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK                 0x000000f0L
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK                 0x00000f00L
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK          0x0000f000L
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK           0x000f0000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK              0x00100000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL                   0x00100000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK                     0x00200000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q                          0x00200000L
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK                0x0000ffffL
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK     0xffffffffL
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK       0xffffffffL
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK               0x0000003fL
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK                   0x00000fc0L
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK                   0x0007f000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK          0x01f80000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK            0x7e000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY_MASK                       0x80000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY                            0x80000000L
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK   0xffffffffL
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK          0x00000040L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL               0x00000040L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK    0x00000080L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP         0x00000080L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK          0x00004000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL               0x00004000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK             0x00008000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA                  0x00008000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK          0x000f0000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK          0x00f00000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK            0x01000000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP                 0x01000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK            0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP                 0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK           0xfc000000L
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK         0x00000003L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK         0x0000000cL
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK         0x00000030L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK         0x000000c0L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK         0x00000300L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK         0x00000c00L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK         0x00003000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK         0x0000c000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK         0x00030000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK         0x000c0000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK         0x00300000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK         0x00c00000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK           0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD                0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK           0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD                0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK           0x04000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD                0x04000000L
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK             0x18000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK           0x20000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR                0x20000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK         0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS              0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK         0x80000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS              0x80000000L
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK            0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C                 0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK           0x00000080L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C                0x00000080L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK            0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B                 0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK           0x00008000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B                0x00008000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK           0x003f0000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK            0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A                 0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK           0x00800000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A                0x00800000L
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK           0x1f000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK               0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL                    0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK               0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL                    0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK               0x80000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK             0x000001ffL
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK            0x00000e00L
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK               0x00007000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK               0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD                    0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK         0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0              0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0            0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK         0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1              0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK       0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1            0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK         0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2              0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK       0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2            0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK         0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3              0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK       0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3            0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK         0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4              0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK       0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4            0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK         0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5              0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK       0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5            0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK           0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0                0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK           0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1                0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK           0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2                0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK           0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3                0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK           0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4                0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK           0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5                0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK           0x000003fcL
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK           0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION                0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK             0x01ff0000L
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK            0x0e000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK               0x70000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK               0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK         0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0              0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0            0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK         0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1              0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK       0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1            0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK         0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2              0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK       0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2            0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK         0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3              0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK       0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3            0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK         0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4              0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK       0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4            0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK         0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5              0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK       0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5            0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK           0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0                0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK           0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1                0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK           0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2                0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK           0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3                0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK           0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4                0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK           0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5                0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK           0x03fc0000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK           0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION                0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK             0x000003ffL
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK          0x0000fc00L
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK             0x001f0000L
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK          0xffe00000L
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK          0x000007ffL
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK             0x03ff0000L
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK          0xfc000000L
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK             0x0000001fL
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK            0x07ffffe0L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK         0x000003ffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK      0x00001c00L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK      0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL           0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK  0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP       0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK      0xffff8000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK      0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0           0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION            0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK       0x000003fcL
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK       0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION            0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK    0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE         0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK          0x0000f000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK         0x03ff0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK      0x1c000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK      0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL           0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK      0xc0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK        0x0001ffffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION            0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK       0x03fc0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK       0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION            0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK    0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE         0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK          0xf0000000L
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK               0x0000000fL
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK           0xfffffff0L
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK         0x000000ffL
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK          0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL               0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK      0x00000600L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK         0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE              0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK             0x0000f000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK               0x000f0000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK         0xfff00000L
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK           0x00ffffffL
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK          0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL               0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK      0x06000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK         0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE              0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK             0xf0000000L
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK     0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY          0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK      0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM           0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK            0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK            0x30000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK            0xc0000000L
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK           0x00003000L
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK           0x0000c000L
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK           0x00030000L
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK         0x001c0000L
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK     0x00e00000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK       0x03000000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK       0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK         0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD              0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK          0x60000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK    0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS         0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK      0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION           0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK             0x000001fcL
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK               0x0000fe00L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK             0x001f0000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK             0x03e00000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK             0x7c000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK          0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE               0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK      0x06000000L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK              0xc0000000L
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK      0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL           0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK       0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL            0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK   0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL        0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK          0x003f0000L
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK       0x3f800000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK               0x000000ffL
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK               0x00ff0000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED_MASK                            0xffffffffL
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN_MASK                          0xffffffffL
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE_MASK                           0xffffffffL
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA_MASK                          0xffffffffL
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE_MASK                             0xffffffffL
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE_MASK                    0x00000001L
+#define SQ_CONSTANT_VFETCH_0__TYPE                         0x00000001L
+#define SQ_CONSTANT_VFETCH_0__STATE_MASK                   0x00000002L
+#define SQ_CONSTANT_VFETCH_0__STATE                        0x00000002L
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK            0xfffffffcL
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK             0x00000003L
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK           0xfffffffcL
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE_MASK                         0xffffffffL
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE_MASK                         0xffffffffL
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK                 0x000000ffL
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK                 0x0000ff00L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK                 0x00ff0000L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK                 0xff000000L
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK                     0x000000ffL
+#define SQ_CF_LOOP__CF_LOOP_START_MASK                     0x0000ff00L
+#define SQ_CF_LOOP__CF_LOOP_STEP_MASK                      0x00ff0000L
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED_MASK                         0xffffffffL
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN_MASK                       0xffffffffL
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE_MASK                        0xffffffffL
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA_MASK                       0xffffffffL
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE_MASK                          0xffffffffL
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK              0x000000ffL
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK              0x0000ff00L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK              0x00ff0000L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK              0xff000000L
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK                  0x000000ffL
+#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK                  0x0000ff00L
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK                   0x00ff0000L
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_VS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_PS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK                0x000007ffL
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK                0x007ff000L
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK             0x0000ffffL
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK        0xffff0000L
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK                   0x0000003fL
+#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK                   0x00003f00L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK                  0x00010000L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE                       0x00010000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK                  0x00020000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE                       0x00020000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK                    0x00040000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN                         0x00040000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK                0x00080000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX                     0x00080000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK              0x00f00000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK               0x07000000L
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK               0x78000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK                0x80000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX                     0x80000000L
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK                   0x0000000fL
+#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK                   0x000000f0L
+#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK                   0x00000f00L
+#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK                   0x0000f000L
+#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK                   0x000f0000L
+#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK                   0x00f00000L
+#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK                   0x0f000000L
+#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK                   0xf0000000L
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK                   0x0000000fL
+#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK                   0x000000f0L
+#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK                  0x00000f00L
+#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK                  0x0000f000L
+#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK                  0x000f0000L
+#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK                  0x00f00000L
+#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK                  0x0f000000L
+#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK                  0xf0000000L
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_VS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_PS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK           0x00000001L
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE                0x00000001L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK          0x00000002L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY               0x00000002L
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK               0x0000000cL
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK                0x0000ff00L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK              0x00010000L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF                   0x00010000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK               0x00020000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE                    0x00020000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK                 0x00040000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL                      0x00040000L
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE_MASK                        0x00000007L
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK                   0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_ON                        0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK                0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK                     0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK                 0x0007ff00L
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK                0xff000000L
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK                    0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_PIX                         0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK                    0x00000002L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX                         0x00000002L
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK                0x0000ff00L
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK                0x07ff0000L
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK            0x0000003fL
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK      0x00000040L
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY           0x00000040L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK              0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE                   0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK         0x00000100L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE              0x00000100L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK             0x00000200L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL                  0x00000200L
+#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK                  0x00001c00L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK          0x00002000L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE               0x00002000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK         0x00004000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE              0x00004000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK     0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE          0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK            0x003f0000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK             0x00400000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE                  0x00400000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK            0x00800000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE                 0x00800000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK             0x01000000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE                  0x01000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK             0x02000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE                  0x02000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK             0x04000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE                  0x04000000L
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK                  0x00000007L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK               0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1                    0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK                  0x00000070L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK               0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2                    0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK                 0x00000700L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK               0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3                    0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK                  0x00007000L
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK             0x00000001L
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR                  0x00000001L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK            0x00000002L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR                 0x00000002L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK             0x00000004L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT                  0x00000004L
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK           0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR                0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK          0x00000002L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR               0x00000002L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK           0x00000004L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT                0x00000004L
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK            0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR                 0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK           0x00000002L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR                0x00000002L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK            0x00000004L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT                 0x00000004L
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID_MASK                     0x00000007L
+#define MH_AXI_ERROR__AXI_READ_ERROR_MASK                  0x00000008L
+#define MH_AXI_ERROR__AXI_READ_ERROR                       0x00000008L
+#define MH_AXI_ERROR__AXI_WRITE_ID_MASK                    0x00000070L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK                 0x00000080L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR                      0x00000080L
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX_MASK                          0x0000003fL
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA_MASK                           0xffffffffL
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK                 0x00000001L
+#define MH_AXI_HALT_CONTROL__AXI_HALT                      0x00000001L
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY_MASK                       0x00000001L
+#define MH_DEBUG_REG00__MH_BUSY                            0x00000001L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK             0x00000002L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING                  0x00000002L
+#define MH_DEBUG_REG00__CP_REQUEST_MASK                    0x00000004L
+#define MH_DEBUG_REG00__CP_REQUEST                         0x00000004L
+#define MH_DEBUG_REG00__VGT_REQUEST_MASK                   0x00000008L
+#define MH_DEBUG_REG00__VGT_REQUEST                        0x00000008L
+#define MH_DEBUG_REG00__TC_REQUEST_MASK                    0x00000010L
+#define MH_DEBUG_REG00__TC_REQUEST                         0x00000010L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK                  0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY                       0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_FULL_MASK                   0x00000040L
+#define MH_DEBUG_REG00__TC_CAM_FULL                        0x00000040L
+#define MH_DEBUG_REG00__TCD_EMPTY_MASK                     0x00000080L
+#define MH_DEBUG_REG00__TCD_EMPTY                          0x00000080L
+#define MH_DEBUG_REG00__TCD_FULL_MASK                      0x00000100L
+#define MH_DEBUG_REG00__TCD_FULL                           0x00000100L
+#define MH_DEBUG_REG00__RB_REQUEST_MASK                    0x00000200L
+#define MH_DEBUG_REG00__RB_REQUEST                         0x00000200L
+#define MH_DEBUG_REG00__PA_REQUEST_MASK                    0x00000400L
+#define MH_DEBUG_REG00__PA_REQUEST                         0x00000400L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK               0x00000800L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE                    0x00000800L
+#define MH_DEBUG_REG00__ARQ_EMPTY_MASK                     0x00001000L
+#define MH_DEBUG_REG00__ARQ_EMPTY                          0x00001000L
+#define MH_DEBUG_REG00__ARQ_FULL_MASK                      0x00002000L
+#define MH_DEBUG_REG00__ARQ_FULL                           0x00002000L
+#define MH_DEBUG_REG00__WDB_EMPTY_MASK                     0x00004000L
+#define MH_DEBUG_REG00__WDB_EMPTY                          0x00004000L
+#define MH_DEBUG_REG00__WDB_FULL_MASK                      0x00008000L
+#define MH_DEBUG_REG00__WDB_FULL                           0x00008000L
+#define MH_DEBUG_REG00__AXI_AVALID_MASK                    0x00010000L
+#define MH_DEBUG_REG00__AXI_AVALID                         0x00010000L
+#define MH_DEBUG_REG00__AXI_AREADY_MASK                    0x00020000L
+#define MH_DEBUG_REG00__AXI_AREADY                         0x00020000L
+#define MH_DEBUG_REG00__AXI_ARVALID_MASK                   0x00040000L
+#define MH_DEBUG_REG00__AXI_ARVALID                        0x00040000L
+#define MH_DEBUG_REG00__AXI_ARREADY_MASK                   0x00080000L
+#define MH_DEBUG_REG00__AXI_ARREADY                        0x00080000L
+#define MH_DEBUG_REG00__AXI_WVALID_MASK                    0x00100000L
+#define MH_DEBUG_REG00__AXI_WVALID                         0x00100000L
+#define MH_DEBUG_REG00__AXI_WREADY_MASK                    0x00200000L
+#define MH_DEBUG_REG00__AXI_WREADY                         0x00200000L
+#define MH_DEBUG_REG00__AXI_RVALID_MASK                    0x00400000L
+#define MH_DEBUG_REG00__AXI_RVALID                         0x00400000L
+#define MH_DEBUG_REG00__AXI_RREADY_MASK                    0x00800000L
+#define MH_DEBUG_REG00__AXI_RREADY                         0x00800000L
+#define MH_DEBUG_REG00__AXI_BVALID_MASK                    0x01000000L
+#define MH_DEBUG_REG00__AXI_BVALID                         0x01000000L
+#define MH_DEBUG_REG00__AXI_BREADY_MASK                    0x02000000L
+#define MH_DEBUG_REG00__AXI_BREADY                         0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK                  0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ                       0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK                  0x08000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK                       0x08000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK                   0x10000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA                        0x10000000L
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q_MASK                     0x00000001L
+#define MH_DEBUG_REG01__CP_SEND_q                          0x00000001L
+#define MH_DEBUG_REG01__CP_RTR_q_MASK                      0x00000002L
+#define MH_DEBUG_REG01__CP_RTR_q                           0x00000002L
+#define MH_DEBUG_REG01__CP_WRITE_q_MASK                    0x00000004L
+#define MH_DEBUG_REG01__CP_WRITE_q                         0x00000004L
+#define MH_DEBUG_REG01__CP_TAG_q_MASK                      0x00000038L
+#define MH_DEBUG_REG01__CP_BLEN_q_MASK                     0x00000040L
+#define MH_DEBUG_REG01__CP_BLEN_q                          0x00000040L
+#define MH_DEBUG_REG01__VGT_SEND_q_MASK                    0x00000080L
+#define MH_DEBUG_REG01__VGT_SEND_q                         0x00000080L
+#define MH_DEBUG_REG01__VGT_RTR_q_MASK                     0x00000100L
+#define MH_DEBUG_REG01__VGT_RTR_q                          0x00000100L
+#define MH_DEBUG_REG01__VGT_TAG_q_MASK                     0x00000200L
+#define MH_DEBUG_REG01__VGT_TAG_q                          0x00000200L
+#define MH_DEBUG_REG01__TC_SEND_q_MASK                     0x00000400L
+#define MH_DEBUG_REG01__TC_SEND_q                          0x00000400L
+#define MH_DEBUG_REG01__TC_RTR_q_MASK                      0x00000800L
+#define MH_DEBUG_REG01__TC_RTR_q                           0x00000800L
+#define MH_DEBUG_REG01__TC_BLEN_q_MASK                     0x00001000L
+#define MH_DEBUG_REG01__TC_BLEN_q                          0x00001000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK                 0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q                      0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK                  0x00004000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q                       0x00004000L
+#define MH_DEBUG_REG01__TC_MH_written_MASK                 0x00008000L
+#define MH_DEBUG_REG01__TC_MH_written                      0x00008000L
+#define MH_DEBUG_REG01__RB_SEND_q_MASK                     0x00010000L
+#define MH_DEBUG_REG01__RB_SEND_q                          0x00010000L
+#define MH_DEBUG_REG01__RB_RTR_q_MASK                      0x00020000L
+#define MH_DEBUG_REG01__RB_RTR_q                           0x00020000L
+#define MH_DEBUG_REG01__PA_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG01__PA_SEND_q                          0x00040000L
+#define MH_DEBUG_REG01__PA_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG01__PA_RTR_q                           0x00080000L
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG02__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG02__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG02__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG02__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK                 0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_rlast                      0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_tag_MASK                   0x00000070L
+#define MH_DEBUG_REG02__RDC_RID_MASK                       0x00000380L
+#define MH_DEBUG_REG02__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG02__MH_CP_writeclean_MASK              0x00001000L
+#define MH_DEBUG_REG02__MH_CP_writeclean                   0x00001000L
+#define MH_DEBUG_REG02__MH_RB_writeclean_MASK              0x00002000L
+#define MH_DEBUG_REG02__MH_RB_writeclean                   0x00002000L
+#define MH_DEBUG_REG02__MH_PA_writeclean_MASK              0x00004000L
+#define MH_DEBUG_REG02__MH_PA_writeclean                   0x00004000L
+#define MH_DEBUG_REG02__BRC_BID_MASK                       0x00038000L
+#define MH_DEBUG_REG02__BRC_BRESP_MASK                     0x000c0000L
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK             0xffffffffL
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK            0xffffffffL
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG05__CP_MH_send                         0x00000001L
+#define MH_DEBUG_REG05__CP_MH_write_MASK                   0x00000002L
+#define MH_DEBUG_REG05__CP_MH_write                        0x00000002L
+#define MH_DEBUG_REG05__CP_MH_tag_MASK                     0x0000001cL
+#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK                 0xffffffe0L
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be_MASK                      0x000000ffL
+#define MH_DEBUG_REG08__RB_MH_be_MASK                      0x0000ff00L
+#define MH_DEBUG_REG08__PA_MH_be_MASK                      0x00ff0000L
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK                   0x00000007L
+#define MH_DEBUG_REG09__VGT_MH_send_MASK                   0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_send                        0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK                  0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_tagbe                       0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK                0xffffffe0L
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG10__TC_MH_send_MASK                    0x00000004L
+#define MH_DEBUG_REG10__TC_MH_send                         0x00000004L
+#define MH_DEBUG_REG10__TC_MH_mask_MASK                    0x00000018L
+#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info_MASK                    0x01ffffffL
+#define MH_DEBUG_REG11__TC_MH_send_MASK                    0x02000000L
+#define MH_DEBUG_REG11__TC_MH_send                         0x02000000L
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK                  0x01ffffffL
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK             0x02000000L
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send                  0x02000000L
+#define MH_DEBUG_REG12__TC_MH_written_MASK                 0x04000000L
+#define MH_DEBUG_REG12__TC_MH_written                      0x04000000L
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK                   0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_SEND                        0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK                   0x00000018L
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK              0xffffffe0L
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK                   0x01ffffffL
+#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK                   0x02000000L
+#define MH_DEBUG_REG14__TC_ROQ_SEND                        0x02000000L
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG15__RB_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG15__RB_MH_send                         0x00000010L
+#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG18__PA_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG18__PA_MH_send                         0x00000010L
+#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG21__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG21__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG21__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG21__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG21__ALEN_q_2_0_MASK                    0x000000e0L
+#define MH_DEBUG_REG21__ARVALID_q_MASK                     0x00000100L
+#define MH_DEBUG_REG21__ARVALID_q                          0x00000100L
+#define MH_DEBUG_REG21__ARREADY_q_MASK                     0x00000200L
+#define MH_DEBUG_REG21__ARREADY_q                          0x00000200L
+#define MH_DEBUG_REG21__ARID_q_MASK                        0x00001c00L
+#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK                   0x00006000L
+#define MH_DEBUG_REG21__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG21__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG21__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG21__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG21__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG21__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG21__RID_q_MASK                         0x001c0000L
+#define MH_DEBUG_REG21__WVALID_q_MASK                      0x00200000L
+#define MH_DEBUG_REG21__WVALID_q                           0x00200000L
+#define MH_DEBUG_REG21__WREADY_q_MASK                      0x00400000L
+#define MH_DEBUG_REG21__WREADY_q                           0x00400000L
+#define MH_DEBUG_REG21__WLAST_q_MASK                       0x00800000L
+#define MH_DEBUG_REG21__WLAST_q                            0x00800000L
+#define MH_DEBUG_REG21__WID_q_MASK                         0x07000000L
+#define MH_DEBUG_REG21__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG21__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG21__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG21__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG21__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG22__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG22__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG22__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG22__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG22__ALEN_q_1_0_MASK                    0x00000060L
+#define MH_DEBUG_REG22__ARVALID_q_MASK                     0x00000080L
+#define MH_DEBUG_REG22__ARVALID_q                          0x00000080L
+#define MH_DEBUG_REG22__ARREADY_q_MASK                     0x00000100L
+#define MH_DEBUG_REG22__ARREADY_q                          0x00000100L
+#define MH_DEBUG_REG22__ARID_q_MASK                        0x00000e00L
+#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK                   0x00001000L
+#define MH_DEBUG_REG22__ARLEN_q_1_1                        0x00001000L
+#define MH_DEBUG_REG22__WVALID_q_MASK                      0x00002000L
+#define MH_DEBUG_REG22__WVALID_q                           0x00002000L
+#define MH_DEBUG_REG22__WREADY_q_MASK                      0x00004000L
+#define MH_DEBUG_REG22__WREADY_q                           0x00004000L
+#define MH_DEBUG_REG22__WLAST_q_MASK                       0x00008000L
+#define MH_DEBUG_REG22__WLAST_q                            0x00008000L
+#define MH_DEBUG_REG22__WID_q_MASK                         0x00070000L
+#define MH_DEBUG_REG22__WSTRB_q_MASK                       0x07f80000L
+#define MH_DEBUG_REG22__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG22__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG22__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG22__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG22__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q                      0x00000001L
+#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK                   0x0000000eL
+#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK                  0xfffffff0L
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG24__REG_A_MASK                         0x0000fffcL
+#define MH_DEBUG_REG24__REG_RE_MASK                        0x00010000L
+#define MH_DEBUG_REG24__REG_RE                             0x00010000L
+#define MH_DEBUG_REG24__REG_WE_MASK                        0x00020000L
+#define MH_DEBUG_REG24__REG_WE                             0x00020000L
+#define MH_DEBUG_REG24__BLOCK_RS_MASK                      0x00040000L
+#define MH_DEBUG_REG24__BLOCK_RS                           0x00040000L
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD_MASK                        0xffffffffL
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy_MASK                  0x00000001L
+#define MH_DEBUG_REG26__MH_RBBM_busy                       0x00000001L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK          0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int               0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK         0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int              0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK       0x00000008L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int            0x00000008L
+#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK                   0x00000010L
+#define MH_DEBUG_REG26__GAT_CLK_ENA                        0x00000010L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK       0x00000020L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override            0x00000020L
+#define MH_DEBUG_REG26__CNT_q_MASK                         0x00000fc0L
+#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK                   0x00001000L
+#define MH_DEBUG_REG26__TCD_EMPTY_q                        0x00001000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK                  0x00002000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY                       0x00002000L
+#define MH_DEBUG_REG26__MH_BUSY_d_MASK                     0x00004000L
+#define MH_DEBUG_REG26__MH_BUSY_d                          0x00004000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK                 0x00008000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY                      0x00008000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL   0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC    0x00020000L
+#define MH_DEBUG_REG26__CP_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG26__CP_SEND_q                          0x00040000L
+#define MH_DEBUG_REG26__CP_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG26__CP_RTR_q                           0x00080000L
+#define MH_DEBUG_REG26__VGT_SEND_q_MASK                    0x00100000L
+#define MH_DEBUG_REG26__VGT_SEND_q                         0x00100000L
+#define MH_DEBUG_REG26__VGT_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG26__VGT_RTR_q                          0x00200000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK                 0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q                      0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK              0x00800000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q                   0x00800000L
+#define MH_DEBUG_REG26__RB_SEND_q_MASK                     0x01000000L
+#define MH_DEBUG_REG26__RB_SEND_q                          0x01000000L
+#define MH_DEBUG_REG26__RB_RTR_q_MASK                      0x02000000L
+#define MH_DEBUG_REG26__RB_RTR_q                           0x02000000L
+#define MH_DEBUG_REG26__PA_SEND_q_MASK                     0x04000000L
+#define MH_DEBUG_REG26__PA_SEND_q                          0x04000000L
+#define MH_DEBUG_REG26__PA_RTR_q_MASK                      0x08000000L
+#define MH_DEBUG_REG26__PA_RTR_q                           0x08000000L
+#define MH_DEBUG_REG26__RDC_VALID_MASK                     0x10000000L
+#define MH_DEBUG_REG26__RDC_VALID                          0x10000000L
+#define MH_DEBUG_REG26__RDC_RLAST_MASK                     0x20000000L
+#define MH_DEBUG_REG26__RDC_RLAST                          0x20000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID_MASK                 0x40000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID                      0x40000000L
+#define MH_DEBUG_REG26__BRC_VALID_MASK                     0x80000000L
+#define MH_DEBUG_REG26__BRC_VALID                          0x80000000L
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK                0x00000007L
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK           0x00000038L
+#define MH_DEBUG_REG27__EFF1_WINNER_MASK                   0x000001c0L
+#define MH_DEBUG_REG27__ARB_WINNER_MASK                    0x00000e00L
+#define MH_DEBUG_REG27__ARB_WINNER_q_MASK                  0x00007000L
+#define MH_DEBUG_REG27__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG27__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG27__KILL_EFF1_MASK                     0x00010000L
+#define MH_DEBUG_REG27__KILL_EFF1                          0x00010000L
+#define MH_DEBUG_REG27__ARB_HOLD_MASK                      0x00020000L
+#define MH_DEBUG_REG27__ARB_HOLD                           0x00020000L
+#define MH_DEBUG_REG27__ARB_RTR_q_MASK                     0x00040000L
+#define MH_DEBUG_REG27__ARB_RTR_q                          0x00040000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK                  0x00080000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL                       0x00080000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK                 0x00100000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL                      0x00100000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK                  0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL                       0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK             0x00400000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL                  0x00400000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK                  0x00800000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL                       0x00800000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK                  0x01000000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL                       0x01000000L
+#define MH_DEBUG_REG27__ARB_QUAL_MASK                      0x02000000L
+#define MH_DEBUG_REG27__ARB_QUAL                           0x02000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK                   0x04000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ                        0x04000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK                  0x08000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ                       0x08000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK                   0x10000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ                        0x10000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK                   0x20000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ                        0x20000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK                0x40000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q                     0x40000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK                   0x80000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q                        0x80000000L
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER_MASK                   0x00000007L
+#define MH_DEBUG_REG28__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK                  0x00000040L
+#define MH_DEBUG_REG28__CP_SEND_QUAL                       0x00000040L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK                 0x00000080L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL                      0x00000080L
+#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK                  0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_QUAL                       0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK             0x00000200L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL                  0x00000200L
+#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK                  0x00000400L
+#define MH_DEBUG_REG28__RB_SEND_QUAL                       0x00000400L
+#define MH_DEBUG_REG28__ARB_QUAL_MASK                      0x00000800L
+#define MH_DEBUG_REG28__ARB_QUAL                           0x00000800L
+#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK                   0x00001000L
+#define MH_DEBUG_REG28__CP_EFF1_REQ                        0x00001000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK                  0x00002000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ                       0x00002000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK                   0x00004000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ                        0x00004000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK                   0x00008000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ                        0x00008000L
+#define MH_DEBUG_REG28__EFF1_WIN_MASK                      0x00010000L
+#define MH_DEBUG_REG28__EFF1_WIN                           0x00010000L
+#define MH_DEBUG_REG28__KILL_EFF1_MASK                     0x00020000L
+#define MH_DEBUG_REG28__KILL_EFF1                          0x00020000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK                0x00040000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q                     0x00040000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK                   0x00080000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD                        0x00080000L
+#define MH_DEBUG_REG28__ARB_HOLD_MASK                      0x00100000L
+#define MH_DEBUG_REG28__ARB_HOLD                           0x00100000L
+#define MH_DEBUG_REG28__ARB_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG28__ARB_RTR_q                          0x00200000L
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK       0xffc00000L
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK           0x00000007L
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK          0x00000038L
+#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK                0x000001c0L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK         0x00000200L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d              0x00000200L
+#define MH_DEBUG_REG29__ARB_HOLD_MASK                      0x00000400L
+#define MH_DEBUG_REG29__ARB_HOLD                           0x00000400L
+#define MH_DEBUG_REG29__ARB_RTR_q_MASK                     0x00000800L
+#define MH_DEBUG_REG29__ARB_RTR_q                          0x00000800L
+#define MH_DEBUG_REG29__CLNT_REQ_MASK                      0x0001f000L
+#define MH_DEBUG_REG29__RECENT_d_0_MASK                    0x000e0000L
+#define MH_DEBUG_REG29__RECENT_d_1_MASK                    0x00700000L
+#define MH_DEBUG_REG29__RECENT_d_2_MASK                    0x03800000L
+#define MH_DEBUG_REG29__RECENT_d_3_MASK                    0x1c000000L
+#define MH_DEBUG_REG29__RECENT_d_4_MASK                    0xe0000000L
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK                   0x00000001L
+#define MH_DEBUG_REG30__TC_ARB_HOLD                        0x00000001L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK        0x00000002L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK             0x00000002L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK          0x00000004L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK               0x00000004L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK                0x00000008L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q                     0x00000008L
+#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK                   0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_IP_q                        0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK                  0x000000e0L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK              0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q                   0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK                 0x00000400L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q                      0x00000400L
+#define MH_DEBUG_REG30__TC_MH_written_MASK                 0x00000800L
+#define MH_DEBUG_REG30__TC_MH_written                      0x00000800L
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK            0x0007f000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK                 0x00080000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE                      0x00080000L
+#define MH_DEBUG_REG30__WLAST_q_MASK                       0x00100000L
+#define MH_DEBUG_REG30__WLAST_q                            0x00100000L
+#define MH_DEBUG_REG30__WBURST_IP_q_MASK                   0x00200000L
+#define MH_DEBUG_REG30__WBURST_IP_q                        0x00200000L
+#define MH_DEBUG_REG30__WBURST_CNT_q_MASK                  0x01c00000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK                  0x02000000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL                       0x02000000L
+#define MH_DEBUG_REG30__CP_MH_write_MASK                   0x04000000L
+#define MH_DEBUG_REG30__CP_MH_write                        0x04000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK                  0x08000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL                       0x08000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK                  0x10000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL                       0x10000000L
+#define MH_DEBUG_REG30__ARB_WINNER_MASK                    0xe0000000L
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK           0x03ffffffL
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0x1c000000L
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG32__ROQ_MARK_q_MASK                    0x0000ff00L
+#define MH_DEBUG_REG32__ROQ_VALID_q_MASK                   0x00ff0000L
+#define MH_DEBUG_REG32__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG32__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG32__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG32__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG33__ROQ_MARK_d_MASK                    0x0000ff00L
+#define MH_DEBUG_REG33__ROQ_VALID_d_MASK                   0x00ff0000L
+#define MH_DEBUG_REG33__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG33__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG33__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG33__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK             0x000000ffL
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK             0x0000ff00L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK         0x00ff0000L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK         0xff000000L
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG35__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK                  0x00000004L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0                       0x00000004L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK                 0x00000008L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0                      0x00000008L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK             0x00000010L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0                  0x00000010L
+#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG36__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK                  0x00000004L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1                       0x00000004L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK                 0x00000008L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1                      0x00000008L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK             0x00000010L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1                  0x00000010L
+#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG37__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK                  0x00000004L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2                       0x00000004L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK                 0x00000008L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2                      0x00000008L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK             0x00000010L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2                  0x00000010L
+#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG38__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK                  0x00000004L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3                       0x00000004L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK                 0x00000008L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3                      0x00000008L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK             0x00000010L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3                  0x00000010L
+#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG39__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK                  0x00000004L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4                       0x00000004L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK                 0x00000008L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4                      0x00000008L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK             0x00000010L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4                  0x00000010L
+#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG40__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK                  0x00000004L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5                       0x00000004L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK                 0x00000008L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5                      0x00000008L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK             0x00000010L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5                  0x00000010L
+#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG41__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK                  0x00000004L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6                       0x00000004L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK                 0x00000008L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6                      0x00000008L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK             0x00000010L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6                  0x00000010L
+#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG42__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK                  0x00000004L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7                       0x00000004L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK                 0x00000008L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7                      0x00000008L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK             0x00000010L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7                  0x00000010L
+#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK                  0x00000001L
+#define MH_DEBUG_REG43__ARB_REG_WE_q                       0x00000001L
+#define MH_DEBUG_REG43__ARB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG43__ARB_WE                             0x00000002L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK               0x00000004L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q                    0x00000004L
+#define MH_DEBUG_REG43__ARB_RTR_q_MASK                     0x00000008L
+#define MH_DEBUG_REG43__ARB_RTR_q                          0x00000008L
+#define MH_DEBUG_REG43__ARB_REG_RTR_MASK                   0x00000010L
+#define MH_DEBUG_REG43__ARB_REG_RTR                        0x00000010L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK                0x00000020L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR                     0x00000020L
+#define MH_DEBUG_REG43__MMU_RTR_MASK                       0x00000040L
+#define MH_DEBUG_REG43__MMU_RTR                            0x00000040L
+#define MH_DEBUG_REG43__ARB_ID_q_MASK                      0x00000380L
+#define MH_DEBUG_REG43__ARB_WRITE_q_MASK                   0x00000400L
+#define MH_DEBUG_REG43__ARB_WRITE_q                        0x00000400L
+#define MH_DEBUG_REG43__ARB_BLEN_q_MASK                    0x00000800L
+#define MH_DEBUG_REG43__ARB_BLEN_q                         0x00000800L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK                0x00001000L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY                     0x00001000L
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK                0x0000e000L
+#define MH_DEBUG_REG43__MMU_WE_MASK                        0x00010000L
+#define MH_DEBUG_REG43__MMU_WE                             0x00010000L
+#define MH_DEBUG_REG43__ARQ_RTR_MASK                       0x00020000L
+#define MH_DEBUG_REG43__ARQ_RTR                            0x00020000L
+#define MH_DEBUG_REG43__MMU_ID_MASK                        0x001c0000L
+#define MH_DEBUG_REG43__MMU_WRITE_MASK                     0x00200000L
+#define MH_DEBUG_REG43__MMU_WRITE                          0x00200000L
+#define MH_DEBUG_REG43__MMU_BLEN_MASK                      0x00400000L
+#define MH_DEBUG_REG43__MMU_BLEN                           0x00400000L
+#define MH_DEBUG_REG43__WBURST_IP_q_MASK                   0x00800000L
+#define MH_DEBUG_REG43__WBURST_IP_q                        0x00800000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK                 0x01000000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q                      0x01000000L
+#define MH_DEBUG_REG43__WDB_WE_MASK                        0x02000000L
+#define MH_DEBUG_REG43__WDB_WE                             0x02000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK                0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4                     0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK                0x08000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3                     0x08000000L
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG44__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG44__ARB_ID_q_MASK                      0x0000000eL
+#define MH_DEBUG_REG44__ARB_VAD_q_MASK                     0xfffffff0L
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG45__MMU_WE                             0x00000001L
+#define MH_DEBUG_REG45__MMU_ID_MASK                        0x0000000eL
+#define MH_DEBUG_REG45__MMU_PAD_MASK                       0xfffffff0L
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG46__WDAT_REG_WE_q                      0x00000001L
+#define MH_DEBUG_REG46__WDB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG46__WDB_WE                             0x00000002L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK              0x00000004L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q                   0x00000004L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK                0x00000008L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4                     0x00000008L
+#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK                   0x00000ff0L
+#define MH_DEBUG_REG46__ARB_WLAST_MASK                     0x00001000L
+#define MH_DEBUG_REG46__ARB_WLAST                          0x00001000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK                0x00002000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY                     0x00002000L
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK                0x0007c000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK                  0x00080000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q                       0x00080000L
+#define MH_DEBUG_REG46__WDB_WDC_WID_MASK                   0x00700000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK                 0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST                      0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK                 0xff000000L
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK            0xffffffffL
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK           0xffffffffL
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK                0x00000001L
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY                     0x00000001L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK               0x00000002L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY                    0x00000002L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK                0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY                     0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK                0x00000008L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE                     0x00000008L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK              0x00000010L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS                   0x00000010L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK             0x00000020L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q                  0x00000020L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK                 0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q                      0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK             0x00001f80L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK                 0x00002000L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q                      0x00002000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK                0x00004000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q                     0x00004000L
+#define MH_DEBUG_REG49__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG49__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG49__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG49__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG49__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG49__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG49__BVALID_q_MASK                      0x00040000L
+#define MH_DEBUG_REG49__BVALID_q                           0x00040000L
+#define MH_DEBUG_REG49__BREADY_q_MASK                      0x00080000L
+#define MH_DEBUG_REG49__BREADY_q                           0x00080000L
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG50__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG50__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG50__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG50__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK               0x00000008L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND                    0x00000008L
+#define MH_DEBUG_REG50__TLBMISS_VALID_MASK                 0x00000010L
+#define MH_DEBUG_REG50__TLBMISS_VALID                      0x00000010L
+#define MH_DEBUG_REG50__RDC_VALID_MASK                     0x00000020L
+#define MH_DEBUG_REG50__RDC_VALID                          0x00000020L
+#define MH_DEBUG_REG50__RDC_RID_MASK                       0x000001c0L
+#define MH_DEBUG_REG50__RDC_RLAST_MASK                     0x00000200L
+#define MH_DEBUG_REG50__RDC_RLAST                          0x00000200L
+#define MH_DEBUG_REG50__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK              0x00001000L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS                   0x00001000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK             0x00002000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q                  0x00002000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK              0x00004000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q                   0x00004000L
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK       0x001f8000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK               0x00200000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE                    0x00200000L
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK          0x0fc00000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK                   0x10000000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1                        0x10000000L
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0xe0000000L
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK             0xffffffffL
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK        0x00000003L
+#define MH_DEBUG_REG52__ARB_WE_MASK                        0x00000004L
+#define MH_DEBUG_REG52__ARB_WE                             0x00000004L
+#define MH_DEBUG_REG52__MMU_RTR_MASK                       0x00000008L
+#define MH_DEBUG_REG52__MMU_RTR                            0x00000008L
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK       0x03fffff0L
+#define MH_DEBUG_REG52__ARB_ID_q_MASK                      0x1c000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q_MASK                   0x20000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q                        0x20000000L
+#define MH_DEBUG_REG52__client_behavior_q_MASK             0xc0000000L
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid_MASK                  0x00000001L
+#define MH_DEBUG_REG53__stage1_valid                       0x00000001L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK             0x00000002L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q                  0x00000002L
+#define MH_DEBUG_REG53__pa_in_mpu_range_MASK               0x00000004L
+#define MH_DEBUG_REG53__pa_in_mpu_range                    0x00000004L
+#define MH_DEBUG_REG53__tag_match_q_MASK                   0x00000008L
+#define MH_DEBUG_REG53__tag_match_q                        0x00000008L
+#define MH_DEBUG_REG53__tag_miss_q_MASK                    0x00000010L
+#define MH_DEBUG_REG53__tag_miss_q                         0x00000010L
+#define MH_DEBUG_REG53__va_in_range_q_MASK                 0x00000020L
+#define MH_DEBUG_REG53__va_in_range_q                      0x00000020L
+#define MH_DEBUG_REG53__MMU_MISS_MASK                      0x00000040L
+#define MH_DEBUG_REG53__MMU_MISS                           0x00000040L
+#define MH_DEBUG_REG53__MMU_READ_MISS_MASK                 0x00000080L
+#define MH_DEBUG_REG53__MMU_READ_MISS                      0x00000080L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK                0x00000100L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS                     0x00000100L
+#define MH_DEBUG_REG53__MMU_HIT_MASK                       0x00000200L
+#define MH_DEBUG_REG53__MMU_HIT                            0x00000200L
+#define MH_DEBUG_REG53__MMU_READ_HIT_MASK                  0x00000400L
+#define MH_DEBUG_REG53__MMU_READ_HIT                       0x00000400L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK                 0x00000800L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT                      0x00000800L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK        0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS             0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK         0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT              0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK     0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS          0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK      0x00008000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT           0x00008000L
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK               0xffff0000L
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR_MASK                       0x00000001L
+#define MH_DEBUG_REG54__ARQ_RTR                            0x00000001L
+#define MH_DEBUG_REG54__MMU_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG54__MMU_WE                             0x00000002L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK             0x00000004L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q                  0x00000004L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK              0x00000008L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS                   0x00000008L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK               0x00000010L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND                    0x00000010L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH  0x00000020L
+#define MH_DEBUG_REG54__pa_in_mpu_range_MASK               0x00000040L
+#define MH_DEBUG_REG54__pa_in_mpu_range                    0x00000040L
+#define MH_DEBUG_REG54__stage1_valid_MASK                  0x00000080L
+#define MH_DEBUG_REG54__stage1_valid                       0x00000080L
+#define MH_DEBUG_REG54__stage2_valid_MASK                  0x00000100L
+#define MH_DEBUG_REG54__stage2_valid                       0x00000100L
+#define MH_DEBUG_REG54__client_behavior_q_MASK             0x00000600L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK             0x00000800L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q                  0x00000800L
+#define MH_DEBUG_REG54__tag_match_q_MASK                   0x00001000L
+#define MH_DEBUG_REG54__tag_match_q                        0x00001000L
+#define MH_DEBUG_REG54__tag_miss_q_MASK                    0x00002000L
+#define MH_DEBUG_REG54__tag_miss_q                         0x00002000L
+#define MH_DEBUG_REG54__va_in_range_q_MASK                 0x00004000L
+#define MH_DEBUG_REG54__va_in_range_q                      0x00004000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK          0x00008000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q               0x00008000L
+#define MH_DEBUG_REG54__TAG_valid_q_MASK                   0xffff0000L
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG55__TAG_valid_q_0_MASK                 0x00002000L
+#define MH_DEBUG_REG55__TAG_valid_q_0                      0x00002000L
+#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG55__TAG1_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG55__TAG_valid_q_1_MASK                 0x20000000L
+#define MH_DEBUG_REG55__TAG_valid_q_1                      0x20000000L
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG56__TAG_valid_q_2_MASK                 0x00002000L
+#define MH_DEBUG_REG56__TAG_valid_q_2                      0x00002000L
+#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG56__TAG3_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG56__TAG_valid_q_3_MASK                 0x20000000L
+#define MH_DEBUG_REG56__TAG_valid_q_3                      0x20000000L
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG57__TAG_valid_q_4_MASK                 0x00002000L
+#define MH_DEBUG_REG57__TAG_valid_q_4                      0x00002000L
+#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG57__TAG5_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG57__TAG_valid_q_5_MASK                 0x20000000L
+#define MH_DEBUG_REG57__TAG_valid_q_5                      0x20000000L
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG58__TAG_valid_q_6_MASK                 0x00002000L
+#define MH_DEBUG_REG58__TAG_valid_q_6                      0x00002000L
+#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG58__TAG7_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG58__TAG_valid_q_7_MASK                 0x20000000L
+#define MH_DEBUG_REG58__TAG_valid_q_7                      0x20000000L
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG59__TAG_valid_q_8_MASK                 0x00002000L
+#define MH_DEBUG_REG59__TAG_valid_q_8                      0x00002000L
+#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG59__TAG9_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG59__TAG_valid_q_9_MASK                 0x20000000L
+#define MH_DEBUG_REG59__TAG_valid_q_9                      0x20000000L
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG60__TAG_valid_q_10_MASK                0x00002000L
+#define MH_DEBUG_REG60__TAG_valid_q_10                     0x00002000L
+#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG60__TAG11_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG60__TAG_valid_q_11_MASK                0x20000000L
+#define MH_DEBUG_REG60__TAG_valid_q_11                     0x20000000L
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG61__TAG_valid_q_12_MASK                0x00002000L
+#define MH_DEBUG_REG61__TAG_valid_q_12                     0x00002000L
+#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG61__TAG13_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG61__TAG_valid_q_13_MASK                0x20000000L
+#define MH_DEBUG_REG61__TAG_valid_q_13                     0x20000000L
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG62__TAG_valid_q_14_MASK                0x00002000L
+#define MH_DEBUG_REG62__TAG_valid_q_14                     0x00002000L
+#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG62__TAG15_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG62__TAG_valid_q_15_MASK                0x20000000L
+#define MH_DEBUG_REG62__TAG_valid_q_15                     0x20000000L
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE_MASK                     0x00000001L
+#define MH_MMU_CONFIG__MMU_ENABLE                          0x00000001L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK              0x00000002L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE                   0x00000002L
+#define MH_MMU_CONFIG__RESERVED1_MASK                      0x0000000cL
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK             0x00000030L
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK             0x000000c0L
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK            0x00000300L
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK            0x00000c00L
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK            0x00003000L
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK            0x0000c000L
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK            0x00030000L
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK           0x000c0000L
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK           0x00300000L
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK             0x00c00000L
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK             0x03000000L
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK             0x00000fffL
+#define MH_MMU_VA_RANGE__VA_BASE_MASK                      0xfffff000L
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE_MASK                       0xfffff000L
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK                 0x00000001L
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT                      0x00000001L
+#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK                    0x00000002L
+#define MH_MMU_PAGE_FAULT__OP_TYPE                         0x00000002L
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK              0x0000000cL
+#define MH_MMU_PAGE_FAULT__AXI_ID_MASK                     0x00000070L
+#define MH_MMU_PAGE_FAULT__RESERVED1_MASK                  0x00000080L
+#define MH_MMU_PAGE_FAULT__RESERVED1                       0x00000080L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK   0x00000100L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE        0x00000100L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK       0x00000200L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE            0x00000200L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK      0x00000400L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR           0x00000400L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK     0x00000800L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR          0x00000800L
+#define MH_MMU_PAGE_FAULT__REQ_VA_MASK                     0xfffff000L
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK                 0xffffffe0L
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK             0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL                  0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK              0x00000002L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC                   0x00000002L
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE_MASK                     0xfffff000L
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END_MASK                       0xfffff000L
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK                     0x00000002L
+#define WAIT_UNTIL__WAIT_RE_VSYNC                          0x00000002L
+#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK                     0x00000004L
+#define WAIT_UNTIL__WAIT_FE_VSYNC                          0x00000004L
+#define WAIT_UNTIL__WAIT_VSYNC_MASK                        0x00000008L
+#define WAIT_UNTIL__WAIT_VSYNC                             0x00000008L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK                    0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0                         0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK                    0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1                         0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK                    0x00000040L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2                         0x00000040L
+#define WAIT_UNTIL__WAIT_CMDFIFO_MASK                      0x00000400L
+#define WAIT_UNTIL__WAIT_CMDFIFO                           0x00000400L
+#define WAIT_UNTIL__WAIT_2D_IDLE_MASK                      0x00004000L
+#define WAIT_UNTIL__WAIT_2D_IDLE                           0x00004000L
+#define WAIT_UNTIL__WAIT_3D_IDLE_MASK                      0x00008000L
+#define WAIT_UNTIL__WAIT_3D_IDLE                           0x00008000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK                 0x00010000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN                      0x00010000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK                 0x00020000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN                      0x00020000L
+#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK                   0x00f00000L
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK           0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI                0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK      0x00000020L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI           0x00000020L
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL_MASK                    0x0000001fL
+#define RBBM_STATUS__TC_BUSY_MASK                          0x00000020L
+#define RBBM_STATUS__TC_BUSY                               0x00000020L
+#define RBBM_STATUS__HIRQ_PENDING_MASK                     0x00000100L
+#define RBBM_STATUS__HIRQ_PENDING                          0x00000100L
+#define RBBM_STATUS__CPRQ_PENDING_MASK                     0x00000200L
+#define RBBM_STATUS__CPRQ_PENDING                          0x00000200L
+#define RBBM_STATUS__CFRQ_PENDING_MASK                     0x00000400L
+#define RBBM_STATUS__CFRQ_PENDING                          0x00000400L
+#define RBBM_STATUS__PFRQ_PENDING_MASK                     0x00000800L
+#define RBBM_STATUS__PFRQ_PENDING                          0x00000800L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK                  0x00001000L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA                       0x00001000L
+#define RBBM_STATUS__RBBM_WU_BUSY_MASK                     0x00004000L
+#define RBBM_STATUS__RBBM_WU_BUSY                          0x00004000L
+#define RBBM_STATUS__CP_NRT_BUSY_MASK                      0x00010000L
+#define RBBM_STATUS__CP_NRT_BUSY                           0x00010000L
+#define RBBM_STATUS__MH_BUSY_MASK                          0x00040000L
+#define RBBM_STATUS__MH_BUSY                               0x00040000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK                0x00080000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY                     0x00080000L
+#define RBBM_STATUS__SX_BUSY_MASK                          0x00200000L
+#define RBBM_STATUS__SX_BUSY                               0x00200000L
+#define RBBM_STATUS__TPC_BUSY_MASK                         0x00400000L
+#define RBBM_STATUS__TPC_BUSY                              0x00400000L
+#define RBBM_STATUS__SC_CNTX_BUSY_MASK                     0x01000000L
+#define RBBM_STATUS__SC_CNTX_BUSY                          0x01000000L
+#define RBBM_STATUS__PA_BUSY_MASK                          0x02000000L
+#define RBBM_STATUS__PA_BUSY                               0x02000000L
+#define RBBM_STATUS__VGT_BUSY_MASK                         0x04000000L
+#define RBBM_STATUS__VGT_BUSY                              0x04000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK                   0x08000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY                        0x08000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK                    0x10000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY                         0x10000000L
+#define RBBM_STATUS__RB_CNTX_BUSY_MASK                     0x40000000L
+#define RBBM_STATUS__RB_CNTX_BUSY                          0x40000000L
+#define RBBM_STATUS__GUI_ACTIVE_MASK                       0x80000000L
+#define RBBM_STATUS__GUI_ACTIVE                            0x80000000L
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK             0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0                  0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK             0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1                  0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK             0x00000004L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2                  0x00000004L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK               0x00000008L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID                    0x00000008L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK                0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0                     0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK                0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1                     0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK                0x00000040L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2                     0x00000040L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK                   0x00000080L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL                        0x00000080L
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK                  0x00000300L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK                0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0                     0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK                0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1                     0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK                0x00001000L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2                     0x00001000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK                   0x00002000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL                        0x00002000L
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK                  0x0000c000L
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK                0x00030000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK                0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0                     0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK                0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1                     0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK                0x00400000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2                     0x00400000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK                   0x00800000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL                        0x00800000L
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK                  0x03000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK                0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0                     0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK                0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1                     0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK                0x10000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2                     0x10000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK                   0x20000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL                        0x20000000L
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK                  0xc0000000L
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK         0x00000003L
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK         0x00000300L
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK         0x00030000L
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK         0x03000000L
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST_MASK                  0xffffffffL
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK            0x0000ffffL
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK           0x00ff0000L
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK               0xff000000L
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK               0xffffffffL
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0_MASK                   0x000000ffL
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1_MASK                   0x0000000fL
+#define RBBM_PERIPHID1__DESIGNER0_MASK                     0x000000f0L
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1_MASK                     0x0000000fL
+#define RBBM_PERIPHID2__REVISION_MASK                      0x000000f0L
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK           0x00000003L
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK          0x0000000cL
+#define RBBM_PERIPHID3__MH_INTERFACE_MASK                  0x00000030L
+#define RBBM_PERIPHID3__CONTINUATION_MASK                  0x00000080L
+#define RBBM_PERIPHID3__CONTINUATION                       0x00000080L
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT_MASK                       0x000000ffL
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK               0x0001ff00L
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK            0x0000001fL
+#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK                    0x000003e0L
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK                0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_CP                     0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK                0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA                     0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK                0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH                     0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK                0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC                     0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK                0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ                     0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK                0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX                     0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK               0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB                    0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK                0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC                     0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK               0x00010000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT                    0x00010000L
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK    0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE         0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK        0x00000004L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE             0x00000004L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK    0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE         0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK     0x00000010L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE          0x00000010L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK    0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE         0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK     0x00000100L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE          0x00000100L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK        0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE             0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK   0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE        0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK   0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE        0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK   0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE        0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK   0x00004000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE        0x00004000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK   0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE        0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK   0x00010000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE        0x00010000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK   0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE        0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK   0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE        0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK     0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE          0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK    0x00200000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE         0x00200000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK      0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE           0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK    0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE         0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK  0x01000000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE       0x01000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK       0x02000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE            0x02000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK    0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE         0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK        0x08000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE             0x08000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK     0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE          0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK    0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE         0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK    0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE         0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK  0x80000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000L
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK     0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE          0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK     0x00000004L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE          0x00000004L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK   0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE        0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE      0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK   0x00000020L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE        0x00000020L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE     0x00000040L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK      0x00000080L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE           0x00000080L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK    0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE         0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK    0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE         0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK    0x00000800L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE         0x00000800L
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK                0x0000ffffL
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK             0x003f0000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK               0x01000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP                    0x01000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK                  0x02000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI                       0x02000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK      0x20000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE           0x20000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK         0x40000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE              0x40000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK             0x80000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE                  0x80000000L
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK                   0x00000001L
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE                        0x00000001L
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK                 0xffffffffL
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK               0x0000003fL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK                0x00000f00L
+#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK                    0x00001000L
+#define RBBM_DEBUG_CNTL__SW_ENABLE                         0x00001000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK          0x003f0000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK           0x0f000000L
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK           0xf0000000L
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR_MASK                        0x00000002L
+#define RBBM_DEBUG__IGNORE_RTR                             0x00000002L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK                0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU                     0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK             0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC                  0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK             0x00000010L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI                  0x00000010L
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK         0x00000f00L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK                 0x00010000L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI                      0x00010000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK      0x00020000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI           0x00020000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK     0x00040000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI          0x00040000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK      0x00080000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI           0x00080000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK                    0x00100000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR                         0x00100000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK                   0x00200000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR                        0x00200000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK                    0x00400000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR                         0x00400000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK        0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI             0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK               0x01000000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR                    0x01000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK               0x80000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY                    0x80000000L
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS_MASK                 0x0001fffcL
+#define RBBM_READ_ERROR__READ_REQUESTER_MASK               0x40000000L
+#define RBBM_READ_ERROR__READ_REQUESTER                    0x40000000L
+#define RBBM_READ_ERROR__READ_ERROR_MASK                   0x80000000L
+#define RBBM_READ_ERROR__READ_ERROR                        0x80000000L
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK   0x000000ffL
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK                 0x00000001L
+#define RBBM_INT_CNTL__RDERR_INT_MASK                      0x00000001L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK        0x00000002L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK             0x00000002L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK              0x00080000L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK                   0x00080000L
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK               0x00000001L
+#define RBBM_INT_STATUS__RDERR_INT_STAT                    0x00000001L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK      0x00000002L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT           0x00000002L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK            0x00080000L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT                 0x00080000L
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK_MASK                   0x00000001L
+#define RBBM_INT_ACK__RDERR_INT_ACK                        0x00000001L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK          0x00000002L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK               0x00000002L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK                0x00080000L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK                     0x00080000L
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK                0x00000020L
+#define MASTER_INT_SIGNAL__MH_INT_STAT                     0x00000020L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK                0x04000000L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT                     0x04000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK                0x40000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT                     0x40000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK              0x80000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT                   0x80000000L
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK     0x0000003fL
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK          0xffffffffL
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK          0x0000ffffL
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE_MASK                           0xffffffe0L
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ_MASK                          0x0000003fL
+#define CP_RB_CNTL__RB_BLKSZ_MASK                          0x00003f00L
+#define CP_RB_CNTL__BUF_SWAP_MASK                          0x00030000L
+#define CP_RB_CNTL__RB_POLL_EN_MASK                        0x00100000L
+#define CP_RB_CNTL__RB_POLL_EN                             0x00100000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK                      0x08000000L
+#define CP_RB_CNTL__RB_NO_UPDATE                           0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                    0x80000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA                         0x80000000L
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                 0xfffffffcL
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR_MASK                           0x000fffffL
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                     0x000fffffL
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR_MASK                           0x000fffffL
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK             0x0fffffffL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK             0xf0000000L
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK                 0xfffffffcL
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE_MASK                         0xfffffffcL
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                       0x000fffffL
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE_MASK                         0xfffffffcL
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                       0x000fffffL
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE_MASK                           0xfffffffcL
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK                         0x000fffffL
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK            0x0000000fL
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK            0x00000f00L
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK             0x000f0000L
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END_MASK                    0x001f0000L
+#define CP_MEQ_THRESHOLDS__ROQ_END_MASK                    0x1f000000L
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK                    0x0000007fL
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK                     0x00007f00L
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK                     0x007f0000L
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST_MASK                      0x0000007fL
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK                         0x0000001fL
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK              0x0000007fL
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK              0x007f0000L
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK           0x0000007fL
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK           0x007f0000L
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK           0x0000007fL
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK           0x007f0000L
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK            0x00000007L
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK            0x00000700L
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK                   0x0000007fL
+#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK                   0x007f0000L
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR_MASK                         0x000003ffL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK                         0x03ff0000L
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK                   0x00000001L
+#define CP_MIU_TAG_STAT__TAG_0_STAT                        0x00000001L
+#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK                   0x00000002L
+#define CP_MIU_TAG_STAT__TAG_1_STAT                        0x00000002L
+#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK                   0x00000004L
+#define CP_MIU_TAG_STAT__TAG_2_STAT                        0x00000004L
+#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK                   0x00000008L
+#define CP_MIU_TAG_STAT__TAG_3_STAT                        0x00000008L
+#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK                   0x00000010L
+#define CP_MIU_TAG_STAT__TAG_4_STAT                        0x00000010L
+#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK                   0x00000020L
+#define CP_MIU_TAG_STAT__TAG_5_STAT                        0x00000020L
+#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK                   0x00000040L
+#define CP_MIU_TAG_STAT__TAG_6_STAT                        0x00000040L
+#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK                   0x00000080L
+#define CP_MIU_TAG_STAT__TAG_7_STAT                        0x00000080L
+#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK                   0x00000100L
+#define CP_MIU_TAG_STAT__TAG_8_STAT                        0x00000100L
+#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK                   0x00000200L
+#define CP_MIU_TAG_STAT__TAG_9_STAT                        0x00000200L
+#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK                  0x00000400L
+#define CP_MIU_TAG_STAT__TAG_10_STAT                       0x00000400L
+#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK                  0x00000800L
+#define CP_MIU_TAG_STAT__TAG_11_STAT                       0x00000800L
+#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK                  0x00001000L
+#define CP_MIU_TAG_STAT__TAG_12_STAT                       0x00001000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK                  0x00002000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT                       0x00002000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK                  0x00004000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT                       0x00004000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK                  0x00008000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT                       0x00008000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK                  0x00010000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT                       0x00010000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK                  0x00020000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT                       0x00020000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK           0x80000000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG                0x80000000L
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX_MASK                       0x0000007fL
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                   0x00030000L
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA_MASK                         0xffffffffL
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX_MASK                        0x0000ffffL
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK            0x02000000L
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY                 0x02000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK            0x04000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY                 0x04000000L
+#define CP_ME_CNTL__ME_HALT_MASK                           0x10000000L
+#define CP_ME_CNTL__ME_HALT                                0x10000000L
+#define CP_ME_CNTL__ME_BUSY_MASK                           0x20000000L
+#define CP_ME_CNTL__ME_BUSY                                0x20000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE_MASK                     0x80000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE                          0x80000000L
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA_MASK                   0xffffffffL
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                   0xffffffffL
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR_MASK                       0xffffffffL
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK             0x007fffffL
+#define CP_DEBUG__PREDICATE_DISABLE_MASK                   0x00800000L
+#define CP_DEBUG__PREDICATE_DISABLE                        0x00800000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK                 0x01000000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE                      0x01000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK             0x02000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE                  0x02000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK                  0x04000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS                       0x04000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK                 0x08000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE                      0x08000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK              0x10000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE                   0x10000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK              0x40000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL                   0x40000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK              0x80000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE                   0x80000000L
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK                0xffffffffL
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK                0xffffffffL
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK                0xffffffffL
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK                0xffffffffL
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK                0xffffffffL
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK                0xffffffffL
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK                0xffffffffL
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK                0xffffffffL
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK_MASK                    0x000000ffL
+#define SCRATCH_UMSK__SCRATCH_SWAP_MASK                    0x00030000L
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR_MASK                    0xffffffe0L
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM                    0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR                   0x00000002L
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM                    0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR                   0x00000002L
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK               0x00000001L
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC                    0x00000001L
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK                0x00000003L
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK                0xfffffffcL
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK                0xffffffffL
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK   0x00000001L
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR        0x00000001L
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK  0x00000003L
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK  0xfffffffcL
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK  0xffffffffL
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK_MASK                      0x00080000L
+#define CP_INT_CNTL__SW_INT_MASK                           0x00080000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK             0x00800000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK                  0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK                0x01000000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK                     0x01000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK        0x02000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK             0x02000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK          0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK               0x04000000L
+#define CP_INT_CNTL__IB_ERROR_MASK_MASK                    0x08000000L
+#define CP_INT_CNTL__IB_ERROR_MASK                         0x08000000L
+#define CP_INT_CNTL__IB2_INT_MASK_MASK                     0x20000000L
+#define CP_INT_CNTL__IB2_INT_MASK                          0x20000000L
+#define CP_INT_CNTL__IB1_INT_MASK_MASK                     0x40000000L
+#define CP_INT_CNTL__IB1_INT_MASK                          0x40000000L
+#define CP_INT_CNTL__RB_INT_MASK_MASK                      0x80000000L
+#define CP_INT_CNTL__RB_INT_MASK                           0x80000000L
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT_MASK                    0x00080000L
+#define CP_INT_STATUS__SW_INT_STAT                         0x00080000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK           0x00800000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT                0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK              0x01000000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT                   0x01000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK      0x02000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT           0x02000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK        0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT             0x04000000L
+#define CP_INT_STATUS__IB_ERROR_STAT_MASK                  0x08000000L
+#define CP_INT_STATUS__IB_ERROR_STAT                       0x08000000L
+#define CP_INT_STATUS__IB2_INT_STAT_MASK                   0x20000000L
+#define CP_INT_STATUS__IB2_INT_STAT                        0x20000000L
+#define CP_INT_STATUS__IB1_INT_STAT_MASK                   0x40000000L
+#define CP_INT_STATUS__IB1_INT_STAT                        0x40000000L
+#define CP_INT_STATUS__RB_INT_STAT_MASK                    0x80000000L
+#define CP_INT_STATUS__RB_INT_STAT                         0x80000000L
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK_MASK                        0x00080000L
+#define CP_INT_ACK__SW_INT_ACK                             0x00080000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK               0x00800000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK                    0x00800000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK                  0x01000000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK                       0x01000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK          0x02000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK               0x02000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK            0x04000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK                 0x04000000L
+#define CP_INT_ACK__IB_ERROR_ACK_MASK                      0x08000000L
+#define CP_INT_ACK__IB_ERROR_ACK                           0x08000000L
+#define CP_INT_ACK__IB2_INT_ACK_MASK                       0x20000000L
+#define CP_INT_ACK__IB2_INT_ACK                            0x20000000L
+#define CP_INT_ACK__IB1_INT_ACK_MASK                       0x40000000L
+#define CP_INT_ACK__IB1_INT_ACK                            0x40000000L
+#define CP_INT_ACK__RB_INT_ACK_MASK                        0x80000000L
+#define CP_INT_ACK__RB_INT_ACK                             0x80000000L
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                 0x000001ffL
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                 0x00ffffffL
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                0x0000000fL
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK          0x00000300L
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK          0x0000003fL
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK               0xffffffffL
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK               0x0000ffffL
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK                   0xffffffffL
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK                   0xffffffffL
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK               0xffffffffL
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK               0xffffffffL
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0_MASK                      0x00000001L
+#define CP_NV_FLAGS_0__DISCARD_0                           0x00000001L
+#define CP_NV_FLAGS_0__END_RCVD_0_MASK                     0x00000002L
+#define CP_NV_FLAGS_0__END_RCVD_0                          0x00000002L
+#define CP_NV_FLAGS_0__DISCARD_1_MASK                      0x00000004L
+#define CP_NV_FLAGS_0__DISCARD_1                           0x00000004L
+#define CP_NV_FLAGS_0__END_RCVD_1_MASK                     0x00000008L
+#define CP_NV_FLAGS_0__END_RCVD_1                          0x00000008L
+#define CP_NV_FLAGS_0__DISCARD_2_MASK                      0x00000010L
+#define CP_NV_FLAGS_0__DISCARD_2                           0x00000010L
+#define CP_NV_FLAGS_0__END_RCVD_2_MASK                     0x00000020L
+#define CP_NV_FLAGS_0__END_RCVD_2                          0x00000020L
+#define CP_NV_FLAGS_0__DISCARD_3_MASK                      0x00000040L
+#define CP_NV_FLAGS_0__DISCARD_3                           0x00000040L
+#define CP_NV_FLAGS_0__END_RCVD_3_MASK                     0x00000080L
+#define CP_NV_FLAGS_0__END_RCVD_3                          0x00000080L
+#define CP_NV_FLAGS_0__DISCARD_4_MASK                      0x00000100L
+#define CP_NV_FLAGS_0__DISCARD_4                           0x00000100L
+#define CP_NV_FLAGS_0__END_RCVD_4_MASK                     0x00000200L
+#define CP_NV_FLAGS_0__END_RCVD_4                          0x00000200L
+#define CP_NV_FLAGS_0__DISCARD_5_MASK                      0x00000400L
+#define CP_NV_FLAGS_0__DISCARD_5                           0x00000400L
+#define CP_NV_FLAGS_0__END_RCVD_5_MASK                     0x00000800L
+#define CP_NV_FLAGS_0__END_RCVD_5                          0x00000800L
+#define CP_NV_FLAGS_0__DISCARD_6_MASK                      0x00001000L
+#define CP_NV_FLAGS_0__DISCARD_6                           0x00001000L
+#define CP_NV_FLAGS_0__END_RCVD_6_MASK                     0x00002000L
+#define CP_NV_FLAGS_0__END_RCVD_6                          0x00002000L
+#define CP_NV_FLAGS_0__DISCARD_7_MASK                      0x00004000L
+#define CP_NV_FLAGS_0__DISCARD_7                           0x00004000L
+#define CP_NV_FLAGS_0__END_RCVD_7_MASK                     0x00008000L
+#define CP_NV_FLAGS_0__END_RCVD_7                          0x00008000L
+#define CP_NV_FLAGS_0__DISCARD_8_MASK                      0x00010000L
+#define CP_NV_FLAGS_0__DISCARD_8                           0x00010000L
+#define CP_NV_FLAGS_0__END_RCVD_8_MASK                     0x00020000L
+#define CP_NV_FLAGS_0__END_RCVD_8                          0x00020000L
+#define CP_NV_FLAGS_0__DISCARD_9_MASK                      0x00040000L
+#define CP_NV_FLAGS_0__DISCARD_9                           0x00040000L
+#define CP_NV_FLAGS_0__END_RCVD_9_MASK                     0x00080000L
+#define CP_NV_FLAGS_0__END_RCVD_9                          0x00080000L
+#define CP_NV_FLAGS_0__DISCARD_10_MASK                     0x00100000L
+#define CP_NV_FLAGS_0__DISCARD_10                          0x00100000L
+#define CP_NV_FLAGS_0__END_RCVD_10_MASK                    0x00200000L
+#define CP_NV_FLAGS_0__END_RCVD_10                         0x00200000L
+#define CP_NV_FLAGS_0__DISCARD_11_MASK                     0x00400000L
+#define CP_NV_FLAGS_0__DISCARD_11                          0x00400000L
+#define CP_NV_FLAGS_0__END_RCVD_11_MASK                    0x00800000L
+#define CP_NV_FLAGS_0__END_RCVD_11                         0x00800000L
+#define CP_NV_FLAGS_0__DISCARD_12_MASK                     0x01000000L
+#define CP_NV_FLAGS_0__DISCARD_12                          0x01000000L
+#define CP_NV_FLAGS_0__END_RCVD_12_MASK                    0x02000000L
+#define CP_NV_FLAGS_0__END_RCVD_12                         0x02000000L
+#define CP_NV_FLAGS_0__DISCARD_13_MASK                     0x04000000L
+#define CP_NV_FLAGS_0__DISCARD_13                          0x04000000L
+#define CP_NV_FLAGS_0__END_RCVD_13_MASK                    0x08000000L
+#define CP_NV_FLAGS_0__END_RCVD_13                         0x08000000L
+#define CP_NV_FLAGS_0__DISCARD_14_MASK                     0x10000000L
+#define CP_NV_FLAGS_0__DISCARD_14                          0x10000000L
+#define CP_NV_FLAGS_0__END_RCVD_14_MASK                    0x20000000L
+#define CP_NV_FLAGS_0__END_RCVD_14                         0x20000000L
+#define CP_NV_FLAGS_0__DISCARD_15_MASK                     0x40000000L
+#define CP_NV_FLAGS_0__DISCARD_15                          0x40000000L
+#define CP_NV_FLAGS_0__END_RCVD_15_MASK                    0x80000000L
+#define CP_NV_FLAGS_0__END_RCVD_15                         0x80000000L
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16_MASK                     0x00000001L
+#define CP_NV_FLAGS_1__DISCARD_16                          0x00000001L
+#define CP_NV_FLAGS_1__END_RCVD_16_MASK                    0x00000002L
+#define CP_NV_FLAGS_1__END_RCVD_16                         0x00000002L
+#define CP_NV_FLAGS_1__DISCARD_17_MASK                     0x00000004L
+#define CP_NV_FLAGS_1__DISCARD_17                          0x00000004L
+#define CP_NV_FLAGS_1__END_RCVD_17_MASK                    0x00000008L
+#define CP_NV_FLAGS_1__END_RCVD_17                         0x00000008L
+#define CP_NV_FLAGS_1__DISCARD_18_MASK                     0x00000010L
+#define CP_NV_FLAGS_1__DISCARD_18                          0x00000010L
+#define CP_NV_FLAGS_1__END_RCVD_18_MASK                    0x00000020L
+#define CP_NV_FLAGS_1__END_RCVD_18                         0x00000020L
+#define CP_NV_FLAGS_1__DISCARD_19_MASK                     0x00000040L
+#define CP_NV_FLAGS_1__DISCARD_19                          0x00000040L
+#define CP_NV_FLAGS_1__END_RCVD_19_MASK                    0x00000080L
+#define CP_NV_FLAGS_1__END_RCVD_19                         0x00000080L
+#define CP_NV_FLAGS_1__DISCARD_20_MASK                     0x00000100L
+#define CP_NV_FLAGS_1__DISCARD_20                          0x00000100L
+#define CP_NV_FLAGS_1__END_RCVD_20_MASK                    0x00000200L
+#define CP_NV_FLAGS_1__END_RCVD_20                         0x00000200L
+#define CP_NV_FLAGS_1__DISCARD_21_MASK                     0x00000400L
+#define CP_NV_FLAGS_1__DISCARD_21                          0x00000400L
+#define CP_NV_FLAGS_1__END_RCVD_21_MASK                    0x00000800L
+#define CP_NV_FLAGS_1__END_RCVD_21                         0x00000800L
+#define CP_NV_FLAGS_1__DISCARD_22_MASK                     0x00001000L
+#define CP_NV_FLAGS_1__DISCARD_22                          0x00001000L
+#define CP_NV_FLAGS_1__END_RCVD_22_MASK                    0x00002000L
+#define CP_NV_FLAGS_1__END_RCVD_22                         0x00002000L
+#define CP_NV_FLAGS_1__DISCARD_23_MASK                     0x00004000L
+#define CP_NV_FLAGS_1__DISCARD_23                          0x00004000L
+#define CP_NV_FLAGS_1__END_RCVD_23_MASK                    0x00008000L
+#define CP_NV_FLAGS_1__END_RCVD_23                         0x00008000L
+#define CP_NV_FLAGS_1__DISCARD_24_MASK                     0x00010000L
+#define CP_NV_FLAGS_1__DISCARD_24                          0x00010000L
+#define CP_NV_FLAGS_1__END_RCVD_24_MASK                    0x00020000L
+#define CP_NV_FLAGS_1__END_RCVD_24                         0x00020000L
+#define CP_NV_FLAGS_1__DISCARD_25_MASK                     0x00040000L
+#define CP_NV_FLAGS_1__DISCARD_25                          0x00040000L
+#define CP_NV_FLAGS_1__END_RCVD_25_MASK                    0x00080000L
+#define CP_NV_FLAGS_1__END_RCVD_25                         0x00080000L
+#define CP_NV_FLAGS_1__DISCARD_26_MASK                     0x00100000L
+#define CP_NV_FLAGS_1__DISCARD_26                          0x00100000L
+#define CP_NV_FLAGS_1__END_RCVD_26_MASK                    0x00200000L
+#define CP_NV_FLAGS_1__END_RCVD_26                         0x00200000L
+#define CP_NV_FLAGS_1__DISCARD_27_MASK                     0x00400000L
+#define CP_NV_FLAGS_1__DISCARD_27                          0x00400000L
+#define CP_NV_FLAGS_1__END_RCVD_27_MASK                    0x00800000L
+#define CP_NV_FLAGS_1__END_RCVD_27                         0x00800000L
+#define CP_NV_FLAGS_1__DISCARD_28_MASK                     0x01000000L
+#define CP_NV_FLAGS_1__DISCARD_28                          0x01000000L
+#define CP_NV_FLAGS_1__END_RCVD_28_MASK                    0x02000000L
+#define CP_NV_FLAGS_1__END_RCVD_28                         0x02000000L
+#define CP_NV_FLAGS_1__DISCARD_29_MASK                     0x04000000L
+#define CP_NV_FLAGS_1__DISCARD_29                          0x04000000L
+#define CP_NV_FLAGS_1__END_RCVD_29_MASK                    0x08000000L
+#define CP_NV_FLAGS_1__END_RCVD_29                         0x08000000L
+#define CP_NV_FLAGS_1__DISCARD_30_MASK                     0x10000000L
+#define CP_NV_FLAGS_1__DISCARD_30                          0x10000000L
+#define CP_NV_FLAGS_1__END_RCVD_30_MASK                    0x20000000L
+#define CP_NV_FLAGS_1__END_RCVD_30                         0x20000000L
+#define CP_NV_FLAGS_1__DISCARD_31_MASK                     0x40000000L
+#define CP_NV_FLAGS_1__DISCARD_31                          0x40000000L
+#define CP_NV_FLAGS_1__END_RCVD_31_MASK                    0x80000000L
+#define CP_NV_FLAGS_1__END_RCVD_31                         0x80000000L
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32_MASK                     0x00000001L
+#define CP_NV_FLAGS_2__DISCARD_32                          0x00000001L
+#define CP_NV_FLAGS_2__END_RCVD_32_MASK                    0x00000002L
+#define CP_NV_FLAGS_2__END_RCVD_32                         0x00000002L
+#define CP_NV_FLAGS_2__DISCARD_33_MASK                     0x00000004L
+#define CP_NV_FLAGS_2__DISCARD_33                          0x00000004L
+#define CP_NV_FLAGS_2__END_RCVD_33_MASK                    0x00000008L
+#define CP_NV_FLAGS_2__END_RCVD_33                         0x00000008L
+#define CP_NV_FLAGS_2__DISCARD_34_MASK                     0x00000010L
+#define CP_NV_FLAGS_2__DISCARD_34                          0x00000010L
+#define CP_NV_FLAGS_2__END_RCVD_34_MASK                    0x00000020L
+#define CP_NV_FLAGS_2__END_RCVD_34                         0x00000020L
+#define CP_NV_FLAGS_2__DISCARD_35_MASK                     0x00000040L
+#define CP_NV_FLAGS_2__DISCARD_35                          0x00000040L
+#define CP_NV_FLAGS_2__END_RCVD_35_MASK                    0x00000080L
+#define CP_NV_FLAGS_2__END_RCVD_35                         0x00000080L
+#define CP_NV_FLAGS_2__DISCARD_36_MASK                     0x00000100L
+#define CP_NV_FLAGS_2__DISCARD_36                          0x00000100L
+#define CP_NV_FLAGS_2__END_RCVD_36_MASK                    0x00000200L
+#define CP_NV_FLAGS_2__END_RCVD_36                         0x00000200L
+#define CP_NV_FLAGS_2__DISCARD_37_MASK                     0x00000400L
+#define CP_NV_FLAGS_2__DISCARD_37                          0x00000400L
+#define CP_NV_FLAGS_2__END_RCVD_37_MASK                    0x00000800L
+#define CP_NV_FLAGS_2__END_RCVD_37                         0x00000800L
+#define CP_NV_FLAGS_2__DISCARD_38_MASK                     0x00001000L
+#define CP_NV_FLAGS_2__DISCARD_38                          0x00001000L
+#define CP_NV_FLAGS_2__END_RCVD_38_MASK                    0x00002000L
+#define CP_NV_FLAGS_2__END_RCVD_38                         0x00002000L
+#define CP_NV_FLAGS_2__DISCARD_39_MASK                     0x00004000L
+#define CP_NV_FLAGS_2__DISCARD_39                          0x00004000L
+#define CP_NV_FLAGS_2__END_RCVD_39_MASK                    0x00008000L
+#define CP_NV_FLAGS_2__END_RCVD_39                         0x00008000L
+#define CP_NV_FLAGS_2__DISCARD_40_MASK                     0x00010000L
+#define CP_NV_FLAGS_2__DISCARD_40                          0x00010000L
+#define CP_NV_FLAGS_2__END_RCVD_40_MASK                    0x00020000L
+#define CP_NV_FLAGS_2__END_RCVD_40                         0x00020000L
+#define CP_NV_FLAGS_2__DISCARD_41_MASK                     0x00040000L
+#define CP_NV_FLAGS_2__DISCARD_41                          0x00040000L
+#define CP_NV_FLAGS_2__END_RCVD_41_MASK                    0x00080000L
+#define CP_NV_FLAGS_2__END_RCVD_41                         0x00080000L
+#define CP_NV_FLAGS_2__DISCARD_42_MASK                     0x00100000L
+#define CP_NV_FLAGS_2__DISCARD_42                          0x00100000L
+#define CP_NV_FLAGS_2__END_RCVD_42_MASK                    0x00200000L
+#define CP_NV_FLAGS_2__END_RCVD_42                         0x00200000L
+#define CP_NV_FLAGS_2__DISCARD_43_MASK                     0x00400000L
+#define CP_NV_FLAGS_2__DISCARD_43                          0x00400000L
+#define CP_NV_FLAGS_2__END_RCVD_43_MASK                    0x00800000L
+#define CP_NV_FLAGS_2__END_RCVD_43                         0x00800000L
+#define CP_NV_FLAGS_2__DISCARD_44_MASK                     0x01000000L
+#define CP_NV_FLAGS_2__DISCARD_44                          0x01000000L
+#define CP_NV_FLAGS_2__END_RCVD_44_MASK                    0x02000000L
+#define CP_NV_FLAGS_2__END_RCVD_44                         0x02000000L
+#define CP_NV_FLAGS_2__DISCARD_45_MASK                     0x04000000L
+#define CP_NV_FLAGS_2__DISCARD_45                          0x04000000L
+#define CP_NV_FLAGS_2__END_RCVD_45_MASK                    0x08000000L
+#define CP_NV_FLAGS_2__END_RCVD_45                         0x08000000L
+#define CP_NV_FLAGS_2__DISCARD_46_MASK                     0x10000000L
+#define CP_NV_FLAGS_2__DISCARD_46                          0x10000000L
+#define CP_NV_FLAGS_2__END_RCVD_46_MASK                    0x20000000L
+#define CP_NV_FLAGS_2__END_RCVD_46                         0x20000000L
+#define CP_NV_FLAGS_2__DISCARD_47_MASK                     0x40000000L
+#define CP_NV_FLAGS_2__DISCARD_47                          0x40000000L
+#define CP_NV_FLAGS_2__END_RCVD_47_MASK                    0x80000000L
+#define CP_NV_FLAGS_2__END_RCVD_47                         0x80000000L
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48_MASK                     0x00000001L
+#define CP_NV_FLAGS_3__DISCARD_48                          0x00000001L
+#define CP_NV_FLAGS_3__END_RCVD_48_MASK                    0x00000002L
+#define CP_NV_FLAGS_3__END_RCVD_48                         0x00000002L
+#define CP_NV_FLAGS_3__DISCARD_49_MASK                     0x00000004L
+#define CP_NV_FLAGS_3__DISCARD_49                          0x00000004L
+#define CP_NV_FLAGS_3__END_RCVD_49_MASK                    0x00000008L
+#define CP_NV_FLAGS_3__END_RCVD_49                         0x00000008L
+#define CP_NV_FLAGS_3__DISCARD_50_MASK                     0x00000010L
+#define CP_NV_FLAGS_3__DISCARD_50                          0x00000010L
+#define CP_NV_FLAGS_3__END_RCVD_50_MASK                    0x00000020L
+#define CP_NV_FLAGS_3__END_RCVD_50                         0x00000020L
+#define CP_NV_FLAGS_3__DISCARD_51_MASK                     0x00000040L
+#define CP_NV_FLAGS_3__DISCARD_51                          0x00000040L
+#define CP_NV_FLAGS_3__END_RCVD_51_MASK                    0x00000080L
+#define CP_NV_FLAGS_3__END_RCVD_51                         0x00000080L
+#define CP_NV_FLAGS_3__DISCARD_52_MASK                     0x00000100L
+#define CP_NV_FLAGS_3__DISCARD_52                          0x00000100L
+#define CP_NV_FLAGS_3__END_RCVD_52_MASK                    0x00000200L
+#define CP_NV_FLAGS_3__END_RCVD_52                         0x00000200L
+#define CP_NV_FLAGS_3__DISCARD_53_MASK                     0x00000400L
+#define CP_NV_FLAGS_3__DISCARD_53                          0x00000400L
+#define CP_NV_FLAGS_3__END_RCVD_53_MASK                    0x00000800L
+#define CP_NV_FLAGS_3__END_RCVD_53                         0x00000800L
+#define CP_NV_FLAGS_3__DISCARD_54_MASK                     0x00001000L
+#define CP_NV_FLAGS_3__DISCARD_54                          0x00001000L
+#define CP_NV_FLAGS_3__END_RCVD_54_MASK                    0x00002000L
+#define CP_NV_FLAGS_3__END_RCVD_54                         0x00002000L
+#define CP_NV_FLAGS_3__DISCARD_55_MASK                     0x00004000L
+#define CP_NV_FLAGS_3__DISCARD_55                          0x00004000L
+#define CP_NV_FLAGS_3__END_RCVD_55_MASK                    0x00008000L
+#define CP_NV_FLAGS_3__END_RCVD_55                         0x00008000L
+#define CP_NV_FLAGS_3__DISCARD_56_MASK                     0x00010000L
+#define CP_NV_FLAGS_3__DISCARD_56                          0x00010000L
+#define CP_NV_FLAGS_3__END_RCVD_56_MASK                    0x00020000L
+#define CP_NV_FLAGS_3__END_RCVD_56                         0x00020000L
+#define CP_NV_FLAGS_3__DISCARD_57_MASK                     0x00040000L
+#define CP_NV_FLAGS_3__DISCARD_57                          0x00040000L
+#define CP_NV_FLAGS_3__END_RCVD_57_MASK                    0x00080000L
+#define CP_NV_FLAGS_3__END_RCVD_57                         0x00080000L
+#define CP_NV_FLAGS_3__DISCARD_58_MASK                     0x00100000L
+#define CP_NV_FLAGS_3__DISCARD_58                          0x00100000L
+#define CP_NV_FLAGS_3__END_RCVD_58_MASK                    0x00200000L
+#define CP_NV_FLAGS_3__END_RCVD_58                         0x00200000L
+#define CP_NV_FLAGS_3__DISCARD_59_MASK                     0x00400000L
+#define CP_NV_FLAGS_3__DISCARD_59                          0x00400000L
+#define CP_NV_FLAGS_3__END_RCVD_59_MASK                    0x00800000L
+#define CP_NV_FLAGS_3__END_RCVD_59                         0x00800000L
+#define CP_NV_FLAGS_3__DISCARD_60_MASK                     0x01000000L
+#define CP_NV_FLAGS_3__DISCARD_60                          0x01000000L
+#define CP_NV_FLAGS_3__END_RCVD_60_MASK                    0x02000000L
+#define CP_NV_FLAGS_3__END_RCVD_60                         0x02000000L
+#define CP_NV_FLAGS_3__DISCARD_61_MASK                     0x04000000L
+#define CP_NV_FLAGS_3__DISCARD_61                          0x04000000L
+#define CP_NV_FLAGS_3__END_RCVD_61_MASK                    0x08000000L
+#define CP_NV_FLAGS_3__END_RCVD_61                         0x08000000L
+#define CP_NV_FLAGS_3__DISCARD_62_MASK                     0x10000000L
+#define CP_NV_FLAGS_3__DISCARD_62                          0x10000000L
+#define CP_NV_FLAGS_3__END_RCVD_62_MASK                    0x20000000L
+#define CP_NV_FLAGS_3__END_RCVD_62                         0x20000000L
+#define CP_NV_FLAGS_3__DISCARD_63_MASK                     0x40000000L
+#define CP_NV_FLAGS_3__DISCARD_63                          0x40000000L
+#define CP_NV_FLAGS_3__END_RCVD_63_MASK                    0x80000000L
+#define CP_NV_FLAGS_3__END_RCVD_63                         0x80000000L
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK       0x0000001fL
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK         0xffffffffL
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER_MASK                      0xffffffffL
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY_MASK                          0x00000001L
+#define CP_STAT__MIU_WR_BUSY                               0x00000001L
+#define CP_STAT__MIU_RD_REQ_BUSY_MASK                      0x00000002L
+#define CP_STAT__MIU_RD_REQ_BUSY                           0x00000002L
+#define CP_STAT__MIU_RD_RETURN_BUSY_MASK                   0x00000004L
+#define CP_STAT__MIU_RD_RETURN_BUSY                        0x00000004L
+#define CP_STAT__RBIU_BUSY_MASK                            0x00000008L
+#define CP_STAT__RBIU_BUSY                                 0x00000008L
+#define CP_STAT__RCIU_BUSY_MASK                            0x00000010L
+#define CP_STAT__RCIU_BUSY                                 0x00000010L
+#define CP_STAT__CSF_RING_BUSY_MASK                        0x00000020L
+#define CP_STAT__CSF_RING_BUSY                             0x00000020L
+#define CP_STAT__CSF_INDIRECTS_BUSY_MASK                   0x00000040L
+#define CP_STAT__CSF_INDIRECTS_BUSY                        0x00000040L
+#define CP_STAT__CSF_INDIRECT2_BUSY_MASK                   0x00000080L
+#define CP_STAT__CSF_INDIRECT2_BUSY                        0x00000080L
+#define CP_STAT__CSF_ST_BUSY_MASK                          0x00000200L
+#define CP_STAT__CSF_ST_BUSY                               0x00000200L
+#define CP_STAT__CSF_BUSY_MASK                             0x00000400L
+#define CP_STAT__CSF_BUSY                                  0x00000400L
+#define CP_STAT__RING_QUEUE_BUSY_MASK                      0x00000800L
+#define CP_STAT__RING_QUEUE_BUSY                           0x00000800L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK                 0x00001000L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY                      0x00001000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK                 0x00002000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY                      0x00002000L
+#define CP_STAT__ST_QUEUE_BUSY_MASK                        0x00010000L
+#define CP_STAT__ST_QUEUE_BUSY                             0x00010000L
+#define CP_STAT__PFP_BUSY_MASK                             0x00020000L
+#define CP_STAT__PFP_BUSY                                  0x00020000L
+#define CP_STAT__MEQ_RING_BUSY_MASK                        0x00040000L
+#define CP_STAT__MEQ_RING_BUSY                             0x00040000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK                   0x00080000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY                        0x00080000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK                   0x00100000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY                        0x00100000L
+#define CP_STAT__MIU_WC_STALL_MASK                         0x00200000L
+#define CP_STAT__MIU_WC_STALL                              0x00200000L
+#define CP_STAT__CP_NRT_BUSY_MASK                          0x00400000L
+#define CP_STAT__CP_NRT_BUSY                               0x00400000L
+#define CP_STAT___3D_BUSY_MASK                             0x00800000L
+#define CP_STAT___3D_BUSY                                  0x00800000L
+#define CP_STAT__ME_BUSY_MASK                              0x04000000L
+#define CP_STAT__ME_BUSY                                   0x04000000L
+#define CP_STAT__ME_WC_BUSY_MASK                           0x20000000L
+#define CP_STAT__ME_WC_BUSY                                0x20000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK              0x40000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY                   0x40000000L
+#define CP_STAT__CP_BUSY_MASK                              0x80000000L
+#define CP_STAT__CP_BUSY                                   0x80000000L
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE_MASK                          0xffffffffL
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE_MASK                          0xffffffffL
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK           0x000000ffL
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK       0x00000100L
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA            0x00000100L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK             0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA                  0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK             0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA                  0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK             0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA                  0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK             0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA                  0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK             0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA                  0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK             0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA                  0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK             0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA                  0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK             0x00010000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA                  0x00010000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK           0x00020000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA                0x00020000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK               0x02000000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA                    0x02000000L
+#define COHER_STATUS_PM4__STATUS_MASK                      0x80000000L
+#define COHER_STATUS_PM4__STATUS                           0x80000000L
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE_MASK                         0xffffffffL
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE_MASK                         0xffffffffL
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK          0x000000ffL
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK      0x00000100L
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA           0x00000100L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK            0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA                 0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK            0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA                 0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK            0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA                 0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK            0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA                 0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK            0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA                 0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK            0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA                 0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK            0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA                 0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK            0x00010000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA                 0x00010000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK          0x00020000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA               0x00020000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK              0x02000000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA                   0x02000000L
+#define COHER_STATUS_HOST__STATUS_MASK                     0x80000000L
+#define COHER_STATUS_HOST__STATUS                          0x80000000L
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0_MASK                0xfffff000L
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1_MASK                0xfffff000L
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2_MASK                0xfffff000L
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3_MASK                0xfffff000L
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4_MASK                0xfffff000L
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5_MASK                0xfffff000L
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6_MASK                0xfffff000L
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7_MASK                0xfffff000L
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH_MASK                0x00003fffL
+#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK                 0x0000c000L
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT_MASK                   0x0000000fL
+#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK               0x00000030L
+#define RB_COLOR_INFO__COLOR_LINEAR_MASK                   0x00000040L
+#define RB_COLOR_INFO__COLOR_LINEAR                        0x00000040L
+#define RB_COLOR_INFO__COLOR_ENDIAN_MASK                   0x00000180L
+#define RB_COLOR_INFO__COLOR_SWAP_MASK                     0x00000600L
+#define RB_COLOR_INFO__COLOR_BASE_MASK                     0xfffff000L
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK                   0x00000001L
+#define RB_DEPTH_INFO__DEPTH_FORMAT                        0x00000001L
+#define RB_DEPTH_INFO__DEPTH_BASE_MASK                     0xfffff000L
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF_MASK                 0x000000ffL
+#define RB_STENCILREFMASK__STENCILMASK_MASK                0x0000ff00L
+#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK           0x00ff0000L
+#define RB_STENCILREFMASK__RESERVED0_MASK                  0x01000000L
+#define RB_STENCILREFMASK__RESERVED0                       0x01000000L
+#define RB_STENCILREFMASK__RESERVED1_MASK                  0x02000000L
+#define RB_STENCILREFMASK__RESERVED1                       0x02000000L
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF_MASK                       0xffffffffL
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED_MASK                      0x00000001L
+#define RB_COLOR_MASK__WRITE_RED                           0x00000001L
+#define RB_COLOR_MASK__WRITE_GREEN_MASK                    0x00000002L
+#define RB_COLOR_MASK__WRITE_GREEN                         0x00000002L
+#define RB_COLOR_MASK__WRITE_BLUE_MASK                     0x00000004L
+#define RB_COLOR_MASK__WRITE_BLUE                          0x00000004L
+#define RB_COLOR_MASK__WRITE_ALPHA_MASK                    0x00000008L
+#define RB_COLOR_MASK__WRITE_ALPHA                         0x00000008L
+#define RB_COLOR_MASK__RESERVED2_MASK                      0x00000010L
+#define RB_COLOR_MASK__RESERVED2                           0x00000010L
+#define RB_COLOR_MASK__RESERVED3_MASK                      0x00000020L
+#define RB_COLOR_MASK__RESERVED3                           0x00000020L
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED_MASK                       0x000000ffL
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN_MASK                   0x000000ffL
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE_MASK                     0x000000ffL
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK                   0x000000ffL
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED_MASK                         0x000000ffL
+#define RB_FOG_COLOR__FOG_GREEN_MASK                       0x0000ff00L
+#define RB_FOG_COLOR__FOG_BLUE_MASK                        0x00ff0000L
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK           0x000000ffL
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK          0x0000ff00L
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK     0x00ff0000L
+#define RB_STENCILREFMASK_BF__RESERVED4_MASK               0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED4                    0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED5_MASK               0x02000000L
+#define RB_STENCILREFMASK_BF__RESERVED5                    0x02000000L
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK               0x00000001L
+#define RB_DEPTHCONTROL__STENCIL_ENABLE                    0x00000001L
+#define RB_DEPTHCONTROL__Z_ENABLE_MASK                     0x00000002L
+#define RB_DEPTHCONTROL__Z_ENABLE                          0x00000002L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK               0x00000004L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE                    0x00000004L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK               0x00000008L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE                    0x00000008L
+#define RB_DEPTHCONTROL__ZFUNC_MASK                        0x00000070L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK              0x00000080L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE                   0x00000080L
+#define RB_DEPTHCONTROL__STENCILFUNC_MASK                  0x00000700L
+#define RB_DEPTHCONTROL__STENCILFAIL_MASK                  0x00003800L
+#define RB_DEPTHCONTROL__STENCILZPASS_MASK                 0x0001c000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_MASK                 0x000e0000L
+#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK               0x00700000L
+#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK               0x03800000L
+#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK              0x1c000000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK              0xe0000000L
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK               0x0000001fL
+#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK               0x000000e0L
+#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK              0x00001f00L
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK               0x001f0000L
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK               0x00e00000L
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK              0x1f000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK           0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE                0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_MASK                  0x40000000L
+#define RB_BLENDCONTROL__BLEND_FORCE                       0x40000000L
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC_MASK                   0x00000007L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK            0x00000008L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE                 0x00000008L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK         0x00000010L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE              0x00000010L
+#define RB_COLORCONTROL__BLEND_DISABLE_MASK                0x00000020L
+#define RB_COLORCONTROL__BLEND_DISABLE                     0x00000020L
+#define RB_COLORCONTROL__FOG_ENABLE_MASK                   0x00000040L
+#define RB_COLORCONTROL__FOG_ENABLE                        0x00000040L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK               0x00000080L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG                    0x00000080L
+#define RB_COLORCONTROL__ROP_CODE_MASK                     0x00000f00L
+#define RB_COLORCONTROL__DITHER_MODE_MASK                  0x00003000L
+#define RB_COLORCONTROL__DITHER_TYPE_MASK                  0x0000c000L
+#define RB_COLORCONTROL__PIXEL_FOG_MASK                    0x00010000L
+#define RB_COLORCONTROL__PIXEL_FOG                         0x00010000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK        0x03000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK        0x0c000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK        0x30000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK        0xc0000000L
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE_MASK                    0x00000007L
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK           0xffffffffL
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK           0x00000007L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK           0x00000008L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE                0x00000008L
+#define RB_COPY_CONTROL__CLEAR_MASK_MASK                   0x000000f0L
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK             0xfffff000L
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK           0x000001ffL
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK           0x00000007L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK           0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR                0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK           0x000000f0L
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK             0x00000300L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK      0x00000c00L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK      0x00003000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK        0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED             0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK      0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN           0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK       0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE            0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK      0x00020000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA           0x00020000L
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK           0x00001fffL
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK           0x03ffe000L
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                   0xffffffffL
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK       0x00000001L
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT            0x00000001L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK        0x00000002L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT             0x00000002L
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK       0xffffffffL
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK       0x00000001L
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE            0x00000001L
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK           0x00000006L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK              0x00000008L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM                   0x00000008L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK      0x00000020L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP           0x00000020L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK      0x00000040L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP           0x00000040L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK             0x00000080L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE                  0x00000080L
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK              0x00001f00L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK              0x00004000L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE                   0x00004000L
+#define RB_BC_CONTROL__CRC_MODE_MASK                       0x00008000L
+#define RB_BC_CONTROL__CRC_MODE                            0x00008000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK        0x00010000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS             0x00010000L
+#define RB_BC_CONTROL__DISABLE_ACCUM_MASK                  0x00020000L
+#define RB_BC_CONTROL__DISABLE_ACCUM                       0x00020000L
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK               0x003c0000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK      0x00400000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE           0x00400000L
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK          0x07800000L
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK      0x18000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK  0x20000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000L
+#define RB_BC_CONTROL__CRC_SYSTEM_MASK                     0x40000000L
+#define RB_BC_CONTROL__CRC_SYSTEM                          0x40000000L
+#define RB_BC_CONTROL__RESERVED6_MASK                      0x80000000L
+#define RB_BC_CONTROL__RESERVED6                           0x80000000L
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE_MASK                     0x0000000fL
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK             0x00000030L
+#define RB_EDRAM_INFO__EDRAM_RANGE_MASK                    0xffffc000L
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA_MASK                      0xffffffffL
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK                0x00000001L
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE                     0x00000001L
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK_MASK                         0xffffffffL
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK               0xffffffffL
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK               0xffffffffL
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK             0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL                  0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK             0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL                  0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK             0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL                  0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK             0x00000008L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL                  0x00000008L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK            0x00000010L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL                 0x00000010L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK            0x00000020L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL                 0x00000020L
+#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK                     0x00000040L
+#define RB_DEBUG_0__RDREQ_Z1_FULL                          0x00000040L
+#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK                     0x00000080L
+#define RB_DEBUG_0__RDREQ_Z0_FULL                          0x00000080L
+#define RB_DEBUG_0__RDREQ_C1_FULL_MASK                     0x00000100L
+#define RB_DEBUG_0__RDREQ_C1_FULL                          0x00000100L
+#define RB_DEBUG_0__RDREQ_C0_FULL_MASK                     0x00000200L
+#define RB_DEBUG_0__RDREQ_C0_FULL                          0x00000200L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK            0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL                 0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK            0x00000800L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL                 0x00000800L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK            0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL                 0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK            0x00002000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL                 0x00002000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK                0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL                     0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK                0x00008000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL                     0x00008000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK                     0x00010000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL                          0x00010000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK                     0x00020000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL                          0x00020000L
+#define RB_DEBUG_0__WRREQ_C1_FULL_MASK                     0x00040000L
+#define RB_DEBUG_0__WRREQ_C1_FULL                          0x00040000L
+#define RB_DEBUG_0__WRREQ_C0_FULL_MASK                     0x00080000L
+#define RB_DEBUG_0__WRREQ_C0_FULL                          0x00080000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK              0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL                   0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK              0x00200000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL                   0x00200000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK              0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL                   0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK              0x00800000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL                   0x00800000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK           0x01000000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL                0x01000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK           0x02000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL                0x02000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL_MASK                     0x04000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL                          0x04000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL_MASK                     0x08000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL                          0x08000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK                    0x10000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL                         0x10000000L
+#define RB_DEBUG_0__C_REQ_FULL_MASK                        0x20000000L
+#define RB_DEBUG_0__C_REQ_FULL                             0x20000000L
+#define RB_DEBUG_0__C_MASK_FULL_MASK                       0x40000000L
+#define RB_DEBUG_0__C_MASK_FULL                            0x40000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK                   0x80000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL                        0x80000000L
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK                0x00000001L
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY                     0x00000001L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK                0x00000002L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY                     0x00000002L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK                0x00000004L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY                     0x00000004L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK                0x00000008L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY                     0x00000008L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK           0x00000010L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY                0x00000010L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK           0x00000020L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY                0x00000020L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK                    0x00000040L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY                         0x00000040L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK                    0x00000080L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY                         0x00000080L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK                    0x00000100L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY                         0x00000100L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK                    0x00000200L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY                         0x00000200L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK           0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY                0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK           0x00000800L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY                0x00000800L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK           0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY                0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK           0x00002000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY                0x00002000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK               0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY                    0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK               0x00008000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY                    0x00008000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK                    0x00010000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY                         0x00010000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK                    0x00020000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY                         0x00020000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK                0x00040000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY                     0x00040000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK                0x00080000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY                     0x00080000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK             0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY                  0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY                  0x00200000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY                  0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK             0x00800000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY                  0x00800000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK          0x01000000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY               0x01000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK          0x02000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY               0x02000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK                    0x04000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY                         0x04000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK                    0x08000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY                         0x08000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK                   0x10000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY                        0x10000000L
+#define RB_DEBUG_1__C_REQ_EMPTY_MASK                       0x20000000L
+#define RB_DEBUG_1__C_REQ_EMPTY                            0x20000000L
+#define RB_DEBUG_1__C_MASK_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_1__C_MASK_EMPTY                           0x40000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK                  0x80000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY                       0x80000000L
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK                   0x0000000fL
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK                 0x000007f0L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK                   0x00000800L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG                        0x00000800L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK                 0x00001000L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG                      0x00001000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK                0x00002000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT                     0x00002000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK                   0x00004000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL                        0x00004000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK                0x00008000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL                     0x00008000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK                0x00010000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL                     0x00010000L
+#define RB_DEBUG_2__Z0_MASK_FULL_MASK                      0x00020000L
+#define RB_DEBUG_2__Z0_MASK_FULL                           0x00020000L
+#define RB_DEBUG_2__Z1_MASK_FULL_MASK                      0x00040000L
+#define RB_DEBUG_2__Z1_MASK_FULL                           0x00040000L
+#define RB_DEBUG_2__Z0_REQ_FULL_MASK                       0x00080000L
+#define RB_DEBUG_2__Z0_REQ_FULL                            0x00080000L
+#define RB_DEBUG_2__Z1_REQ_FULL_MASK                       0x00100000L
+#define RB_DEBUG_2__Z1_REQ_FULL                            0x00100000L
+#define RB_DEBUG_2__Z_SAMP_FULL_MASK                       0x00200000L
+#define RB_DEBUG_2__Z_SAMP_FULL                            0x00200000L
+#define RB_DEBUG_2__Z_TILE_FULL_MASK                       0x00400000L
+#define RB_DEBUG_2__Z_TILE_FULL                            0x00400000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK                  0x00800000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY                       0x00800000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK               0x01000000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY                    0x01000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK               0x02000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY                    0x02000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK                     0x04000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY                          0x04000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK                     0x08000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY                          0x08000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK                      0x10000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY                           0x10000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK                      0x20000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY                           0x20000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY                           0x40000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY_MASK                      0x80000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY                           0x80000000L
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID_MASK                       0x0000000fL
+#define RB_DEBUG_3__ACCUM_FLUSHING_MASK                    0x000000f0L
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK           0x00003f00L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK             0x00004000L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID                  0x00004000L
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK               0x00078000L
+#define RB_DEBUG_3__SHD_FULL_MASK                          0x00080000L
+#define RB_DEBUG_3__SHD_FULL                               0x00080000L
+#define RB_DEBUG_3__SHD_EMPTY_MASK                         0x00100000L
+#define RB_DEBUG_3__SHD_EMPTY                              0x00100000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY                  0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY                  0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK              0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL                   0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK              0x01000000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL                   0x01000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK                  0x02000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY                       0x02000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK                  0x04000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY                       0x04000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK                   0x08000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL                        0x08000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK                   0x10000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL                        0x10000000L
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK               0x00000001L
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG                    0x00000001L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK               0x00000002L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG                    0x00000002L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK             0x00000004L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG                  0x00000004L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK             0x00000008L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG                  0x00000008L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK             0x00000010L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY                  0x00000010L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK            0x00000020L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY                 0x00000020L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK              0x00000040L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL                   0x00000040L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK             0x00000080L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL                  0x00000080L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK       0x00000100L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW            0x00000100L
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK               0x00001e00L
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK             0x00000001L
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR                  0x00000001L
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED_MASK                        0xffffffffL
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP   0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK     0x00000600L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h
new file mode 100644
index 00000000000..ec7c7e12661
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h
@@ -0,0 +1,590 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamato_OFFSET_HEADER
+#define _yamato_OFFSET_HEADER
+
+// Registers from PA block
+
+#define mmPA_CL_VPORT_XSCALE           0x210F
+#define mmPA_CL_VPORT_XOFFSET          0x2110
+#define mmPA_CL_VPORT_YSCALE           0x2111
+#define mmPA_CL_VPORT_YOFFSET          0x2112
+#define mmPA_CL_VPORT_ZSCALE           0x2113
+#define mmPA_CL_VPORT_ZOFFSET          0x2114
+#define mmPA_CL_VTE_CNTL               0x2206
+#define mmPA_CL_CLIP_CNTL              0x2204
+#define mmPA_CL_GB_VERT_CLIP_ADJ       0x2303
+#define mmPA_CL_GB_VERT_DISC_ADJ       0x2304
+#define mmPA_CL_GB_HORZ_CLIP_ADJ       0x2305
+#define mmPA_CL_GB_HORZ_DISC_ADJ       0x2306
+#define mmPA_CL_ENHANCE                0x0C85
+#define mmPA_SC_ENHANCE                0x0CA5
+#define mmPA_SU_VTX_CNTL               0x2302
+#define mmPA_SU_POINT_SIZE             0x2280
+#define mmPA_SU_POINT_MINMAX           0x2281
+#define mmPA_SU_LINE_CNTL              0x2282
+#define mmPA_SU_FACE_DATA              0x0C86
+#define mmPA_SU_SC_MODE_CNTL           0x2205
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
+#define mmPA_SU_PERFCOUNTER0_SELECT    0x0C88
+#define mmPA_SU_PERFCOUNTER1_SELECT    0x0C89
+#define mmPA_SU_PERFCOUNTER2_SELECT    0x0C8A
+#define mmPA_SU_PERFCOUNTER3_SELECT    0x0C8B
+#define mmPA_SU_PERFCOUNTER0_LOW       0x0C8C
+#define mmPA_SU_PERFCOUNTER0_HI        0x0C8D
+#define mmPA_SU_PERFCOUNTER1_LOW       0x0C8E
+#define mmPA_SU_PERFCOUNTER1_HI        0x0C8F
+#define mmPA_SU_PERFCOUNTER2_LOW       0x0C90
+#define mmPA_SU_PERFCOUNTER2_HI        0x0C91
+#define mmPA_SU_PERFCOUNTER3_LOW       0x0C92
+#define mmPA_SU_PERFCOUNTER3_HI        0x0C93
+#define mmPA_SC_WINDOW_OFFSET          0x2080
+#define mmPA_SC_AA_CONFIG              0x2301
+#define mmPA_SC_AA_MASK                0x2312
+#define mmPA_SC_LINE_STIPPLE           0x2283
+#define mmPA_SC_LINE_CNTL              0x2300
+#define mmPA_SC_WINDOW_SCISSOR_TL      0x2081
+#define mmPA_SC_WINDOW_SCISSOR_BR      0x2082
+#define mmPA_SC_SCREEN_SCISSOR_TL      0x200E
+#define mmPA_SC_SCREEN_SCISSOR_BR      0x200F
+#define mmPA_SC_VIZ_QUERY              0x2293
+#define mmPA_SC_VIZ_QUERY_STATUS       0x0C44
+#define mmPA_SC_LINE_STIPPLE_STATE     0x0C40
+#define mmPA_SC_PERFCOUNTER0_SELECT    0x0C98
+#define mmPA_SC_PERFCOUNTER0_LOW       0x0C99
+#define mmPA_SC_PERFCOUNTER0_HI        0x0C9A
+#define mmPA_CL_CNTL_STATUS            0x0C84
+#define mmPA_SU_CNTL_STATUS            0x0C94
+#define mmPA_SC_CNTL_STATUS            0x0CA4
+#define mmPA_SU_DEBUG_CNTL             0x0C80
+#define mmPA_SU_DEBUG_DATA             0x0C81
+#define mmPA_SC_DEBUG_CNTL             0x0C82
+#define mmPA_SC_DEBUG_DATA             0x0C83
+
+
+// Registers from VGT block
+
+#define mmGFX_COPY_STATE               0x21F4
+#define mmVGT_DRAW_INITIATOR           0x21FC
+#define mmVGT_EVENT_INITIATOR          0x21F9
+#define mmVGT_DMA_BASE                 0x21FA
+#define mmVGT_DMA_SIZE                 0x21FB
+#define mmVGT_BIN_BASE                 0x21FE
+#define mmVGT_BIN_SIZE                 0x21FF
+#define mmVGT_CURRENT_BIN_ID_MIN       0x2207
+#define mmVGT_CURRENT_BIN_ID_MAX       0x2203
+#define mmVGT_IMMED_DATA               0x21FD
+#define mmVGT_MAX_VTX_INDX             0x2100
+#define mmVGT_MIN_VTX_INDX             0x2101
+#define mmVGT_INDX_OFFSET              0x2102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL  0x2316
+#define mmVGT_OUT_DEALLOC_CNTL         0x2317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103
+#define mmVGT_ENHANCE                  0x2294
+#define mmVGT_VTX_VECT_EJECT_REG       0x0C2C
+#define mmVGT_LAST_COPY_STATE          0x0C30
+#define mmVGT_DEBUG_CNTL               0x0C38
+#define mmVGT_DEBUG_DATA               0x0C39
+#define mmVGT_CNTL_STATUS              0x0C3C
+#define mmVGT_CRC_SQ_DATA              0x0C3A
+#define mmVGT_CRC_SQ_CTRL              0x0C3B
+#define mmVGT_PERFCOUNTER0_SELECT      0x0C48
+#define mmVGT_PERFCOUNTER1_SELECT      0x0C49
+#define mmVGT_PERFCOUNTER2_SELECT      0x0C4A
+#define mmVGT_PERFCOUNTER3_SELECT      0x0C4B
+#define mmVGT_PERFCOUNTER0_LOW         0x0C4C
+#define mmVGT_PERFCOUNTER1_LOW         0x0C4E
+#define mmVGT_PERFCOUNTER2_LOW         0x0C50
+#define mmVGT_PERFCOUNTER3_LOW         0x0C52
+#define mmVGT_PERFCOUNTER0_HI          0x0C4D
+#define mmVGT_PERFCOUNTER1_HI          0x0C4F
+#define mmVGT_PERFCOUNTER2_HI          0x0C51
+#define mmVGT_PERFCOUNTER3_HI          0x0C53
+
+
+// Registers from TP block
+
+#define mmTC_CNTL_STATUS               0x0E00
+#define mmTCR_CHICKEN                  0x0E02
+#define mmTCF_CHICKEN                  0x0E03
+#define mmTCM_CHICKEN                  0x0E04
+#define mmTCR_PERFCOUNTER0_SELECT      0x0E05
+#define mmTCR_PERFCOUNTER1_SELECT      0x0E08
+#define mmTCR_PERFCOUNTER0_HI          0x0E06
+#define mmTCR_PERFCOUNTER1_HI          0x0E09
+#define mmTCR_PERFCOUNTER0_LOW         0x0E07
+#define mmTCR_PERFCOUNTER1_LOW         0x0E0A
+#define mmTP_TC_CLKGATE_CNTL           0x0E17
+#define mmTPC_CNTL_STATUS              0x0E18
+#define mmTPC_DEBUG0                   0x0E19
+#define mmTPC_DEBUG1                   0x0E1A
+#define mmTPC_CHICKEN                  0x0E1B
+#define mmTP0_CNTL_STATUS              0x0E1C
+#define mmTP0_DEBUG                    0x0E1D
+#define mmTP0_CHICKEN                  0x0E1E
+#define mmTP0_PERFCOUNTER0_SELECT      0x0E1F
+#define mmTP0_PERFCOUNTER0_HI          0x0E20
+#define mmTP0_PERFCOUNTER0_LOW         0x0E21
+#define mmTP0_PERFCOUNTER1_SELECT      0x0E22
+#define mmTP0_PERFCOUNTER1_HI          0x0E23
+#define mmTP0_PERFCOUNTER1_LOW         0x0E24
+#define mmTCM_PERFCOUNTER0_SELECT      0x0E54
+#define mmTCM_PERFCOUNTER1_SELECT      0x0E57
+#define mmTCM_PERFCOUNTER0_HI          0x0E55
+#define mmTCM_PERFCOUNTER1_HI          0x0E58
+#define mmTCM_PERFCOUNTER0_LOW         0x0E56
+#define mmTCM_PERFCOUNTER1_LOW         0x0E59
+#define mmTCF_PERFCOUNTER0_SELECT      0x0E5A
+#define mmTCF_PERFCOUNTER1_SELECT      0x0E5D
+#define mmTCF_PERFCOUNTER2_SELECT      0x0E60
+#define mmTCF_PERFCOUNTER3_SELECT      0x0E63
+#define mmTCF_PERFCOUNTER4_SELECT      0x0E66
+#define mmTCF_PERFCOUNTER5_SELECT      0x0E69
+#define mmTCF_PERFCOUNTER6_SELECT      0x0E6C
+#define mmTCF_PERFCOUNTER7_SELECT      0x0E6F
+#define mmTCF_PERFCOUNTER8_SELECT      0x0E72
+#define mmTCF_PERFCOUNTER9_SELECT      0x0E75
+#define mmTCF_PERFCOUNTER10_SELECT     0x0E78
+#define mmTCF_PERFCOUNTER11_SELECT     0x0E7B
+#define mmTCF_PERFCOUNTER0_HI          0x0E5B
+#define mmTCF_PERFCOUNTER1_HI          0x0E5E
+#define mmTCF_PERFCOUNTER2_HI          0x0E61
+#define mmTCF_PERFCOUNTER3_HI          0x0E64
+#define mmTCF_PERFCOUNTER4_HI          0x0E67
+#define mmTCF_PERFCOUNTER5_HI          0x0E6A
+#define mmTCF_PERFCOUNTER6_HI          0x0E6D
+#define mmTCF_PERFCOUNTER7_HI          0x0E70
+#define mmTCF_PERFCOUNTER8_HI          0x0E73
+#define mmTCF_PERFCOUNTER9_HI          0x0E76
+#define mmTCF_PERFCOUNTER10_HI         0x0E79
+#define mmTCF_PERFCOUNTER11_HI         0x0E7C
+#define mmTCF_PERFCOUNTER0_LOW         0x0E5C
+#define mmTCF_PERFCOUNTER1_LOW         0x0E5F
+#define mmTCF_PERFCOUNTER2_LOW         0x0E62
+#define mmTCF_PERFCOUNTER3_LOW         0x0E65
+#define mmTCF_PERFCOUNTER4_LOW         0x0E68
+#define mmTCF_PERFCOUNTER5_LOW         0x0E6B
+#define mmTCF_PERFCOUNTER6_LOW         0x0E6E
+#define mmTCF_PERFCOUNTER7_LOW         0x0E71
+#define mmTCF_PERFCOUNTER8_LOW         0x0E74
+#define mmTCF_PERFCOUNTER9_LOW         0x0E77
+#define mmTCF_PERFCOUNTER10_LOW        0x0E7A
+#define mmTCF_PERFCOUNTER11_LOW        0x0E7D
+#define mmTCF_DEBUG                    0x0EC0
+#define mmTCA_FIFO_DEBUG               0x0EC1
+#define mmTCA_PROBE_DEBUG              0x0EC2
+#define mmTCA_TPC_DEBUG                0x0EC3
+#define mmTCB_CORE_DEBUG               0x0EC4
+#define mmTCB_TAG0_DEBUG               0x0EC5
+#define mmTCB_TAG1_DEBUG               0x0EC6
+#define mmTCB_TAG2_DEBUG               0x0EC7
+#define mmTCB_TAG3_DEBUG               0x0EC8
+#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9
+#define mmTCB_FETCH_GEN_WALKER_DEBUG   0x0ECB
+#define mmTCB_FETCH_GEN_PIPE0_DEBUG    0x0ECC
+#define mmTCD_INPUT0_DEBUG             0x0ED0
+#define mmTCD_DEGAMMA_DEBUG            0x0ED4
+#define mmTCD_DXTMUX_SCTARB_DEBUG      0x0ED5
+#define mmTCD_DXTC_ARB_DEBUG           0x0ED6
+#define mmTCD_STALLS_DEBUG             0x0ED7
+#define mmTCO_STALLS_DEBUG             0x0EE0
+#define mmTCO_QUAD0_DEBUG0             0x0EE1
+#define mmTCO_QUAD0_DEBUG1             0x0EE2
+
+
+// Registers from TC block
+
+
+
+// Registers from SQ block
+
+#define mmSQ_GPR_MANAGEMENT            0x0D00
+#define mmSQ_FLOW_CONTROL              0x0D01
+#define mmSQ_INST_STORE_MANAGMENT      0x0D02
+#define mmSQ_RESOURCE_MANAGMENT        0x0D03
+#define mmSQ_EO_RT                     0x0D04
+#define mmSQ_DEBUG_MISC                0x0D05
+#define mmSQ_ACTIVITY_METER_CNTL       0x0D06
+#define mmSQ_ACTIVITY_METER_STATUS     0x0D07
+#define mmSQ_INPUT_ARB_PRIORITY        0x0D08
+#define mmSQ_THREAD_ARB_PRIORITY       0x0D09
+#define mmSQ_VS_WATCHDOG_TIMER         0x0D0A
+#define mmSQ_PS_WATCHDOG_TIMER         0x0D0B
+#define mmSQ_INT_CNTL                  0x0D34
+#define mmSQ_INT_STATUS                0x0D35
+#define mmSQ_INT_ACK                   0x0D36
+#define mmSQ_DEBUG_INPUT_FSM           0x0DAE
+#define mmSQ_DEBUG_CONST_MGR_FSM       0x0DAF
+#define mmSQ_DEBUG_TP_FSM              0x0DB0
+#define mmSQ_DEBUG_FSM_ALU_0           0x0DB1
+#define mmSQ_DEBUG_FSM_ALU_1           0x0DB2
+#define mmSQ_DEBUG_EXP_ALLOC           0x0DB3
+#define mmSQ_DEBUG_PTR_BUFF            0x0DB4
+#define mmSQ_DEBUG_GPR_VTX             0x0DB5
+#define mmSQ_DEBUG_GPR_PIX             0x0DB6
+#define mmSQ_DEBUG_TB_STATUS_SEL       0x0DB7
+#define mmSQ_DEBUG_VTX_TB_0            0x0DB8
+#define mmSQ_DEBUG_VTX_TB_1            0x0DB9
+#define mmSQ_DEBUG_VTX_TB_STATUS_REG   0x0DBA
+#define mmSQ_DEBUG_VTX_TB_STATE_MEM    0x0DBB
+#define mmSQ_DEBUG_PIX_TB_0            0x0DBC
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
+#define mmSQ_DEBUG_PIX_TB_STATE_MEM    0x0DC1
+#define mmSQ_PERFCOUNTER0_SELECT       0x0DC8
+#define mmSQ_PERFCOUNTER1_SELECT       0x0DC9
+#define mmSQ_PERFCOUNTER2_SELECT       0x0DCA
+#define mmSQ_PERFCOUNTER3_SELECT       0x0DCB
+#define mmSQ_PERFCOUNTER0_LOW          0x0DCC
+#define mmSQ_PERFCOUNTER0_HI           0x0DCD
+#define mmSQ_PERFCOUNTER1_LOW          0x0DCE
+#define mmSQ_PERFCOUNTER1_HI           0x0DCF
+#define mmSQ_PERFCOUNTER2_LOW          0x0DD0
+#define mmSQ_PERFCOUNTER2_HI           0x0DD1
+#define mmSQ_PERFCOUNTER3_LOW          0x0DD2
+#define mmSQ_PERFCOUNTER3_HI           0x0DD3
+#define mmSX_PERFCOUNTER0_SELECT       0x0DD4
+#define mmSX_PERFCOUNTER0_LOW          0x0DD8
+#define mmSX_PERFCOUNTER0_HI           0x0DD9
+#define mmSQ_INSTRUCTION_ALU_0         0x5000
+#define mmSQ_INSTRUCTION_ALU_1         0x5001
+#define mmSQ_INSTRUCTION_ALU_2         0x5002
+#define mmSQ_INSTRUCTION_CF_EXEC_0     0x5080
+#define mmSQ_INSTRUCTION_CF_EXEC_1     0x5081
+#define mmSQ_INSTRUCTION_CF_EXEC_2     0x5082
+#define mmSQ_INSTRUCTION_CF_LOOP_0     0x5083
+#define mmSQ_INSTRUCTION_CF_LOOP_1     0x5084
+#define mmSQ_INSTRUCTION_CF_LOOP_2     0x5085
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088
+#define mmSQ_INSTRUCTION_CF_ALLOC_0    0x5089
+#define mmSQ_INSTRUCTION_CF_ALLOC_1    0x508A
+#define mmSQ_INSTRUCTION_CF_ALLOC_2    0x508B
+#define mmSQ_INSTRUCTION_TFETCH_0      0x5043
+#define mmSQ_INSTRUCTION_TFETCH_1      0x5044
+#define mmSQ_INSTRUCTION_TFETCH_2      0x5045
+#define mmSQ_INSTRUCTION_VFETCH_0      0x5040
+#define mmSQ_INSTRUCTION_VFETCH_1      0x5041
+#define mmSQ_INSTRUCTION_VFETCH_2      0x5042
+#define mmSQ_CONSTANT_0                0x4000
+#define mmSQ_CONSTANT_1                0x4001
+#define mmSQ_CONSTANT_2                0x4002
+#define mmSQ_CONSTANT_3                0x4003
+#define mmSQ_FETCH_0                   0x4800
+#define mmSQ_FETCH_1                   0x4801
+#define mmSQ_FETCH_2                   0x4802
+#define mmSQ_FETCH_3                   0x4803
+#define mmSQ_FETCH_4                   0x4804
+#define mmSQ_FETCH_5                   0x4805
+#define mmSQ_CONSTANT_VFETCH_0         0x4806
+#define mmSQ_CONSTANT_VFETCH_1         0x4808
+#define mmSQ_CONSTANT_T2               0x480C
+#define mmSQ_CONSTANT_T3               0x4812
+#define mmSQ_CF_BOOLEANS               0x4900
+#define mmSQ_CF_LOOP                   0x4908
+#define mmSQ_CONSTANT_RT_0             0x4940
+#define mmSQ_CONSTANT_RT_1             0x4941
+#define mmSQ_CONSTANT_RT_2             0x4942
+#define mmSQ_CONSTANT_RT_3             0x4943
+#define mmSQ_FETCH_RT_0                0x4D40
+#define mmSQ_FETCH_RT_1                0x4D41
+#define mmSQ_FETCH_RT_2                0x4D42
+#define mmSQ_FETCH_RT_3                0x4D43
+#define mmSQ_FETCH_RT_4                0x4D44
+#define mmSQ_FETCH_RT_5                0x4D45
+#define mmSQ_CF_RT_BOOLEANS            0x4E00
+#define mmSQ_CF_RT_LOOP                0x4E14
+#define mmSQ_VS_PROGRAM                0x21F7
+#define mmSQ_PS_PROGRAM                0x21F6
+#define mmSQ_CF_PROGRAM_SIZE           0x2315
+#define mmSQ_INTERPOLATOR_CNTL         0x2182
+#define mmSQ_PROGRAM_CNTL              0x2180
+#define mmSQ_WRAPPING_0                0x2183
+#define mmSQ_WRAPPING_1                0x2184
+#define mmSQ_VS_CONST                  0x2307
+#define mmSQ_PS_CONST                  0x2308
+#define mmSQ_CONTEXT_MISC              0x2181
+#define mmSQ_CF_RD_BASE                0x21F5
+#define mmSQ_DEBUG_MISC_0              0x2309
+#define mmSQ_DEBUG_MISC_1              0x230A
+
+
+// Registers from SX block
+
+
+
+// Registers from MH block
+
+#define mmMH_ARBITER_CONFIG            0x0A40
+#define mmMH_CLNT_AXI_ID_REUSE         0x0A41
+#define mmMH_INTERRUPT_MASK            0x0A42
+#define mmMH_INTERRUPT_STATUS          0x0A43
+#define mmMH_INTERRUPT_CLEAR           0x0A44
+#define mmMH_AXI_ERROR                 0x0A45
+#define mmMH_PERFCOUNTER0_SELECT       0x0A46
+#define mmMH_PERFCOUNTER1_SELECT       0x0A4A
+#define mmMH_PERFCOUNTER0_CONFIG       0x0A47
+#define mmMH_PERFCOUNTER1_CONFIG       0x0A4B
+#define mmMH_PERFCOUNTER0_LOW          0x0A48
+#define mmMH_PERFCOUNTER1_LOW          0x0A4C
+#define mmMH_PERFCOUNTER0_HI           0x0A49
+#define mmMH_PERFCOUNTER1_HI           0x0A4D
+#define mmMH_DEBUG_CTRL                0x0A4E
+#define mmMH_DEBUG_DATA                0x0A4F
+#define mmMH_AXI_HALT_CONTROL          0x0A50
+#define mmMH_MMU_CONFIG                0x0040
+#define mmMH_MMU_VA_RANGE              0x0041
+#define mmMH_MMU_PT_BASE               0x0042
+#define mmMH_MMU_PAGE_FAULT            0x0043
+#define mmMH_MMU_TRAN_ERROR            0x0044
+#define mmMH_MMU_INVALIDATE            0x0045
+#define mmMH_MMU_MPU_BASE              0x0046
+#define mmMH_MMU_MPU_END               0x0047
+
+
+// Registers from RBBM block
+
+#define mmWAIT_UNTIL                   0x05C8
+#define mmRBBM_ISYNC_CNTL              0x05C9
+#define mmRBBM_STATUS                  0x05D0
+#define mmRBBM_DSPLY                   0x0391
+#define mmRBBM_RENDER_LATEST           0x0392
+#define mmRBBM_RTL_RELEASE             0x0000
+#define mmRBBM_PATCH_RELEASE           0x0001
+#define mmRBBM_AUXILIARY_CONFIG        0x0002
+#define mmRBBM_PERIPHID0               0x03F8
+#define mmRBBM_PERIPHID1               0x03F9
+#define mmRBBM_PERIPHID2               0x03FA
+#define mmRBBM_PERIPHID3               0x03FB
+#define mmRBBM_CNTL                    0x003B
+#define mmRBBM_SKEW_CNTL               0x003D
+#define mmRBBM_SOFT_RESET              0x003C
+#define mmRBBM_PM_OVERRIDE1            0x039C
+#define mmRBBM_PM_OVERRIDE2            0x039D
+#define mmGC_SYS_IDLE                  0x039E
+#define mmNQWAIT_UNTIL                 0x0394
+#define mmRBBM_DEBUG_OUT               0x03A0
+#define mmRBBM_DEBUG_CNTL              0x03A1
+#define mmRBBM_DEBUG                   0x039B
+#define mmRBBM_READ_ERROR              0x03B3
+#define mmRBBM_WAIT_IDLE_CLOCKS        0x03B2
+#define mmRBBM_INT_CNTL                0x03B4
+#define mmRBBM_INT_STATUS              0x03B5
+#define mmRBBM_INT_ACK                 0x03B6
+#define mmMASTER_INT_SIGNAL            0x03B7
+#define mmRBBM_PERFCOUNTER1_SELECT     0x0395
+#define mmRBBM_PERFCOUNTER1_LO         0x0397
+#define mmRBBM_PERFCOUNTER1_HI         0x0398
+
+
+// Registers from CP block
+
+#define mmCP_RB_BASE                   0x01C0
+#define mmCP_RB_CNTL                   0x01C1
+#define mmCP_RB_RPTR_ADDR              0x01C3
+#define mmCP_RB_RPTR                   0x01C4
+#define mmCP_RB_RPTR_WR                0x01C7
+#define mmCP_RB_WPTR                   0x01C5
+#define mmCP_RB_WPTR_DELAY             0x01C6
+#define mmCP_RB_WPTR_BASE              0x01C8
+#define mmCP_IB1_BASE                  0x0458
+#define mmCP_IB1_BUFSZ                 0x0459
+#define mmCP_IB2_BASE                  0x045A
+#define mmCP_IB2_BUFSZ                 0x045B
+#define mmCP_ST_BASE                   0x044D
+#define mmCP_ST_BUFSZ                  0x044E
+#define mmCP_QUEUE_THRESHOLDS          0x01D5
+#define mmCP_MEQ_THRESHOLDS            0x01D6
+#define mmCP_CSQ_AVAIL                 0x01D7
+#define mmCP_STQ_AVAIL                 0x01D8
+#define mmCP_MEQ_AVAIL                 0x01D9
+#define mmCP_CSQ_RB_STAT               0x01FD
+#define mmCP_CSQ_IB1_STAT              0x01FE
+#define mmCP_CSQ_IB2_STAT              0x01FF
+#define mmCP_NON_PREFETCH_CNTRS        0x0440
+#define mmCP_STQ_ST_STAT               0x0443
+#define mmCP_MEQ_STAT                  0x044F
+#define mmCP_MIU_TAG_STAT              0x0452
+#define mmCP_CMD_INDEX                 0x01DA
+#define mmCP_CMD_DATA                  0x01DB
+#define mmCP_ME_CNTL                   0x01F6
+#define mmCP_ME_STATUS                 0x01F7
+#define mmCP_ME_RAM_WADDR              0x01F8
+#define mmCP_ME_RAM_RADDR              0x01F9
+#define mmCP_ME_RAM_DATA               0x01FA
+#define mmCP_ME_RDADDR                 0x01EA
+#define mmCP_DEBUG                     0x01FC
+#define mmSCRATCH_REG0                 0x0578
+#define mmGUI_SCRATCH_REG0             0x0578
+#define mmSCRATCH_REG1                 0x0579
+#define mmGUI_SCRATCH_REG1             0x0579
+#define mmSCRATCH_REG2                 0x057A
+#define mmGUI_SCRATCH_REG2             0x057A
+#define mmSCRATCH_REG3                 0x057B
+#define mmGUI_SCRATCH_REG3             0x057B
+#define mmSCRATCH_REG4                 0x057C
+#define mmGUI_SCRATCH_REG4             0x057C
+#define mmSCRATCH_REG5                 0x057D
+#define mmGUI_SCRATCH_REG5             0x057D
+#define mmSCRATCH_REG6                 0x057E
+#define mmGUI_SCRATCH_REG6             0x057E
+#define mmSCRATCH_REG7                 0x057F
+#define mmGUI_SCRATCH_REG7             0x057F
+#define mmSCRATCH_UMSK                 0x01DC
+#define mmSCRATCH_ADDR                 0x01DD
+#define mmCP_ME_VS_EVENT_SRC           0x0600
+#define mmCP_ME_VS_EVENT_ADDR          0x0601
+#define mmCP_ME_VS_EVENT_DATA          0x0602
+#define mmCP_ME_VS_EVENT_ADDR_SWM      0x0603
+#define mmCP_ME_VS_EVENT_DATA_SWM      0x0604
+#define mmCP_ME_PS_EVENT_SRC           0x0605
+#define mmCP_ME_PS_EVENT_ADDR          0x0606
+#define mmCP_ME_PS_EVENT_DATA          0x0607
+#define mmCP_ME_PS_EVENT_ADDR_SWM      0x0608
+#define mmCP_ME_PS_EVENT_DATA_SWM      0x0609
+#define mmCP_ME_CF_EVENT_SRC           0x060A
+#define mmCP_ME_CF_EVENT_ADDR          0x060B
+#define mmCP_ME_CF_EVENT_DATA          0x060C
+#define mmCP_ME_NRT_ADDR               0x060D
+#define mmCP_ME_NRT_DATA               0x060E
+#define mmCP_ME_VS_FETCH_DONE_SRC      0x0612
+#define mmCP_ME_VS_FETCH_DONE_ADDR     0x0613
+#define mmCP_ME_VS_FETCH_DONE_DATA     0x0614
+#define mmCP_INT_CNTL                  0x01F2
+#define mmCP_INT_STATUS                0x01F3
+#define mmCP_INT_ACK                   0x01F4
+#define mmCP_PFP_UCODE_ADDR            0x00C0
+#define mmCP_PFP_UCODE_DATA            0x00C1
+#define mmCP_PERFMON_CNTL              0x0444
+#define mmCP_PERFCOUNTER_SELECT        0x0445
+#define mmCP_PERFCOUNTER_LO            0x0446
+#define mmCP_PERFCOUNTER_HI            0x0447
+#define mmCP_BIN_MASK_LO               0x0454
+#define mmCP_BIN_MASK_HI               0x0455
+#define mmCP_BIN_SELECT_LO             0x0456
+#define mmCP_BIN_SELECT_HI             0x0457
+#define mmCP_NV_FLAGS_0                0x01EE
+#define mmCP_NV_FLAGS_1                0x01EF
+#define mmCP_NV_FLAGS_2                0x01F0
+#define mmCP_NV_FLAGS_3                0x01F1
+#define mmCP_STATE_DEBUG_INDEX         0x01EC
+#define mmCP_STATE_DEBUG_DATA          0x01ED
+#define mmCP_PROG_COUNTER              0x044B
+#define mmCP_STAT                      0x047F
+#define mmBIOS_0_SCRATCH               0x0004
+#define mmBIOS_1_SCRATCH               0x0005
+#define mmBIOS_2_SCRATCH               0x0006
+#define mmBIOS_3_SCRATCH               0x0007
+#define mmBIOS_4_SCRATCH               0x0008
+#define mmBIOS_5_SCRATCH               0x0009
+#define mmBIOS_6_SCRATCH               0x000A
+#define mmBIOS_7_SCRATCH               0x000B
+#define mmBIOS_8_SCRATCH               0x0580
+#define mmBIOS_9_SCRATCH               0x0581
+#define mmBIOS_10_SCRATCH              0x0582
+#define mmBIOS_11_SCRATCH              0x0583
+#define mmBIOS_12_SCRATCH              0x0584
+#define mmBIOS_13_SCRATCH              0x0585
+#define mmBIOS_14_SCRATCH              0x0586
+#define mmBIOS_15_SCRATCH              0x0587
+#define mmCOHER_SIZE_PM4               0x0A29
+#define mmCOHER_BASE_PM4               0x0A2A
+#define mmCOHER_STATUS_PM4             0x0A2B
+#define mmCOHER_SIZE_HOST              0x0A2F
+#define mmCOHER_BASE_HOST              0x0A30
+#define mmCOHER_STATUS_HOST            0x0A31
+#define mmCOHER_DEST_BASE_0            0x2006
+#define mmCOHER_DEST_BASE_1            0x2007
+#define mmCOHER_DEST_BASE_2            0x2008
+#define mmCOHER_DEST_BASE_3            0x2009
+#define mmCOHER_DEST_BASE_4            0x200A
+#define mmCOHER_DEST_BASE_5            0x200B
+#define mmCOHER_DEST_BASE_6            0x200C
+#define mmCOHER_DEST_BASE_7            0x200D
+
+
+// Registers from SC block
+
+
+
+// Registers from BC block
+
+#define mmRB_SURFACE_INFO              0x2000
+#define mmRB_COLOR_INFO                0x2001
+#define mmRB_DEPTH_INFO                0x2002
+#define mmRB_STENCILREFMASK            0x210D
+#define mmRB_ALPHA_REF                 0x210E
+#define mmRB_COLOR_MASK                0x2104
+#define mmRB_BLEND_RED                 0x2105
+#define mmRB_BLEND_GREEN               0x2106
+#define mmRB_BLEND_BLUE                0x2107
+#define mmRB_BLEND_ALPHA               0x2108
+#define mmRB_FOG_COLOR                 0x2109
+#define mmRB_STENCILREFMASK_BF         0x210C
+#define mmRB_DEPTHCONTROL              0x2200
+#define mmRB_BLENDCONTROL              0x2201
+#define mmRB_COLORCONTROL              0x2202
+#define mmRB_MODECONTROL               0x2208
+#define mmRB_COLOR_DEST_MASK           0x2326
+#define mmRB_COPY_CONTROL              0x2318
+#define mmRB_COPY_DEST_BASE            0x2319
+#define mmRB_COPY_DEST_PITCH           0x231A
+#define mmRB_COPY_DEST_INFO            0x231B
+#define mmRB_COPY_DEST_PIXEL_OFFSET    0x231C
+#define mmRB_DEPTH_CLEAR               0x231D
+#define mmRB_SAMPLE_COUNT_CTL          0x2324
+#define mmRB_SAMPLE_COUNT_ADDR         0x2325
+#define mmRB_BC_CONTROL                0x0F01
+#define mmRB_EDRAM_INFO                0x0F02
+#define mmRB_CRC_RD_PORT               0x0F0C
+#define mmRB_CRC_CONTROL               0x0F0D
+#define mmRB_CRC_MASK                  0x0F0E
+#define mmRB_PERFCOUNTER0_SELECT       0x0F04
+#define mmRB_PERFCOUNTER0_LOW          0x0F08
+#define mmRB_PERFCOUNTER0_HI           0x0F09
+#define mmRB_TOTAL_SAMPLES             0x0F0F
+#define mmRB_ZPASS_SAMPLES             0x0F10
+#define mmRB_ZFAIL_SAMPLES             0x0F11
+#define mmRB_SFAIL_SAMPLES             0x0F12
+#define mmRB_DEBUG_0                   0x0F26
+#define mmRB_DEBUG_1                   0x0F27
+#define mmRB_DEBUG_2                   0x0F28
+#define mmRB_DEBUG_3                   0x0F29
+#define mmRB_DEBUG_4                   0x0F2A
+#define mmRB_FLAG_CONTROL              0x0F2B
+#define mmRB_BC_SPARES                 0x0F2C
+#define mmBC_DUMMY_CRAYRB_ENUMS        0x0F15
+#define mmBC_DUMMY_CRAYRB_MOREENUMS    0x0F16
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h
new file mode 100644
index 00000000000..17379dcfa0e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h
@@ -0,0 +1,223 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_RANDOM_HEADER)
+#define _yamato_RANDOM_HEADER
+
+/*************************************************************
+ * THIS FILE IS AUTOMATICALLY CREATED.  DO NOT EDIT THIS FILE.
+ *************************************************************/
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SU_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SC_PERFCNT_SELECT>;
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRIM_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SOURCE_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_FACENESS_CULL_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_INDEX_SIZE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SMALL_INDEX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRE_FETCH_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_GRP_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_EVENT_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DMA_SWAP_MODE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCR_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TP_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCM_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCF_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SQ_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SX_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Abs_modifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Exporting>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ScalarOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SwizzleType>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<InputModifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredicateSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect1>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VectorOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect0>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Ressource_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Instruction_serial>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VC_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressing>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CFOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Allocation_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexInstOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressmode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexCoordDenorm>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SrcSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DstSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MipFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<AnisoFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ArbitraryFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SampleLocation>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VertexMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Sample_Cntl>;
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MhPerfEncode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MmuClntBeh>;
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RBBM_PERFCOUNT1_SEL>;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CP_PERFCOUNT_SEL>;
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareFrag>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareRef>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<StencilOp>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<BlendOpX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CombFuncX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherModeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherTypeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceEndian>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramSizeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RB_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceSwap>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumber>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceTiling>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumberX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArrayX>;
+
+#endif /*_yamato_RANDOM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h
new file mode 100644
index 00000000000..fc6b8b98f84
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h
@@ -0,0 +1,14278 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_REG_HEADER)
+#define _yamato_REG_HEADER
+
+    union PA_CL_VPORT_XSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_XSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_XSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_XOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_XOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_XOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_YSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_YSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_YOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_YOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_ZSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_ZSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_ZOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_ZOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VTE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int                                 : 2;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                                 : 2;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CLIP_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+        unsigned int                                 : 27;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 27;
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 28;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_VTX_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PIX_CENTER : 1;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      PIX_CENTER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          HEIGHT : 16;
+        unsigned int                           WIDTH : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           WIDTH : 16;
+        unsigned int                          HEIGHT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_MINMAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_SIZE : 16;
+        unsigned int                        MAX_SIZE : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MAX_SIZE : 16;
+        unsigned int                        MIN_SIZE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           WIDTH : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                           WIDTH : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_FACE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                       BASE_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_SC_MODE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CULL_FRONT : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                            FACE : 1;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int                                 : 2;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int               FACE_WRITE_ENABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               FACE_WRITE_ENABLE : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                                 : 2;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int                            FACE : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                      CULL_FRONT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 WINDOW_X_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_X_OFFSET : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+        unsigned int                                 : 10;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 10;
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         AA_MASK : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                         AA_MASK : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    LINE_PATTERN : 16;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                                 : 4;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                    LINE_PATTERN : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BRES_CNTL : 8;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int                       BRES_CNTL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 1;
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VIZ_QUERY_ENA : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                                 : 1;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                   VIZ_QUERY_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STATUS_BITS : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     STATUS_BITS : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CURRENT_PTR : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int                     CURRENT_PTR : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         CL_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CL_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SU_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SU_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SC_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SU_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SU_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           clip_ga_bc_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int                     ALWAYS_ZERO : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 12;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_ga_bc_fifo_write : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int                     ALWAYS_ZERO : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 8;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO1 : 21;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO1 : 21;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO0 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 6;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO3 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO0 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 24;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            clprim_in_back_event : 1;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int     clip_priority_seq_indx_load : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int     clip_priority_seq_indx_load : 2;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int            clprim_in_back_event : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int         clprim_in_back_event_id : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         clprim_in_back_event_id : 6;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+        unsigned int                     ALWAYS_ZERO : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 28;
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clip_priority_available_vte_out_clip : 2;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clip_priority_available_vte_out_clip : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               sm0_clip_vert_cnt : 4;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int               sm0_current_state : 7;
+        unsigned int                    ALWAYS_ZERO0 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 5;
+        unsigned int               sm0_current_state : 7;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int               sm0_clip_vert_cnt : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   nan_kill_flag : 4;
+        unsigned int                position_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int           sx_pending_rd_aux_sel : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           sx_pending_rd_aux_sel : 1;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                position_address : 3;
+        unsigned int                   nan_kill_flag : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                param_cache_base : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                param_cache_base : 7;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         sx_sent : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                          sx_aux : 1;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                req_active_verts : 7;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int        sx_pending_fifo_contents : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int        sx_pending_fifo_contents : 3;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int                req_active_verts : 7;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                          sx_aux : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                         sx_sent : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    vertex_fifo_entriesavailable : 4;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int                   current_state : 2;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                   current_state : 2;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int    vertex_fifo_entriesavailable : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   su_cntl_state : 5;
+        unsigned int                     pmode_state : 6;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                       geom_busy : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       geom_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     pmode_state : 6;
+        unsigned int                   su_cntl_state : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort0_gated_17_4 : 14;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int              y_sort0_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort1_gated_17_4 : 14;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int              y_sort1_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort2_gated_17_4 : 14;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int              y_sort2_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort0_gated : 11;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                      type_gated : 3;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                       eop_gated : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                       eop_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                      type_gated : 3;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int           attr_indx_sort0_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort2_gated : 11;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int                  event_id_gated : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                  event_id_gated : 5;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int           attr_indx_sort2_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SC_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SC_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    pa_freeze_b1 : 1;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                                 : 17;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 17;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                    pa_freeze_b1 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        em_state : 3;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                                 : 21;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 21;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                        em_state : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rc_rtr_dly : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                                 : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int                        event_s1 : 1;
+        unsigned int                                 : 8;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 8;
+        unsigned int                        event_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                                 : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                      rc_rtr_dly : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       x_curr_s1 : 11;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                                 : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 9;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                       x_curr_s1 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        y_end_s1 : 14;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        x_end_s1 : 14;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      z_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                           state : 3;
+        unsigned int                   state_delayed : 3;
+        unsigned int                      data_valid : 1;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                      data_valid : 1;
+        unsigned int                   state_delayed : 3;
+        unsigned int                           state : 3;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                      z_ff_empty : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      event_flag : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                       fposition : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                           state : 2;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                                 : 6;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 6;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                           state : 2;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                      event_flag : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     sample_last : 1;
+        unsigned int                     sample_mask : 4;
+        unsigned int                        sample_y : 2;
+        unsigned int                        sample_x : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                                 : 3;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 3;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                       fposition : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                        sample_x : 2;
+        unsigned int                        sample_y : 2;
+        unsigned int                     sample_mask : 4;
+        unsigned int                     sample_last : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rb_sc_send : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                      mask_state : 2;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_ready : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int                      mask_ready : 1;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_state : 2;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                      rb_sc_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            combined_sample_mask : 16;
+        unsigned int                                 : 15;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 15;
+        unsigned int            combined_sample_mask : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            ez_sample_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_event : 1;
+        unsigned int                      next_state : 3;
+        unsigned int                           state : 3;
+        unsigned int                           stall : 1;
+        unsigned int                                 : 16;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 16;
+        unsigned int                           stall : 1;
+        unsigned int                           state : 3;
+        unsigned int                      next_state : 3;
+        unsigned int               packer_send_event : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int            ez_sample_data_ready : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SQ_iterator_free_buff : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                                 : 7;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 7;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int           SQ_iterator_free_buff : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GFX_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DRAW_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       PRIM_TYPE : 6;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                                 : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int                     NUM_INDICES : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     NUM_INDICES : 16;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                       PRIM_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_EVENT_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EVENT_TYPE : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      EVENT_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                       SWAP_MODE : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SWAP_MODE : 2;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                  FACENESS_RESET : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  FACENESS_RESET : 1;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MIN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_IMMED_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MAX_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MAX_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MAX_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MIN_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MIN_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_INDX_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INDX_OFFSET : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                     INDX_OFFSET : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VERTEX_REUSE_BLOCK_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_OUT_DEALLOC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEALLOC_DIST : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    DEALLOC_DIST : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MULTI_PRIM_IB_RESET_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESET_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      RESET_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            MISC : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                            MISC : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VTX_VECT_EJECT_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PRIM_COUNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                      PRIM_COUNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_LAST_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VGT_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                  VGT_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     te_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     te_grp_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                out_te_data_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_te_data_read : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      vgt_clk_en : 1;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                      vgt_clk_en : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int                      read_block : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int                   selected_data : 8;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                           gap_q : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int                     grp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     grp_trigger : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int                           gap_q : 1;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                   selected_data : 8;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int                      read_block : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     save_read_q : 1;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                     save_read_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            prim_side_indx_valid : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                       hold_prim : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int                       hold_prim : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int            prim_side_indx_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       null_terminate_vtx_vector : 1;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int                    new_packet_q : 1;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int                                 : 4;
+        unsigned int                     out_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 4;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int                    new_packet_q : 1;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int       null_terminate_vtx_vector : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   L2_INVALIDATE : 1;
+        unsigned int                                 : 17;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 11;
+        unsigned int                         TC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 11;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 17;
+        unsigned int                   L2_INVALIDATE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int                           SPARE : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 23;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP_TC_CLKGATE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TP_BUSY_EXTEND : 3;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                  TP_BUSY_EXTEND : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TPC_INPUT_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int                        TPC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int                  TPC_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        LOD_CNTL : 2;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                                 : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                    SQ_TP_WAKEUP : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SQ_TP_WAKEUP : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                                 : 3;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 1;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                        LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          UNUSED : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                          UNUSED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 BLEND_PRECISION : 1;
+        unsigned int                           SPARE : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 31;
+        unsigned int                 BLEND_PRECISION : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TP_INPUT_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                         TP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TP_BUSY : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                   TP_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      Q_LOD_CNTL : 2;
+        unsigned int                                 : 1;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int                                 : 1;
+        unsigned int                      Q_LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TT_MODE : 1;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                           SPARE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 30;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                         TT_MODE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 6;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TPC_full : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                         tca_rts : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                         tca_rts : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                        TPC_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                                 : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_FIFO_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        tp0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tpc_full : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                        tpc_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tp0_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_PROBE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ProbeFilter_stall : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int               ProbeFilter_stall : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_TPC_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                                 : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 18;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_CORE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       access512 : 1;
+        unsigned int                           tiled : 1;
+        unsigned int                                 : 2;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 1;
+        unsigned int                          format : 6;
+        unsigned int                                 : 2;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 3;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 3;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 2;
+        unsigned int                          format : 6;
+        unsigned int                                 : 1;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 2;
+        unsigned int                           tiled : 1;
+        unsigned int                       access512 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG1_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG2_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG3_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       left_done : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int                     update_left : 1;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int                    valid_left_q : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    valid_left_q : 1;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int                     update_left : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int                       left_done : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_WALKER_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                                 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                            busy : 1;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                            busy : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                                 : 3;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_PIPE0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     tc0_arb_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                            busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         valid_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                         valid_q : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                            busy : 1;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                     tc0_arb_rts : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_INPUT0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                                 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DEGAMMA_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTMUX_SCTARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 9;
+        unsigned int                          pstate : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int                                 : 3;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 6;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                                 : 6;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 3;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int                                 : 3;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                                 : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTC_ARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                        n0_stall : 1;
+        unsigned int                          pstate : 1;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int                 n0_dxt2_4_types : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 n0_dxt2_4_types : 1;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                        n0_stall : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 10;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_incoming_rtr : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                not_incoming_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int                                 : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             rl_sg_sector_format : 8;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                                 : 2;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int                            busy : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            busy : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 2;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int             rl_sg_sector_format : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       fifo_busy : 1;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                    write_enable : 1;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                                 : 2;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int                                 : 2;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                    write_enable : 1;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                       fifo_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_GPR_MANAGEMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     REG_DYNAMIC : 1;
+        unsigned int                                 : 3;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 3;
+        unsigned int                     REG_DYNAMIC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FLOW_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+        unsigned int                                 : 2;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 2;
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INST_STORE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   INST_BASE_PIX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_PIX : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_RESOURCE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_EO_RT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 EO_CONSTANTS_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                 EO_CONSTANTS_RT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  DB_ALUCST_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                        RESERVED : 2;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                                 : 1;
+        unsigned int                  DB_ALUCST_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TIMEBASE : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                           SPARE : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                        TIMEBASE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERCENT_BUSY : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    PERCENT_BUSY : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INPUT_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_THREAD_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                        RESERVED : 2;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_WATCHDOG_MASK : 1;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                PS_WATCHDOG_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_INPUT_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       VC_VSR_LD : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           PC_AS : 3;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                           PC_AS : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_VSR_LD : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_CONST_MGR_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TP_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           EX_TP : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           CF_TP : 4;
+        unsigned int                           IF_TP : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           IF_TP : 3;
+        unsigned int                           CF_TP : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           EX_TP : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_EXP_ALLOC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   POS_BUF_AVAIL : 4;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                   POS_BUF_AVAIL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PTR_BUFF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   END_OF_BUFFER : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                   END_OF_BUFFER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_VTX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VTX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_PIX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TB_STATUS_SEL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int                                 : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_PTR : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                     VS_DONE_PTR : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATUS_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VS_STATUS_REG : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VS_STATUS_REG : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_HEAD_PTR : 6;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int                            BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BUSY : 1;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                    PIX_HEAD_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VECTOR_RESULT : 6;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                   SCALAR_OPCODE : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SCALAR_OPCODE : 6;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int                   VECTOR_RESULT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                 CONST_0_REL_ABS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CONST_0_REL_ABS : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SRC_C_REG_PTR : 6;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_A_SEL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_A_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   SRC_C_REG_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_1 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 11;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 11;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 6;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                      RESERVED_0 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                        RESERVED : 22;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                        RESERVED : 22;
+        unsigned int                         LOOP_ID : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      RESERVED_1 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 17;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 1;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_2 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_2 : 2;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                      RESERVED_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 17;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                        RESERVED : 17;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 4;
+        unsigned int                        RESERVED : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 28;
+        unsigned int                            SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 8;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                            SIZE : 4;
+        unsigned int                      RESERVED_1 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 12;
+        unsigned int                            SIZE : 4;
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                      RESERVED_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 24;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                        RESERVED : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_Z : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_SEL_Z : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               USE_REG_GRADIENTS : 1;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int               USE_REG_GRADIENTS : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                         SRC_SEL : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SRC_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          STRIDE : 8;
+        unsigned int                                 : 8;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 7;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                                 : 7;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 8;
+        unsigned int                          STRIDE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TYPE : 1;
+        unsigned int                           STATE : 1;
+        unsigned int                    BASE_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BASE_ADDRESS : 30;
+        unsigned int                           STATE : 1;
+        unsigned int                            TYPE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ENDIAN_SWAP : 2;
+        unsigned int                   LIMIT_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   LIMIT_ADDRESS : 30;
+        unsigned int                     ENDIAN_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_PROGRAM_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      VS_CF_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INTERPOLATOR_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARAM_SHADE : 16;
+        unsigned int                SAMPLING_PATTERN : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                SAMPLING_PATTERN : 16;
+        unsigned int                     PARAM_SHADE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PROGRAM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                   GEN_INDEX_VTX : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   GEN_INDEX_VTX : 1;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      VS_NUM_REG : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_0 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_7 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PARAM_WRAP_7 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_0 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_8 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_15 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PARAM_WRAP_15 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                    PARAM_WRAP_8 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONTEXT_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                                 : 4;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RD_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RD_BASE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                         RD_BASE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DB_PROB_ON : 1;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 5;
+        unsigned int                   DB_PROB_COUNT : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DB_PROB_COUNT : 8;
+        unsigned int                                 : 5;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      DB_PROB_ON : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DB_ON_PIX : 1;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                                 : 6;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                                 : 6;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                       DB_ON_PIX : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_ARBITER_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_CLNT_AXI_ID_REUSE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          CPw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                                 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 17;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          CPw_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     AXI_READ_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                     AXI_READ_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           INDEX : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                           INDEX : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_HALT_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AXI_HALT : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                        AXI_HALT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                         MH_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CP_MH_send : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                   CP_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CP_MH_ad_31_5 : 27;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                      CP_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG06 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 CP_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CP_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG07 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CP_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                CP_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG08 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CP_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        CP_MH_be : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 3;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                 TC_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 TC_MH_addr_31_5 : 27;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_info : 25;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_info : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_TC_mcinfo : 25;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                    MH_TC_mcinfo : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ROQ_INFO : 25;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_INFO : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                 RB_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_addr_31_5 : 27;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RB_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                RB_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                RB_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                 PA_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_addr_31_5 : 27;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG19 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PA_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PA_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PA_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG22 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG23 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                    CTRL_ARC_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CTRL_ARC_PAD : 28;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG24 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                           REG_A : 14;
+        unsigned int                          REG_RE : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                          REG_RE : 1;
+        unsigned int                           REG_A : 14;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG25 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          REG_WD : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REG_WD : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG26 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       BRC_VALID : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BRC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG27 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  EFF2_FP_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                  EFF2_FP_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG28 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG29 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_4 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RECENT_d_4 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG30 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG31 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG32 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG33 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG34 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG35 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                      ROQ_ADDR_0 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_0 : 27;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG36 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                      ROQ_ADDR_1 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_1 : 27;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG37 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                      ROQ_ADDR_2 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_2 : 27;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG38 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                      ROQ_ADDR_3 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_3 : 27;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG39 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                      ROQ_ADDR_4 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_4 : 27;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG40 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                      ROQ_ADDR_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_5 : 27;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG41 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                      ROQ_ADDR_6 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_6 : 27;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG42 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                      ROQ_ADDR_7 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_7 : 27;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG43 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ARB_REG_WE_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                    ARB_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG44 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                       ARB_VAD_q : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ARB_VAD_q : 28;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG45 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          MMU_WE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         MMU_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_PAD : 28;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                          MMU_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG46 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG47 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG48 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG49 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG50 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG51 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG52 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int               client_behavior_q : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               client_behavior_q : 2;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG53 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    stage1_valid : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                    stage1_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG54 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                    stage2_valid : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                     TAG_valid_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TAG_valid_q : 16;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                    stage2_valid : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG55 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG0_VA : 13;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                         TAG0_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG56 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG2_VA : 13;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                         TAG2_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG57 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG4_VA : 13;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                         TAG4_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG58 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG6_VA : 13;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                         TAG6_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG59 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG8_VA : 13;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                         TAG8_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG60 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG10_VA : 13;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                        TAG10_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG61 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG12_VA : 13;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                        TAG12_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG62 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG14_VA : 13;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                        TAG14_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG63 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      MMU_ENABLE : 1;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                      MMU_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_VA_RANGE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                NUM_64KB_REGIONS : 12;
+        unsigned int                         VA_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         VA_BASE : 20;
+        unsigned int                NUM_64KB_REGIONS : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PT_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         PT_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         PT_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PAGE_FAULT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PAGE_FAULT : 1;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int                          REQ_VA : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REQ_VA : 20;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                      PAGE_FAULT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_TRAN_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                      TRAN_ERROR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      TRAN_ERROR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_INVALIDATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  INVALIDATE_ALL : 1;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                  INVALIDATE_ALL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                        MPU_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MPU_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_END {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         MPU_END : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MPU_END : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union WAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int                                 : 2;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 2;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_ISYNC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CMDFIFO_AVAIL : 5;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                      GUI_ACTIVE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      GUI_ACTIVE : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                                 : 2;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                   CMDFIFO_AVAIL : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DSPLY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RENDER_LATEST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RTL_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CHANGELIST : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      CHANGELIST : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PATCH_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PATCH_REVISION : 16;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                     CUSTOMER_ID : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     CUSTOMER_ID : 8;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                  PATCH_REVISION : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_AUXILIARY_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER0 : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     PARTNUMBER0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER1 : 4;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                     PARTNUMBER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DESIGNER1 : 4;
+        unsigned int                        REVISION : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        REVISION : 4;
+        unsigned int                       DESIGNER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int                                 : 1;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 1;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    READ_TIMEOUT : 8;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                    READ_TIMEOUT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SKEW_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SOFT_RESET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SOFT_RESET_CP : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                                 : 5;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 2;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                                 : 2;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 5;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_CP : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GC_SYS_IDLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int                                 : 2;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int                                 : 3;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int                                 : 3;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                                 : 2;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union NQWAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WAIT_GUI_IDLE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                   WAIT_GUI_IDLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_OUT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                                 : 3;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 3;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int                                 : 3;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 4;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int                                 : 6;
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+        unsigned int                                 : 6;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int                                 : 4;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 3;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_READ_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 13;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                      READ_ERROR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      READ_ERROR : 1;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                                 : 13;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_WAIT_IDLE_CLOCKS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_MASK : 1;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                  RDERR_INT_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_STAT : 1;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                  RDERR_INT_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   RDERR_INT_ACK : 1;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                   RDERR_INT_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MASTER_INT_SIGNAL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                   RBBM_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   RBBM_INT_STAT : 1;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNT1_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                 PERF_COUNT1_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PERF_COUNT1_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERF_COUNT1_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                         RB_BASE : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BASE : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RB_BUFSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 6;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 3;
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+        unsigned int                                 : 3;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 6;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BUFSZ : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_RPTR_SWAP : 2;
+        unsigned int                    RB_RPTR_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_RPTR_ADDR : 30;
+        unsigned int                    RB_RPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_RPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_RPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_WR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RB_RPTR_WR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                      RB_RPTR_WR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_WPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_WPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_DELAY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PRE_WRITE_TIMER : 28;
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+        unsigned int                 PRE_WRITE_TIMER : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_WPTR_SWAP : 2;
+        unsigned int                    RB_WPTR_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_WPTR_BASE : 30;
+        unsigned int                    RB_WPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB1_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB1_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB1_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB1_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB2_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB2_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB2_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB2_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                         ST_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         ST_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        ST_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        ST_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_QUEUE_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CSQ_IB1_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB1_START : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CSQ_CNT_RING : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                    CSQ_CNT_RING : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STQ_CNT_ST : 7;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                      STQ_CNT_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MEQ_CNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                         MEQ_CNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_RB_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB1_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB2_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NON_PREFETCH_CNTRS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     IB1_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB1_COUNTER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_ST_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STQ_RPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_RPTR_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MEQ_RPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_RPTR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MIU_TAG_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TAG_0_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                                 : 13;
+        unsigned int              INVALID_RETURN_TAG : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              INVALID_RETURN_TAG : 1;
+        unsigned int                                 : 13;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_0_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CMD_INDEX : 7;
+        unsigned int                                 : 9;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 9;
+        unsigned int                       CMD_INDEX : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CMD_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CMD_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ME_STATMUX : 16;
+        unsigned int                                 : 9;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   PROG_CNT_SIZE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PROG_CNT_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                                 : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 9;
+        unsigned int                      ME_STATMUX : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ME_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ME_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_WADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_WADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_WADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_RADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_RADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_RADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ME_RAM_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ME_RAM_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RDADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ME_RDADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ME_RDADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int                                 : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG4 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG4 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG5 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG5 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG6 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG6 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG7 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG7 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_UMSK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_UMSK : 8;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_UMSK : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                    SCRATCH_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_SWM : 1;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                     VS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_SWAP : 2;
+        unsigned int                    VS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_ADDR : 30;
+        unsigned int                    VS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PS_DONE_SWM : 1;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                     PS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_SWAP : 2;
+        unsigned int                    PS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_ADDR : 30;
+        unsigned int                    PS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CF_DONE_SRC : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                     CF_DONE_SRC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_SWAP : 2;
+        unsigned int                    CF_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_ADDR : 30;
+        unsigned int                    CF_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_SWAP : 2;
+        unsigned int                  NRT_WRITE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_ADDR : 30;
+        unsigned int                  NRT_WRITE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                     RB_INT_MASK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                     RB_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                      RB_INT_ACK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RB_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_ADDR : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      UCODE_ADDR : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_DATA : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      UCODE_DATA : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFMON_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFMON_STATE : 4;
+        unsigned int                                 : 4;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PERFMON_STATE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFCOUNT_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                   PERFCOUNT_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PERFCOUNT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    PERFCOUNT_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DISCARD_0 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_15 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_15 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_16 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_31 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_31 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_16 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_32 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_47 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_47 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_32 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_48 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_63 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_63 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_48 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               STATE_DEBUG_INDEX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int               STATE_DEBUG_INDEX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                STATE_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                STATE_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PROG_COUNTER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         COUNTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         COUNTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     MIU_WR_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                         CP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CP_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int                     MIU_WR_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_0_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_1_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_2_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_3_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_4_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_5_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_6_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_7_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_8_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_9_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_10_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_11_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_12_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_13_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_14_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_15_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_0 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_0 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_1 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_1 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_2 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_2 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_3 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_3 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_4 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_4 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_5 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_5 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_6 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_6 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_7 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_7 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SURFACE_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SURFACE_PITCH : 14;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                   SURFACE_PITCH : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    COLOR_FORMAT : 4;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      COLOR_BASE : 20;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_FORMAT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEPTH_FORMAT : 1;
+        unsigned int                                 : 11;
+        unsigned int                      DEPTH_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      DEPTH_BASE : 20;
+        unsigned int                                 : 11;
+        unsigned int                    DEPTH_FORMAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STENCILREF : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                      STENCILREF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ALPHA_REF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ALPHA_REF : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ALPHA_REF : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       WRITE_RED : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                       WRITE_RED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_RED {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BLEND_RED : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       BLEND_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_GREEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_GREEN : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_GREEN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_BLUE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      BLEND_BLUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      BLEND_BLUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_ALPHA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_ALPHA : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_ALPHA : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FOG_COLOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         FOG_RED : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                         FOG_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK_BF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   STENCILREF_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int                   STENCILREF_BF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTHCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  STENCIL_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                 STENCILZFAIL_BF : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 STENCILZFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  STENCIL_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLENDCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  COLOR_SRCBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                  COLOR_SRCBLEND : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLORCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ALPHA_FUNC : 3;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                                 : 7;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int                                 : 7;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int                      ALPHA_FUNC : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_MODECONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_MODE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                      EDRAM_MODE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_DEST_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COLOR_DEST_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 COLOR_DEST_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                  COPY_DEST_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  COPY_DEST_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PITCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COPY_DEST_PITCH : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                 COPY_DEST_PITCH : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                COPY_DEST_ENDIAN : 3;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_ENDIAN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PIXEL_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        OFFSET_X : 13;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                        OFFSET_X : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     DEPTH_CLEAR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEPTH_CLEAR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_CTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int                                 : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int                       RESERVED6 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       RESERVED6 : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                                 : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_EDRAM_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_SIZE : 4;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                                 : 8;
+        unsigned int                     EDRAM_RANGE : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     EDRAM_RANGE : 18;
+        unsigned int                                 : 8;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                      EDRAM_SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_RD_PORT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CRC_RD_ADVANCE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                  CRC_RD_ADVANCE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_TOTAL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TOTAL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TOTAL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZPASS_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZPASS_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZPASS_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 TILE_FIFO_COUNT : 4;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z_TILE_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    Z_TILE_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 TILE_FIFO_COUNT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ACCUM_VALID : 4;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int                     ACCUM_VALID : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int                                 : 19;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 19;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FLAG_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_SPARES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_ENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_MOREENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h
new file mode 100644
index 00000000000..10807b43ea4
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h
@@ -0,0 +1,4183 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_SHIFT_HEADER)
+#define _yamato_SHIFT_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT          0x00000000
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT           0x00000000
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT          0x00000001
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT           0x00000002
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT          0x00000003
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT           0x00000004
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT          0x00000005
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                  0x00000008
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                   0x00000009
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                  0x0000000a
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT             0x0000000b
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT               0x00000010
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT     0x00000012
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT          0x00000013
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT        0x00000014
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                0x00000015
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT              0x00000016
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT               0x00000017
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT               0x00000018
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT         0x00000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                  0x00000000
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                  0x00000001
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                  0x00000003
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                    0x00000000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT                     0x00000010
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                0x00000000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                0x00000010
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT                      0x00000000
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT                  0x00000005
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT              0x00000000
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT               0x00000001
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                    0x00000002
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT               0x00000003
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT    0x00000005
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT     0x00000008
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT             0x0000000f
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT     0x00000012
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT      0x00000013
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT          0x00000014
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT       0x00000015
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT       0x00000017
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT    0x00000019
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT      0x0000001d
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT        0x0000001e
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT       0x0000001f
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT        0x00000000
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT      0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT         0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT       0x00000000
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT        0x00000000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT        0x00000010
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT           0x00000000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT            0x0000000d
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK__SHIFT                      0x00000000
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT            0x00000000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT            0x00000010
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT       0x0000001c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT         0x0000001d
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT                  0x00000000
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT              0x00000008
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT          0x00000009
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                 0x0000000a
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT              0x00000000
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT               0x00000001
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT      0x00000007
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT         0x00000000
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT       0x00000000
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT     0x00000008
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                  0x0000001f
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT  0x00000000
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT   0x00000001
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT  0x00000002
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT   0x00000003
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT     0x0000000d
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT            0x00000014
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT    0x00000013
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT            0x00000018
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT           0x00000018
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT           0x00000008
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT           0x0000001a
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT           0x00000008
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT           0x00000001
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT           0x00000016
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT           0x0000001c
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT   0x00000000
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT           0x00000006
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT           0x0000000c
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT           0x00000012
+#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT        0x00000014
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT   0x0000001c
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT    0x0000001d
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT           0x0000000a
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT           0x00000013
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT            0x00000004
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT           0x00000002
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT           0x00000016
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT      0x00000000
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT     0x00000004
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT    0x0000000e
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT      0x00000014
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT           0x0000001b
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT           0x00000000
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT        0x00000004
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT           0x0000000a
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT            0x0000000d
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT            0x00000011
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT  0x00000013
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT       0x00000017
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT   0x0000001e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT   0x0000001f
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT            0x00000000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT          0x00000002
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT     0x00000004
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT      0x0000000b
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT         0x0000000c
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT                 0x00000014
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT            0x00000015
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT            0x00000017
+#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT        0x00000019
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT                 0x00000000
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT            0x00000001
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT                  0x00000002
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT         0x00000003
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT        0x00000009
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT            0x00000012
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT            0x00000016
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT   0x0000001b
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT    0x0000001c
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT            0x00000004
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT     0x00000005
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT            0x00000008
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT           0x0000000c
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT       0x0000000e
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT        0x0000000f
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT  0x00000012
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT   0x00000013
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT  0x00000015
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT            0x00000016
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT             0x00000000
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT               0x00000005
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT                 0x0000000b
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT               0x0000000c
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT         0x0000000d
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT               0x0000000e
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT                0x0000000f
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT              0x00000010
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT                 0x00000011
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT           0x0000000b
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT          0x0000000c
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT             0x0000000d
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT             0x00000010
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT        0x00000011
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT              0x00000014
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT        0x00000015
+#define SETUP_DEBUG_REG4__type_gated__SHIFT                0x00000017
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT                0x0000001a
+#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT          0x0000001b
+#define SETUP_DEBUG_REG4__event_gated__SHIFT               0x0000001c
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT                 0x0000001d
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT     0x0000000b
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT       0x00000016
+#define SETUP_DEBUG_REG5__event_id_gated__SHIFT            0x00000018
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1__SHIFT                    0x00000000
+#define SC_DEBUG_0__pa_sc_valid__SHIFT                     0x00000001
+#define SC_DEBUG_0__pa_sc_phase__SHIFT                     0x00000002
+#define SC_DEBUG_0__cntx_cnt__SHIFT                        0x00000005
+#define SC_DEBUG_0__decr_cntx_cnt__SHIFT                   0x0000000c
+#define SC_DEBUG_0__incr_cntx_cnt__SHIFT                   0x0000000d
+#define SC_DEBUG_0__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state__SHIFT                        0x00000000
+#define SC_DEBUG_1__em1_data_ready__SHIFT                  0x00000003
+#define SC_DEBUG_1__em2_data_ready__SHIFT                  0x00000004
+#define SC_DEBUG_1__move_em1_to_em2__SHIFT                 0x00000005
+#define SC_DEBUG_1__ef_data_ready__SHIFT                   0x00000006
+#define SC_DEBUG_1__ef_state__SHIFT                        0x00000007
+#define SC_DEBUG_1__pipe_valid__SHIFT                      0x00000009
+#define SC_DEBUG_1__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly__SHIFT                      0x00000000
+#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT            0x00000001
+#define SC_DEBUG_2__pipe_freeze_b__SHIFT                   0x00000003
+#define SC_DEBUG_2__prim_rts__SHIFT                        0x00000004
+#define SC_DEBUG_2__next_prim_rts_dly__SHIFT               0x00000005
+#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT               0x00000006
+#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT               0x00000007
+#define SC_DEBUG_2__stage0_rts__SHIFT                      0x00000008
+#define SC_DEBUG_2__phase_rts_dly__SHIFT                   0x00000009
+#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT              0x0000000f
+#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT              0x00000010
+#define SC_DEBUG_2__event_id_s1__SHIFT                     0x00000011
+#define SC_DEBUG_2__event_s1__SHIFT                        0x00000016
+#define SC_DEBUG_2__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1__SHIFT                       0x00000000
+#define SC_DEBUG_3__y_curr_s1__SHIFT                       0x0000000b
+#define SC_DEBUG_3__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_4__y_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_4__y_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_4__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_5__x_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_5__x_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_5__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty__SHIFT                      0x00000000
+#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT                 0x00000001
+#define SC_DEBUG_6__xy_ff_empty__SHIFT                     0x00000002
+#define SC_DEBUG_6__event_flag__SHIFT                      0x00000003
+#define SC_DEBUG_6__z_mask_needed__SHIFT                   0x00000004
+#define SC_DEBUG_6__state__SHIFT                           0x00000005
+#define SC_DEBUG_6__state_delayed__SHIFT                   0x00000008
+#define SC_DEBUG_6__data_valid__SHIFT                      0x0000000b
+#define SC_DEBUG_6__data_valid_d__SHIFT                    0x0000000c
+#define SC_DEBUG_6__tilex_delayed__SHIFT                   0x0000000d
+#define SC_DEBUG_6__tiley_delayed__SHIFT                   0x00000016
+#define SC_DEBUG_6__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag__SHIFT                      0x00000000
+#define SC_DEBUG_7__deallocate__SHIFT                      0x00000001
+#define SC_DEBUG_7__fposition__SHIFT                       0x00000004
+#define SC_DEBUG_7__sr_prim_we__SHIFT                      0x00000005
+#define SC_DEBUG_7__last_tile__SHIFT                       0x00000006
+#define SC_DEBUG_7__tile_ff_we__SHIFT                      0x00000007
+#define SC_DEBUG_7__qs_data_valid__SHIFT                   0x00000008
+#define SC_DEBUG_7__qs_q0_y__SHIFT                         0x00000009
+#define SC_DEBUG_7__qs_q0_x__SHIFT                         0x0000000b
+#define SC_DEBUG_7__qs_q0_valid__SHIFT                     0x0000000d
+#define SC_DEBUG_7__prim_ff_we__SHIFT                      0x0000000e
+#define SC_DEBUG_7__tile_ff_re__SHIFT                      0x0000000f
+#define SC_DEBUG_7__fw_prim_data_valid__SHIFT              0x00000010
+#define SC_DEBUG_7__last_quad_of_tile__SHIFT               0x00000011
+#define SC_DEBUG_7__first_quad_of_tile__SHIFT              0x00000012
+#define SC_DEBUG_7__first_quad_of_prim__SHIFT              0x00000013
+#define SC_DEBUG_7__new_prim__SHIFT                        0x00000014
+#define SC_DEBUG_7__load_new_tile_data__SHIFT              0x00000015
+#define SC_DEBUG_7__state__SHIFT                           0x00000016
+#define SC_DEBUG_7__fifos_ready__SHIFT                     0x00000018
+#define SC_DEBUG_7__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last__SHIFT                     0x00000000
+#define SC_DEBUG_8__sample_mask__SHIFT                     0x00000001
+#define SC_DEBUG_8__sample_y__SHIFT                        0x00000005
+#define SC_DEBUG_8__sample_x__SHIFT                        0x00000007
+#define SC_DEBUG_8__sample_send__SHIFT                     0x00000009
+#define SC_DEBUG_8__next_cycle__SHIFT                      0x0000000a
+#define SC_DEBUG_8__ez_sample_ff_full__SHIFT               0x0000000c
+#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT                  0x0000000d
+#define SC_DEBUG_8__num_samples__SHIFT                     0x0000000e
+#define SC_DEBUG_8__last_quad_of_tile__SHIFT               0x00000010
+#define SC_DEBUG_8__last_quad_of_prim__SHIFT               0x00000011
+#define SC_DEBUG_8__first_quad_of_prim__SHIFT              0x00000012
+#define SC_DEBUG_8__sample_we__SHIFT                       0x00000013
+#define SC_DEBUG_8__fposition__SHIFT                       0x00000014
+#define SC_DEBUG_8__event_id__SHIFT                        0x00000015
+#define SC_DEBUG_8__event_flag__SHIFT                      0x0000001a
+#define SC_DEBUG_8__fw_prim_data_valid__SHIFT              0x0000001b
+#define SC_DEBUG_8__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send__SHIFT                      0x00000000
+#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT                   0x00000001
+#define SC_DEBUG_9__fifo_data_ready__SHIFT                 0x00000005
+#define SC_DEBUG_9__early_z_enable__SHIFT                  0x00000006
+#define SC_DEBUG_9__mask_state__SHIFT                      0x00000007
+#define SC_DEBUG_9__next_ez_mask__SHIFT                    0x00000009
+#define SC_DEBUG_9__mask_ready__SHIFT                      0x00000019
+#define SC_DEBUG_9__drop_sample__SHIFT                     0x0000001a
+#define SC_DEBUG_9__fetch_new_sample_data__SHIFT           0x0000001b
+#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT        0x0000001c
+#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT       0x0000001d
+#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT         0x0000001e
+#define SC_DEBUG_9__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask__SHIFT           0x00000000
+#define SC_DEBUG_10__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready__SHIFT           0x00000000
+#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT      0x00000001
+#define SC_DEBUG_11__ez_prim_data_ready__SHIFT             0x00000002
+#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT        0x00000003
+#define SC_DEBUG_11__iterator_input_fz__SHIFT              0x00000004
+#define SC_DEBUG_11__packer_send_quads__SHIFT              0x00000005
+#define SC_DEBUG_11__packer_send_cmd__SHIFT                0x00000006
+#define SC_DEBUG_11__packer_send_event__SHIFT              0x00000007
+#define SC_DEBUG_11__next_state__SHIFT                     0x00000008
+#define SC_DEBUG_11__state__SHIFT                          0x0000000b
+#define SC_DEBUG_11__stall__SHIFT                          0x0000000e
+#define SC_DEBUG_11__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT          0x00000000
+#define SC_DEBUG_12__event_id__SHIFT                       0x00000001
+#define SC_DEBUG_12__event_flag__SHIFT                     0x00000006
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT        0x00000007
+#define SC_DEBUG_12__itercmdfifo_full__SHIFT               0x00000008
+#define SC_DEBUG_12__itercmdfifo_empty__SHIFT              0x00000009
+#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT        0x0000000a
+#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT           0x0000000b
+#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT          0x0000000c
+#define SC_DEBUG_12__iter_qdhit0__SHIFT                    0x0000000d
+#define SC_DEBUG_12__bc_use_centers_reg__SHIFT             0x0000000e
+#define SC_DEBUG_12__bc_output_xy_reg__SHIFT               0x0000000f
+#define SC_DEBUG_12__iter_phase_out__SHIFT                 0x00000010
+#define SC_DEBUG_12__iter_phase_reg__SHIFT                 0x00000012
+#define SC_DEBUG_12__iterator_SP_valid__SHIFT              0x00000014
+#define SC_DEBUG_12__eopv_reg__SHIFT                       0x00000015
+#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT                0x00000016
+#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT            0x00000017
+#define SC_DEBUG_12__trigger__SHIFT                        0x0000001f
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                0x00000000
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT               0x00000000
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT           0x00000006
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT    0x00000008
+#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT              0x0000000b
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                 0x0000000c
+#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT             0x0000000d
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT   0x0000000e
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT         0x0000000f
+#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT             0x00000010
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT             0x00000000
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT                     0x00000000
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_DMA_SIZE__SWAP_MODE__SHIFT                     0x0000001e
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT                 0x00000000
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT                0x0000001e
+#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT                0x0000001f
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                  0x00000000
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                  0x00000000
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                0x00000000
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT          0x00000000
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT    0x00000000
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT                           0x00000000
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT          0x00000000
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT           0x00000000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT           0x00000010
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT              0x00000000
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                   0x00000000
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT               0x00000001
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT           0x00000002
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT               0x00000003
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                0x00000004
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT               0x00000005
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                0x00000006
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT               0x00000007
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT          0x00000008
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy__SHIFT                 0x00000000
+#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT                 0x00000001
+#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT                 0x00000002
+#define VGT_DEBUG_REG0__dma_request_busy__SHIFT            0x00000003
+#define VGT_DEBUG_REG0__out_busy__SHIFT                    0x00000004
+#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT            0x00000005
+#define VGT_DEBUG_REG0__grp_busy__SHIFT                    0x00000006
+#define VGT_DEBUG_REG0__dma_busy__SHIFT                    0x00000007
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT       0x00000008
+#define VGT_DEBUG_REG0__rbiu_busy__SHIFT                   0x00000009
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT    0x0000000a
+#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT             0x0000000b
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT           0x0000000c
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT                    0x0000000d
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT     0x0000000e
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT        0x0000000f
+#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT               0x00000010
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read__SHIFT            0x00000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT           0x00000001
+#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT            0x00000002
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT           0x00000003
+#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT            0x00000004
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT           0x00000005
+#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT            0x00000006
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT           0x00000007
+#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT            0x00000008
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT           0x00000009
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT                 0x0000000a
+#define VGT_DEBUG_REG1__grp_te_valid__SHIFT                0x0000000b
+#define VGT_DEBUG_REG1__pt_grp_read__SHIFT                 0x0000000c
+#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT                0x0000000d
+#define VGT_DEBUG_REG1__vr_grp_read__SHIFT                 0x0000000e
+#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT                0x0000000f
+#define VGT_DEBUG_REG1__grp_dma_read__SHIFT                0x00000010
+#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT               0x00000011
+#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT            0x00000012
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT           0x00000013
+#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT                  0x00000014
+#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT                 0x00000015
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT           0x00000016
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT          0x00000017
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT           0x00000018
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT          0x00000019
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT           0x0000001a
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT          0x0000001b
+#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT                  0x0000001c
+#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT                 0x0000001d
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT              0x0000001e
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT                  0x00000000
+#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT            0x00000001
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT        0x00000000
+#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT           0x00000005
+#define VGT_DEBUG_REG6__input_data_valid__SHIFT            0x0000000a
+#define VGT_DEBUG_REG6__input_data_xfer__SHIFT             0x0000000b
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT      0x0000000c
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT      0x0000000d
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT  0x0000000e
+#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT      0x0000000f
+#define VGT_DEBUG_REG6__shifter_first_load__SHIFT          0x00000010
+#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT       0x00000013
+#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT             0x00000014
+#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT         0x00000015
+#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT        0x00000017
+#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT         0x00000018
+#define VGT_DEBUG_REG6__extract_vector__SHIFT              0x00000019
+#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT              0x0000001a
+#define VGT_DEBUG_REG6__destination_rtr__SHIFT             0x0000001b
+#define VGT_DEBUG_REG6__grp_trigger__SHIFT                 0x0000001c
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT          0x00000000
+#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT     0x00000010
+#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT        0x00000014
+#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG7__current_source_sel__SHIFT          0x0000001e
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel__SHIFT          0x00000000
+#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT            0x00000002
+#define VGT_DEBUG_REG8__input_data_cnt__SHIFT              0x00000007
+#define VGT_DEBUG_REG8__input_data_lsw__SHIFT              0x0000000c
+#define VGT_DEBUG_REG8__input_data_msw__SHIFT              0x00000011
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q__SHIFT               0x00000000
+#define VGT_DEBUG_REG9__next_stride_d__SHIFT               0x00000005
+#define VGT_DEBUG_REG9__current_shift_q__SHIFT             0x0000000a
+#define VGT_DEBUG_REG9__current_shift_d__SHIFT             0x0000000f
+#define VGT_DEBUG_REG9__current_stride_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG9__current_stride_d__SHIFT            0x00000019
+#define VGT_DEBUG_REG9__grp_trigger__SHIFT                 0x0000001e
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003
+#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT             0x00000004
+#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT        0x00000005
+#define VGT_DEBUG_REG10__bin_valid__SHIFT                  0x00000006
+#define VGT_DEBUG_REG10__read_block__SHIFT                 0x00000007
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT     0x00000008
+#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT          0x00000009
+#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG10__selected_data__SHIFT              0x0000000b
+#define VGT_DEBUG_REG10__mask_input_data__SHIFT            0x00000013
+#define VGT_DEBUG_REG10__gap_q__SHIFT                      0x0000001b
+#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT          0x0000001c
+#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT          0x0000001d
+#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT          0x0000001e
+#define VGT_DEBUG_REG10__grp_trigger__SHIFT                0x0000001f
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT       0x00000000
+#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT          0x00000005
+#define VGT_DEBUG_REG12__input_data_valid__SHIFT           0x0000000a
+#define VGT_DEBUG_REG12__input_data_xfer__SHIFT            0x0000000b
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT     0x0000000c
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT     0x0000000d
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e
+#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT     0x0000000f
+#define VGT_DEBUG_REG12__shifter_first_load__SHIFT         0x00000010
+#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT             0x00000011
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT      0x00000013
+#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT        0x00000015
+#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT       0x00000017
+#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT        0x00000018
+#define VGT_DEBUG_REG12__extract_vector__SHIFT             0x00000019
+#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT             0x0000001a
+#define VGT_DEBUG_REG12__destination_rtr__SHIFT            0x0000001b
+#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT               0x0000001c
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT         0x00000000
+#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT    0x00000010
+#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT       0x00000014
+#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT             0x00000018
+#define VGT_DEBUG_REG13__current_source_sel__SHIFT         0x0000001e
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel__SHIFT         0x00000000
+#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT           0x00000002
+#define VGT_DEBUG_REG14__input_data_cnt__SHIFT             0x00000007
+#define VGT_DEBUG_REG14__input_data_lsw__SHIFT             0x0000000c
+#define VGT_DEBUG_REG14__input_data_msw__SHIFT             0x00000011
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q__SHIFT              0x00000000
+#define VGT_DEBUG_REG15__next_stride_d__SHIFT              0x00000005
+#define VGT_DEBUG_REG15__current_shift_q__SHIFT            0x0000000a
+#define VGT_DEBUG_REG15__current_shift_d__SHIFT            0x0000000f
+#define VGT_DEBUG_REG15__current_stride_q__SHIFT           0x00000014
+#define VGT_DEBUG_REG15__current_stride_d__SHIFT           0x00000019
+#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT               0x0000001e
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT  0x00000000
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT   0x00000002
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT    0x00000003
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT   0x00000004
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT  0x00000005
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT   0x00000006
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT     0x00000007
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT         0x00000008
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT         0x00000009
+#define VGT_DEBUG_REG16__rst_last_bit__SHIFT               0x0000000a
+#define VGT_DEBUG_REG16__current_state_q__SHIFT            0x0000000b
+#define VGT_DEBUG_REG16__old_state_q__SHIFT                0x0000000c
+#define VGT_DEBUG_REG16__old_state_en__SHIFT               0x0000000d
+#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT            0x0000000e
+#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT             0x0000000f
+#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT           0x00000010
+#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT           0x00000011
+#define VGT_DEBUG_REG16__load_empty_reg__SHIFT             0x00000012
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT   0x00000013
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT   0x0000001e
+#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q__SHIFT                0x00000000
+#define VGT_DEBUG_REG17__extend_read_q__SHIFT              0x00000001
+#define VGT_DEBUG_REG17__grp_indx_size__SHIFT              0x00000002
+#define VGT_DEBUG_REG17__cull_prim_true__SHIFT             0x00000004
+#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT               0x00000005
+#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT               0x00000006
+#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT          0x00000007
+#define VGT_DEBUG_REG17__check_second_reg__SHIFT           0x00000008
+#define VGT_DEBUG_REG17__check_first_reg__SHIFT            0x00000009
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT    0x0000000b
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT    0x0000000c
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT     0x0000000d
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT     0x0000000e
+#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT            0x0000000f
+#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT            0x00000010
+#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT    0x00000000
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT    0x00000006
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d
+#define VGT_DEBUG_REG18__dma_mem_full__SHIFT               0x0000000f
+#define VGT_DEBUG_REG18__dma_ram_re__SHIFT                 0x00000010
+#define VGT_DEBUG_REG18__dma_ram_we__SHIFT                 0x00000011
+#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT              0x00000012
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT       0x00000013
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT       0x00000014
+#define VGT_DEBUG_REG18__bin_mem_full__SHIFT               0x00000015
+#define VGT_DEBUG_REG18__bin_ram_we__SHIFT                 0x00000016
+#define VGT_DEBUG_REG18__bin_ram_re__SHIFT                 0x00000017
+#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT              0x00000018
+#define VGT_DEBUG_REG18__start_bin_req__SHIFT              0x00000019
+#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT        0x0000001a
+#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT               0x0000001b
+#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT         0x0000001c
+#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT         0x0000001d
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT       0x00000000
+#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT       0x00000001
+#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT          0x00000002
+#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT          0x00000003
+#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT        0x00000004
+#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT          0x00000005
+#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT             0x00000006
+#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT             0x00000007
+#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT           0x00000008
+#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT          0x00000009
+#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT             0x0000000a
+#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT             0x0000000b
+#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT           0x0000000c
+#define VGT_DEBUG_REG20__hold_prim__SHIFT                  0x0000000d
+#define VGT_DEBUG_REG20__sent_cnt__SHIFT                   0x0000000e
+#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT        0x00000012
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT       0x00000013
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT       0x00000014
+#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT   0x00000015
+#define VGT_DEBUG_REG20__out_trigger__SHIFT                0x0000001a
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT  0x00000000
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001
+#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT            0x00000004
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT    0x00000007
+#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT    0x0000000e
+#define VGT_DEBUG_REG21__new_packet_q__SHIFT               0x00000012
+#define VGT_DEBUG_REG21__new_allocate_q__SHIFT             0x00000013
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT    0x00000014
+#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT       0x00000016
+#define VGT_DEBUG_REG21__insert_null_prim__SHIFT           0x00000017
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT      0x00000018
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT      0x00000019
+#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT       0x0000001a
+#define VGT_DEBUG_REG21__out_trigger__SHIFT                0x0000001f
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC__SHIFT                        0x00000000
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC__SHIFT                        0x00000000
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT             0x00000000
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT               0x00000000
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT              0x00000012
+#define TC_CNTL_STATUS__TC_BUSY__SHIFT                     0x0000001f
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT               0x00000008
+#define TCM_CHICKEN__SPARE__SHIFT                          0x00000009
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT          0x00000000
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT          0x00000003
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT             0x00000000
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT           0x00000001
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT        0x00000002
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT        0x00000003
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT       0x00000004
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT         0x00000005
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT            0x00000006
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT      0x00000008
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT        0x00000009
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT           0x0000000a
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT           0x0000000c
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT        0x0000000d
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT          0x0000000e
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT             0x0000000f
+#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT                  0x00000010
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT            0x00000011
+#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT                  0x00000013
+#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT                  0x00000014
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT               0x00000015
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT             0x00000016
+#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT                  0x00000017
+#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT                  0x00000018
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT               0x00000019
+#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT                  0x0000001b
+#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT                  0x0000001c
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT          0x0000001d
+#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT                  0x0000001e
+#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT                   0x0000001f
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL__SHIFT                        0x00000000
+#define TPC_DEBUG0__IC_CTR__SHIFT                          0x00000002
+#define TPC_DEBUG0__WALKER_CNTL__SHIFT                     0x00000004
+#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT                    0x00000008
+#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT             0x0000000c
+#define TPC_DEBUG0__WALKER_STATE__SHIFT                    0x00000010
+#define TPC_DEBUG0__ALIGNER_STATE__SHIFT                   0x0000001a
+#define TPC_DEBUG0__REG_CLK_EN__SHIFT                      0x0000001d
+#define TPC_DEBUG0__TPC_CLK_EN__SHIFT                      0x0000001e
+#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT                    0x0000001f
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED__SHIFT                          0x00000000
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION__SHIFT                0x00000000
+#define TPC_CHICKEN__SPARE__SHIFT                          0x00000001
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT              0x00000000
+#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT                0x00000001
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT           0x00000002
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT               0x00000003
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT         0x00000004
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT            0x00000005
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT            0x00000006
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT            0x00000007
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT              0x00000008
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT           0x00000009
+#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT                 0x0000000a
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT            0x0000000b
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT              0x0000000c
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT           0x0000000d
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT             0x0000000e
+#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT                  0x00000010
+#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT                  0x00000011
+#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT                  0x00000012
+#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT                  0x00000013
+#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT                  0x00000014
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT               0x00000015
+#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT                  0x00000016
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT               0x00000017
+#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT                  0x00000018
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT               0x00000019
+#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT                  0x0000001a
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT               0x0000001b
+#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT                  0x0000001c
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT             0x0000001d
+#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT                  0x0000001e
+#define TP0_CNTL_STATUS__TP_BUSY__SHIFT                    0x0000001f
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL__SHIFT                       0x00000000
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT                   0x00000003
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT             0x00000004
+#define TP0_DEBUG__REG_CLK_EN__SHIFT                       0x00000015
+#define TP0_DEBUG__PERF_CLK_EN__SHIFT                      0x00000016
+#define TP0_DEBUG__TP_CLK_EN__SHIFT                        0x00000017
+#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT                    0x00000018
+#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT                   0x0000001c
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE__SHIFT                        0x00000000
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT            0x00000001
+#define TP0_CHICKEN__SPARE__SHIFT                          0x00000002
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr__SHIFT                    0x00000006
+#define TCF_DEBUG__TC_MH_send__SHIFT                       0x00000007
+#define TCF_DEBUG__not_FG0_rtr__SHIFT                      0x00000008
+#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT                  0x0000000c
+#define TCF_DEBUG__TCB_ff_stall__SHIFT                     0x0000000d
+#define TCF_DEBUG__TCB_miss_stall__SHIFT                   0x0000000e
+#define TCF_DEBUG__TCA_TCB_stall__SHIFT                    0x0000000f
+#define TCF_DEBUG__PF0_stall__SHIFT                        0x00000010
+#define TCF_DEBUG__TP0_full__SHIFT                         0x00000014
+#define TCF_DEBUG__TPC_full__SHIFT                         0x00000018
+#define TCF_DEBUG__not_TPC_rtr__SHIFT                      0x00000019
+#define TCF_DEBUG__tca_state_rts__SHIFT                    0x0000001a
+#define TCF_DEBUG__tca_rts__SHIFT                          0x0000001b
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full__SHIFT                    0x00000000
+#define TCA_FIFO_DEBUG__tpc_full__SHIFT                    0x00000004
+#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT               0x00000005
+#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT               0x00000006
+#define TCA_FIFO_DEBUG__FW_full__SHIFT                     0x00000007
+#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT                 0x00000008
+#define TCA_FIFO_DEBUG__FW_rts0__SHIFT                     0x0000000c
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT              0x00000010
+#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT                  0x00000011
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT          0x00000000
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts__SHIFT             0x0000000c
+#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT              0x0000000d
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512__SHIFT                   0x00000000
+#define TCB_CORE_DEBUG__tiled__SHIFT                       0x00000001
+#define TCB_CORE_DEBUG__opcode__SHIFT                      0x00000004
+#define TCB_CORE_DEBUG__format__SHIFT                      0x00000008
+#define TCB_CORE_DEBUG__sector_format__SHIFT               0x00000010
+#define TCB_CORE_DEBUG__sector_format512__SHIFT            0x00000018
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG0_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG0_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG1_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG1_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG2_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG2_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG3_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG3_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT   0x00000004
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT    0x00000006
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT   0x0000000b
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT   0x0000000c
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT            0x0000000f
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT      0x00000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT       0x00000002
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT    0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT             0x00000017
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT         0x00000018
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT          0x00000019
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT         0x0000001a
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT          0x0000001c
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT          0x0000001e
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty__SHIFT                     0x00000010
+#define TCD_INPUT0_DEBUG__full__SHIFT                      0x00000011
+#define TCD_INPUT0_DEBUG__valid_q1__SHIFT                  0x00000014
+#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT                    0x00000015
+#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT              0x00000017
+#define TCD_INPUT0_DEBUG__ip_send__SHIFT                   0x00000018
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT            0x00000019
+#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT                0x0000001a
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT      0x00000000
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT          0x00000002
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT      0x00000003
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT           0x00000004
+#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT               0x00000005
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT              0x00000006
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT             0x00000009
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT         0x0000000a
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT           0x0000000b
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT  0x00000014
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT   0x0000001c
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT      0x0000001d
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT                0x00000004
+#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT                  0x00000005
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT    0x00000006
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT          0x00000007
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT       0x00000009
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT    0x0000000c
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT       0x00000012
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT         0x0000001e
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT         0x0000001f
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT   0x0000000a
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT   0x0000000b
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT         0x00000011
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT       0x00000012
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT          0x00000013
+#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT          0x0000001f
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT          0x00000005
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT           0x00000006
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT       0x00000007
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT       0x00000000
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT       0x00000008
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT                 0x00000009
+#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT                 0x0000000a
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT      0x0000000b
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT                0x0000000c
+#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT                0x0000000d
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT           0x00000010
+#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT              0x00000018
+#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT            0x00000019
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT  0x0000001a
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT  0x0000001b
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT  0x0000001c
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT  0x0000001d
+#define TCO_QUAD0_DEBUG0__busy__SHIFT                      0x0000001e
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT                 0x00000000
+#define TCO_QUAD0_DEBUG1__empty__SHIFT                     0x00000001
+#define TCO_QUAD0_DEBUG1__full__SHIFT                      0x00000002
+#define TCO_QUAD0_DEBUG1__write_enable__SHIFT              0x00000003
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT            0x00000004
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT             0x0000000b
+#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT           0x00000014
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT         0x00000015
+#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT           0x00000016
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT        0x00000017
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT             0x00000018
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT             0x00000019
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT                 0x0000001a
+#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT                 0x0000001b
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT                0x0000001c
+#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT                0x0000001d
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT          0x0000001e
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT              0x00000000
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT             0x00000004
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT             0x0000000c
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT   0x00000000
+#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT                 0x00000004
+#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT                    0x00000008
+#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT                 0x0000000c
+#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT                   0x00000010
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT               0x00000011
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT          0x00000012
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT      0x00000015
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT     0x00000016
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT               0x00000017
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT               0x00000018
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT           0x00000019
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT    0x0000001b
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT      0x00000000
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT      0x00000010
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT   0x00000010
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT                   0x00000000
+#define SQ_EO_RT__EO_TSTATE_RT__SHIFT                      0x00000010
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT               0x00000000
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT               0x0000000c
+#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT                  0x00000014
+#define SQ_DEBUG_MISC__RESERVED__SHIFT                     0x00000015
+#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT               0x00000017
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT              0x00000019
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT              0x0000001a
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT              0x0000001b
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT              0x0000001c
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT            0x00000000
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT       0x00000008
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT      0x00000010
+#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT               0x00000018
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT      0x00000000
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT      0x00000000
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT        0x00000003
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT      0x00000004
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT        0x00000007
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT            0x00000008
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT     0x00000000
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT       0x00000003
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT     0x00000004
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT       0x00000007
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT           0x00000008
+#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT            0x00000012
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT               0x00000000
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT               0x00000001
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT          0x00000000
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT          0x00000001
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT                 0x00000000
+#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT                 0x00000001
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT               0x00000000
+#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT                0x00000003
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT               0x00000004
+#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT                 0x00000008
+#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT                   0x0000000c
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT           0x0000000f
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT             0x00000014
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT           0x00000005
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT           0x0000000d
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT                      0x00000000
+#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT                  0x00000003
+#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT                      0x00000004
+#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT                      0x00000008
+#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT                  0x0000000b
+#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT                     0x0000000c
+#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT                  0x0000000e
+#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT                      0x00000010
+#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT                  0x00000012
+#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT                     0x00000014
+#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT                  0x00000016
+#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT                     0x00000018
+#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT                  0x0000001a
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT                  0x0000001c
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT           0x00000000
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT         0x00000004
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT            0x0000000c
+#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT                0x0000000f
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT     0x00000010
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT            0x00000000
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT              0x00000001
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT          0x00000005
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT         0x00000006
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT              0x00000009
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT               0x0000000e
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT        0x0000000f
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT                 0x00000010
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT             0x00000011
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT   0x0000001d
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT           0x00000000
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT               0x00000004
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT               0x00000008
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT        0x0000000c
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT         0x00000010
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT            0x00000014
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT                   0x00000015
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT              0x00000000
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT   0x00000000
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT     0x00000000
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT             0x00000000
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT                 0x00000006
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT                 0x0000000c
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT        0x00000013
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT          0x00000019
+#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT                     0x0000001f
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT        0x00000006
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT  0x00000007
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT        0x0000000e
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT           0x0000000f
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT        0x00000010
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT        0x00000014
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT          0x00000018
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT          0x00000019
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT         0x0000001a
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT       0x00000000
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT       0x00000002
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT       0x00000004
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT       0x00000006
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT       0x00000008
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT       0x0000000c
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT       0x0000000e
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT       0x00000010
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT       0x00000012
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT       0x00000014
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT       0x00000016
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT         0x00000019
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT           0x0000001b
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT       0x0000001e
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT       0x0000001f
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT          0x00000006
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT         0x00000007
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT          0x0000000e
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT         0x00000010
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT          0x00000016
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT         0x00000017
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT             0x0000001d
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT             0x0000001e
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT          0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT             0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT             0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT       0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT     0x00000013
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT       0x00000014
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT     0x00000015
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT       0x00000016
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT     0x00000017
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT       0x00000018
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT     0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT       0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT     0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT         0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT         0x0000001e
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT         0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT         0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT         0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT         0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT          0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT             0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT       0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT     0x00000003
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT       0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT     0x00000005
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT       0x00000006
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT     0x00000007
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT       0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT     0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT     0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT         0x0000000d
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT         0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT         0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT         0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT        0x0000000a
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT        0x00000015
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT        0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT        0x0000001a
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT          0x00000005
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT    0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT    0x0000000d
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT    0x0000000f
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT    0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT     0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT     0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT  0x0000000b
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT        0x0000000c
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT    0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT    0x0000001d
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT    0x0000001e
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT      0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT     0x00000012
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT  0x0000001b
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT        0x0000001c
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT         0x00000004
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT        0x00000008
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT    0x00000009
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT       0x0000000b
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT           0x0000000c
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT             0x00000010
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT       0x00000014
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT        0x00000018
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT    0x00000019
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT       0x0000001b
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT           0x0000001c
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT   0x00000013
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT    0x00000019
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT          0x0000001a
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT          0x0000001c
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT          0x0000001e
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT         0x00000010
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT       0x00000012
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT   0x00000015
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT     0x00000018
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT       0x0000001c
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT        0x0000001d
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT  0x00000000
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT    0x00000001
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT           0x00000002
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT             0x00000009
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT           0x00000010
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT           0x00000015
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT           0x0000001a
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT        0x00000013
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT    0x00000019
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT            0x0000001e
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT    0x0000000c
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT     0x0000000d
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT        0x00000010
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT     0x00000017
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT             0x00000010
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED__SHIFT                          0x00000000
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN__SHIFT                        0x00000000
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE__SHIFT                         0x00000000
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA__SHIFT                        0x00000000
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE__SHIFT                           0x00000000
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT                  0x00000000
+#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT                 0x00000001
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT          0x00000002
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT           0x00000000
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT         0x00000002
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE__SHIFT                       0x00000000
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE__SHIFT                       0x00000000
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT               0x00000000
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT               0x00000008
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT               0x00000010
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT               0x00000018
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT                   0x00000000
+#define SQ_CF_LOOP__CF_LOOP_START__SHIFT                   0x00000008
+#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT                    0x00000010
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED__SHIFT                       0x00000000
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN__SHIFT                     0x00000000
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE__SHIFT                      0x00000000
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA__SHIFT                     0x00000000
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE__SHIFT                        0x00000000
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT            0x00000000
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT            0x00000008
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT            0x00000010
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT            0x00000018
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT                0x00000000
+#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT                0x00000008
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT                 0x00000010
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_VS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_PS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT              0x00000000
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT              0x0000000c
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT           0x00000000
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT      0x00000010
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT                 0x00000000
+#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT                 0x00000008
+#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT                0x00000010
+#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT                0x00000011
+#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT                  0x00000012
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT              0x00000013
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT            0x00000014
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT             0x00000018
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT             0x0000001b
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT              0x0000001f
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT                 0x00000000
+#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT                 0x00000004
+#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT                 0x00000008
+#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT                 0x0000000c
+#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT                 0x00000010
+#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT                 0x00000014
+#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT                 0x00000018
+#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT                 0x0000001c
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT                 0x00000000
+#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT                 0x00000004
+#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT                0x00000008
+#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT                0x0000000c
+#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT                0x00000010
+#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT                0x00000014
+#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT                0x00000018
+#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT                0x0000001c
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_VS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_PS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT         0x00000000
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT        0x00000001
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT             0x00000002
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT              0x00000008
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT            0x00000010
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT             0x00000011
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT               0x00000012
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE__SHIFT                      0x00000000
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT                 0x00000000
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT              0x00000004
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT               0x00000008
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT              0x00000018
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT                  0x00000000
+#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT                  0x00000001
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT              0x00000008
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT              0x00000010
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT          0x00000000
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT    0x00000006
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT            0x00000007
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT       0x00000008
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT           0x00000009
+#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT                0x0000000a
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT        0x0000000d
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT       0x0000000e
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT   0x0000000f
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT          0x00000010
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT           0x00000016
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT          0x00000017
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT           0x00000018
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT           0x00000019
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT           0x0000001a
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT                0x00000000
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT             0x00000003
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT                0x00000004
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT             0x00000007
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT               0x00000008
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT             0x0000000b
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT                0x0000000c
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT           0x00000000
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT          0x00000001
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT           0x00000002
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT         0x00000000
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT        0x00000001
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT         0x00000002
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT          0x00000000
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT         0x00000001
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT          0x00000002
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID__SHIFT                   0x00000000
+#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT                0x00000003
+#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT                  0x00000004
+#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT               0x00000007
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX__SHIFT                        0x00000000
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA__SHIFT                         0x00000000
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT               0x00000000
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY__SHIFT                     0x00000000
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT           0x00000001
+#define MH_DEBUG_REG00__CP_REQUEST__SHIFT                  0x00000002
+#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT                 0x00000003
+#define MH_DEBUG_REG00__TC_REQUEST__SHIFT                  0x00000004
+#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT                0x00000005
+#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT                 0x00000006
+#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT                   0x00000007
+#define MH_DEBUG_REG00__TCD_FULL__SHIFT                    0x00000008
+#define MH_DEBUG_REG00__RB_REQUEST__SHIFT                  0x00000009
+#define MH_DEBUG_REG00__PA_REQUEST__SHIFT                  0x0000000a
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT             0x0000000b
+#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT                   0x0000000c
+#define MH_DEBUG_REG00__ARQ_FULL__SHIFT                    0x0000000d
+#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT                   0x0000000e
+#define MH_DEBUG_REG00__WDB_FULL__SHIFT                    0x0000000f
+#define MH_DEBUG_REG00__AXI_AVALID__SHIFT                  0x00000010
+#define MH_DEBUG_REG00__AXI_AREADY__SHIFT                  0x00000011
+#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT                 0x00000012
+#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT                 0x00000013
+#define MH_DEBUG_REG00__AXI_WVALID__SHIFT                  0x00000014
+#define MH_DEBUG_REG00__AXI_WREADY__SHIFT                  0x00000015
+#define MH_DEBUG_REG00__AXI_RVALID__SHIFT                  0x00000016
+#define MH_DEBUG_REG00__AXI_RREADY__SHIFT                  0x00000017
+#define MH_DEBUG_REG00__AXI_BVALID__SHIFT                  0x00000018
+#define MH_DEBUG_REG00__AXI_BREADY__SHIFT                  0x00000019
+#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT                0x0000001a
+#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT                0x0000001b
+#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT                 0x0000001c
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q__SHIFT                   0x00000000
+#define MH_DEBUG_REG01__CP_RTR_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT                  0x00000002
+#define MH_DEBUG_REG01__CP_TAG_q__SHIFT                    0x00000003
+#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT                   0x00000006
+#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT                  0x00000007
+#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG01__TC_SEND_q__SHIFT                   0x0000000a
+#define MH_DEBUG_REG01__TC_RTR_q__SHIFT                    0x0000000b
+#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT                   0x0000000c
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT                0x0000000e
+#define MH_DEBUG_REG01__TC_MH_written__SHIFT               0x0000000f
+#define MH_DEBUG_REG01__RB_SEND_q__SHIFT                   0x00000010
+#define MH_DEBUG_REG01__RB_RTR_q__SHIFT                    0x00000011
+#define MH_DEBUG_REG01__PA_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG01__PA_RTR_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT               0x00000003
+#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT                 0x00000004
+#define MH_DEBUG_REG02__RDC_RID__SHIFT                     0x00000007
+#define MH_DEBUG_REG02__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT            0x0000000c
+#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT            0x0000000d
+#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT            0x0000000e
+#define MH_DEBUG_REG02__BRC_BID__SHIFT                     0x0000000f
+#define MH_DEBUG_REG02__BRC_BRESP__SHIFT                   0x00000012
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT           0x00000000
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT          0x00000000
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG05__CP_MH_write__SHIFT                 0x00000001
+#define MH_DEBUG_REG05__CP_MH_tag__SHIFT                   0x00000002
+#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT               0x00000005
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be__SHIFT                    0x00000000
+#define MH_DEBUG_REG08__RB_MH_be__SHIFT                    0x00000008
+#define MH_DEBUG_REG08__PA_MH_be__SHIFT                    0x00000010
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG09__VGT_MH_send__SHIFT                 0x00000003
+#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT                0x00000004
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT              0x00000005
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG10__TC_MH_send__SHIFT                  0x00000002
+#define MH_DEBUG_REG10__TC_MH_mask__SHIFT                  0x00000003
+#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info__SHIFT                  0x00000000
+#define MH_DEBUG_REG11__TC_MH_send__SHIFT                  0x00000019
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT                0x00000000
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT           0x00000019
+#define MH_DEBUG_REG12__TC_MH_written__SHIFT               0x0000001a
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT                 0x00000002
+#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT                 0x00000003
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT            0x00000005
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT                 0x00000000
+#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT                 0x00000019
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG15__RB_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG18__PA_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG21__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG21__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG21__ARVALID_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG21__ARREADY_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG21__ARID_q__SHIFT                      0x0000000a
+#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT                 0x0000000d
+#define MH_DEBUG_REG21__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG21__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG21__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG21__RID_q__SHIFT                       0x00000012
+#define MH_DEBUG_REG21__WVALID_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG21__WREADY_q__SHIFT                    0x00000016
+#define MH_DEBUG_REG21__WLAST_q__SHIFT                     0x00000017
+#define MH_DEBUG_REG21__WID_q__SHIFT                       0x00000018
+#define MH_DEBUG_REG21__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG21__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG21__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG22__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG22__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG22__ARVALID_q__SHIFT                   0x00000007
+#define MH_DEBUG_REG22__ARREADY_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG22__ARID_q__SHIFT                      0x00000009
+#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT                 0x0000000c
+#define MH_DEBUG_REG22__WVALID_q__SHIFT                    0x0000000d
+#define MH_DEBUG_REG22__WREADY_q__SHIFT                    0x0000000e
+#define MH_DEBUG_REG22__WLAST_q__SHIFT                     0x0000000f
+#define MH_DEBUG_REG22__WID_q__SHIFT                       0x00000010
+#define MH_DEBUG_REG22__WSTRB_q__SHIFT                     0x00000013
+#define MH_DEBUG_REG22__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG22__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG22__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT                 0x00000001
+#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT                0x00000004
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG24__REG_A__SHIFT                       0x00000002
+#define MH_DEBUG_REG24__REG_RE__SHIFT                      0x00000010
+#define MH_DEBUG_REG24__REG_WE__SHIFT                      0x00000011
+#define MH_DEBUG_REG24__BLOCK_RS__SHIFT                    0x00000012
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD__SHIFT                      0x00000000
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT                0x00000000
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT        0x00000001
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT       0x00000002
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT     0x00000003
+#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT                 0x00000004
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT     0x00000005
+#define MH_DEBUG_REG26__CNT_q__SHIFT                       0x00000006
+#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT                0x0000000d
+#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT                   0x0000000e
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT               0x0000000f
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011
+#define MH_DEBUG_REG26__CP_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG26__CP_RTR_q__SHIFT                    0x00000013
+#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT                  0x00000014
+#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT               0x00000016
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT            0x00000017
+#define MH_DEBUG_REG26__RB_SEND_q__SHIFT                   0x00000018
+#define MH_DEBUG_REG26__RB_RTR_q__SHIFT                    0x00000019
+#define MH_DEBUG_REG26__PA_SEND_q__SHIFT                   0x0000001a
+#define MH_DEBUG_REG26__PA_RTR_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG26__RDC_VALID__SHIFT                   0x0000001c
+#define MH_DEBUG_REG26__RDC_RLAST__SHIFT                   0x0000001d
+#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT               0x0000001e
+#define MH_DEBUG_REG26__BRC_VALID__SHIFT                   0x0000001f
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT              0x00000000
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT         0x00000003
+#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT                 0x00000006
+#define MH_DEBUG_REG27__ARB_WINNER__SHIFT                  0x00000009
+#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT                0x0000000c
+#define MH_DEBUG_REG27__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG27__KILL_EFF1__SHIFT                   0x00000010
+#define MH_DEBUG_REG27__ARB_HOLD__SHIFT                    0x00000011
+#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT                0x00000013
+#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT               0x00000014
+#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT                0x00000015
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT           0x00000016
+#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT                0x00000017
+#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT                0x00000018
+#define MH_DEBUG_REG27__ARB_QUAL__SHIFT                    0x00000019
+#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT                 0x0000001a
+#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT                0x0000001b
+#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT                 0x0000001c
+#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT                 0x0000001d
+#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT              0x0000001e
+#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT                 0x00000000
+#define MH_DEBUG_REG28__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT                0x00000006
+#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT               0x00000007
+#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT                0x00000008
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT           0x00000009
+#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT                0x0000000a
+#define MH_DEBUG_REG28__ARB_QUAL__SHIFT                    0x0000000b
+#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT                 0x0000000c
+#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT                0x0000000d
+#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT                 0x0000000e
+#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT                 0x0000000f
+#define MH_DEBUG_REG28__EFF1_WIN__SHIFT                    0x00000010
+#define MH_DEBUG_REG28__KILL_EFF1__SHIFT                   0x00000011
+#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT              0x00000012
+#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT                 0x00000013
+#define MH_DEBUG_REG28__ARB_HOLD__SHIFT                    0x00000014
+#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT     0x00000016
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT         0x00000000
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT        0x00000003
+#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT              0x00000006
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT       0x00000009
+#define MH_DEBUG_REG29__ARB_HOLD__SHIFT                    0x0000000a
+#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT                   0x0000000b
+#define MH_DEBUG_REG29__CLNT_REQ__SHIFT                    0x0000000c
+#define MH_DEBUG_REG29__RECENT_d_0__SHIFT                  0x00000011
+#define MH_DEBUG_REG29__RECENT_d_1__SHIFT                  0x00000014
+#define MH_DEBUG_REG29__RECENT_d_2__SHIFT                  0x00000017
+#define MH_DEBUG_REG29__RECENT_d_3__SHIFT                  0x0000001a
+#define MH_DEBUG_REG29__RECENT_d_4__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT                 0x00000000
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT      0x00000001
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT        0x00000002
+#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT              0x00000003
+#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT                0x00000005
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT            0x00000009
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT               0x0000000a
+#define MH_DEBUG_REG30__TC_MH_written__SHIFT               0x0000000b
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT          0x0000000c
+#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT               0x00000013
+#define MH_DEBUG_REG30__WLAST_q__SHIFT                     0x00000014
+#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT                 0x00000015
+#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT                0x00000016
+#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT                0x00000019
+#define MH_DEBUG_REG30__CP_MH_write__SHIFT                 0x0000001a
+#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT                0x0000001b
+#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT                0x0000001c
+#define MH_DEBUG_REG30__ARB_WINNER__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT         0x00000000
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT                  0x00000008
+#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT                 0x00000010
+#define MH_DEBUG_REG32__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG32__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT                  0x00000008
+#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT                 0x00000010
+#define MH_DEBUG_REG33__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG33__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT           0x00000000
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT           0x00000008
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT       0x00000010
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT       0x00000018
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT                0x00000002
+#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT               0x00000003
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT           0x00000004
+#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT                  0x00000005
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT                0x00000002
+#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT               0x00000003
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT           0x00000004
+#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT                  0x00000005
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT                0x00000002
+#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT               0x00000003
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT           0x00000004
+#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT                  0x00000005
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT                0x00000002
+#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT               0x00000003
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT           0x00000004
+#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT                  0x00000005
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT                0x00000002
+#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT               0x00000003
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT           0x00000004
+#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT                  0x00000005
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT                0x00000002
+#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT               0x00000003
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT           0x00000004
+#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT                  0x00000005
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT                0x00000002
+#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT               0x00000003
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT           0x00000004
+#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT                  0x00000005
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT                0x00000002
+#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT               0x00000003
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT           0x00000004
+#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT                  0x00000005
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT                0x00000000
+#define MH_DEBUG_REG43__ARB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT             0x00000002
+#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT                   0x00000003
+#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT                 0x00000004
+#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT              0x00000005
+#define MH_DEBUG_REG43__MMU_RTR__SHIFT                     0x00000006
+#define MH_DEBUG_REG43__ARB_ID_q__SHIFT                    0x00000007
+#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT                 0x0000000a
+#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT                  0x0000000b
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT              0x0000000c
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT              0x0000000d
+#define MH_DEBUG_REG43__MMU_WE__SHIFT                      0x00000010
+#define MH_DEBUG_REG43__ARQ_RTR__SHIFT                     0x00000011
+#define MH_DEBUG_REG43__MMU_ID__SHIFT                      0x00000012
+#define MH_DEBUG_REG43__MMU_WRITE__SHIFT                   0x00000015
+#define MH_DEBUG_REG43__MMU_BLEN__SHIFT                    0x00000016
+#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT                 0x00000017
+#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT               0x00000018
+#define MH_DEBUG_REG43__WDB_WE__SHIFT                      0x00000019
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT              0x0000001a
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT              0x0000001b
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG44__ARB_ID_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT                   0x00000004
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG45__MMU_ID__SHIFT                      0x00000001
+#define MH_DEBUG_REG45__MMU_PAD__SHIFT                     0x00000004
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG46__WDB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT            0x00000002
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT              0x00000003
+#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG46__ARB_WLAST__SHIFT                   0x0000000c
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT              0x0000000d
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT                0x00000013
+#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT                 0x00000014
+#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT               0x00000017
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT               0x00000018
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT          0x00000000
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT         0x00000000
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT              0x00000000
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT             0x00000001
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT              0x00000002
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT              0x00000003
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT            0x00000004
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT           0x00000005
+#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT               0x00000006
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT           0x00000007
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG49__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG49__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG49__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG49__BVALID_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG49__BREADY_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT             0x00000003
+#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT               0x00000004
+#define MH_DEBUG_REG50__RDC_VALID__SHIFT                   0x00000005
+#define MH_DEBUG_REG50__RDC_RID__SHIFT                     0x00000006
+#define MH_DEBUG_REG50__RDC_RLAST__SHIFT                   0x00000009
+#define MH_DEBUG_REG50__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT            0x0000000c
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT           0x0000000d
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT            0x0000000e
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT     0x0000000f
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT             0x00000015
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT        0x00000016
+#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT                 0x0000001c
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT           0x00000000
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT      0x00000000
+#define MH_DEBUG_REG52__ARB_WE__SHIFT                      0x00000002
+#define MH_DEBUG_REG52__MMU_RTR__SHIFT                     0x00000003
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT     0x00000004
+#define MH_DEBUG_REG52__ARB_ID_q__SHIFT                    0x0000001a
+#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT                 0x0000001d
+#define MH_DEBUG_REG52__client_behavior_q__SHIFT           0x0000001e
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid__SHIFT                0x00000000
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT           0x00000001
+#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT             0x00000002
+#define MH_DEBUG_REG53__tag_match_q__SHIFT                 0x00000003
+#define MH_DEBUG_REG53__tag_miss_q__SHIFT                  0x00000004
+#define MH_DEBUG_REG53__va_in_range_q__SHIFT               0x00000005
+#define MH_DEBUG_REG53__MMU_MISS__SHIFT                    0x00000006
+#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT               0x00000007
+#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT              0x00000008
+#define MH_DEBUG_REG53__MMU_HIT__SHIFT                     0x00000009
+#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT                0x0000000a
+#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT               0x0000000b
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT      0x0000000c
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT       0x0000000d
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT   0x0000000e
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT    0x0000000f
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT             0x00000010
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR__SHIFT                     0x00000000
+#define MH_DEBUG_REG54__MMU_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT           0x00000002
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT            0x00000003
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT             0x00000004
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005
+#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT             0x00000006
+#define MH_DEBUG_REG54__stage1_valid__SHIFT                0x00000007
+#define MH_DEBUG_REG54__stage2_valid__SHIFT                0x00000008
+#define MH_DEBUG_REG54__client_behavior_q__SHIFT           0x00000009
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT           0x0000000b
+#define MH_DEBUG_REG54__tag_match_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG54__tag_miss_q__SHIFT                  0x0000000d
+#define MH_DEBUG_REG54__va_in_range_q__SHIFT               0x0000000e
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT        0x0000000f
+#define MH_DEBUG_REG54__TAG_valid_q__SHIFT                 0x00000010
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT               0x0000000d
+#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG55__TAG1_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT               0x0000001d
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT               0x0000000d
+#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG56__TAG3_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT               0x0000001d
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT               0x0000000d
+#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG57__TAG5_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT               0x0000001d
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT               0x0000000d
+#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG58__TAG7_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT               0x0000001d
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT               0x0000000d
+#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG59__TAG9_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT               0x0000001d
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT              0x0000000d
+#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG60__TAG11_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT              0x0000001d
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT              0x0000000d
+#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG61__TAG13_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT              0x0000001d
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT              0x0000000d
+#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG62__TAG15_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT              0x0000001d
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT                   0x00000000
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT            0x00000001
+#define MH_MMU_CONFIG__RESERVED1__SHIFT                    0x00000002
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT           0x00000004
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT           0x00000006
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT          0x00000008
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT          0x0000000a
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT          0x0000000c
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT          0x0000000e
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT          0x00000010
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT         0x00000012
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT         0x00000014
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT           0x00000016
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT           0x00000018
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT           0x00000000
+#define MH_MMU_VA_RANGE__VA_BASE__SHIFT                    0x0000000c
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE__SHIFT                     0x0000000c
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT               0x00000000
+#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT                  0x00000001
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT            0x00000002
+#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT                   0x00000004
+#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT                0x00000007
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT     0x00000009
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT    0x0000000a
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT   0x0000000b
+#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT                   0x0000000c
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT               0x00000005
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT           0x00000000
+#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT            0x00000001
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT                   0x0000000c
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END__SHIFT                     0x0000000c
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT                   0x00000001
+#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT                   0x00000002
+#define WAIT_UNTIL__WAIT_VSYNC__SHIFT                      0x00000003
+#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT                  0x00000004
+#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT                  0x00000005
+#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT                  0x00000006
+#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT                    0x0000000a
+#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT                    0x0000000e
+#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT                    0x0000000f
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT               0x00000010
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT               0x00000011
+#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT                 0x00000014
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT         0x00000004
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT    0x00000005
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT                  0x00000000
+#define RBBM_STATUS__TC_BUSY__SHIFT                        0x00000005
+#define RBBM_STATUS__HIRQ_PENDING__SHIFT                   0x00000008
+#define RBBM_STATUS__CPRQ_PENDING__SHIFT                   0x00000009
+#define RBBM_STATUS__CFRQ_PENDING__SHIFT                   0x0000000a
+#define RBBM_STATUS__PFRQ_PENDING__SHIFT                   0x0000000b
+#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT                0x0000000c
+#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT                   0x0000000e
+#define RBBM_STATUS__CP_NRT_BUSY__SHIFT                    0x00000010
+#define RBBM_STATUS__MH_BUSY__SHIFT                        0x00000012
+#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT              0x00000013
+#define RBBM_STATUS__SX_BUSY__SHIFT                        0x00000015
+#define RBBM_STATUS__TPC_BUSY__SHIFT                       0x00000016
+#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT                   0x00000018
+#define RBBM_STATUS__PA_BUSY__SHIFT                        0x00000019
+#define RBBM_STATUS__VGT_BUSY__SHIFT                       0x0000001a
+#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT                 0x0000001b
+#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT                  0x0000001c
+#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT                   0x0000001e
+#define RBBM_STATUS__GUI_ACTIVE__SHIFT                     0x0000001f
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT           0x00000000
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT           0x00000001
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT           0x00000002
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT             0x00000003
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT              0x00000004
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT              0x00000005
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT              0x00000006
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT                 0x00000007
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT                0x00000008
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT              0x0000000a
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT              0x0000000b
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT              0x0000000c
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT                 0x0000000d
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT                0x0000000e
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT              0x00000010
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT              0x00000014
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT              0x00000015
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT              0x00000016
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT                 0x00000017
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT                0x00000018
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT              0x0000001a
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT              0x0000001b
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT              0x0000001c
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT                 0x0000001d
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT                0x0000001e
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT       0x00000000
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT       0x00000008
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT       0x00000010
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT       0x00000018
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT                0x00000000
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT          0x00000000
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT         0x00000010
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT             0x00000018
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT             0x00000000
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT                 0x00000000
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT                 0x00000000
+#define RBBM_PERIPHID1__DESIGNER0__SHIFT                   0x00000004
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1__SHIFT                   0x00000000
+#define RBBM_PERIPHID2__REVISION__SHIFT                    0x00000004
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT         0x00000000
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT        0x00000002
+#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT                0x00000004
+#define RBBM_PERIPHID3__CONTINUATION__SHIFT                0x00000007
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT__SHIFT                     0x00000000
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT             0x00000008
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT          0x00000000
+#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT                  0x00000005
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT              0x00000000
+#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT              0x00000002
+#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT              0x00000003
+#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT              0x00000004
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT              0x00000005
+#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT              0x00000006
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT             0x0000000c
+#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT              0x0000000f
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT             0x00000010
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000001
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT      0x00000002
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT  0x00000003
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT   0x00000004
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000005
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT   0x00000008
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT      0x00000009
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT   0x00000014
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000015
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT    0x00000016
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000017
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT     0x00000019
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001a
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT      0x0000001b
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT   0x0000001c
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001d
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT  0x0000001e
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT   0x00000001
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT   0x00000002
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT    0x00000007
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT  0x00000008
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT  0x00000009
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT  0x0000000b
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT              0x00000000
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT           0x00000010
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT             0x00000018
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT                0x00000019
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT    0x0000001d
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT       0x0000001e
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT           0x0000001f
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT                 0x00000000
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT               0x00000000
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT             0x00000000
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT              0x00000008
+#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT                  0x0000000c
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT        0x00000010
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT         0x00000018
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT         0x0000001c
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR__SHIFT                      0x00000001
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT              0x00000002
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT           0x00000003
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT           0x00000004
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT       0x00000008
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT               0x00000010
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000011
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT   0x00000012
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000013
+#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT                  0x00000014
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT                 0x00000015
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT                  0x00000016
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT      0x00000017
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT             0x00000018
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT             0x0000001f
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT               0x00000002
+#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT             0x0000001e
+#define RBBM_READ_ERROR__READ_ERROR__SHIFT                 0x0000001f
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT               0x00000000
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT      0x00000001
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT            0x00000013
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT             0x00000000
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT    0x00000001
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT          0x00000013
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT                 0x00000000
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT        0x00000001
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT              0x00000013
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT              0x00000005
+#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT              0x0000001a
+#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT              0x0000001e
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT            0x0000001f
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT   0x00000000
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT        0x00000000
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT        0x00000000
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT                         0x00000005
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT                        0x00000000
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT                        0x00000008
+#define CP_RB_CNTL__BUF_SWAP__SHIFT                        0x00000010
+#define CP_RB_CNTL__RB_POLL_EN__SHIFT                      0x00000014
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                    0x0000001b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                  0x0000001f
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT               0x00000002
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT                         0x00000000
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                   0x00000000
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT                         0x00000000
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT           0x00000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT           0x0000001c
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT               0x00000002
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE__SHIFT                       0x00000002
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                     0x00000000
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE__SHIFT                       0x00000002
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                     0x00000000
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE__SHIFT                         0x00000002
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                       0x00000000
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT          0x00000000
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT          0x00000008
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT           0x00000010
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT                  0x00000010
+#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT                  0x00000018
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT                  0x00000000
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT                   0x00000008
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT                   0x00000010
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT                    0x00000000
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                       0x00000000
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT            0x00000000
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT            0x00000010
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT         0x00000000
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT         0x00000010
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT         0x00000000
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT         0x00000010
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT          0x00000000
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT          0x00000008
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT                 0x00000000
+#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT                 0x00000010
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                       0x00000000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                       0x00000010
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT                 0x00000000
+#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT                 0x00000001
+#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT                 0x00000002
+#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT                 0x00000003
+#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT                 0x00000004
+#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT                 0x00000005
+#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT                 0x00000006
+#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT                 0x00000007
+#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT                 0x00000008
+#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT                 0x00000009
+#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT                0x0000000a
+#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT                0x0000000b
+#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT                0x0000000c
+#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT                0x0000000d
+#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT                0x0000000e
+#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT                0x0000000f
+#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT                0x00000010
+#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT                0x00000011
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT         0x0000001f
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT                     0x00000000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                 0x00000010
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT                       0x00000000
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX__SHIFT                      0x00000000
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT          0x00000019
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT          0x0000001a
+#define CP_ME_CNTL__ME_HALT__SHIFT                         0x0000001c
+#define CP_ME_CNTL__ME_BUSY__SHIFT                         0x0000001d
+#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT                   0x0000001f
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT                 0x00000000
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                 0x00000000
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR__SHIFT                     0x00000000
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT           0x00000000
+#define CP_DEBUG__PREDICATE_DISABLE__SHIFT                 0x00000017
+#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT               0x00000018
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT           0x00000019
+#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT                0x0000001a
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT               0x0000001b
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT            0x0000001c
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT            0x0000001e
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT            0x0000001f
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT              0x00000000
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT              0x00000000
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT              0x00000000
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT              0x00000000
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT              0x00000000
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT              0x00000000
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT              0x00000000
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT              0x00000000
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT                  0x00000000
+#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT                  0x00000010
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT                  0x00000005
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT             0x00000000
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT              0x00000000
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT              0x00000002
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT              0x00000000
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK__SHIFT                    0x00000013
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT           0x00000017
+#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT              0x00000018
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT      0x00000019
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT        0x0000001a
+#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT                  0x0000001b
+#define CP_INT_CNTL__IB2_INT_MASK__SHIFT                   0x0000001d
+#define CP_INT_CNTL__IB1_INT_MASK__SHIFT                   0x0000001e
+#define CP_INT_CNTL__RB_INT_MASK__SHIFT                    0x0000001f
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT__SHIFT                  0x00000013
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT         0x00000017
+#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT            0x00000018
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT    0x00000019
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT      0x0000001a
+#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT                0x0000001b
+#define CP_INT_STATUS__IB2_INT_STAT__SHIFT                 0x0000001d
+#define CP_INT_STATUS__IB1_INT_STAT__SHIFT                 0x0000001e
+#define CP_INT_STATUS__RB_INT_STAT__SHIFT                  0x0000001f
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK__SHIFT                      0x00000013
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT             0x00000017
+#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT                0x00000018
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT        0x00000019
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT          0x0000001a
+#define CP_INT_ACK__IB_ERROR_ACK__SHIFT                    0x0000001b
+#define CP_INT_ACK__IB2_INT_ACK__SHIFT                     0x0000001d
+#define CP_INT_ACK__IB1_INT_ACK__SHIFT                     0x0000001e
+#define CP_INT_ACK__RB_INT_ACK__SHIFT                      0x0000001f
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT               0x00000000
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT               0x00000000
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT              0x00000000
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT        0x00000008
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT        0x00000000
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT             0x00000000
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT             0x00000000
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT                 0x00000000
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT                 0x00000000
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT             0x00000000
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT             0x00000000
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0__SHIFT                    0x00000000
+#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT                   0x00000001
+#define CP_NV_FLAGS_0__DISCARD_1__SHIFT                    0x00000002
+#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT                   0x00000003
+#define CP_NV_FLAGS_0__DISCARD_2__SHIFT                    0x00000004
+#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT                   0x00000005
+#define CP_NV_FLAGS_0__DISCARD_3__SHIFT                    0x00000006
+#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT                   0x00000007
+#define CP_NV_FLAGS_0__DISCARD_4__SHIFT                    0x00000008
+#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT                   0x00000009
+#define CP_NV_FLAGS_0__DISCARD_5__SHIFT                    0x0000000a
+#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT                   0x0000000b
+#define CP_NV_FLAGS_0__DISCARD_6__SHIFT                    0x0000000c
+#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT                   0x0000000d
+#define CP_NV_FLAGS_0__DISCARD_7__SHIFT                    0x0000000e
+#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT                   0x0000000f
+#define CP_NV_FLAGS_0__DISCARD_8__SHIFT                    0x00000010
+#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT                   0x00000011
+#define CP_NV_FLAGS_0__DISCARD_9__SHIFT                    0x00000012
+#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT                   0x00000013
+#define CP_NV_FLAGS_0__DISCARD_10__SHIFT                   0x00000014
+#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT                  0x00000015
+#define CP_NV_FLAGS_0__DISCARD_11__SHIFT                   0x00000016
+#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT                  0x00000017
+#define CP_NV_FLAGS_0__DISCARD_12__SHIFT                   0x00000018
+#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT                  0x00000019
+#define CP_NV_FLAGS_0__DISCARD_13__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_0__DISCARD_14__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_0__DISCARD_15__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16__SHIFT                   0x00000000
+#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT                  0x00000001
+#define CP_NV_FLAGS_1__DISCARD_17__SHIFT                   0x00000002
+#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT                  0x00000003
+#define CP_NV_FLAGS_1__DISCARD_18__SHIFT                   0x00000004
+#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT                  0x00000005
+#define CP_NV_FLAGS_1__DISCARD_19__SHIFT                   0x00000006
+#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT                  0x00000007
+#define CP_NV_FLAGS_1__DISCARD_20__SHIFT                   0x00000008
+#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT                  0x00000009
+#define CP_NV_FLAGS_1__DISCARD_21__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_1__DISCARD_22__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_1__DISCARD_23__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_1__DISCARD_24__SHIFT                   0x00000010
+#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT                  0x00000011
+#define CP_NV_FLAGS_1__DISCARD_25__SHIFT                   0x00000012
+#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT                  0x00000013
+#define CP_NV_FLAGS_1__DISCARD_26__SHIFT                   0x00000014
+#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT                  0x00000015
+#define CP_NV_FLAGS_1__DISCARD_27__SHIFT                   0x00000016
+#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT                  0x00000017
+#define CP_NV_FLAGS_1__DISCARD_28__SHIFT                   0x00000018
+#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT                  0x00000019
+#define CP_NV_FLAGS_1__DISCARD_29__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_1__DISCARD_30__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_1__DISCARD_31__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32__SHIFT                   0x00000000
+#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT                  0x00000001
+#define CP_NV_FLAGS_2__DISCARD_33__SHIFT                   0x00000002
+#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT                  0x00000003
+#define CP_NV_FLAGS_2__DISCARD_34__SHIFT                   0x00000004
+#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT                  0x00000005
+#define CP_NV_FLAGS_2__DISCARD_35__SHIFT                   0x00000006
+#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT                  0x00000007
+#define CP_NV_FLAGS_2__DISCARD_36__SHIFT                   0x00000008
+#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT                  0x00000009
+#define CP_NV_FLAGS_2__DISCARD_37__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_2__DISCARD_38__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_2__DISCARD_39__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_2__DISCARD_40__SHIFT                   0x00000010
+#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT                  0x00000011
+#define CP_NV_FLAGS_2__DISCARD_41__SHIFT                   0x00000012
+#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT                  0x00000013
+#define CP_NV_FLAGS_2__DISCARD_42__SHIFT                   0x00000014
+#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT                  0x00000015
+#define CP_NV_FLAGS_2__DISCARD_43__SHIFT                   0x00000016
+#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT                  0x00000017
+#define CP_NV_FLAGS_2__DISCARD_44__SHIFT                   0x00000018
+#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT                  0x00000019
+#define CP_NV_FLAGS_2__DISCARD_45__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_2__DISCARD_46__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_2__DISCARD_47__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48__SHIFT                   0x00000000
+#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT                  0x00000001
+#define CP_NV_FLAGS_3__DISCARD_49__SHIFT                   0x00000002
+#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT                  0x00000003
+#define CP_NV_FLAGS_3__DISCARD_50__SHIFT                   0x00000004
+#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT                  0x00000005
+#define CP_NV_FLAGS_3__DISCARD_51__SHIFT                   0x00000006
+#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT                  0x00000007
+#define CP_NV_FLAGS_3__DISCARD_52__SHIFT                   0x00000008
+#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT                  0x00000009
+#define CP_NV_FLAGS_3__DISCARD_53__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_3__DISCARD_54__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_3__DISCARD_55__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_3__DISCARD_56__SHIFT                   0x00000010
+#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT                  0x00000011
+#define CP_NV_FLAGS_3__DISCARD_57__SHIFT                   0x00000012
+#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT                  0x00000013
+#define CP_NV_FLAGS_3__DISCARD_58__SHIFT                   0x00000014
+#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT                  0x00000015
+#define CP_NV_FLAGS_3__DISCARD_59__SHIFT                   0x00000016
+#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT                  0x00000017
+#define CP_NV_FLAGS_3__DISCARD_60__SHIFT                   0x00000018
+#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT                  0x00000019
+#define CP_NV_FLAGS_3__DISCARD_61__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_3__DISCARD_62__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_3__DISCARD_63__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT                  0x0000001f
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT     0x00000000
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT       0x00000000
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER__SHIFT                    0x00000000
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY__SHIFT                        0x00000000
+#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT                    0x00000001
+#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT                 0x00000002
+#define CP_STAT__RBIU_BUSY__SHIFT                          0x00000003
+#define CP_STAT__RCIU_BUSY__SHIFT                          0x00000004
+#define CP_STAT__CSF_RING_BUSY__SHIFT                      0x00000005
+#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT                 0x00000006
+#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT                 0x00000007
+#define CP_STAT__CSF_ST_BUSY__SHIFT                        0x00000009
+#define CP_STAT__CSF_BUSY__SHIFT                           0x0000000a
+#define CP_STAT__RING_QUEUE_BUSY__SHIFT                    0x0000000b
+#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT               0x0000000c
+#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT               0x0000000d
+#define CP_STAT__ST_QUEUE_BUSY__SHIFT                      0x00000010
+#define CP_STAT__PFP_BUSY__SHIFT                           0x00000011
+#define CP_STAT__MEQ_RING_BUSY__SHIFT                      0x00000012
+#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT                 0x00000013
+#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT                 0x00000014
+#define CP_STAT__MIU_WC_STALL__SHIFT                       0x00000015
+#define CP_STAT__CP_NRT_BUSY__SHIFT                        0x00000016
+#define CP_STAT___3D_BUSY__SHIFT                           0x00000017
+#define CP_STAT__ME_BUSY__SHIFT                            0x0000001a
+#define CP_STAT__ME_WC_BUSY__SHIFT                         0x0000001d
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT            0x0000001e
+#define CP_STAT__CP_BUSY__SHIFT                            0x0000001f
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE__SHIFT                        0x00000000
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE__SHIFT                        0x00000000
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT         0x00000000
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT     0x00000008
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT           0x00000009
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT           0x0000000a
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT           0x0000000b
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT           0x0000000c
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT           0x0000000d
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT           0x0000000e
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT           0x0000000f
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT           0x00000010
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT         0x00000011
+#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT             0x00000019
+#define COHER_STATUS_PM4__STATUS__SHIFT                    0x0000001f
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE__SHIFT                       0x00000000
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE__SHIFT                       0x00000000
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT        0x00000000
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT    0x00000008
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT          0x00000009
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT          0x0000000a
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT          0x0000000b
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT          0x0000000c
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT          0x0000000d
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT          0x0000000e
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT          0x0000000f
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT          0x00000010
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT        0x00000011
+#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT            0x00000019
+#define COHER_STATUS_HOST__STATUS__SHIFT                   0x0000001f
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT              0x0000000c
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT              0x00000000
+#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT               0x0000000e
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT                 0x00000000
+#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT             0x00000004
+#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT                 0x00000006
+#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT                 0x00000007
+#define RB_COLOR_INFO__COLOR_SWAP__SHIFT                   0x00000009
+#define RB_COLOR_INFO__COLOR_BASE__SHIFT                   0x0000000c
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT                 0x00000000
+#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT                   0x0000000c
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF__SHIFT               0x00000000
+#define RB_STENCILREFMASK__STENCILMASK__SHIFT              0x00000008
+#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT         0x00000010
+#define RB_STENCILREFMASK__RESERVED0__SHIFT                0x00000018
+#define RB_STENCILREFMASK__RESERVED1__SHIFT                0x00000019
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF__SHIFT                     0x00000000
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED__SHIFT                    0x00000000
+#define RB_COLOR_MASK__WRITE_GREEN__SHIFT                  0x00000001
+#define RB_COLOR_MASK__WRITE_BLUE__SHIFT                   0x00000002
+#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT                  0x00000003
+#define RB_COLOR_MASK__RESERVED2__SHIFT                    0x00000004
+#define RB_COLOR_MASK__RESERVED3__SHIFT                    0x00000005
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED__SHIFT                     0x00000000
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT                 0x00000000
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT                   0x00000000
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                 0x00000000
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED__SHIFT                       0x00000000
+#define RB_FOG_COLOR__FOG_GREEN__SHIFT                     0x00000008
+#define RB_FOG_COLOR__FOG_BLUE__SHIFT                      0x00000010
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT         0x00000000
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT        0x00000008
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT   0x00000010
+#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT             0x00000018
+#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT             0x00000019
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT             0x00000000
+#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT                   0x00000001
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT             0x00000002
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT             0x00000003
+#define RB_DEPTHCONTROL__ZFUNC__SHIFT                      0x00000004
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT            0x00000007
+#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT                0x00000008
+#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT                0x0000000b
+#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT               0x0000000e
+#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT               0x00000011
+#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT             0x00000014
+#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT             0x00000017
+#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT            0x0000001a
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT            0x0000001d
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT             0x00000000
+#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT             0x00000005
+#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT            0x00000008
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT             0x00000010
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT             0x00000015
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT            0x00000018
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT         0x0000001d
+#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT                0x0000001e
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT                 0x00000000
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT          0x00000003
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT       0x00000004
+#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT              0x00000005
+#define RB_COLORCONTROL__FOG_ENABLE__SHIFT                 0x00000006
+#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT             0x00000007
+#define RB_COLORCONTROL__ROP_CODE__SHIFT                   0x00000008
+#define RB_COLORCONTROL__DITHER_MODE__SHIFT                0x0000000c
+#define RB_COLORCONTROL__DITHER_TYPE__SHIFT                0x0000000e
+#define RB_COLORCONTROL__PIXEL_FOG__SHIFT                  0x00000010
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT      0x00000018
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT      0x0000001a
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT      0x0000001c
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT      0x0000001e
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE__SHIFT                  0x00000000
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT         0x00000000
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT         0x00000000
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT         0x00000003
+#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT                 0x00000004
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT           0x0000000c
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT         0x00000000
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT         0x00000000
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT         0x00000003
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT         0x00000004
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT           0x00000008
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT    0x0000000a
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT    0x0000000c
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT      0x0000000e
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT    0x0000000f
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT     0x00000010
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT    0x00000011
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT         0x00000000
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT         0x0000000d
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                 0x00000000
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT     0x00000000
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT      0x00000001
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT     0x00000000
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT     0x00000000
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT         0x00000001
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT            0x00000003
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT    0x00000005
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT    0x00000006
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT           0x00000007
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT            0x00000008
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT            0x0000000e
+#define RB_BC_CONTROL__CRC_MODE__SHIFT                     0x0000000f
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT      0x00000010
+#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT                0x00000011
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT             0x00000012
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT    0x00000016
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT        0x00000017
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT    0x0000001b
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d
+#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT                   0x0000001e
+#define RB_BC_CONTROL__RESERVED6__SHIFT                    0x0000001f
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT                   0x00000000
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT           0x00000004
+#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT                  0x0000000e
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA__SHIFT                    0x00000000
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT              0x00000000
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK__SHIFT                       0x00000000
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT             0x00000000
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT             0x00000000
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT           0x00000000
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT           0x00000001
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT           0x00000002
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT           0x00000003
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT          0x00000004
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT          0x00000005
+#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT                   0x00000006
+#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT                   0x00000007
+#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT                   0x00000008
+#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT                   0x00000009
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT          0x0000000a
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT          0x0000000b
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT          0x0000000c
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT          0x0000000d
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT              0x0000000e
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT                   0x00000010
+#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT                   0x00000011
+#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT                   0x00000012
+#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT                   0x00000013
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT            0x00000014
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT            0x00000015
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT            0x00000016
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT            0x00000017
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT         0x00000018
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT         0x00000019
+#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT                   0x0000001a
+#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT                   0x0000001b
+#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT                  0x0000001c
+#define RB_DEBUG_0__C_REQ_FULL__SHIFT                      0x0000001d
+#define RB_DEBUG_0__C_MASK_FULL__SHIFT                     0x0000001e
+#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT                 0x0000001f
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT              0x00000000
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT              0x00000001
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT              0x00000002
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT              0x00000003
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT         0x00000004
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT         0x00000005
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT                  0x00000006
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT                  0x00000007
+#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT                  0x00000008
+#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT                  0x00000009
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT         0x0000000a
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT         0x0000000b
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT         0x0000000c
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT         0x0000000d
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT             0x0000000e
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT             0x0000000f
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT                  0x00000010
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT                  0x00000011
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT              0x00000012
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT              0x00000013
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT           0x00000014
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT           0x00000017
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT        0x00000018
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT        0x00000019
+#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT                  0x0000001a
+#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT                  0x0000001b
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT                 0x0000001c
+#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT                     0x0000001d
+#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT                0x0000001f
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT                 0x00000000
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT               0x00000004
+#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT                 0x0000000b
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT               0x0000000c
+#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT              0x0000000d
+#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT                 0x0000000e
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT              0x00000010
+#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT                    0x00000011
+#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT                    0x00000012
+#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT                     0x00000013
+#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT                     0x00000014
+#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT                     0x00000015
+#define RB_DEBUG_2__Z_TILE_FULL__SHIFT                     0x00000016
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT                0x00000017
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT             0x00000018
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT             0x00000019
+#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT                   0x0000001a
+#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT                   0x0000001b
+#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT                    0x0000001c
+#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT                    0x0000001d
+#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT                    0x0000001f
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID__SHIFT                     0x00000000
+#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT                  0x00000004
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT         0x00000008
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT           0x0000000e
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT             0x0000000f
+#define RB_DEBUG_3__SHD_FULL__SHIFT                        0x00000013
+#define RB_DEBUG_3__SHD_EMPTY__SHIFT                       0x00000014
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT            0x00000017
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT            0x00000018
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT                0x00000019
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT                0x0000001a
+#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT                 0x0000001b
+#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT                 0x0000001c
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT             0x00000000
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT             0x00000001
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT           0x00000002
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT           0x00000003
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT           0x00000004
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT          0x00000005
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT            0x00000006
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT           0x00000007
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT     0x00000008
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT             0x00000009
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT           0x00000000
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED__SHIFT                      0x00000000
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT   0x00000009
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h
new file mode 100644
index 00000000000..d6cc2fe9abd
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h
@@ -0,0 +1,52421 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_CP_FIDDLE_H)
+#define _CP_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * CP_RB_BASE struct
+ */
+
+#define CP_RB_BASE_RB_BASE_SIZE        27
+
+#define CP_RB_BASE_RB_BASE_SHIFT       5
+
+#define CP_RB_BASE_RB_BASE_MASK        0xffffffe0
+
+#define CP_RB_BASE_MASK \
+     (CP_RB_BASE_RB_BASE_MASK)
+
+#define CP_RB_BASE(rb_base) \
+     ((rb_base << CP_RB_BASE_RB_BASE_SHIFT))
+
+#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \
+     ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT)
+
+#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \
+     cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int                                : 5;
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+     } cp_rb_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+          unsigned int                                : 5;
+     } cp_rb_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+
+/*
+ * CP_RB_CNTL struct
+ */
+
+#define CP_RB_CNTL_RB_BUFSZ_SIZE       6
+#define CP_RB_CNTL_RB_BLKSZ_SIZE       6
+#define CP_RB_CNTL_BUF_SWAP_SIZE       2
+#define CP_RB_CNTL_RB_POLL_EN_SIZE     1
+#define CP_RB_CNTL_RB_NO_UPDATE_SIZE   1
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
+
+#define CP_RB_CNTL_RB_BUFSZ_SHIFT      0
+#define CP_RB_CNTL_RB_BLKSZ_SHIFT      8
+#define CP_RB_CNTL_BUF_SWAP_SHIFT      16
+#define CP_RB_CNTL_RB_POLL_EN_SHIFT    20
+#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT  27
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31
+
+#define CP_RB_CNTL_RB_BUFSZ_MASK       0x0000003f
+#define CP_RB_CNTL_RB_BLKSZ_MASK       0x00003f00
+#define CP_RB_CNTL_BUF_SWAP_MASK       0x00030000
+#define CP_RB_CNTL_RB_POLL_EN_MASK     0x00100000
+#define CP_RB_CNTL_RB_NO_UPDATE_MASK   0x08000000
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000
+
+#define CP_RB_CNTL_MASK \
+     (CP_RB_CNTL_RB_BUFSZ_MASK | \
+      CP_RB_CNTL_RB_BLKSZ_MASK | \
+      CP_RB_CNTL_BUF_SWAP_MASK | \
+      CP_RB_CNTL_RB_POLL_EN_MASK | \
+      CP_RB_CNTL_RB_NO_UPDATE_MASK | \
+      CP_RB_CNTL_RB_RPTR_WR_ENA_MASK)
+
+#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \
+     ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \
+      (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \
+      (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \
+      (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \
+      (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \
+      (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT))
+
+#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+     } cp_rb_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+     } cp_rb_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+
+/*
+ * CP_RB_RPTR_ADDR struct
+ */
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc
+
+#define CP_RB_RPTR_ADDR_MASK \
+     (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \
+      CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK)
+
+#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \
+     ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \
+      (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT))
+
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+
+/*
+ * CP_RB_RPTR struct
+ */
+
+#define CP_RB_RPTR_RB_RPTR_SIZE        20
+
+#define CP_RB_RPTR_RB_RPTR_SHIFT       0
+
+#define CP_RB_RPTR_RB_RPTR_MASK        0x000fffff
+
+#define CP_RB_RPTR_MASK \
+     (CP_RB_RPTR_RB_RPTR_MASK)
+
+#define CP_RB_RPTR(rb_rptr) \
+     ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT))
+
+#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \
+     ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \
+     cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+     } cp_rb_rptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+
+/*
+ * CP_RB_RPTR_WR struct
+ */
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE  20
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK  0x000fffff
+
+#define CP_RB_RPTR_WR_MASK \
+     (CP_RB_RPTR_WR_RB_RPTR_WR_MASK)
+
+#define CP_RB_RPTR_WR(rb_rptr_wr) \
+     ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT))
+
+#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \
+     ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \
+     cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_wr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+     } cp_rb_rptr_wr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+
+/*
+ * CP_RB_WPTR struct
+ */
+
+#define CP_RB_WPTR_RB_WPTR_SIZE        20
+
+#define CP_RB_WPTR_RB_WPTR_SHIFT       0
+
+#define CP_RB_WPTR_RB_WPTR_MASK        0x000fffff
+
+#define CP_RB_WPTR_MASK \
+     (CP_RB_WPTR_RB_WPTR_MASK)
+
+#define CP_RB_WPTR(rb_wptr) \
+     ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT))
+
+#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \
+     ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \
+     cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_wptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+     } cp_rb_wptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+
+/*
+ * CP_RB_WPTR_DELAY struct
+ */
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000
+
+#define CP_RB_WPTR_DELAY_MASK \
+     (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \
+      CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK)
+
+#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \
+     ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \
+      (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT))
+
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_delay_t f;
+} cp_rb_wptr_delay_u;
+
+
+/*
+ * CP_RB_WPTR_BASE struct
+ */
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc
+
+#define CP_RB_WPTR_BASE_MASK \
+     (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \
+      CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK)
+
+#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \
+     ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \
+      (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT))
+
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+     } cp_rb_wptr_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+     } cp_rb_wptr_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_base_t f;
+} cp_rb_wptr_base_u;
+
+
+/*
+ * CP_IB1_BASE struct
+ */
+
+#define CP_IB1_BASE_IB1_BASE_SIZE      30
+
+#define CP_IB1_BASE_IB1_BASE_SHIFT     2
+
+#define CP_IB1_BASE_IB1_BASE_MASK      0xfffffffc
+
+#define CP_IB1_BASE_MASK \
+     (CP_IB1_BASE_IB1_BASE_MASK)
+
+#define CP_IB1_BASE(ib1_base) \
+     ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT))
+
+#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \
+     ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \
+     cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int                                : 2;
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+     } cp_ib1_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib1_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_base_t f;
+} cp_ib1_base_u;
+
+
+/*
+ * CP_IB1_BUFSZ struct
+ */
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE    20
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT   0
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK    0x000fffff
+
+#define CP_IB1_BUFSZ_MASK \
+     (CP_IB1_BUFSZ_IB1_BUFSZ_MASK)
+
+#define CP_IB1_BUFSZ(ib1_bufsz) \
+     ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT))
+
+#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \
+     ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \
+     cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib1_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+     } cp_ib1_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_bufsz_t f;
+} cp_ib1_bufsz_u;
+
+
+/*
+ * CP_IB2_BASE struct
+ */
+
+#define CP_IB2_BASE_IB2_BASE_SIZE      30
+
+#define CP_IB2_BASE_IB2_BASE_SHIFT     2
+
+#define CP_IB2_BASE_IB2_BASE_MASK      0xfffffffc
+
+#define CP_IB2_BASE_MASK \
+     (CP_IB2_BASE_IB2_BASE_MASK)
+
+#define CP_IB2_BASE(ib2_base) \
+     ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT))
+
+#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \
+     ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \
+     cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int                                : 2;
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+     } cp_ib2_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib2_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_base_t f;
+} cp_ib2_base_u;
+
+
+/*
+ * CP_IB2_BUFSZ struct
+ */
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE    20
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT   0
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK    0x000fffff
+
+#define CP_IB2_BUFSZ_MASK \
+     (CP_IB2_BUFSZ_IB2_BUFSZ_MASK)
+
+#define CP_IB2_BUFSZ(ib2_bufsz) \
+     ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT))
+
+#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \
+     ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \
+     cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib2_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+     } cp_ib2_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_bufsz_t f;
+} cp_ib2_bufsz_u;
+
+
+/*
+ * CP_ST_BASE struct
+ */
+
+#define CP_ST_BASE_ST_BASE_SIZE        30
+
+#define CP_ST_BASE_ST_BASE_SHIFT       2
+
+#define CP_ST_BASE_ST_BASE_MASK        0xfffffffc
+
+#define CP_ST_BASE_MASK \
+     (CP_ST_BASE_ST_BASE_MASK)
+
+#define CP_ST_BASE(st_base) \
+     ((st_base << CP_ST_BASE_ST_BASE_SHIFT))
+
+#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \
+     ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT)
+
+#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \
+     cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int                                : 2;
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+     } cp_st_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_st_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_base_t f;
+} cp_st_base_u;
+
+
+/*
+ * CP_ST_BUFSZ struct
+ */
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SIZE      20
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT     0
+
+#define CP_ST_BUFSZ_ST_BUFSZ_MASK      0x000fffff
+
+#define CP_ST_BUFSZ_MASK \
+     (CP_ST_BUFSZ_ST_BUFSZ_MASK)
+
+#define CP_ST_BUFSZ(st_bufsz) \
+     ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT))
+
+#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \
+     ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \
+     cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_st_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+     } cp_st_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_bufsz_t f;
+} cp_st_bufsz_u;
+
+
+/*
+ * CP_QUEUE_THRESHOLDS struct
+ */
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000
+
+#define CP_QUEUE_THRESHOLDS_MASK \
+     (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK)
+
+#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \
+     ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \
+      (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \
+      (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT))
+
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 12;
+     } cp_queue_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int                                : 12;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+     } cp_queue_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_queue_thresholds_t f;
+} cp_queue_thresholds_u;
+
+
+/*
+ * CP_MEQ_THRESHOLDS struct
+ */
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5
+#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16
+#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000
+#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000
+
+#define CP_MEQ_THRESHOLDS_MASK \
+     (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \
+      CP_MEQ_THRESHOLDS_ROQ_END_MASK)
+
+#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \
+     ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \
+      (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT))
+
+#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 16;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+     } cp_meq_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 16;
+     } cp_meq_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_thresholds_t f;
+} cp_meq_thresholds_u;
+
+
+/*
+ * CP_CSQ_AVAIL struct
+ */
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE  7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE  7
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK  0x00007f00
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK  0x007f0000
+
+#define CP_CSQ_AVAIL_MASK \
+     (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK)
+
+#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \
+     ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \
+      (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \
+      (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT))
+
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int                                : 9;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+     } cp_csq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_avail_t f;
+} cp_csq_avail_u;
+
+
+/*
+ * CP_STQ_AVAIL struct
+ */
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE   7
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT  0
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_MASK   0x0000007f
+
+#define CP_STQ_AVAIL_MASK \
+     (CP_STQ_AVAIL_STQ_CNT_ST_MASK)
+
+#define CP_STQ_AVAIL(stq_cnt_st) \
+     ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT))
+
+#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \
+     ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \
+     cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+          unsigned int                                : 25;
+     } cp_stq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int                                : 25;
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+     } cp_stq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_avail_t f;
+} cp_stq_avail_u;
+
+
+/*
+ * CP_MEQ_AVAIL struct
+ */
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SIZE      5
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT     0
+
+#define CP_MEQ_AVAIL_MEQ_CNT_MASK      0x0000001f
+
+#define CP_MEQ_AVAIL_MASK \
+     (CP_MEQ_AVAIL_MEQ_CNT_MASK)
+
+#define CP_MEQ_AVAIL(meq_cnt) \
+     ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT))
+
+#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \
+     ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \
+     cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+          unsigned int                                : 27;
+     } cp_meq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int                                : 27;
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+     } cp_meq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_avail_t f;
+} cp_meq_avail_u;
+
+
+/*
+ * CP_CSQ_RB_STAT struct
+ */
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000
+
+#define CP_CSQ_RB_STAT_MASK \
+     (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \
+      CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK)
+
+#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \
+     ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \
+      (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT))
+
+#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_rb_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+     } cp_csq_rb_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_rb_stat_t f;
+} cp_csq_rb_stat_u;
+
+
+/*
+ * CP_CSQ_IB1_STAT struct
+ */
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000
+
+#define CP_CSQ_IB1_STAT_MASK \
+     (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \
+      CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK)
+
+#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \
+     ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \
+      (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT))
+
+#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib1_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+     } cp_csq_ib1_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib1_stat_t f;
+} cp_csq_ib1_stat_u;
+
+
+/*
+ * CP_CSQ_IB2_STAT struct
+ */
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000
+
+#define CP_CSQ_IB2_STAT_MASK \
+     (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \
+      CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK)
+
+#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \
+     ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \
+      (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT))
+
+#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib2_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+     } cp_csq_ib2_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib2_stat_t f;
+} cp_csq_ib2_stat_u;
+
+
+/*
+ * CP_NON_PREFETCH_CNTRS struct
+ */
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700
+
+#define CP_NON_PREFETCH_CNTRS_MASK \
+     (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \
+      CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK)
+
+#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \
+     ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \
+      (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT))
+
+#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 21;
+     } cp_non_prefetch_cntrs_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int                                : 21;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+     } cp_non_prefetch_cntrs_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_non_prefetch_cntrs_t f;
+} cp_non_prefetch_cntrs_u;
+
+
+/*
+ * CP_STQ_ST_STAT struct
+ */
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000
+
+#define CP_STQ_ST_STAT_MASK \
+     (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \
+      CP_STQ_ST_STAT_STQ_WPTR_ST_MASK)
+
+#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \
+     ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \
+      (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT))
+
+#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+     } cp_stq_st_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+     } cp_stq_st_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_st_stat_t f;
+} cp_stq_st_stat_u;
+
+
+/*
+ * CP_MEQ_STAT struct
+ */
+
+#define CP_MEQ_STAT_MEQ_RPTR_SIZE      10
+#define CP_MEQ_STAT_MEQ_WPTR_SIZE      10
+
+#define CP_MEQ_STAT_MEQ_RPTR_SHIFT     0
+#define CP_MEQ_STAT_MEQ_WPTR_SHIFT     16
+
+#define CP_MEQ_STAT_MEQ_RPTR_MASK      0x000003ff
+#define CP_MEQ_STAT_MEQ_WPTR_MASK      0x03ff0000
+
+#define CP_MEQ_STAT_MASK \
+     (CP_MEQ_STAT_MEQ_RPTR_MASK | \
+      CP_MEQ_STAT_MEQ_WPTR_MASK)
+
+#define CP_MEQ_STAT(meq_rptr, meq_wptr) \
+     ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \
+      (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT))
+
+#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+     } cp_meq_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+     } cp_meq_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_stat_t f;
+} cp_meq_stat_u;
+
+
+/*
+ * CP_MIU_TAG_STAT struct
+ */
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001
+#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002
+#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004
+#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008
+#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010
+#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020
+#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040
+#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080
+#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100
+#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200
+#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400
+#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800
+#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000
+#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000
+#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000
+#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000
+#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000
+#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000
+
+#define CP_MIU_TAG_STAT_MASK \
+     (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \
+      CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK)
+
+#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \
+     ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \
+      (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \
+      (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \
+      (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \
+      (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \
+      (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \
+      (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \
+      (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \
+      (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \
+      (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \
+      (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \
+      (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \
+      (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \
+      (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \
+      (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \
+      (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \
+      (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \
+      (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \
+      (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT))
+
+#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int                                : 13;
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+     } cp_miu_tag_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+          unsigned int                                : 13;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+     } cp_miu_tag_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_miu_tag_stat_t f;
+} cp_miu_tag_stat_u;
+
+
+/*
+ * CP_CMD_INDEX struct
+ */
+
+#define CP_CMD_INDEX_CMD_INDEX_SIZE    7
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2
+
+#define CP_CMD_INDEX_CMD_INDEX_SHIFT   0
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16
+
+#define CP_CMD_INDEX_CMD_INDEX_MASK    0x0000007f
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000
+
+#define CP_CMD_INDEX_MASK \
+     (CP_CMD_INDEX_CMD_INDEX_MASK | \
+      CP_CMD_INDEX_CMD_QUEUE_SEL_MASK)
+
+#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \
+     ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \
+      (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT))
+
+#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 14;
+     } cp_cmd_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int                                : 14;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+     } cp_cmd_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_index_t f;
+} cp_cmd_index_u;
+
+
+/*
+ * CP_CMD_DATA struct
+ */
+
+#define CP_CMD_DATA_CMD_DATA_SIZE      32
+
+#define CP_CMD_DATA_CMD_DATA_SHIFT     0
+
+#define CP_CMD_DATA_CMD_DATA_MASK      0xffffffff
+
+#define CP_CMD_DATA_MASK \
+     (CP_CMD_DATA_CMD_DATA_MASK)
+
+#define CP_CMD_DATA(cmd_data) \
+     ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT))
+
+#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \
+     ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \
+     cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_data_t f;
+} cp_cmd_data_u;
+
+
+/*
+ * CP_ME_CNTL struct
+ */
+
+#define CP_ME_CNTL_ME_STATMUX_SIZE     16
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_ME_HALT_SIZE        1
+#define CP_ME_CNTL_ME_BUSY_SIZE        1
+#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE  1
+
+#define CP_ME_CNTL_ME_STATMUX_SHIFT    0
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26
+#define CP_ME_CNTL_ME_HALT_SHIFT       28
+#define CP_ME_CNTL_ME_BUSY_SHIFT       29
+#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31
+
+#define CP_ME_CNTL_ME_STATMUX_MASK     0x0000ffff
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000
+#define CP_ME_CNTL_ME_HALT_MASK        0x10000000
+#define CP_ME_CNTL_ME_BUSY_MASK        0x20000000
+#define CP_ME_CNTL_PROG_CNT_SIZE_MASK  0x80000000
+
+#define CP_ME_CNTL_MASK \
+     (CP_ME_CNTL_ME_STATMUX_MASK | \
+      CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_ME_HALT_MASK | \
+      CP_ME_CNTL_ME_BUSY_MASK | \
+      CP_ME_CNTL_PROG_CNT_SIZE_MASK)
+
+#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \
+     ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \
+      (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \
+      (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \
+      (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT))
+
+#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+          unsigned int                                : 9;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+     } cp_me_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 9;
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+     } cp_me_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+
+/*
+ * CP_ME_STATUS struct
+ */
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_ME_STATUS_MASK \
+     (CP_ME_STATUS_ME_DEBUG_DATA_MASK)
+
+#define CP_ME_STATUS(me_debug_data) \
+     ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT))
+
+#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \
+     ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \
+     cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_status_t f;
+} cp_me_status_u;
+
+
+/*
+ * CP_ME_RAM_WADDR struct
+ */
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_WADDR_MASK \
+     (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK)
+
+#define CP_ME_RAM_WADDR(me_ram_waddr) \
+     ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT))
+
+#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \
+     ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \
+     cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_waddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+     } cp_me_ram_waddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_waddr_t f;
+} cp_me_ram_waddr_u;
+
+
+/*
+ * CP_ME_RAM_RADDR struct
+ */
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_RADDR_MASK \
+     (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK)
+
+#define CP_ME_RAM_RADDR(me_ram_raddr) \
+     ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT))
+
+#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \
+     ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \
+     cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_raddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+     } cp_me_ram_raddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+
+/*
+ * CP_ME_RAM_DATA struct
+ */
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff
+
+#define CP_ME_RAM_DATA_MASK \
+     (CP_ME_RAM_DATA_ME_RAM_DATA_MASK)
+
+#define CP_ME_RAM_DATA(me_ram_data) \
+     ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT))
+
+#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \
+     ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \
+     cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_data_t f;
+} cp_me_ram_data_u;
+
+
+/*
+ * CP_ME_RDADDR struct
+ */
+
+#define CP_ME_RDADDR_ME_RDADDR_SIZE    32
+
+#define CP_ME_RDADDR_ME_RDADDR_SHIFT   0
+
+#define CP_ME_RDADDR_ME_RDADDR_MASK    0xffffffff
+
+#define CP_ME_RDADDR_MASK \
+     (CP_ME_RDADDR_ME_RDADDR_MASK)
+
+#define CP_ME_RDADDR(me_rdaddr) \
+     ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT))
+
+#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \
+     ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \
+     cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_rdaddr_t f;
+} cp_me_rdaddr_u;
+
+
+/*
+ * CP_DEBUG struct
+ */
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23
+#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0
+#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff
+#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000
+#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000
+#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000
+
+#define CP_DEBUG_MASK \
+     (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \
+      CP_DEBUG_PREDICATE_DISABLE_MASK | \
+      CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \
+      CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \
+      CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \
+      CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \
+      CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \
+      CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \
+      CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK)
+
+#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \
+     ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \
+      (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \
+      (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \
+      (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \
+      (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \
+      (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \
+      (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \
+      (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \
+      (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT))
+
+#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \
+     ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \
+     ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+     } cp_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+     } cp_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+
+/*
+ * SCRATCH_REG0 struct
+ */
+
+#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32
+
+#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0
+
+#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff
+
+#define SCRATCH_REG0_MASK \
+     (SCRATCH_REG0_SCRATCH_REG0_MASK)
+
+#define SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT))
+
+#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \
+     scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+
+/*
+ * SCRATCH_REG1 struct
+ */
+
+#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32
+
+#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0
+
+#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff
+
+#define SCRATCH_REG1_MASK \
+     (SCRATCH_REG1_SCRATCH_REG1_MASK)
+
+#define SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT))
+
+#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \
+     scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+
+/*
+ * SCRATCH_REG2 struct
+ */
+
+#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32
+
+#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0
+
+#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff
+
+#define SCRATCH_REG2_MASK \
+     (SCRATCH_REG2_SCRATCH_REG2_MASK)
+
+#define SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT))
+
+#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \
+     scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+
+/*
+ * SCRATCH_REG3 struct
+ */
+
+#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32
+
+#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0
+
+#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff
+
+#define SCRATCH_REG3_MASK \
+     (SCRATCH_REG3_SCRATCH_REG3_MASK)
+
+#define SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT))
+
+#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \
+     scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+
+/*
+ * SCRATCH_REG4 struct
+ */
+
+#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32
+
+#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0
+
+#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff
+
+#define SCRATCH_REG4_MASK \
+     (SCRATCH_REG4_SCRATCH_REG4_MASK)
+
+#define SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT))
+
+#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \
+     scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+
+/*
+ * SCRATCH_REG5 struct
+ */
+
+#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32
+
+#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0
+
+#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff
+
+#define SCRATCH_REG5_MASK \
+     (SCRATCH_REG5_SCRATCH_REG5_MASK)
+
+#define SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT))
+
+#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \
+     scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+
+/*
+ * SCRATCH_REG6 struct
+ */
+
+#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32
+
+#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0
+
+#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff
+
+#define SCRATCH_REG6_MASK \
+     (SCRATCH_REG6_SCRATCH_REG6_MASK)
+
+#define SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT))
+
+#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \
+     scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg6_t f;
+} scratch_reg6_u;
+
+
+/*
+ * SCRATCH_REG7 struct
+ */
+
+#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32
+
+#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0
+
+#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff
+
+#define SCRATCH_REG7_MASK \
+     (SCRATCH_REG7_SCRATCH_REG7_MASK)
+
+#define SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT))
+
+#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \
+     scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg7_t f;
+} scratch_reg7_u;
+
+
+/*
+ * SCRATCH_UMSK struct
+ */
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8
+#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0
+#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff
+#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000
+
+#define SCRATCH_UMSK_MASK \
+     (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \
+      SCRATCH_UMSK_SCRATCH_SWAP_MASK)
+
+#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \
+     ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \
+      (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT))
+
+#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 14;
+     } scratch_umsk_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int                                : 14;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+     } scratch_umsk_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+
+/*
+ * SCRATCH_ADDR struct
+ */
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0
+
+#define SCRATCH_ADDR_MASK \
+     (SCRATCH_ADDR_SCRATCH_ADDR_MASK)
+
+#define SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT))
+
+#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \
+     scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int                                : 5;
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+     } scratch_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+          unsigned int                                : 5;
+     } scratch_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_SRC struct
+ */
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_VS_EVENT_SRC_MASK \
+     (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \
+      CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK)
+
+#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \
+     ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \
+      (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_vs_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int                                : 30;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+     } cp_me_vs_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_src_t f;
+} cp_me_vs_event_src_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_MASK \
+     (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \
+      CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK)
+
+#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \
+     ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \
+      (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_t f;
+} cp_me_vs_event_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_MASK \
+     (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK)
+
+#define CP_ME_VS_EVENT_DATA(vs_done_data) \
+     ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \
+     ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \
+     cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_t f;
+} cp_me_vs_event_data_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \
+      CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \
+     ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \
+      (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_swm_t f;
+} cp_me_vs_event_addr_swm_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_SWM_MASK \
+     (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \
+     ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \
+     ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \
+     cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_swm_t f;
+} cp_me_vs_event_data_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_SRC struct
+ */
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_PS_EVENT_SRC_MASK \
+     (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \
+      CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK)
+
+#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \
+     ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \
+      (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT))
+
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_ps_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int                                : 30;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+     } cp_me_ps_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_src_t f;
+} cp_me_ps_event_src_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_MASK \
+     (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \
+      CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK)
+
+#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \
+     ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \
+      (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_t f;
+} cp_me_ps_event_addr_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_MASK \
+     (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK)
+
+#define CP_ME_PS_EVENT_DATA(ps_done_data) \
+     ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \
+     ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \
+     cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_t f;
+} cp_me_ps_event_data_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \
+      CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \
+     ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \
+      (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_swm_t f;
+} cp_me_ps_event_addr_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_SWM_MASK \
+     (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \
+     ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \
+     ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \
+     cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_swm_t f;
+} cp_me_ps_event_data_swm_u;
+
+
+/*
+ * CP_ME_CF_EVENT_SRC struct
+ */
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001
+
+#define CP_ME_CF_EVENT_SRC_MASK \
+     (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK)
+
+#define CP_ME_CF_EVENT_SRC(cf_done_src) \
+     ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT))
+
+#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \
+     ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \
+     cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+          unsigned int                                : 31;
+     } cp_me_cf_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int                                : 31;
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+     } cp_me_cf_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_src_t f;
+} cp_me_cf_event_src_u;
+
+
+/*
+ * CP_ME_CF_EVENT_ADDR struct
+ */
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_CF_EVENT_ADDR_MASK \
+     (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \
+      CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK)
+
+#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \
+     ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \
+      (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT))
+
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_addr_t f;
+} cp_me_cf_event_addr_u;
+
+
+/*
+ * CP_ME_CF_EVENT_DATA struct
+ */
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_CF_EVENT_DATA_MASK \
+     (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK)
+
+#define CP_ME_CF_EVENT_DATA(cf_done_data) \
+     ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT))
+
+#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \
+     ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \
+     cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_data_t f;
+} cp_me_cf_event_data_u;
+
+
+/*
+ * CP_ME_NRT_ADDR struct
+ */
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_NRT_ADDR_MASK \
+     (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \
+      CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK)
+
+#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \
+     ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \
+      (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT))
+
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+     } cp_me_nrt_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+     } cp_me_nrt_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_addr_t f;
+} cp_me_nrt_addr_u;
+
+
+/*
+ * CP_ME_NRT_DATA struct
+ */
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff
+
+#define CP_ME_NRT_DATA_MASK \
+     (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK)
+
+#define CP_ME_NRT_DATA(nrt_write_data) \
+     ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT))
+
+#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \
+     ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \
+     cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_data_t f;
+} cp_me_nrt_data_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_SRC struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001
+
+#define CP_ME_VS_FETCH_DONE_SRC_MASK \
+     (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \
+     ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \
+     ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \
+     cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+          unsigned int                                : 31;
+     } cp_me_vs_fetch_done_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int                                : 31;
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+     } cp_me_vs_fetch_done_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_src_t f;
+} cp_me_vs_fetch_done_src_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_ADDR struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_FETCH_DONE_ADDR_MASK \
+     (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \
+      CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \
+     ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \
+      (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_addr_t f;
+} cp_me_vs_fetch_done_addr_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_DATA struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_FETCH_DONE_DATA_MASK \
+     (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK)
+
+#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \
+     ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \
+     ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \
+     cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_data_t f;
+} cp_me_vs_fetch_done_data_u;
+
+
+/*
+ * CP_INT_CNTL struct
+ */
+
+#define CP_INT_CNTL_SW_INT_MASK_SIZE   1
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB2_INT_MASK_SIZE  1
+#define CP_INT_CNTL_IB1_INT_MASK_SIZE  1
+#define CP_INT_CNTL_RB_INT_MASK_SIZE   1
+
+#define CP_INT_CNTL_SW_INT_MASK_SHIFT  19
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26
+#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27
+#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29
+#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30
+#define CP_INT_CNTL_RB_INT_MASK_SHIFT  31
+
+#define CP_INT_CNTL_SW_INT_MASK_MASK   0x00080000
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000
+#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000
+#define CP_INT_CNTL_IB2_INT_MASK_MASK  0x20000000
+#define CP_INT_CNTL_IB1_INT_MASK_MASK  0x40000000
+#define CP_INT_CNTL_RB_INT_MASK_MASK   0x80000000
+
+#define CP_INT_CNTL_MASK \
+     (CP_INT_CNTL_SW_INT_MASK_MASK | \
+      CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \
+      CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB2_INT_MASK_MASK | \
+      CP_INT_CNTL_IB1_INT_MASK_MASK | \
+      CP_INT_CNTL_RB_INT_MASK_MASK)
+
+#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \
+     ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \
+      (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \
+      (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \
+      (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \
+      (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \
+      (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \
+      (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \
+      (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \
+      (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT))
+
+#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+     } cp_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_cntl_t f;
+} cp_int_cntl_u;
+
+
+/*
+ * CP_INT_STATUS struct
+ */
+
+#define CP_INT_STATUS_SW_INT_STAT_SIZE 1
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1
+#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1
+#define CP_INT_STATUS_RB_INT_STAT_SIZE 1
+
+#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26
+#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27
+#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29
+#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30
+#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31
+
+#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000
+#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000
+#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000
+
+#define CP_INT_STATUS_MASK \
+     (CP_INT_STATUS_SW_INT_STAT_MASK | \
+      CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \
+      CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB2_INT_STAT_MASK | \
+      CP_INT_STATUS_IB1_INT_STAT_MASK | \
+      CP_INT_STATUS_RB_INT_STAT_MASK)
+
+#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \
+     ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \
+      (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \
+      (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \
+      (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \
+      (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \
+      (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \
+      (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \
+      (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \
+      (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT))
+
+#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+     } cp_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 19;
+     } cp_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_status_t f;
+} cp_int_status_u;
+
+
+/*
+ * CP_INT_ACK struct
+ */
+
+#define CP_INT_ACK_SW_INT_ACK_SIZE     1
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_IB_ERROR_ACK_SIZE   1
+#define CP_INT_ACK_IB2_INT_ACK_SIZE    1
+#define CP_INT_ACK_IB1_INT_ACK_SIZE    1
+#define CP_INT_ACK_RB_INT_ACK_SIZE     1
+
+#define CP_INT_ACK_SW_INT_ACK_SHIFT    19
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26
+#define CP_INT_ACK_IB_ERROR_ACK_SHIFT  27
+#define CP_INT_ACK_IB2_INT_ACK_SHIFT   29
+#define CP_INT_ACK_IB1_INT_ACK_SHIFT   30
+#define CP_INT_ACK_RB_INT_ACK_SHIFT    31
+
+#define CP_INT_ACK_SW_INT_ACK_MASK     0x00080000
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000
+#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000
+#define CP_INT_ACK_IB_ERROR_ACK_MASK   0x08000000
+#define CP_INT_ACK_IB2_INT_ACK_MASK    0x20000000
+#define CP_INT_ACK_IB1_INT_ACK_MASK    0x40000000
+#define CP_INT_ACK_RB_INT_ACK_MASK     0x80000000
+
+#define CP_INT_ACK_MASK \
+     (CP_INT_ACK_SW_INT_ACK_MASK | \
+      CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \
+      CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB2_INT_ACK_MASK | \
+      CP_INT_ACK_IB1_INT_ACK_MASK | \
+      CP_INT_ACK_RB_INT_ACK_MASK)
+
+#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \
+     ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \
+      (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \
+      (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \
+      (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \
+      (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \
+      (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \
+      (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \
+      (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \
+      (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT))
+
+#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+     } cp_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_ack_t f;
+} cp_int_ack_u;
+
+
+/*
+ * CP_PFP_UCODE_ADDR struct
+ */
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff
+
+#define CP_PFP_UCODE_ADDR_MASK \
+     (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK)
+
+#define CP_PFP_UCODE_ADDR(ucode_addr) \
+     ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT))
+
+#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \
+     ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \
+     cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+          unsigned int                                : 23;
+     } cp_pfp_ucode_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int                                : 23;
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+     } cp_pfp_ucode_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_addr_t f;
+} cp_pfp_ucode_addr_u;
+
+
+/*
+ * CP_PFP_UCODE_DATA struct
+ */
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff
+
+#define CP_PFP_UCODE_DATA_MASK \
+     (CP_PFP_UCODE_DATA_UCODE_DATA_MASK)
+
+#define CP_PFP_UCODE_DATA(ucode_data) \
+     ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT))
+
+#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \
+     ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \
+     cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+          unsigned int                                : 8;
+     } cp_pfp_ucode_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int                                : 8;
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+     } cp_pfp_ucode_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_data_t f;
+} cp_pfp_ucode_data_u;
+
+
+/*
+ * CP_PERFMON_CNTL struct
+ */
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300
+
+#define CP_PERFMON_CNTL_MASK \
+     (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \
+      CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK)
+
+#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \
+     ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \
+      (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT))
+
+#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 22;
+     } cp_perfmon_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int                                : 22;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+     } cp_perfmon_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfmon_cntl_t f;
+} cp_perfmon_cntl_u;
+
+
+/*
+ * CP_PERFCOUNTER_SELECT struct
+ */
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f
+
+#define CP_PERFCOUNTER_SELECT_MASK \
+     (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK)
+
+#define CP_PERFCOUNTER_SELECT(perfcount_sel) \
+     ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT))
+
+#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \
+     ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \
+     cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+          unsigned int                                : 26;
+     } cp_perfcounter_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int                                : 26;
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+     } cp_perfcounter_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_select_t f;
+} cp_perfcounter_select_u;
+
+
+/*
+ * CP_PERFCOUNTER_LO struct
+ */
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff
+
+#define CP_PERFCOUNTER_LO_MASK \
+     (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK)
+
+#define CP_PERFCOUNTER_LO(perfcount_lo) \
+     ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT))
+
+#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \
+     ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \
+     cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_lo_t f;
+} cp_perfcounter_lo_u;
+
+
+/*
+ * CP_PERFCOUNTER_HI struct
+ */
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff
+
+#define CP_PERFCOUNTER_HI_MASK \
+     (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK)
+
+#define CP_PERFCOUNTER_HI(perfcount_hi) \
+     ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT))
+
+#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \
+     ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \
+     cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+          unsigned int                                : 16;
+     } cp_perfcounter_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+     } cp_perfcounter_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_hi_t f;
+} cp_perfcounter_hi_u;
+
+
+/*
+ * CP_BIN_MASK_LO struct
+ */
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff
+
+#define CP_BIN_MASK_LO_MASK \
+     (CP_BIN_MASK_LO_BIN_MASK_LO_MASK)
+
+#define CP_BIN_MASK_LO(bin_mask_lo) \
+     ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT))
+
+#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \
+     ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \
+     cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_lo_t f;
+} cp_bin_mask_lo_u;
+
+
+/*
+ * CP_BIN_MASK_HI struct
+ */
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff
+
+#define CP_BIN_MASK_HI_MASK \
+     (CP_BIN_MASK_HI_BIN_MASK_HI_MASK)
+
+#define CP_BIN_MASK_HI(bin_mask_hi) \
+     ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT))
+
+#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \
+     ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \
+     cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_hi_t f;
+} cp_bin_mask_hi_u;
+
+
+/*
+ * CP_BIN_SELECT_LO struct
+ */
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff
+
+#define CP_BIN_SELECT_LO_MASK \
+     (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK)
+
+#define CP_BIN_SELECT_LO(bin_select_lo) \
+     ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT))
+
+#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \
+     ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \
+     cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_lo_t f;
+} cp_bin_select_lo_u;
+
+
+/*
+ * CP_BIN_SELECT_HI struct
+ */
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff
+
+#define CP_BIN_SELECT_HI_MASK \
+     (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK)
+
+#define CP_BIN_SELECT_HI(bin_select_hi) \
+     ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT))
+
+#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \
+     ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \
+     cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_hi_t f;
+} cp_bin_select_hi_u;
+
+
+/*
+ * CP_NV_FLAGS_0 struct
+ */
+
+#define CP_NV_FLAGS_0_DISCARD_0_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_0_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_1_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_1_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_2_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_2_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_3_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_3_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_4_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_4_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_5_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_5_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_6_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_6_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_7_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_7_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_8_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_8_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_9_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_9_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_10_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_11_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_12_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_13_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_14_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_15_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1
+
+#define CP_NV_FLAGS_0_DISCARD_0_SHIFT  0
+#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1
+#define CP_NV_FLAGS_0_DISCARD_1_SHIFT  2
+#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3
+#define CP_NV_FLAGS_0_DISCARD_2_SHIFT  4
+#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5
+#define CP_NV_FLAGS_0_DISCARD_3_SHIFT  6
+#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7
+#define CP_NV_FLAGS_0_DISCARD_4_SHIFT  8
+#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9
+#define CP_NV_FLAGS_0_DISCARD_5_SHIFT  10
+#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11
+#define CP_NV_FLAGS_0_DISCARD_6_SHIFT  12
+#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13
+#define CP_NV_FLAGS_0_DISCARD_7_SHIFT  14
+#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15
+#define CP_NV_FLAGS_0_DISCARD_8_SHIFT  16
+#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17
+#define CP_NV_FLAGS_0_DISCARD_9_SHIFT  18
+#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19
+#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20
+#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21
+#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22
+#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23
+#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24
+#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25
+#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26
+#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27
+#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28
+#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29
+#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30
+#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31
+
+#define CP_NV_FLAGS_0_DISCARD_0_MASK   0x00000001
+#define CP_NV_FLAGS_0_END_RCVD_0_MASK  0x00000002
+#define CP_NV_FLAGS_0_DISCARD_1_MASK   0x00000004
+#define CP_NV_FLAGS_0_END_RCVD_1_MASK  0x00000008
+#define CP_NV_FLAGS_0_DISCARD_2_MASK   0x00000010
+#define CP_NV_FLAGS_0_END_RCVD_2_MASK  0x00000020
+#define CP_NV_FLAGS_0_DISCARD_3_MASK   0x00000040
+#define CP_NV_FLAGS_0_END_RCVD_3_MASK  0x00000080
+#define CP_NV_FLAGS_0_DISCARD_4_MASK   0x00000100
+#define CP_NV_FLAGS_0_END_RCVD_4_MASK  0x00000200
+#define CP_NV_FLAGS_0_DISCARD_5_MASK   0x00000400
+#define CP_NV_FLAGS_0_END_RCVD_5_MASK  0x00000800
+#define CP_NV_FLAGS_0_DISCARD_6_MASK   0x00001000
+#define CP_NV_FLAGS_0_END_RCVD_6_MASK  0x00002000
+#define CP_NV_FLAGS_0_DISCARD_7_MASK   0x00004000
+#define CP_NV_FLAGS_0_END_RCVD_7_MASK  0x00008000
+#define CP_NV_FLAGS_0_DISCARD_8_MASK   0x00010000
+#define CP_NV_FLAGS_0_END_RCVD_8_MASK  0x00020000
+#define CP_NV_FLAGS_0_DISCARD_9_MASK   0x00040000
+#define CP_NV_FLAGS_0_END_RCVD_9_MASK  0x00080000
+#define CP_NV_FLAGS_0_DISCARD_10_MASK  0x00100000
+#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000
+#define CP_NV_FLAGS_0_DISCARD_11_MASK  0x00400000
+#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000
+#define CP_NV_FLAGS_0_DISCARD_12_MASK  0x01000000
+#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000
+#define CP_NV_FLAGS_0_DISCARD_13_MASK  0x04000000
+#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000
+#define CP_NV_FLAGS_0_DISCARD_14_MASK  0x10000000
+#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000
+#define CP_NV_FLAGS_0_DISCARD_15_MASK  0x40000000
+#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000
+
+#define CP_NV_FLAGS_0_MASK \
+     (CP_NV_FLAGS_0_DISCARD_0_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_0_MASK | \
+      CP_NV_FLAGS_0_DISCARD_1_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_1_MASK | \
+      CP_NV_FLAGS_0_DISCARD_2_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_2_MASK | \
+      CP_NV_FLAGS_0_DISCARD_3_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_3_MASK | \
+      CP_NV_FLAGS_0_DISCARD_4_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_4_MASK | \
+      CP_NV_FLAGS_0_DISCARD_5_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_5_MASK | \
+      CP_NV_FLAGS_0_DISCARD_6_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_6_MASK | \
+      CP_NV_FLAGS_0_DISCARD_7_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_7_MASK | \
+      CP_NV_FLAGS_0_DISCARD_8_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_8_MASK | \
+      CP_NV_FLAGS_0_DISCARD_9_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_9_MASK | \
+      CP_NV_FLAGS_0_DISCARD_10_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_10_MASK | \
+      CP_NV_FLAGS_0_DISCARD_11_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_11_MASK | \
+      CP_NV_FLAGS_0_DISCARD_12_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_12_MASK | \
+      CP_NV_FLAGS_0_DISCARD_13_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_13_MASK | \
+      CP_NV_FLAGS_0_DISCARD_14_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_14_MASK | \
+      CP_NV_FLAGS_0_DISCARD_15_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_15_MASK)
+
+#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \
+     ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \
+      (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \
+      (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \
+      (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \
+      (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \
+      (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \
+      (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \
+      (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \
+      (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \
+      (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \
+      (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \
+      (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \
+      (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \
+      (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \
+      (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \
+      (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \
+      (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \
+      (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \
+      (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \
+      (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \
+      (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \
+      (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \
+      (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \
+      (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \
+      (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \
+      (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \
+      (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \
+      (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \
+      (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \
+      (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \
+      (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \
+      (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT))
+
+#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+     } cp_nv_flags_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+     } cp_nv_flags_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_0_t f;
+} cp_nv_flags_0_u;
+
+
+/*
+ * CP_NV_FLAGS_1 struct
+ */
+
+#define CP_NV_FLAGS_1_DISCARD_16_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_17_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_18_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_19_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_20_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_21_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_22_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_23_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_24_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_25_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_26_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_27_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_28_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_29_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_30_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_31_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1
+
+#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0
+#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1
+#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2
+#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3
+#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4
+#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5
+#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6
+#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7
+#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8
+#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9
+#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10
+#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11
+#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12
+#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13
+#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14
+#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15
+#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16
+#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17
+#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18
+#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19
+#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20
+#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21
+#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22
+#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23
+#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24
+#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25
+#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26
+#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27
+#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28
+#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29
+#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30
+#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31
+
+#define CP_NV_FLAGS_1_DISCARD_16_MASK  0x00000001
+#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002
+#define CP_NV_FLAGS_1_DISCARD_17_MASK  0x00000004
+#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008
+#define CP_NV_FLAGS_1_DISCARD_18_MASK  0x00000010
+#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020
+#define CP_NV_FLAGS_1_DISCARD_19_MASK  0x00000040
+#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080
+#define CP_NV_FLAGS_1_DISCARD_20_MASK  0x00000100
+#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200
+#define CP_NV_FLAGS_1_DISCARD_21_MASK  0x00000400
+#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800
+#define CP_NV_FLAGS_1_DISCARD_22_MASK  0x00001000
+#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000
+#define CP_NV_FLAGS_1_DISCARD_23_MASK  0x00004000
+#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000
+#define CP_NV_FLAGS_1_DISCARD_24_MASK  0x00010000
+#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000
+#define CP_NV_FLAGS_1_DISCARD_25_MASK  0x00040000
+#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000
+#define CP_NV_FLAGS_1_DISCARD_26_MASK  0x00100000
+#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000
+#define CP_NV_FLAGS_1_DISCARD_27_MASK  0x00400000
+#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000
+#define CP_NV_FLAGS_1_DISCARD_28_MASK  0x01000000
+#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000
+#define CP_NV_FLAGS_1_DISCARD_29_MASK  0x04000000
+#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000
+#define CP_NV_FLAGS_1_DISCARD_30_MASK  0x10000000
+#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000
+#define CP_NV_FLAGS_1_DISCARD_31_MASK  0x40000000
+#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000
+
+#define CP_NV_FLAGS_1_MASK \
+     (CP_NV_FLAGS_1_DISCARD_16_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_16_MASK | \
+      CP_NV_FLAGS_1_DISCARD_17_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_17_MASK | \
+      CP_NV_FLAGS_1_DISCARD_18_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_18_MASK | \
+      CP_NV_FLAGS_1_DISCARD_19_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_19_MASK | \
+      CP_NV_FLAGS_1_DISCARD_20_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_20_MASK | \
+      CP_NV_FLAGS_1_DISCARD_21_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_21_MASK | \
+      CP_NV_FLAGS_1_DISCARD_22_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_22_MASK | \
+      CP_NV_FLAGS_1_DISCARD_23_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_23_MASK | \
+      CP_NV_FLAGS_1_DISCARD_24_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_24_MASK | \
+      CP_NV_FLAGS_1_DISCARD_25_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_25_MASK | \
+      CP_NV_FLAGS_1_DISCARD_26_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_26_MASK | \
+      CP_NV_FLAGS_1_DISCARD_27_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_27_MASK | \
+      CP_NV_FLAGS_1_DISCARD_28_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_28_MASK | \
+      CP_NV_FLAGS_1_DISCARD_29_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_29_MASK | \
+      CP_NV_FLAGS_1_DISCARD_30_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_30_MASK | \
+      CP_NV_FLAGS_1_DISCARD_31_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_31_MASK)
+
+#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \
+     ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \
+      (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \
+      (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \
+      (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \
+      (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \
+      (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \
+      (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \
+      (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \
+      (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \
+      (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \
+      (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \
+      (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \
+      (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \
+      (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \
+      (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \
+      (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \
+      (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \
+      (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \
+      (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \
+      (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \
+      (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \
+      (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \
+      (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \
+      (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \
+      (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \
+      (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \
+      (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \
+      (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \
+      (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \
+      (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \
+      (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \
+      (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT))
+
+#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+     } cp_nv_flags_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+     } cp_nv_flags_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_1_t f;
+} cp_nv_flags_1_u;
+
+
+/*
+ * CP_NV_FLAGS_2 struct
+ */
+
+#define CP_NV_FLAGS_2_DISCARD_32_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_33_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_34_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_35_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_36_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_37_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_38_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_39_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_40_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_41_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_42_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_43_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_44_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_45_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_46_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_47_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1
+
+#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0
+#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1
+#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2
+#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3
+#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4
+#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5
+#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6
+#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7
+#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8
+#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9
+#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10
+#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11
+#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12
+#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13
+#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14
+#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15
+#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16
+#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17
+#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18
+#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19
+#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20
+#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21
+#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22
+#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23
+#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24
+#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25
+#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26
+#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27
+#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28
+#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29
+#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30
+#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31
+
+#define CP_NV_FLAGS_2_DISCARD_32_MASK  0x00000001
+#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002
+#define CP_NV_FLAGS_2_DISCARD_33_MASK  0x00000004
+#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008
+#define CP_NV_FLAGS_2_DISCARD_34_MASK  0x00000010
+#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020
+#define CP_NV_FLAGS_2_DISCARD_35_MASK  0x00000040
+#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080
+#define CP_NV_FLAGS_2_DISCARD_36_MASK  0x00000100
+#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200
+#define CP_NV_FLAGS_2_DISCARD_37_MASK  0x00000400
+#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800
+#define CP_NV_FLAGS_2_DISCARD_38_MASK  0x00001000
+#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000
+#define CP_NV_FLAGS_2_DISCARD_39_MASK  0x00004000
+#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000
+#define CP_NV_FLAGS_2_DISCARD_40_MASK  0x00010000
+#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000
+#define CP_NV_FLAGS_2_DISCARD_41_MASK  0x00040000
+#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000
+#define CP_NV_FLAGS_2_DISCARD_42_MASK  0x00100000
+#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000
+#define CP_NV_FLAGS_2_DISCARD_43_MASK  0x00400000
+#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000
+#define CP_NV_FLAGS_2_DISCARD_44_MASK  0x01000000
+#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000
+#define CP_NV_FLAGS_2_DISCARD_45_MASK  0x04000000
+#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000
+#define CP_NV_FLAGS_2_DISCARD_46_MASK  0x10000000
+#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000
+#define CP_NV_FLAGS_2_DISCARD_47_MASK  0x40000000
+#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000
+
+#define CP_NV_FLAGS_2_MASK \
+     (CP_NV_FLAGS_2_DISCARD_32_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_32_MASK | \
+      CP_NV_FLAGS_2_DISCARD_33_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_33_MASK | \
+      CP_NV_FLAGS_2_DISCARD_34_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_34_MASK | \
+      CP_NV_FLAGS_2_DISCARD_35_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_35_MASK | \
+      CP_NV_FLAGS_2_DISCARD_36_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_36_MASK | \
+      CP_NV_FLAGS_2_DISCARD_37_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_37_MASK | \
+      CP_NV_FLAGS_2_DISCARD_38_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_38_MASK | \
+      CP_NV_FLAGS_2_DISCARD_39_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_39_MASK | \
+      CP_NV_FLAGS_2_DISCARD_40_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_40_MASK | \
+      CP_NV_FLAGS_2_DISCARD_41_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_41_MASK | \
+      CP_NV_FLAGS_2_DISCARD_42_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_42_MASK | \
+      CP_NV_FLAGS_2_DISCARD_43_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_43_MASK | \
+      CP_NV_FLAGS_2_DISCARD_44_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_44_MASK | \
+      CP_NV_FLAGS_2_DISCARD_45_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_45_MASK | \
+      CP_NV_FLAGS_2_DISCARD_46_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_46_MASK | \
+      CP_NV_FLAGS_2_DISCARD_47_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_47_MASK)
+
+#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \
+     ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \
+      (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \
+      (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \
+      (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \
+      (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \
+      (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \
+      (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \
+      (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \
+      (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \
+      (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \
+      (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \
+      (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \
+      (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \
+      (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \
+      (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \
+      (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \
+      (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \
+      (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \
+      (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \
+      (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \
+      (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \
+      (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \
+      (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \
+      (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \
+      (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \
+      (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \
+      (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \
+      (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \
+      (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \
+      (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \
+      (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \
+      (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT))
+
+#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+     } cp_nv_flags_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+     } cp_nv_flags_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_2_t f;
+} cp_nv_flags_2_u;
+
+
+/*
+ * CP_NV_FLAGS_3 struct
+ */
+
+#define CP_NV_FLAGS_3_DISCARD_48_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_49_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_50_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_51_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_52_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_53_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_54_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_55_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_56_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_57_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_58_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_59_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_60_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_61_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_62_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_63_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1
+
+#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0
+#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1
+#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2
+#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3
+#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4
+#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5
+#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6
+#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7
+#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8
+#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9
+#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10
+#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11
+#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12
+#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13
+#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14
+#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15
+#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16
+#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17
+#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18
+#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19
+#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20
+#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21
+#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22
+#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23
+#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24
+#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25
+#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26
+#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27
+#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28
+#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29
+#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30
+#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31
+
+#define CP_NV_FLAGS_3_DISCARD_48_MASK  0x00000001
+#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002
+#define CP_NV_FLAGS_3_DISCARD_49_MASK  0x00000004
+#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008
+#define CP_NV_FLAGS_3_DISCARD_50_MASK  0x00000010
+#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020
+#define CP_NV_FLAGS_3_DISCARD_51_MASK  0x00000040
+#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080
+#define CP_NV_FLAGS_3_DISCARD_52_MASK  0x00000100
+#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200
+#define CP_NV_FLAGS_3_DISCARD_53_MASK  0x00000400
+#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800
+#define CP_NV_FLAGS_3_DISCARD_54_MASK  0x00001000
+#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000
+#define CP_NV_FLAGS_3_DISCARD_55_MASK  0x00004000
+#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000
+#define CP_NV_FLAGS_3_DISCARD_56_MASK  0x00010000
+#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000
+#define CP_NV_FLAGS_3_DISCARD_57_MASK  0x00040000
+#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000
+#define CP_NV_FLAGS_3_DISCARD_58_MASK  0x00100000
+#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000
+#define CP_NV_FLAGS_3_DISCARD_59_MASK  0x00400000
+#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000
+#define CP_NV_FLAGS_3_DISCARD_60_MASK  0x01000000
+#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000
+#define CP_NV_FLAGS_3_DISCARD_61_MASK  0x04000000
+#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000
+#define CP_NV_FLAGS_3_DISCARD_62_MASK  0x10000000
+#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000
+#define CP_NV_FLAGS_3_DISCARD_63_MASK  0x40000000
+#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000
+
+#define CP_NV_FLAGS_3_MASK \
+     (CP_NV_FLAGS_3_DISCARD_48_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_48_MASK | \
+      CP_NV_FLAGS_3_DISCARD_49_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_49_MASK | \
+      CP_NV_FLAGS_3_DISCARD_50_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_50_MASK | \
+      CP_NV_FLAGS_3_DISCARD_51_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_51_MASK | \
+      CP_NV_FLAGS_3_DISCARD_52_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_52_MASK | \
+      CP_NV_FLAGS_3_DISCARD_53_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_53_MASK | \
+      CP_NV_FLAGS_3_DISCARD_54_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_54_MASK | \
+      CP_NV_FLAGS_3_DISCARD_55_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_55_MASK | \
+      CP_NV_FLAGS_3_DISCARD_56_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_56_MASK | \
+      CP_NV_FLAGS_3_DISCARD_57_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_57_MASK | \
+      CP_NV_FLAGS_3_DISCARD_58_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_58_MASK | \
+      CP_NV_FLAGS_3_DISCARD_59_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_59_MASK | \
+      CP_NV_FLAGS_3_DISCARD_60_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_60_MASK | \
+      CP_NV_FLAGS_3_DISCARD_61_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_61_MASK | \
+      CP_NV_FLAGS_3_DISCARD_62_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_62_MASK | \
+      CP_NV_FLAGS_3_DISCARD_63_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_63_MASK)
+
+#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \
+     ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \
+      (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \
+      (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \
+      (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \
+      (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \
+      (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \
+      (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \
+      (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \
+      (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \
+      (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \
+      (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \
+      (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \
+      (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \
+      (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \
+      (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \
+      (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \
+      (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \
+      (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \
+      (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \
+      (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \
+      (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \
+      (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \
+      (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \
+      (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \
+      (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \
+      (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \
+      (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \
+      (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \
+      (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \
+      (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \
+      (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \
+      (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT))
+
+#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+     } cp_nv_flags_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+     } cp_nv_flags_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_3_t f;
+} cp_nv_flags_3_u;
+
+
+/*
+ * CP_STATE_DEBUG_INDEX struct
+ */
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f
+
+#define CP_STATE_DEBUG_INDEX_MASK \
+     (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK)
+
+#define CP_STATE_DEBUG_INDEX(state_debug_index) \
+     ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT))
+
+#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \
+     ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \
+     cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+          unsigned int                                : 27;
+     } cp_state_debug_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int                                : 27;
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+     } cp_state_debug_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_index_t f;
+} cp_state_debug_index_u;
+
+
+/*
+ * CP_STATE_DEBUG_DATA struct
+ */
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_STATE_DEBUG_DATA_MASK \
+     (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK)
+
+#define CP_STATE_DEBUG_DATA(state_debug_data) \
+     ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT))
+
+#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \
+     ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \
+     cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_data_t f;
+} cp_state_debug_data_u;
+
+
+/*
+ * CP_PROG_COUNTER struct
+ */
+
+#define CP_PROG_COUNTER_COUNTER_SIZE   32
+
+#define CP_PROG_COUNTER_COUNTER_SHIFT  0
+
+#define CP_PROG_COUNTER_COUNTER_MASK   0xffffffff
+
+#define CP_PROG_COUNTER_MASK \
+     (CP_PROG_COUNTER_COUNTER_MASK)
+
+#define CP_PROG_COUNTER(counter) \
+     ((counter << CP_PROG_COUNTER_COUNTER_SHIFT))
+
+#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \
+     ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \
+     cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_prog_counter_t f;
+} cp_prog_counter_u;
+
+
+/*
+ * CP_STAT struct
+ */
+
+#define CP_STAT_MIU_WR_BUSY_SIZE       1
+#define CP_STAT_MIU_RD_REQ_BUSY_SIZE   1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1
+#define CP_STAT_RBIU_BUSY_SIZE         1
+#define CP_STAT_RCIU_BUSY_SIZE         1
+#define CP_STAT_CSF_RING_BUSY_SIZE     1
+#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_CSF_ST_BUSY_SIZE       1
+#define CP_STAT_CSF_BUSY_SIZE          1
+#define CP_STAT_RING_QUEUE_BUSY_SIZE   1
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1
+#define CP_STAT_ST_QUEUE_BUSY_SIZE     1
+#define CP_STAT_PFP_BUSY_SIZE          1
+#define CP_STAT_MEQ_RING_BUSY_SIZE     1
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_MIU_WC_STALL_SIZE      1
+#define CP_STAT_CP_NRT_BUSY_SIZE       1
+#define CP_STAT__3D_BUSY_SIZE          1
+#define CP_STAT_ME_BUSY_SIZE           1
+#define CP_STAT_ME_WC_BUSY_SIZE        1
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1
+#define CP_STAT_CP_BUSY_SIZE           1
+
+#define CP_STAT_MIU_WR_BUSY_SHIFT      0
+#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT  1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2
+#define CP_STAT_RBIU_BUSY_SHIFT        3
+#define CP_STAT_RCIU_BUSY_SHIFT        4
+#define CP_STAT_CSF_RING_BUSY_SHIFT    5
+#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6
+#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7
+#define CP_STAT_CSF_ST_BUSY_SHIFT      9
+#define CP_STAT_CSF_BUSY_SHIFT         10
+#define CP_STAT_RING_QUEUE_BUSY_SHIFT  11
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13
+#define CP_STAT_ST_QUEUE_BUSY_SHIFT    16
+#define CP_STAT_PFP_BUSY_SHIFT         17
+#define CP_STAT_MEQ_RING_BUSY_SHIFT    18
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20
+#define CP_STAT_MIU_WC_STALL_SHIFT     21
+#define CP_STAT_CP_NRT_BUSY_SHIFT      22
+#define CP_STAT__3D_BUSY_SHIFT         23
+#define CP_STAT_ME_BUSY_SHIFT          26
+#define CP_STAT_ME_WC_BUSY_SHIFT       29
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30
+#define CP_STAT_CP_BUSY_SHIFT          31
+
+#define CP_STAT_MIU_WR_BUSY_MASK       0x00000001
+#define CP_STAT_MIU_RD_REQ_BUSY_MASK   0x00000002
+#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004
+#define CP_STAT_RBIU_BUSY_MASK         0x00000008
+#define CP_STAT_RCIU_BUSY_MASK         0x00000010
+#define CP_STAT_CSF_RING_BUSY_MASK     0x00000020
+#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040
+#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080
+#define CP_STAT_CSF_ST_BUSY_MASK       0x00000200
+#define CP_STAT_CSF_BUSY_MASK          0x00000400
+#define CP_STAT_RING_QUEUE_BUSY_MASK   0x00000800
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000
+#define CP_STAT_ST_QUEUE_BUSY_MASK     0x00010000
+#define CP_STAT_PFP_BUSY_MASK          0x00020000
+#define CP_STAT_MEQ_RING_BUSY_MASK     0x00040000
+#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000
+#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000
+#define CP_STAT_MIU_WC_STALL_MASK      0x00200000
+#define CP_STAT_CP_NRT_BUSY_MASK       0x00400000
+#define CP_STAT__3D_BUSY_MASK          0x00800000
+#define CP_STAT_ME_BUSY_MASK           0x04000000
+#define CP_STAT_ME_WC_BUSY_MASK        0x20000000
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000
+#define CP_STAT_CP_BUSY_MASK           0x80000000
+
+#define CP_STAT_MASK \
+     (CP_STAT_MIU_WR_BUSY_MASK | \
+      CP_STAT_MIU_RD_REQ_BUSY_MASK | \
+      CP_STAT_MIU_RD_RETURN_BUSY_MASK | \
+      CP_STAT_RBIU_BUSY_MASK | \
+      CP_STAT_RCIU_BUSY_MASK | \
+      CP_STAT_CSF_RING_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECTS_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECT2_BUSY_MASK | \
+      CP_STAT_CSF_ST_BUSY_MASK | \
+      CP_STAT_CSF_BUSY_MASK | \
+      CP_STAT_RING_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \
+      CP_STAT_ST_QUEUE_BUSY_MASK | \
+      CP_STAT_PFP_BUSY_MASK | \
+      CP_STAT_MEQ_RING_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \
+      CP_STAT_MIU_WC_STALL_MASK | \
+      CP_STAT_CP_NRT_BUSY_MASK | \
+      CP_STAT__3D_BUSY_MASK | \
+      CP_STAT_ME_BUSY_MASK | \
+      CP_STAT_ME_WC_BUSY_MASK | \
+      CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \
+      CP_STAT_CP_BUSY_MASK)
+
+#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \
+     ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \
+      (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \
+      (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \
+      (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \
+      (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \
+      (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \
+      (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \
+      (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \
+      (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \
+      (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \
+      (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \
+      (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \
+      (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \
+      (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \
+      (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \
+      (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \
+      (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \
+      (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \
+      (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \
+      (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \
+      (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \
+      (me_busy << CP_STAT_ME_BUSY_SHIFT) | \
+      (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \
+      (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \
+      (cp_busy << CP_STAT_CP_BUSY_SHIFT))
+
+#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_GET_RBIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_GET_RCIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_PFP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_GET__3D_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_GET_ME_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_GET_CP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT)
+
+#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+     } cp_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+     } cp_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+
+/*
+ * BIOS_0_SCRATCH struct
+ */
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_0_SCRATCH_MASK \
+     (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_0_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \
+     ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \
+     bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_0_scratch_t f;
+} bios_0_scratch_u;
+
+
+/*
+ * BIOS_1_SCRATCH struct
+ */
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_1_SCRATCH_MASK \
+     (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_1_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \
+     ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \
+     bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_1_scratch_t f;
+} bios_1_scratch_u;
+
+
+/*
+ * BIOS_2_SCRATCH struct
+ */
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_2_SCRATCH_MASK \
+     (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_2_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \
+     ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \
+     bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_2_scratch_t f;
+} bios_2_scratch_u;
+
+
+/*
+ * BIOS_3_SCRATCH struct
+ */
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_3_SCRATCH_MASK \
+     (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_3_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \
+     ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \
+     bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_3_scratch_t f;
+} bios_3_scratch_u;
+
+
+/*
+ * BIOS_4_SCRATCH struct
+ */
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_4_SCRATCH_MASK \
+     (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_4_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \
+     ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \
+     bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_4_scratch_t f;
+} bios_4_scratch_u;
+
+
+/*
+ * BIOS_5_SCRATCH struct
+ */
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_5_SCRATCH_MASK \
+     (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_5_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \
+     ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \
+     bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_5_scratch_t f;
+} bios_5_scratch_u;
+
+
+/*
+ * BIOS_6_SCRATCH struct
+ */
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_6_SCRATCH_MASK \
+     (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_6_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \
+     ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \
+     bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_6_scratch_t f;
+} bios_6_scratch_u;
+
+
+/*
+ * BIOS_7_SCRATCH struct
+ */
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_7_SCRATCH_MASK \
+     (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_7_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \
+     ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \
+     bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_7_scratch_t f;
+} bios_7_scratch_u;
+
+
+/*
+ * BIOS_8_SCRATCH struct
+ */
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_8_SCRATCH_MASK \
+     (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_8_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \
+     ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \
+     bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_8_scratch_t f;
+} bios_8_scratch_u;
+
+
+/*
+ * BIOS_9_SCRATCH struct
+ */
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_9_SCRATCH_MASK \
+     (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_9_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \
+     ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \
+     bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_9_scratch_t f;
+} bios_9_scratch_u;
+
+
+/*
+ * BIOS_10_SCRATCH struct
+ */
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_10_SCRATCH_MASK \
+     (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_10_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \
+     ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \
+     bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_10_scratch_t f;
+} bios_10_scratch_u;
+
+
+/*
+ * BIOS_11_SCRATCH struct
+ */
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_11_SCRATCH_MASK \
+     (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_11_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \
+     ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \
+     bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_11_scratch_t f;
+} bios_11_scratch_u;
+
+
+/*
+ * BIOS_12_SCRATCH struct
+ */
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_12_SCRATCH_MASK \
+     (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_12_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \
+     ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \
+     bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_12_scratch_t f;
+} bios_12_scratch_u;
+
+
+/*
+ * BIOS_13_SCRATCH struct
+ */
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_13_SCRATCH_MASK \
+     (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_13_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \
+     ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \
+     bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_13_scratch_t f;
+} bios_13_scratch_u;
+
+
+/*
+ * BIOS_14_SCRATCH struct
+ */
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_14_SCRATCH_MASK \
+     (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_14_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \
+     ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \
+     bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_14_scratch_t f;
+} bios_14_scratch_u;
+
+
+/*
+ * BIOS_15_SCRATCH struct
+ */
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_15_SCRATCH_MASK \
+     (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_15_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \
+     ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \
+     bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_15_scratch_t f;
+} bios_15_scratch_u;
+
+
+/*
+ * COHER_SIZE_PM4 struct
+ */
+
+#define COHER_SIZE_PM4_SIZE_SIZE       32
+
+#define COHER_SIZE_PM4_SIZE_SHIFT      0
+
+#define COHER_SIZE_PM4_SIZE_MASK       0xffffffff
+
+#define COHER_SIZE_PM4_MASK \
+     (COHER_SIZE_PM4_SIZE_MASK)
+
+#define COHER_SIZE_PM4(size) \
+     ((size << COHER_SIZE_PM4_SIZE_SHIFT))
+
+#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \
+     ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT)
+
+#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \
+     coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_pm4_t f;
+} coher_size_pm4_u;
+
+
+/*
+ * COHER_BASE_PM4 struct
+ */
+
+#define COHER_BASE_PM4_BASE_SIZE       32
+
+#define COHER_BASE_PM4_BASE_SHIFT      0
+
+#define COHER_BASE_PM4_BASE_MASK       0xffffffff
+
+#define COHER_BASE_PM4_MASK \
+     (COHER_BASE_PM4_BASE_MASK)
+
+#define COHER_BASE_PM4(base) \
+     ((base << COHER_BASE_PM4_BASE_SHIFT))
+
+#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \
+     ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT)
+
+#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \
+     coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_pm4_t f;
+} coher_base_pm4_u;
+
+
+/*
+ * COHER_STATUS_PM4 struct
+ */
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_PM4_STATUS_SIZE   1
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_PM4_STATUS_SHIFT  31
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_PM4_STATUS_MASK   0x80000000
+
+#define COHER_STATUS_PM4_MASK \
+     (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_PM4_STATUS_MASK)
+
+#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_PM4_STATUS_SHIFT))
+
+#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT)
+
+#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+     } coher_status_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+     } coher_status_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_pm4_t f;
+} coher_status_pm4_u;
+
+
+/*
+ * COHER_SIZE_HOST struct
+ */
+
+#define COHER_SIZE_HOST_SIZE_SIZE      32
+
+#define COHER_SIZE_HOST_SIZE_SHIFT     0
+
+#define COHER_SIZE_HOST_SIZE_MASK      0xffffffff
+
+#define COHER_SIZE_HOST_MASK \
+     (COHER_SIZE_HOST_SIZE_MASK)
+
+#define COHER_SIZE_HOST(size) \
+     ((size << COHER_SIZE_HOST_SIZE_SHIFT))
+
+#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \
+     ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT)
+
+#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \
+     coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_host_t f;
+} coher_size_host_u;
+
+
+/*
+ * COHER_BASE_HOST struct
+ */
+
+#define COHER_BASE_HOST_BASE_SIZE      32
+
+#define COHER_BASE_HOST_BASE_SHIFT     0
+
+#define COHER_BASE_HOST_BASE_MASK      0xffffffff
+
+#define COHER_BASE_HOST_MASK \
+     (COHER_BASE_HOST_BASE_MASK)
+
+#define COHER_BASE_HOST(base) \
+     ((base << COHER_BASE_HOST_BASE_SHIFT))
+
+#define COHER_BASE_HOST_GET_BASE(coher_base_host) \
+     ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT)
+
+#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \
+     coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_host_t f;
+} coher_base_host_u;
+
+
+/*
+ * COHER_STATUS_HOST struct
+ */
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_HOST_STATUS_SIZE  1
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_HOST_STATUS_SHIFT 31
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_HOST_STATUS_MASK  0x80000000
+
+#define COHER_STATUS_HOST_MASK \
+     (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_HOST_STATUS_MASK)
+
+#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_HOST_STATUS_SHIFT))
+
+#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT)
+
+#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+     } coher_status_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+     } coher_status_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_host_t f;
+} coher_status_host_u;
+
+
+/*
+ * COHER_DEST_BASE_0 struct
+ */
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000
+
+#define COHER_DEST_BASE_0_MASK \
+     (COHER_DEST_BASE_0_DEST_BASE_0_MASK)
+
+#define COHER_DEST_BASE_0(dest_base_0) \
+     ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT))
+
+#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \
+     ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \
+     coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+     } coher_dest_base_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_0_t f;
+} coher_dest_base_0_u;
+
+
+/*
+ * COHER_DEST_BASE_1 struct
+ */
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000
+
+#define COHER_DEST_BASE_1_MASK \
+     (COHER_DEST_BASE_1_DEST_BASE_1_MASK)
+
+#define COHER_DEST_BASE_1(dest_base_1) \
+     ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT))
+
+#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \
+     ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \
+     coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+     } coher_dest_base_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_1_t f;
+} coher_dest_base_1_u;
+
+
+/*
+ * COHER_DEST_BASE_2 struct
+ */
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000
+
+#define COHER_DEST_BASE_2_MASK \
+     (COHER_DEST_BASE_2_DEST_BASE_2_MASK)
+
+#define COHER_DEST_BASE_2(dest_base_2) \
+     ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT))
+
+#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \
+     ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \
+     coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+     } coher_dest_base_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_2_t f;
+} coher_dest_base_2_u;
+
+
+/*
+ * COHER_DEST_BASE_3 struct
+ */
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000
+
+#define COHER_DEST_BASE_3_MASK \
+     (COHER_DEST_BASE_3_DEST_BASE_3_MASK)
+
+#define COHER_DEST_BASE_3(dest_base_3) \
+     ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT))
+
+#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \
+     ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \
+     coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+     } coher_dest_base_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_3_t f;
+} coher_dest_base_3_u;
+
+
+/*
+ * COHER_DEST_BASE_4 struct
+ */
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000
+
+#define COHER_DEST_BASE_4_MASK \
+     (COHER_DEST_BASE_4_DEST_BASE_4_MASK)
+
+#define COHER_DEST_BASE_4(dest_base_4) \
+     ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT))
+
+#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \
+     ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \
+     coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+     } coher_dest_base_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_4_t f;
+} coher_dest_base_4_u;
+
+
+/*
+ * COHER_DEST_BASE_5 struct
+ */
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000
+
+#define COHER_DEST_BASE_5_MASK \
+     (COHER_DEST_BASE_5_DEST_BASE_5_MASK)
+
+#define COHER_DEST_BASE_5(dest_base_5) \
+     ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT))
+
+#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \
+     ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \
+     coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+     } coher_dest_base_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_5_t f;
+} coher_dest_base_5_u;
+
+
+/*
+ * COHER_DEST_BASE_6 struct
+ */
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000
+
+#define COHER_DEST_BASE_6_MASK \
+     (COHER_DEST_BASE_6_DEST_BASE_6_MASK)
+
+#define COHER_DEST_BASE_6(dest_base_6) \
+     ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT))
+
+#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \
+     ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \
+     coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+     } coher_dest_base_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_6_t f;
+} coher_dest_base_6_u;
+
+
+/*
+ * COHER_DEST_BASE_7 struct
+ */
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000
+
+#define COHER_DEST_BASE_7_MASK \
+     (COHER_DEST_BASE_7_DEST_BASE_7_MASK)
+
+#define COHER_DEST_BASE_7(dest_base_7) \
+     ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT))
+
+#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \
+     ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \
+     coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+     } coher_dest_base_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_7_t f;
+} coher_dest_base_7_u;
+
+
+#endif
+
+
+#if !defined (_RBBM_FIDDLE_H)
+#define _RBBM_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * WAIT_UNTIL struct
+ */
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_VSYNC_SIZE     1
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1
+#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2
+#define WAIT_UNTIL_WAIT_VSYNC_SHIFT    3
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6
+#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT  10
+#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT  14
+#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT  15
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK  0x00000002
+#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK  0x00000004
+#define WAIT_UNTIL_WAIT_VSYNC_MASK     0x00000008
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040
+#define WAIT_UNTIL_WAIT_CMDFIFO_MASK   0x00000400
+#define WAIT_UNTIL_WAIT_2D_IDLE_MASK   0x00004000
+#define WAIT_UNTIL_WAIT_3D_IDLE_MASK   0x00008000
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000
+
+#define WAIT_UNTIL_MASK \
+     (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \
+      WAIT_UNTIL_WAIT_CMDFIFO_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_CMDFIFO_ENTRIES_MASK)
+
+#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \
+     ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \
+      (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \
+      (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \
+      (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \
+      (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \
+      (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \
+      (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \
+      (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \
+      (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \
+      (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \
+      (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \
+      (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT))
+
+#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \
+     ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 1;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int                                : 2;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 8;
+     } wait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 8;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int                                : 1;
+     } wait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+
+/*
+ * RBBM_ISYNC_CNTL struct
+ */
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020
+
+#define RBBM_ISYNC_CNTL_MASK \
+     (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \
+      RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK)
+
+#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \
+     ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \
+      (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT))
+
+#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 4;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int                                : 26;
+     } rbbm_isync_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 26;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int                                : 4;
+     } rbbm_isync_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_isync_cntl_t f;
+} rbbm_isync_cntl_u;
+
+
+/*
+ * RBBM_STATUS struct
+ */
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5
+#define RBBM_STATUS_TC_BUSY_SIZE       1
+#define RBBM_STATUS_HIRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CPRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_PFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1
+#define RBBM_STATUS_RBBM_WU_BUSY_SIZE  1
+#define RBBM_STATUS_CP_NRT_BUSY_SIZE   1
+#define RBBM_STATUS_MH_BUSY_SIZE       1
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1
+#define RBBM_STATUS_SX_BUSY_SIZE       1
+#define RBBM_STATUS_TPC_BUSY_SIZE      1
+#define RBBM_STATUS_SC_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_PA_BUSY_SIZE       1
+#define RBBM_STATUS_VGT_BUSY_SIZE      1
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1
+#define RBBM_STATUS_RB_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_GUI_ACTIVE_SIZE    1
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0
+#define RBBM_STATUS_TC_BUSY_SHIFT      5
+#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8
+#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9
+#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10
+#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12
+#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14
+#define RBBM_STATUS_CP_NRT_BUSY_SHIFT  16
+#define RBBM_STATUS_MH_BUSY_SHIFT      18
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19
+#define RBBM_STATUS_SX_BUSY_SHIFT      21
+#define RBBM_STATUS_TPC_BUSY_SHIFT     22
+#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24
+#define RBBM_STATUS_PA_BUSY_SHIFT      25
+#define RBBM_STATUS_VGT_BUSY_SHIFT     26
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28
+#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30
+#define RBBM_STATUS_GUI_ACTIVE_SHIFT   31
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f
+#define RBBM_STATUS_TC_BUSY_MASK       0x00000020
+#define RBBM_STATUS_HIRQ_PENDING_MASK  0x00000100
+#define RBBM_STATUS_CPRQ_PENDING_MASK  0x00000200
+#define RBBM_STATUS_CFRQ_PENDING_MASK  0x00000400
+#define RBBM_STATUS_PFRQ_PENDING_MASK  0x00000800
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000
+#define RBBM_STATUS_RBBM_WU_BUSY_MASK  0x00004000
+#define RBBM_STATUS_CP_NRT_BUSY_MASK   0x00010000
+#define RBBM_STATUS_MH_BUSY_MASK       0x00040000
+#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000
+#define RBBM_STATUS_SX_BUSY_MASK       0x00200000
+#define RBBM_STATUS_TPC_BUSY_MASK      0x00400000
+#define RBBM_STATUS_SC_CNTX_BUSY_MASK  0x01000000
+#define RBBM_STATUS_PA_BUSY_MASK       0x02000000
+#define RBBM_STATUS_VGT_BUSY_MASK      0x04000000
+#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000
+#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000
+#define RBBM_STATUS_RB_CNTX_BUSY_MASK  0x40000000
+#define RBBM_STATUS_GUI_ACTIVE_MASK    0x80000000
+
+#define RBBM_STATUS_MASK \
+     (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \
+      RBBM_STATUS_TC_BUSY_MASK | \
+      RBBM_STATUS_HIRQ_PENDING_MASK | \
+      RBBM_STATUS_CPRQ_PENDING_MASK | \
+      RBBM_STATUS_CFRQ_PENDING_MASK | \
+      RBBM_STATUS_PFRQ_PENDING_MASK | \
+      RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \
+      RBBM_STATUS_RBBM_WU_BUSY_MASK | \
+      RBBM_STATUS_CP_NRT_BUSY_MASK | \
+      RBBM_STATUS_MH_BUSY_MASK | \
+      RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \
+      RBBM_STATUS_SX_BUSY_MASK | \
+      RBBM_STATUS_TPC_BUSY_MASK | \
+      RBBM_STATUS_SC_CNTX_BUSY_MASK | \
+      RBBM_STATUS_PA_BUSY_MASK | \
+      RBBM_STATUS_VGT_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \
+      RBBM_STATUS_RB_CNTX_BUSY_MASK | \
+      RBBM_STATUS_GUI_ACTIVE_MASK)
+
+#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \
+     ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \
+      (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \
+      (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \
+      (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \
+      (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \
+      (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \
+      (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \
+      (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \
+      (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \
+      (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \
+      (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \
+      (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \
+      (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \
+      (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \
+      (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \
+      (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \
+      (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \
+      (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \
+      (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \
+      (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT))
+
+#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+     } rbbm_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int                                : 2;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+     } rbbm_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+
+/*
+ * RBBM_DSPLY struct
+ */
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000
+
+#define RBBM_DSPLY_MASK \
+     (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \
+      RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK)
+
+#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \
+     ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \
+      (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \
+      (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \
+      (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \
+      (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \
+      (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \
+      (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \
+      (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \
+      (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \
+      (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \
+      (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \
+      (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \
+      (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \
+      (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \
+      (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \
+      (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \
+      (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \
+      (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \
+      (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \
+      (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \
+      (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \
+      (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \
+      (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \
+      (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \
+      (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT))
+
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+     } rbbm_dsply_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+     } rbbm_dsply_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_dsply_t f;
+} rbbm_dsply_u;
+
+
+/*
+ * RBBM_RENDER_LATEST struct
+ */
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000
+
+#define RBBM_RENDER_LATEST_MASK \
+     (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK)
+
+#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \
+     ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \
+      (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \
+      (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \
+      (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT))
+
+#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+     } rbbm_render_latest_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+     } rbbm_render_latest_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_render_latest_t f;
+} rbbm_render_latest_u;
+
+
+/*
+ * RBBM_RTL_RELEASE struct
+ */
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0
+
+#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff
+
+#define RBBM_RTL_RELEASE_MASK \
+     (RBBM_RTL_RELEASE_CHANGELIST_MASK)
+
+#define RBBM_RTL_RELEASE(changelist) \
+     ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT))
+
+#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \
+     ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \
+     rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_rtl_release_t f;
+} rbbm_rtl_release_u;
+
+
+/*
+ * RBBM_PATCH_RELEASE struct
+ */
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000
+
+#define RBBM_PATCH_RELEASE_MASK \
+     (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \
+      RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \
+      RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK)
+
+#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \
+     ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \
+      (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \
+      (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT))
+
+#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+     } rbbm_patch_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+     } rbbm_patch_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_patch_release_t f;
+} rbbm_patch_release_u;
+
+
+/*
+ * RBBM_AUXILIARY_CONFIG struct
+ */
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff
+
+#define RBBM_AUXILIARY_CONFIG_MASK \
+     (RBBM_AUXILIARY_CONFIG_RESERVED_MASK)
+
+#define RBBM_AUXILIARY_CONFIG(reserved) \
+     ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT))
+
+#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \
+     ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \
+     rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_auxiliary_config_t f;
+} rbbm_auxiliary_config_u;
+
+
+/*
+ * RBBM_PERIPHID0 struct
+ */
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0
+
+#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff
+
+#define RBBM_PERIPHID0_MASK \
+     (RBBM_PERIPHID0_PARTNUMBER0_MASK)
+
+#define RBBM_PERIPHID0(partnumber0) \
+     ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT))
+
+#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \
+     ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \
+     rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int                                : 24;
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+     } rbbm_periphid0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid0_t f;
+} rbbm_periphid0_u;
+
+
+/*
+ * RBBM_PERIPHID1 struct
+ */
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4
+#define RBBM_PERIPHID1_DESIGNER0_SIZE  4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0
+#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f
+#define RBBM_PERIPHID1_DESIGNER0_MASK  0x000000f0
+
+#define RBBM_PERIPHID1_MASK \
+     (RBBM_PERIPHID1_PARTNUMBER1_MASK | \
+      RBBM_PERIPHID1_DESIGNER0_MASK)
+
+#define RBBM_PERIPHID1(partnumber1, designer0) \
+     ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \
+      (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT))
+
+#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int                                : 24;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+     } rbbm_periphid1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid1_t f;
+} rbbm_periphid1_u;
+
+
+/*
+ * RBBM_PERIPHID2 struct
+ */
+
+#define RBBM_PERIPHID2_DESIGNER1_SIZE  4
+#define RBBM_PERIPHID2_REVISION_SIZE   4
+
+#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0
+#define RBBM_PERIPHID2_REVISION_SHIFT  4
+
+#define RBBM_PERIPHID2_DESIGNER1_MASK  0x0000000f
+#define RBBM_PERIPHID2_REVISION_MASK   0x000000f0
+
+#define RBBM_PERIPHID2_MASK \
+     (RBBM_PERIPHID2_DESIGNER1_MASK | \
+      RBBM_PERIPHID2_REVISION_MASK)
+
+#define RBBM_PERIPHID2(designer1, revision) \
+     ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \
+      (revision << RBBM_PERIPHID2_REVISION_SHIFT))
+
+#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT)
+
+#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int                                : 24;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+     } rbbm_periphid2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid2_t f;
+} rbbm_periphid2_u;
+
+
+/*
+ * RBBM_PERIPHID3 struct
+ */
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_CONTINUATION_SIZE 1
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4
+#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c
+#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030
+#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080
+
+#define RBBM_PERIPHID3_MASK \
+     (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \
+      RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \
+      RBBM_PERIPHID3_MH_INTERFACE_MASK | \
+      RBBM_PERIPHID3_CONTINUATION_MASK)
+
+#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \
+     ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \
+      (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \
+      (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \
+      (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT))
+
+#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int                                : 1;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int                                : 24;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+     } rbbm_periphid3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid3_t f;
+} rbbm_periphid3_u;
+
+
+/*
+ * RBBM_CNTL struct
+ */
+
+#define RBBM_CNTL_READ_TIMEOUT_SIZE    8
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9
+
+#define RBBM_CNTL_READ_TIMEOUT_SHIFT   0
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8
+
+#define RBBM_CNTL_READ_TIMEOUT_MASK    0x000000ff
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00
+
+#define RBBM_CNTL_MASK \
+     (RBBM_CNTL_READ_TIMEOUT_MASK | \
+      RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK)
+
+#define RBBM_CNTL(read_timeout, regclk_deassert_time) \
+     ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \
+      (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT))
+
+#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int                                : 15;
+     } rbbm_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int                                : 15;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+     } rbbm_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+
+/*
+ * RBBM_SKEW_CNTL struct
+ */
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f
+#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0
+
+#define RBBM_SKEW_CNTL_MASK \
+     (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \
+      RBBM_SKEW_CNTL_SKEW_COUNT_MASK)
+
+#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \
+     ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \
+      (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT))
+
+#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int                                : 22;
+     } rbbm_skew_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int                                : 22;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+     } rbbm_skew_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_skew_cntl_t f;
+} rbbm_skew_cntl_u;
+
+
+/*
+ * RBBM_SOFT_RESET struct
+ */
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000
+
+#define RBBM_SOFT_RESET_MASK \
+     (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK)
+
+#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \
+     ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \
+      (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \
+      (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \
+      (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \
+      (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \
+      (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \
+      (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \
+      (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \
+      (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT))
+
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int                                : 15;
+     } rbbm_soft_reset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int                                : 15;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+     } rbbm_soft_reset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE1 struct
+ */
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000
+
+#define RBBM_PM_OVERRIDE1_MASK \
+     (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \
+     ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override1_t f;
+} rbbm_pm_override1_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE2 struct
+ */
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800
+
+#define RBBM_PM_OVERRIDE2_MASK \
+     (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \
+     ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \
+      (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \
+      (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int                                : 20;
+     } rbbm_pm_override2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int                                : 20;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override2_t f;
+} rbbm_pm_override2_u;
+
+
+/*
+ * GC_SYS_IDLE struct
+ */
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000
+
+#define GC_SYS_IDLE_MASK \
+     (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK)
+
+#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \
+     ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \
+      (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \
+      (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \
+      (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \
+      (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \
+      (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \
+      (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT))
+
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+     } gc_sys_idle_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+     } gc_sys_idle_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gc_sys_idle_t f;
+} gc_sys_idle_u;
+
+
+/*
+ * NQWAIT_UNTIL struct
+ */
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001
+
+#define NQWAIT_UNTIL_MASK \
+     (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK)
+
+#define NQWAIT_UNTIL(wait_gui_idle) \
+     ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT))
+
+#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \
+     ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \
+     nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+          unsigned int                                : 31;
+     } nqwait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int                                : 31;
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+     } nqwait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+
+/*
+ * RBBM_DEBUG_OUT struct
+ */
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff
+
+#define RBBM_DEBUG_OUT_MASK \
+     (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK)
+
+#define RBBM_DEBUG_OUT(debug_bus_out) \
+     ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT))
+
+#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \
+     ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \
+     rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_out_t f;
+} rbbm_debug_out_u;
+
+
+/*
+ * RBBM_DEBUG_CNTL struct
+ */
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00
+#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000
+
+#define RBBM_DEBUG_CNTL_MASK \
+     (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK)
+
+#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \
+     ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \
+      (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \
+      (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \
+      (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \
+      (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \
+      (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT))
+
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+     } rbbm_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+     } rbbm_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_cntl_t f;
+} rbbm_debug_cntl_u;
+
+
+/*
+ * RBBM_DEBUG struct
+ */
+
+#define RBBM_DEBUG_IGNORE_RTR_SIZE     1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1
+
+#define RBBM_DEBUG_IGNORE_RTR_SHIFT    1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31
+
+#define RBBM_DEBUG_IGNORE_RTR_MASK     0x00000002
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000
+
+#define RBBM_DEBUG_MASK \
+     (RBBM_DEBUG_IGNORE_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \
+      RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \
+      RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK)
+
+#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \
+     ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \
+      (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \
+      (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \
+      (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \
+      (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \
+      (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \
+      (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \
+      (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \
+      (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \
+      (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \
+      (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \
+      (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT))
+
+#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int                                : 1;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int                                : 3;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 4;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+     } rbbm_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+          unsigned int                                : 6;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int                                : 4;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 3;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int                                : 1;
+     } rbbm_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+
+/*
+ * RBBM_READ_ERROR struct
+ */
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
+#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
+#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2
+#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30
+#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31
+
+#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000
+#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000
+
+#define RBBM_READ_ERROR_MASK \
+     (RBBM_READ_ERROR_READ_ADDRESS_MASK | \
+      RBBM_READ_ERROR_READ_REQUESTER_MASK | \
+      RBBM_READ_ERROR_READ_ERROR_MASK)
+
+#define RBBM_READ_ERROR(read_address, read_requester, read_error) \
+     ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \
+      (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \
+      (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT))
+
+#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int                                : 2;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+     } rbbm_read_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 2;
+     } rbbm_read_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_read_error_t f;
+} rbbm_read_error_u;
+
+
+/*
+ * RBBM_WAIT_IDLE_CLOCKS struct
+ */
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff
+
+#define RBBM_WAIT_IDLE_CLOCKS_MASK \
+     (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK)
+
+#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \
+     ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT))
+
+#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \
+     ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \
+     rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+          unsigned int                                : 24;
+     } rbbm_wait_idle_clocks_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int                                : 24;
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+     } rbbm_wait_idle_clocks_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_wait_idle_clocks_t f;
+} rbbm_wait_idle_clocks_u;
+
+
+/*
+ * RBBM_INT_CNTL struct
+ */
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000
+
+#define RBBM_INT_CNTL_MASK \
+     (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \
+      RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \
+      RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK)
+
+#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \
+     ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \
+      (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \
+      (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT))
+
+#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+     } rbbm_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_cntl_t f;
+} rbbm_int_cntl_u;
+
+
+/*
+ * RBBM_INT_STATUS struct
+ */
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000
+
+#define RBBM_INT_STATUS_MASK \
+     (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \
+      RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \
+      RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK)
+
+#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \
+     ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \
+      (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \
+      (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT))
+
+#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+     } rbbm_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_status_t f;
+} rbbm_int_status_u;
+
+
+/*
+ * RBBM_INT_ACK struct
+ */
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000
+
+#define RBBM_INT_ACK_MASK \
+     (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \
+      RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \
+      RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK)
+
+#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \
+     ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \
+      (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \
+      (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT))
+
+#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+     } rbbm_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_ack_t f;
+} rbbm_int_ack_u;
+
+
+/*
+ * MASTER_INT_SIGNAL struct
+ */
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000
+#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000
+
+#define MASTER_INT_SIGNAL_MASK \
+     (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK)
+
+#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \
+     ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \
+      (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \
+      (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \
+      (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT))
+
+#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int                                : 5;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+     } master_int_signal_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 5;
+     } master_int_signal_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     master_int_signal_t f;
+} master_int_signal_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_SELECT struct
+ */
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f
+
+#define RBBM_PERFCOUNTER1_SELECT_MASK \
+     (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK)
+
+#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \
+     ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT))
+
+#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \
+     ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \
+     rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+          unsigned int                                : 26;
+     } rbbm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int                                : 26;
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+     } rbbm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_select_t f;
+} rbbm_perfcounter1_select_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_LO struct
+ */
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff
+
+#define RBBM_PERFCOUNTER1_LO_MASK \
+     (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK)
+
+#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \
+     ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT))
+
+#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \
+     ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \
+     rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_lo_t f;
+} rbbm_perfcounter1_lo_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_HI struct
+ */
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff
+
+#define RBBM_PERFCOUNTER1_HI_MASK \
+     (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK)
+
+#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \
+     ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT))
+
+#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \
+     ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \
+     rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+          unsigned int                                : 16;
+     } rbbm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+     } rbbm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_hi_t f;
+} rbbm_perfcounter1_hi_u;
+
+
+#endif
+
+
+#if !defined (_MH_FIDDLE_H)
+#define _MH_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * MH_ARBITER_CONFIG struct
+ */
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200
+#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000
+
+#define MH_ARBITER_CONFIG_MASK \
+     (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \
+      MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \
+      MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK)
+
+#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \
+     ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \
+      (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \
+      (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \
+      (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \
+      (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \
+      (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \
+      (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \
+      (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \
+      (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \
+      (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \
+      (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \
+      (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \
+      (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \
+      (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT))
+
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int                                : 5;
+     } mh_arbiter_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int                                : 5;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+     } mh_arbiter_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_arbiter_config_t f;
+} mh_arbiter_config_u;
+
+
+/*
+ * MH_CLNT_AXI_ID_REUSE struct
+ */
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000
+
+#define MH_CLNT_AXI_ID_REUSE_MASK \
+     (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \
+      MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \
+      MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK)
+
+#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \
+     ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \
+      (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \
+      (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \
+      (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \
+      (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \
+      (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \
+      (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT))
+
+#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int                                : 17;
+     } mh_clnt_axi_id_reuse_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int                                : 17;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+     } mh_clnt_axi_id_reuse_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_clnt_axi_id_reuse_t f;
+} mh_clnt_axi_id_reuse_u;
+
+
+/*
+ * MH_INTERRUPT_MASK struct
+ */
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_MASK_MASK \
+     (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_mask_t f;
+} mh_interrupt_mask_u;
+
+
+/*
+ * MH_INTERRUPT_STATUS struct
+ */
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_STATUS_MASK \
+     (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_status_t f;
+} mh_interrupt_status_u;
+
+
+/*
+ * MH_INTERRUPT_CLEAR struct
+ */
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_CLEAR_MASK \
+     (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_clear_t f;
+} mh_interrupt_clear_u;
+
+
+/*
+ * MH_AXI_ERROR struct
+ */
+
+#define MH_AXI_ERROR_AXI_READ_ID_SIZE  3
+#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1
+#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1
+
+#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3
+#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7
+
+#define MH_AXI_ERROR_AXI_READ_ID_MASK  0x00000007
+#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008
+#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080
+
+#define MH_AXI_ERROR_MASK \
+     (MH_AXI_ERROR_AXI_READ_ID_MASK | \
+      MH_AXI_ERROR_AXI_READ_ERROR_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ID_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ERROR_MASK)
+
+#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \
+     ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \
+      (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \
+      (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT))
+
+#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int                                : 24;
+     } mh_axi_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int                                : 24;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+     } mh_axi_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_error_t f;
+} mh_axi_error_u;
+
+
+/*
+ * MH_PERFCOUNTER0_SELECT struct
+ */
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_SELECT_MASK \
+     (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \
+     ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \
+     mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_select_t f;
+} mh_perfcounter0_select_u;
+
+
+/*
+ * MH_PERFCOUNTER1_SELECT struct
+ */
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_SELECT_MASK \
+     (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \
+     ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \
+     mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_select_t f;
+} mh_perfcounter1_select_u;
+
+
+/*
+ * MH_PERFCOUNTER0_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_CONFIG_MASK \
+     (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER0_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \
+     ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \
+     mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter0_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_config_t f;
+} mh_perfcounter0_config_u;
+
+
+/*
+ * MH_PERFCOUNTER1_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_CONFIG_MASK \
+     (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER1_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \
+     ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \
+     mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter1_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_config_t f;
+} mh_perfcounter1_config_u;
+
+
+/*
+ * MH_PERFCOUNTER0_LOW struct
+ */
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER0_LOW_MASK \
+     (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER0_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \
+     ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \
+     mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_low_t f;
+} mh_perfcounter0_low_u;
+
+
+/*
+ * MH_PERFCOUNTER1_LOW struct
+ */
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER1_LOW_MASK \
+     (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER1_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \
+     ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \
+     mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_low_t f;
+} mh_perfcounter1_low_u;
+
+
+/*
+ * MH_PERFCOUNTER0_HI struct
+ */
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER0_HI_MASK \
+     (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER0_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \
+     ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \
+     mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_hi_t f;
+} mh_perfcounter0_hi_u;
+
+
+/*
+ * MH_PERFCOUNTER1_HI struct
+ */
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER1_HI_MASK \
+     (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER1_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \
+     ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \
+     mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_hi_t f;
+} mh_perfcounter1_hi_u;
+
+
+/*
+ * MH_DEBUG_CTRL struct
+ */
+
+#define MH_DEBUG_CTRL_INDEX_SIZE       6
+
+#define MH_DEBUG_CTRL_INDEX_SHIFT      0
+
+#define MH_DEBUG_CTRL_INDEX_MASK       0x0000003f
+
+#define MH_DEBUG_CTRL_MASK \
+     (MH_DEBUG_CTRL_INDEX_MASK)
+
+#define MH_DEBUG_CTRL(index) \
+     ((index << MH_DEBUG_CTRL_INDEX_SHIFT))
+
+#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \
+     ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \
+     mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+          unsigned int                                : 26;
+     } mh_debug_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int                                : 26;
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+     } mh_debug_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_ctrl_t f;
+} mh_debug_ctrl_u;
+
+
+/*
+ * MH_DEBUG_DATA struct
+ */
+
+#define MH_DEBUG_DATA_DATA_SIZE        32
+
+#define MH_DEBUG_DATA_DATA_SHIFT       0
+
+#define MH_DEBUG_DATA_DATA_MASK        0xffffffff
+
+#define MH_DEBUG_DATA_MASK \
+     (MH_DEBUG_DATA_DATA_MASK)
+
+#define MH_DEBUG_DATA(data) \
+     ((data << MH_DEBUG_DATA_DATA_SHIFT))
+
+#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \
+     ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT)
+
+#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \
+     mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_data_t f;
+} mh_debug_data_u;
+
+
+/*
+ * MH_AXI_HALT_CONTROL struct
+ */
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001
+
+#define MH_AXI_HALT_CONTROL_MASK \
+     (MH_AXI_HALT_CONTROL_AXI_HALT_MASK)
+
+#define MH_AXI_HALT_CONTROL(axi_halt) \
+     ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT))
+
+#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \
+     ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \
+     mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+          unsigned int                                : 31;
+     } mh_axi_halt_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int                                : 31;
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+     } mh_axi_halt_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_halt_control_t f;
+} mh_axi_halt_control_u;
+
+
+/*
+ * MH_DEBUG_REG00 struct
+ */
+
+#define MH_DEBUG_REG00_MH_BUSY_SIZE    1
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1
+#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1
+#define MH_DEBUG_REG00_TCD_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_TCD_FULL_SIZE   1
+#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1
+#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_ARQ_FULL_SIZE   1
+#define MH_DEBUG_REG00_WDB_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_WDB_FULL_SIZE   1
+#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1
+
+#define MH_DEBUG_REG00_MH_BUSY_SHIFT   0
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1
+#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2
+#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3
+#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5
+#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6
+#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7
+#define MH_DEBUG_REG00_TCD_FULL_SHIFT  8
+#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9
+#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11
+#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12
+#define MH_DEBUG_REG00_ARQ_FULL_SHIFT  13
+#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14
+#define MH_DEBUG_REG00_WDB_FULL_SHIFT  15
+#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16
+#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17
+#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18
+#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19
+#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20
+#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21
+#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22
+#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23
+#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24
+#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28
+
+#define MH_DEBUG_REG00_MH_BUSY_MASK    0x00000001
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002
+#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004
+#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008
+#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020
+#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040
+#define MH_DEBUG_REG00_TCD_EMPTY_MASK  0x00000080
+#define MH_DEBUG_REG00_TCD_FULL_MASK   0x00000100
+#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200
+#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800
+#define MH_DEBUG_REG00_ARQ_EMPTY_MASK  0x00001000
+#define MH_DEBUG_REG00_ARQ_FULL_MASK   0x00002000
+#define MH_DEBUG_REG00_WDB_EMPTY_MASK  0x00004000
+#define MH_DEBUG_REG00_WDB_FULL_MASK   0x00008000
+#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000
+#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000
+#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000
+#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000
+#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000
+#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000
+#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000
+#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000
+#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000
+#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000
+#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000
+#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000
+#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000
+
+#define MH_DEBUG_REG00_MASK \
+     (MH_DEBUG_REG00_MH_BUSY_MASK | \
+      MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \
+      MH_DEBUG_REG00_CP_REQUEST_MASK | \
+      MH_DEBUG_REG00_VGT_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \
+      MH_DEBUG_REG00_TC_CAM_FULL_MASK | \
+      MH_DEBUG_REG00_TCD_EMPTY_MASK | \
+      MH_DEBUG_REG00_TCD_FULL_MASK | \
+      MH_DEBUG_REG00_RB_REQUEST_MASK | \
+      MH_DEBUG_REG00_PA_REQUEST_MASK | \
+      MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \
+      MH_DEBUG_REG00_ARQ_EMPTY_MASK | \
+      MH_DEBUG_REG00_ARQ_FULL_MASK | \
+      MH_DEBUG_REG00_WDB_EMPTY_MASK | \
+      MH_DEBUG_REG00_WDB_FULL_MASK | \
+      MH_DEBUG_REG00_AXI_AVALID_MASK | \
+      MH_DEBUG_REG00_AXI_AREADY_MASK | \
+      MH_DEBUG_REG00_AXI_ARVALID_MASK | \
+      MH_DEBUG_REG00_AXI_ARREADY_MASK | \
+      MH_DEBUG_REG00_AXI_WVALID_MASK | \
+      MH_DEBUG_REG00_AXI_WREADY_MASK | \
+      MH_DEBUG_REG00_AXI_RVALID_MASK | \
+      MH_DEBUG_REG00_AXI_RREADY_MASK | \
+      MH_DEBUG_REG00_AXI_BVALID_MASK | \
+      MH_DEBUG_REG00_AXI_BREADY_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \
+      MH_DEBUG_REG00_AXI_RDY_ENA_MASK)
+
+#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \
+     ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \
+      (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \
+      (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \
+      (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \
+      (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \
+      (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \
+      (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \
+      (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \
+      (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \
+      (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \
+      (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \
+      (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \
+      (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \
+      (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \
+      (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \
+      (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \
+      (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \
+      (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \
+      (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \
+      (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \
+      (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \
+      (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \
+      (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \
+      (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \
+      (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \
+      (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \
+      (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \
+      (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \
+      (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT))
+
+#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int                                : 3;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+     } mh_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg00_t f;
+} mh_debug_reg00_u;
+
+
+/*
+ * MH_DEBUG_REG01 struct
+ */
+
+#define MH_DEBUG_REG01_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1
+#define MH_DEBUG_REG01_CP_TAG_q_SIZE   3
+#define MH_DEBUG_REG01_CP_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_TAG_q_SIZE  1
+#define MH_DEBUG_REG01_TC_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_TC_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_TC_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG01_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG01_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_PA_RTR_q_SIZE   1
+
+#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0
+#define MH_DEBUG_REG01_CP_RTR_q_SHIFT  1
+#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2
+#define MH_DEBUG_REG01_CP_TAG_q_SHIFT  3
+#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6
+#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7
+#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8
+#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9
+#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10
+#define MH_DEBUG_REG01_TC_RTR_q_SHIFT  11
+#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14
+#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15
+#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16
+#define MH_DEBUG_REG01_RB_RTR_q_SHIFT  17
+#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18
+#define MH_DEBUG_REG01_PA_RTR_q_SHIFT  19
+
+#define MH_DEBUG_REG01_CP_SEND_q_MASK  0x00000001
+#define MH_DEBUG_REG01_CP_RTR_q_MASK   0x00000002
+#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004
+#define MH_DEBUG_REG01_CP_TAG_q_MASK   0x00000038
+#define MH_DEBUG_REG01_CP_BLEN_q_MASK  0x00000040
+#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080
+#define MH_DEBUG_REG01_VGT_RTR_q_MASK  0x00000100
+#define MH_DEBUG_REG01_VGT_TAG_q_MASK  0x00000200
+#define MH_DEBUG_REG01_TC_SEND_q_MASK  0x00000400
+#define MH_DEBUG_REG01_TC_RTR_q_MASK   0x00000800
+#define MH_DEBUG_REG01_TC_BLEN_q_MASK  0x00001000
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000
+#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000
+#define MH_DEBUG_REG01_RB_SEND_q_MASK  0x00010000
+#define MH_DEBUG_REG01_RB_RTR_q_MASK   0x00020000
+#define MH_DEBUG_REG01_PA_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG01_PA_RTR_q_MASK   0x00080000
+
+#define MH_DEBUG_REG01_MASK \
+     (MH_DEBUG_REG01_CP_SEND_q_MASK | \
+      MH_DEBUG_REG01_CP_RTR_q_MASK | \
+      MH_DEBUG_REG01_CP_WRITE_q_MASK | \
+      MH_DEBUG_REG01_CP_TAG_q_MASK | \
+      MH_DEBUG_REG01_CP_BLEN_q_MASK | \
+      MH_DEBUG_REG01_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG01_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG01_VGT_TAG_q_MASK | \
+      MH_DEBUG_REG01_TC_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_BLEN_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_MH_written_MASK | \
+      MH_DEBUG_REG01_RB_SEND_q_MASK | \
+      MH_DEBUG_REG01_RB_RTR_q_MASK | \
+      MH_DEBUG_REG01_PA_SEND_q_MASK | \
+      MH_DEBUG_REG01_PA_RTR_q_MASK)
+
+#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \
+     ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \
+      (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \
+      (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \
+      (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \
+      (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \
+      (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \
+      (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \
+      (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT))
+
+#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int                                : 12;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+     } mh_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg01_t f;
+} mh_debug_reg01_u;
+
+
+/*
+ * MH_DEBUG_REG02 struct
+ */
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3
+#define MH_DEBUG_REG02_RDC_RID_SIZE    3
+#define MH_DEBUG_REG02_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1
+#define MH_DEBUG_REG02_BRC_BID_SIZE    3
+#define MH_DEBUG_REG02_BRC_BRESP_SIZE  2
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3
+#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4
+#define MH_DEBUG_REG02_RDC_RID_SHIFT   7
+#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12
+#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13
+#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14
+#define MH_DEBUG_REG02_BRC_BID_SHIFT   15
+#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008
+#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070
+#define MH_DEBUG_REG02_RDC_RID_MASK    0x00000380
+#define MH_DEBUG_REG02_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000
+#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000
+#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000
+#define MH_DEBUG_REG02_BRC_BID_MASK    0x00038000
+#define MH_DEBUG_REG02_BRC_BRESP_MASK  0x000c0000
+
+#define MH_DEBUG_REG02_MASK \
+     (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_tag_MASK | \
+      MH_DEBUG_REG02_RDC_RID_MASK | \
+      MH_DEBUG_REG02_RDC_RRESP_MASK | \
+      MH_DEBUG_REG02_MH_CP_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_RB_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_PA_writeclean_MASK | \
+      MH_DEBUG_REG02_BRC_BID_MASK | \
+      MH_DEBUG_REG02_BRC_BRESP_MASK)
+
+#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \
+     ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \
+      (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \
+      (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \
+      (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \
+      (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \
+      (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \
+      (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \
+      (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT))
+
+#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int                                : 12;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+     } mh_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg02_t f;
+} mh_debug_reg02_u;
+
+
+/*
+ * MH_DEBUG_REG03 struct
+ */
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG03_MASK \
+     (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK)
+
+#define MH_DEBUG_REG03(mh_clnt_data_31_0) \
+     ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \
+     ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \
+     mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg03_t f;
+} mh_debug_reg03_u;
+
+
+/*
+ * MH_DEBUG_REG04 struct
+ */
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG04_MASK \
+     (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK)
+
+#define MH_DEBUG_REG04(mh_clnt_data_63_32) \
+     ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \
+     ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \
+     mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg04_t f;
+} mh_debug_reg04_u;
+
+
+/*
+ * MH_DEBUG_REG05 struct
+ */
+
+#define MH_DEBUG_REG05_CP_MH_send_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_tag_SIZE  3
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0
+#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1
+#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002
+#define MH_DEBUG_REG05_CP_MH_tag_MASK  0x0000001c
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG05_MASK \
+     (MH_DEBUG_REG05_CP_MH_send_MASK | \
+      MH_DEBUG_REG05_CP_MH_write_MASK | \
+      MH_DEBUG_REG05_CP_MH_tag_MASK | \
+      MH_DEBUG_REG05_CP_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \
+     ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \
+      (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \
+      (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+     } mh_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+     } mh_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg05_t f;
+} mh_debug_reg05_u;
+
+
+/*
+ * MH_DEBUG_REG06 struct
+ */
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG06_MASK \
+     (MH_DEBUG_REG06_CP_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG06(cp_mh_data_31_0) \
+     ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \
+     ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \
+     mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg06_t f;
+} mh_debug_reg06_u;
+
+
+/*
+ * MH_DEBUG_REG07 struct
+ */
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG07_MASK \
+     (MH_DEBUG_REG07_CP_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG07(cp_mh_data_63_32) \
+     ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \
+     ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \
+     mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg07_t f;
+} mh_debug_reg07_u;
+
+
+/*
+ * MH_DEBUG_REG08 struct
+ */
+
+#define MH_DEBUG_REG08_CP_MH_be_SIZE   8
+#define MH_DEBUG_REG08_RB_MH_be_SIZE   8
+#define MH_DEBUG_REG08_PA_MH_be_SIZE   8
+
+#define MH_DEBUG_REG08_CP_MH_be_SHIFT  0
+#define MH_DEBUG_REG08_RB_MH_be_SHIFT  8
+#define MH_DEBUG_REG08_PA_MH_be_SHIFT  16
+
+#define MH_DEBUG_REG08_CP_MH_be_MASK   0x000000ff
+#define MH_DEBUG_REG08_RB_MH_be_MASK   0x0000ff00
+#define MH_DEBUG_REG08_PA_MH_be_MASK   0x00ff0000
+
+#define MH_DEBUG_REG08_MASK \
+     (MH_DEBUG_REG08_CP_MH_be_MASK | \
+      MH_DEBUG_REG08_RB_MH_be_MASK | \
+      MH_DEBUG_REG08_PA_MH_be_MASK)
+
+#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \
+     ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \
+      (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \
+      (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT))
+
+#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int                                : 8;
+     } mh_debug_reg08_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int                                : 8;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+     } mh_debug_reg08_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg08_t f;
+} mh_debug_reg08_u;
+
+
+/*
+ * MH_DEBUG_REG09 struct
+ */
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3
+#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007
+#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008
+#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG09_MASK \
+     (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG09_VGT_MH_send_MASK | \
+      MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \
+      MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \
+     ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \
+      (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \
+      (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \
+      (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+     } mh_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg09_t f;
+} mh_debug_reg09_u;
+
+
+/*
+ * MH_DEBUG_REG10 struct
+ */
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2
+#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004
+#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG10_MASK \
+     (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG10_TC_MH_send_MASK | \
+      MH_DEBUG_REG10_TC_MH_mask_MASK | \
+      MH_DEBUG_REG10_TC_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \
+      (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \
+      (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+     } mh_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg10_t f;
+} mh_debug_reg10_u;
+
+
+/*
+ * MH_DEBUG_REG11 struct
+ */
+
+#define MH_DEBUG_REG11_TC_MH_info_SIZE 25
+#define MH_DEBUG_REG11_TC_MH_send_SIZE 1
+
+#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0
+#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25
+
+#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff
+#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000
+
+#define MH_DEBUG_REG11_MASK \
+     (MH_DEBUG_REG11_TC_MH_info_MASK | \
+      MH_DEBUG_REG11_TC_MH_send_MASK)
+
+#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \
+     ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT))
+
+#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int                                : 6;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+     } mh_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg11_t f;
+} mh_debug_reg11_u;
+
+
+/*
+ * MH_DEBUG_REG12 struct
+ */
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1
+#define MH_DEBUG_REG12_TC_MH_written_SIZE 1
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25
+#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000
+#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000
+
+#define MH_DEBUG_REG12_MASK \
+     (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \
+      MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \
+      MH_DEBUG_REG12_TC_MH_written_MASK)
+
+#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \
+     ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \
+      (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT))
+
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int                                : 5;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+     } mh_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg12_t f;
+} mh_debug_reg12_u;
+
+
+/*
+ * MH_DEBUG_REG13 struct
+ */
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004
+#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG13_MASK \
+     (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK)
+
+#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \
+      (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \
+      (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT))
+
+#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+     } mh_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg13_t f;
+} mh_debug_reg13_u;
+
+
+/*
+ * MH_DEBUG_REG14 struct
+ */
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff
+#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000
+
+#define MH_DEBUG_REG14_MASK \
+     (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \
+      MH_DEBUG_REG14_TC_ROQ_SEND_MASK)
+
+#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \
+     ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT))
+
+#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int                                : 6;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+     } mh_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg14_t f;
+} mh_debug_reg14_u;
+
+
+/*
+ * MH_DEBUG_REG15 struct
+ */
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG15_RB_MH_send_SIZE 1
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG15_MASK \
+     (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG15_RB_MH_send_MASK | \
+      MH_DEBUG_REG15_RB_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \
+      (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \
+      (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+     } mh_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg15_t f;
+} mh_debug_reg15_u;
+
+
+/*
+ * MH_DEBUG_REG16 struct
+ */
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG16_MASK \
+     (MH_DEBUG_REG16_RB_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG16(rb_mh_data_31_0) \
+     ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \
+     ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \
+     mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg16_t f;
+} mh_debug_reg16_u;
+
+
+/*
+ * MH_DEBUG_REG17 struct
+ */
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG17_MASK \
+     (MH_DEBUG_REG17_RB_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG17(rb_mh_data_63_32) \
+     ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg17_t f;
+} mh_debug_reg17_u;
+
+
+/*
+ * MH_DEBUG_REG18 struct
+ */
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG18_PA_MH_send_SIZE 1
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG18_MASK \
+     (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG18_PA_MH_send_MASK | \
+      MH_DEBUG_REG18_PA_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \
+      (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \
+      (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+     } mh_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg18_t f;
+} mh_debug_reg18_u;
+
+
+/*
+ * MH_DEBUG_REG19 struct
+ */
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG19_MASK \
+     (MH_DEBUG_REG19_PA_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG19(pa_mh_data_31_0) \
+     ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg19_t f;
+} mh_debug_reg19_u;
+
+
+/*
+ * MH_DEBUG_REG20 struct
+ */
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG20_MASK \
+     (MH_DEBUG_REG20_PA_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG20(pa_mh_data_63_32) \
+     ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg20_t f;
+} mh_debug_reg20_u;
+
+
+/*
+ * MH_DEBUG_REG21 struct
+ */
+
+#define MH_DEBUG_REG21_AVALID_q_SIZE   1
+#define MH_DEBUG_REG21_AREADY_q_SIZE   1
+#define MH_DEBUG_REG21_AID_q_SIZE      3
+#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3
+#define MH_DEBUG_REG21_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG21_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG21_ARID_q_SIZE     3
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG21_RVALID_q_SIZE   1
+#define MH_DEBUG_REG21_RREADY_q_SIZE   1
+#define MH_DEBUG_REG21_RLAST_q_SIZE    1
+#define MH_DEBUG_REG21_RID_q_SIZE      3
+#define MH_DEBUG_REG21_WVALID_q_SIZE   1
+#define MH_DEBUG_REG21_WREADY_q_SIZE   1
+#define MH_DEBUG_REG21_WLAST_q_SIZE    1
+#define MH_DEBUG_REG21_WID_q_SIZE      3
+#define MH_DEBUG_REG21_BVALID_q_SIZE   1
+#define MH_DEBUG_REG21_BREADY_q_SIZE   1
+#define MH_DEBUG_REG21_BID_q_SIZE      3
+
+#define MH_DEBUG_REG21_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG21_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG21_AID_q_SHIFT     2
+#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5
+#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8
+#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9
+#define MH_DEBUG_REG21_ARID_q_SHIFT    10
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13
+#define MH_DEBUG_REG21_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG21_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG21_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG21_RID_q_SHIFT     18
+#define MH_DEBUG_REG21_WVALID_q_SHIFT  21
+#define MH_DEBUG_REG21_WREADY_q_SHIFT  22
+#define MH_DEBUG_REG21_WLAST_q_SHIFT   23
+#define MH_DEBUG_REG21_WID_q_SHIFT     24
+#define MH_DEBUG_REG21_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG21_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG21_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG21_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG21_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG21_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0
+#define MH_DEBUG_REG21_ARVALID_q_MASK  0x00000100
+#define MH_DEBUG_REG21_ARREADY_q_MASK  0x00000200
+#define MH_DEBUG_REG21_ARID_q_MASK     0x00001c00
+#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000
+#define MH_DEBUG_REG21_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG21_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG21_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG21_RID_q_MASK      0x001c0000
+#define MH_DEBUG_REG21_WVALID_q_MASK   0x00200000
+#define MH_DEBUG_REG21_WREADY_q_MASK   0x00400000
+#define MH_DEBUG_REG21_WLAST_q_MASK    0x00800000
+#define MH_DEBUG_REG21_WID_q_MASK      0x07000000
+#define MH_DEBUG_REG21_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG21_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG21_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG21_MASK \
+     (MH_DEBUG_REG21_AVALID_q_MASK | \
+      MH_DEBUG_REG21_AREADY_q_MASK | \
+      MH_DEBUG_REG21_AID_q_MASK | \
+      MH_DEBUG_REG21_ALEN_q_2_0_MASK | \
+      MH_DEBUG_REG21_ARVALID_q_MASK | \
+      MH_DEBUG_REG21_ARREADY_q_MASK | \
+      MH_DEBUG_REG21_ARID_q_MASK | \
+      MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \
+      MH_DEBUG_REG21_RVALID_q_MASK | \
+      MH_DEBUG_REG21_RREADY_q_MASK | \
+      MH_DEBUG_REG21_RLAST_q_MASK | \
+      MH_DEBUG_REG21_RID_q_MASK | \
+      MH_DEBUG_REG21_WVALID_q_MASK | \
+      MH_DEBUG_REG21_WREADY_q_MASK | \
+      MH_DEBUG_REG21_WLAST_q_MASK | \
+      MH_DEBUG_REG21_WID_q_MASK | \
+      MH_DEBUG_REG21_BVALID_q_MASK | \
+      MH_DEBUG_REG21_BREADY_q_MASK | \
+      MH_DEBUG_REG21_BID_q_MASK)
+
+#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \
+      (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \
+      (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \
+      (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG21_BID_q_SHIFT))
+
+#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT)
+
+#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg21_t f;
+} mh_debug_reg21_u;
+
+
+/*
+ * MH_DEBUG_REG22 struct
+ */
+
+#define MH_DEBUG_REG22_AVALID_q_SIZE   1
+#define MH_DEBUG_REG22_AREADY_q_SIZE   1
+#define MH_DEBUG_REG22_AID_q_SIZE      3
+#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG22_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG22_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG22_ARID_q_SIZE     3
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1
+#define MH_DEBUG_REG22_WVALID_q_SIZE   1
+#define MH_DEBUG_REG22_WREADY_q_SIZE   1
+#define MH_DEBUG_REG22_WLAST_q_SIZE    1
+#define MH_DEBUG_REG22_WID_q_SIZE      3
+#define MH_DEBUG_REG22_WSTRB_q_SIZE    8
+#define MH_DEBUG_REG22_BVALID_q_SIZE   1
+#define MH_DEBUG_REG22_BREADY_q_SIZE   1
+#define MH_DEBUG_REG22_BID_q_SIZE      3
+
+#define MH_DEBUG_REG22_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG22_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG22_AID_q_SHIFT     2
+#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5
+#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7
+#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8
+#define MH_DEBUG_REG22_ARID_q_SHIFT    9
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12
+#define MH_DEBUG_REG22_WVALID_q_SHIFT  13
+#define MH_DEBUG_REG22_WREADY_q_SHIFT  14
+#define MH_DEBUG_REG22_WLAST_q_SHIFT   15
+#define MH_DEBUG_REG22_WID_q_SHIFT     16
+#define MH_DEBUG_REG22_WSTRB_q_SHIFT   19
+#define MH_DEBUG_REG22_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG22_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG22_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG22_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG22_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG22_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060
+#define MH_DEBUG_REG22_ARVALID_q_MASK  0x00000080
+#define MH_DEBUG_REG22_ARREADY_q_MASK  0x00000100
+#define MH_DEBUG_REG22_ARID_q_MASK     0x00000e00
+#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000
+#define MH_DEBUG_REG22_WVALID_q_MASK   0x00002000
+#define MH_DEBUG_REG22_WREADY_q_MASK   0x00004000
+#define MH_DEBUG_REG22_WLAST_q_MASK    0x00008000
+#define MH_DEBUG_REG22_WID_q_MASK      0x00070000
+#define MH_DEBUG_REG22_WSTRB_q_MASK    0x07f80000
+#define MH_DEBUG_REG22_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG22_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG22_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG22_MASK \
+     (MH_DEBUG_REG22_AVALID_q_MASK | \
+      MH_DEBUG_REG22_AREADY_q_MASK | \
+      MH_DEBUG_REG22_AID_q_MASK | \
+      MH_DEBUG_REG22_ALEN_q_1_0_MASK | \
+      MH_DEBUG_REG22_ARVALID_q_MASK | \
+      MH_DEBUG_REG22_ARREADY_q_MASK | \
+      MH_DEBUG_REG22_ARID_q_MASK | \
+      MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \
+      MH_DEBUG_REG22_WVALID_q_MASK | \
+      MH_DEBUG_REG22_WREADY_q_MASK | \
+      MH_DEBUG_REG22_WLAST_q_MASK | \
+      MH_DEBUG_REG22_WID_q_MASK | \
+      MH_DEBUG_REG22_WSTRB_q_MASK | \
+      MH_DEBUG_REG22_BVALID_q_MASK | \
+      MH_DEBUG_REG22_BREADY_q_MASK | \
+      MH_DEBUG_REG22_BID_q_MASK)
+
+#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \
+      (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \
+      (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \
+      (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG22_BID_q_SHIFT))
+
+#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT)
+
+#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg22_t f;
+} mh_debug_reg22_u;
+
+
+/*
+ * MH_DEBUG_REG23 struct
+ */
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001
+#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0
+
+#define MH_DEBUG_REG23_MASK \
+     (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_PAD_MASK)
+
+#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \
+     ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \
+      (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \
+      (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT))
+
+#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+     } mh_debug_reg23_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+     } mh_debug_reg23_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg23_t f;
+} mh_debug_reg23_u;
+
+
+/*
+ * MH_DEBUG_REG24 struct
+ */
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG24_REG_A_SIZE      14
+#define MH_DEBUG_REG24_REG_RE_SIZE     1
+#define MH_DEBUG_REG24_REG_WE_SIZE     1
+#define MH_DEBUG_REG24_BLOCK_RS_SIZE   1
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG24_REG_A_SHIFT     2
+#define MH_DEBUG_REG24_REG_RE_SHIFT    16
+#define MH_DEBUG_REG24_REG_WE_SHIFT    17
+#define MH_DEBUG_REG24_BLOCK_RS_SHIFT  18
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG24_REG_A_MASK      0x0000fffc
+#define MH_DEBUG_REG24_REG_RE_MASK     0x00010000
+#define MH_DEBUG_REG24_REG_WE_MASK     0x00020000
+#define MH_DEBUG_REG24_BLOCK_RS_MASK   0x00040000
+
+#define MH_DEBUG_REG24_MASK \
+     (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG24_REG_A_MASK | \
+      MH_DEBUG_REG24_REG_RE_MASK | \
+      MH_DEBUG_REG24_REG_WE_MASK | \
+      MH_DEBUG_REG24_BLOCK_RS_MASK)
+
+#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \
+     ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \
+      (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \
+      (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \
+      (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \
+      (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT))
+
+#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg24_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int                                : 13;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg24_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg24_t f;
+} mh_debug_reg24_u;
+
+
+/*
+ * MH_DEBUG_REG25 struct
+ */
+
+#define MH_DEBUG_REG25_REG_WD_SIZE     32
+
+#define MH_DEBUG_REG25_REG_WD_SHIFT    0
+
+#define MH_DEBUG_REG25_REG_WD_MASK     0xffffffff
+
+#define MH_DEBUG_REG25_MASK \
+     (MH_DEBUG_REG25_REG_WD_MASK)
+
+#define MH_DEBUG_REG25(reg_wd) \
+     ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT))
+
+#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg25_t f;
+} mh_debug_reg25_u;
+
+
+/*
+ * MH_DEBUG_REG26 struct
+ */
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1
+#define MH_DEBUG_REG26_CNT_q_SIZE      6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG26_MH_BUSY_d_SIZE  1
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+#define MH_DEBUG_REG26_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG26_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_PA_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG26_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG26_BRC_VALID_SIZE  1
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5
+#define MH_DEBUG_REG26_CNT_q_SHIFT     6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13
+#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17
+#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18
+#define MH_DEBUG_REG26_CP_RTR_q_SHIFT  19
+#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20
+#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23
+#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24
+#define MH_DEBUG_REG26_RB_RTR_q_SHIFT  25
+#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26
+#define MH_DEBUG_REG26_PA_RTR_q_SHIFT  27
+#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28
+#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29
+#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30
+#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008
+#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020
+#define MH_DEBUG_REG26_CNT_q_MASK      0x00000fc0
+#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG26_MH_BUSY_d_MASK  0x00004000
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000
+#define MH_DEBUG_REG26_CP_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG26_CP_RTR_q_MASK   0x00080000
+#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000
+#define MH_DEBUG_REG26_VGT_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000
+#define MH_DEBUG_REG26_RB_SEND_q_MASK  0x01000000
+#define MH_DEBUG_REG26_RB_RTR_q_MASK   0x02000000
+#define MH_DEBUG_REG26_PA_SEND_q_MASK  0x04000000
+#define MH_DEBUG_REG26_PA_RTR_q_MASK   0x08000000
+#define MH_DEBUG_REG26_RDC_VALID_MASK  0x10000000
+#define MH_DEBUG_REG26_RDC_RLAST_MASK  0x20000000
+#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000
+#define MH_DEBUG_REG26_BRC_VALID_MASK  0x80000000
+
+#define MH_DEBUG_REG26_MASK \
+     (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \
+      MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \
+      MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \
+      MH_DEBUG_REG26_CNT_q_MASK | \
+      MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG26_MH_BUSY_d_MASK | \
+      MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \
+      MH_DEBUG_REG26_CP_SEND_q_MASK | \
+      MH_DEBUG_REG26_CP_RTR_q_MASK | \
+      MH_DEBUG_REG26_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG26_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG26_RB_SEND_q_MASK | \
+      MH_DEBUG_REG26_RB_RTR_q_MASK | \
+      MH_DEBUG_REG26_PA_SEND_q_MASK | \
+      MH_DEBUG_REG26_PA_RTR_q_MASK | \
+      MH_DEBUG_REG26_RDC_VALID_MASK | \
+      MH_DEBUG_REG26_RDC_RLAST_MASK | \
+      MH_DEBUG_REG26_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG26_BRC_VALID_MASK)
+
+#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \
+     ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \
+      (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \
+      (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \
+      (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \
+      (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \
+      (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \
+      (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \
+      (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \
+      (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \
+      (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \
+      (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \
+      (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT))
+
+#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+     } mh_debug_reg26_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+     } mh_debug_reg26_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg26_t f;
+} mh_debug_reg26_u;
+
+
+/*
+ * MH_DEBUG_REG27 struct
+ */
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG27_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG27_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG27_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6
+#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9
+#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12
+#define MH_DEBUG_REG27_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16
+#define MH_DEBUG_REG27_ARB_HOLD_SHIFT  17
+#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24
+#define MH_DEBUG_REG27_ARB_QUAL_SHIFT  25
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038
+#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0
+#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00
+#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000
+#define MH_DEBUG_REG27_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG27_KILL_EFF1_MASK  0x00010000
+#define MH_DEBUG_REG27_ARB_HOLD_MASK   0x00020000
+#define MH_DEBUG_REG27_ARB_RTR_q_MASK  0x00040000
+#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000
+#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000
+#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000
+#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000
+#define MH_DEBUG_REG27_ARB_QUAL_MASK   0x02000000
+#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000
+#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000
+#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000
+#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000
+
+#define MH_DEBUG_REG27_MASK \
+     (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \
+      MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG27_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_q_MASK | \
+      MH_DEBUG_REG27_EFF1_WIN_MASK | \
+      MH_DEBUG_REG27_KILL_EFF1_MASK | \
+      MH_DEBUG_REG27_ARB_HOLD_MASK | \
+      MH_DEBUG_REG27_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_ARB_QUAL_MASK | \
+      MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG27_TCHOLD_IP_q_MASK)
+
+#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \
+     ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \
+      (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \
+      (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \
+      (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT))
+
+#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+     } mh_debug_reg27_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+     } mh_debug_reg27_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg27_t f;
+} mh_debug_reg27_u;
+
+
+/*
+ * MH_DEBUG_REG28 struct
+ */
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG28_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG28_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG28_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0
+#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10
+#define MH_DEBUG_REG28_ARB_QUAL_SHIFT  11
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15
+#define MH_DEBUG_REG28_EFF1_WIN_SHIFT  16
+#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19
+#define MH_DEBUG_REG28_ARB_HOLD_SHIFT  20
+#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22
+
+#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080
+#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200
+#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400
+#define MH_DEBUG_REG28_ARB_QUAL_MASK   0x00000800
+#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000
+#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000
+#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000
+#define MH_DEBUG_REG28_EFF1_WIN_MASK   0x00010000
+#define MH_DEBUG_REG28_KILL_EFF1_MASK  0x00020000
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000
+#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000
+#define MH_DEBUG_REG28_ARB_HOLD_MASK   0x00100000
+#define MH_DEBUG_REG28_ARB_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000
+
+#define MH_DEBUG_REG28_MASK \
+     (MH_DEBUG_REG28_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG28_ARB_WINNER_MASK | \
+      MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_ARB_QUAL_MASK | \
+      MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_EFF1_WIN_MASK | \
+      MH_DEBUG_REG28_KILL_EFF1_MASK | \
+      MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK)
+
+#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \
+     ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \
+      (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \
+      (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT))
+
+#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+     } mh_debug_reg28_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+     } mh_debug_reg28_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg28_t f;
+} mh_debug_reg28_u;
+
+
+/*
+ * MH_DEBUG_REG29 struct
+ */
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1
+#define MH_DEBUG_REG29_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG29_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG29_CLNT_REQ_SIZE   5
+#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9
+#define MH_DEBUG_REG29_ARB_HOLD_SHIFT  10
+#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11
+#define MH_DEBUG_REG29_CLNT_REQ_SHIFT  12
+#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17
+#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20
+#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23
+#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26
+#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038
+#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200
+#define MH_DEBUG_REG29_ARB_HOLD_MASK   0x00000400
+#define MH_DEBUG_REG29_ARB_RTR_q_MASK  0x00000800
+#define MH_DEBUG_REG29_CLNT_REQ_MASK   0x0001f000
+#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000
+#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000
+#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000
+#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000
+#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000
+
+#define MH_DEBUG_REG29_MASK \
+     (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \
+      MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \
+      MH_DEBUG_REG29_ARB_HOLD_MASK | \
+      MH_DEBUG_REG29_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG29_CLNT_REQ_MASK | \
+      MH_DEBUG_REG29_RECENT_d_0_MASK | \
+      MH_DEBUG_REG29_RECENT_d_1_MASK | \
+      MH_DEBUG_REG29_RECENT_d_2_MASK | \
+      MH_DEBUG_REG29_RECENT_d_3_MASK | \
+      MH_DEBUG_REG29_RECENT_d_4_MASK)
+
+#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \
+     ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \
+      (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \
+      (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \
+      (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \
+      (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \
+      (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \
+      (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \
+      (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \
+      (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \
+      (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT))
+
+#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+     } mh_debug_reg29_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+     } mh_debug_reg29_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg29_t f;
+} mh_debug_reg29_u;
+
+
+/*
+ * MH_DEBUG_REG30 struct
+ */
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG30_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1
+#define MH_DEBUG_REG30_WLAST_q_SIZE    1
+#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10
+#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19
+#define MH_DEBUG_REG30_WLAST_q_SHIFT   20
+#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21
+#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25
+#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28
+#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008
+#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400
+#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000
+#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000
+#define MH_DEBUG_REG30_WLAST_q_MASK    0x00100000
+#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000
+#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000
+#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000
+#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000
+#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000
+#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000
+#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000
+
+#define MH_DEBUG_REG30_MASK \
+     (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \
+      MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG30_TC_MH_written_MASK | \
+      MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \
+      MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \
+      MH_DEBUG_REG30_WLAST_q_MASK | \
+      MH_DEBUG_REG30_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG30_WBURST_CNT_q_MASK | \
+      MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_CP_MH_write_MASK | \
+      MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_ARB_WINNER_MASK)
+
+#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \
+     ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \
+      (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \
+      (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \
+      (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \
+      (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \
+      (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \
+      (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \
+      (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT))
+
+#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+     } mh_debug_reg30_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+     } mh_debug_reg30_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg30_t f;
+} mh_debug_reg30_u;
+
+
+/*
+ * MH_DEBUG_REG31 struct
+ */
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000
+
+#define MH_DEBUG_REG31_MASK \
+     (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \
+      MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \
+     ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg31_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int                                : 3;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+     } mh_debug_reg31_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg31_t f;
+} mh_debug_reg31_u;
+
+
+/*
+ * MH_DEBUG_REG32 struct
+ */
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8
+#define MH_DEBUG_REG32_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG32_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16
+#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00
+#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000
+#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG32_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG32_MASK \
+     (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_MARK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_VALID_q_MASK | \
+      MH_DEBUG_REG32_TC_MH_send_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG32_KILL_EFF1_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \
+      (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg32_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg32_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg32_t f;
+} mh_debug_reg32_u;
+
+
+/*
+ * MH_DEBUG_REG33 struct
+ */
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8
+#define MH_DEBUG_REG33_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG33_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16
+#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00
+#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000
+#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG33_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG33_MASK \
+     (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG33_ROQ_MARK_d_MASK | \
+      MH_DEBUG_REG33_ROQ_VALID_d_MASK | \
+      MH_DEBUG_REG33_TC_MH_send_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG33_KILL_EFF1_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \
+      (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg33_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg33_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg33_t f;
+} mh_debug_reg33_u;
+
+
+/*
+ * MH_DEBUG_REG34 struct
+ */
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000
+
+#define MH_DEBUG_REG34_MASK \
+     (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK)
+
+#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \
+     ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \
+      (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \
+      (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \
+      (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT))
+
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+     } mh_debug_reg34_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+     } mh_debug_reg34_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg34_t f;
+} mh_debug_reg34_u;
+
+
+/*
+ * MH_DEBUG_REG35 struct
+ */
+
+#define MH_DEBUG_REG35_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27
+
+#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5
+
+#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010
+#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0
+
+#define MH_DEBUG_REG35_MASK \
+     (MH_DEBUG_REG35_TC_MH_send_MASK | \
+      MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \
+      MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_ADDR_0_MASK)
+
+#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \
+     ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \
+      (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \
+      (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \
+      (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT))
+
+#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+     } mh_debug_reg35_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+     } mh_debug_reg35_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg35_t f;
+} mh_debug_reg35_u;
+
+
+/*
+ * MH_DEBUG_REG36 struct
+ */
+
+#define MH_DEBUG_REG36_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27
+
+#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5
+
+#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010
+#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0
+
+#define MH_DEBUG_REG36_MASK \
+     (MH_DEBUG_REG36_TC_MH_send_MASK | \
+      MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \
+      MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_ADDR_1_MASK)
+
+#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \
+     ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \
+      (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \
+      (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \
+      (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT))
+
+#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+     } mh_debug_reg36_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+     } mh_debug_reg36_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg36_t f;
+} mh_debug_reg36_u;
+
+
+/*
+ * MH_DEBUG_REG37 struct
+ */
+
+#define MH_DEBUG_REG37_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27
+
+#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5
+
+#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010
+#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0
+
+#define MH_DEBUG_REG37_MASK \
+     (MH_DEBUG_REG37_TC_MH_send_MASK | \
+      MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \
+      MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_ADDR_2_MASK)
+
+#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \
+     ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \
+      (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \
+      (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \
+      (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT))
+
+#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+     } mh_debug_reg37_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+     } mh_debug_reg37_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg37_t f;
+} mh_debug_reg37_u;
+
+
+/*
+ * MH_DEBUG_REG38 struct
+ */
+
+#define MH_DEBUG_REG38_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27
+
+#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5
+
+#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010
+#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0
+
+#define MH_DEBUG_REG38_MASK \
+     (MH_DEBUG_REG38_TC_MH_send_MASK | \
+      MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \
+      MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_ADDR_3_MASK)
+
+#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \
+     ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \
+      (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \
+      (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \
+      (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT))
+
+#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+     } mh_debug_reg38_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+     } mh_debug_reg38_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg38_t f;
+} mh_debug_reg38_u;
+
+
+/*
+ * MH_DEBUG_REG39 struct
+ */
+
+#define MH_DEBUG_REG39_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27
+
+#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5
+
+#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010
+#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0
+
+#define MH_DEBUG_REG39_MASK \
+     (MH_DEBUG_REG39_TC_MH_send_MASK | \
+      MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \
+      MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_ADDR_4_MASK)
+
+#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \
+     ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \
+      (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \
+      (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \
+      (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT))
+
+#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+     } mh_debug_reg39_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+     } mh_debug_reg39_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg39_t f;
+} mh_debug_reg39_u;
+
+
+/*
+ * MH_DEBUG_REG40 struct
+ */
+
+#define MH_DEBUG_REG40_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27
+
+#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5
+
+#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010
+#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG40_MASK \
+     (MH_DEBUG_REG40_TC_MH_send_MASK | \
+      MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \
+      MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_ADDR_5_MASK)
+
+#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \
+     ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \
+      (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \
+      (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \
+      (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT))
+
+#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+     } mh_debug_reg40_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+     } mh_debug_reg40_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg40_t f;
+} mh_debug_reg40_u;
+
+
+/*
+ * MH_DEBUG_REG41 struct
+ */
+
+#define MH_DEBUG_REG41_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27
+
+#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5
+
+#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010
+#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0
+
+#define MH_DEBUG_REG41_MASK \
+     (MH_DEBUG_REG41_TC_MH_send_MASK | \
+      MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \
+      MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_ADDR_6_MASK)
+
+#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \
+     ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \
+      (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \
+      (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \
+      (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT))
+
+#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+     } mh_debug_reg41_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+     } mh_debug_reg41_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg41_t f;
+} mh_debug_reg41_u;
+
+
+/*
+ * MH_DEBUG_REG42 struct
+ */
+
+#define MH_DEBUG_REG42_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27
+
+#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5
+
+#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010
+#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0
+
+#define MH_DEBUG_REG42_MASK \
+     (MH_DEBUG_REG42_TC_MH_send_MASK | \
+      MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \
+      MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_ADDR_7_MASK)
+
+#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \
+     ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \
+      (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \
+      (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \
+      (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT))
+
+#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+     } mh_debug_reg42_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+     } mh_debug_reg42_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg42_t f;
+} mh_debug_reg42_u;
+
+
+/*
+ * MH_DEBUG_REG43 struct
+ */
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_WE_SIZE     1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1
+#define MH_DEBUG_REG43_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG43_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3
+#define MH_DEBUG_REG43_MMU_WE_SIZE     1
+#define MH_DEBUG_REG43_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG43_MMU_ID_SIZE     3
+#define MH_DEBUG_REG43_MMU_WRITE_SIZE  1
+#define MH_DEBUG_REG43_MMU_BLEN_SIZE   1
+#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_WDB_WE_SIZE     1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG43_ARB_WE_SHIFT    1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3
+#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5
+#define MH_DEBUG_REG43_MMU_RTR_SHIFT   6
+#define MH_DEBUG_REG43_ARB_ID_q_SHIFT  7
+#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10
+#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13
+#define MH_DEBUG_REG43_MMU_WE_SHIFT    16
+#define MH_DEBUG_REG43_ARQ_RTR_SHIFT   17
+#define MH_DEBUG_REG43_MMU_ID_SHIFT    18
+#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21
+#define MH_DEBUG_REG43_MMU_BLEN_SHIFT  22
+#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24
+#define MH_DEBUG_REG43_WDB_WE_SHIFT    25
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG43_ARB_WE_MASK     0x00000002
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG43_ARB_RTR_q_MASK  0x00000008
+#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020
+#define MH_DEBUG_REG43_MMU_RTR_MASK    0x00000040
+#define MH_DEBUG_REG43_ARB_ID_q_MASK   0x00000380
+#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400
+#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000
+#define MH_DEBUG_REG43_MMU_WE_MASK     0x00010000
+#define MH_DEBUG_REG43_ARQ_RTR_MASK    0x00020000
+#define MH_DEBUG_REG43_MMU_ID_MASK     0x001c0000
+#define MH_DEBUG_REG43_MMU_WRITE_MASK  0x00200000
+#define MH_DEBUG_REG43_MMU_BLEN_MASK   0x00400000
+#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000
+#define MH_DEBUG_REG43_WDB_WE_MASK     0x02000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000
+
+#define MH_DEBUG_REG43_MASK \
+     (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_ARB_WE_MASK | \
+      MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \
+      MH_DEBUG_REG43_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG43_ARB_REG_RTR_MASK | \
+      MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_RTR_MASK | \
+      MH_DEBUG_REG43_ARB_ID_q_MASK | \
+      MH_DEBUG_REG43_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG43_ARB_BLEN_q_MASK | \
+      MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG43_MMU_WE_MASK | \
+      MH_DEBUG_REG43_ARQ_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_ID_MASK | \
+      MH_DEBUG_REG43_MMU_WRITE_MASK | \
+      MH_DEBUG_REG43_MMU_BLEN_MASK | \
+      MH_DEBUG_REG43_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_WDB_WE_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK)
+
+#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \
+     ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \
+      (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \
+      (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \
+      (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \
+      (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \
+      (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \
+      (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \
+      (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \
+      (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \
+      (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \
+      (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT))
+
+#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int                                : 4;
+     } mh_debug_reg43_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int                                : 4;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+     } mh_debug_reg43_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg43_t f;
+} mh_debug_reg43_u;
+
+
+/*
+ * MH_DEBUG_REG44 struct
+ */
+
+#define MH_DEBUG_REG44_ARB_WE_SIZE     1
+#define MH_DEBUG_REG44_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG44_ARB_VAD_q_SIZE  28
+
+#define MH_DEBUG_REG44_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG44_ARB_ID_q_SHIFT  1
+#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4
+
+#define MH_DEBUG_REG44_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG44_ARB_ID_q_MASK   0x0000000e
+#define MH_DEBUG_REG44_ARB_VAD_q_MASK  0xfffffff0
+
+#define MH_DEBUG_REG44_MASK \
+     (MH_DEBUG_REG44_ARB_WE_MASK | \
+      MH_DEBUG_REG44_ARB_ID_q_MASK | \
+      MH_DEBUG_REG44_ARB_VAD_q_MASK)
+
+#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \
+     ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \
+      (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT))
+
+#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+     } mh_debug_reg44_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+     } mh_debug_reg44_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg44_t f;
+} mh_debug_reg44_u;
+
+
+/*
+ * MH_DEBUG_REG45 struct
+ */
+
+#define MH_DEBUG_REG45_MMU_WE_SIZE     1
+#define MH_DEBUG_REG45_MMU_ID_SIZE     3
+#define MH_DEBUG_REG45_MMU_PAD_SIZE    28
+
+#define MH_DEBUG_REG45_MMU_WE_SHIFT    0
+#define MH_DEBUG_REG45_MMU_ID_SHIFT    1
+#define MH_DEBUG_REG45_MMU_PAD_SHIFT   4
+
+#define MH_DEBUG_REG45_MMU_WE_MASK     0x00000001
+#define MH_DEBUG_REG45_MMU_ID_MASK     0x0000000e
+#define MH_DEBUG_REG45_MMU_PAD_MASK    0xfffffff0
+
+#define MH_DEBUG_REG45_MASK \
+     (MH_DEBUG_REG45_MMU_WE_MASK | \
+      MH_DEBUG_REG45_MMU_ID_MASK | \
+      MH_DEBUG_REG45_MMU_PAD_MASK)
+
+#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \
+     ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \
+      (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT))
+
+#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+     } mh_debug_reg45_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+     } mh_debug_reg45_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg45_t f;
+} mh_debug_reg45_u;
+
+
+/*
+ * MH_DEBUG_REG46 struct
+ */
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WE_SIZE     1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8
+#define MH_DEBUG_REG46_ARB_WLAST_SIZE  1
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG46_WDB_WE_SHIFT    1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4
+#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19
+#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG46_WDB_WE_MASK     0x00000002
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008
+#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0
+#define MH_DEBUG_REG46_ARB_WLAST_MASK  0x00001000
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000
+#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000
+
+#define MH_DEBUG_REG46_MASK \
+     (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WE_MASK | \
+      MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \
+      MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \
+      MH_DEBUG_REG46_ARB_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WID_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK)
+
+#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \
+     ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \
+      (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \
+      (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \
+      (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \
+      (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \
+      (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \
+      (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \
+      (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \
+      (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \
+      (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT))
+
+#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+     } mh_debug_reg46_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+     } mh_debug_reg46_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg46_t f;
+} mh_debug_reg46_u;
+
+
+/*
+ * MH_DEBUG_REG47 struct
+ */
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG47_MASK \
+     (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK)
+
+#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \
+     ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT))
+
+#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg47_t f;
+} mh_debug_reg47_u;
+
+
+/*
+ * MH_DEBUG_REG48 struct
+ */
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG48_MASK \
+     (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK)
+
+#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \
+     ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT))
+
+#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg48_t f;
+} mh_debug_reg48_u;
+
+
+/*
+ * MH_DEBUG_REG49 struct
+ */
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RVALID_q_SIZE   1
+#define MH_DEBUG_REG49_RREADY_q_SIZE   1
+#define MH_DEBUG_REG49_RLAST_q_SIZE    1
+#define MH_DEBUG_REG49_BVALID_q_SIZE   1
+#define MH_DEBUG_REG49_BREADY_q_SIZE   1
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14
+#define MH_DEBUG_REG49_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG49_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG49_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG49_BVALID_q_SHIFT  18
+#define MH_DEBUG_REG49_BREADY_q_SHIFT  19
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000
+#define MH_DEBUG_REG49_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG49_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG49_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG49_BVALID_q_MASK   0x00040000
+#define MH_DEBUG_REG49_BREADY_q_MASK   0x00080000
+
+#define MH_DEBUG_REG49_MASK \
+     (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \
+      MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \
+      MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RVALID_q_MASK | \
+      MH_DEBUG_REG49_RREADY_q_MASK | \
+      MH_DEBUG_REG49_RLAST_q_MASK | \
+      MH_DEBUG_REG49_BVALID_q_MASK | \
+      MH_DEBUG_REG49_BREADY_q_MASK)
+
+#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \
+     ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \
+      (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \
+      (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \
+      (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \
+      (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT))
+
+#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg49_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int                                : 12;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+     } mh_debug_reg49_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg49_t f;
+} mh_debug_reg49_u;
+
+
+/*
+ * MH_DEBUG_REG50 struct
+ */
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG50_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG50_RDC_RID_SIZE    3
+#define MH_DEBUG_REG50_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG50_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3
+#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4
+#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5
+#define MH_DEBUG_REG50_RDC_RID_SHIFT   6
+#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9
+#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008
+#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010
+#define MH_DEBUG_REG50_RDC_VALID_MASK  0x00000020
+#define MH_DEBUG_REG50_RDC_RID_MASK    0x000001c0
+#define MH_DEBUG_REG50_RDC_RLAST_MASK  0x00000200
+#define MH_DEBUG_REG50_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000
+#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000
+
+#define MH_DEBUG_REG50_MASK \
+     (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG50_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_RID_MASK | \
+      MH_DEBUG_REG50_RDC_RLAST_MASK | \
+      MH_DEBUG_REG50_RDC_RRESP_MASK | \
+      MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \
+      MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \
+      MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \
+      MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \
+      MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \
+     ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \
+      (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \
+      (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \
+      (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \
+      (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+     } mh_debug_reg50_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+     } mh_debug_reg50_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg50_t f;
+} mh_debug_reg50_u;
+
+
+/*
+ * MH_DEBUG_REG51 struct
+ */
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG51_MASK \
+     (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK)
+
+#define MH_DEBUG_REG51(rf_mmu_page_fault) \
+     ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg51_t f;
+} mh_debug_reg51_u;
+
+
+/*
+ * MH_DEBUG_REG52 struct
+ */
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2
+#define MH_DEBUG_REG52_ARB_WE_SIZE     1
+#define MH_DEBUG_REG52_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22
+#define MH_DEBUG_REG52_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG52_client_behavior_q_SIZE 2
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0
+#define MH_DEBUG_REG52_ARB_WE_SHIFT    2
+#define MH_DEBUG_REG52_MMU_RTR_SHIFT   3
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4
+#define MH_DEBUG_REG52_ARB_ID_q_SHIFT  26
+#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29
+#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003
+#define MH_DEBUG_REG52_ARB_WE_MASK     0x00000004
+#define MH_DEBUG_REG52_MMU_RTR_MASK    0x00000008
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0
+#define MH_DEBUG_REG52_ARB_ID_q_MASK   0x1c000000
+#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000
+#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000
+
+#define MH_DEBUG_REG52_MASK \
+     (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \
+      MH_DEBUG_REG52_ARB_WE_MASK | \
+      MH_DEBUG_REG52_MMU_RTR_MASK | \
+      MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \
+      MH_DEBUG_REG52_ARB_ID_q_MASK | \
+      MH_DEBUG_REG52_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG52_client_behavior_q_MASK)
+
+#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \
+     ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \
+      (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \
+      (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT))
+
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+     } mh_debug_reg52_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+     } mh_debug_reg52_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg52_t f;
+} mh_debug_reg52_u;
+
+
+/*
+ * MH_DEBUG_REG53 struct
+ */
+
+#define MH_DEBUG_REG53_stage1_valid_SIZE 1
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG53_tag_match_q_SIZE 1
+#define MH_DEBUG_REG53_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG53_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG53_MMU_MISS_SIZE   1
+#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_HIT_SIZE    1
+#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16
+
+#define MH_DEBUG_REG53_stage1_valid_SHIFT 0
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2
+#define MH_DEBUG_REG53_tag_match_q_SHIFT 3
+#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4
+#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5
+#define MH_DEBUG_REG53_MMU_MISS_SHIFT  6
+#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8
+#define MH_DEBUG_REG53_MMU_HIT_SHIFT   9
+#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16
+
+#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002
+#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004
+#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008
+#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010
+#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020
+#define MH_DEBUG_REG53_MMU_MISS_MASK   0x00000040
+#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100
+#define MH_DEBUG_REG53_MMU_HIT_MASK    0x00000200
+#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG53_MASK \
+     (MH_DEBUG_REG53_stage1_valid_MASK | \
+      MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG53_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG53_tag_match_q_MASK | \
+      MH_DEBUG_REG53_tag_miss_q_MASK | \
+      MH_DEBUG_REG53_va_in_range_q_MASK | \
+      MH_DEBUG_REG53_MMU_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_READ_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_READ_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \
+      MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK)
+
+#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \
+     ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \
+      (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \
+      (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \
+      (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \
+      (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \
+      (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \
+      (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \
+      (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \
+      (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \
+      (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \
+      (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \
+      (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT))
+
+#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+     } mh_debug_reg53_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+     } mh_debug_reg53_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg53_t f;
+} mh_debug_reg53_u;
+
+
+/*
+ * MH_DEBUG_REG54 struct
+ */
+
+#define MH_DEBUG_REG54_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG54_MMU_WE_SIZE     1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1
+#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG54_stage1_valid_SIZE 1
+#define MH_DEBUG_REG54_stage2_valid_SIZE 1
+#define MH_DEBUG_REG54_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG54_tag_match_q_SIZE 1
+#define MH_DEBUG_REG54_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG54_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1
+#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_SHIFT   0
+#define MH_DEBUG_REG54_MMU_WE_SHIFT    1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5
+#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6
+#define MH_DEBUG_REG54_stage1_valid_SHIFT 7
+#define MH_DEBUG_REG54_stage2_valid_SHIFT 8
+#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11
+#define MH_DEBUG_REG54_tag_match_q_SHIFT 12
+#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13
+#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15
+#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_MASK    0x00000001
+#define MH_DEBUG_REG54_MMU_WE_MASK     0x00000002
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020
+#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040
+#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080
+#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100
+#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800
+#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000
+#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000
+#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000
+#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG54_MASK \
+     (MH_DEBUG_REG54_ARQ_RTR_MASK | \
+      MH_DEBUG_REG54_MMU_WE_MASK | \
+      MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \
+      MH_DEBUG_REG54_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG54_stage1_valid_MASK | \
+      MH_DEBUG_REG54_stage2_valid_MASK | \
+      MH_DEBUG_REG54_client_behavior_q_MASK | \
+      MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG54_tag_match_q_MASK | \
+      MH_DEBUG_REG54_tag_miss_q_MASK | \
+      MH_DEBUG_REG54_va_in_range_q_MASK | \
+      MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_MASK)
+
+#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \
+     ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \
+      (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \
+      (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \
+      (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \
+      (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \
+      (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT))
+
+#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+     } mh_debug_reg54_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+     } mh_debug_reg54_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg54_t f;
+} mh_debug_reg54_u;
+
+
+/*
+ * MH_DEBUG_REG55 struct
+ */
+
+#define MH_DEBUG_REG55_TAG0_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG55_TAG1_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1
+
+#define MH_DEBUG_REG55_TAG0_VA_SHIFT   0
+#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG55_TAG1_VA_SHIFT   16
+#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29
+
+#define MH_DEBUG_REG55_TAG0_VA_MASK    0x00001fff
+#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000
+#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG55_TAG1_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000
+
+#define MH_DEBUG_REG55_MASK \
+     (MH_DEBUG_REG55_TAG0_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_0_MASK | \
+      MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG55_TAG1_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_1_MASK)
+
+#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \
+     ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \
+      (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \
+      (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \
+      (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \
+      (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT))
+
+#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg55_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+     } mh_debug_reg55_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg55_t f;
+} mh_debug_reg55_u;
+
+
+/*
+ * MH_DEBUG_REG56 struct
+ */
+
+#define MH_DEBUG_REG56_TAG2_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG56_TAG3_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1
+
+#define MH_DEBUG_REG56_TAG2_VA_SHIFT   0
+#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG56_TAG3_VA_SHIFT   16
+#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29
+
+#define MH_DEBUG_REG56_TAG2_VA_MASK    0x00001fff
+#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000
+#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG56_TAG3_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000
+
+#define MH_DEBUG_REG56_MASK \
+     (MH_DEBUG_REG56_TAG2_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_2_MASK | \
+      MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG56_TAG3_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_3_MASK)
+
+#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \
+     ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \
+      (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \
+      (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \
+      (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \
+      (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT))
+
+#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg56_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+     } mh_debug_reg56_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg56_t f;
+} mh_debug_reg56_u;
+
+
+/*
+ * MH_DEBUG_REG57 struct
+ */
+
+#define MH_DEBUG_REG57_TAG4_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG57_TAG5_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1
+
+#define MH_DEBUG_REG57_TAG4_VA_SHIFT   0
+#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG57_TAG5_VA_SHIFT   16
+#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29
+
+#define MH_DEBUG_REG57_TAG4_VA_MASK    0x00001fff
+#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000
+#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG57_TAG5_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000
+
+#define MH_DEBUG_REG57_MASK \
+     (MH_DEBUG_REG57_TAG4_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_4_MASK | \
+      MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG57_TAG5_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_5_MASK)
+
+#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \
+     ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \
+      (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \
+      (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \
+      (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \
+      (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT))
+
+#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg57_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+     } mh_debug_reg57_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg57_t f;
+} mh_debug_reg57_u;
+
+
+/*
+ * MH_DEBUG_REG58 struct
+ */
+
+#define MH_DEBUG_REG58_TAG6_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG58_TAG7_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1
+
+#define MH_DEBUG_REG58_TAG6_VA_SHIFT   0
+#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG58_TAG7_VA_SHIFT   16
+#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29
+
+#define MH_DEBUG_REG58_TAG6_VA_MASK    0x00001fff
+#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000
+#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG58_TAG7_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000
+
+#define MH_DEBUG_REG58_MASK \
+     (MH_DEBUG_REG58_TAG6_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_6_MASK | \
+      MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG58_TAG7_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_7_MASK)
+
+#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \
+     ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \
+      (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \
+      (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \
+      (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \
+      (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT))
+
+#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg58_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+     } mh_debug_reg58_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg58_t f;
+} mh_debug_reg58_u;
+
+
+/*
+ * MH_DEBUG_REG59 struct
+ */
+
+#define MH_DEBUG_REG59_TAG8_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG59_TAG9_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1
+
+#define MH_DEBUG_REG59_TAG8_VA_SHIFT   0
+#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG59_TAG9_VA_SHIFT   16
+#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29
+
+#define MH_DEBUG_REG59_TAG8_VA_MASK    0x00001fff
+#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000
+#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG59_TAG9_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000
+
+#define MH_DEBUG_REG59_MASK \
+     (MH_DEBUG_REG59_TAG8_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_8_MASK | \
+      MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG59_TAG9_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_9_MASK)
+
+#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \
+     ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \
+      (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \
+      (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \
+      (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \
+      (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT))
+
+#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg59_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+     } mh_debug_reg59_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg59_t f;
+} mh_debug_reg59_u;
+
+
+/*
+ * MH_DEBUG_REG60 struct
+ */
+
+#define MH_DEBUG_REG60_TAG10_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG60_TAG11_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1
+
+#define MH_DEBUG_REG60_TAG10_VA_SHIFT  0
+#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG60_TAG11_VA_SHIFT  16
+#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29
+
+#define MH_DEBUG_REG60_TAG10_VA_MASK   0x00001fff
+#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000
+#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG60_TAG11_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000
+
+#define MH_DEBUG_REG60_MASK \
+     (MH_DEBUG_REG60_TAG10_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_10_MASK | \
+      MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG60_TAG11_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_11_MASK)
+
+#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \
+     ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \
+      (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \
+      (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \
+      (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \
+      (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT))
+
+#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg60_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+     } mh_debug_reg60_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg60_t f;
+} mh_debug_reg60_u;
+
+
+/*
+ * MH_DEBUG_REG61 struct
+ */
+
+#define MH_DEBUG_REG61_TAG12_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG61_TAG13_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1
+
+#define MH_DEBUG_REG61_TAG12_VA_SHIFT  0
+#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG61_TAG13_VA_SHIFT  16
+#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29
+
+#define MH_DEBUG_REG61_TAG12_VA_MASK   0x00001fff
+#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000
+#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG61_TAG13_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000
+
+#define MH_DEBUG_REG61_MASK \
+     (MH_DEBUG_REG61_TAG12_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_12_MASK | \
+      MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG61_TAG13_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_13_MASK)
+
+#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \
+     ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \
+      (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \
+      (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \
+      (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \
+      (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT))
+
+#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg61_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+     } mh_debug_reg61_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg61_t f;
+} mh_debug_reg61_u;
+
+
+/*
+ * MH_DEBUG_REG62 struct
+ */
+
+#define MH_DEBUG_REG62_TAG14_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG62_TAG15_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1
+
+#define MH_DEBUG_REG62_TAG14_VA_SHIFT  0
+#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG62_TAG15_VA_SHIFT  16
+#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29
+
+#define MH_DEBUG_REG62_TAG14_VA_MASK   0x00001fff
+#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000
+#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG62_TAG15_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000
+
+#define MH_DEBUG_REG62_MASK \
+     (MH_DEBUG_REG62_TAG14_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_14_MASK | \
+      MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG62_TAG15_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_15_MASK)
+
+#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \
+     ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \
+      (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \
+      (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \
+      (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \
+      (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT))
+
+#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg62_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+     } mh_debug_reg62_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg62_t f;
+} mh_debug_reg62_u;
+
+
+/*
+ * MH_DEBUG_REG63 struct
+ */
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG63_MASK \
+     (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG63(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \
+     ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \
+     mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg63_t f;
+} mh_debug_reg63_u;
+
+
+/*
+ * MH_MMU_CONFIG struct
+ */
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SIZE  1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1
+#define MH_MMU_CONFIG_RESERVED1_SIZE   2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1
+#define MH_MMU_CONFIG_RESERVED1_SHIFT  2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24
+
+#define MH_MMU_CONFIG_MMU_ENABLE_MASK  0x00000001
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002
+#define MH_MMU_CONFIG_RESERVED1_MASK   0x0000000c
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000
+
+#define MH_MMU_CONFIG_MASK \
+     (MH_MMU_CONFIG_MMU_ENABLE_MASK | \
+      MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \
+      MH_MMU_CONFIG_RESERVED1_MASK | \
+      MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK)
+
+#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \
+     ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \
+      (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \
+      (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \
+      (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \
+      (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT))
+
+#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int                                : 6;
+     } mh_mmu_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int                                : 6;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+     } mh_mmu_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_config_t f;
+} mh_mmu_config_u;
+
+
+/*
+ * MH_MMU_VA_RANGE struct
+ */
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12
+#define MH_MMU_VA_RANGE_VA_BASE_SIZE   20
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0
+#define MH_MMU_VA_RANGE_VA_BASE_SHIFT  12
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff
+#define MH_MMU_VA_RANGE_VA_BASE_MASK   0xfffff000
+
+#define MH_MMU_VA_RANGE_MASK \
+     (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \
+      MH_MMU_VA_RANGE_VA_BASE_MASK)
+
+#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \
+     ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \
+      (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT))
+
+#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+     } mh_mmu_va_range_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+     } mh_mmu_va_range_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_va_range_t f;
+} mh_mmu_va_range_u;
+
+
+/*
+ * MH_MMU_PT_BASE struct
+ */
+
+#define MH_MMU_PT_BASE_PT_BASE_SIZE    20
+
+#define MH_MMU_PT_BASE_PT_BASE_SHIFT   12
+
+#define MH_MMU_PT_BASE_PT_BASE_MASK    0xfffff000
+
+#define MH_MMU_PT_BASE_MASK \
+     (MH_MMU_PT_BASE_PT_BASE_MASK)
+
+#define MH_MMU_PT_BASE(pt_base) \
+     ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT))
+
+#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \
+     ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \
+     mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int                                : 12;
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+     } mh_mmu_pt_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_pt_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_pt_base_t f;
+} mh_mmu_pt_base_u;
+
+
+/*
+ * MH_MMU_PAGE_FAULT struct
+ */
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE  3
+#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE  20
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4
+#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11
+#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001
+#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c
+#define MH_MMU_PAGE_FAULT_AXI_ID_MASK  0x00000070
+#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800
+#define MH_MMU_PAGE_FAULT_REQ_VA_MASK  0xfffff000
+
+#define MH_MMU_PAGE_FAULT_MASK \
+     (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \
+      MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \
+      MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_PAGE_FAULT_AXI_ID_MASK | \
+      MH_MMU_PAGE_FAULT_RESERVED1_MASK | \
+      MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_REQ_VA_MASK)
+
+#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \
+     ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \
+      (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \
+      (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \
+      (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \
+      (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \
+      (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \
+      (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \
+      (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT))
+
+#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+     } mh_mmu_page_fault_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+     } mh_mmu_page_fault_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_page_fault_t f;
+} mh_mmu_page_fault_u;
+
+
+/*
+ * MH_MMU_TRAN_ERROR struct
+ */
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0
+
+#define MH_MMU_TRAN_ERROR_MASK \
+     (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK)
+
+#define MH_MMU_TRAN_ERROR(tran_error) \
+     ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT))
+
+#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \
+     ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \
+     mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int                                : 5;
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+     } mh_mmu_tran_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+          unsigned int                                : 5;
+     } mh_mmu_tran_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_tran_error_t f;
+} mh_mmu_tran_error_u;
+
+
+/*
+ * MH_MMU_INVALIDATE struct
+ */
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002
+
+#define MH_MMU_INVALIDATE_MASK \
+     (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_MMU_INVALIDATE_INVALIDATE_TC_MASK)
+
+#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \
+     ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT))
+
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int                                : 30;
+     } mh_mmu_invalidate_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int                                : 30;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+     } mh_mmu_invalidate_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_invalidate_t f;
+} mh_mmu_invalidate_u;
+
+
+/*
+ * MH_MMU_MPU_BASE struct
+ */
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SIZE  20
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12
+
+#define MH_MMU_MPU_BASE_MPU_BASE_MASK  0xfffff000
+
+#define MH_MMU_MPU_BASE_MASK \
+     (MH_MMU_MPU_BASE_MPU_BASE_MASK)
+
+#define MH_MMU_MPU_BASE(mpu_base) \
+     ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT))
+
+#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \
+     ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \
+     mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int                                : 12;
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+     } mh_mmu_mpu_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_base_t f;
+} mh_mmu_mpu_base_u;
+
+
+/*
+ * MH_MMU_MPU_END struct
+ */
+
+#define MH_MMU_MPU_END_MPU_END_SIZE    20
+
+#define MH_MMU_MPU_END_MPU_END_SHIFT   12
+
+#define MH_MMU_MPU_END_MPU_END_MASK    0xfffff000
+
+#define MH_MMU_MPU_END_MASK \
+     (MH_MMU_MPU_END_MPU_END_MASK)
+
+#define MH_MMU_MPU_END(mpu_end) \
+     ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT))
+
+#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \
+     ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \
+     mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int                                : 12;
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+     } mh_mmu_mpu_end_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_end_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_end_t f;
+} mh_mmu_mpu_end_u;
+
+
+#endif
+
+
+#if !defined (_PA_FIDDLE_H)
+#define _PA_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * PA_CL_VPORT_XSCALE struct
+ */
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_XSCALE_MASK \
+     (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK)
+
+#define PA_CL_VPORT_XSCALE(vport_xscale) \
+     ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT))
+
+#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \
+     ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \
+     pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xscale_t f;
+} pa_cl_vport_xscale_u;
+
+
+/*
+ * PA_CL_VPORT_XOFFSET struct
+ */
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_XOFFSET_MASK \
+     (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK)
+
+#define PA_CL_VPORT_XOFFSET(vport_xoffset) \
+     ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT))
+
+#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \
+     ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \
+     pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xoffset_t f;
+} pa_cl_vport_xoffset_u;
+
+
+/*
+ * PA_CL_VPORT_YSCALE struct
+ */
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_YSCALE_MASK \
+     (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK)
+
+#define PA_CL_VPORT_YSCALE(vport_yscale) \
+     ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT))
+
+#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \
+     ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \
+     pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yscale_t f;
+} pa_cl_vport_yscale_u;
+
+
+/*
+ * PA_CL_VPORT_YOFFSET struct
+ */
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_YOFFSET_MASK \
+     (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK)
+
+#define PA_CL_VPORT_YOFFSET(vport_yoffset) \
+     ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT))
+
+#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \
+     ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \
+     pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yoffset_t f;
+} pa_cl_vport_yoffset_u;
+
+
+/*
+ * PA_CL_VPORT_ZSCALE struct
+ */
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZSCALE_MASK \
+     (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK)
+
+#define PA_CL_VPORT_ZSCALE(vport_zscale) \
+     ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT))
+
+#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \
+     ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \
+     pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zscale_t f;
+} pa_cl_vport_zscale_u;
+
+
+/*
+ * PA_CL_VPORT_ZOFFSET struct
+ */
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZOFFSET_MASK \
+     (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK)
+
+#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \
+     ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT))
+
+#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \
+     ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \
+     pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zoffset_t f;
+} pa_cl_vport_zoffset_u;
+
+
+/*
+ * PA_CL_VTE_CNTL struct
+ */
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE  1
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK  0x00000200
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800
+
+#define PA_CL_VTE_CNTL_MASK \
+     (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \
+      PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK)
+
+#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \
+     ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \
+      (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \
+      (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \
+      (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \
+      (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \
+      (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \
+      (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \
+      (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \
+      (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \
+      (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT))
+
+#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int                                : 2;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int                                : 20;
+     } pa_cl_vte_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int                                : 20;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int                                : 2;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+     } pa_cl_vte_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vte_cntl_t f;
+} pa_cl_vte_cntl_u;
+
+
+/*
+ * PA_CL_CLIP_CNTL struct
+ */
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000
+
+#define PA_CL_CLIP_CNTL_MASK \
+     (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \
+      PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \
+      PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \
+      PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \
+      PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \
+      PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK)
+
+#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \
+     ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \
+      (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \
+      (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \
+      (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \
+      (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \
+      (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \
+      (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \
+      (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT))
+
+#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 16;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int                                : 7;
+     } pa_cl_clip_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 7;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 16;
+     } pa_cl_clip_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_clip_cntl_t f;
+} pa_cl_clip_cntl_u;
+
+
+/*
+ * PA_CL_GB_VERT_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_CLIP_ADJ_MASK \
+     (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \
+     ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \
+     pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_clip_adj_t f;
+} pa_cl_gb_vert_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_VERT_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_DISC_ADJ_MASK \
+     (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \
+     ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \
+     pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_disc_adj_t f;
+} pa_cl_gb_vert_disc_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \
+     (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \
+     ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \
+     pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_clip_adj_t f;
+} pa_cl_gb_horz_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_DISC_ADJ_MASK \
+     (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \
+     ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \
+     pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_disc_adj_t f;
+} pa_cl_gb_horz_disc_adj_u;
+
+
+/*
+ * PA_CL_ENHANCE struct
+ */
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1
+#define PA_CL_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0
+#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001
+#define PA_CL_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_CL_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_CL_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_CL_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_CL_ENHANCE_MASK \
+     (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE3_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE2_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE1_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \
+      (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+          unsigned int                                : 27;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_cl_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 27;
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+     } pa_cl_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_enhance_t f;
+} pa_cl_enhance_u;
+
+
+/*
+ * PA_SC_ENHANCE struct
+ */
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_SC_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_SC_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_SC_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_SC_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_SC_ENHANCE_MASK \
+     (PA_SC_ENHANCE_ECO_SPARE3_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE2_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE1_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int                                : 28;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_sc_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 28;
+     } pa_sc_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_enhance_t f;
+} pa_sc_enhance_u;
+
+
+/*
+ * PA_SU_VTX_CNTL struct
+ */
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1
+#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2
+#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0
+#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1
+#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001
+#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006
+#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038
+
+#define PA_SU_VTX_CNTL_MASK \
+     (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \
+      PA_SU_VTX_CNTL_ROUND_MODE_MASK | \
+      PA_SU_VTX_CNTL_QUANT_MODE_MASK)
+
+#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \
+     ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \
+      (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \
+      (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT))
+
+#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int                                : 26;
+     } pa_su_vtx_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int                                : 26;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+     } pa_su_vtx_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_vtx_cntl_t f;
+} pa_su_vtx_cntl_u;
+
+
+/*
+ * PA_SU_POINT_SIZE struct
+ */
+
+#define PA_SU_POINT_SIZE_HEIGHT_SIZE   16
+#define PA_SU_POINT_SIZE_WIDTH_SIZE    16
+
+#define PA_SU_POINT_SIZE_HEIGHT_SHIFT  0
+#define PA_SU_POINT_SIZE_WIDTH_SHIFT   16
+
+#define PA_SU_POINT_SIZE_HEIGHT_MASK   0x0000ffff
+#define PA_SU_POINT_SIZE_WIDTH_MASK    0xffff0000
+
+#define PA_SU_POINT_SIZE_MASK \
+     (PA_SU_POINT_SIZE_HEIGHT_MASK | \
+      PA_SU_POINT_SIZE_WIDTH_MASK)
+
+#define PA_SU_POINT_SIZE(height, width) \
+     ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \
+      (width << PA_SU_POINT_SIZE_WIDTH_SHIFT))
+
+#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+     } pa_su_point_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+     } pa_su_point_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_size_t f;
+} pa_su_point_size_u;
+
+
+/*
+ * PA_SU_POINT_MINMAX struct
+ */
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff
+#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000
+
+#define PA_SU_POINT_MINMAX_MASK \
+     (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \
+      PA_SU_POINT_MINMAX_MAX_SIZE_MASK)
+
+#define PA_SU_POINT_MINMAX(min_size, max_size) \
+     ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \
+      (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT))
+
+#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_minmax_t f;
+} pa_su_point_minmax_u;
+
+
+/*
+ * PA_SU_LINE_CNTL struct
+ */
+
+#define PA_SU_LINE_CNTL_WIDTH_SIZE     16
+
+#define PA_SU_LINE_CNTL_WIDTH_SHIFT    0
+
+#define PA_SU_LINE_CNTL_WIDTH_MASK     0x0000ffff
+
+#define PA_SU_LINE_CNTL_MASK \
+     (PA_SU_LINE_CNTL_WIDTH_MASK)
+
+#define PA_SU_LINE_CNTL(width) \
+     ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT))
+
+#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \
+     ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \
+     pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+          unsigned int                                : 16;
+     } pa_su_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int                                : 16;
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+     } pa_su_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_line_cntl_t f;
+} pa_su_line_cntl_u;
+
+
+/*
+ * PA_SU_FACE_DATA struct
+ */
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5
+
+#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0
+
+#define PA_SU_FACE_DATA_MASK \
+     (PA_SU_FACE_DATA_BASE_ADDR_MASK)
+
+#define PA_SU_FACE_DATA(base_addr) \
+     ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT))
+
+#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \
+     ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \
+     pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int                                : 5;
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+     } pa_su_face_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+          unsigned int                                : 5;
+     } pa_su_face_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_face_data_t f;
+} pa_su_face_data_u;
+
+
+/*
+ * PA_SU_SC_MODE_CNTL struct
+ */
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_SIZE   1
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1
+#define PA_SU_SC_MODE_CNTL_FACE_SHIFT  2
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002
+#define PA_SU_SC_MODE_CNTL_FACE_MASK   0x00000004
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000
+
+#define PA_SU_SC_MODE_CNTL_MASK \
+     (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \
+      PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \
+      PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \
+      PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \
+      PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \
+      PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK)
+
+#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, zero_area_faceness, face_kill_enable, face_write_enable) \
+     ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \
+      (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \
+      (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \
+      (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \
+      (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \
+      (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \
+      (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \
+      (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \
+      (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \
+      (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \
+      (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \
+      (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \
+      (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \
+      (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \
+      (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \
+      (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \
+      (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \
+      (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \
+      (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \
+      (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \
+      (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT))
+
+#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int                                : 2;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_sc_mode_cntl_t f;
+} pa_su_sc_mode_cntl_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \
+     ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \
+     pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_scale_t f;
+} pa_su_poly_offset_front_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \
+     ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \
+     pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_offset_t f;
+} pa_su_poly_offset_front_offset_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \
+     ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \
+     pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_scale_t f;
+} pa_su_poly_offset_back_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \
+     ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \
+     pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_offset_t f;
+} pa_su_poly_offset_back_offset_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER0_SELECT_MASK \
+     (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \
+     ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \
+     pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_select_t f;
+} pa_su_perfcounter0_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER1_SELECT_MASK \
+     (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \
+     ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \
+     pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_select_t f;
+} pa_su_perfcounter1_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER2_SELECT_MASK \
+     (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \
+     ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \
+     pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_select_t f;
+} pa_su_perfcounter2_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER3_SELECT_MASK \
+     (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \
+     ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \
+     pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_select_t f;
+} pa_su_perfcounter3_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER0_LOW_MASK \
+     (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \
+     ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \
+     pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_low_t f;
+} pa_su_perfcounter0_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER0_HI_MASK \
+     (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \
+     ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \
+     pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_hi_t f;
+} pa_su_perfcounter0_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER1_LOW_MASK \
+     (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \
+     ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \
+     pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_low_t f;
+} pa_su_perfcounter1_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER1_HI_MASK \
+     (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \
+     ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \
+     pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_hi_t f;
+} pa_su_perfcounter1_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER2_LOW_MASK \
+     (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \
+     ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \
+     pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_low_t f;
+} pa_su_perfcounter2_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER2_HI_MASK \
+     (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \
+     ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \
+     pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_hi_t f;
+} pa_su_perfcounter2_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER3_LOW_MASK \
+     (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \
+     ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \
+     pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_low_t f;
+} pa_su_perfcounter3_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER3_HI_MASK \
+     (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \
+     ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \
+     pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_hi_t f;
+} pa_su_perfcounter3_hi_u;
+
+
+/*
+ * PA_SC_WINDOW_OFFSET struct
+ */
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000
+
+#define PA_SC_WINDOW_OFFSET_MASK \
+     (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \
+      PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK)
+
+#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \
+     ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \
+      (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT))
+
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_window_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+     } pa_sc_window_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_offset_t f;
+} pa_sc_window_offset_u;
+
+
+/*
+ * PA_SC_AA_CONFIG struct
+ */
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000
+
+#define PA_SC_AA_CONFIG_MASK \
+     (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \
+      PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK)
+
+#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \
+     ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \
+      (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT))
+
+#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+          unsigned int                                : 10;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 15;
+     } pa_sc_aa_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int                                : 15;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 10;
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+     } pa_sc_aa_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_config_t f;
+} pa_sc_aa_config_u;
+
+
+/*
+ * PA_SC_AA_MASK struct
+ */
+
+#define PA_SC_AA_MASK_AA_MASK_SIZE     16
+
+#define PA_SC_AA_MASK_AA_MASK_SHIFT    0
+
+#define PA_SC_AA_MASK_AA_MASK_MASK     0x0000ffff
+
+#define PA_SC_AA_MASK_MASK \
+     (PA_SC_AA_MASK_AA_MASK_MASK)
+
+#define PA_SC_AA_MASK(aa_mask) \
+     ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT))
+
+#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \
+     ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \
+     pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_aa_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int                                : 16;
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+     } pa_sc_aa_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_mask_t f;
+} pa_sc_aa_mask_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000
+
+#define PA_SC_LINE_STIPPLE_MASK \
+     (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \
+      PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \
+      PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \
+      PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK)
+
+#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \
+     ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \
+      (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \
+      (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \
+      (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_line_stipple_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int                                : 1;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int                                : 4;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+     } pa_sc_line_stipple_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_t f;
+} pa_sc_line_stipple_u;
+
+
+/*
+ * PA_SC_LINE_CNTL struct
+ */
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200
+#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400
+
+#define PA_SC_LINE_CNTL_MASK \
+     (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \
+      PA_SC_LINE_CNTL_LAST_PIXEL_MASK)
+
+#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \
+     ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \
+      (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \
+      (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \
+      (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT))
+
+#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int                                : 21;
+     } pa_sc_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int                                : 21;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+     } pa_sc_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_cntl_t f;
+} pa_sc_line_cntl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_TL struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000
+
+#define PA_SC_WINDOW_SCISSOR_TL_MASK \
+     (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \
+     ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \
+      (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_tl_t f;
+} pa_sc_window_scissor_tl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_BR struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000
+
+#define PA_SC_WINDOW_SCISSOR_BR_MASK \
+     (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+     } pa_sc_window_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_window_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_br_t f;
+} pa_sc_window_scissor_br_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_TL struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_TL_MASK \
+     (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \
+     ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_screen_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_tl_t f;
+} pa_sc_screen_scissor_tl_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_BR struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_BR_MASK \
+     (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_screen_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_br_t f;
+} pa_sc_screen_scissor_br_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY struct
+ */
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080
+
+#define PA_SC_VIZ_QUERY_MASK \
+     (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \
+      PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \
+      PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK)
+
+#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \
+     ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \
+      (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \
+      (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT))
+
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int                                : 1;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_viz_query_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int                                : 24;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 1;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+     } pa_sc_viz_query_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_t f;
+} pa_sc_viz_query_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY_STATUS struct
+ */
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff
+
+#define PA_SC_VIZ_QUERY_STATUS_MASK \
+     (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK)
+
+#define PA_SC_VIZ_QUERY_STATUS(status_bits) \
+     ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT))
+
+#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \
+     ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \
+     pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_status_t f;
+} pa_sc_viz_query_status_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE_STATE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00
+
+#define PA_SC_LINE_STIPPLE_STATE_MASK \
+     (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \
+      PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK)
+
+#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \
+     ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \
+      (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_line_stipple_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int                                : 16;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+     } pa_sc_line_stipple_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_state_t f;
+} pa_sc_line_stipple_state_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SC_PERFCOUNTER0_SELECT_MASK \
+     (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \
+     ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \
+     pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_sc_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_select_t f;
+} pa_sc_perfcounter0_select_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SC_PERFCOUNTER0_LOW_MASK \
+     (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \
+     ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \
+     pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_low_t f;
+} pa_sc_perfcounter0_low_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SC_PERFCOUNTER0_HI_MASK \
+     (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \
+     ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \
+     pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_hi_t f;
+} pa_sc_perfcounter0_hi_u;
+
+
+/*
+ * PA_CL_CNTL_STATUS struct
+ */
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000
+
+#define PA_CL_CNTL_STATUS_MASK \
+     (PA_CL_CNTL_STATUS_CL_BUSY_MASK)
+
+#define PA_CL_CNTL_STATUS(cl_busy) \
+     ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT))
+
+#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \
+     ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \
+     pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+     } pa_cl_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_cl_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_cntl_status_t f;
+} pa_cl_cntl_status_u;
+
+
+/*
+ * PA_SU_CNTL_STATUS struct
+ */
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000
+
+#define PA_SU_CNTL_STATUS_MASK \
+     (PA_SU_CNTL_STATUS_SU_BUSY_MASK)
+
+#define PA_SU_CNTL_STATUS(su_busy) \
+     ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT))
+
+#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \
+     ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \
+     pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+     } pa_su_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_su_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_cntl_status_t f;
+} pa_su_cntl_status_u;
+
+
+/*
+ * PA_SC_CNTL_STATUS struct
+ */
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000
+
+#define PA_SC_CNTL_STATUS_MASK \
+     (PA_SC_CNTL_STATUS_SC_BUSY_MASK)
+
+#define PA_SC_CNTL_STATUS(sc_busy) \
+     ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT))
+
+#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \
+     ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \
+     pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+     } pa_sc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_sc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_cntl_status_t f;
+} pa_sc_cntl_status_u;
+
+
+/*
+ * PA_SU_DEBUG_CNTL struct
+ */
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SU_DEBUG_CNTL_MASK \
+     (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK)
+
+#define PA_SU_DEBUG_CNTL(su_debug_indx) \
+     ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT))
+
+#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \
+     ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \
+     pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_su_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+     } pa_su_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_cntl_t f;
+} pa_su_debug_cntl_u;
+
+
+/*
+ * PA_SU_DEBUG_DATA struct
+ */
+
+#define PA_SU_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SU_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SU_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SU_DEBUG_DATA_MASK \
+     (PA_SU_DEBUG_DATA_DATA_MASK)
+
+#define PA_SU_DEBUG_DATA(data) \
+     ((data << PA_SU_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \
+     ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \
+     pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_data_t f;
+} pa_su_debug_data_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG00 struct
+ */
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000
+
+#define CLIPPER_DEBUG_REG00_MASK \
+     (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \
+     ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \
+      (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \
+      (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \
+      (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \
+      (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \
+      (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \
+      (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \
+      (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \
+      (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \
+      (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \
+      (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \
+      (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \
+      (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \
+      (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \
+      (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \
+      (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \
+      (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \
+      (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \
+      (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \
+      (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+     } clipper_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg00_t f;
+} clipper_debug_reg00_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG01 struct
+ */
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000
+
+#define CLIPPER_DEBUG_REG01_MASK \
+     (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \
+      CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \
+     ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \
+      (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \
+      (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \
+      (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \
+      (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \
+      (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \
+      (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+     } clipper_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg01_t f;
+} clipper_debug_reg01_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG02 struct
+ */
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+
+#define CLIPPER_DEBUG_REG02_MASK \
+     (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \
+      CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK)
+
+#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \
+     ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \
+      (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT))
+
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+     } clipper_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+     } clipper_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg02_t f;
+} clipper_debug_reg02_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG03 struct
+ */
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG03_MASK \
+     (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \
+     ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+     } clipper_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg03_t f;
+} clipper_debug_reg03_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG04 struct
+ */
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00
+
+#define CLIPPER_DEBUG_REG04_MASK \
+     (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \
+     ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+     } clipper_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg04_t f;
+} clipper_debug_reg04_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG05 struct
+ */
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000
+
+#define CLIPPER_DEBUG_REG05_MASK \
+     (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \
+     ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \
+      (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+     } clipper_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg05_t f;
+} clipper_debug_reg05_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG09 struct
+ */
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000
+#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000
+
+#define CLIPPER_DEBUG_REG09_MASK \
+     (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \
+      CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK)
+
+#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \
+     ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \
+      (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \
+      (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \
+      (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \
+      (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \
+      (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \
+      (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \
+      (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \
+      (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT))
+
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+     } clipper_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+     } clipper_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg09_t f;
+} clipper_debug_reg09_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG10 struct
+ */
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG10_MASK \
+     (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK)
+
+#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \
+     ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \
+      (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \
+      (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \
+      (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \
+      (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT))
+
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+     } clipper_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+     } clipper_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg10_t f;
+} clipper_debug_reg10_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG11 struct
+ */
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0
+
+#define CLIPPER_DEBUG_REG11_MASK \
+     (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \
+      CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \
+     ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+     } clipper_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg11_t f;
+} clipper_debug_reg11_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG12 struct
+ */
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define CLIPPER_DEBUG_REG12_MASK \
+     (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \
+      CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \
+     ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \
+      (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \
+      (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \
+      (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \
+      (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \
+      (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+     } clipper_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg12_t f;
+} clipper_debug_reg12_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG13 struct
+ */
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000
+#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000
+
+#define CLIPPER_DEBUG_REG13_MASK \
+     (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \
+     ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \
+      (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \
+      (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \
+      (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+     } clipper_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg13_t f;
+} clipper_debug_reg13_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG0 struct
+ */
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4
+#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3
+#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0
+#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380
+#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000
+
+#define SXIFCCG_DEBUG_REG0_MASK \
+     (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \
+      SXIFCCG_DEBUG_REG0_position_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG0_point_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK)
+
+#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \
+     ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \
+      (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \
+      (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \
+      (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \
+      (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \
+      (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \
+      (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \
+      (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT))
+
+#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg0_t f;
+} sxifccg_debug_reg0_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG1 struct
+ */
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4
+#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c
+#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000
+#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000
+#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000
+
+#define SXIFCCG_DEBUG_REG1_MASK \
+     (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \
+      SXIFCCG_DEBUG_REG1_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \
+      SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG1_aux_sel_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \
+      SXIFCCG_DEBUG_REG1_param_cache_base_MASK)
+
+#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \
+     ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \
+      (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \
+      (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \
+      (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \
+      (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \
+      (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \
+      (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \
+      (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT))
+
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg1_t f;
+} sxifccg_debug_reg1_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG2 struct
+ */
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002
+#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8
+#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000
+
+#define SXIFCCG_DEBUG_REG2_MASK \
+     (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_aux_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK)
+
+#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \
+     ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \
+      (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \
+      (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \
+      (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \
+      (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \
+      (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \
+      (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \
+      (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \
+      (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \
+      (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT))
+
+#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg2_t f;
+} sxifccg_debug_reg2_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG3 struct
+ */
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4
+#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8
+#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010
+#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00
+#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define SXIFCCG_DEBUG_REG3_MASK \
+     (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG3_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG3_current_state_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK)
+
+#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \
+     ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \
+      (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \
+      (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \
+      (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \
+      (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \
+      (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \
+      (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \
+      (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT))
+
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg3_t f;
+} sxifccg_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG0 struct
+ */
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5
+#define SETUP_DEBUG_REG0_pmode_state_SIZE 6
+#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1
+#define SETUP_DEBUG_REG0_geom_enable_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1
+#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1
+#define SETUP_DEBUG_REG0_geom_busy_SIZE 1
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0
+#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5
+#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11
+#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13
+#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14
+#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15
+#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16
+#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17
+
+#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f
+#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0
+#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800
+#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000
+#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000
+#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000
+#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000
+#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000
+
+#define SETUP_DEBUG_REG0_MASK \
+     (SETUP_DEBUG_REG0_su_cntl_state_MASK | \
+      SETUP_DEBUG_REG0_pmode_state_MASK | \
+      SETUP_DEBUG_REG0_ge_stallb_MASK | \
+      SETUP_DEBUG_REG0_geom_enable_MASK | \
+      SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \
+      SETUP_DEBUG_REG0_su_clip_rtr_MASK | \
+      SETUP_DEBUG_REG0_pfifo_busy_MASK | \
+      SETUP_DEBUG_REG0_su_cntl_busy_MASK | \
+      SETUP_DEBUG_REG0_geom_busy_MASK)
+
+#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \
+     ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \
+      (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \
+      (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \
+      (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \
+      (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \
+      (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \
+      (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \
+      (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \
+      (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT))
+
+#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int                                : 14;
+     } setup_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int                                : 14;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+     } setup_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg0_t f;
+} setup_debug_reg0_u;
+
+
+/*
+ * SETUP_DEBUG_REG1 struct
+ */
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG1_MASK \
+     (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \
+      SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \
+     ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \
+      (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int                                : 4;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+     } setup_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg1_t f;
+} setup_debug_reg1_u;
+
+
+/*
+ * SETUP_DEBUG_REG2 struct
+ */
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG2_MASK \
+     (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \
+      SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \
+     ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \
+      (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int                                : 4;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+     } setup_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg2_t f;
+} setup_debug_reg2_u;
+
+
+/*
+ * SETUP_DEBUG_REG3 struct
+ */
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG3_MASK \
+     (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \
+      SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \
+     ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \
+      (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int                                : 4;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+     } setup_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg3_t f;
+} setup_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG4 struct
+ */
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11
+#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1
+#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3
+#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3
+#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2
+#define SETUP_DEBUG_REG4_type_gated_SIZE 3
+#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_event_gated_SIZE 1
+#define SETUP_DEBUG_REG4_eop_gated_SIZE 1
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0
+#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11
+#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12
+#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13
+#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17
+#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21
+#define SETUP_DEBUG_REG4_type_gated_SHIFT 23
+#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27
+#define SETUP_DEBUG_REG4_event_gated_SHIFT 28
+#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800
+#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000
+#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000
+#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000
+#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000
+#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000
+#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000
+#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000
+#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000
+#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000
+
+#define SETUP_DEBUG_REG4_MASK \
+     (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \
+      SETUP_DEBUG_REG4_null_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_backfacing_gated_MASK | \
+      SETUP_DEBUG_REG4_st_indx_gated_MASK | \
+      SETUP_DEBUG_REG4_clipped_gated_MASK | \
+      SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \
+      SETUP_DEBUG_REG4_xmajor_gated_MASK | \
+      SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \
+      SETUP_DEBUG_REG4_type_gated_MASK | \
+      SETUP_DEBUG_REG4_fpov_gated_MASK | \
+      SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_event_gated_MASK | \
+      SETUP_DEBUG_REG4_eop_gated_MASK)
+
+#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \
+     ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \
+      (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \
+      (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \
+      (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \
+      (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \
+      (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \
+      (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \
+      (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \
+      (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \
+      (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \
+      (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \
+      (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \
+      (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT))
+
+#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int                                : 2;
+     } setup_debug_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int                                : 2;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+     } setup_debug_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg4_t f;
+} setup_debug_reg4_u;
+
+
+/*
+ * SETUP_DEBUG_REG5 struct
+ */
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2
+#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22
+#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000
+#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000
+
+#define SETUP_DEBUG_REG5_MASK \
+     (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \
+      SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \
+      SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \
+      SETUP_DEBUG_REG5_event_id_gated_MASK)
+
+#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \
+     ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \
+      (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \
+      (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \
+      (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT))
+
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int                                : 3;
+     } setup_debug_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int                                : 3;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+     } setup_debug_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg5_t f;
+} setup_debug_reg5_u;
+
+
+/*
+ * PA_SC_DEBUG_CNTL struct
+ */
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SC_DEBUG_CNTL_MASK \
+     (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK)
+
+#define PA_SC_DEBUG_CNTL(sc_debug_indx) \
+     ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT))
+
+#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \
+     ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \
+     pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_sc_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+     } pa_sc_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_cntl_t f;
+} pa_sc_debug_cntl_u;
+
+
+/*
+ * PA_SC_DEBUG_DATA struct
+ */
+
+#define PA_SC_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SC_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SC_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SC_DEBUG_DATA_MASK \
+     (PA_SC_DEBUG_DATA_DATA_MASK)
+
+#define PA_SC_DEBUG_DATA(data) \
+     ((data << PA_SC_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \
+     ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \
+     pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_data_t f;
+} pa_sc_debug_data_u;
+
+
+/*
+ * SC_DEBUG_0 struct
+ */
+
+#define SC_DEBUG_0_pa_freeze_b1_SIZE   1
+#define SC_DEBUG_0_pa_sc_valid_SIZE    1
+#define SC_DEBUG_0_pa_sc_phase_SIZE    3
+#define SC_DEBUG_0_cntx_cnt_SIZE       7
+#define SC_DEBUG_0_decr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_incr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_trigger_SIZE        1
+
+#define SC_DEBUG_0_pa_freeze_b1_SHIFT  0
+#define SC_DEBUG_0_pa_sc_valid_SHIFT   1
+#define SC_DEBUG_0_pa_sc_phase_SHIFT   2
+#define SC_DEBUG_0_cntx_cnt_SHIFT      5
+#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12
+#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13
+#define SC_DEBUG_0_trigger_SHIFT       31
+
+#define SC_DEBUG_0_pa_freeze_b1_MASK   0x00000001
+#define SC_DEBUG_0_pa_sc_valid_MASK    0x00000002
+#define SC_DEBUG_0_pa_sc_phase_MASK    0x0000001c
+#define SC_DEBUG_0_cntx_cnt_MASK       0x00000fe0
+#define SC_DEBUG_0_decr_cntx_cnt_MASK  0x00001000
+#define SC_DEBUG_0_incr_cntx_cnt_MASK  0x00002000
+#define SC_DEBUG_0_trigger_MASK        0x80000000
+
+#define SC_DEBUG_0_MASK \
+     (SC_DEBUG_0_pa_freeze_b1_MASK | \
+      SC_DEBUG_0_pa_sc_valid_MASK | \
+      SC_DEBUG_0_pa_sc_phase_MASK | \
+      SC_DEBUG_0_cntx_cnt_MASK | \
+      SC_DEBUG_0_decr_cntx_cnt_MASK | \
+      SC_DEBUG_0_incr_cntx_cnt_MASK | \
+      SC_DEBUG_0_trigger_MASK)
+
+#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \
+     ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \
+      (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \
+      (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \
+      (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \
+      (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \
+      (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \
+      (trigger << SC_DEBUG_0_trigger_SHIFT))
+
+#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_trigger(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT)
+
+#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int                                : 17;
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+     } sc_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+          unsigned int                                : 17;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+     } sc_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_0_t f;
+} sc_debug_0_u;
+
+
+/*
+ * SC_DEBUG_1 struct
+ */
+
+#define SC_DEBUG_1_em_state_SIZE       3
+#define SC_DEBUG_1_em1_data_ready_SIZE 1
+#define SC_DEBUG_1_em2_data_ready_SIZE 1
+#define SC_DEBUG_1_move_em1_to_em2_SIZE 1
+#define SC_DEBUG_1_ef_data_ready_SIZE  1
+#define SC_DEBUG_1_ef_state_SIZE       2
+#define SC_DEBUG_1_pipe_valid_SIZE     1
+#define SC_DEBUG_1_trigger_SIZE        1
+
+#define SC_DEBUG_1_em_state_SHIFT      0
+#define SC_DEBUG_1_em1_data_ready_SHIFT 3
+#define SC_DEBUG_1_em2_data_ready_SHIFT 4
+#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5
+#define SC_DEBUG_1_ef_data_ready_SHIFT 6
+#define SC_DEBUG_1_ef_state_SHIFT      7
+#define SC_DEBUG_1_pipe_valid_SHIFT    9
+#define SC_DEBUG_1_trigger_SHIFT       31
+
+#define SC_DEBUG_1_em_state_MASK       0x00000007
+#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008
+#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010
+#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020
+#define SC_DEBUG_1_ef_data_ready_MASK  0x00000040
+#define SC_DEBUG_1_ef_state_MASK       0x00000180
+#define SC_DEBUG_1_pipe_valid_MASK     0x00000200
+#define SC_DEBUG_1_trigger_MASK        0x80000000
+
+#define SC_DEBUG_1_MASK \
+     (SC_DEBUG_1_em_state_MASK | \
+      SC_DEBUG_1_em1_data_ready_MASK | \
+      SC_DEBUG_1_em2_data_ready_MASK | \
+      SC_DEBUG_1_move_em1_to_em2_MASK | \
+      SC_DEBUG_1_ef_data_ready_MASK | \
+      SC_DEBUG_1_ef_state_MASK | \
+      SC_DEBUG_1_pipe_valid_MASK | \
+      SC_DEBUG_1_trigger_MASK)
+
+#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \
+     ((em_state << SC_DEBUG_1_em_state_SHIFT) | \
+      (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \
+      (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \
+      (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \
+      (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \
+      (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \
+      (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \
+      (trigger << SC_DEBUG_1_trigger_SHIFT))
+
+#define SC_DEBUG_1_GET_em_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_GET_trigger(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT)
+
+#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int                                : 21;
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+     } sc_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+          unsigned int                                : 21;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+     } sc_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_1_t f;
+} sc_debug_1_u;
+
+
+/*
+ * SC_DEBUG_2 struct
+ */
+
+#define SC_DEBUG_2_rc_rtr_dly_SIZE     1
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1
+#define SC_DEBUG_2_pipe_freeze_b_SIZE  1
+#define SC_DEBUG_2_prim_rts_SIZE       1
+#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1
+#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1
+#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1
+#define SC_DEBUG_2_stage0_rts_SIZE     1
+#define SC_DEBUG_2_phase_rts_dly_SIZE  1
+#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1
+#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1
+#define SC_DEBUG_2_event_id_s1_SIZE    5
+#define SC_DEBUG_2_event_s1_SIZE       1
+#define SC_DEBUG_2_trigger_SIZE        1
+
+#define SC_DEBUG_2_rc_rtr_dly_SHIFT    0
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1
+#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3
+#define SC_DEBUG_2_prim_rts_SHIFT      4
+#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5
+#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6
+#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7
+#define SC_DEBUG_2_stage0_rts_SHIFT    8
+#define SC_DEBUG_2_phase_rts_dly_SHIFT 9
+#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15
+#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16
+#define SC_DEBUG_2_event_id_s1_SHIFT   17
+#define SC_DEBUG_2_event_s1_SHIFT      22
+#define SC_DEBUG_2_trigger_SHIFT       31
+
+#define SC_DEBUG_2_rc_rtr_dly_MASK     0x00000001
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002
+#define SC_DEBUG_2_pipe_freeze_b_MASK  0x00000008
+#define SC_DEBUG_2_prim_rts_MASK       0x00000010
+#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020
+#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040
+#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080
+#define SC_DEBUG_2_stage0_rts_MASK     0x00000100
+#define SC_DEBUG_2_phase_rts_dly_MASK  0x00000200
+#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000
+#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000
+#define SC_DEBUG_2_event_id_s1_MASK    0x003e0000
+#define SC_DEBUG_2_event_s1_MASK       0x00400000
+#define SC_DEBUG_2_trigger_MASK        0x80000000
+
+#define SC_DEBUG_2_MASK \
+     (SC_DEBUG_2_rc_rtr_dly_MASK | \
+      SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \
+      SC_DEBUG_2_pipe_freeze_b_MASK | \
+      SC_DEBUG_2_prim_rts_MASK | \
+      SC_DEBUG_2_next_prim_rts_dly_MASK | \
+      SC_DEBUG_2_next_prim_rtr_dly_MASK | \
+      SC_DEBUG_2_pre_stage1_rts_d1_MASK | \
+      SC_DEBUG_2_stage0_rts_MASK | \
+      SC_DEBUG_2_phase_rts_dly_MASK | \
+      SC_DEBUG_2_end_of_prim_s1_dly_MASK | \
+      SC_DEBUG_2_pass_empty_prim_s1_MASK | \
+      SC_DEBUG_2_event_id_s1_MASK | \
+      SC_DEBUG_2_event_s1_MASK | \
+      SC_DEBUG_2_trigger_MASK)
+
+#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \
+     ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \
+      (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \
+      (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \
+      (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \
+      (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \
+      (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \
+      (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \
+      (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \
+      (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \
+      (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \
+      (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \
+      (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \
+      (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \
+      (trigger << SC_DEBUG_2_trigger_SHIFT))
+
+#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_GET_trigger(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT)
+
+#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int                                : 1;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int                                : 8;
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+     } sc_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+          unsigned int                                : 8;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int                                : 1;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+     } sc_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_2_t f;
+} sc_debug_2_u;
+
+
+/*
+ * SC_DEBUG_3 struct
+ */
+
+#define SC_DEBUG_3_x_curr_s1_SIZE      11
+#define SC_DEBUG_3_y_curr_s1_SIZE      11
+#define SC_DEBUG_3_trigger_SIZE        1
+
+#define SC_DEBUG_3_x_curr_s1_SHIFT     0
+#define SC_DEBUG_3_y_curr_s1_SHIFT     11
+#define SC_DEBUG_3_trigger_SHIFT       31
+
+#define SC_DEBUG_3_x_curr_s1_MASK      0x000007ff
+#define SC_DEBUG_3_y_curr_s1_MASK      0x003ff800
+#define SC_DEBUG_3_trigger_MASK        0x80000000
+
+#define SC_DEBUG_3_MASK \
+     (SC_DEBUG_3_x_curr_s1_MASK | \
+      SC_DEBUG_3_y_curr_s1_MASK | \
+      SC_DEBUG_3_trigger_MASK)
+
+#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \
+     ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \
+      (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \
+      (trigger << SC_DEBUG_3_trigger_SHIFT))
+
+#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_trigger(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT)
+
+#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int                                : 9;
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+     } sc_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+          unsigned int                                : 9;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+     } sc_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_3_t f;
+} sc_debug_3_u;
+
+
+/*
+ * SC_DEBUG_4 struct
+ */
+
+#define SC_DEBUG_4_y_end_s1_SIZE       14
+#define SC_DEBUG_4_y_start_s1_SIZE     14
+#define SC_DEBUG_4_y_dir_s1_SIZE       1
+#define SC_DEBUG_4_trigger_SIZE        1
+
+#define SC_DEBUG_4_y_end_s1_SHIFT      0
+#define SC_DEBUG_4_y_start_s1_SHIFT    14
+#define SC_DEBUG_4_y_dir_s1_SHIFT      28
+#define SC_DEBUG_4_trigger_SHIFT       31
+
+#define SC_DEBUG_4_y_end_s1_MASK       0x00003fff
+#define SC_DEBUG_4_y_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_4_y_dir_s1_MASK       0x10000000
+#define SC_DEBUG_4_trigger_MASK        0x80000000
+
+#define SC_DEBUG_4_MASK \
+     (SC_DEBUG_4_y_end_s1_MASK | \
+      SC_DEBUG_4_y_start_s1_MASK | \
+      SC_DEBUG_4_y_dir_s1_MASK | \
+      SC_DEBUG_4_trigger_MASK)
+
+#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \
+     ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \
+      (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \
+      (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_4_trigger_SHIFT))
+
+#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_GET_trigger(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT)
+
+#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+     } sc_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+     } sc_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_4_t f;
+} sc_debug_4_u;
+
+
+/*
+ * SC_DEBUG_5 struct
+ */
+
+#define SC_DEBUG_5_x_end_s1_SIZE       14
+#define SC_DEBUG_5_x_start_s1_SIZE     14
+#define SC_DEBUG_5_x_dir_s1_SIZE       1
+#define SC_DEBUG_5_trigger_SIZE        1
+
+#define SC_DEBUG_5_x_end_s1_SHIFT      0
+#define SC_DEBUG_5_x_start_s1_SHIFT    14
+#define SC_DEBUG_5_x_dir_s1_SHIFT      28
+#define SC_DEBUG_5_trigger_SHIFT       31
+
+#define SC_DEBUG_5_x_end_s1_MASK       0x00003fff
+#define SC_DEBUG_5_x_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_5_x_dir_s1_MASK       0x10000000
+#define SC_DEBUG_5_trigger_MASK        0x80000000
+
+#define SC_DEBUG_5_MASK \
+     (SC_DEBUG_5_x_end_s1_MASK | \
+      SC_DEBUG_5_x_start_s1_MASK | \
+      SC_DEBUG_5_x_dir_s1_MASK | \
+      SC_DEBUG_5_trigger_MASK)
+
+#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \
+     ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \
+      (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \
+      (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_5_trigger_SHIFT))
+
+#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_GET_trigger(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT)
+
+#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+     } sc_debug_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+     } sc_debug_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_5_t f;
+} sc_debug_5_u;
+
+
+/*
+ * SC_DEBUG_6 struct
+ */
+
+#define SC_DEBUG_6_z_ff_empty_SIZE     1
+#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1
+#define SC_DEBUG_6_xy_ff_empty_SIZE    1
+#define SC_DEBUG_6_event_flag_SIZE     1
+#define SC_DEBUG_6_z_mask_needed_SIZE  1
+#define SC_DEBUG_6_state_SIZE          3
+#define SC_DEBUG_6_state_delayed_SIZE  3
+#define SC_DEBUG_6_data_valid_SIZE     1
+#define SC_DEBUG_6_data_valid_d_SIZE   1
+#define SC_DEBUG_6_tilex_delayed_SIZE  9
+#define SC_DEBUG_6_tiley_delayed_SIZE  9
+#define SC_DEBUG_6_trigger_SIZE        1
+
+#define SC_DEBUG_6_z_ff_empty_SHIFT    0
+#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1
+#define SC_DEBUG_6_xy_ff_empty_SHIFT   2
+#define SC_DEBUG_6_event_flag_SHIFT    3
+#define SC_DEBUG_6_z_mask_needed_SHIFT 4
+#define SC_DEBUG_6_state_SHIFT         5
+#define SC_DEBUG_6_state_delayed_SHIFT 8
+#define SC_DEBUG_6_data_valid_SHIFT    11
+#define SC_DEBUG_6_data_valid_d_SHIFT  12
+#define SC_DEBUG_6_tilex_delayed_SHIFT 13
+#define SC_DEBUG_6_tiley_delayed_SHIFT 22
+#define SC_DEBUG_6_trigger_SHIFT       31
+
+#define SC_DEBUG_6_z_ff_empty_MASK     0x00000001
+#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002
+#define SC_DEBUG_6_xy_ff_empty_MASK    0x00000004
+#define SC_DEBUG_6_event_flag_MASK     0x00000008
+#define SC_DEBUG_6_z_mask_needed_MASK  0x00000010
+#define SC_DEBUG_6_state_MASK          0x000000e0
+#define SC_DEBUG_6_state_delayed_MASK  0x00000700
+#define SC_DEBUG_6_data_valid_MASK     0x00000800
+#define SC_DEBUG_6_data_valid_d_MASK   0x00001000
+#define SC_DEBUG_6_tilex_delayed_MASK  0x003fe000
+#define SC_DEBUG_6_tiley_delayed_MASK  0x7fc00000
+#define SC_DEBUG_6_trigger_MASK        0x80000000
+
+#define SC_DEBUG_6_MASK \
+     (SC_DEBUG_6_z_ff_empty_MASK | \
+      SC_DEBUG_6_qmcntl_ff_empty_MASK | \
+      SC_DEBUG_6_xy_ff_empty_MASK | \
+      SC_DEBUG_6_event_flag_MASK | \
+      SC_DEBUG_6_z_mask_needed_MASK | \
+      SC_DEBUG_6_state_MASK | \
+      SC_DEBUG_6_state_delayed_MASK | \
+      SC_DEBUG_6_data_valid_MASK | \
+      SC_DEBUG_6_data_valid_d_MASK | \
+      SC_DEBUG_6_tilex_delayed_MASK | \
+      SC_DEBUG_6_tiley_delayed_MASK | \
+      SC_DEBUG_6_trigger_MASK)
+
+#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \
+     ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \
+      (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \
+      (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \
+      (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \
+      (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \
+      (state << SC_DEBUG_6_state_SHIFT) | \
+      (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \
+      (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \
+      (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \
+      (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \
+      (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \
+      (trigger << SC_DEBUG_6_trigger_SHIFT))
+
+#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_GET_state(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_GET_trigger(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT)
+
+#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+     } sc_debug_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+     } sc_debug_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_6_t f;
+} sc_debug_6_u;
+
+
+/*
+ * SC_DEBUG_7 struct
+ */
+
+#define SC_DEBUG_7_event_flag_SIZE     1
+#define SC_DEBUG_7_deallocate_SIZE     3
+#define SC_DEBUG_7_fposition_SIZE      1
+#define SC_DEBUG_7_sr_prim_we_SIZE     1
+#define SC_DEBUG_7_last_tile_SIZE      1
+#define SC_DEBUG_7_tile_ff_we_SIZE     1
+#define SC_DEBUG_7_qs_data_valid_SIZE  1
+#define SC_DEBUG_7_qs_q0_y_SIZE        2
+#define SC_DEBUG_7_qs_q0_x_SIZE        2
+#define SC_DEBUG_7_qs_q0_valid_SIZE    1
+#define SC_DEBUG_7_prim_ff_we_SIZE     1
+#define SC_DEBUG_7_tile_ff_re_SIZE     1
+#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_7_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_7_new_prim_SIZE       1
+#define SC_DEBUG_7_load_new_tile_data_SIZE 1
+#define SC_DEBUG_7_state_SIZE          2
+#define SC_DEBUG_7_fifos_ready_SIZE    1
+#define SC_DEBUG_7_trigger_SIZE        1
+
+#define SC_DEBUG_7_event_flag_SHIFT    0
+#define SC_DEBUG_7_deallocate_SHIFT    1
+#define SC_DEBUG_7_fposition_SHIFT     4
+#define SC_DEBUG_7_sr_prim_we_SHIFT    5
+#define SC_DEBUG_7_last_tile_SHIFT     6
+#define SC_DEBUG_7_tile_ff_we_SHIFT    7
+#define SC_DEBUG_7_qs_data_valid_SHIFT 8
+#define SC_DEBUG_7_qs_q0_y_SHIFT       9
+#define SC_DEBUG_7_qs_q0_x_SHIFT       11
+#define SC_DEBUG_7_qs_q0_valid_SHIFT   13
+#define SC_DEBUG_7_prim_ff_we_SHIFT    14
+#define SC_DEBUG_7_tile_ff_re_SHIFT    15
+#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16
+#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17
+#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18
+#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19
+#define SC_DEBUG_7_new_prim_SHIFT      20
+#define SC_DEBUG_7_load_new_tile_data_SHIFT 21
+#define SC_DEBUG_7_state_SHIFT         22
+#define SC_DEBUG_7_fifos_ready_SHIFT   24
+#define SC_DEBUG_7_trigger_SHIFT       31
+
+#define SC_DEBUG_7_event_flag_MASK     0x00000001
+#define SC_DEBUG_7_deallocate_MASK     0x0000000e
+#define SC_DEBUG_7_fposition_MASK      0x00000010
+#define SC_DEBUG_7_sr_prim_we_MASK     0x00000020
+#define SC_DEBUG_7_last_tile_MASK      0x00000040
+#define SC_DEBUG_7_tile_ff_we_MASK     0x00000080
+#define SC_DEBUG_7_qs_data_valid_MASK  0x00000100
+#define SC_DEBUG_7_qs_q0_y_MASK        0x00000600
+#define SC_DEBUG_7_qs_q0_x_MASK        0x00001800
+#define SC_DEBUG_7_qs_q0_valid_MASK    0x00002000
+#define SC_DEBUG_7_prim_ff_we_MASK     0x00004000
+#define SC_DEBUG_7_tile_ff_re_MASK     0x00008000
+#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000
+#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000
+#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000
+#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000
+#define SC_DEBUG_7_new_prim_MASK       0x00100000
+#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000
+#define SC_DEBUG_7_state_MASK          0x00c00000
+#define SC_DEBUG_7_fifos_ready_MASK    0x01000000
+#define SC_DEBUG_7_trigger_MASK        0x80000000
+
+#define SC_DEBUG_7_MASK \
+     (SC_DEBUG_7_event_flag_MASK | \
+      SC_DEBUG_7_deallocate_MASK | \
+      SC_DEBUG_7_fposition_MASK | \
+      SC_DEBUG_7_sr_prim_we_MASK | \
+      SC_DEBUG_7_last_tile_MASK | \
+      SC_DEBUG_7_tile_ff_we_MASK | \
+      SC_DEBUG_7_qs_data_valid_MASK | \
+      SC_DEBUG_7_qs_q0_y_MASK | \
+      SC_DEBUG_7_qs_q0_x_MASK | \
+      SC_DEBUG_7_qs_q0_valid_MASK | \
+      SC_DEBUG_7_prim_ff_we_MASK | \
+      SC_DEBUG_7_tile_ff_re_MASK | \
+      SC_DEBUG_7_fw_prim_data_valid_MASK | \
+      SC_DEBUG_7_last_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_prim_MASK | \
+      SC_DEBUG_7_new_prim_MASK | \
+      SC_DEBUG_7_load_new_tile_data_MASK | \
+      SC_DEBUG_7_state_MASK | \
+      SC_DEBUG_7_fifos_ready_MASK | \
+      SC_DEBUG_7_trigger_MASK)
+
+#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \
+     ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \
+      (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \
+      (fposition << SC_DEBUG_7_fposition_SHIFT) | \
+      (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \
+      (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \
+      (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \
+      (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \
+      (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \
+      (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \
+      (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \
+      (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \
+      (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \
+      (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \
+      (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \
+      (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \
+      (state << SC_DEBUG_7_state_SHIFT) | \
+      (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \
+      (trigger << SC_DEBUG_7_trigger_SHIFT))
+
+#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_GET_fposition(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_GET_state(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_GET_trigger(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT)
+
+#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int                                : 6;
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+     } sc_debug_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+          unsigned int                                : 6;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+     } sc_debug_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_7_t f;
+} sc_debug_7_u;
+
+
+/*
+ * SC_DEBUG_8 struct
+ */
+
+#define SC_DEBUG_8_sample_last_SIZE    1
+#define SC_DEBUG_8_sample_mask_SIZE    4
+#define SC_DEBUG_8_sample_y_SIZE       2
+#define SC_DEBUG_8_sample_x_SIZE       2
+#define SC_DEBUG_8_sample_send_SIZE    1
+#define SC_DEBUG_8_next_cycle_SIZE     2
+#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1
+#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1
+#define SC_DEBUG_8_num_samples_SIZE    2
+#define SC_DEBUG_8_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_8_last_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_sample_we_SIZE      1
+#define SC_DEBUG_8_fposition_SIZE      1
+#define SC_DEBUG_8_event_id_SIZE       5
+#define SC_DEBUG_8_event_flag_SIZE     1
+#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_8_trigger_SIZE        1
+
+#define SC_DEBUG_8_sample_last_SHIFT   0
+#define SC_DEBUG_8_sample_mask_SHIFT   1
+#define SC_DEBUG_8_sample_y_SHIFT      5
+#define SC_DEBUG_8_sample_x_SHIFT      7
+#define SC_DEBUG_8_sample_send_SHIFT   9
+#define SC_DEBUG_8_next_cycle_SHIFT    10
+#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12
+#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13
+#define SC_DEBUG_8_num_samples_SHIFT   14
+#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16
+#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17
+#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18
+#define SC_DEBUG_8_sample_we_SHIFT     19
+#define SC_DEBUG_8_fposition_SHIFT     20
+#define SC_DEBUG_8_event_id_SHIFT      21
+#define SC_DEBUG_8_event_flag_SHIFT    26
+#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27
+#define SC_DEBUG_8_trigger_SHIFT       31
+
+#define SC_DEBUG_8_sample_last_MASK    0x00000001
+#define SC_DEBUG_8_sample_mask_MASK    0x0000001e
+#define SC_DEBUG_8_sample_y_MASK       0x00000060
+#define SC_DEBUG_8_sample_x_MASK       0x00000180
+#define SC_DEBUG_8_sample_send_MASK    0x00000200
+#define SC_DEBUG_8_next_cycle_MASK     0x00000c00
+#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000
+#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000
+#define SC_DEBUG_8_num_samples_MASK    0x0000c000
+#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000
+#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000
+#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000
+#define SC_DEBUG_8_sample_we_MASK      0x00080000
+#define SC_DEBUG_8_fposition_MASK      0x00100000
+#define SC_DEBUG_8_event_id_MASK       0x03e00000
+#define SC_DEBUG_8_event_flag_MASK     0x04000000
+#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000
+#define SC_DEBUG_8_trigger_MASK        0x80000000
+
+#define SC_DEBUG_8_MASK \
+     (SC_DEBUG_8_sample_last_MASK | \
+      SC_DEBUG_8_sample_mask_MASK | \
+      SC_DEBUG_8_sample_y_MASK | \
+      SC_DEBUG_8_sample_x_MASK | \
+      SC_DEBUG_8_sample_send_MASK | \
+      SC_DEBUG_8_next_cycle_MASK | \
+      SC_DEBUG_8_ez_sample_ff_full_MASK | \
+      SC_DEBUG_8_rb_sc_samp_rtr_MASK | \
+      SC_DEBUG_8_num_samples_MASK | \
+      SC_DEBUG_8_last_quad_of_tile_MASK | \
+      SC_DEBUG_8_last_quad_of_prim_MASK | \
+      SC_DEBUG_8_first_quad_of_prim_MASK | \
+      SC_DEBUG_8_sample_we_MASK | \
+      SC_DEBUG_8_fposition_MASK | \
+      SC_DEBUG_8_event_id_MASK | \
+      SC_DEBUG_8_event_flag_MASK | \
+      SC_DEBUG_8_fw_prim_data_valid_MASK | \
+      SC_DEBUG_8_trigger_MASK)
+
+#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \
+     ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \
+      (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \
+      (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \
+      (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \
+      (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \
+      (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \
+      (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \
+      (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \
+      (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \
+      (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \
+      (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \
+      (fposition << SC_DEBUG_8_fposition_SHIFT) | \
+      (event_id << SC_DEBUG_8_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \
+      (trigger << SC_DEBUG_8_trigger_SHIFT))
+
+#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_GET_fposition(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_GET_event_id(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_GET_trigger(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT)
+
+#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int                                : 3;
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+     } sc_debug_8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+     } sc_debug_8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_8_t f;
+} sc_debug_8_u;
+
+
+/*
+ * SC_DEBUG_9 struct
+ */
+
+#define SC_DEBUG_9_rb_sc_send_SIZE     1
+#define SC_DEBUG_9_rb_sc_ez_mask_SIZE  4
+#define SC_DEBUG_9_fifo_data_ready_SIZE 1
+#define SC_DEBUG_9_early_z_enable_SIZE 1
+#define SC_DEBUG_9_mask_state_SIZE     2
+#define SC_DEBUG_9_next_ez_mask_SIZE   16
+#define SC_DEBUG_9_mask_ready_SIZE     1
+#define SC_DEBUG_9_drop_sample_SIZE    1
+#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_9_trigger_SIZE        1
+
+#define SC_DEBUG_9_rb_sc_send_SHIFT    0
+#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1
+#define SC_DEBUG_9_fifo_data_ready_SHIFT 5
+#define SC_DEBUG_9_early_z_enable_SHIFT 6
+#define SC_DEBUG_9_mask_state_SHIFT    7
+#define SC_DEBUG_9_next_ez_mask_SHIFT  9
+#define SC_DEBUG_9_mask_ready_SHIFT    25
+#define SC_DEBUG_9_drop_sample_SHIFT   26
+#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30
+#define SC_DEBUG_9_trigger_SHIFT       31
+
+#define SC_DEBUG_9_rb_sc_send_MASK     0x00000001
+#define SC_DEBUG_9_rb_sc_ez_mask_MASK  0x0000001e
+#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020
+#define SC_DEBUG_9_early_z_enable_MASK 0x00000040
+#define SC_DEBUG_9_mask_state_MASK     0x00000180
+#define SC_DEBUG_9_next_ez_mask_MASK   0x01fffe00
+#define SC_DEBUG_9_mask_ready_MASK     0x02000000
+#define SC_DEBUG_9_drop_sample_MASK    0x04000000
+#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000
+#define SC_DEBUG_9_trigger_MASK        0x80000000
+
+#define SC_DEBUG_9_MASK \
+     (SC_DEBUG_9_rb_sc_send_MASK | \
+      SC_DEBUG_9_rb_sc_ez_mask_MASK | \
+      SC_DEBUG_9_fifo_data_ready_MASK | \
+      SC_DEBUG_9_early_z_enable_MASK | \
+      SC_DEBUG_9_mask_state_MASK | \
+      SC_DEBUG_9_next_ez_mask_MASK | \
+      SC_DEBUG_9_mask_ready_MASK | \
+      SC_DEBUG_9_drop_sample_MASK | \
+      SC_DEBUG_9_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_9_trigger_MASK)
+
+#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \
+     ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \
+      (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \
+      (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \
+      (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \
+      (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \
+      (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \
+      (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \
+      (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \
+      (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \
+      (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \
+      (trigger << SC_DEBUG_9_trigger_SHIFT))
+
+#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_GET_trigger(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT)
+
+#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+     } sc_debug_9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+     } sc_debug_9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_9_t f;
+} sc_debug_9_u;
+
+
+/*
+ * SC_DEBUG_10 struct
+ */
+
+#define SC_DEBUG_10_combined_sample_mask_SIZE 16
+#define SC_DEBUG_10_trigger_SIZE       1
+
+#define SC_DEBUG_10_combined_sample_mask_SHIFT 0
+#define SC_DEBUG_10_trigger_SHIFT      31
+
+#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff
+#define SC_DEBUG_10_trigger_MASK       0x80000000
+
+#define SC_DEBUG_10_MASK \
+     (SC_DEBUG_10_combined_sample_mask_MASK | \
+      SC_DEBUG_10_trigger_MASK)
+
+#define SC_DEBUG_10(combined_sample_mask, trigger) \
+     ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \
+      (trigger << SC_DEBUG_10_trigger_SHIFT))
+
+#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_GET_trigger(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT)
+
+#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+          unsigned int                                : 15;
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+     } sc_debug_10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+          unsigned int                                : 15;
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+     } sc_debug_10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_10_t f;
+} sc_debug_10_u;
+
+
+/*
+ * SC_DEBUG_11 struct
+ */
+
+#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_11_iterator_input_fz_SIZE 1
+#define SC_DEBUG_11_packer_send_quads_SIZE 1
+#define SC_DEBUG_11_packer_send_cmd_SIZE 1
+#define SC_DEBUG_11_packer_send_event_SIZE 1
+#define SC_DEBUG_11_next_state_SIZE    3
+#define SC_DEBUG_11_state_SIZE         3
+#define SC_DEBUG_11_stall_SIZE         1
+#define SC_DEBUG_11_trigger_SIZE       1
+
+#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1
+#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3
+#define SC_DEBUG_11_iterator_input_fz_SHIFT 4
+#define SC_DEBUG_11_packer_send_quads_SHIFT 5
+#define SC_DEBUG_11_packer_send_cmd_SHIFT 6
+#define SC_DEBUG_11_packer_send_event_SHIFT 7
+#define SC_DEBUG_11_next_state_SHIFT   8
+#define SC_DEBUG_11_state_SHIFT        11
+#define SC_DEBUG_11_stall_SHIFT        14
+#define SC_DEBUG_11_trigger_SHIFT      31
+
+#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002
+#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008
+#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010
+#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020
+#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040
+#define SC_DEBUG_11_packer_send_event_MASK 0x00000080
+#define SC_DEBUG_11_next_state_MASK    0x00000700
+#define SC_DEBUG_11_state_MASK         0x00003800
+#define SC_DEBUG_11_stall_MASK         0x00004000
+#define SC_DEBUG_11_trigger_MASK       0x80000000
+
+#define SC_DEBUG_11_MASK \
+     (SC_DEBUG_11_ez_sample_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_11_ez_prim_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_11_iterator_input_fz_MASK | \
+      SC_DEBUG_11_packer_send_quads_MASK | \
+      SC_DEBUG_11_packer_send_cmd_MASK | \
+      SC_DEBUG_11_packer_send_event_MASK | \
+      SC_DEBUG_11_next_state_MASK | \
+      SC_DEBUG_11_state_MASK | \
+      SC_DEBUG_11_stall_MASK | \
+      SC_DEBUG_11_trigger_MASK)
+
+#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \
+     ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \
+      (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \
+      (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \
+      (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \
+      (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \
+      (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \
+      (next_state << SC_DEBUG_11_next_state_SHIFT) | \
+      (state << SC_DEBUG_11_state_SHIFT) | \
+      (stall << SC_DEBUG_11_stall_SHIFT) | \
+      (trigger << SC_DEBUG_11_trigger_SHIFT))
+
+#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_GET_next_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_GET_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_GET_stall(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_GET_trigger(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT)
+
+#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int                                : 16;
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+     } sc_debug_11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+          unsigned int                                : 16;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+     } sc_debug_11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_11_t f;
+} sc_debug_11_u;
+
+
+/*
+ * SC_DEBUG_12 struct
+ */
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1
+#define SC_DEBUG_12_event_id_SIZE      5
+#define SC_DEBUG_12_event_flag_SIZE    1
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_full_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1
+#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1
+#define SC_DEBUG_12_iter_qdhit0_SIZE   1
+#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1
+#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1
+#define SC_DEBUG_12_iter_phase_out_SIZE 2
+#define SC_DEBUG_12_iter_phase_reg_SIZE 2
+#define SC_DEBUG_12_iterator_SP_valid_SIZE 1
+#define SC_DEBUG_12_eopv_reg_SIZE      1
+#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1
+#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1
+#define SC_DEBUG_12_trigger_SIZE       1
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0
+#define SC_DEBUG_12_event_id_SHIFT     1
+#define SC_DEBUG_12_event_flag_SHIFT   6
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7
+#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8
+#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9
+#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11
+#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12
+#define SC_DEBUG_12_iter_qdhit0_SHIFT  13
+#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14
+#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15
+#define SC_DEBUG_12_iter_phase_out_SHIFT 16
+#define SC_DEBUG_12_iter_phase_reg_SHIFT 18
+#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20
+#define SC_DEBUG_12_eopv_reg_SHIFT     21
+#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22
+#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23
+#define SC_DEBUG_12_trigger_SHIFT      31
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001
+#define SC_DEBUG_12_event_id_MASK      0x0000003e
+#define SC_DEBUG_12_event_flag_MASK    0x00000040
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080
+#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100
+#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200
+#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400
+#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800
+#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000
+#define SC_DEBUG_12_iter_qdhit0_MASK   0x00002000
+#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000
+#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000
+#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000
+#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000
+#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000
+#define SC_DEBUG_12_eopv_reg_MASK      0x00200000
+#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000
+#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000
+#define SC_DEBUG_12_trigger_MASK       0x80000000
+
+#define SC_DEBUG_12_MASK \
+     (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \
+      SC_DEBUG_12_event_id_MASK | \
+      SC_DEBUG_12_event_flag_MASK | \
+      SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \
+      SC_DEBUG_12_itercmdfifo_full_MASK | \
+      SC_DEBUG_12_itercmdfifo_empty_MASK | \
+      SC_DEBUG_12_iter_ds_one_clk_command_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_vector_MASK | \
+      SC_DEBUG_12_iter_qdhit0_MASK | \
+      SC_DEBUG_12_bc_use_centers_reg_MASK | \
+      SC_DEBUG_12_bc_output_xy_reg_MASK | \
+      SC_DEBUG_12_iter_phase_out_MASK | \
+      SC_DEBUG_12_iter_phase_reg_MASK | \
+      SC_DEBUG_12_iterator_SP_valid_MASK | \
+      SC_DEBUG_12_eopv_reg_MASK | \
+      SC_DEBUG_12_one_clk_cmd_reg_MASK | \
+      SC_DEBUG_12_iter_dx_end_of_prim_MASK | \
+      SC_DEBUG_12_trigger_MASK)
+
+#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \
+     ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \
+      (event_id << SC_DEBUG_12_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \
+      (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \
+      (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \
+      (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \
+      (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \
+      (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \
+      (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \
+      (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \
+      (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \
+      (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \
+      (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \
+      (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \
+      (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \
+      (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \
+      (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \
+      (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \
+      (trigger << SC_DEBUG_12_trigger_SHIFT))
+
+#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_GET_event_id(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_GET_trigger(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT)
+
+#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int                                : 7;
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+     } sc_debug_12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+          unsigned int                                : 7;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+     } sc_debug_12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_12_t f;
+} sc_debug_12_u;
+
+
+#endif
+
+
+#if !defined (_VGT_FIDDLE_H)
+#define _VGT_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+#define VGT_OUT_POINT                  0x00000000
+#define VGT_OUT_LINE                   0x00000001
+#define VGT_OUT_TRI                    0x00000002
+#define VGT_OUT_RECT_V0                0x00000003
+#define VGT_OUT_RECT_V1                0x00000004
+#define VGT_OUT_RECT_V2                0x00000005
+#define VGT_OUT_RECT_V3                0x00000006
+#define VGT_OUT_RESERVED               0x00000007
+#define VGT_TE_QUAD                    0x00000008
+#define VGT_TE_PRIM_INDEX_LINE         0x00000009
+#define VGT_TE_PRIM_INDEX_TRI          0x0000000a
+#define VGT_TE_PRIM_INDEX_QUAD         0x0000000b
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * GFX_COPY_STATE struct
+ */
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0
+
+#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+
+#define GFX_COPY_STATE_MASK \
+     (GFX_COPY_STATE_SRC_STATE_ID_MASK)
+
+#define GFX_COPY_STATE(src_state_id) \
+     ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT))
+
+#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \
+     ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \
+     gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 31;
+     } gfx_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int                                : 31;
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+     } gfx_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gfx_copy_state_t f;
+} gfx_copy_state_u;
+
+
+/*
+ * VGT_DRAW_INITIATOR struct
+ */
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1
+#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11
+#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800
+#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000
+#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000
+
+#define VGT_DRAW_INITIATOR_MASK \
+     (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \
+      VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \
+      VGT_DRAW_INITIATOR_NOT_EOP_MASK | \
+      VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \
+      VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_NUM_INDICES_MASK)
+
+#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \
+     ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \
+      (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \
+      (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \
+      (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \
+      (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \
+      (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \
+      (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \
+      (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \
+      (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT))
+
+#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+     } vgt_draw_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+     } vgt_draw_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_draw_initiator_t f;
+} vgt_draw_initiator_u;
+
+
+/*
+ * VGT_EVENT_INITIATOR struct
+ */
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f
+
+#define VGT_EVENT_INITIATOR_MASK \
+     (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK)
+
+#define VGT_EVENT_INITIATOR(event_type) \
+     ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT))
+
+#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \
+     ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \
+     vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+          unsigned int                                : 26;
+     } vgt_event_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int                                : 26;
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+     } vgt_event_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_event_initiator_t f;
+} vgt_event_initiator_u;
+
+
+/*
+ * VGT_DMA_BASE struct
+ */
+
+#define VGT_DMA_BASE_BASE_ADDR_SIZE    32
+
+#define VGT_DMA_BASE_BASE_ADDR_SHIFT   0
+
+#define VGT_DMA_BASE_BASE_ADDR_MASK    0xffffffff
+
+#define VGT_DMA_BASE_MASK \
+     (VGT_DMA_BASE_BASE_ADDR_MASK)
+
+#define VGT_DMA_BASE(base_addr) \
+     ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT))
+
+#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \
+     ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \
+     vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_base_t f;
+} vgt_dma_base_u;
+
+
+/*
+ * VGT_DMA_SIZE struct
+ */
+
+#define VGT_DMA_SIZE_NUM_WORDS_SIZE    24
+#define VGT_DMA_SIZE_SWAP_MODE_SIZE    2
+
+#define VGT_DMA_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_DMA_SIZE_SWAP_MODE_SHIFT   30
+
+#define VGT_DMA_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_DMA_SIZE_SWAP_MODE_MASK    0xc0000000
+
+#define VGT_DMA_SIZE_MASK \
+     (VGT_DMA_SIZE_NUM_WORDS_MASK | \
+      VGT_DMA_SIZE_SWAP_MODE_MASK)
+
+#define VGT_DMA_SIZE(num_words, swap_mode) \
+     ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \
+      (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT))
+
+#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+     } vgt_dma_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+     } vgt_dma_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_size_t f;
+} vgt_dma_size_u;
+
+
+/*
+ * VGT_BIN_BASE struct
+ */
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff
+
+#define VGT_BIN_BASE_MASK \
+     (VGT_BIN_BASE_BIN_BASE_ADDR_MASK)
+
+#define VGT_BIN_BASE(bin_base_addr) \
+     ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT))
+
+#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \
+     ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \
+     vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_base_t f;
+} vgt_bin_base_u;
+
+
+/*
+ * VGT_BIN_SIZE struct
+ */
+
+#define VGT_BIN_SIZE_NUM_WORDS_SIZE    24
+#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1
+#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1
+
+#define VGT_BIN_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30
+#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31
+
+#define VGT_BIN_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000
+#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000
+
+#define VGT_BIN_SIZE_MASK \
+     (VGT_BIN_SIZE_NUM_WORDS_MASK | \
+      VGT_BIN_SIZE_FACENESS_FETCH_MASK | \
+      VGT_BIN_SIZE_FACENESS_RESET_MASK)
+
+#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \
+     ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \
+      (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \
+      (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT))
+
+#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+     } vgt_bin_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+     } vgt_bin_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_size_t f;
+} vgt_bin_size_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MIN struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MIN_MASK \
+     (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_min_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+     } vgt_current_bin_id_min_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_min_t f;
+} vgt_current_bin_id_min_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MAX struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MAX_MASK \
+     (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_max_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+     } vgt_current_bin_id_max_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_max_t f;
+} vgt_current_bin_id_max_u;
+
+
+/*
+ * VGT_IMMED_DATA struct
+ */
+
+#define VGT_IMMED_DATA_DATA_SIZE       32
+
+#define VGT_IMMED_DATA_DATA_SHIFT      0
+
+#define VGT_IMMED_DATA_DATA_MASK       0xffffffff
+
+#define VGT_IMMED_DATA_MASK \
+     (VGT_IMMED_DATA_DATA_MASK)
+
+#define VGT_IMMED_DATA(data) \
+     ((data << VGT_IMMED_DATA_DATA_SHIFT))
+
+#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \
+     ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT)
+
+#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \
+     vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_immed_data_t f;
+} vgt_immed_data_u;
+
+
+/*
+ * VGT_MAX_VTX_INDX struct
+ */
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff
+
+#define VGT_MAX_VTX_INDX_MASK \
+     (VGT_MAX_VTX_INDX_MAX_INDX_MASK)
+
+#define VGT_MAX_VTX_INDX(max_indx) \
+     ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT))
+
+#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \
+     ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \
+     vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_max_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+     } vgt_max_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_max_vtx_indx_t f;
+} vgt_max_vtx_indx_u;
+
+
+/*
+ * VGT_MIN_VTX_INDX struct
+ */
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff
+
+#define VGT_MIN_VTX_INDX_MASK \
+     (VGT_MIN_VTX_INDX_MIN_INDX_MASK)
+
+#define VGT_MIN_VTX_INDX(min_indx) \
+     ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT))
+
+#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \
+     ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \
+     vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_min_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+     } vgt_min_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_min_vtx_indx_t f;
+} vgt_min_vtx_indx_u;
+
+
+/*
+ * VGT_INDX_OFFSET struct
+ */
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff
+
+#define VGT_INDX_OFFSET_MASK \
+     (VGT_INDX_OFFSET_INDX_OFFSET_MASK)
+
+#define VGT_INDX_OFFSET(indx_offset) \
+     ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT))
+
+#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \
+     ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \
+     vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+          unsigned int                                : 8;
+     } vgt_indx_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int                                : 8;
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+     } vgt_indx_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_indx_offset_t f;
+} vgt_indx_offset_u;
+
+
+/*
+ * VGT_VERTEX_REUSE_BLOCK_CNTL struct
+ */
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \
+     (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \
+     ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT))
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \
+     ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \
+     vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+          unsigned int                                : 29;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int                                : 29;
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vertex_reuse_block_cntl_t f;
+} vgt_vertex_reuse_block_cntl_u;
+
+
+/*
+ * VGT_OUT_DEALLOC_CNTL struct
+ */
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003
+
+#define VGT_OUT_DEALLOC_CNTL_MASK \
+     (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK)
+
+#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \
+     ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT))
+
+#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \
+     ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \
+     vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+          unsigned int                                : 30;
+     } vgt_out_dealloc_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int                                : 30;
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+     } vgt_out_dealloc_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_out_dealloc_cntl_t f;
+} vgt_out_dealloc_cntl_u;
+
+
+/*
+ * VGT_MULTI_PRIM_IB_RESET_INDX struct
+ */
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \
+     (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \
+     ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT))
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \
+     ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \
+     vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int                                : 8;
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_multi_prim_ib_reset_indx_t f;
+} vgt_multi_prim_ib_reset_indx_u;
+
+
+/*
+ * VGT_ENHANCE struct
+ */
+
+#define VGT_ENHANCE_MISC_SIZE          16
+
+#define VGT_ENHANCE_MISC_SHIFT         0
+
+#define VGT_ENHANCE_MISC_MASK          0x0000ffff
+
+#define VGT_ENHANCE_MASK \
+     (VGT_ENHANCE_MISC_MASK)
+
+#define VGT_ENHANCE(misc) \
+     ((misc << VGT_ENHANCE_MISC_SHIFT))
+
+#define VGT_ENHANCE_GET_MISC(vgt_enhance) \
+     ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT)
+
+#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \
+     vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+          unsigned int                                : 16;
+     } vgt_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int                                : 16;
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+     } vgt_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_enhance_t f;
+} vgt_enhance_u;
+
+
+/*
+ * VGT_VTX_VECT_EJECT_REG struct
+ */
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f
+
+#define VGT_VTX_VECT_EJECT_REG_MASK \
+     (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK)
+
+#define VGT_VTX_VECT_EJECT_REG(prim_count) \
+     ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT))
+
+#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \
+     ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \
+     vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+          unsigned int                                : 27;
+     } vgt_vtx_vect_eject_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int                                : 27;
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+     } vgt_vtx_vect_eject_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vtx_vect_eject_reg_t f;
+} vgt_vtx_vect_eject_reg_u;
+
+
+/*
+ * VGT_LAST_COPY_STATE struct
+ */
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000
+
+#define VGT_LAST_COPY_STATE_MASK \
+     (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \
+      VGT_LAST_COPY_STATE_DST_STATE_ID_MASK)
+
+#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \
+     ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \
+      (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT))
+
+#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+     } vgt_last_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+     } vgt_last_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_last_copy_state_t f;
+} vgt_last_copy_state_u;
+
+
+/*
+ * VGT_DEBUG_CNTL struct
+ */
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f
+
+#define VGT_DEBUG_CNTL_MASK \
+     (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK)
+
+#define VGT_DEBUG_CNTL(vgt_debug_indx) \
+     ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT))
+
+#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \
+     ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \
+     vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } vgt_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+     } vgt_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_cntl_t f;
+} vgt_debug_cntl_u;
+
+
+/*
+ * VGT_DEBUG_DATA struct
+ */
+
+#define VGT_DEBUG_DATA_DATA_SIZE       32
+
+#define VGT_DEBUG_DATA_DATA_SHIFT      0
+
+#define VGT_DEBUG_DATA_DATA_MASK       0xffffffff
+
+#define VGT_DEBUG_DATA_MASK \
+     (VGT_DEBUG_DATA_DATA_MASK)
+
+#define VGT_DEBUG_DATA(data) \
+     ((data << VGT_DEBUG_DATA_DATA_SHIFT))
+
+#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \
+     ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT)
+
+#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \
+     vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_data_t f;
+} vgt_debug_data_u;
+
+
+/*
+ * VGT_CNTL_STATUS struct
+ */
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SIZE  1
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8
+
+#define VGT_CNTL_STATUS_VGT_BUSY_MASK  0x00000001
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100
+
+#define VGT_CNTL_STATUS_MASK \
+     (VGT_CNTL_STATUS_VGT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK)
+
+#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \
+     ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \
+      (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \
+      (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \
+      (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \
+      (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \
+      (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \
+      (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \
+      (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \
+      (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT))
+
+#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int                                : 23;
+     } vgt_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int                                : 23;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+     } vgt_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_cntl_status_t f;
+} vgt_cntl_status_u;
+
+
+/*
+ * VGT_DEBUG_REG0 struct
+ */
+
+#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_out_busy_SIZE   1
+#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1
+#define VGT_DEBUG_REG0_grp_busy_SIZE   1
+#define VGT_DEBUG_REG0_dma_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_rbiu_busy_SIZE  1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1
+
+#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0
+#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2
+#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3
+#define VGT_DEBUG_REG0_out_busy_SHIFT  4
+#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5
+#define VGT_DEBUG_REG0_grp_busy_SHIFT  6
+#define VGT_DEBUG_REG0_dma_busy_SHIFT  7
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8
+#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11
+#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12
+#define VGT_DEBUG_REG0_vgt_busy_SHIFT  13
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16
+
+#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001
+#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002
+#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004
+#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008
+#define VGT_DEBUG_REG0_out_busy_MASK   0x00000010
+#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020
+#define VGT_DEBUG_REG0_grp_busy_MASK   0x00000040
+#define VGT_DEBUG_REG0_dma_busy_MASK   0x00000080
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100
+#define VGT_DEBUG_REG0_rbiu_busy_MASK  0x00000200
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800
+#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000
+#define VGT_DEBUG_REG0_vgt_busy_MASK   0x00002000
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000
+
+#define VGT_DEBUG_REG0_MASK \
+     (VGT_DEBUG_REG0_te_grp_busy_MASK | \
+      VGT_DEBUG_REG0_pt_grp_busy_MASK | \
+      VGT_DEBUG_REG0_vr_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_out_busy_MASK | \
+      VGT_DEBUG_REG0_grp_backend_busy_MASK | \
+      VGT_DEBUG_REG0_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_MASK | \
+      VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_busy_MASK)
+
+#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \
+     ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \
+      (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \
+      (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \
+      (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \
+      (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \
+      (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \
+      (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \
+      (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \
+      (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \
+      (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \
+      (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \
+      (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \
+      (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \
+      (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \
+      (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \
+      (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \
+      (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT))
+
+#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int                                : 15;
+     } vgt_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int                                : 15;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+     } vgt_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg0_t f;
+} vgt_debug_reg0_u;
+
+
+/*
+ * VGT_DEBUG_REG1 struct
+ */
+
+#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1
+#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_te_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1
+#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1
+#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1
+#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1
+
+#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0
+#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3
+#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5
+#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7
+#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9
+#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10
+#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11
+#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12
+#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13
+#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14
+#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15
+#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16
+#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20
+#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28
+#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30
+
+#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001
+#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002
+#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004
+#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008
+#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010
+#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020
+#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040
+#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080
+#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100
+#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200
+#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400
+#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800
+#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000
+#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000
+#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000
+#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000
+#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000
+#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000
+#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000
+#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000
+
+#define VGT_DEBUG_REG1_MASK \
+     (VGT_DEBUG_REG1_out_te_data_read_MASK | \
+      VGT_DEBUG_REG1_te_out_data_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_prim_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_data_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_prim_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_indx_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_te_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_te_valid_MASK | \
+      VGT_DEBUG_REG1_pt_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_pt_valid_MASK | \
+      VGT_DEBUG_REG1_vr_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_vr_valid_MASK | \
+      VGT_DEBUG_REG1_grp_dma_read_MASK | \
+      VGT_DEBUG_REG1_dma_grp_valid_MASK | \
+      VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \
+      VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \
+      VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_MH_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \
+      VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_SQ_send_MASK | \
+      VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK)
+
+#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \
+     ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \
+      (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \
+      (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \
+      (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \
+      (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \
+      (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \
+      (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \
+      (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \
+      (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \
+      (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \
+      (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \
+      (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \
+      (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \
+      (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \
+      (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \
+      (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \
+      (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \
+      (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \
+      (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \
+      (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \
+      (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \
+      (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \
+      (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \
+      (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \
+      (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \
+      (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \
+      (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \
+      (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \
+      (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \
+      (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \
+      (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT))
+
+#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int                                : 1;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+     } vgt_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg1_t f;
+} vgt_debug_reg1_u;
+
+
+/*
+ * VGT_DEBUG_REG3 struct
+ */
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002
+
+#define VGT_DEBUG_REG3_MASK \
+     (VGT_DEBUG_REG3_vgt_clk_en_MASK | \
+      VGT_DEBUG_REG3_reg_fifos_clk_en_MASK)
+
+#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \
+     ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \
+      (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT))
+
+#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int                                : 30;
+     } vgt_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int                                : 30;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+     } vgt_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg3_t f;
+} vgt_debug_reg3_u;
+
+
+/*
+ * VGT_DEBUG_REG6 struct
+ */
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG6_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_extract_vector_SIZE 1
+#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG6_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG6_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG6_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG6_MASK \
+     (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG6_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG6_input_data_valid_MASK | \
+      VGT_DEBUG_REG6_input_data_xfer_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG6_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG6_shifter_first_load_MASK | \
+      VGT_DEBUG_REG6_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG6_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG6_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG6_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG6_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG6_extract_vector_MASK | \
+      VGT_DEBUG_REG6_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG6_destination_rtr_MASK | \
+      VGT_DEBUG_REG6_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int                                : 3;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg6_t f;
+} vgt_debug_reg6_u;
+
+
+/*
+ * VGT_DEBUG_REG7 struct
+ */
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG7_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG7_MASK \
+     (VGT_DEBUG_REG7_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG7_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG7_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG7_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+     } vgt_debug_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+     } vgt_debug_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg7_t f;
+} vgt_debug_reg7_u;
+
+
+/*
+ * VGT_DEBUG_REG8 struct
+ */
+
+#define VGT_DEBUG_REG8_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG8_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG8_MASK \
+     (VGT_DEBUG_REG8_current_source_sel_MASK | \
+      VGT_DEBUG_REG8_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG8_input_data_cnt_MASK | \
+      VGT_DEBUG_REG8_input_data_lsw_MASK | \
+      VGT_DEBUG_REG8_input_data_msw_MASK | \
+      VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+     } vgt_debug_reg8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg8_t f;
+} vgt_debug_reg8_u;
+
+
+/*
+ * VGT_DEBUG_REG9 struct
+ */
+
+#define VGT_DEBUG_REG9_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG9_MASK \
+     (VGT_DEBUG_REG9_next_stride_q_MASK | \
+      VGT_DEBUG_REG9_next_stride_d_MASK | \
+      VGT_DEBUG_REG9_current_shift_q_MASK | \
+      VGT_DEBUG_REG9_current_shift_d_MASK | \
+      VGT_DEBUG_REG9_current_stride_q_MASK | \
+      VGT_DEBUG_REG9_current_stride_d_MASK | \
+      VGT_DEBUG_REG9_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int                                : 1;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+     } vgt_debug_reg9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg9_t f;
+} vgt_debug_reg9_u;
+
+
+/*
+ * VGT_DEBUG_REG10 struct
+ */
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG10_bin_valid_SIZE 1
+#define VGT_DEBUG_REG10_read_block_SIZE 1
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1
+#define VGT_DEBUG_REG10_selected_data_SIZE 8
+#define VGT_DEBUG_REG10_mask_input_data_SIZE 8
+#define VGT_DEBUG_REG10_gap_q_SIZE     1
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1
+#define VGT_DEBUG_REG10_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3
+#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4
+#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5
+#define VGT_DEBUG_REG10_bin_valid_SHIFT 6
+#define VGT_DEBUG_REG10_read_block_SHIFT 7
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8
+#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10
+#define VGT_DEBUG_REG10_selected_data_SHIFT 11
+#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19
+#define VGT_DEBUG_REG10_gap_q_SHIFT    27
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30
+#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008
+#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010
+#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020
+#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040
+#define VGT_DEBUG_REG10_read_block_MASK 0x00000080
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100
+#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200
+#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400
+#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800
+#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000
+#define VGT_DEBUG_REG10_gap_q_MASK     0x08000000
+#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000
+#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000
+#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000
+#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG10_MASK \
+     (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG10_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG10_bin_valid_MASK | \
+      VGT_DEBUG_REG10_read_block_MASK | \
+      VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \
+      VGT_DEBUG_REG10_last_bit_enable_q_MASK | \
+      VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \
+      VGT_DEBUG_REG10_selected_data_MASK | \
+      VGT_DEBUG_REG10_mask_input_data_MASK | \
+      VGT_DEBUG_REG10_gap_q_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \
+      VGT_DEBUG_REG10_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \
+     ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \
+      (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \
+      (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \
+      (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \
+      (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \
+      (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \
+      (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \
+      (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \
+      (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \
+      (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \
+      (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \
+      (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \
+      (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \
+      (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \
+      (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+     } vgt_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+     } vgt_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg10_t f;
+} vgt_debug_reg10_u;
+
+
+/*
+ * VGT_DEBUG_REG12 struct
+ */
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG12_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_extract_vector_SIZE 1
+#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG12_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG12_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG12_MASK \
+     (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG12_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG12_input_data_valid_MASK | \
+      VGT_DEBUG_REG12_input_data_xfer_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG12_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG12_shifter_first_load_MASK | \
+      VGT_DEBUG_REG12_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG12_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG12_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG12_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG12_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG12_extract_vector_MASK | \
+      VGT_DEBUG_REG12_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG12_destination_rtr_MASK | \
+      VGT_DEBUG_REG12_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int                                : 3;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg12_t f;
+} vgt_debug_reg12_u;
+
+
+/*
+ * VGT_DEBUG_REG13 struct
+ */
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG13_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG13_MASK \
+     (VGT_DEBUG_REG13_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG13_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG13_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG13_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+     } vgt_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+     } vgt_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg13_t f;
+} vgt_debug_reg13_u;
+
+
+/*
+ * VGT_DEBUG_REG14 struct
+ */
+
+#define VGT_DEBUG_REG14_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG14_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG14_MASK \
+     (VGT_DEBUG_REG14_current_source_sel_MASK | \
+      VGT_DEBUG_REG14_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG14_input_data_cnt_MASK | \
+      VGT_DEBUG_REG14_input_data_lsw_MASK | \
+      VGT_DEBUG_REG14_input_data_msw_MASK | \
+      VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+     } vgt_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg14_t f;
+} vgt_debug_reg14_u;
+
+
+/*
+ * VGT_DEBUG_REG15 struct
+ */
+
+#define VGT_DEBUG_REG15_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG15_MASK \
+     (VGT_DEBUG_REG15_next_stride_q_MASK | \
+      VGT_DEBUG_REG15_next_stride_d_MASK | \
+      VGT_DEBUG_REG15_current_shift_q_MASK | \
+      VGT_DEBUG_REG15_current_shift_d_MASK | \
+      VGT_DEBUG_REG15_current_stride_q_MASK | \
+      VGT_DEBUG_REG15_current_stride_d_MASK | \
+      VGT_DEBUG_REG15_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int                                : 1;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+     } vgt_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg15_t f;
+} vgt_debug_reg15_u;
+
+
+/*
+ * VGT_DEBUG_REG16 struct
+ */
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1
+#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1
+#define VGT_DEBUG_REG16_current_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_en_SIZE 1
+#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1
+#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9
+#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10
+#define VGT_DEBUG_REG16_current_state_q_SHIFT 11
+#define VGT_DEBUG_REG16_old_state_q_SHIFT 12
+#define VGT_DEBUG_REG16_old_state_en_SHIFT 13
+#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15
+#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17
+#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30
+#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200
+#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400
+#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800
+#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000
+#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000
+#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000
+#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000
+#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000
+#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000
+#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000
+#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG16_MASK \
+     (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \
+      VGT_DEBUG_REG16_rst_last_bit_MASK | \
+      VGT_DEBUG_REG16_current_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_en_MASK | \
+      VGT_DEBUG_REG16_prev_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_last_bit_block_q_MASK | \
+      VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \
+      VGT_DEBUG_REG16_load_empty_reg_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \
+      VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \
+     ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \
+      (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \
+      (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \
+      (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \
+      (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \
+      (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \
+      (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \
+      (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \
+      (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \
+      (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \
+      (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \
+      (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \
+      (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \
+      (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \
+      (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \
+      (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \
+      (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \
+      (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \
+      (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \
+      (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \
+      (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+     } vgt_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+     } vgt_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg16_t f;
+} vgt_debug_reg16_u;
+
+
+/*
+ * VGT_DEBUG_REG17 struct
+ */
+
+#define VGT_DEBUG_REG17_save_read_q_SIZE 1
+#define VGT_DEBUG_REG17_extend_read_q_SIZE 1
+#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2
+#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1
+#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1
+#define VGT_DEBUG_REG17_check_second_reg_SIZE 1
+#define VGT_DEBUG_REG17_check_first_reg_SIZE 1
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1
+#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG17_save_read_q_SHIFT 0
+#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1
+#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2
+#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4
+#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5
+#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6
+#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7
+#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8
+#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14
+#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15
+#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24
+#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001
+#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002
+#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c
+#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010
+#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020
+#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040
+#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080
+#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100
+#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000
+#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000
+#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000
+#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000
+#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000
+#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG17_MASK \
+     (VGT_DEBUG_REG17_save_read_q_MASK | \
+      VGT_DEBUG_REG17_extend_read_q_MASK | \
+      VGT_DEBUG_REG17_grp_indx_size_MASK | \
+      VGT_DEBUG_REG17_cull_prim_true_MASK | \
+      VGT_DEBUG_REG17_reset_bit2_q_MASK | \
+      VGT_DEBUG_REG17_reset_bit1_q_MASK | \
+      VGT_DEBUG_REG17_first_reg_first_q_MASK | \
+      VGT_DEBUG_REG17_check_second_reg_MASK | \
+      VGT_DEBUG_REG17_check_first_reg_MASK | \
+      VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \
+      VGT_DEBUG_REG17_to_second_reg_q_MASK | \
+      VGT_DEBUG_REG17_roll_over_msk_q_MASK | \
+      VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \
+     ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \
+      (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \
+      (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \
+      (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \
+      (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \
+      (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \
+      (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \
+      (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \
+      (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \
+      (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \
+      (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \
+      (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \
+      (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \
+      (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \
+      (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \
+      (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \
+      (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \
+      (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+     } vgt_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+     } vgt_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg17_t f;
+} vgt_debug_reg17_u;
+
+
+/*
+ * VGT_DEBUG_REG18 struct
+ */
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_start_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1
+#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13
+#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15
+#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16
+#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17
+#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20
+#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21
+#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22
+#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23
+#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24
+#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26
+#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27
+#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28
+#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000
+#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000
+#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000
+#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000
+#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000
+#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000
+#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000
+#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000
+#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000
+#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000
+#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000
+#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000
+#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000
+#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000
+
+#define VGT_DEBUG_REG18_MASK \
+     (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG18_dma_mem_full_MASK | \
+      VGT_DEBUG_REG18_dma_ram_re_MASK | \
+      VGT_DEBUG_REG18_dma_ram_we_MASK | \
+      VGT_DEBUG_REG18_dma_mem_empty_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \
+      VGT_DEBUG_REG18_bin_mem_full_MASK | \
+      VGT_DEBUG_REG18_bin_ram_we_MASK | \
+      VGT_DEBUG_REG18_bin_ram_re_MASK | \
+      VGT_DEBUG_REG18_bin_mem_empty_MASK | \
+      VGT_DEBUG_REG18_start_bin_req_MASK | \
+      VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \
+      VGT_DEBUG_REG18_dma_req_xfer_MASK | \
+      VGT_DEBUG_REG18_have_valid_bin_req_MASK | \
+      VGT_DEBUG_REG18_have_valid_dma_req_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK)
+
+#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \
+     ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \
+      (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \
+      (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \
+      (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \
+      (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \
+      (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \
+      (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \
+      (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \
+      (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \
+      (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \
+      (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \
+      (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \
+      (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \
+      (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \
+      (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \
+      (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \
+      (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \
+      (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \
+      (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT))
+
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+     } vgt_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+     } vgt_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg18_t f;
+} vgt_debug_reg18_u;
+
+
+/*
+ * VGT_DEBUG_REG20 struct
+ */
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_sent_cnt_SIZE  4
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5
+#define VGT_DEBUG_REG20_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5
+#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6
+#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7
+#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8
+#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9
+#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10
+#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11
+#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12
+#define VGT_DEBUG_REG20_hold_prim_SHIFT 13
+#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21
+#define VGT_DEBUG_REG20_out_trigger_SHIFT 26
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004
+#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020
+#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040
+#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080
+#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100
+#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200
+#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400
+#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800
+#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000
+#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000
+#define VGT_DEBUG_REG20_sent_cnt_MASK  0x0003c000
+#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000
+#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000
+#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000
+
+#define VGT_DEBUG_REG20_MASK \
+     (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_re_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_we_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_full_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_re_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_we_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_full_MASK | \
+      VGT_DEBUG_REG20_hold_prim_MASK | \
+      VGT_DEBUG_REG20_sent_cnt_MASK | \
+      VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \
+      VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \
+      VGT_DEBUG_REG20_out_trigger_MASK)
+
+#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \
+     ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \
+      (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \
+      (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \
+      (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \
+      (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \
+      (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \
+      (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \
+      (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \
+      (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \
+      (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \
+      (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \
+      (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \
+      (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \
+      (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \
+      (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \
+      (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \
+      (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \
+      (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \
+      (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int                                : 5;
+     } vgt_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int                                : 5;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+     } vgt_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg20_t f;
+} vgt_debug_reg20_u;
+
+
+/*
+ * VGT_DEBUG_REG21 struct
+ */
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3
+#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4
+#define VGT_DEBUG_REG21_new_packet_q_SIZE 1
+#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1
+#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1
+#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1
+#define VGT_DEBUG_REG21_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1
+#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14
+#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18
+#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22
+#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25
+#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26
+#define VGT_DEBUG_REG21_out_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e
+#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380
+#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000
+#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000
+#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000
+#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000
+#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000
+#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000
+#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG21_MASK \
+     (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \
+      VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \
+      VGT_DEBUG_REG21_alloc_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \
+      VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \
+      VGT_DEBUG_REG21_new_packet_q_MASK | \
+      VGT_DEBUG_REG21_new_allocate_q_MASK | \
+      VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \
+      VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \
+      VGT_DEBUG_REG21_insert_null_prim_MASK | \
+      VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \
+      VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \
+      VGT_DEBUG_REG21_buffered_thread_size_MASK | \
+      VGT_DEBUG_REG21_out_trigger_MASK)
+
+#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \
+     ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \
+      (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \
+      (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \
+      (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \
+      (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \
+      (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \
+      (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \
+      (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \
+      (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \
+      (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \
+      (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \
+      (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \
+      (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \
+      (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int                                : 4;
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+     } vgt_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+          unsigned int                                : 4;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+     } vgt_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg21_t f;
+} vgt_debug_reg21_u;
+
+
+/*
+ * VGT_CRC_SQ_DATA struct
+ */
+
+#define VGT_CRC_SQ_DATA_CRC_SIZE       32
+
+#define VGT_CRC_SQ_DATA_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_DATA_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_DATA_MASK \
+     (VGT_CRC_SQ_DATA_CRC_MASK)
+
+#define VGT_CRC_SQ_DATA(crc) \
+     ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT))
+
+#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \
+     ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \
+     vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_data_t f;
+} vgt_crc_sq_data_u;
+
+
+/*
+ * VGT_CRC_SQ_CTRL struct
+ */
+
+#define VGT_CRC_SQ_CTRL_CRC_SIZE       32
+
+#define VGT_CRC_SQ_CTRL_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_CTRL_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_CTRL_MASK \
+     (VGT_CRC_SQ_CTRL_CRC_MASK)
+
+#define VGT_CRC_SQ_CTRL(crc) \
+     ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT))
+
+#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \
+     ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \
+     vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_ctrl_t f;
+} vgt_crc_sq_ctrl_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER0_SELECT_MASK \
+     (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \
+     ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \
+     vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_select_t f;
+} vgt_perfcounter0_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER1_SELECT_MASK \
+     (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \
+     ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \
+     vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_select_t f;
+} vgt_perfcounter1_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER2_SELECT_MASK \
+     (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \
+     ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \
+     vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_select_t f;
+} vgt_perfcounter2_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER3_SELECT_MASK \
+     (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \
+     ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \
+     vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_select_t f;
+} vgt_perfcounter3_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_LOW struct
+ */
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER0_LOW_MASK \
+     (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \
+     ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \
+     vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_low_t f;
+} vgt_perfcounter0_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_LOW struct
+ */
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER1_LOW_MASK \
+     (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \
+     ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \
+     vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_low_t f;
+} vgt_perfcounter1_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_LOW struct
+ */
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER2_LOW_MASK \
+     (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \
+     ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \
+     vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_low_t f;
+} vgt_perfcounter2_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_LOW struct
+ */
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER3_LOW_MASK \
+     (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \
+     ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \
+     vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_low_t f;
+} vgt_perfcounter3_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_HI struct
+ */
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER0_HI_MASK \
+     (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \
+     ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \
+     vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_hi_t f;
+} vgt_perfcounter0_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_HI struct
+ */
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER1_HI_MASK \
+     (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \
+     ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \
+     vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_hi_t f;
+} vgt_perfcounter1_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_HI struct
+ */
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER2_HI_MASK \
+     (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \
+     ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \
+     vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_hi_t f;
+} vgt_perfcounter2_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_HI struct
+ */
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER3_HI_MASK \
+     (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \
+     ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \
+     vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_hi_t f;
+} vgt_perfcounter3_hi_u;
+
+
+#endif
+
+
+#if !defined (_SQ_FIDDLE_H)
+#define _SQ_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * SQ_GPR_MANAGEMENT struct
+ */
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000
+
+#define SQ_GPR_MANAGEMENT_MASK \
+     (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK)
+
+#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \
+     ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \
+      (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \
+      (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT))
+
+#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 13;
+     } sq_gpr_management_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int                                : 13;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+     } sq_gpr_management_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_gpr_management_t f;
+} sq_gpr_management_u;
+
+
+/*
+ * SQ_FLOW_CONTROL struct
+ */
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1
+#define SQ_FLOW_CONTROL_ONE_ALU_SIZE   1
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4
+#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE  1
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0
+#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4
+#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT  8
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12
+#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003
+#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010
+#define SQ_FLOW_CONTROL_ONE_ALU_MASK   0x00000100
+#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000
+#define SQ_FLOW_CONTROL_NO_PV_PS_MASK  0x00010000
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000
+
+#define SQ_FLOW_CONTROL_MASK \
+     (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ONE_THREAD_MASK | \
+      SQ_FLOW_CONTROL_ONE_ALU_MASK | \
+      SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \
+      SQ_FLOW_CONTROL_NO_PV_PS_MASK | \
+      SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \
+      SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \
+      SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \
+      SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \
+      SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \
+      SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \
+      SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK)
+
+#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \
+     ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \
+      (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \
+      (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \
+      (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \
+      (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \
+      (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \
+      (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \
+      (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \
+      (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \
+      (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \
+      (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \
+      (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \
+      (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \
+      (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \
+      (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT))
+
+#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+          unsigned int                                : 2;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int                                : 4;
+     } sq_flow_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int                                : 4;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 2;
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+     } sq_flow_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_flow_control_t f;
+} sq_flow_control_u;
+
+
+/*
+ * SQ_INST_STORE_MANAGMENT struct
+ */
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000
+
+#define SQ_INST_STORE_MANAGMENT_MASK \
+     (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \
+      SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK)
+
+#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \
+     ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \
+      (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT))
+
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+     } sq_inst_store_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+     } sq_inst_store_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_inst_store_managment_t f;
+} sq_inst_store_managment_u;
+
+
+/*
+ * SQ_RESOURCE_MANAGMENT struct
+ */
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000
+
+#define SQ_RESOURCE_MANAGMENT_MASK \
+     (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK)
+
+#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \
+     ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT))
+
+#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int                                : 7;
+     } sq_resource_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int                                : 7;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+     } sq_resource_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_resource_managment_t f;
+} sq_resource_managment_u;
+
+
+/*
+ * SQ_EO_RT struct
+ */
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE  8
+#define SQ_EO_RT_EO_TSTATE_RT_SIZE     8
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0
+#define SQ_EO_RT_EO_TSTATE_RT_SHIFT    16
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_MASK  0x000000ff
+#define SQ_EO_RT_EO_TSTATE_RT_MASK     0x00ff0000
+
+#define SQ_EO_RT_MASK \
+     (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \
+      SQ_EO_RT_EO_TSTATE_RT_MASK)
+
+#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \
+     ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \
+      (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT))
+
+#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+     } sq_eo_rt_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+     } sq_eo_rt_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_eo_rt_t f;
+} sq_eo_rt_u;
+
+
+/*
+ * SQ_DEBUG_MISC struct
+ */
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8
+#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1
+#define SQ_DEBUG_MISC_RESERVED_SIZE    2
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12
+#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20
+#define SQ_DEBUG_MISC_RESERVED_SHIFT   21
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000
+#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000
+#define SQ_DEBUG_MISC_RESERVED_MASK    0x00600000
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000
+
+#define SQ_DEBUG_MISC_MASK \
+     (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_READ_CTX_MASK | \
+      SQ_DEBUG_MISC_RESERVED_MASK | \
+      SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK)
+
+#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \
+     ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \
+      (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \
+      (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \
+      (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \
+      (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \
+      (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \
+      (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \
+      (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \
+      (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT))
+
+#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int                                : 3;
+     } sq_debug_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int                                : 3;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+     } sq_debug_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_t f;
+} sq_debug_misc_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_CNTL struct
+ */
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000
+#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000
+
+#define SQ_ACTIVITY_METER_CNTL_MASK \
+     (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \
+      SQ_ACTIVITY_METER_CNTL_SPARE_MASK)
+
+#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \
+     ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \
+      (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \
+      (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \
+      (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT))
+
+#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_cntl_t f;
+} sq_activity_meter_cntl_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_STATUS struct
+ */
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff
+
+#define SQ_ACTIVITY_METER_STATUS_MASK \
+     (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK)
+
+#define SQ_ACTIVITY_METER_STATUS(percent_busy) \
+     ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT))
+
+#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \
+     ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \
+     sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+          unsigned int                                : 24;
+     } sq_activity_meter_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int                                : 24;
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+     } sq_activity_meter_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_status_t f;
+} sq_activity_meter_status_u;
+
+
+/*
+ * SQ_INPUT_ARB_PRIORITY struct
+ */
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+
+#define SQ_INPUT_ARB_PRIORITY_MASK \
+     (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK)
+
+#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \
+     ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT))
+
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int                                : 14;
+     } sq_input_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int                                : 14;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_input_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_input_arb_priority_t f;
+} sq_input_arb_priority_u;
+
+
+/*
+ * SQ_THREAD_ARB_PRIORITY struct
+ */
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000
+
+#define SQ_THREAD_ARB_PRIORITY_MASK \
+     (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \
+      SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \
+      SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK)
+
+#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \
+     ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \
+      (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \
+      (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \
+      (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \
+      (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT))
+
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int                                : 9;
+     } sq_thread_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int                                : 9;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_thread_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_thread_arb_priority_t f;
+} sq_thread_arb_priority_u;
+
+
+/*
+ * SQ_VS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_VS_WATCHDOG_TIMER_MASK \
+     (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_watchdog_timer_t f;
+} sq_vs_watchdog_timer_u;
+
+
+/*
+ * SQ_PS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_PS_WATCHDOG_TIMER_MASK \
+     (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_watchdog_timer_t f;
+} sq_ps_watchdog_timer_u;
+
+
+/*
+ * SQ_INT_CNTL struct
+ */
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002
+
+#define SQ_INT_CNTL_MASK \
+     (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \
+      SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK)
+
+#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \
+     ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \
+      (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT))
+
+#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+     } sq_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_cntl_t f;
+} sq_int_cntl_u;
+
+
+/*
+ * SQ_INT_STATUS struct
+ */
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002
+
+#define SQ_INT_STATUS_MASK \
+     (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \
+      SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK)
+
+#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \
+     ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \
+      (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT))
+
+#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int                                : 30;
+     } sq_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+     } sq_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_status_t f;
+} sq_int_status_u;
+
+
+/*
+ * SQ_INT_ACK struct
+ */
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002
+
+#define SQ_INT_ACK_MASK \
+     (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \
+      SQ_INT_ACK_VS_WATCHDOG_ACK_MASK)
+
+#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \
+     ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \
+      (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT))
+
+#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+     } sq_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_ack_t f;
+} sq_int_ack_u;
+
+
+/*
+ * SQ_DEBUG_INPUT_FSM struct
+ */
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE  3
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007
+#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK  0x00007000
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000
+
+#define SQ_DEBUG_INPUT_FSM_MASK \
+     (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \
+      SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK)
+
+#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \
+     ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \
+      (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \
+      (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \
+      (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \
+      (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \
+      (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \
+      (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \
+      (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT))
+
+#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_input_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int                                : 4;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+     } sq_debug_input_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_input_fsm_t f;
+} sq_debug_input_fsm_u;
+
+
+/*
+ * SQ_DEBUG_CONST_MGR_FSM struct
+ */
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000
+
+#define SQ_DEBUG_CONST_MGR_FSM_MASK \
+     (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK)
+
+#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \
+     ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \
+      (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \
+      (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \
+      (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \
+      (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \
+      (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \
+      (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \
+      (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \
+      (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \
+      (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT))
+
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int                                : 8;
+     } sq_debug_const_mgr_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int                                : 8;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+     } sq_debug_const_mgr_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_const_mgr_fsm_t f;
+} sq_debug_const_mgr_fsm_u;
+
+
+/*
+ * SQ_DEBUG_TP_FSM struct
+ */
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1
+#define SQ_DEBUG_TP_FSM_CF_TP_SIZE     4
+#define SQ_DEBUG_TP_FSM_IF_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2
+#define SQ_DEBUG_TP_FSM_GS_TP_SIZE     2
+#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT    0
+#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3
+#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT    4
+#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT    8
+#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT   12
+#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14
+#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT    16
+#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18
+#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT   20
+#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22
+#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT   24
+#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28
+
+#define SQ_DEBUG_TP_FSM_EX_TP_MASK     0x00000007
+#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_TP_FSM_CF_TP_MASK     0x000000f0
+#define SQ_DEBUG_TP_FSM_IF_TP_MASK     0x00000700
+#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_TP_FSM_TIS_TP_MASK    0x00003000
+#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000
+#define SQ_DEBUG_TP_FSM_GS_TP_MASK     0x00030000
+#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000
+#define SQ_DEBUG_TP_FSM_FCR_TP_MASK    0x00300000
+#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000
+#define SQ_DEBUG_TP_FSM_FCS_TP_MASK    0x03000000
+#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000
+
+#define SQ_DEBUG_TP_FSM_MASK \
+     (SQ_DEBUG_TP_FSM_EX_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED0_MASK | \
+      SQ_DEBUG_TP_FSM_CF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_IF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_TP_FSM_TIS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_TP_FSM_GS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED3_MASK | \
+      SQ_DEBUG_TP_FSM_FCR_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED4_MASK | \
+      SQ_DEBUG_TP_FSM_FCS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED5_MASK | \
+      SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK)
+
+#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \
+     ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \
+      (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \
+      (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \
+      (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \
+      (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \
+      (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \
+      (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \
+      (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \
+      (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \
+      (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \
+      (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \
+      (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \
+      (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \
+      (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT))
+
+#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_tp_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+     } sq_debug_tp_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tp_fsm_t f;
+} sq_debug_tp_fsm_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_0 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_0_MASK \
+     (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_0_t f;
+} sq_debug_fsm_alu_0_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_1 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_1_MASK \
+     (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_1_t f;
+} sq_debug_fsm_alu_1_u;
+
+
+/*
+ * SQ_DEBUG_EXP_ALLOC struct
+ */
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000
+
+#define SQ_DEBUG_EXP_ALLOC_MASK \
+     (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \
+      SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK)
+
+#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \
+     ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \
+      (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \
+      (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \
+      (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \
+      (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT))
+
+#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_exp_alloc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int                                : 10;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+     } sq_debug_exp_alloc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_exp_alloc_t f;
+} sq_debug_exp_alloc_u;
+
+
+/*
+ * SQ_DEBUG_PTR_BUFF struct
+ */
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000
+
+#define SQ_DEBUG_PTR_BUFF_MASK \
+     (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \
+      SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \
+      SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \
+      SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \
+      SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \
+      SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK)
+
+#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \
+     ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \
+      (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \
+      (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \
+      (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \
+      (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \
+      (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \
+      (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \
+      (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \
+      (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT))
+
+#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_ptr_buff_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int                                : 4;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+     } sq_debug_ptr_buff_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_ptr_buff_t f;
+} sq_debug_ptr_buff_u;
+
+
+/*
+ * SQ_DEBUG_GPR_VTX struct
+ */
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_VTX_MASK \
+     (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \
+     ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \
+      (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \
+      (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \
+      (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_vtx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int                                : 1;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_vtx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_vtx_t f;
+} sq_debug_gpr_vtx_u;
+
+
+/*
+ * SQ_DEBUG_GPR_PIX struct
+ */
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_PIX_MASK \
+     (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \
+     ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \
+      (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \
+      (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \
+      (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_pix_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int                                : 1;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_pix_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_pix_t f;
+} sq_debug_gpr_pix_u;
+
+
+/*
+ * SQ_DEBUG_TB_STATUS_SEL struct
+ */
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000
+
+#define SQ_DEBUG_TB_STATUS_SEL_MASK \
+     (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK)
+
+#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \
+     ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \
+      (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \
+      (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \
+      (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \
+      (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT))
+
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tb_status_sel_t f;
+} sq_debug_tb_status_sel_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_0 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE  1
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK  0x00200000
+
+#define SQ_DEBUG_VTX_TB_0_MASK \
+     (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \
+      SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK)
+
+#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \
+     ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \
+      (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \
+      (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \
+      (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \
+      (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \
+      (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \
+      (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_vtx_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int                                : 10;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+     } sq_debug_vtx_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_0_t f;
+} sq_debug_vtx_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_1 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff
+
+#define SQ_DEBUG_VTX_TB_1_MASK \
+     (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK)
+
+#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \
+     ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \
+     ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \
+     sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+          unsigned int                                : 16;
+     } sq_debug_vtx_tb_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int                                : 16;
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+     } sq_debug_vtx_tb_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_1_t f;
+} sq_debug_vtx_tb_1_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATUS_REG struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \
+     (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \
+     ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \
+     ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \
+     sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_status_reg_t f;
+} sq_debug_vtx_tb_status_reg_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \
+     ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \
+     ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \
+     sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_state_mem_t f;
+} sq_debug_vtx_tb_state_mem_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE    1
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25
+#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT   31
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000
+#define SQ_DEBUG_PIX_TB_0_BUSY_MASK    0x80000000
+
+#define SQ_DEBUG_PIX_TB_0_MASK \
+     (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_BUSY_MASK)
+
+#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \
+     ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \
+      (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \
+      (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \
+      (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \
+      (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \
+      (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_0_t f;
+} sq_debug_pix_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \
+     ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \
+     ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \
+     sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_0_t f;
+} sq_debug_pix_tb_status_reg_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \
+     ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \
+     ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \
+     sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_1_t f;
+} sq_debug_pix_tb_status_reg_1_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \
+     ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \
+     ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \
+     sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_2_t f;
+} sq_debug_pix_tb_status_reg_2_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \
+     ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \
+     ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \
+     sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_3_t f;
+} sq_debug_pix_tb_status_reg_3_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \
+     ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \
+     ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \
+     sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_state_mem_t f;
+} sq_debug_pix_tb_state_mem_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER0_SELECT_MASK \
+     (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \
+     ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \
+     sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_select_t f;
+} sq_perfcounter0_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER1_SELECT_MASK \
+     (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \
+     ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \
+     sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_select_t f;
+} sq_perfcounter1_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER2_SELECT_MASK \
+     (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \
+     ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \
+     sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_select_t f;
+} sq_perfcounter2_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER3_SELECT_MASK \
+     (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \
+     ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \
+     sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_select_t f;
+} sq_perfcounter3_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_LOW struct
+ */
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER0_LOW_MASK \
+     (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \
+     ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \
+     sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_low_t f;
+} sq_perfcounter0_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_HI struct
+ */
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER0_HI_MASK \
+     (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \
+     ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \
+     sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_hi_t f;
+} sq_perfcounter0_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_LOW struct
+ */
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER1_LOW_MASK \
+     (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \
+     ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \
+     sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_low_t f;
+} sq_perfcounter1_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_HI struct
+ */
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER1_HI_MASK \
+     (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \
+     ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \
+     sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_hi_t f;
+} sq_perfcounter1_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_LOW struct
+ */
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER2_LOW_MASK \
+     (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \
+     ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \
+     sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_low_t f;
+} sq_perfcounter2_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_HI struct
+ */
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER2_HI_MASK \
+     (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \
+     ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \
+     sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_hi_t f;
+} sq_perfcounter2_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_LOW struct
+ */
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER3_LOW_MASK \
+     (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \
+     ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \
+     sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_low_t f;
+} sq_perfcounter3_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_HI struct
+ */
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER3_HI_MASK \
+     (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \
+     ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \
+     sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_hi_t f;
+} sq_perfcounter3_hi_u;
+
+
+/*
+ * SX_PERFCOUNTER0_SELECT struct
+ */
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SX_PERFCOUNTER0_SELECT_MASK \
+     (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SX_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \
+     ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \
+     sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sx_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sx_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_select_t f;
+} sx_perfcounter0_select_u;
+
+
+/*
+ * SX_PERFCOUNTER0_LOW struct
+ */
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SX_PERFCOUNTER0_LOW_MASK \
+     (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \
+     ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \
+     sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_low_t f;
+} sx_perfcounter0_low_u;
+
+
+/*
+ * SX_PERFCOUNTER0_HI struct
+ */
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SX_PERFCOUNTER0_HI_MASK \
+     (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \
+     ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \
+     sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sx_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sx_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_hi_t f;
+} sx_perfcounter0_hi_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_0 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_ALU_0_MASK \
+     (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \
+     ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \
+      (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \
+      (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \
+      (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \
+      (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \
+      (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \
+      (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \
+      (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \
+      (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \
+      (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \
+      (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+     } sq_instruction_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+     } sq_instruction_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_0_t f;
+} sq_instruction_alu_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_1 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_1_MASK \
+     (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \
+      SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK)
+
+#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \
+     ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \
+      (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \
+      (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \
+      (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \
+      (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \
+      (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \
+      (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \
+      (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \
+      (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \
+      (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \
+      (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \
+      (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \
+      (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \
+      (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \
+      (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \
+      (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \
+      (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \
+      (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+     } sq_instruction_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+     } sq_instruction_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_1_t f;
+} sq_instruction_alu_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_2 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_2_MASK \
+     (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK)
+
+#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \
+     ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \
+      (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \
+      (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \
+      (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \
+      (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \
+      (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \
+      (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \
+      (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \
+      (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \
+      (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \
+      (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \
+      (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \
+      (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+     } sq_instruction_alu_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+     } sq_instruction_alu_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_2_t f;
+} sq_instruction_alu_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_0_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \
+     ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \
+      (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_0_t f;
+} sq_instruction_cf_exec_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_1_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \
+     ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_1_t f;
+} sq_instruction_cf_exec_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_EXEC_2_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \
+     ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \
+      (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_2_t f;
+} sq_instruction_cf_exec_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000
+
+#define SQ_INSTRUCTION_CF_LOOP_0_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \
+      (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_0_t f;
+} sq_instruction_cf_loop_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_CF_LOOP_1_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_1_t f;
+} sq_instruction_cf_loop_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_LOOP_2_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \
+     ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_2_t f;
+} sq_instruction_cf_loop_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \
+      (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_0_t f;
+} sq_instruction_cf_jmp_call_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \
+      (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_1_t f;
+} sq_instruction_cf_jmp_call_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_2_t f;
+} sq_instruction_cf_jmp_call_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \
+     ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_0_t f;
+} sq_instruction_cf_alloc_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \
+      (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_1_t f;
+} sq_instruction_cf_alloc_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_2_t f;
+} sq_instruction_cf_alloc_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_TFETCH_0_MASK \
+     (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \
+     ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \
+      (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \
+      (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \
+      (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \
+      (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \
+      (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_0_t f;
+} sq_instruction_tfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_1_MASK \
+     (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \
+      (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \
+      (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \
+      (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \
+      (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \
+      (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \
+      (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \
+      (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \
+      (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \
+      (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_1_t f;
+} sq_instruction_tfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_2_MASK \
+     (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \
+     ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \
+      (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \
+      (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \
+      (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \
+      (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \
+      (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \
+      (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_2_t f;
+} sq_instruction_tfetch_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_VFETCH_0_MASK \
+     (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \
+     ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \
+      (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \
+      (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \
+      (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_0_t f;
+} sq_instruction_vfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_1_MASK \
+     (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \
+      (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \
+      (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \
+      (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \
+      (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \
+      (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_1_t f;
+} sq_instruction_vfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_2_MASK \
+     (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \
+     ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \
+      (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+          unsigned int                                : 8;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 7;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int                                : 7;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 8;
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_2_t f;
+} sq_instruction_vfetch_2_u;
+
+
+/*
+ * SQ_CONSTANT_0 struct
+ */
+
+#define SQ_CONSTANT_0_RED_SIZE         32
+
+#define SQ_CONSTANT_0_RED_SHIFT        0
+
+#define SQ_CONSTANT_0_RED_MASK         0xffffffff
+
+#define SQ_CONSTANT_0_MASK \
+     (SQ_CONSTANT_0_RED_MASK)
+
+#define SQ_CONSTANT_0(red) \
+     ((red << SQ_CONSTANT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \
+     ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \
+     sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_0_t f;
+} sq_constant_0_u;
+
+
+/*
+ * SQ_CONSTANT_1 struct
+ */
+
+#define SQ_CONSTANT_1_GREEN_SIZE       32
+
+#define SQ_CONSTANT_1_GREEN_SHIFT      0
+
+#define SQ_CONSTANT_1_GREEN_MASK       0xffffffff
+
+#define SQ_CONSTANT_1_MASK \
+     (SQ_CONSTANT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_1(green) \
+     ((green << SQ_CONSTANT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \
+     ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \
+     sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_1_t f;
+} sq_constant_1_u;
+
+
+/*
+ * SQ_CONSTANT_2 struct
+ */
+
+#define SQ_CONSTANT_2_BLUE_SIZE        32
+
+#define SQ_CONSTANT_2_BLUE_SHIFT       0
+
+#define SQ_CONSTANT_2_BLUE_MASK        0xffffffff
+
+#define SQ_CONSTANT_2_MASK \
+     (SQ_CONSTANT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_2(blue) \
+     ((blue << SQ_CONSTANT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \
+     ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \
+     sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_2_t f;
+} sq_constant_2_u;
+
+
+/*
+ * SQ_CONSTANT_3 struct
+ */
+
+#define SQ_CONSTANT_3_ALPHA_SIZE       32
+
+#define SQ_CONSTANT_3_ALPHA_SHIFT      0
+
+#define SQ_CONSTANT_3_ALPHA_MASK       0xffffffff
+
+#define SQ_CONSTANT_3_MASK \
+     (SQ_CONSTANT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_3(alpha) \
+     ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \
+     ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \
+     sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_3_t f;
+} sq_constant_3_u;
+
+
+/*
+ * SQ_FETCH_0 struct
+ */
+
+#define SQ_FETCH_0_VALUE_SIZE          32
+
+#define SQ_FETCH_0_VALUE_SHIFT         0
+
+#define SQ_FETCH_0_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_0_MASK \
+     (SQ_FETCH_0_VALUE_MASK)
+
+#define SQ_FETCH_0(value) \
+     ((value << SQ_FETCH_0_VALUE_SHIFT))
+
+#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \
+     ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT)
+
+#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \
+     sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_0_t f;
+} sq_fetch_0_u;
+
+
+/*
+ * SQ_FETCH_1 struct
+ */
+
+#define SQ_FETCH_1_VALUE_SIZE          32
+
+#define SQ_FETCH_1_VALUE_SHIFT         0
+
+#define SQ_FETCH_1_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_1_MASK \
+     (SQ_FETCH_1_VALUE_MASK)
+
+#define SQ_FETCH_1(value) \
+     ((value << SQ_FETCH_1_VALUE_SHIFT))
+
+#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \
+     ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT)
+
+#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \
+     sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_1_t f;
+} sq_fetch_1_u;
+
+
+/*
+ * SQ_FETCH_2 struct
+ */
+
+#define SQ_FETCH_2_VALUE_SIZE          32
+
+#define SQ_FETCH_2_VALUE_SHIFT         0
+
+#define SQ_FETCH_2_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_2_MASK \
+     (SQ_FETCH_2_VALUE_MASK)
+
+#define SQ_FETCH_2(value) \
+     ((value << SQ_FETCH_2_VALUE_SHIFT))
+
+#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \
+     ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT)
+
+#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \
+     sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_2_t f;
+} sq_fetch_2_u;
+
+
+/*
+ * SQ_FETCH_3 struct
+ */
+
+#define SQ_FETCH_3_VALUE_SIZE          32
+
+#define SQ_FETCH_3_VALUE_SHIFT         0
+
+#define SQ_FETCH_3_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_3_MASK \
+     (SQ_FETCH_3_VALUE_MASK)
+
+#define SQ_FETCH_3(value) \
+     ((value << SQ_FETCH_3_VALUE_SHIFT))
+
+#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \
+     ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT)
+
+#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \
+     sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_3_t f;
+} sq_fetch_3_u;
+
+
+/*
+ * SQ_FETCH_4 struct
+ */
+
+#define SQ_FETCH_4_VALUE_SIZE          32
+
+#define SQ_FETCH_4_VALUE_SHIFT         0
+
+#define SQ_FETCH_4_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_4_MASK \
+     (SQ_FETCH_4_VALUE_MASK)
+
+#define SQ_FETCH_4(value) \
+     ((value << SQ_FETCH_4_VALUE_SHIFT))
+
+#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \
+     ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT)
+
+#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \
+     sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_4_t f;
+} sq_fetch_4_u;
+
+
+/*
+ * SQ_FETCH_5 struct
+ */
+
+#define SQ_FETCH_5_VALUE_SIZE          32
+
+#define SQ_FETCH_5_VALUE_SHIFT         0
+
+#define SQ_FETCH_5_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_5_MASK \
+     (SQ_FETCH_5_VALUE_MASK)
+
+#define SQ_FETCH_5(value) \
+     ((value << SQ_FETCH_5_VALUE_SHIFT))
+
+#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \
+     ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT)
+
+#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \
+     sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_5_t f;
+} sq_fetch_5_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_0 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0
+#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001
+#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_0_MASK \
+     (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \
+      SQ_CONSTANT_VFETCH_0_STATE_MASK | \
+      SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \
+     ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \
+      (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \
+      (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_0_t f;
+} sq_constant_vfetch_0_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_1 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_1_MASK \
+     (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \
+      SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \
+     ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \
+      (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_1_t f;
+} sq_constant_vfetch_1_u;
+
+
+/*
+ * SQ_CONSTANT_T2 struct
+ */
+
+#define SQ_CONSTANT_T2_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T2_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T2_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T2_MASK \
+     (SQ_CONSTANT_T2_VALUE_MASK)
+
+#define SQ_CONSTANT_T2(value) \
+     ((value << SQ_CONSTANT_T2_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \
+     ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \
+     sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t2_t f;
+} sq_constant_t2_u;
+
+
+/*
+ * SQ_CONSTANT_T3 struct
+ */
+
+#define SQ_CONSTANT_T3_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T3_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T3_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T3_MASK \
+     (SQ_CONSTANT_T3_VALUE_MASK)
+
+#define SQ_CONSTANT_T3(value) \
+     ((value << SQ_CONSTANT_T3_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \
+     ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \
+     sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t3_t f;
+} sq_constant_t3_u;
+
+
+/*
+ * SQ_CF_BOOLEANS struct
+ */
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_BOOLEANS_MASK \
+     (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_booleans_t f;
+} sq_cf_booleans_u;
+
+
+/*
+ * SQ_CF_LOOP struct
+ */
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_START_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE   8
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT  16
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK  0x000000ff
+#define SQ_CF_LOOP_CF_LOOP_START_MASK  0x0000ff00
+#define SQ_CF_LOOP_CF_LOOP_STEP_MASK   0x00ff0000
+
+#define SQ_CF_LOOP_MASK \
+     (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_loop_t f;
+} sq_cf_loop_u;
+
+
+/*
+ * SQ_CONSTANT_RT_0 struct
+ */
+
+#define SQ_CONSTANT_RT_0_RED_SIZE      32
+
+#define SQ_CONSTANT_RT_0_RED_SHIFT     0
+
+#define SQ_CONSTANT_RT_0_RED_MASK      0xffffffff
+
+#define SQ_CONSTANT_RT_0_MASK \
+     (SQ_CONSTANT_RT_0_RED_MASK)
+
+#define SQ_CONSTANT_RT_0(red) \
+     ((red << SQ_CONSTANT_RT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \
+     ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \
+     sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_0_t f;
+} sq_constant_rt_0_u;
+
+
+/*
+ * SQ_CONSTANT_RT_1 struct
+ */
+
+#define SQ_CONSTANT_RT_1_GREEN_SIZE    32
+
+#define SQ_CONSTANT_RT_1_GREEN_SHIFT   0
+
+#define SQ_CONSTANT_RT_1_GREEN_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_1_MASK \
+     (SQ_CONSTANT_RT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_RT_1(green) \
+     ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \
+     ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \
+     sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_1_t f;
+} sq_constant_rt_1_u;
+
+
+/*
+ * SQ_CONSTANT_RT_2 struct
+ */
+
+#define SQ_CONSTANT_RT_2_BLUE_SIZE     32
+
+#define SQ_CONSTANT_RT_2_BLUE_SHIFT    0
+
+#define SQ_CONSTANT_RT_2_BLUE_MASK     0xffffffff
+
+#define SQ_CONSTANT_RT_2_MASK \
+     (SQ_CONSTANT_RT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_RT_2(blue) \
+     ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \
+     ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \
+     sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_2_t f;
+} sq_constant_rt_2_u;
+
+
+/*
+ * SQ_CONSTANT_RT_3 struct
+ */
+
+#define SQ_CONSTANT_RT_3_ALPHA_SIZE    32
+
+#define SQ_CONSTANT_RT_3_ALPHA_SHIFT   0
+
+#define SQ_CONSTANT_RT_3_ALPHA_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_3_MASK \
+     (SQ_CONSTANT_RT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_RT_3(alpha) \
+     ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \
+     ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \
+     sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_3_t f;
+} sq_constant_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_0 struct
+ */
+
+#define SQ_FETCH_RT_0_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_0_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_0_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_0_MASK \
+     (SQ_FETCH_RT_0_VALUE_MASK)
+
+#define SQ_FETCH_RT_0(value) \
+     ((value << SQ_FETCH_RT_0_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \
+     ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \
+     sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_0_t f;
+} sq_fetch_rt_0_u;
+
+
+/*
+ * SQ_FETCH_RT_1 struct
+ */
+
+#define SQ_FETCH_RT_1_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_1_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_1_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_1_MASK \
+     (SQ_FETCH_RT_1_VALUE_MASK)
+
+#define SQ_FETCH_RT_1(value) \
+     ((value << SQ_FETCH_RT_1_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \
+     ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \
+     sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_1_t f;
+} sq_fetch_rt_1_u;
+
+
+/*
+ * SQ_FETCH_RT_2 struct
+ */
+
+#define SQ_FETCH_RT_2_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_2_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_2_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_2_MASK \
+     (SQ_FETCH_RT_2_VALUE_MASK)
+
+#define SQ_FETCH_RT_2(value) \
+     ((value << SQ_FETCH_RT_2_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \
+     ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \
+     sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_2_t f;
+} sq_fetch_rt_2_u;
+
+
+/*
+ * SQ_FETCH_RT_3 struct
+ */
+
+#define SQ_FETCH_RT_3_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_3_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_3_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_3_MASK \
+     (SQ_FETCH_RT_3_VALUE_MASK)
+
+#define SQ_FETCH_RT_3(value) \
+     ((value << SQ_FETCH_RT_3_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \
+     ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \
+     sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_3_t f;
+} sq_fetch_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_4 struct
+ */
+
+#define SQ_FETCH_RT_4_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_4_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_4_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_4_MASK \
+     (SQ_FETCH_RT_4_VALUE_MASK)
+
+#define SQ_FETCH_RT_4(value) \
+     ((value << SQ_FETCH_RT_4_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \
+     ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \
+     sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_4_t f;
+} sq_fetch_rt_4_u;
+
+
+/*
+ * SQ_FETCH_RT_5 struct
+ */
+
+#define SQ_FETCH_RT_5_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_5_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_5_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_5_MASK \
+     (SQ_FETCH_RT_5_VALUE_MASK)
+
+#define SQ_FETCH_RT_5(value) \
+     ((value << SQ_FETCH_RT_5_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \
+     ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \
+     sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_5_t f;
+} sq_fetch_rt_5_u;
+
+
+/*
+ * SQ_CF_RT_BOOLEANS struct
+ */
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_RT_BOOLEANS_MASK \
+     (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_booleans_t f;
+} sq_cf_rt_booleans_u;
+
+
+/*
+ * SQ_CF_RT_LOOP struct
+ */
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff
+#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000
+
+#define SQ_CF_RT_LOOP_MASK \
+     (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_rt_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_rt_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_loop_t f;
+} sq_cf_rt_loop_u;
+
+
+/*
+ * SQ_VS_PROGRAM struct
+ */
+
+#define SQ_VS_PROGRAM_BASE_SIZE        12
+#define SQ_VS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_VS_PROGRAM_BASE_SHIFT       0
+#define SQ_VS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_VS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_VS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_VS_PROGRAM_MASK \
+     (SQ_VS_PROGRAM_BASE_MASK | \
+      SQ_VS_PROGRAM_SIZE_MASK)
+
+#define SQ_VS_PROGRAM(base, size) \
+     ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_VS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_vs_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+     } sq_vs_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_program_t f;
+} sq_vs_program_u;
+
+
+/*
+ * SQ_PS_PROGRAM struct
+ */
+
+#define SQ_PS_PROGRAM_BASE_SIZE        12
+#define SQ_PS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_PS_PROGRAM_BASE_SHIFT       0
+#define SQ_PS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_PS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_PS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_PS_PROGRAM_MASK \
+     (SQ_PS_PROGRAM_BASE_MASK | \
+      SQ_PS_PROGRAM_SIZE_MASK)
+
+#define SQ_PS_PROGRAM(base, size) \
+     ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_PS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_ps_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+     } sq_ps_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_program_t f;
+} sq_ps_program_u;
+
+
+/*
+ * SQ_CF_PROGRAM_SIZE struct
+ */
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000
+
+#define SQ_CF_PROGRAM_SIZE_MASK \
+     (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \
+      SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK)
+
+#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \
+     ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \
+      (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT))
+
+#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 9;
+     } sq_cf_program_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int                                : 9;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+     } sq_cf_program_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_program_size_t f;
+} sq_cf_program_size_u;
+
+
+/*
+ * SQ_INTERPOLATOR_CNTL struct
+ */
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000
+
+#define SQ_INTERPOLATOR_CNTL_MASK \
+     (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \
+      SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK)
+
+#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \
+     ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \
+      (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT))
+
+#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+     } sq_interpolator_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+     } sq_interpolator_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_interpolator_cntl_t f;
+} sq_interpolator_cntl_u;
+
+
+/*
+ * SQ_PROGRAM_CNTL struct
+ */
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000
+#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000
+
+#define SQ_PROGRAM_CNTL_MASK \
+     (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK)
+
+#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \
+     ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \
+      (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \
+      (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \
+      (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \
+      (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \
+      (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \
+      (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \
+      (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \
+      (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \
+      (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT))
+
+#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+     } sq_program_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+     } sq_program_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_program_cntl_t f;
+} sq_program_cntl_u;
+
+
+/*
+ * SQ_WRAPPING_0 struct
+ */
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f
+#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0
+#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00
+#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000
+#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000
+#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000
+#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000
+#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000
+
+#define SQ_WRAPPING_0_MASK \
+     (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_7_MASK)
+
+#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \
+     ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \
+      (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \
+      (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \
+      (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \
+      (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \
+      (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \
+      (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \
+      (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT))
+
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+     } sq_wrapping_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+     } sq_wrapping_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_0_t f;
+} sq_wrapping_0_u;
+
+
+/*
+ * SQ_WRAPPING_1 struct
+ */
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f
+#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0
+#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00
+#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000
+#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000
+#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000
+#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000
+#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000
+
+#define SQ_WRAPPING_1_MASK \
+     (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_15_MASK)
+
+#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \
+     ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \
+      (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \
+      (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \
+      (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \
+      (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \
+      (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \
+      (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \
+      (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT))
+
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+     } sq_wrapping_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+     } sq_wrapping_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_1_t f;
+} sq_wrapping_1_u;
+
+
+/*
+ * SQ_VS_CONST struct
+ */
+
+#define SQ_VS_CONST_BASE_SIZE          9
+#define SQ_VS_CONST_SIZE_SIZE          9
+
+#define SQ_VS_CONST_BASE_SHIFT         0
+#define SQ_VS_CONST_SIZE_SHIFT         12
+
+#define SQ_VS_CONST_BASE_MASK          0x000001ff
+#define SQ_VS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_VS_CONST_MASK \
+     (SQ_VS_CONST_BASE_MASK | \
+      SQ_VS_CONST_SIZE_MASK)
+
+#define SQ_VS_CONST(base, size) \
+     ((base << SQ_VS_CONST_BASE_SHIFT) | \
+      (size << SQ_VS_CONST_SIZE_SHIFT))
+
+#define SQ_VS_CONST_GET_BASE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT)
+
+#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_vs_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+     } sq_vs_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_const_t f;
+} sq_vs_const_u;
+
+
+/*
+ * SQ_PS_CONST struct
+ */
+
+#define SQ_PS_CONST_BASE_SIZE          9
+#define SQ_PS_CONST_SIZE_SIZE          9
+
+#define SQ_PS_CONST_BASE_SHIFT         0
+#define SQ_PS_CONST_SIZE_SHIFT         12
+
+#define SQ_PS_CONST_BASE_MASK          0x000001ff
+#define SQ_PS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_PS_CONST_MASK \
+     (SQ_PS_CONST_BASE_MASK | \
+      SQ_PS_CONST_SIZE_MASK)
+
+#define SQ_PS_CONST(base, size) \
+     ((base << SQ_PS_CONST_BASE_SHIFT) | \
+      (size << SQ_PS_CONST_SIZE_SHIFT))
+
+#define SQ_PS_CONST_GET_BASE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT)
+
+#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_ps_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+     } sq_ps_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_const_t f;
+} sq_ps_const_u;
+
+
+/*
+ * SQ_CONTEXT_MISC struct
+ */
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000
+
+#define SQ_CONTEXT_MISC_MASK \
+     (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \
+      SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \
+      SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \
+      SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \
+      SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK)
+
+#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \
+     ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \
+      (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \
+      (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \
+      (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \
+      (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \
+      (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \
+      (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT))
+
+#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int                                : 4;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int                                : 13;
+     } sq_context_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int                                : 13;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int                                : 4;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+     } sq_context_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_context_misc_t f;
+} sq_context_misc_u;
+
+
+/*
+ * SQ_CF_RD_BASE struct
+ */
+
+#define SQ_CF_RD_BASE_RD_BASE_SIZE     3
+
+#define SQ_CF_RD_BASE_RD_BASE_SHIFT    0
+
+#define SQ_CF_RD_BASE_RD_BASE_MASK     0x00000007
+
+#define SQ_CF_RD_BASE_MASK \
+     (SQ_CF_RD_BASE_RD_BASE_MASK)
+
+#define SQ_CF_RD_BASE(rd_base) \
+     ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT))
+
+#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \
+     ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \
+     sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+          unsigned int                                : 29;
+     } sq_cf_rd_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int                                : 29;
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+     } sq_cf_rd_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rd_base_t f;
+} sq_cf_rd_base_u;
+
+
+/*
+ * SQ_DEBUG_MISC_0 struct
+ */
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000
+
+#define SQ_DEBUG_MISC_0_MASK \
+     (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK)
+
+#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \
+     ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \
+      (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \
+      (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \
+      (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT))
+
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+     } sq_debug_misc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+     } sq_debug_misc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_0_t f;
+} sq_debug_misc_0_u;
+
+
+/*
+ * SQ_DEBUG_MISC_1 struct
+ */
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000
+
+#define SQ_DEBUG_MISC_1_MASK \
+     (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \
+      SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \
+      SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \
+      SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK)
+
+#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \
+     ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \
+      (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \
+      (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \
+      (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT))
+
+#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int                                : 5;
+     } sq_debug_misc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int                                : 5;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+     } sq_debug_misc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_1_t f;
+} sq_debug_misc_1_u;
+
+
+#endif
+
+
+#if !defined (_SX_FIDDLE_H)
+#define _SX_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_TP_FIDDLE_H)
+#define _TP_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * TC_CNTL_STATUS struct
+ */
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2
+#define TC_CNTL_STATUS_TC_BUSY_SIZE    1
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18
+#define TC_CNTL_STATUS_TC_BUSY_SHIFT   31
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000
+#define TC_CNTL_STATUS_TC_BUSY_MASK    0x80000000
+
+#define TC_CNTL_STATUS_MASK \
+     (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \
+      TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \
+      TC_CNTL_STATUS_TC_BUSY_MASK)
+
+#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \
+     ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \
+      (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \
+      (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT))
+
+#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+          unsigned int                                : 17;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+     } tc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 17;
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+     } tc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tc_cntl_status_t f;
+} tc_cntl_status_u;
+
+
+/*
+ * TCR_CHICKEN struct
+ */
+
+#define TCR_CHICKEN_SPARE_SIZE         32
+
+#define TCR_CHICKEN_SPARE_SHIFT        0
+
+#define TCR_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCR_CHICKEN_MASK \
+     (TCR_CHICKEN_SPARE_MASK)
+
+#define TCR_CHICKEN(spare) \
+     ((spare << TCR_CHICKEN_SPARE_SHIFT))
+
+#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \
+     ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT)
+
+#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \
+     tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_chicken_t f;
+} tcr_chicken_u;
+
+
+/*
+ * TCF_CHICKEN struct
+ */
+
+#define TCF_CHICKEN_SPARE_SIZE         32
+
+#define TCF_CHICKEN_SPARE_SHIFT        0
+
+#define TCF_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCF_CHICKEN_MASK \
+     (TCF_CHICKEN_SPARE_MASK)
+
+#define TCF_CHICKEN(spare) \
+     ((spare << TCF_CHICKEN_SPARE_SHIFT))
+
+#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \
+     ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT)
+
+#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \
+     tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_chicken_t f;
+} tcf_chicken_u;
+
+
+/*
+ * TCM_CHICKEN struct
+ */
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1
+#define TCM_CHICKEN_SPARE_SIZE         23
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8
+#define TCM_CHICKEN_SPARE_SHIFT        9
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100
+#define TCM_CHICKEN_SPARE_MASK         0xfffffe00
+
+#define TCM_CHICKEN_MASK \
+     (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \
+      TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \
+      TCM_CHICKEN_SPARE_MASK)
+
+#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \
+     ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \
+      (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \
+      (spare << TCM_CHICKEN_SPARE_SHIFT))
+
+#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT)
+
+#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+     } tcm_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+     } tcm_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_chicken_t f;
+} tcm_chicken_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER0_SELECT_MASK \
+     (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \
+     ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \
+     tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_select_t f;
+} tcr_perfcounter0_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER1_SELECT_MASK \
+     (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \
+     ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \
+     tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_select_t f;
+} tcr_perfcounter1_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_HI struct
+ */
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER0_HI_MASK \
+     (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \
+     ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \
+     tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_hi_t f;
+} tcr_perfcounter0_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_HI struct
+ */
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER1_HI_MASK \
+     (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \
+     ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \
+     tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_hi_t f;
+} tcr_perfcounter1_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_LOW struct
+ */
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER0_LOW_MASK \
+     (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \
+     ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \
+     tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_low_t f;
+} tcr_perfcounter0_low_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_LOW struct
+ */
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER1_LOW_MASK \
+     (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \
+     ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \
+     tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_low_t f;
+} tcr_perfcounter1_low_u;
+
+
+/*
+ * TP_TC_CLKGATE_CNTL struct
+ */
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038
+
+#define TP_TC_CLKGATE_CNTL_MASK \
+     (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \
+      TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK)
+
+#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \
+     ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \
+      (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT))
+
+#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int                                : 26;
+     } tp_tc_clkgate_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int                                : 26;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+     } tp_tc_clkgate_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp_tc_clkgate_cntl_t f;
+} tp_tc_clkgate_cntl_u;
+
+
+/*
+ * TPC_CNTL_STATUS struct
+ */
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BUSY_SIZE  1
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15
+#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17
+#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19
+#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22
+#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23
+#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25
+#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27
+#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30
+#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000
+#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000
+#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000
+#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000
+#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000
+#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000
+#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000
+#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000
+#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000
+#define TPC_CNTL_STATUS_TPC_BUSY_MASK  0x80000000
+
+#define TPC_CNTL_STATUS_MASK \
+     (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTR_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TF_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \
+      TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \
+      TPC_CNTL_STATUS_TPC_BUSY_MASK)
+
+#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \
+     ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \
+      (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \
+      (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \
+      (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \
+      (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \
+      (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \
+      (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \
+      (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \
+      (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \
+      (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \
+      (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \
+      (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \
+      (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \
+      (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \
+      (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \
+      (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \
+      (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \
+      (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \
+      (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \
+      (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \
+      (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \
+      (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \
+      (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT))
+
+#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_cntl_status_t f;
+} tpc_cntl_status_u;
+
+
+/*
+ * TPC_DEBUG0 struct
+ */
+
+#define TPC_DEBUG0_LOD_CNTL_SIZE       2
+#define TPC_DEBUG0_IC_CTR_SIZE         2
+#define TPC_DEBUG0_WALKER_CNTL_SIZE    4
+#define TPC_DEBUG0_ALIGNER_CNTL_SIZE   3
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1
+#define TPC_DEBUG0_WALKER_STATE_SIZE   10
+#define TPC_DEBUG0_ALIGNER_STATE_SIZE  2
+#define TPC_DEBUG0_REG_CLK_EN_SIZE     1
+#define TPC_DEBUG0_TPC_CLK_EN_SIZE     1
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE   1
+
+#define TPC_DEBUG0_LOD_CNTL_SHIFT      0
+#define TPC_DEBUG0_IC_CTR_SHIFT        2
+#define TPC_DEBUG0_WALKER_CNTL_SHIFT   4
+#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT  8
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12
+#define TPC_DEBUG0_WALKER_STATE_SHIFT  16
+#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26
+#define TPC_DEBUG0_REG_CLK_EN_SHIFT    29
+#define TPC_DEBUG0_TPC_CLK_EN_SHIFT    30
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT  31
+
+#define TPC_DEBUG0_LOD_CNTL_MASK       0x00000003
+#define TPC_DEBUG0_IC_CTR_MASK         0x0000000c
+#define TPC_DEBUG0_WALKER_CNTL_MASK    0x000000f0
+#define TPC_DEBUG0_ALIGNER_CNTL_MASK   0x00000700
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000
+#define TPC_DEBUG0_WALKER_STATE_MASK   0x03ff0000
+#define TPC_DEBUG0_ALIGNER_STATE_MASK  0x0c000000
+#define TPC_DEBUG0_REG_CLK_EN_MASK     0x20000000
+#define TPC_DEBUG0_TPC_CLK_EN_MASK     0x40000000
+#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK   0x80000000
+
+#define TPC_DEBUG0_MASK \
+     (TPC_DEBUG0_LOD_CNTL_MASK | \
+      TPC_DEBUG0_IC_CTR_MASK | \
+      TPC_DEBUG0_WALKER_CNTL_MASK | \
+      TPC_DEBUG0_ALIGNER_CNTL_MASK | \
+      TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \
+      TPC_DEBUG0_WALKER_STATE_MASK | \
+      TPC_DEBUG0_ALIGNER_STATE_MASK | \
+      TPC_DEBUG0_REG_CLK_EN_MASK | \
+      TPC_DEBUG0_TPC_CLK_EN_MASK | \
+      TPC_DEBUG0_SQ_TP_WAKEUP_MASK)
+
+#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \
+     ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \
+      (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \
+      (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \
+      (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \
+      (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \
+      (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \
+      (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \
+      (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \
+      (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \
+      (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT))
+
+#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 3;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+     } tpc_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+     } tpc_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug0_t f;
+} tpc_debug0_u;
+
+
+/*
+ * TPC_DEBUG1 struct
+ */
+
+#define TPC_DEBUG1_UNUSED_SIZE         1
+
+#define TPC_DEBUG1_UNUSED_SHIFT        0
+
+#define TPC_DEBUG1_UNUSED_MASK         0x00000001
+
+#define TPC_DEBUG1_MASK \
+     (TPC_DEBUG1_UNUSED_MASK)
+
+#define TPC_DEBUG1(unused) \
+     ((unused << TPC_DEBUG1_UNUSED_SHIFT))
+
+#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \
+     ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT)
+
+#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \
+     tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+          unsigned int                                : 31;
+     } tpc_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int                                : 31;
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+     } tpc_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug1_t f;
+} tpc_debug1_u;
+
+
+/*
+ * TPC_CHICKEN struct
+ */
+
+#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1
+#define TPC_CHICKEN_SPARE_SIZE         31
+
+#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0
+#define TPC_CHICKEN_SPARE_SHIFT        1
+
+#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001
+#define TPC_CHICKEN_SPARE_MASK         0xfffffffe
+
+#define TPC_CHICKEN_MASK \
+     (TPC_CHICKEN_BLEND_PRECISION_MASK | \
+      TPC_CHICKEN_SPARE_MASK)
+
+#define TPC_CHICKEN(blend_precision, spare) \
+     ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \
+      (spare << TPC_CHICKEN_SPARE_SHIFT))
+
+#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT)
+
+#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+     } tpc_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+     } tpc_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_chicken_t f;
+} tpc_chicken_u;
+
+
+/*
+ * TP0_CNTL_STATUS struct
+ */
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1
+#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TP_BUSY_SIZE   1
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14
+#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16
+#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17
+#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18
+#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19
+#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21
+#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23
+#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25
+#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27
+#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29
+#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30
+#define TP0_CNTL_STATUS_TP_BUSY_SHIFT  31
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200
+#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000
+#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000
+#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000
+#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000
+#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000
+#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000
+#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000
+#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000
+#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000
+#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000
+#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000
+#define TP0_CNTL_STATUS_TP_BUSY_MASK   0x80000000
+
+#define TP0_CNTL_STATUS_MASK \
+     (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_IN_LC_RTS_MASK | \
+      TP0_CNTL_STATUS_LC_LA_RTS_MASK | \
+      TP0_CNTL_STATUS_LA_FL_RTS_MASK | \
+      TP0_CNTL_STATUS_FL_TA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \
+      TP0_CNTL_STATUS_TB_TO_RTS_MASK | \
+      TP0_CNTL_STATUS_TP_BUSY_MASK)
+
+#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \
+     ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \
+      (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \
+      (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \
+      (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \
+      (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \
+      (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \
+      (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \
+      (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \
+      (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \
+      (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \
+      (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \
+      (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \
+      (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \
+      (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \
+      (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \
+      (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \
+      (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \
+      (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \
+      (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \
+      (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \
+      (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \
+      (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \
+      (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \
+      (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \
+      (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \
+      (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \
+      (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \
+      (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \
+      (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \
+      (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT))
+
+#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_cntl_status_t f;
+} tp0_cntl_status_u;
+
+
+/*
+ * TP0_DEBUG struct
+ */
+
+#define TP0_DEBUG_Q_LOD_CNTL_SIZE      2
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE  1
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17
+#define TP0_DEBUG_REG_CLK_EN_SIZE      1
+#define TP0_DEBUG_PERF_CLK_EN_SIZE     1
+#define TP0_DEBUG_TP_CLK_EN_SIZE       1
+#define TP0_DEBUG_Q_WALKER_CNTL_SIZE   4
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE  3
+
+#define TP0_DEBUG_Q_LOD_CNTL_SHIFT     0
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4
+#define TP0_DEBUG_REG_CLK_EN_SHIFT     21
+#define TP0_DEBUG_PERF_CLK_EN_SHIFT    22
+#define TP0_DEBUG_TP_CLK_EN_SHIFT      23
+#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT  24
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28
+
+#define TP0_DEBUG_Q_LOD_CNTL_MASK      0x00000003
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK  0x00000008
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0
+#define TP0_DEBUG_REG_CLK_EN_MASK      0x00200000
+#define TP0_DEBUG_PERF_CLK_EN_MASK     0x00400000
+#define TP0_DEBUG_TP_CLK_EN_MASK       0x00800000
+#define TP0_DEBUG_Q_WALKER_CNTL_MASK   0x0f000000
+#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK  0x70000000
+
+#define TP0_DEBUG_MASK \
+     (TP0_DEBUG_Q_LOD_CNTL_MASK | \
+      TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \
+      TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \
+      TP0_DEBUG_REG_CLK_EN_MASK | \
+      TP0_DEBUG_PERF_CLK_EN_MASK | \
+      TP0_DEBUG_TP_CLK_EN_MASK | \
+      TP0_DEBUG_Q_WALKER_CNTL_MASK | \
+      TP0_DEBUG_Q_ALIGNER_CNTL_MASK)
+
+#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \
+     ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \
+      (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \
+      (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \
+      (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \
+      (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \
+      (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \
+      (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \
+      (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT))
+
+#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+     } tp0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int                                : 1;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+     } tp0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_debug_t f;
+} tp0_debug_u;
+
+
+/*
+ * TP0_CHICKEN struct
+ */
+
+#define TP0_CHICKEN_TT_MODE_SIZE       1
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1
+#define TP0_CHICKEN_SPARE_SIZE         30
+
+#define TP0_CHICKEN_TT_MODE_SHIFT      0
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1
+#define TP0_CHICKEN_SPARE_SHIFT        2
+
+#define TP0_CHICKEN_TT_MODE_MASK       0x00000001
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002
+#define TP0_CHICKEN_SPARE_MASK         0xfffffffc
+
+#define TP0_CHICKEN_MASK \
+     (TP0_CHICKEN_TT_MODE_MASK | \
+      TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \
+      TP0_CHICKEN_SPARE_MASK)
+
+#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \
+     ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \
+      (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \
+      (spare << TP0_CHICKEN_SPARE_SHIFT))
+
+#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT)
+
+#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+     } tp0_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+     } tp0_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_chicken_t f;
+} tp0_chicken_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER0_SELECT_MASK \
+     (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \
+     ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \
+     tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_select_t f;
+} tp0_perfcounter0_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_HI struct
+ */
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER0_HI_MASK \
+     (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \
+     ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \
+     tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_hi_t f;
+} tp0_perfcounter0_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_LOW struct
+ */
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER0_LOW_MASK \
+     (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \
+     ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \
+     tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_low_t f;
+} tp0_perfcounter0_low_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER1_SELECT_MASK \
+     (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \
+     ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \
+     tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_select_t f;
+} tp0_perfcounter1_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_HI struct
+ */
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER1_HI_MASK \
+     (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \
+     ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \
+     tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_hi_t f;
+} tp0_perfcounter1_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_LOW struct
+ */
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER1_LOW_MASK \
+     (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \
+     ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \
+     tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_low_t f;
+} tp0_perfcounter1_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER0_SELECT_MASK \
+     (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \
+     ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \
+     tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_select_t f;
+} tcm_perfcounter0_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER1_SELECT_MASK \
+     (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \
+     ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \
+     tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_select_t f;
+} tcm_perfcounter1_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_HI struct
+ */
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER0_HI_MASK \
+     (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \
+     ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \
+     tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_hi_t f;
+} tcm_perfcounter0_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_HI struct
+ */
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER1_HI_MASK \
+     (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \
+     ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \
+     tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_hi_t f;
+} tcm_perfcounter1_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_LOW struct
+ */
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER0_LOW_MASK \
+     (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \
+     ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \
+     tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_low_t f;
+} tcm_perfcounter0_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_LOW struct
+ */
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER1_LOW_MASK \
+     (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \
+     ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \
+     tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_low_t f;
+} tcm_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER0_SELECT_MASK \
+     (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \
+     ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \
+     tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_select_t f;
+} tcf_perfcounter0_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER1_SELECT_MASK \
+     (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \
+     ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \
+     tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_select_t f;
+} tcf_perfcounter1_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER2_SELECT_MASK \
+     (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \
+     ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \
+     tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_select_t f;
+} tcf_perfcounter2_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER3_SELECT_MASK \
+     (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \
+     ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \
+     tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_select_t f;
+} tcf_perfcounter3_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER4_SELECT_MASK \
+     (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \
+     ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \
+     tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter4_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter4_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_select_t f;
+} tcf_perfcounter4_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER5_SELECT_MASK \
+     (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \
+     ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \
+     tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter5_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter5_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_select_t f;
+} tcf_perfcounter5_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER6_SELECT_MASK \
+     (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \
+     ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \
+     tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter6_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter6_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_select_t f;
+} tcf_perfcounter6_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER7_SELECT_MASK \
+     (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \
+     ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \
+     tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter7_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter7_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_select_t f;
+} tcf_perfcounter7_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER8_SELECT_MASK \
+     (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \
+     ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \
+     tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter8_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter8_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_select_t f;
+} tcf_perfcounter8_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER9_SELECT_MASK \
+     (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \
+     ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \
+     tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter9_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter9_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_select_t f;
+} tcf_perfcounter9_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER10_SELECT_MASK \
+     (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \
+     ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \
+     tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter10_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter10_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_select_t f;
+} tcf_perfcounter10_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER11_SELECT_MASK \
+     (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \
+     ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \
+     tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter11_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter11_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_select_t f;
+} tcf_perfcounter11_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_HI struct
+ */
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER0_HI_MASK \
+     (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \
+     ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \
+     tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_hi_t f;
+} tcf_perfcounter0_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_HI struct
+ */
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER1_HI_MASK \
+     (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \
+     ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \
+     tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_hi_t f;
+} tcf_perfcounter1_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_HI struct
+ */
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER2_HI_MASK \
+     (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \
+     ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \
+     tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_hi_t f;
+} tcf_perfcounter2_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_HI struct
+ */
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER3_HI_MASK \
+     (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \
+     ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \
+     tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_hi_t f;
+} tcf_perfcounter3_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_HI struct
+ */
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER4_HI_MASK \
+     (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \
+     ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \
+     tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter4_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter4_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_hi_t f;
+} tcf_perfcounter4_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_HI struct
+ */
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER5_HI_MASK \
+     (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \
+     ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \
+     tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter5_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter5_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_hi_t f;
+} tcf_perfcounter5_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_HI struct
+ */
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER6_HI_MASK \
+     (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \
+     ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \
+     tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter6_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter6_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_hi_t f;
+} tcf_perfcounter6_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_HI struct
+ */
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER7_HI_MASK \
+     (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \
+     ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \
+     tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter7_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter7_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_hi_t f;
+} tcf_perfcounter7_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_HI struct
+ */
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER8_HI_MASK \
+     (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \
+     ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \
+     tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter8_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter8_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_hi_t f;
+} tcf_perfcounter8_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_HI struct
+ */
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER9_HI_MASK \
+     (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \
+     ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \
+     tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter9_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter9_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_hi_t f;
+} tcf_perfcounter9_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_HI struct
+ */
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER10_HI_MASK \
+     (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \
+     ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \
+     tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter10_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter10_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_hi_t f;
+} tcf_perfcounter10_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_HI struct
+ */
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER11_HI_MASK \
+     (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \
+     ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \
+     tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter11_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter11_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_hi_t f;
+} tcf_perfcounter11_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_LOW struct
+ */
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER0_LOW_MASK \
+     (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \
+     ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \
+     tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_low_t f;
+} tcf_perfcounter0_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_LOW struct
+ */
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER1_LOW_MASK \
+     (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \
+     ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \
+     tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_low_t f;
+} tcf_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_LOW struct
+ */
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER2_LOW_MASK \
+     (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \
+     ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \
+     tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_low_t f;
+} tcf_perfcounter2_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_LOW struct
+ */
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER3_LOW_MASK \
+     (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \
+     ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \
+     tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_low_t f;
+} tcf_perfcounter3_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_LOW struct
+ */
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER4_LOW_MASK \
+     (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \
+     ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \
+     tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_low_t f;
+} tcf_perfcounter4_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_LOW struct
+ */
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER5_LOW_MASK \
+     (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \
+     ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \
+     tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_low_t f;
+} tcf_perfcounter5_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_LOW struct
+ */
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER6_LOW_MASK \
+     (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \
+     ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \
+     tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_low_t f;
+} tcf_perfcounter6_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_LOW struct
+ */
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER7_LOW_MASK \
+     (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \
+     ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \
+     tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_low_t f;
+} tcf_perfcounter7_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_LOW struct
+ */
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER8_LOW_MASK \
+     (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \
+     ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \
+     tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_low_t f;
+} tcf_perfcounter8_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_LOW struct
+ */
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER9_LOW_MASK \
+     (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \
+     ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \
+     tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_low_t f;
+} tcf_perfcounter9_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_LOW struct
+ */
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER10_LOW_MASK \
+     (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \
+     ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \
+     tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_low_t f;
+} tcf_perfcounter10_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_LOW struct
+ */
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER11_LOW_MASK \
+     (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \
+     ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \
+     tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_low_t f;
+} tcf_perfcounter11_low_u;
+
+
+/*
+ * TCF_DEBUG struct
+ */
+
+#define TCF_DEBUG_not_MH_TC_rtr_SIZE   1
+#define TCF_DEBUG_TC_MH_send_SIZE      1
+#define TCF_DEBUG_not_FG0_rtr_SIZE     1
+#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1
+#define TCF_DEBUG_TCB_ff_stall_SIZE    1
+#define TCF_DEBUG_TCB_miss_stall_SIZE  1
+#define TCF_DEBUG_TCA_TCB_stall_SIZE   1
+#define TCF_DEBUG_PF0_stall_SIZE       1
+#define TCF_DEBUG_TP0_full_SIZE        1
+#define TCF_DEBUG_TPC_full_SIZE        1
+#define TCF_DEBUG_not_TPC_rtr_SIZE     1
+#define TCF_DEBUG_tca_state_rts_SIZE   1
+#define TCF_DEBUG_tca_rts_SIZE         1
+
+#define TCF_DEBUG_not_MH_TC_rtr_SHIFT  6
+#define TCF_DEBUG_TC_MH_send_SHIFT     7
+#define TCF_DEBUG_not_FG0_rtr_SHIFT    8
+#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12
+#define TCF_DEBUG_TCB_ff_stall_SHIFT   13
+#define TCF_DEBUG_TCB_miss_stall_SHIFT 14
+#define TCF_DEBUG_TCA_TCB_stall_SHIFT  15
+#define TCF_DEBUG_PF0_stall_SHIFT      16
+#define TCF_DEBUG_TP0_full_SHIFT       20
+#define TCF_DEBUG_TPC_full_SHIFT       24
+#define TCF_DEBUG_not_TPC_rtr_SHIFT    25
+#define TCF_DEBUG_tca_state_rts_SHIFT  26
+#define TCF_DEBUG_tca_rts_SHIFT        27
+
+#define TCF_DEBUG_not_MH_TC_rtr_MASK   0x00000040
+#define TCF_DEBUG_TC_MH_send_MASK      0x00000080
+#define TCF_DEBUG_not_FG0_rtr_MASK     0x00000100
+#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000
+#define TCF_DEBUG_TCB_ff_stall_MASK    0x00002000
+#define TCF_DEBUG_TCB_miss_stall_MASK  0x00004000
+#define TCF_DEBUG_TCA_TCB_stall_MASK   0x00008000
+#define TCF_DEBUG_PF0_stall_MASK       0x00010000
+#define TCF_DEBUG_TP0_full_MASK        0x00100000
+#define TCF_DEBUG_TPC_full_MASK        0x01000000
+#define TCF_DEBUG_not_TPC_rtr_MASK     0x02000000
+#define TCF_DEBUG_tca_state_rts_MASK   0x04000000
+#define TCF_DEBUG_tca_rts_MASK         0x08000000
+
+#define TCF_DEBUG_MASK \
+     (TCF_DEBUG_not_MH_TC_rtr_MASK | \
+      TCF_DEBUG_TC_MH_send_MASK | \
+      TCF_DEBUG_not_FG0_rtr_MASK | \
+      TCF_DEBUG_not_TCB_TCO_rtr_MASK | \
+      TCF_DEBUG_TCB_ff_stall_MASK | \
+      TCF_DEBUG_TCB_miss_stall_MASK | \
+      TCF_DEBUG_TCA_TCB_stall_MASK | \
+      TCF_DEBUG_PF0_stall_MASK | \
+      TCF_DEBUG_TP0_full_MASK | \
+      TCF_DEBUG_TPC_full_MASK | \
+      TCF_DEBUG_not_TPC_rtr_MASK | \
+      TCF_DEBUG_tca_state_rts_MASK | \
+      TCF_DEBUG_tca_rts_MASK)
+
+#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \
+     ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \
+      (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \
+      (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \
+      (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \
+      (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \
+      (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \
+      (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \
+      (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \
+      (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \
+      (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \
+      (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \
+      (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \
+      (tca_rts << TCF_DEBUG_tca_rts_SHIFT))
+
+#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_GET_TP0_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_GET_TPC_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_GET_tca_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT)
+
+#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 6;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int                                : 4;
+     } tcf_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 4;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int                                : 6;
+     } tcf_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_debug_t f;
+} tcf_debug_u;
+
+
+/*
+ * TCA_FIFO_DEBUG struct
+ */
+
+#define TCA_FIFO_DEBUG_tp0_full_SIZE   1
+#define TCA_FIFO_DEBUG_tpc_full_SIZE   1
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1
+#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1
+#define TCA_FIFO_DEBUG_FW_full_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1
+#define TCA_FIFO_DEBUG_FW_rts0_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1
+
+#define TCA_FIFO_DEBUG_tp0_full_SHIFT  0
+#define TCA_FIFO_DEBUG_tpc_full_SHIFT  4
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5
+#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6
+#define TCA_FIFO_DEBUG_FW_full_SHIFT   7
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8
+#define TCA_FIFO_DEBUG_FW_rts0_SHIFT   12
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17
+
+#define TCA_FIFO_DEBUG_tp0_full_MASK   0x00000001
+#define TCA_FIFO_DEBUG_tpc_full_MASK   0x00000010
+#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020
+#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040
+#define TCA_FIFO_DEBUG_FW_full_MASK    0x00000080
+#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100
+#define TCA_FIFO_DEBUG_FW_rts0_MASK    0x00001000
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000
+#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000
+
+#define TCA_FIFO_DEBUG_MASK \
+     (TCA_FIFO_DEBUG_tp0_full_MASK | \
+      TCA_FIFO_DEBUG_tpc_full_MASK | \
+      TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \
+      TCA_FIFO_DEBUG_load_tp_fifos_MASK | \
+      TCA_FIFO_DEBUG_FW_full_MASK | \
+      TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \
+      TCA_FIFO_DEBUG_FW_rts0_MASK | \
+      TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \
+      TCA_FIFO_DEBUG_FW_tpc_rts_MASK)
+
+#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \
+     ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \
+      (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \
+      (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \
+      (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \
+      (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \
+      (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \
+      (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \
+      (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \
+      (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT))
+
+#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int                                : 14;
+     } tca_fifo_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int                                : 14;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+     } tca_fifo_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_fifo_debug_t f;
+} tca_fifo_debug_u;
+
+
+/*
+ * TCA_PROBE_DEBUG struct
+ */
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001
+
+#define TCA_PROBE_DEBUG_MASK \
+     (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK)
+
+#define TCA_PROBE_DEBUG(probefilter_stall) \
+     ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT))
+
+#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \
+     ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \
+     tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+          unsigned int                                : 31;
+     } tca_probe_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int                                : 31;
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+     } tca_probe_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_probe_debug_t f;
+} tca_probe_debug_u;
+
+
+/*
+ * TCA_TPC_DEBUG struct
+ */
+
+#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1
+#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1
+
+#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12
+#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13
+
+#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000
+#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000
+
+#define TCA_TPC_DEBUG_MASK \
+     (TCA_TPC_DEBUG_captue_state_rts_MASK | \
+      TCA_TPC_DEBUG_capture_tca_rts_MASK)
+
+#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \
+     ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \
+      (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT))
+
+#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 12;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int                                : 18;
+     } tca_tpc_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 18;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int                                : 12;
+     } tca_tpc_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_tpc_debug_t f;
+} tca_tpc_debug_u;
+
+
+/*
+ * TCB_CORE_DEBUG struct
+ */
+
+#define TCB_CORE_DEBUG_access512_SIZE  1
+#define TCB_CORE_DEBUG_tiled_SIZE      1
+#define TCB_CORE_DEBUG_opcode_SIZE     3
+#define TCB_CORE_DEBUG_format_SIZE     6
+#define TCB_CORE_DEBUG_sector_format_SIZE 5
+#define TCB_CORE_DEBUG_sector_format512_SIZE 3
+
+#define TCB_CORE_DEBUG_access512_SHIFT 0
+#define TCB_CORE_DEBUG_tiled_SHIFT     1
+#define TCB_CORE_DEBUG_opcode_SHIFT    4
+#define TCB_CORE_DEBUG_format_SHIFT    8
+#define TCB_CORE_DEBUG_sector_format_SHIFT 16
+#define TCB_CORE_DEBUG_sector_format512_SHIFT 24
+
+#define TCB_CORE_DEBUG_access512_MASK  0x00000001
+#define TCB_CORE_DEBUG_tiled_MASK      0x00000002
+#define TCB_CORE_DEBUG_opcode_MASK     0x00000070
+#define TCB_CORE_DEBUG_format_MASK     0x00003f00
+#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000
+#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000
+
+#define TCB_CORE_DEBUG_MASK \
+     (TCB_CORE_DEBUG_access512_MASK | \
+      TCB_CORE_DEBUG_tiled_MASK | \
+      TCB_CORE_DEBUG_opcode_MASK | \
+      TCB_CORE_DEBUG_format_MASK | \
+      TCB_CORE_DEBUG_sector_format_MASK | \
+      TCB_CORE_DEBUG_sector_format512_MASK)
+
+#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \
+     ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \
+      (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \
+      (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \
+      (format << TCB_CORE_DEBUG_format_SHIFT) | \
+      (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \
+      (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT))
+
+#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int                                : 2;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 1;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 5;
+     } tcb_core_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int                                : 5;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 2;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+     } tcb_core_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_core_debug_t f;
+} tcb_core_debug_u;
+
+
+/*
+ * TCB_TAG0_DEBUG struct
+ */
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG0_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG0_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG0_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG0_DEBUG_MASK \
+     (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG0_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG0_DEBUG_miss_stall_MASK | \
+      TCB_TAG0_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG0_DEBUG_max_misses_MASK)
+
+#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+     } tcb_tag0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag0_debug_t f;
+} tcb_tag0_debug_u;
+
+
+/*
+ * TCB_TAG1_DEBUG struct
+ */
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG1_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG1_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG1_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG1_DEBUG_MASK \
+     (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG1_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG1_DEBUG_miss_stall_MASK | \
+      TCB_TAG1_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG1_DEBUG_max_misses_MASK)
+
+#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+     } tcb_tag1_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag1_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag1_debug_t f;
+} tcb_tag1_debug_u;
+
+
+/*
+ * TCB_TAG2_DEBUG struct
+ */
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG2_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG2_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG2_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG2_DEBUG_MASK \
+     (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG2_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG2_DEBUG_miss_stall_MASK | \
+      TCB_TAG2_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG2_DEBUG_max_misses_MASK)
+
+#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+     } tcb_tag2_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag2_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag2_debug_t f;
+} tcb_tag2_debug_u;
+
+
+/*
+ * TCB_TAG3_DEBUG struct
+ */
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG3_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG3_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG3_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG3_DEBUG_MASK \
+     (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG3_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG3_DEBUG_miss_stall_MASK | \
+      TCB_TAG3_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG3_DEBUG_max_misses_MASK)
+
+#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+     } tcb_tag3_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag3_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag3_debug_t f;
+} tcb_tag3_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \
+     (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \
+     ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \
+      (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \
+      (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \
+      (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \
+      (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \
+      (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \
+      (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \
+      (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT))
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int                                : 3;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int                                : 3;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_sector_walker0_debug_t f;
+} tcb_fetch_gen_sector_walker0_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_WALKER_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \
+     (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \
+     ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \
+      (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \
+      (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \
+      (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \
+      (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \
+      (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT))
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 4;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int                                : 12;
+     } tcb_fetch_gen_walker_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 12;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int                                : 4;
+     } tcb_fetch_gen_walker_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_walker_debug_t f;
+} tcb_fetch_gen_walker_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_PIPE0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \
+     (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \
+     ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \
+      (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \
+      (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \
+      (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \
+      (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \
+      (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \
+      (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \
+      (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \
+      (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \
+      (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \
+      (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT))
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_pipe0_debug_t f;
+} tcb_fetch_gen_pipe0_debug_u;
+
+
+/*
+ * TCD_INPUT0_DEBUG struct
+ */
+
+#define TCD_INPUT0_DEBUG_empty_SIZE    1
+#define TCD_INPUT0_DEBUG_full_SIZE     1
+#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_cnt_q1_SIZE   2
+#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_ip_send_SIZE  1
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1
+
+#define TCD_INPUT0_DEBUG_empty_SHIFT   16
+#define TCD_INPUT0_DEBUG_full_SHIFT    17
+#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20
+#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT  21
+#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23
+#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26
+
+#define TCD_INPUT0_DEBUG_empty_MASK    0x00010000
+#define TCD_INPUT0_DEBUG_full_MASK     0x00020000
+#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000
+#define TCD_INPUT0_DEBUG_cnt_q1_MASK   0x00600000
+#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000
+#define TCD_INPUT0_DEBUG_ip_send_MASK  0x01000000
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000
+#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000
+
+#define TCD_INPUT0_DEBUG_MASK \
+     (TCD_INPUT0_DEBUG_empty_MASK | \
+      TCD_INPUT0_DEBUG_full_MASK | \
+      TCD_INPUT0_DEBUG_valid_q1_MASK | \
+      TCD_INPUT0_DEBUG_cnt_q1_MASK | \
+      TCD_INPUT0_DEBUG_last_send_q1_MASK | \
+      TCD_INPUT0_DEBUG_ip_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_busy_MASK)
+
+#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \
+     ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \
+      (full << TCD_INPUT0_DEBUG_full_SHIFT) | \
+      (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \
+      (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \
+      (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \
+      (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \
+      (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \
+      (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT))
+
+#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 16;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int                                : 2;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int                                : 5;
+     } tcd_input0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 5;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int                                : 2;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int                                : 16;
+     } tcd_input0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_input0_debug_t f;
+} tcd_input0_debug_u;
+
+
+/*
+ * TCD_DEGAMMA_DEBUG struct
+ */
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040
+
+#define TCD_DEGAMMA_DEBUG_MASK \
+     (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK)
+
+#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \
+     ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \
+      (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \
+      (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \
+      (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \
+      (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \
+      (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT))
+
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int                                : 25;
+     } tcd_degamma_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int                                : 25;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+     } tcd_degamma_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_degamma_debug_t f;
+} tcd_degamma_debug_u;
+
+
+/*
+ * TCD_DXTMUX_SCTARB_DEBUG struct
+ */
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000
+
+#define TCD_DXTMUX_SCTARB_DEBUG_MASK \
+     (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK)
+
+#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \
+     ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \
+      (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \
+      (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \
+      (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \
+      (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \
+      (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \
+      (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \
+      (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \
+      (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT))
+
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 9;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int                                : 2;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 2;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int                                : 9;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtmux_sctarb_debug_t f;
+} tcd_dxtmux_sctarb_debug_u;
+
+
+/*
+ * TCD_DXTC_ARB_DEBUG struct
+ */
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4
+#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010
+#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000
+
+#define TCD_DXTC_ARB_DEBUG_MASK \
+     (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \
+      TCD_DXTC_ARB_DEBUG_pstate_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK)
+
+#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \
+     ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \
+      (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \
+      (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \
+      (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \
+      (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \
+      (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \
+      (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \
+      (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \
+      (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT))
+
+#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int                                : 4;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+     } tcd_dxtc_arb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int                                : 4;
+     } tcd_dxtc_arb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtc_arb_debug_t f;
+} tcd_dxtc_arb_debug_u;
+
+
+/*
+ * TCD_STALLS_DEBUG struct
+ */
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000
+#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000
+
+#define TCD_STALLS_DEBUG_MASK \
+     (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_incoming_rtr_MASK)
+
+#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \
+     ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \
+      (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \
+      (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \
+      (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \
+      (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \
+      (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT))
+
+#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int                                : 10;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+     } tcd_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int                                : 10;
+     } tcd_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_stalls_debug_t f;
+} tcd_stalls_debug_u;
+
+
+/*
+ * TCO_STALLS_DEBUG struct
+ */
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080
+
+#define TCO_STALLS_DEBUG_MASK \
+     (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK)
+
+#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \
+     ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \
+      (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \
+      (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT))
+
+#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 5;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int                                : 24;
+     } tco_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 24;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int                                : 5;
+     } tco_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_stalls_debug_t f;
+} tco_stalls_debug_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG0 struct
+ */
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1
+#define TCO_QUAD0_DEBUG0_busy_SIZE     1
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16
+#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29
+#define TCO_QUAD0_DEBUG0_busy_SHIFT    30
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000
+#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000
+#define TCO_QUAD0_DEBUG0_busy_MASK     0x40000000
+
+#define TCO_QUAD0_DEBUG0_MASK \
+     (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \
+      TCO_QUAD0_DEBUG0_read_cache_q_MASK | \
+      TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \
+      TCO_QUAD0_DEBUG0_busy_MASK)
+
+#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \
+     ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \
+      (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \
+      (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \
+      (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \
+      (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \
+      (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \
+      (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \
+      (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \
+      (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \
+      (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \
+      (busy << TCO_QUAD0_DEBUG0_busy_SHIFT))
+
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int                                : 2;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int                                : 1;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 2;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+     } tco_quad0_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug0_t f;
+} tco_quad0_debug0_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG1 struct
+ */
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_empty_SIZE    1
+#define TCO_QUAD0_DEBUG1_full_SIZE     1
+#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0
+#define TCO_QUAD0_DEBUG1_empty_SHIFT   1
+#define TCO_QUAD0_DEBUG1_full_SHIFT    2
+#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001
+#define TCO_QUAD0_DEBUG1_empty_MASK    0x00000002
+#define TCO_QUAD0_DEBUG1_full_MASK     0x00000004
+#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800
+#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000
+#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000
+
+#define TCO_QUAD0_DEBUG1_MASK \
+     (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_empty_MASK | \
+      TCO_QUAD0_DEBUG1_full_MASK | \
+      TCO_QUAD0_DEBUG1_write_enable_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \
+      TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \
+      TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK)
+
+#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \
+     ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \
+      (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \
+      (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \
+      (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \
+      (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \
+      (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \
+      (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \
+      (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \
+      (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \
+      (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \
+      (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \
+      (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \
+      (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT))
+
+#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int                                : 2;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int                                : 1;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int                                : 2;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+     } tco_quad0_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug1_t f;
+} tco_quad0_debug1_u;
+
+
+#endif
+
+
+#if !defined (_TC_FIDDLE_H)
+#define _TC_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_SC_FIDDLE_H)
+#define _SC_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_BC_FIDDLE_H)
+#define _BC_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * RB_SURFACE_INFO struct
+ */
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff
+#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000
+
+#define RB_SURFACE_INFO_MASK \
+     (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \
+      RB_SURFACE_INFO_MSAA_SAMPLES_MASK)
+
+#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \
+     ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \
+      (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT))
+
+#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int                                : 16;
+     } rb_surface_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int                                : 16;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+     } rb_surface_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_surface_info_t f;
+} rb_surface_info_u;
+
+
+/*
+ * RB_COLOR_INFO struct
+ */
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2
+#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1
+#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2
+#define RB_COLOR_INFO_COLOR_SWAP_SIZE  2
+#define RB_COLOR_INFO_COLOR_BASE_SIZE  20
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4
+#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6
+#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7
+#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9
+#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12
+
+#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030
+#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040
+#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180
+#define RB_COLOR_INFO_COLOR_SWAP_MASK  0x00000600
+#define RB_COLOR_INFO_COLOR_BASE_MASK  0xfffff000
+
+#define RB_COLOR_INFO_MASK \
+     (RB_COLOR_INFO_COLOR_FORMAT_MASK | \
+      RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \
+      RB_COLOR_INFO_COLOR_LINEAR_MASK | \
+      RB_COLOR_INFO_COLOR_ENDIAN_MASK | \
+      RB_COLOR_INFO_COLOR_SWAP_MASK | \
+      RB_COLOR_INFO_COLOR_BASE_MASK)
+
+#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \
+     ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \
+      (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \
+      (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \
+      (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \
+      (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \
+      (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT))
+
+#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+     } rb_color_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+     } rb_color_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_info_t f;
+} rb_color_info_u;
+
+
+/*
+ * RB_DEPTH_INFO struct
+ */
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1
+#define RB_DEPTH_INFO_DEPTH_BASE_SIZE  20
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0
+#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001
+#define RB_DEPTH_INFO_DEPTH_BASE_MASK  0xfffff000
+
+#define RB_DEPTH_INFO_MASK \
+     (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \
+      RB_DEPTH_INFO_DEPTH_BASE_MASK)
+
+#define RB_DEPTH_INFO(depth_format, depth_base) \
+     ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \
+      (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT))
+
+#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+     } rb_depth_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+     } rb_depth_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_info_t f;
+} rb_depth_info_u;
+
+
+/*
+ * RB_STENCILREFMASK struct
+ */
+
+#define RB_STENCILREFMASK_STENCILREF_SIZE 8
+#define RB_STENCILREFMASK_STENCILMASK_SIZE 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8
+#define RB_STENCILREFMASK_RESERVED0_SIZE 1
+#define RB_STENCILREFMASK_RESERVED1_SIZE 1
+
+#define RB_STENCILREFMASK_STENCILREF_SHIFT 0
+#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
+#define RB_STENCILREFMASK_RESERVED0_SHIFT 24
+#define RB_STENCILREFMASK_RESERVED1_SHIFT 25
+
+#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
+#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
+#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000
+#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000
+#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000
+
+#define RB_STENCILREFMASK_MASK \
+     (RB_STENCILREFMASK_STENCILREF_MASK | \
+      RB_STENCILREFMASK_STENCILMASK_MASK | \
+      RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \
+      RB_STENCILREFMASK_RESERVED0_MASK | \
+      RB_STENCILREFMASK_RESERVED1_MASK)
+
+#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \
+     ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \
+      (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \
+      (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \
+      (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \
+      (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT))
+
+#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int                                : 6;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+     } rb_stencilrefmask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_t f;
+} rb_stencilrefmask_u;
+
+
+/*
+ * RB_ALPHA_REF struct
+ */
+
+#define RB_ALPHA_REF_ALPHA_REF_SIZE    32
+
+#define RB_ALPHA_REF_ALPHA_REF_SHIFT   0
+
+#define RB_ALPHA_REF_ALPHA_REF_MASK    0xffffffff
+
+#define RB_ALPHA_REF_MASK \
+     (RB_ALPHA_REF_ALPHA_REF_MASK)
+
+#define RB_ALPHA_REF(alpha_ref) \
+     ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT))
+
+#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \
+     ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \
+     rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_alpha_ref_t f;
+} rb_alpha_ref_u;
+
+
+/*
+ * RB_COLOR_MASK struct
+ */
+
+#define RB_COLOR_MASK_WRITE_RED_SIZE   1
+#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1
+#define RB_COLOR_MASK_WRITE_BLUE_SIZE  1
+#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1
+#define RB_COLOR_MASK_RESERVED2_SIZE   1
+#define RB_COLOR_MASK_RESERVED3_SIZE   1
+
+#define RB_COLOR_MASK_WRITE_RED_SHIFT  0
+#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1
+#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2
+#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3
+#define RB_COLOR_MASK_RESERVED2_SHIFT  4
+#define RB_COLOR_MASK_RESERVED3_SHIFT  5
+
+#define RB_COLOR_MASK_WRITE_RED_MASK   0x00000001
+#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002
+#define RB_COLOR_MASK_WRITE_BLUE_MASK  0x00000004
+#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008
+#define RB_COLOR_MASK_RESERVED2_MASK   0x00000010
+#define RB_COLOR_MASK_RESERVED3_MASK   0x00000020
+
+#define RB_COLOR_MASK_MASK \
+     (RB_COLOR_MASK_WRITE_RED_MASK | \
+      RB_COLOR_MASK_WRITE_GREEN_MASK | \
+      RB_COLOR_MASK_WRITE_BLUE_MASK | \
+      RB_COLOR_MASK_WRITE_ALPHA_MASK | \
+      RB_COLOR_MASK_RESERVED2_MASK | \
+      RB_COLOR_MASK_RESERVED3_MASK)
+
+#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \
+     ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \
+      (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \
+      (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \
+      (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \
+      (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \
+      (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT))
+
+#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int                                : 26;
+     } rb_color_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int                                : 26;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+     } rb_color_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_mask_t f;
+} rb_color_mask_u;
+
+
+/*
+ * RB_BLEND_RED struct
+ */
+
+#define RB_BLEND_RED_BLEND_RED_SIZE    8
+
+#define RB_BLEND_RED_BLEND_RED_SHIFT   0
+
+#define RB_BLEND_RED_BLEND_RED_MASK    0x000000ff
+
+#define RB_BLEND_RED_MASK \
+     (RB_BLEND_RED_BLEND_RED_MASK)
+
+#define RB_BLEND_RED(blend_red) \
+     ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT))
+
+#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \
+     ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \
+     rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_red_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int                                : 24;
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+     } rb_blend_red_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_red_t f;
+} rb_blend_red_u;
+
+
+/*
+ * RB_BLEND_GREEN struct
+ */
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0
+
+#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff
+
+#define RB_BLEND_GREEN_MASK \
+     (RB_BLEND_GREEN_BLEND_GREEN_MASK)
+
+#define RB_BLEND_GREEN(blend_green) \
+     ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT))
+
+#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \
+     ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \
+     rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_green_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int                                : 24;
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+     } rb_blend_green_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_green_t f;
+} rb_blend_green_u;
+
+
+/*
+ * RB_BLEND_BLUE struct
+ */
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SIZE  8
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0
+
+#define RB_BLEND_BLUE_BLEND_BLUE_MASK  0x000000ff
+
+#define RB_BLEND_BLUE_MASK \
+     (RB_BLEND_BLUE_BLEND_BLUE_MASK)
+
+#define RB_BLEND_BLUE(blend_blue) \
+     ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT))
+
+#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \
+     ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \
+     rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_blue_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int                                : 24;
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+     } rb_blend_blue_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_blue_t f;
+} rb_blend_blue_u;
+
+
+/*
+ * RB_BLEND_ALPHA struct
+ */
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff
+
+#define RB_BLEND_ALPHA_MASK \
+     (RB_BLEND_ALPHA_BLEND_ALPHA_MASK)
+
+#define RB_BLEND_ALPHA(blend_alpha) \
+     ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT))
+
+#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \
+     ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \
+     rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_alpha_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int                                : 24;
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+     } rb_blend_alpha_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_alpha_t f;
+} rb_blend_alpha_u;
+
+
+/*
+ * RB_FOG_COLOR struct
+ */
+
+#define RB_FOG_COLOR_FOG_RED_SIZE      8
+#define RB_FOG_COLOR_FOG_GREEN_SIZE    8
+#define RB_FOG_COLOR_FOG_BLUE_SIZE     8
+
+#define RB_FOG_COLOR_FOG_RED_SHIFT     0
+#define RB_FOG_COLOR_FOG_GREEN_SHIFT   8
+#define RB_FOG_COLOR_FOG_BLUE_SHIFT    16
+
+#define RB_FOG_COLOR_FOG_RED_MASK      0x000000ff
+#define RB_FOG_COLOR_FOG_GREEN_MASK    0x0000ff00
+#define RB_FOG_COLOR_FOG_BLUE_MASK     0x00ff0000
+
+#define RB_FOG_COLOR_MASK \
+     (RB_FOG_COLOR_FOG_RED_MASK | \
+      RB_FOG_COLOR_FOG_GREEN_MASK | \
+      RB_FOG_COLOR_FOG_BLUE_MASK)
+
+#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \
+     ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \
+      (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \
+      (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT))
+
+#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int                                : 8;
+     } rb_fog_color_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int                                : 8;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+     } rb_fog_color_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_fog_color_t f;
+} rb_fog_color_u;
+
+
+/*
+ * RB_STENCILREFMASK_BF struct
+ */
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1
+#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16
+#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24
+#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000
+#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000
+#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000
+
+#define RB_STENCILREFMASK_BF_MASK \
+     (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED4_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED5_MASK)
+
+#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \
+     ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \
+      (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \
+      (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \
+      (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \
+      (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT))
+
+#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_bf_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int                                : 6;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+     } rb_stencilrefmask_bf_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_bf_t f;
+} rb_stencilrefmask_bf_u;
+
+
+/*
+ * RB_DEPTHCONTROL struct
+ */
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_Z_ENABLE_SIZE  1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_ZFUNC_SIZE     3
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0
+#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3
+#define RB_DEPTHCONTROL_ZFUNC_SHIFT    4
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7
+#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8
+#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11
+#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14
+#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001
+#define RB_DEPTHCONTROL_Z_ENABLE_MASK  0x00000002
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008
+#define RB_DEPTHCONTROL_ZFUNC_MASK     0x00000070
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080
+#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700
+#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800
+#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000
+#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000
+
+#define RB_DEPTHCONTROL_MASK \
+     (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_ZFUNC_MASK | \
+      RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK)
+
+#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \
+     ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \
+      (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \
+      (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \
+      (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \
+      (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \
+      (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \
+      (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \
+      (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \
+      (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \
+      (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \
+      (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \
+      (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \
+      (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \
+      (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT))
+
+#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+     } rb_depthcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+     } rb_depthcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depthcontrol_t f;
+} rb_depthcontrol_u;
+
+
+/*
+ * RB_BLENDCONTROL struct
+ */
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1
+#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29
+#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000
+#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000
+
+#define RB_BLENDCONTROL_MASK \
+     (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_MASK)
+
+#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \
+     ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \
+      (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \
+      (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \
+      (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \
+      (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \
+      (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \
+      (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \
+      (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT))
+
+#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int                                : 1;
+     } rb_blendcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int                                : 1;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+     } rb_blendcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blendcontrol_t f;
+} rb_blendcontrol_u;
+
+
+/*
+ * RB_COLORCONTROL struct
+ */
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1
+#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1
+#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1
+#define RB_COLORCONTROL_ROP_CODE_SIZE  4
+#define RB_COLORCONTROL_DITHER_MODE_SIZE 2
+#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2
+#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4
+#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5
+#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7
+#define RB_COLORCONTROL_ROP_CODE_SHIFT 8
+#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12
+#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14
+#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30
+
+#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010
+#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020
+#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080
+#define RB_COLORCONTROL_ROP_CODE_MASK  0x00000f00
+#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000
+#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000
+#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000
+
+#define RB_COLORCONTROL_MASK \
+     (RB_COLORCONTROL_ALPHA_FUNC_MASK | \
+      RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \
+      RB_COLORCONTROL_BLEND_DISABLE_MASK | \
+      RB_COLORCONTROL_FOG_ENABLE_MASK | \
+      RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \
+      RB_COLORCONTROL_ROP_CODE_MASK | \
+      RB_COLORCONTROL_DITHER_MODE_MASK | \
+      RB_COLORCONTROL_DITHER_TYPE_MASK | \
+      RB_COLORCONTROL_PIXEL_FOG_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK)
+
+#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \
+     ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \
+      (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \
+      (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \
+      (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \
+      (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \
+      (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \
+      (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \
+      (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \
+      (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \
+      (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \
+      (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \
+      (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \
+      (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \
+      (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT))
+
+#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int                                : 7;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+     } rb_colorcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int                                : 7;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+     } rb_colorcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_colorcontrol_t f;
+} rb_colorcontrol_u;
+
+
+/*
+ * RB_MODECONTROL struct
+ */
+
+#define RB_MODECONTROL_EDRAM_MODE_SIZE 3
+
+#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0
+
+#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007
+
+#define RB_MODECONTROL_MASK \
+     (RB_MODECONTROL_EDRAM_MODE_MASK)
+
+#define RB_MODECONTROL(edram_mode) \
+     ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT))
+
+#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \
+     ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \
+     rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+          unsigned int                                : 29;
+     } rb_modecontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int                                : 29;
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+     } rb_modecontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_modecontrol_t f;
+} rb_modecontrol_u;
+
+
+/*
+ * RB_COLOR_DEST_MASK struct
+ */
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff
+
+#define RB_COLOR_DEST_MASK_MASK \
+     (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK)
+
+#define RB_COLOR_DEST_MASK(color_dest_mask) \
+     ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT))
+
+#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \
+     ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \
+     rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_dest_mask_t f;
+} rb_color_dest_mask_u;
+
+
+/*
+ * RB_COPY_CONTROL struct
+ */
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1
+#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3
+#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008
+#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0
+
+#define RB_COPY_CONTROL_MASK \
+     (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \
+      RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \
+      RB_COPY_CONTROL_CLEAR_MASK_MASK)
+
+#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \
+     ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \
+      (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \
+      (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT))
+
+#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int                                : 24;
+     } rb_copy_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int                                : 24;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+     } rb_copy_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_control_t f;
+} rb_copy_control_u;
+
+
+/*
+ * RB_COPY_DEST_BASE struct
+ */
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000
+
+#define RB_COPY_DEST_BASE_MASK \
+     (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK)
+
+#define RB_COPY_DEST_BASE(copy_dest_base) \
+     ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT))
+
+#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \
+     ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \
+     rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int                                : 12;
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+     } rb_copy_dest_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+          unsigned int                                : 12;
+     } rb_copy_dest_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_base_t f;
+} rb_copy_dest_base_u;
+
+
+/*
+ * RB_COPY_DEST_PITCH struct
+ */
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff
+
+#define RB_COPY_DEST_PITCH_MASK \
+     (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK)
+
+#define RB_COPY_DEST_PITCH(copy_dest_pitch) \
+     ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT))
+
+#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \
+     ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \
+     rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+          unsigned int                                : 23;
+     } rb_copy_dest_pitch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int                                : 23;
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+     } rb_copy_dest_pitch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pitch_t f;
+} rb_copy_dest_pitch_u;
+
+
+/*
+ * RB_COPY_DEST_INFO struct
+ */
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000
+
+#define RB_COPY_DEST_INFO_MASK \
+     (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \
+     ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \
+      (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \
+      (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \
+      (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \
+      (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \
+      (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \
+      (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \
+      (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \
+      (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \
+      (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 14;
+     } rb_copy_dest_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int                                : 14;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+     } rb_copy_dest_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_info_t f;
+} rb_copy_dest_info_u;
+
+
+/*
+ * RB_COPY_DEST_PIXEL_OFFSET struct
+ */
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000
+
+#define RB_COPY_DEST_PIXEL_OFFSET_MASK \
+     (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \
+      RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK)
+
+#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \
+     ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \
+      (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT))
+
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int                                : 6;
+     } rb_copy_dest_pixel_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int                                : 6;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+     } rb_copy_dest_pixel_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pixel_offset_t f;
+} rb_copy_dest_pixel_offset_u;
+
+
+/*
+ * RB_DEPTH_CLEAR struct
+ */
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff
+
+#define RB_DEPTH_CLEAR_MASK \
+     (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK)
+
+#define RB_DEPTH_CLEAR(depth_clear) \
+     ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT))
+
+#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \
+     ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \
+     rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_clear_t f;
+} rb_depth_clear_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_CTL struct
+ */
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002
+
+#define RB_SAMPLE_COUNT_CTL_MASK \
+     (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \
+      RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK)
+
+#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \
+     ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \
+      (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT))
+
+#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int                                : 30;
+     } rb_sample_count_ctl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int                                : 30;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+     } rb_sample_count_ctl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_ctl_t f;
+} rb_sample_count_ctl_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_ADDR struct
+ */
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff
+
+#define RB_SAMPLE_COUNT_ADDR_MASK \
+     (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK)
+
+#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \
+     ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT))
+
+#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \
+     ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \
+     rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_addr_t f;
+} rb_sample_count_addr_u;
+
+
+/*
+ * RB_BC_CONTROL struct
+ */
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1
+#define RB_BC_CONTROL_CRC_MODE_SIZE    1
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1
+#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_CRC_SYSTEM_SIZE  1
+#define RB_BC_CONTROL_RESERVED6_SIZE   1
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14
+#define RB_BC_CONTROL_CRC_MODE_SHIFT   15
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16
+#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29
+#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30
+#define RB_BC_CONTROL_RESERVED6_SHIFT  31
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000
+#define RB_BC_CONTROL_CRC_MODE_MASK    0x00008000
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000
+#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000
+#define RB_BC_CONTROL_CRC_SYSTEM_MASK  0x40000000
+#define RB_BC_CONTROL_RESERVED6_MASK   0x80000000
+
+#define RB_BC_CONTROL_MASK \
+     (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \
+      RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \
+      RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \
+      RB_BC_CONTROL_CRC_MODE_MASK | \
+      RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \
+      RB_BC_CONTROL_DISABLE_ACCUM_MASK | \
+      RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \
+      RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_CRC_SYSTEM_MASK | \
+      RB_BC_CONTROL_RESERVED6_MASK)
+
+#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \
+     ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \
+      (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \
+      (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \
+      (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \
+      (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \
+      (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \
+      (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \
+      (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \
+      (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \
+      (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \
+      (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \
+      (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \
+      (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \
+      (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \
+      (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \
+      (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \
+      (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \
+      (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \
+      (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT))
+
+#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int                                : 1;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+     } rb_bc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+     } rb_bc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_control_t f;
+} rb_bc_control_u;
+
+
+/*
+ * RB_EDRAM_INFO struct
+ */
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE  4
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
+#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4
+#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_MASK  0x0000000f
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030
+#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000
+
+#define RB_EDRAM_INFO_MASK \
+     (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \
+      RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \
+      RB_EDRAM_INFO_EDRAM_RANGE_MASK)
+
+#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \
+     ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \
+      (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \
+      (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT))
+
+#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+     } rb_edram_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+     } rb_edram_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_edram_info_t f;
+} rb_edram_info_u;
+
+
+/*
+ * RB_CRC_RD_PORT struct
+ */
+
+#define RB_CRC_RD_PORT_CRC_DATA_SIZE   32
+
+#define RB_CRC_RD_PORT_CRC_DATA_SHIFT  0
+
+#define RB_CRC_RD_PORT_CRC_DATA_MASK   0xffffffff
+
+#define RB_CRC_RD_PORT_MASK \
+     (RB_CRC_RD_PORT_CRC_DATA_MASK)
+
+#define RB_CRC_RD_PORT(crc_data) \
+     ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT))
+
+#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \
+     ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \
+     rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_rd_port_t f;
+} rb_crc_rd_port_u;
+
+
+/*
+ * RB_CRC_CONTROL struct
+ */
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001
+
+#define RB_CRC_CONTROL_MASK \
+     (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK)
+
+#define RB_CRC_CONTROL(crc_rd_advance) \
+     ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT))
+
+#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \
+     ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \
+     rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+          unsigned int                                : 31;
+     } rb_crc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int                                : 31;
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+     } rb_crc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_control_t f;
+} rb_crc_control_u;
+
+
+/*
+ * RB_CRC_MASK struct
+ */
+
+#define RB_CRC_MASK_CRC_MASK_SIZE      32
+
+#define RB_CRC_MASK_CRC_MASK_SHIFT     0
+
+#define RB_CRC_MASK_CRC_MASK_MASK      0xffffffff
+
+#define RB_CRC_MASK_MASK \
+     (RB_CRC_MASK_CRC_MASK_MASK)
+
+#define RB_CRC_MASK(crc_mask) \
+     ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT))
+
+#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \
+     ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \
+     rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_mask_t f;
+} rb_crc_mask_u;
+
+
+/*
+ * RB_PERFCOUNTER0_SELECT struct
+ */
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define RB_PERFCOUNTER0_SELECT_MASK \
+     (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define RB_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \
+     ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \
+     rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } rb_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } rb_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_select_t f;
+} rb_perfcounter0_select_u;
+
+
+/*
+ * RB_PERFCOUNTER0_LOW struct
+ */
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define RB_PERFCOUNTER0_LOW_MASK \
+     (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \
+     ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \
+     rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_low_t f;
+} rb_perfcounter0_low_u;
+
+
+/*
+ * RB_PERFCOUNTER0_HI struct
+ */
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define RB_PERFCOUNTER0_HI_MASK \
+     (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \
+     ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \
+     rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } rb_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } rb_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_hi_t f;
+} rb_perfcounter0_hi_u;
+
+
+/*
+ * RB_TOTAL_SAMPLES struct
+ */
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff
+
+#define RB_TOTAL_SAMPLES_MASK \
+     (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK)
+
+#define RB_TOTAL_SAMPLES(total_samples) \
+     ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT))
+
+#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \
+     ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \
+     rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_total_samples_t f;
+} rb_total_samples_u;
+
+
+/*
+ * RB_ZPASS_SAMPLES struct
+ */
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff
+
+#define RB_ZPASS_SAMPLES_MASK \
+     (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK)
+
+#define RB_ZPASS_SAMPLES(zpass_samples) \
+     ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT))
+
+#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \
+     ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \
+     rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zpass_samples_t f;
+} rb_zpass_samples_u;
+
+
+/*
+ * RB_ZFAIL_SAMPLES struct
+ */
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_ZFAIL_SAMPLES_MASK \
+     (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK)
+
+#define RB_ZFAIL_SAMPLES(zfail_samples) \
+     ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT))
+
+#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \
+     ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \
+     rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zfail_samples_t f;
+} rb_zfail_samples_u;
+
+
+/*
+ * RB_SFAIL_SAMPLES struct
+ */
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_SFAIL_SAMPLES_MASK \
+     (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK)
+
+#define RB_SFAIL_SAMPLES(sfail_samples) \
+     ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT))
+
+#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \
+     ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \
+     rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sfail_samples_t f;
+} rb_sfail_samples_u;
+
+
+/*
+ * RB_DEBUG_0 struct
+ */
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE  1
+#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE  1
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1
+#define RB_DEBUG_0_C_REQ_FULL_SIZE     1
+#define RB_DEBUG_0_C_MASK_FULL_SIZE    1
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7
+#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8
+#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17
+#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18
+#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25
+#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26
+#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28
+#define RB_DEBUG_0_C_REQ_FULL_SHIFT    29
+#define RB_DEBUG_0_C_MASK_FULL_SHIFT   30
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020
+#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK  0x00000040
+#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK  0x00000080
+#define RB_DEBUG_0_RDREQ_C1_FULL_MASK  0x00000100
+#define RB_DEBUG_0_RDREQ_C0_FULL_MASK  0x00000200
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000
+#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK  0x00010000
+#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK  0x00020000
+#define RB_DEBUG_0_WRREQ_C1_FULL_MASK  0x00040000
+#define RB_DEBUG_0_WRREQ_C0_FULL_MASK  0x00080000
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000
+#define RB_DEBUG_0_C_SX_LAT_FULL_MASK  0x04000000
+#define RB_DEBUG_0_C_SX_CMD_FULL_MASK  0x08000000
+#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000
+#define RB_DEBUG_0_C_REQ_FULL_MASK     0x20000000
+#define RB_DEBUG_0_C_MASK_FULL_MASK    0x40000000
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000
+
+#define RB_DEBUG_0_MASK \
+     (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_C_SX_LAT_FULL_MASK | \
+      RB_DEBUG_0_C_SX_CMD_FULL_MASK | \
+      RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \
+      RB_DEBUG_0_C_REQ_FULL_MASK | \
+      RB_DEBUG_0_C_MASK_FULL_MASK | \
+      RB_DEBUG_0_EZ_INFSAMP_FULL_MASK)
+
+#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \
+     ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \
+      (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \
+      (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \
+      (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \
+      (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \
+      (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \
+      (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \
+      (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \
+      (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \
+      (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \
+      (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \
+      (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \
+      (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \
+      (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \
+      (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \
+      (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \
+      (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \
+      (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \
+      (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \
+      (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \
+      (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT))
+
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+     } rb_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+     } rb_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_0_t f;
+} rb_debug_0_u;
+
+
+/*
+ * RB_DEBUG_1 struct
+ */
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_REQ_EMPTY_SIZE    1
+#define RB_DEBUG_1_C_MASK_EMPTY_SIZE   1
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28
+#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT   29
+#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT  30
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000
+#define RB_DEBUG_1_C_REQ_EMPTY_MASK    0x20000000
+#define RB_DEBUG_1_C_MASK_EMPTY_MASK   0x40000000
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000
+
+#define RB_DEBUG_1_MASK \
+     (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \
+      RB_DEBUG_1_C_REQ_EMPTY_MASK | \
+      RB_DEBUG_1_C_MASK_EMPTY_MASK | \
+      RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK)
+
+#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \
+     ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \
+      (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \
+      (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \
+      (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \
+      (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \
+      (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \
+      (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \
+      (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \
+      (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \
+      (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \
+      (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \
+      (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \
+      (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \
+      (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \
+      (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \
+      (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \
+      (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \
+      (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \
+      (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \
+      (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \
+      (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT))
+
+#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_1_t f;
+} rb_debug_1_u;
+
+
+/*
+ * RB_DEBUG_2 struct
+ */
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z1_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z0_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z1_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z_SAMP_FULL_SIZE    1
+#define RB_DEBUG_2_Z_TILE_FULL_SIZE    1
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE   1
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16
+#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT  17
+#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT  18
+#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT   19
+#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT   20
+#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT   21
+#define RB_DEBUG_2_Z_TILE_FULL_SHIFT   22
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT  28
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT  29
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT  30
+#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT  31
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000
+#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000
+#define RB_DEBUG_2_Z0_MASK_FULL_MASK   0x00020000
+#define RB_DEBUG_2_Z1_MASK_FULL_MASK   0x00040000
+#define RB_DEBUG_2_Z0_REQ_FULL_MASK    0x00080000
+#define RB_DEBUG_2_Z1_REQ_FULL_MASK    0x00100000
+#define RB_DEBUG_2_Z_SAMP_FULL_MASK    0x00200000
+#define RB_DEBUG_2_Z_TILE_FULL_MASK    0x00400000
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK  0x04000000
+#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK  0x08000000
+#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK   0x10000000
+#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK   0x20000000
+#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK   0x40000000
+#define RB_DEBUG_2_Z_TILE_EMPTY_MASK   0x80000000
+
+#define RB_DEBUG_2_MASK \
+     (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \
+      RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \
+      RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \
+      RB_DEBUG_2_Z0_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z1_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z0_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z1_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z_SAMP_FULL_MASK | \
+      RB_DEBUG_2_Z_TILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \
+      RB_DEBUG_2_Z_TILE_EMPTY_MASK)
+
+#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \
+     ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \
+      (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \
+      (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \
+      (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \
+      (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \
+      (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \
+      (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \
+      (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \
+      (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \
+      (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \
+      (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \
+      (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \
+      (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \
+      (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \
+      (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \
+      (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \
+      (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \
+      (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \
+      (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \
+      (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \
+      (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \
+      (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \
+      (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT))
+
+#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+     } rb_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+     } rb_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_2_t f;
+} rb_debug_2_u;
+
+
+/*
+ * RB_DEBUG_3 struct
+ */
+
+#define RB_DEBUG_3_ACCUM_VALID_SIZE    4
+#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4
+#define RB_DEBUG_3_SHD_FULL_SIZE       1
+#define RB_DEBUG_3_SHD_EMPTY_SIZE      1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1
+
+#define RB_DEBUG_3_ACCUM_VALID_SHIFT   0
+#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15
+#define RB_DEBUG_3_SHD_FULL_SHIFT      19
+#define RB_DEBUG_3_SHD_EMPTY_SHIFT     20
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28
+
+#define RB_DEBUG_3_ACCUM_VALID_MASK    0x0000000f
+#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000
+#define RB_DEBUG_3_SHD_FULL_MASK       0x00080000
+#define RB_DEBUG_3_SHD_EMPTY_MASK      0x00100000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000
+
+#define RB_DEBUG_3_MASK \
+     (RB_DEBUG_3_ACCUM_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_FLUSHING_MASK | \
+      RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \
+      RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \
+      RB_DEBUG_3_SHD_FULL_MASK | \
+      RB_DEBUG_3_SHD_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_FULL_MASK)
+
+#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \
+     ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \
+      (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \
+      (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \
+      (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \
+      (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \
+      (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \
+      (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \
+      (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \
+      (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \
+      (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \
+      (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \
+      (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \
+      (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \
+      (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \
+      (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT))
+
+#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int                                : 3;
+     } rb_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int                                : 3;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+     } rb_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_3_t f;
+} rb_debug_3_u;
+
+
+/*
+ * RB_DEBUG_4 struct
+ */
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00
+
+#define RB_DEBUG_4_MASK \
+     (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \
+      RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \
+      RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK)
+
+#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \
+     ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \
+      (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \
+      (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \
+      (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \
+      (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \
+      (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT))
+
+#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int                                : 19;
+     } rb_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int                                : 19;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+     } rb_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_4_t f;
+} rb_debug_4_u;
+
+
+/*
+ * RB_FLAG_CONTROL struct
+ */
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001
+
+#define RB_FLAG_CONTROL_MASK \
+     (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK)
+
+#define RB_FLAG_CONTROL(debug_flag_clear) \
+     ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT))
+
+#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \
+     ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \
+     rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+          unsigned int                                : 31;
+     } rb_flag_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int                                : 31;
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+     } rb_flag_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_flag_control_t f;
+} rb_flag_control_u;
+
+
+/*
+ * RB_BC_SPARES struct
+ */
+
+#define RB_BC_SPARES_RESERVED_SIZE     32
+
+#define RB_BC_SPARES_RESERVED_SHIFT    0
+
+#define RB_BC_SPARES_RESERVED_MASK     0xffffffff
+
+#define RB_BC_SPARES_MASK \
+     (RB_BC_SPARES_RESERVED_MASK)
+
+#define RB_BC_SPARES(reserved) \
+     ((reserved << RB_BC_SPARES_RESERVED_SHIFT))
+
+#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \
+     ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT)
+
+#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \
+     rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_spares_t f;
+} rb_bc_spares_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_ENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000
+
+#define BC_DUMMY_CRAYRB_ENUMS_MASK \
+     (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK)
+
+#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \
+     ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \
+      (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \
+      (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \
+      (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \
+      (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \
+      (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \
+      (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT))
+
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_enums_t f;
+} bc_dummy_crayrb_enums_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_MOREENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \
+     (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \
+     ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT))
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \
+     ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \
+     bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+          unsigned int                                : 30;
+     } bc_dummy_crayrb_moreenums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int                                : 30;
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+     } bc_dummy_crayrb_moreenums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_moreenums_t f;
+} bc_dummy_crayrb_moreenums_u;
+
+
+#endif
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h
new file mode 100644
index 00000000000..6968abb48bd
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h
@@ -0,0 +1,550 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_TYPEDEF_HEADER)
+#define _yamato_TYPEDEF_HEADER
+
+#include "yamato_registers.h"
+
+typedef union PA_CL_VPORT_XSCALE                regPA_CL_VPORT_XSCALE;
+typedef union PA_CL_VPORT_XOFFSET               regPA_CL_VPORT_XOFFSET;
+typedef union PA_CL_VPORT_YSCALE                regPA_CL_VPORT_YSCALE;
+typedef union PA_CL_VPORT_YOFFSET               regPA_CL_VPORT_YOFFSET;
+typedef union PA_CL_VPORT_ZSCALE                regPA_CL_VPORT_ZSCALE;
+typedef union PA_CL_VPORT_ZOFFSET               regPA_CL_VPORT_ZOFFSET;
+typedef union PA_CL_VTE_CNTL                    regPA_CL_VTE_CNTL;
+typedef union PA_CL_CLIP_CNTL                   regPA_CL_CLIP_CNTL;
+typedef union PA_CL_GB_VERT_CLIP_ADJ            regPA_CL_GB_VERT_CLIP_ADJ;
+typedef union PA_CL_GB_VERT_DISC_ADJ            regPA_CL_GB_VERT_DISC_ADJ;
+typedef union PA_CL_GB_HORZ_CLIP_ADJ            regPA_CL_GB_HORZ_CLIP_ADJ;
+typedef union PA_CL_GB_HORZ_DISC_ADJ            regPA_CL_GB_HORZ_DISC_ADJ;
+typedef union PA_CL_ENHANCE                     regPA_CL_ENHANCE;
+typedef union PA_SC_ENHANCE                     regPA_SC_ENHANCE;
+typedef union PA_SU_VTX_CNTL                    regPA_SU_VTX_CNTL;
+typedef union PA_SU_POINT_SIZE                  regPA_SU_POINT_SIZE;
+typedef union PA_SU_POINT_MINMAX                regPA_SU_POINT_MINMAX;
+typedef union PA_SU_LINE_CNTL                   regPA_SU_LINE_CNTL;
+typedef union PA_SU_FACE_DATA                   regPA_SU_FACE_DATA;
+typedef union PA_SU_SC_MODE_CNTL                regPA_SU_SC_MODE_CNTL;
+typedef union PA_SU_POLY_OFFSET_FRONT_SCALE     regPA_SU_POLY_OFFSET_FRONT_SCALE;
+typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET    regPA_SU_POLY_OFFSET_FRONT_OFFSET;
+typedef union PA_SU_POLY_OFFSET_BACK_SCALE      regPA_SU_POLY_OFFSET_BACK_SCALE;
+typedef union PA_SU_POLY_OFFSET_BACK_OFFSET     regPA_SU_POLY_OFFSET_BACK_OFFSET;
+typedef union PA_SU_PERFCOUNTER0_SELECT         regPA_SU_PERFCOUNTER0_SELECT;
+typedef union PA_SU_PERFCOUNTER1_SELECT         regPA_SU_PERFCOUNTER1_SELECT;
+typedef union PA_SU_PERFCOUNTER2_SELECT         regPA_SU_PERFCOUNTER2_SELECT;
+typedef union PA_SU_PERFCOUNTER3_SELECT         regPA_SU_PERFCOUNTER3_SELECT;
+typedef union PA_SU_PERFCOUNTER0_LOW            regPA_SU_PERFCOUNTER0_LOW;
+typedef union PA_SU_PERFCOUNTER0_HI             regPA_SU_PERFCOUNTER0_HI;
+typedef union PA_SU_PERFCOUNTER1_LOW            regPA_SU_PERFCOUNTER1_LOW;
+typedef union PA_SU_PERFCOUNTER1_HI             regPA_SU_PERFCOUNTER1_HI;
+typedef union PA_SU_PERFCOUNTER2_LOW            regPA_SU_PERFCOUNTER2_LOW;
+typedef union PA_SU_PERFCOUNTER2_HI             regPA_SU_PERFCOUNTER2_HI;
+typedef union PA_SU_PERFCOUNTER3_LOW            regPA_SU_PERFCOUNTER3_LOW;
+typedef union PA_SU_PERFCOUNTER3_HI             regPA_SU_PERFCOUNTER3_HI;
+typedef union PA_SC_WINDOW_OFFSET               regPA_SC_WINDOW_OFFSET;
+typedef union PA_SC_AA_CONFIG                   regPA_SC_AA_CONFIG;
+typedef union PA_SC_AA_MASK                     regPA_SC_AA_MASK;
+typedef union PA_SC_LINE_STIPPLE                regPA_SC_LINE_STIPPLE;
+typedef union PA_SC_LINE_CNTL                   regPA_SC_LINE_CNTL;
+typedef union PA_SC_WINDOW_SCISSOR_TL           regPA_SC_WINDOW_SCISSOR_TL;
+typedef union PA_SC_WINDOW_SCISSOR_BR           regPA_SC_WINDOW_SCISSOR_BR;
+typedef union PA_SC_SCREEN_SCISSOR_TL           regPA_SC_SCREEN_SCISSOR_TL;
+typedef union PA_SC_SCREEN_SCISSOR_BR           regPA_SC_SCREEN_SCISSOR_BR;
+typedef union PA_SC_VIZ_QUERY                   regPA_SC_VIZ_QUERY;
+typedef union PA_SC_VIZ_QUERY_STATUS            regPA_SC_VIZ_QUERY_STATUS;
+typedef union PA_SC_LINE_STIPPLE_STATE          regPA_SC_LINE_STIPPLE_STATE;
+typedef union PA_SC_PERFCOUNTER0_SELECT         regPA_SC_PERFCOUNTER0_SELECT;
+typedef union PA_SC_PERFCOUNTER0_LOW            regPA_SC_PERFCOUNTER0_LOW;
+typedef union PA_SC_PERFCOUNTER0_HI             regPA_SC_PERFCOUNTER0_HI;
+typedef union PA_CL_CNTL_STATUS                 regPA_CL_CNTL_STATUS;
+typedef union PA_SU_CNTL_STATUS                 regPA_SU_CNTL_STATUS;
+typedef union PA_SC_CNTL_STATUS                 regPA_SC_CNTL_STATUS;
+typedef union PA_SU_DEBUG_CNTL                  regPA_SU_DEBUG_CNTL;
+typedef union PA_SU_DEBUG_DATA                  regPA_SU_DEBUG_DATA;
+typedef union PA_SC_DEBUG_CNTL                  regPA_SC_DEBUG_CNTL;
+typedef union PA_SC_DEBUG_DATA                  regPA_SC_DEBUG_DATA;
+typedef union GFX_COPY_STATE                    regGFX_COPY_STATE;
+typedef union VGT_DRAW_INITIATOR                regVGT_DRAW_INITIATOR;
+typedef union VGT_EVENT_INITIATOR               regVGT_EVENT_INITIATOR;
+typedef union VGT_DMA_BASE                      regVGT_DMA_BASE;
+typedef union VGT_DMA_SIZE                      regVGT_DMA_SIZE;
+typedef union VGT_BIN_BASE                      regVGT_BIN_BASE;
+typedef union VGT_BIN_SIZE                      regVGT_BIN_SIZE;
+typedef union VGT_CURRENT_BIN_ID_MIN            regVGT_CURRENT_BIN_ID_MIN;
+typedef union VGT_CURRENT_BIN_ID_MAX            regVGT_CURRENT_BIN_ID_MAX;
+typedef union VGT_IMMED_DATA                    regVGT_IMMED_DATA;
+typedef union VGT_MAX_VTX_INDX                  regVGT_MAX_VTX_INDX;
+typedef union VGT_MIN_VTX_INDX                  regVGT_MIN_VTX_INDX;
+typedef union VGT_INDX_OFFSET                   regVGT_INDX_OFFSET;
+typedef union VGT_VERTEX_REUSE_BLOCK_CNTL       regVGT_VERTEX_REUSE_BLOCK_CNTL;
+typedef union VGT_OUT_DEALLOC_CNTL              regVGT_OUT_DEALLOC_CNTL;
+typedef union VGT_MULTI_PRIM_IB_RESET_INDX      regVGT_MULTI_PRIM_IB_RESET_INDX;
+typedef union VGT_ENHANCE                       regVGT_ENHANCE;
+typedef union VGT_VTX_VECT_EJECT_REG            regVGT_VTX_VECT_EJECT_REG;
+typedef union VGT_LAST_COPY_STATE               regVGT_LAST_COPY_STATE;
+typedef union VGT_DEBUG_CNTL                    regVGT_DEBUG_CNTL;
+typedef union VGT_DEBUG_DATA                    regVGT_DEBUG_DATA;
+typedef union VGT_CNTL_STATUS                   regVGT_CNTL_STATUS;
+typedef union VGT_CRC_SQ_DATA                   regVGT_CRC_SQ_DATA;
+typedef union VGT_CRC_SQ_CTRL                   regVGT_CRC_SQ_CTRL;
+typedef union VGT_PERFCOUNTER0_SELECT           regVGT_PERFCOUNTER0_SELECT;
+typedef union VGT_PERFCOUNTER1_SELECT           regVGT_PERFCOUNTER1_SELECT;
+typedef union VGT_PERFCOUNTER2_SELECT           regVGT_PERFCOUNTER2_SELECT;
+typedef union VGT_PERFCOUNTER3_SELECT           regVGT_PERFCOUNTER3_SELECT;
+typedef union VGT_PERFCOUNTER0_LOW              regVGT_PERFCOUNTER0_LOW;
+typedef union VGT_PERFCOUNTER1_LOW              regVGT_PERFCOUNTER1_LOW;
+typedef union VGT_PERFCOUNTER2_LOW              regVGT_PERFCOUNTER2_LOW;
+typedef union VGT_PERFCOUNTER3_LOW              regVGT_PERFCOUNTER3_LOW;
+typedef union VGT_PERFCOUNTER0_HI               regVGT_PERFCOUNTER0_HI;
+typedef union VGT_PERFCOUNTER1_HI               regVGT_PERFCOUNTER1_HI;
+typedef union VGT_PERFCOUNTER2_HI               regVGT_PERFCOUNTER2_HI;
+typedef union VGT_PERFCOUNTER3_HI               regVGT_PERFCOUNTER3_HI;
+typedef union TC_CNTL_STATUS                    regTC_CNTL_STATUS;
+typedef union TCR_CHICKEN                       regTCR_CHICKEN;
+typedef union TCF_CHICKEN                       regTCF_CHICKEN;
+typedef union TCM_CHICKEN                       regTCM_CHICKEN;
+typedef union TCR_PERFCOUNTER0_SELECT           regTCR_PERFCOUNTER0_SELECT;
+typedef union TCR_PERFCOUNTER1_SELECT           regTCR_PERFCOUNTER1_SELECT;
+typedef union TCR_PERFCOUNTER0_HI               regTCR_PERFCOUNTER0_HI;
+typedef union TCR_PERFCOUNTER1_HI               regTCR_PERFCOUNTER1_HI;
+typedef union TCR_PERFCOUNTER0_LOW              regTCR_PERFCOUNTER0_LOW;
+typedef union TCR_PERFCOUNTER1_LOW              regTCR_PERFCOUNTER1_LOW;
+typedef union TP_TC_CLKGATE_CNTL                regTP_TC_CLKGATE_CNTL;
+typedef union TPC_CNTL_STATUS                   regTPC_CNTL_STATUS;
+typedef union TPC_DEBUG0                        regTPC_DEBUG0;
+typedef union TPC_DEBUG1                        regTPC_DEBUG1;
+typedef union TPC_CHICKEN                       regTPC_CHICKEN;
+typedef union TP0_CNTL_STATUS                   regTP0_CNTL_STATUS;
+typedef union TP0_DEBUG                         regTP0_DEBUG;
+typedef union TP0_CHICKEN                       regTP0_CHICKEN;
+typedef union TP0_PERFCOUNTER0_SELECT           regTP0_PERFCOUNTER0_SELECT;
+typedef union TP0_PERFCOUNTER0_HI               regTP0_PERFCOUNTER0_HI;
+typedef union TP0_PERFCOUNTER0_LOW              regTP0_PERFCOUNTER0_LOW;
+typedef union TP0_PERFCOUNTER1_SELECT           regTP0_PERFCOUNTER1_SELECT;
+typedef union TP0_PERFCOUNTER1_HI               regTP0_PERFCOUNTER1_HI;
+typedef union TP0_PERFCOUNTER1_LOW              regTP0_PERFCOUNTER1_LOW;
+typedef union TCM_PERFCOUNTER0_SELECT           regTCM_PERFCOUNTER0_SELECT;
+typedef union TCM_PERFCOUNTER1_SELECT           regTCM_PERFCOUNTER1_SELECT;
+typedef union TCM_PERFCOUNTER0_HI               regTCM_PERFCOUNTER0_HI;
+typedef union TCM_PERFCOUNTER1_HI               regTCM_PERFCOUNTER1_HI;
+typedef union TCM_PERFCOUNTER0_LOW              regTCM_PERFCOUNTER0_LOW;
+typedef union TCM_PERFCOUNTER1_LOW              regTCM_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER0_SELECT           regTCF_PERFCOUNTER0_SELECT;
+typedef union TCF_PERFCOUNTER1_SELECT           regTCF_PERFCOUNTER1_SELECT;
+typedef union TCF_PERFCOUNTER2_SELECT           regTCF_PERFCOUNTER2_SELECT;
+typedef union TCF_PERFCOUNTER3_SELECT           regTCF_PERFCOUNTER3_SELECT;
+typedef union TCF_PERFCOUNTER4_SELECT           regTCF_PERFCOUNTER4_SELECT;
+typedef union TCF_PERFCOUNTER5_SELECT           regTCF_PERFCOUNTER5_SELECT;
+typedef union TCF_PERFCOUNTER6_SELECT           regTCF_PERFCOUNTER6_SELECT;
+typedef union TCF_PERFCOUNTER7_SELECT           regTCF_PERFCOUNTER7_SELECT;
+typedef union TCF_PERFCOUNTER8_SELECT           regTCF_PERFCOUNTER8_SELECT;
+typedef union TCF_PERFCOUNTER9_SELECT           regTCF_PERFCOUNTER9_SELECT;
+typedef union TCF_PERFCOUNTER10_SELECT          regTCF_PERFCOUNTER10_SELECT;
+typedef union TCF_PERFCOUNTER11_SELECT          regTCF_PERFCOUNTER11_SELECT;
+typedef union TCF_PERFCOUNTER0_HI               regTCF_PERFCOUNTER0_HI;
+typedef union TCF_PERFCOUNTER1_HI               regTCF_PERFCOUNTER1_HI;
+typedef union TCF_PERFCOUNTER2_HI               regTCF_PERFCOUNTER2_HI;
+typedef union TCF_PERFCOUNTER3_HI               regTCF_PERFCOUNTER3_HI;
+typedef union TCF_PERFCOUNTER4_HI               regTCF_PERFCOUNTER4_HI;
+typedef union TCF_PERFCOUNTER5_HI               regTCF_PERFCOUNTER5_HI;
+typedef union TCF_PERFCOUNTER6_HI               regTCF_PERFCOUNTER6_HI;
+typedef union TCF_PERFCOUNTER7_HI               regTCF_PERFCOUNTER7_HI;
+typedef union TCF_PERFCOUNTER8_HI               regTCF_PERFCOUNTER8_HI;
+typedef union TCF_PERFCOUNTER9_HI               regTCF_PERFCOUNTER9_HI;
+typedef union TCF_PERFCOUNTER10_HI              regTCF_PERFCOUNTER10_HI;
+typedef union TCF_PERFCOUNTER11_HI              regTCF_PERFCOUNTER11_HI;
+typedef union TCF_PERFCOUNTER0_LOW              regTCF_PERFCOUNTER0_LOW;
+typedef union TCF_PERFCOUNTER1_LOW              regTCF_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER2_LOW              regTCF_PERFCOUNTER2_LOW;
+typedef union TCF_PERFCOUNTER3_LOW              regTCF_PERFCOUNTER3_LOW;
+typedef union TCF_PERFCOUNTER4_LOW              regTCF_PERFCOUNTER4_LOW;
+typedef union TCF_PERFCOUNTER5_LOW              regTCF_PERFCOUNTER5_LOW;
+typedef union TCF_PERFCOUNTER6_LOW              regTCF_PERFCOUNTER6_LOW;
+typedef union TCF_PERFCOUNTER7_LOW              regTCF_PERFCOUNTER7_LOW;
+typedef union TCF_PERFCOUNTER8_LOW              regTCF_PERFCOUNTER8_LOW;
+typedef union TCF_PERFCOUNTER9_LOW              regTCF_PERFCOUNTER9_LOW;
+typedef union TCF_PERFCOUNTER10_LOW             regTCF_PERFCOUNTER10_LOW;
+typedef union TCF_PERFCOUNTER11_LOW             regTCF_PERFCOUNTER11_LOW;
+typedef union TCF_DEBUG                         regTCF_DEBUG;
+typedef union TCA_FIFO_DEBUG                    regTCA_FIFO_DEBUG;
+typedef union TCA_PROBE_DEBUG                   regTCA_PROBE_DEBUG;
+typedef union TCA_TPC_DEBUG                     regTCA_TPC_DEBUG;
+typedef union TCB_CORE_DEBUG                    regTCB_CORE_DEBUG;
+typedef union TCB_TAG0_DEBUG                    regTCB_TAG0_DEBUG;
+typedef union TCB_TAG1_DEBUG                    regTCB_TAG1_DEBUG;
+typedef union TCB_TAG2_DEBUG                    regTCB_TAG2_DEBUG;
+typedef union TCB_TAG3_DEBUG                    regTCB_TAG3_DEBUG;
+typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG;
+typedef union TCB_FETCH_GEN_WALKER_DEBUG        regTCB_FETCH_GEN_WALKER_DEBUG;
+typedef union TCB_FETCH_GEN_PIPE0_DEBUG         regTCB_FETCH_GEN_PIPE0_DEBUG;
+typedef union TCD_INPUT0_DEBUG                  regTCD_INPUT0_DEBUG;
+typedef union TCD_DEGAMMA_DEBUG                 regTCD_DEGAMMA_DEBUG;
+typedef union TCD_DXTMUX_SCTARB_DEBUG           regTCD_DXTMUX_SCTARB_DEBUG;
+typedef union TCD_DXTC_ARB_DEBUG                regTCD_DXTC_ARB_DEBUG;
+typedef union TCD_STALLS_DEBUG                  regTCD_STALLS_DEBUG;
+typedef union TCO_STALLS_DEBUG                  regTCO_STALLS_DEBUG;
+typedef union TCO_QUAD0_DEBUG0                  regTCO_QUAD0_DEBUG0;
+typedef union TCO_QUAD0_DEBUG1                  regTCO_QUAD0_DEBUG1;
+typedef union SQ_GPR_MANAGEMENT                 regSQ_GPR_MANAGEMENT;
+typedef union SQ_FLOW_CONTROL                   regSQ_FLOW_CONTROL;
+typedef union SQ_INST_STORE_MANAGMENT           regSQ_INST_STORE_MANAGMENT;
+typedef union SQ_RESOURCE_MANAGMENT             regSQ_RESOURCE_MANAGMENT;
+typedef union SQ_EO_RT                          regSQ_EO_RT;
+typedef union SQ_DEBUG_MISC                     regSQ_DEBUG_MISC;
+typedef union SQ_ACTIVITY_METER_CNTL            regSQ_ACTIVITY_METER_CNTL;
+typedef union SQ_ACTIVITY_METER_STATUS          regSQ_ACTIVITY_METER_STATUS;
+typedef union SQ_INPUT_ARB_PRIORITY             regSQ_INPUT_ARB_PRIORITY;
+typedef union SQ_THREAD_ARB_PRIORITY            regSQ_THREAD_ARB_PRIORITY;
+typedef union SQ_VS_WATCHDOG_TIMER              regSQ_VS_WATCHDOG_TIMER;
+typedef union SQ_PS_WATCHDOG_TIMER              regSQ_PS_WATCHDOG_TIMER;
+typedef union SQ_INT_CNTL                       regSQ_INT_CNTL;
+typedef union SQ_INT_STATUS                     regSQ_INT_STATUS;
+typedef union SQ_INT_ACK                        regSQ_INT_ACK;
+typedef union SQ_DEBUG_INPUT_FSM                regSQ_DEBUG_INPUT_FSM;
+typedef union SQ_DEBUG_CONST_MGR_FSM            regSQ_DEBUG_CONST_MGR_FSM;
+typedef union SQ_DEBUG_TP_FSM                   regSQ_DEBUG_TP_FSM;
+typedef union SQ_DEBUG_FSM_ALU_0                regSQ_DEBUG_FSM_ALU_0;
+typedef union SQ_DEBUG_FSM_ALU_1                regSQ_DEBUG_FSM_ALU_1;
+typedef union SQ_DEBUG_EXP_ALLOC                regSQ_DEBUG_EXP_ALLOC;
+typedef union SQ_DEBUG_PTR_BUFF                 regSQ_DEBUG_PTR_BUFF;
+typedef union SQ_DEBUG_GPR_VTX                  regSQ_DEBUG_GPR_VTX;
+typedef union SQ_DEBUG_GPR_PIX                  regSQ_DEBUG_GPR_PIX;
+typedef union SQ_DEBUG_TB_STATUS_SEL            regSQ_DEBUG_TB_STATUS_SEL;
+typedef union SQ_DEBUG_VTX_TB_0                 regSQ_DEBUG_VTX_TB_0;
+typedef union SQ_DEBUG_VTX_TB_1                 regSQ_DEBUG_VTX_TB_1;
+typedef union SQ_DEBUG_VTX_TB_STATUS_REG        regSQ_DEBUG_VTX_TB_STATUS_REG;
+typedef union SQ_DEBUG_VTX_TB_STATE_MEM         regSQ_DEBUG_VTX_TB_STATE_MEM;
+typedef union SQ_DEBUG_PIX_TB_0                 regSQ_DEBUG_PIX_TB_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0      regSQ_DEBUG_PIX_TB_STATUS_REG_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1      regSQ_DEBUG_PIX_TB_STATUS_REG_1;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2      regSQ_DEBUG_PIX_TB_STATUS_REG_2;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3      regSQ_DEBUG_PIX_TB_STATUS_REG_3;
+typedef union SQ_DEBUG_PIX_TB_STATE_MEM         regSQ_DEBUG_PIX_TB_STATE_MEM;
+typedef union SQ_PERFCOUNTER0_SELECT            regSQ_PERFCOUNTER0_SELECT;
+typedef union SQ_PERFCOUNTER1_SELECT            regSQ_PERFCOUNTER1_SELECT;
+typedef union SQ_PERFCOUNTER2_SELECT            regSQ_PERFCOUNTER2_SELECT;
+typedef union SQ_PERFCOUNTER3_SELECT            regSQ_PERFCOUNTER3_SELECT;
+typedef union SQ_PERFCOUNTER0_LOW               regSQ_PERFCOUNTER0_LOW;
+typedef union SQ_PERFCOUNTER0_HI                regSQ_PERFCOUNTER0_HI;
+typedef union SQ_PERFCOUNTER1_LOW               regSQ_PERFCOUNTER1_LOW;
+typedef union SQ_PERFCOUNTER1_HI                regSQ_PERFCOUNTER1_HI;
+typedef union SQ_PERFCOUNTER2_LOW               regSQ_PERFCOUNTER2_LOW;
+typedef union SQ_PERFCOUNTER2_HI                regSQ_PERFCOUNTER2_HI;
+typedef union SQ_PERFCOUNTER3_LOW               regSQ_PERFCOUNTER3_LOW;
+typedef union SQ_PERFCOUNTER3_HI                regSQ_PERFCOUNTER3_HI;
+typedef union SX_PERFCOUNTER0_SELECT            regSX_PERFCOUNTER0_SELECT;
+typedef union SX_PERFCOUNTER0_LOW               regSX_PERFCOUNTER0_LOW;
+typedef union SX_PERFCOUNTER0_HI                regSX_PERFCOUNTER0_HI;
+typedef union SQ_INSTRUCTION_ALU_0              regSQ_INSTRUCTION_ALU_0;
+typedef union SQ_INSTRUCTION_ALU_1              regSQ_INSTRUCTION_ALU_1;
+typedef union SQ_INSTRUCTION_ALU_2              regSQ_INSTRUCTION_ALU_2;
+typedef union SQ_INSTRUCTION_CF_EXEC_0          regSQ_INSTRUCTION_CF_EXEC_0;
+typedef union SQ_INSTRUCTION_CF_EXEC_1          regSQ_INSTRUCTION_CF_EXEC_1;
+typedef union SQ_INSTRUCTION_CF_EXEC_2          regSQ_INSTRUCTION_CF_EXEC_2;
+typedef union SQ_INSTRUCTION_CF_LOOP_0          regSQ_INSTRUCTION_CF_LOOP_0;
+typedef union SQ_INSTRUCTION_CF_LOOP_1          regSQ_INSTRUCTION_CF_LOOP_1;
+typedef union SQ_INSTRUCTION_CF_LOOP_2          regSQ_INSTRUCTION_CF_LOOP_2;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_0      regSQ_INSTRUCTION_CF_JMP_CALL_0;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_1      regSQ_INSTRUCTION_CF_JMP_CALL_1;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_2      regSQ_INSTRUCTION_CF_JMP_CALL_2;
+typedef union SQ_INSTRUCTION_CF_ALLOC_0         regSQ_INSTRUCTION_CF_ALLOC_0;
+typedef union SQ_INSTRUCTION_CF_ALLOC_1         regSQ_INSTRUCTION_CF_ALLOC_1;
+typedef union SQ_INSTRUCTION_CF_ALLOC_2         regSQ_INSTRUCTION_CF_ALLOC_2;
+typedef union SQ_INSTRUCTION_TFETCH_0           regSQ_INSTRUCTION_TFETCH_0;
+typedef union SQ_INSTRUCTION_TFETCH_1           regSQ_INSTRUCTION_TFETCH_1;
+typedef union SQ_INSTRUCTION_TFETCH_2           regSQ_INSTRUCTION_TFETCH_2;
+typedef union SQ_INSTRUCTION_VFETCH_0           regSQ_INSTRUCTION_VFETCH_0;
+typedef union SQ_INSTRUCTION_VFETCH_1           regSQ_INSTRUCTION_VFETCH_1;
+typedef union SQ_INSTRUCTION_VFETCH_2           regSQ_INSTRUCTION_VFETCH_2;
+typedef union SQ_CONSTANT_0                     regSQ_CONSTANT_0;
+typedef union SQ_CONSTANT_1                     regSQ_CONSTANT_1;
+typedef union SQ_CONSTANT_2                     regSQ_CONSTANT_2;
+typedef union SQ_CONSTANT_3                     regSQ_CONSTANT_3;
+typedef union SQ_FETCH_0                        regSQ_FETCH_0;
+typedef union SQ_FETCH_1                        regSQ_FETCH_1;
+typedef union SQ_FETCH_2                        regSQ_FETCH_2;
+typedef union SQ_FETCH_3                        regSQ_FETCH_3;
+typedef union SQ_FETCH_4                        regSQ_FETCH_4;
+typedef union SQ_FETCH_5                        regSQ_FETCH_5;
+typedef union SQ_CONSTANT_VFETCH_0              regSQ_CONSTANT_VFETCH_0;
+typedef union SQ_CONSTANT_VFETCH_1              regSQ_CONSTANT_VFETCH_1;
+typedef union SQ_CONSTANT_T2                    regSQ_CONSTANT_T2;
+typedef union SQ_CONSTANT_T3                    regSQ_CONSTANT_T3;
+typedef union SQ_CF_BOOLEANS                    regSQ_CF_BOOLEANS;
+typedef union SQ_CF_LOOP                        regSQ_CF_LOOP;
+typedef union SQ_CONSTANT_RT_0                  regSQ_CONSTANT_RT_0;
+typedef union SQ_CONSTANT_RT_1                  regSQ_CONSTANT_RT_1;
+typedef union SQ_CONSTANT_RT_2                  regSQ_CONSTANT_RT_2;
+typedef union SQ_CONSTANT_RT_3                  regSQ_CONSTANT_RT_3;
+typedef union SQ_FETCH_RT_0                     regSQ_FETCH_RT_0;
+typedef union SQ_FETCH_RT_1                     regSQ_FETCH_RT_1;
+typedef union SQ_FETCH_RT_2                     regSQ_FETCH_RT_2;
+typedef union SQ_FETCH_RT_3                     regSQ_FETCH_RT_3;
+typedef union SQ_FETCH_RT_4                     regSQ_FETCH_RT_4;
+typedef union SQ_FETCH_RT_5                     regSQ_FETCH_RT_5;
+typedef union SQ_CF_RT_BOOLEANS                 regSQ_CF_RT_BOOLEANS;
+typedef union SQ_CF_RT_LOOP                     regSQ_CF_RT_LOOP;
+typedef union SQ_VS_PROGRAM                     regSQ_VS_PROGRAM;
+typedef union SQ_PS_PROGRAM                     regSQ_PS_PROGRAM;
+typedef union SQ_CF_PROGRAM_SIZE                regSQ_CF_PROGRAM_SIZE;
+typedef union SQ_INTERPOLATOR_CNTL              regSQ_INTERPOLATOR_CNTL;
+typedef union SQ_PROGRAM_CNTL                   regSQ_PROGRAM_CNTL;
+typedef union SQ_WRAPPING_0                     regSQ_WRAPPING_0;
+typedef union SQ_WRAPPING_1                     regSQ_WRAPPING_1;
+typedef union SQ_VS_CONST                       regSQ_VS_CONST;
+typedef union SQ_PS_CONST                       regSQ_PS_CONST;
+typedef union SQ_CONTEXT_MISC                   regSQ_CONTEXT_MISC;
+typedef union SQ_CF_RD_BASE                     regSQ_CF_RD_BASE;
+typedef union SQ_DEBUG_MISC_0                   regSQ_DEBUG_MISC_0;
+typedef union SQ_DEBUG_MISC_1                   regSQ_DEBUG_MISC_1;
+typedef union MH_ARBITER_CONFIG                 regMH_ARBITER_CONFIG;
+typedef union MH_CLNT_AXI_ID_REUSE              regMH_CLNT_AXI_ID_REUSE;
+typedef union MH_INTERRUPT_MASK                 regMH_INTERRUPT_MASK;
+typedef union MH_INTERRUPT_STATUS               regMH_INTERRUPT_STATUS;
+typedef union MH_INTERRUPT_CLEAR                regMH_INTERRUPT_CLEAR;
+typedef union MH_AXI_ERROR                      regMH_AXI_ERROR;
+typedef union MH_PERFCOUNTER0_SELECT            regMH_PERFCOUNTER0_SELECT;
+typedef union MH_PERFCOUNTER1_SELECT            regMH_PERFCOUNTER1_SELECT;
+typedef union MH_PERFCOUNTER0_CONFIG            regMH_PERFCOUNTER0_CONFIG;
+typedef union MH_PERFCOUNTER1_CONFIG            regMH_PERFCOUNTER1_CONFIG;
+typedef union MH_PERFCOUNTER0_LOW               regMH_PERFCOUNTER0_LOW;
+typedef union MH_PERFCOUNTER1_LOW               regMH_PERFCOUNTER1_LOW;
+typedef union MH_PERFCOUNTER0_HI                regMH_PERFCOUNTER0_HI;
+typedef union MH_PERFCOUNTER1_HI                regMH_PERFCOUNTER1_HI;
+typedef union MH_DEBUG_CTRL                     regMH_DEBUG_CTRL;
+typedef union MH_DEBUG_DATA                     regMH_DEBUG_DATA;
+typedef union MH_AXI_HALT_CONTROL               regMH_AXI_HALT_CONTROL;
+typedef union MH_MMU_CONFIG                     regMH_MMU_CONFIG;
+typedef union MH_MMU_VA_RANGE                   regMH_MMU_VA_RANGE;
+typedef union MH_MMU_PT_BASE                    regMH_MMU_PT_BASE;
+typedef union MH_MMU_PAGE_FAULT                 regMH_MMU_PAGE_FAULT;
+typedef union MH_MMU_TRAN_ERROR                 regMH_MMU_TRAN_ERROR;
+typedef union MH_MMU_INVALIDATE                 regMH_MMU_INVALIDATE;
+typedef union MH_MMU_MPU_BASE                   regMH_MMU_MPU_BASE;
+typedef union MH_MMU_MPU_END                    regMH_MMU_MPU_END;
+typedef union WAIT_UNTIL                        regWAIT_UNTIL;
+typedef union RBBM_ISYNC_CNTL                   regRBBM_ISYNC_CNTL;
+typedef union RBBM_STATUS                       regRBBM_STATUS;
+typedef union RBBM_DSPLY                        regRBBM_DSPLY;
+typedef union RBBM_RENDER_LATEST                regRBBM_RENDER_LATEST;
+typedef union RBBM_RTL_RELEASE                  regRBBM_RTL_RELEASE;
+typedef union RBBM_PATCH_RELEASE                regRBBM_PATCH_RELEASE;
+typedef union RBBM_AUXILIARY_CONFIG             regRBBM_AUXILIARY_CONFIG;
+typedef union RBBM_PERIPHID0                    regRBBM_PERIPHID0;
+typedef union RBBM_PERIPHID1                    regRBBM_PERIPHID1;
+typedef union RBBM_PERIPHID2                    regRBBM_PERIPHID2;
+typedef union RBBM_PERIPHID3                    regRBBM_PERIPHID3;
+typedef union RBBM_CNTL                         regRBBM_CNTL;
+typedef union RBBM_SKEW_CNTL                    regRBBM_SKEW_CNTL;
+typedef union RBBM_SOFT_RESET                   regRBBM_SOFT_RESET;
+typedef union RBBM_PM_OVERRIDE1                 regRBBM_PM_OVERRIDE1;
+typedef union RBBM_PM_OVERRIDE2                 regRBBM_PM_OVERRIDE2;
+typedef union GC_SYS_IDLE                       regGC_SYS_IDLE;
+typedef union NQWAIT_UNTIL                      regNQWAIT_UNTIL;
+typedef union RBBM_DEBUG_OUT                    regRBBM_DEBUG_OUT;
+typedef union RBBM_DEBUG_CNTL                   regRBBM_DEBUG_CNTL;
+typedef union RBBM_DEBUG                        regRBBM_DEBUG;
+typedef union RBBM_READ_ERROR                   regRBBM_READ_ERROR;
+typedef union RBBM_WAIT_IDLE_CLOCKS             regRBBM_WAIT_IDLE_CLOCKS;
+typedef union RBBM_INT_CNTL                     regRBBM_INT_CNTL;
+typedef union RBBM_INT_STATUS                   regRBBM_INT_STATUS;
+typedef union RBBM_INT_ACK                      regRBBM_INT_ACK;
+typedef union MASTER_INT_SIGNAL                 regMASTER_INT_SIGNAL;
+typedef union RBBM_PERFCOUNTER1_SELECT          regRBBM_PERFCOUNTER1_SELECT;
+typedef union RBBM_PERFCOUNTER1_LO              regRBBM_PERFCOUNTER1_LO;
+typedef union RBBM_PERFCOUNTER1_HI              regRBBM_PERFCOUNTER1_HI;
+typedef union CP_RB_BASE                        regCP_RB_BASE;
+typedef union CP_RB_CNTL                        regCP_RB_CNTL;
+typedef union CP_RB_RPTR_ADDR                   regCP_RB_RPTR_ADDR;
+typedef union CP_RB_RPTR                        regCP_RB_RPTR;
+typedef union CP_RB_RPTR_WR                     regCP_RB_RPTR_WR;
+typedef union CP_RB_WPTR                        regCP_RB_WPTR;
+typedef union CP_RB_WPTR_DELAY                  regCP_RB_WPTR_DELAY;
+typedef union CP_RB_WPTR_BASE                   regCP_RB_WPTR_BASE;
+typedef union CP_IB1_BASE                       regCP_IB1_BASE;
+typedef union CP_IB1_BUFSZ                      regCP_IB1_BUFSZ;
+typedef union CP_IB2_BASE                       regCP_IB2_BASE;
+typedef union CP_IB2_BUFSZ                      regCP_IB2_BUFSZ;
+typedef union CP_ST_BASE                        regCP_ST_BASE;
+typedef union CP_ST_BUFSZ                       regCP_ST_BUFSZ;
+typedef union CP_QUEUE_THRESHOLDS               regCP_QUEUE_THRESHOLDS;
+typedef union CP_MEQ_THRESHOLDS                 regCP_MEQ_THRESHOLDS;
+typedef union CP_CSQ_AVAIL                      regCP_CSQ_AVAIL;
+typedef union CP_STQ_AVAIL                      regCP_STQ_AVAIL;
+typedef union CP_MEQ_AVAIL                      regCP_MEQ_AVAIL;
+typedef union CP_CSQ_RB_STAT                    regCP_CSQ_RB_STAT;
+typedef union CP_CSQ_IB1_STAT                   regCP_CSQ_IB1_STAT;
+typedef union CP_CSQ_IB2_STAT                   regCP_CSQ_IB2_STAT;
+typedef union CP_NON_PREFETCH_CNTRS             regCP_NON_PREFETCH_CNTRS;
+typedef union CP_STQ_ST_STAT                    regCP_STQ_ST_STAT;
+typedef union CP_MEQ_STAT                       regCP_MEQ_STAT;
+typedef union CP_MIU_TAG_STAT                   regCP_MIU_TAG_STAT;
+typedef union CP_CMD_INDEX                      regCP_CMD_INDEX;
+typedef union CP_CMD_DATA                       regCP_CMD_DATA;
+typedef union CP_ME_CNTL                        regCP_ME_CNTL;
+typedef union CP_ME_STATUS                      regCP_ME_STATUS;
+typedef union CP_ME_RAM_WADDR                   regCP_ME_RAM_WADDR;
+typedef union CP_ME_RAM_RADDR                   regCP_ME_RAM_RADDR;
+typedef union CP_ME_RAM_DATA                    regCP_ME_RAM_DATA;
+typedef union CP_ME_RDADDR                      regCP_ME_RDADDR;
+typedef union CP_DEBUG                          regCP_DEBUG;
+typedef union SCRATCH_REG0                      regSCRATCH_REG0;
+typedef union GUI_SCRATCH_REG0                  regGUI_SCRATCH_REG0;
+typedef union SCRATCH_REG1                      regSCRATCH_REG1;
+typedef union GUI_SCRATCH_REG1                  regGUI_SCRATCH_REG1;
+typedef union SCRATCH_REG2                      regSCRATCH_REG2;
+typedef union GUI_SCRATCH_REG2                  regGUI_SCRATCH_REG2;
+typedef union SCRATCH_REG3                      regSCRATCH_REG3;
+typedef union GUI_SCRATCH_REG3                  regGUI_SCRATCH_REG3;
+typedef union SCRATCH_REG4                      regSCRATCH_REG4;
+typedef union GUI_SCRATCH_REG4                  regGUI_SCRATCH_REG4;
+typedef union SCRATCH_REG5                      regSCRATCH_REG5;
+typedef union GUI_SCRATCH_REG5                  regGUI_SCRATCH_REG5;
+typedef union SCRATCH_REG6                      regSCRATCH_REG6;
+typedef union GUI_SCRATCH_REG6                  regGUI_SCRATCH_REG6;
+typedef union SCRATCH_REG7                      regSCRATCH_REG7;
+typedef union GUI_SCRATCH_REG7                  regGUI_SCRATCH_REG7;
+typedef union SCRATCH_UMSK                      regSCRATCH_UMSK;
+typedef union SCRATCH_ADDR                      regSCRATCH_ADDR;
+typedef union CP_ME_VS_EVENT_SRC                regCP_ME_VS_EVENT_SRC;
+typedef union CP_ME_VS_EVENT_ADDR               regCP_ME_VS_EVENT_ADDR;
+typedef union CP_ME_VS_EVENT_DATA               regCP_ME_VS_EVENT_DATA;
+typedef union CP_ME_VS_EVENT_ADDR_SWM           regCP_ME_VS_EVENT_ADDR_SWM;
+typedef union CP_ME_VS_EVENT_DATA_SWM           regCP_ME_VS_EVENT_DATA_SWM;
+typedef union CP_ME_PS_EVENT_SRC                regCP_ME_PS_EVENT_SRC;
+typedef union CP_ME_PS_EVENT_ADDR               regCP_ME_PS_EVENT_ADDR;
+typedef union CP_ME_PS_EVENT_DATA               regCP_ME_PS_EVENT_DATA;
+typedef union CP_ME_PS_EVENT_ADDR_SWM           regCP_ME_PS_EVENT_ADDR_SWM;
+typedef union CP_ME_PS_EVENT_DATA_SWM           regCP_ME_PS_EVENT_DATA_SWM;
+typedef union CP_ME_CF_EVENT_SRC                regCP_ME_CF_EVENT_SRC;
+typedef union CP_ME_CF_EVENT_ADDR               regCP_ME_CF_EVENT_ADDR;
+typedef union CP_ME_CF_EVENT_DATA               regCP_ME_CF_EVENT_DATA;
+typedef union CP_ME_NRT_ADDR                    regCP_ME_NRT_ADDR;
+typedef union CP_ME_NRT_DATA                    regCP_ME_NRT_DATA;
+typedef union CP_ME_VS_FETCH_DONE_SRC           regCP_ME_VS_FETCH_DONE_SRC;
+typedef union CP_ME_VS_FETCH_DONE_ADDR          regCP_ME_VS_FETCH_DONE_ADDR;
+typedef union CP_ME_VS_FETCH_DONE_DATA          regCP_ME_VS_FETCH_DONE_DATA;
+typedef union CP_INT_CNTL                       regCP_INT_CNTL;
+typedef union CP_INT_STATUS                     regCP_INT_STATUS;
+typedef union CP_INT_ACK                        regCP_INT_ACK;
+typedef union CP_PFP_UCODE_ADDR                 regCP_PFP_UCODE_ADDR;
+typedef union CP_PFP_UCODE_DATA                 regCP_PFP_UCODE_DATA;
+typedef union CP_PERFMON_CNTL                   regCP_PERFMON_CNTL;
+typedef union CP_PERFCOUNTER_SELECT             regCP_PERFCOUNTER_SELECT;
+typedef union CP_PERFCOUNTER_LO                 regCP_PERFCOUNTER_LO;
+typedef union CP_PERFCOUNTER_HI                 regCP_PERFCOUNTER_HI;
+typedef union CP_BIN_MASK_LO                    regCP_BIN_MASK_LO;
+typedef union CP_BIN_MASK_HI                    regCP_BIN_MASK_HI;
+typedef union CP_BIN_SELECT_LO                  regCP_BIN_SELECT_LO;
+typedef union CP_BIN_SELECT_HI                  regCP_BIN_SELECT_HI;
+typedef union CP_NV_FLAGS_0                     regCP_NV_FLAGS_0;
+typedef union CP_NV_FLAGS_1                     regCP_NV_FLAGS_1;
+typedef union CP_NV_FLAGS_2                     regCP_NV_FLAGS_2;
+typedef union CP_NV_FLAGS_3                     regCP_NV_FLAGS_3;
+typedef union CP_STATE_DEBUG_INDEX              regCP_STATE_DEBUG_INDEX;
+typedef union CP_STATE_DEBUG_DATA               regCP_STATE_DEBUG_DATA;
+typedef union CP_PROG_COUNTER                   regCP_PROG_COUNTER;
+typedef union CP_STAT                           regCP_STAT;
+typedef union BIOS_0_SCRATCH                    regBIOS_0_SCRATCH;
+typedef union BIOS_1_SCRATCH                    regBIOS_1_SCRATCH;
+typedef union BIOS_2_SCRATCH                    regBIOS_2_SCRATCH;
+typedef union BIOS_3_SCRATCH                    regBIOS_3_SCRATCH;
+typedef union BIOS_4_SCRATCH                    regBIOS_4_SCRATCH;
+typedef union BIOS_5_SCRATCH                    regBIOS_5_SCRATCH;
+typedef union BIOS_6_SCRATCH                    regBIOS_6_SCRATCH;
+typedef union BIOS_7_SCRATCH                    regBIOS_7_SCRATCH;
+typedef union BIOS_8_SCRATCH                    regBIOS_8_SCRATCH;
+typedef union BIOS_9_SCRATCH                    regBIOS_9_SCRATCH;
+typedef union BIOS_10_SCRATCH                   regBIOS_10_SCRATCH;
+typedef union BIOS_11_SCRATCH                   regBIOS_11_SCRATCH;
+typedef union BIOS_12_SCRATCH                   regBIOS_12_SCRATCH;
+typedef union BIOS_13_SCRATCH                   regBIOS_13_SCRATCH;
+typedef union BIOS_14_SCRATCH                   regBIOS_14_SCRATCH;
+typedef union BIOS_15_SCRATCH                   regBIOS_15_SCRATCH;
+typedef union COHER_SIZE_PM4                    regCOHER_SIZE_PM4;
+typedef union COHER_BASE_PM4                    regCOHER_BASE_PM4;
+typedef union COHER_STATUS_PM4                  regCOHER_STATUS_PM4;
+typedef union COHER_SIZE_HOST                   regCOHER_SIZE_HOST;
+typedef union COHER_BASE_HOST                   regCOHER_BASE_HOST;
+typedef union COHER_STATUS_HOST                 regCOHER_STATUS_HOST;
+typedef union COHER_DEST_BASE_0                 regCOHER_DEST_BASE_0;
+typedef union COHER_DEST_BASE_1                 regCOHER_DEST_BASE_1;
+typedef union COHER_DEST_BASE_2                 regCOHER_DEST_BASE_2;
+typedef union COHER_DEST_BASE_3                 regCOHER_DEST_BASE_3;
+typedef union COHER_DEST_BASE_4                 regCOHER_DEST_BASE_4;
+typedef union COHER_DEST_BASE_5                 regCOHER_DEST_BASE_5;
+typedef union COHER_DEST_BASE_6                 regCOHER_DEST_BASE_6;
+typedef union COHER_DEST_BASE_7                 regCOHER_DEST_BASE_7;
+typedef union RB_SURFACE_INFO                   regRB_SURFACE_INFO;
+typedef union RB_COLOR_INFO                     regRB_COLOR_INFO;
+typedef union RB_DEPTH_INFO                     regRB_DEPTH_INFO;
+typedef union RB_STENCILREFMASK                 regRB_STENCILREFMASK;
+typedef union RB_ALPHA_REF                      regRB_ALPHA_REF;
+typedef union RB_COLOR_MASK                     regRB_COLOR_MASK;
+typedef union RB_BLEND_RED                      regRB_BLEND_RED;
+typedef union RB_BLEND_GREEN                    regRB_BLEND_GREEN;
+typedef union RB_BLEND_BLUE                     regRB_BLEND_BLUE;
+typedef union RB_BLEND_ALPHA                    regRB_BLEND_ALPHA;
+typedef union RB_FOG_COLOR                      regRB_FOG_COLOR;
+typedef union RB_STENCILREFMASK_BF              regRB_STENCILREFMASK_BF;
+typedef union RB_DEPTHCONTROL                   regRB_DEPTHCONTROL;
+typedef union RB_BLENDCONTROL                   regRB_BLENDCONTROL;
+typedef union RB_COLORCONTROL                   regRB_COLORCONTROL;
+typedef union RB_MODECONTROL                    regRB_MODECONTROL;
+typedef union RB_COLOR_DEST_MASK                regRB_COLOR_DEST_MASK;
+typedef union RB_COPY_CONTROL                   regRB_COPY_CONTROL;
+typedef union RB_COPY_DEST_BASE                 regRB_COPY_DEST_BASE;
+typedef union RB_COPY_DEST_PITCH                regRB_COPY_DEST_PITCH;
+typedef union RB_COPY_DEST_INFO                 regRB_COPY_DEST_INFO;
+typedef union RB_COPY_DEST_PIXEL_OFFSET         regRB_COPY_DEST_PIXEL_OFFSET;
+typedef union RB_DEPTH_CLEAR                    regRB_DEPTH_CLEAR;
+typedef union RB_SAMPLE_COUNT_CTL               regRB_SAMPLE_COUNT_CTL;
+typedef union RB_SAMPLE_COUNT_ADDR              regRB_SAMPLE_COUNT_ADDR;
+typedef union RB_BC_CONTROL                     regRB_BC_CONTROL;
+typedef union RB_EDRAM_INFO                     regRB_EDRAM_INFO;
+typedef union RB_CRC_RD_PORT                    regRB_CRC_RD_PORT;
+typedef union RB_CRC_CONTROL                    regRB_CRC_CONTROL;
+typedef union RB_CRC_MASK                       regRB_CRC_MASK;
+typedef union RB_PERFCOUNTER0_SELECT            regRB_PERFCOUNTER0_SELECT;
+typedef union RB_PERFCOUNTER0_LOW               regRB_PERFCOUNTER0_LOW;
+typedef union RB_PERFCOUNTER0_HI                regRB_PERFCOUNTER0_HI;
+typedef union RB_TOTAL_SAMPLES                  regRB_TOTAL_SAMPLES;
+typedef union RB_ZPASS_SAMPLES                  regRB_ZPASS_SAMPLES;
+typedef union RB_ZFAIL_SAMPLES                  regRB_ZFAIL_SAMPLES;
+typedef union RB_SFAIL_SAMPLES                  regRB_SFAIL_SAMPLES;
+typedef union RB_DEBUG_0                        regRB_DEBUG_0;
+typedef union RB_DEBUG_1                        regRB_DEBUG_1;
+typedef union RB_DEBUG_2                        regRB_DEBUG_2;
+typedef union RB_DEBUG_3                        regRB_DEBUG_3;
+typedef union RB_DEBUG_4                        regRB_DEBUG_4;
+typedef union RB_FLAG_CONTROL                   regRB_FLAG_CONTROL;
+typedef union RB_BC_SPARES                      regRB_BC_SPARES;
+typedef union BC_DUMMY_CRAYRB_ENUMS             regBC_DUMMY_CRAYRB_ENUMS;
+typedef union BC_DUMMY_CRAYRB_MOREENUMS         regBC_DUMMY_CRAYRB_MOREENUMS;
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h
new file mode 100644
index 00000000000..ba259a6c9d5
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h
@@ -0,0 +1,169 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamatoix_h
+#define _yamatoix_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+// [SUDEBUGIND] : Indirect Registers
+
+#define ixCLIPPER_DEBUG_REG00                      0x0000
+#define ixCLIPPER_DEBUG_REG01                      0x0001
+#define ixCLIPPER_DEBUG_REG02                      0x0002
+#define ixCLIPPER_DEBUG_REG03                      0x0003
+#define ixCLIPPER_DEBUG_REG04                      0x0004
+#define ixCLIPPER_DEBUG_REG05                      0x0005
+#define ixCLIPPER_DEBUG_REG09                      0x0009
+#define ixCLIPPER_DEBUG_REG10                      0x000A
+#define ixCLIPPER_DEBUG_REG11                      0x000B
+#define ixCLIPPER_DEBUG_REG12                      0x000C
+#define ixCLIPPER_DEBUG_REG13                      0x000D
+#define ixSXIFCCG_DEBUG_REG0                       0x0011
+#define ixSXIFCCG_DEBUG_REG1                       0x0012
+#define ixSXIFCCG_DEBUG_REG2                       0x0013
+#define ixSXIFCCG_DEBUG_REG3                       0x0014
+#define ixSETUP_DEBUG_REG0                         0x0015
+#define ixSETUP_DEBUG_REG1                         0x0016
+#define ixSETUP_DEBUG_REG2                         0x0017
+#define ixSETUP_DEBUG_REG3                         0x0018
+#define ixSETUP_DEBUG_REG4                         0x0019
+#define ixSETUP_DEBUG_REG5                         0x001A
+
+// [SCDEBUGIND] : Indirect Registers
+
+#define ixSC_DEBUG_0                               0x0000
+#define ixSC_DEBUG_1                               0x0001
+#define ixSC_DEBUG_2                               0x0002
+#define ixSC_DEBUG_3                               0x0003
+#define ixSC_DEBUG_4                               0x0004
+#define ixSC_DEBUG_5                               0x0005
+#define ixSC_DEBUG_6                               0x0006
+#define ixSC_DEBUG_7                               0x0007
+#define ixSC_DEBUG_8                               0x0008
+#define ixSC_DEBUG_9                               0x0009
+#define ixSC_DEBUG_10                              0x000A
+#define ixSC_DEBUG_11                              0x000B
+#define ixSC_DEBUG_12                              0x000C
+
+// [VGTDEBUGIND] : Indirect Registers
+
+#define ixVGT_DEBUG_REG0                           0x0000
+#define ixVGT_DEBUG_REG1                           0x0001
+#define ixVGT_DEBUG_REG3                           0x0003
+#define ixVGT_DEBUG_REG6                           0x0006
+#define ixVGT_DEBUG_REG7                           0x0007
+#define ixVGT_DEBUG_REG8                           0x0008
+#define ixVGT_DEBUG_REG9                           0x0009
+#define ixVGT_DEBUG_REG10                          0x000A
+#define ixVGT_DEBUG_REG12                          0x000C
+#define ixVGT_DEBUG_REG13                          0x000D
+#define ixVGT_DEBUG_REG14                          0x000E
+#define ixVGT_DEBUG_REG15                          0x000F
+#define ixVGT_DEBUG_REG16                          0x0010
+#define ixVGT_DEBUG_REG17                          0x0011
+#define ixVGT_DEBUG_REG18                          0x0012
+#define ixVGT_DEBUG_REG20                          0x0014
+#define ixVGT_DEBUG_REG21                          0x0015
+
+// [MHDEBUGIND] : Indirect Registers
+
+#define ixMH_DEBUG_REG00                           0x0000
+#define ixMH_DEBUG_REG01                           0x0001
+#define ixMH_DEBUG_REG02                           0x0002
+#define ixMH_DEBUG_REG03                           0x0003
+#define ixMH_DEBUG_REG04                           0x0004
+#define ixMH_DEBUG_REG05                           0x0005
+#define ixMH_DEBUG_REG06                           0x0006
+#define ixMH_DEBUG_REG07                           0x0007
+#define ixMH_DEBUG_REG08                           0x0008
+#define ixMH_DEBUG_REG09                           0x0009
+#define ixMH_DEBUG_REG10                           0x000A
+#define ixMH_DEBUG_REG11                           0x000B
+#define ixMH_DEBUG_REG12                           0x000C
+#define ixMH_DEBUG_REG13                           0x000D
+#define ixMH_DEBUG_REG14                           0x000E
+#define ixMH_DEBUG_REG15                           0x000F
+#define ixMH_DEBUG_REG16                           0x0010
+#define ixMH_DEBUG_REG17                           0x0011
+#define ixMH_DEBUG_REG18                           0x0012
+#define ixMH_DEBUG_REG19                           0x0013
+#define ixMH_DEBUG_REG20                           0x0014
+#define ixMH_DEBUG_REG21                           0x0015
+#define ixMH_DEBUG_REG22                           0x0016
+#define ixMH_DEBUG_REG23                           0x0017
+#define ixMH_DEBUG_REG24                           0x0018
+#define ixMH_DEBUG_REG25                           0x0019
+#define ixMH_DEBUG_REG26                           0x001A
+#define ixMH_DEBUG_REG27                           0x001B
+#define ixMH_DEBUG_REG28                           0x001C
+#define ixMH_DEBUG_REG29                           0x001D
+#define ixMH_DEBUG_REG30                           0x001E
+#define ixMH_DEBUG_REG31                           0x001F
+#define ixMH_DEBUG_REG32                           0x0020
+#define ixMH_DEBUG_REG33                           0x0021
+#define ixMH_DEBUG_REG34                           0x0022
+#define ixMH_DEBUG_REG35                           0x0023
+#define ixMH_DEBUG_REG36                           0x0024
+#define ixMH_DEBUG_REG37                           0x0025
+#define ixMH_DEBUG_REG38                           0x0026
+#define ixMH_DEBUG_REG39                           0x0027
+#define ixMH_DEBUG_REG40                           0x0028
+#define ixMH_DEBUG_REG41                           0x0029
+#define ixMH_DEBUG_REG42                           0x002A
+#define ixMH_DEBUG_REG43                           0x002B
+#define ixMH_DEBUG_REG44                           0x002C
+#define ixMH_DEBUG_REG45                           0x002D
+#define ixMH_DEBUG_REG46                           0x002E
+#define ixMH_DEBUG_REG47                           0x002F
+#define ixMH_DEBUG_REG48                           0x0030
+#define ixMH_DEBUG_REG49                           0x0031
+#define ixMH_DEBUG_REG50                           0x0032
+#define ixMH_DEBUG_REG51                           0x0033
+#define ixMH_DEBUG_REG52                           0x0034
+#define ixMH_DEBUG_REG53                           0x0035
+#define ixMH_DEBUG_REG54                           0x0036
+#define ixMH_DEBUG_REG55                           0x0037
+#define ixMH_DEBUG_REG56                           0x0038
+#define ixMH_DEBUG_REG57                           0x0039
+#define ixMH_DEBUG_REG58                           0x003A
+#define ixMH_DEBUG_REG59                           0x003B
+#define ixMH_DEBUG_REG60                           0x003C
+#define ixMH_DEBUG_REG61                           0x003D
+#define ixMH_DEBUG_REG62                           0x003E
+#define ixMH_DEBUG_REG63                           0x003F
+
+
+#ifdef __cplusplus
+}
+#endif  // __cplusplus
+
+#endif // _yamatob_h
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h
new file mode 100644
index 00000000000..ab11205f109
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h
@@ -0,0 +1,1867 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_ENUM_HEADER)
+#define _yamato_ENUM_HEADER
+
+
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+#ifndef ENUMS_SU_PERFCNT_SELECT_H
+#define ENUMS_SU_PERFCNT_SELECT_H
+typedef enum SU_PERFCNT_SELECT {
+ PERF_PAPC_PASX_REQ = 0,
+ UNUSED1 = 1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 3,
+ PERF_PAPC_PASX_FIRST_DEAD = 4,
+ PERF_PAPC_PASX_SECOND_DEAD = 5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+ PERF_PAPC_PA_INPUT_PRIM = 8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+ PERF_PAPC_CLPR_CULL_PRIM = 13,
+ UNUSED2 = 14,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+ UNUSED3 = 16,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+ UNUSED4 = 20,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+ UNUSED5 = 22,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+ PERF_PAPC_CLSM_NULL_PRIM = 36,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+ PERF_PAPC_CLSM_CLIP_PRIM = 38,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+ PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+ PERF_PAPC_SU_INPUT_PRIM = 47,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+ PERF_PAPC_SU_OUTPUT_PRIM = 57,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+ PERF_PAPC_PASX_REQ_IDLE = 69,
+ PERF_PAPC_PASX_REQ_BUSY = 70,
+ PERF_PAPC_PASX_REQ_STALLED = 71,
+ PERF_PAPC_PASX_REC_IDLE = 72,
+ PERF_PAPC_PASX_REC_BUSY = 73,
+ PERF_PAPC_PASX_REC_STARVED_SX = 74,
+ PERF_PAPC_PASX_REC_STALLED = 75,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+ PERF_PAPC_CCGSM_IDLE = 78,
+ PERF_PAPC_CCGSM_BUSY = 79,
+ PERF_PAPC_CCGSM_STALLED = 80,
+ PERF_PAPC_CLPRIM_IDLE = 81,
+ PERF_PAPC_CLPRIM_BUSY = 82,
+ PERF_PAPC_CLPRIM_STALLED = 83,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+ PERF_PAPC_CLIPSM_IDLE = 85,
+ PERF_PAPC_CLIPSM_BUSY = 86,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+ PERF_PAPC_CLIPGA_IDLE = 92,
+ PERF_PAPC_CLIPGA_BUSY = 93,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+ PERF_PAPC_CLIPGA_STALLED = 95,
+ PERF_PAPC_CLIP_IDLE = 96,
+ PERF_PAPC_CLIP_BUSY = 97,
+ PERF_PAPC_SU_IDLE = 98,
+ PERF_PAPC_SU_BUSY = 99,
+ PERF_PAPC_SU_STARVED_CLIP = 100,
+ PERF_PAPC_SU_STALLED_SC = 101,
+} SU_PERFCNT_SELECT;
+#endif /*ENUMS_SU_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SC_PERFCNT_SELECT_H
+#define ENUMS_SC_PERFCNT_SELECT_H
+typedef enum SC_PERFCNT_SELECT {
+ SC_SR_WINDOW_VALID = 0,
+ SC_CW_WINDOW_VALID = 1,
+ SC_QM_WINDOW_VALID = 2,
+ SC_FW_WINDOW_VALID = 3,
+ SC_EZ_WINDOW_VALID = 4,
+ SC_IT_WINDOW_VALID = 5,
+ SC_STARVED_BY_PA = 6,
+ SC_STALLED_BY_RB_TILE = 7,
+ SC_STALLED_BY_RB_SAMP = 8,
+ SC_STARVED_BY_RB_EZ = 9,
+ SC_STALLED_BY_SAMPLE_FF = 10,
+ SC_STALLED_BY_SQ = 11,
+ SC_STALLED_BY_SP = 12,
+ SC_TOTAL_NO_PRIMS = 13,
+ SC_NON_EMPTY_PRIMS = 14,
+ SC_NO_TILES_PASSING_QM = 15,
+ SC_NO_PIXELS_PRE_EZ = 16,
+ SC_NO_PIXELS_POST_EZ = 17,
+} SC_PERFCNT_SELECT;
+#endif /*ENUMS_SC_PERFCNT_SELECT_H*/
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+#ifndef ENUMS_VGT_DI_PRIM_TYPE_H
+#define ENUMS_VGT_DI_PRIM_TYPE_H
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0,
+ DI_PT_POINTLIST = 1,
+ DI_PT_LINELIST = 2,
+ DI_PT_LINESTRIP = 3,
+ DI_PT_TRILIST = 4,
+ DI_PT_TRIFAN = 5,
+ DI_PT_TRISTRIP = 6,
+ DI_PT_UNUSED_1 = 7,
+ DI_PT_RECTLIST = 8,
+ DI_PT_UNUSED_2 = 9,
+ DI_PT_UNUSED_3 = 10,
+ DI_PT_UNUSED_4 = 11,
+ DI_PT_UNUSED_5 = 12,
+ DI_PT_QUADLIST = 13,
+ DI_PT_QUADSTRIP = 14,
+ DI_PT_POLYGON = 15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+ DI_PT_2D_FILL_RECT_LIST = 20,
+ DI_PT_2D_LINE_STRIP = 21,
+ DI_PT_2D_TRI_STRIP = 22,
+} VGT_DI_PRIM_TYPE;
+#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/
+
+#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H
+#define ENUMS_VGT_DI_SOURCE_SELECT_H
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0,
+ DI_SRC_SEL_IMMEDIATE = 1,
+ DI_SRC_SEL_AUTO_INDEX = 2,
+ DI_SRC_SEL_RESERVED = 3
+} VGT_DI_SOURCE_SELECT;
+#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_INDEX_SIZE_H
+#define ENUMS_VGT_DI_INDEX_SIZE_H
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0,
+ DI_INDEX_SIZE_32_BIT = 1
+} VGT_DI_INDEX_SIZE;
+#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/
+
+#ifndef ENUMS_VGT_DI_SMALL_INDEX_H
+#define ENUMS_VGT_DI_SMALL_INDEX_H
+typedef enum VGT_DI_SMALL_INDEX {
+ DI_USE_INDEX_SIZE = 0,
+ DI_INDEX_SIZE_8_BIT = 1
+} VGT_DI_SMALL_INDEX;
+#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/
+
+#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE {
+ DISABLE_PRE_FETCH_CULL_ENABLE = 0,
+ PRE_FETCH_CULL_ENABLE = 1
+} VGT_DI_PRE_FETCH_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+typedef enum VGT_DI_GRP_CULL_ENABLE {
+ DISABLE_GRP_CULL_ENABLE = 0,
+ GRP_CULL_ENABLE = 1
+} VGT_DI_GRP_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_EVENT_TYPE_H
+#define ENUMS_VGT_EVENT_TYPE_H
+typedef enum VGT_EVENT_TYPE {
+ VS_DEALLOC = 0,
+ PS_DEALLOC = 1,
+ VS_DONE_TS = 2,
+ PS_DONE_TS = 3,
+ CACHE_FLUSH_TS = 4,
+ CONTEXT_DONE = 5,
+ CACHE_FLUSH = 6,
+ VIZQUERY_START = 7,
+ VIZQUERY_END = 8,
+ SC_WAIT_WC = 9,
+ RST_PIX_CNT = 13,
+ RST_VTX_CNT = 14,
+ TILE_FLUSH = 15,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+ ZPASS_DONE = 21,
+ CACHE_FLUSH_AND_INV_EVENT = 22,
+ PERFCOUNTER_START = 23,
+ PERFCOUNTER_STOP = 24,
+ VS_FETCH_DONE = 27,
+} VGT_EVENT_TYPE;
+#endif /*ENUMS_VGT_EVENT_TYPE_H*/
+
+#ifndef ENUMS_VGT_DMA_SWAP_MODE_H
+#define ENUMS_VGT_DMA_SWAP_MODE_H
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0,
+ VGT_DMA_SWAP_16_BIT = 1,
+ VGT_DMA_SWAP_32_BIT = 2,
+ VGT_DMA_SWAP_WORD = 3
+} VGT_DMA_SWAP_MODE;
+#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/
+
+#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H
+#define ENUMS_VGT_PERFCOUNT_SELECT_H
+typedef enum VGT_PERFCOUNT_SELECT {
+ VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+ VGT_SQ_SEND = 1,
+ VGT_SQ_STALLED = 2,
+ VGT_SQ_STARVED_BUSY = 3,
+ VGT_SQ_STARVED_IDLE = 4,
+ VGT_SQ_STATIC = 5,
+ VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+ VGT_PA_CLIP_V_SEND = 7,
+ VGT_PA_CLIP_V_STALLED = 8,
+ VGT_PA_CLIP_V_STARVED_BUSY = 9,
+ VGT_PA_CLIP_V_STARVED_IDLE = 10,
+ VGT_PA_CLIP_V_STATIC = 11,
+ VGT_PA_CLIP_P_SEND = 12,
+ VGT_PA_CLIP_P_STALLED = 13,
+ VGT_PA_CLIP_P_STARVED_BUSY = 14,
+ VGT_PA_CLIP_P_STARVED_IDLE = 15,
+ VGT_PA_CLIP_P_STATIC = 16,
+ VGT_PA_CLIP_S_SEND = 17,
+ VGT_PA_CLIP_S_STALLED = 18,
+ VGT_PA_CLIP_S_STARVED_BUSY = 19,
+ VGT_PA_CLIP_S_STARVED_IDLE = 20,
+ VGT_PA_CLIP_S_STATIC = 21,
+ RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+ RBIU_IMMED_DATA_FIFO_STARVED = 23,
+ RBIU_IMMED_DATA_FIFO_STALLED = 24,
+ RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+ RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+ RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+ RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+ BIN_PRIM_NEAR_CULL = 29,
+ BIN_PRIM_ZERO_CULL = 30,
+ BIN_PRIM_FAR_CULL = 31,
+ BIN_PRIM_BIN_CULL = 32,
+ SPARE33 = 33,
+ SPARE34 = 34,
+ SPARE35 = 35,
+ SPARE36 = 36,
+ SPARE37 = 37,
+ SPARE38 = 38,
+ SPARE39 = 39,
+ TE_SU_IN_VALID = 40,
+ TE_SU_IN_READ = 41,
+ TE_SU_IN_PRIM = 42,
+ TE_SU_IN_EOP = 43,
+ TE_SU_IN_NULL_PRIM = 44,
+ TE_WK_IN_VALID = 45,
+ TE_WK_IN_READ = 46,
+ TE_OUT_PRIM_VALID = 47,
+ TE_OUT_PRIM_READ = 48,
+} VGT_PERFCOUNT_SELECT;
+#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H
+#define ENUMS_TCR_PERFCOUNT_SELECT_H
+typedef enum TCR_PERFCOUNT_SELECT {
+ DGMMPD_IPMUX0_STALL = 0,
+ reserved_46 = 1,
+ reserved_47 = 2,
+ reserved_48 = 3,
+ DGMMPD_IPMUX_ALL_STALL = 4,
+ OPMUX0_L2_WRITES = 5,
+ reserved_49 = 6,
+ reserved_50 = 7,
+ reserved_51 = 8,
+} TCR_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TP_PERFCOUNT_SELECT_H
+#define ENUMS_TP_PERFCOUNT_SELECT_H
+typedef enum TP_PERFCOUNT_SELECT {
+ POINT_QUADS = 0,
+ BILIN_QUADS = 1,
+ ANISO_QUADS = 2,
+ MIP_QUADS = 3,
+ VOL_QUADS = 4,
+ MIP_VOL_QUADS = 5,
+ MIP_ANISO_QUADS = 6,
+ VOL_ANISO_QUADS = 7,
+ ANISO_2_1_QUADS = 8,
+ ANISO_4_1_QUADS = 9,
+ ANISO_6_1_QUADS = 10,
+ ANISO_8_1_QUADS = 11,
+ ANISO_10_1_QUADS = 12,
+ ANISO_12_1_QUADS = 13,
+ ANISO_14_1_QUADS = 14,
+ ANISO_16_1_QUADS = 15,
+ MIP_VOL_ANISO_QUADS = 16,
+ ALIGN_2_QUADS = 17,
+ ALIGN_4_QUADS = 18,
+ PIX_0_QUAD = 19,
+ PIX_1_QUAD = 20,
+ PIX_2_QUAD = 21,
+ PIX_3_QUAD = 22,
+ PIX_4_QUAD = 23,
+ TP_MIPMAP_LOD0 = 24,
+ TP_MIPMAP_LOD1 = 25,
+ TP_MIPMAP_LOD2 = 26,
+ TP_MIPMAP_LOD3 = 27,
+ TP_MIPMAP_LOD4 = 28,
+ TP_MIPMAP_LOD5 = 29,
+ TP_MIPMAP_LOD6 = 30,
+ TP_MIPMAP_LOD7 = 31,
+ TP_MIPMAP_LOD8 = 32,
+ TP_MIPMAP_LOD9 = 33,
+ TP_MIPMAP_LOD10 = 34,
+ TP_MIPMAP_LOD11 = 35,
+ TP_MIPMAP_LOD12 = 36,
+ TP_MIPMAP_LOD13 = 37,
+ TP_MIPMAP_LOD14 = 38,
+} TP_PERFCOUNT_SELECT;
+#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H
+#define ENUMS_TCM_PERFCOUNT_SELECT_H
+typedef enum TCM_PERFCOUNT_SELECT {
+ QUAD0_RD_LAT_FIFO_EMPTY = 0,
+ reserved_01 = 1,
+ reserved_02 = 2,
+ QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+ QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+ QUAD0_RD_LAT_FIFO_FULL = 5,
+ QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+ reserved_07 = 7,
+ reserved_08 = 8,
+ reserved_09 = 9,
+ reserved_10 = 10,
+ reserved_11 = 11,
+ reserved_12 = 12,
+ reserved_13 = 13,
+ reserved_14 = 14,
+ reserved_15 = 15,
+ reserved_16 = 16,
+ reserved_17 = 17,
+ reserved_18 = 18,
+ reserved_19 = 19,
+ reserved_20 = 20,
+ reserved_21 = 21,
+ reserved_22 = 22,
+ reserved_23 = 23,
+ reserved_24 = 24,
+ reserved_25 = 25,
+ reserved_26 = 26,
+ reserved_27 = 27,
+ READ_STARVED_QUAD0 = 28,
+ reserved_29 = 29,
+ reserved_30 = 30,
+ reserved_31 = 31,
+ READ_STARVED = 32,
+ READ_STALLED_QUAD0 = 33,
+ reserved_34 = 34,
+ reserved_35 = 35,
+ reserved_36 = 36,
+ READ_STALLED = 37,
+ VALID_READ_QUAD0 = 38,
+ reserved_39 = 39,
+ reserved_40 = 40,
+ reserved_41 = 41,
+ TC_TP_STARVED_QUAD0 = 42,
+ reserved_43 = 43,
+ reserved_44 = 44,
+ reserved_45 = 45,
+ TC_TP_STARVED = 46,
+} TCM_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H
+#define ENUMS_TCF_PERFCOUNT_SELECT_H
+typedef enum TCF_PERFCOUNT_SELECT {
+ VALID_CYCLES = 0,
+ SINGLE_PHASES = 1,
+ ANISO_PHASES = 2,
+ MIP_PHASES = 3,
+ VOL_PHASES = 4,
+ MIP_VOL_PHASES = 5,
+ MIP_ANISO_PHASES = 6,
+ VOL_ANISO_PHASES = 7,
+ ANISO_2_1_PHASES = 8,
+ ANISO_4_1_PHASES = 9,
+ ANISO_6_1_PHASES = 10,
+ ANISO_8_1_PHASES = 11,
+ ANISO_10_1_PHASES = 12,
+ ANISO_12_1_PHASES = 13,
+ ANISO_14_1_PHASES = 14,
+ ANISO_16_1_PHASES = 15,
+ MIP_VOL_ANISO_PHASES = 16,
+ ALIGN_2_PHASES = 17,
+ ALIGN_4_PHASES = 18,
+ TPC_BUSY = 19,
+ TPC_STALLED = 20,
+ TPC_STARVED = 21,
+ TPC_WORKING = 22,
+ TPC_WALKER_BUSY = 23,
+ TPC_WALKER_STALLED = 24,
+ TPC_WALKER_WORKING = 25,
+ TPC_ALIGNER_BUSY = 26,
+ TPC_ALIGNER_STALLED = 27,
+ TPC_ALIGNER_STALLED_BY_BLEND = 28,
+ TPC_ALIGNER_STALLED_BY_CACHE = 29,
+ TPC_ALIGNER_WORKING = 30,
+ TPC_BLEND_BUSY = 31,
+ TPC_BLEND_SYNC = 32,
+ TPC_BLEND_STARVED = 33,
+ TPC_BLEND_WORKING = 34,
+ OPCODE_0x00 = 35,
+ OPCODE_0x01 = 36,
+ OPCODE_0x04 = 37,
+ OPCODE_0x10 = 38,
+ OPCODE_0x11 = 39,
+ OPCODE_0x12 = 40,
+ OPCODE_0x13 = 41,
+ OPCODE_0x18 = 42,
+ OPCODE_0x19 = 43,
+ OPCODE_0x1A = 44,
+ OPCODE_OTHER = 45,
+ IN_FIFO_0_EMPTY = 56,
+ IN_FIFO_0_LT_HALF_FULL = 57,
+ IN_FIFO_0_HALF_FULL = 58,
+ IN_FIFO_0_FULL = 59,
+ IN_FIFO_TPC_EMPTY = 72,
+ IN_FIFO_TPC_LT_HALF_FULL = 73,
+ IN_FIFO_TPC_HALF_FULL = 74,
+ IN_FIFO_TPC_FULL = 75,
+ TPC_TC_XFC = 76,
+ TPC_TC_STATE = 77,
+ TC_STALL = 78,
+ QUAD0_TAPS = 79,
+ QUADS = 83,
+ TCA_SYNC_STALL = 84,
+ TAG_STALL = 85,
+ TCB_SYNC_STALL = 88,
+ TCA_VALID = 89,
+ PROBES_VALID = 90,
+ MISS_STALL = 91,
+ FETCH_FIFO_STALL = 92,
+ TCO_STALL = 93,
+ ANY_STALL = 94,
+ TAG_MISSES = 95,
+ TAG_HITS = 96,
+ SUB_TAG_MISSES = 97,
+ SET0_INVALIDATES = 98,
+ SET1_INVALIDATES = 99,
+ SET2_INVALIDATES = 100,
+ SET3_INVALIDATES = 101,
+ SET0_TAG_MISSES = 102,
+ SET1_TAG_MISSES = 103,
+ SET2_TAG_MISSES = 104,
+ SET3_TAG_MISSES = 105,
+ SET0_TAG_HITS = 106,
+ SET1_TAG_HITS = 107,
+ SET2_TAG_HITS = 108,
+ SET3_TAG_HITS = 109,
+ SET0_SUB_TAG_MISSES = 110,
+ SET1_SUB_TAG_MISSES = 111,
+ SET2_SUB_TAG_MISSES = 112,
+ SET3_SUB_TAG_MISSES = 113,
+ SET0_EVICT1 = 114,
+ SET0_EVICT2 = 115,
+ SET0_EVICT3 = 116,
+ SET0_EVICT4 = 117,
+ SET0_EVICT5 = 118,
+ SET0_EVICT6 = 119,
+ SET0_EVICT7 = 120,
+ SET0_EVICT8 = 121,
+ SET1_EVICT1 = 130,
+ SET1_EVICT2 = 131,
+ SET1_EVICT3 = 132,
+ SET1_EVICT4 = 133,
+ SET1_EVICT5 = 134,
+ SET1_EVICT6 = 135,
+ SET1_EVICT7 = 136,
+ SET1_EVICT8 = 137,
+ SET2_EVICT1 = 146,
+ SET2_EVICT2 = 147,
+ SET2_EVICT3 = 148,
+ SET2_EVICT4 = 149,
+ SET2_EVICT5 = 150,
+ SET2_EVICT6 = 151,
+ SET2_EVICT7 = 152,
+ SET2_EVICT8 = 153,
+ SET3_EVICT1 = 162,
+ SET3_EVICT2 = 163,
+ SET3_EVICT3 = 164,
+ SET3_EVICT4 = 165,
+ SET3_EVICT5 = 166,
+ SET3_EVICT6 = 167,
+ SET3_EVICT7 = 168,
+ SET3_EVICT8 = 169,
+ FF_EMPTY = 178,
+ FF_LT_HALF_FULL = 179,
+ FF_HALF_FULL = 180,
+ FF_FULL = 181,
+ FF_XFC = 182,
+ FF_STALLED = 183,
+ FG_MASKS = 184,
+ FG_LEFT_MASKS = 185,
+ FG_LEFT_MASK_STALLED = 186,
+ FG_LEFT_NOT_DONE_STALL = 187,
+ FG_LEFT_FG_STALL = 188,
+ FG_LEFT_SECTORS = 189,
+ FG0_REQUESTS = 195,
+ FG0_STALLED = 196,
+ MEM_REQ512 = 199,
+ MEM_REQ_SENT = 200,
+ MEM_LOCAL_READ_REQ = 202,
+ TC0_MH_STALLED = 203,
+} TCF_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+#ifndef ENUMS_SQ_PERFCNT_SELECT_H
+#define ENUMS_SQ_PERFCNT_SELECT_H
+typedef enum SQ_PERFCNT_SELECT {
+ SQ_PIXEL_VECTORS_SUB = 0,
+ SQ_VERTEX_VECTORS_SUB = 1,
+ SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+ SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+ SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+ SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+ SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+ SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+ SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+ SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+ SQ_EXPORT_CYCLES = 10,
+ SQ_ALU_CST_WRITTEN = 11,
+ SQ_TEX_CST_WRITTEN = 12,
+ SQ_ALU_CST_STALL = 13,
+ SQ_ALU_TEX_STALL = 14,
+ SQ_INST_WRITTEN = 15,
+ SQ_BOOLEAN_WRITTEN = 16,
+ SQ_LOOPS_WRITTEN = 17,
+ SQ_PIXEL_SWAP_IN = 18,
+ SQ_PIXEL_SWAP_OUT = 19,
+ SQ_VERTEX_SWAP_IN = 20,
+ SQ_VERTEX_SWAP_OUT = 21,
+ SQ_ALU_VTX_INST_ISSUED = 22,
+ SQ_TEX_VTX_INST_ISSUED = 23,
+ SQ_VC_VTX_INST_ISSUED = 24,
+ SQ_CF_VTX_INST_ISSUED = 25,
+ SQ_ALU_PIX_INST_ISSUED = 26,
+ SQ_TEX_PIX_INST_ISSUED = 27,
+ SQ_VC_PIX_INST_ISSUED = 28,
+ SQ_CF_PIX_INST_ISSUED = 29,
+ SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+ SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+ SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+ SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+ SQ_ALU_NOPS = 34,
+ SQ_PRED_SKIP = 35,
+ SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+ SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+ SQ_SYNC_TEX_STALL_VTX = 38,
+ SQ_SYNC_VC_STALL_VTX = 39,
+ SQ_CONSTANTS_USED_SIMD0 = 40,
+ SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+ SQ_GPR_STALL_VTX = 42,
+ SQ_GPR_STALL_PIX = 43,
+ SQ_VTX_RS_STALL = 44,
+ SQ_PIX_RS_STALL = 45,
+ SQ_SX_PC_FULL   = 46,
+ SQ_SX_EXP_BUFF_FULL = 47,
+ SQ_SX_POS_BUFF_FULL = 48,
+ SQ_INTERP_QUADS = 49,
+ SQ_INTERP_ACTIVE = 50,
+ SQ_IN_PIXEL_STALL = 51,
+ SQ_IN_VTX_STALL = 52,
+ SQ_VTX_CNT = 53,
+ SQ_VTX_VECTOR2 = 54,
+ SQ_VTX_VECTOR3 = 55,
+ SQ_VTX_VECTOR4 = 56,
+ SQ_PIXEL_VECTOR1 = 57,
+ SQ_PIXEL_VECTOR23 = 58,
+ SQ_PIXEL_VECTOR4 = 59,
+ SQ_CONSTANTS_USED_SIMD1 = 60,
+ SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+ SQ_SX_MEM_EXP_FULL = 62,
+ SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+ SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+ SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+ SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+ SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+ SQ_ALU1_ACTIVE_VTX_SIMD3 = 68,
+ SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+ SQ_ALU1_ACTIVE_PIX_SIMD3 = 70,
+ SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+ SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+ SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+ SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+ SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+ SQ_SYNC_ALU_STALL_SIMD3_VTX = 76,
+ SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+ SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+ SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+ SQ_SYNC_ALU_STALL_SIMD3_PIX = 80,
+ SQ_SYNC_TEX_STALL_PIX = 81,
+ SQ_SYNC_VC_STALL_PIX = 82,
+ SQ_CONSTANTS_USED_SIMD2 = 83,
+ SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+ SQ_CONSTANTS_USED_SIMD3 = 85,
+ SQ_CONSTANTS_SENT_SP_SIMD3 = 86,
+ SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+ SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+ SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+ SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+ SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+ SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+ SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+ SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+ VC_PERF_STATIC = 95,
+ VC_PERF_STALLED = 96,
+ VC_PERF_STARVED = 97,
+ VC_PERF_SEND = 98,
+ VC_PERF_ACTUAL_STARVED = 99,
+ PIXEL_THREAD_0_ACTIVE   = 100,
+ VERTEX_THREAD_0_ACTIVE  = 101,
+ PIXEL_THREAD_0_NUMBER   = 102,
+ VERTEX_THREAD_0_NUMBER  = 103,
+ VERTEX_EVENT_NUMBER     = 104,
+ PIXEL_EVENT_NUMBER  = 105,
+ PTRBUFF_EF_PUSH = 106,
+ PTRBUFF_EF_POP_EVENT = 107,
+ PTRBUFF_EF_POP_NEW_VTX = 108,
+ PTRBUFF_EF_POP_DEALLOC = 109,
+ PTRBUFF_EF_POP_PVECTOR = 110,
+ PTRBUFF_EF_POP_PVECTOR_X = 111,
+ PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+ PTRBUFF_PB_DEALLOC = 113,
+ PTRBUFF_PI_STATE_PPB_POP = 114,
+ PTRBUFF_PI_RTR = 115,
+ PTRBUFF_PI_READ_EN = 116,
+ PTRBUFF_PI_BUFF_SWAP = 117,
+ PTRBUFF_SQ_FREE_BUFF = 118,
+ PTRBUFF_SQ_DEC = 119,
+ PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+ PTRBUFF_SC_VALID_IJ_XFER = 121,
+ PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+ PTRBUFF_QUAL_NEW_VECTOR = 123,
+ PTRBUFF_QUAL_EVENT = 124,
+ PTRBUFF_END_BUFFER = 125,
+ PTRBUFF_FILL_QUAD = 126,
+ VERTS_WRITTEN_SPI = 127,
+ TP_FETCH_INSTR_EXEC = 128,
+ TP_FETCH_INSTR_REQ = 129,
+ TP_DATA_RETURN = 130,
+ SPI_WRITE_CYCLES_SP = 131,
+ SPI_WRITES_SP = 132,
+ SP_ALU_INSTR_EXEC = 133,
+ SP_CONST_ADDR_TO_SQ = 134,
+ SP_PRED_KILLS_TO_SQ = 135,
+ SP_EXPORT_CYCLES_TO_SX = 136,
+ SP_EXPORTS_TO_SX = 137,
+ SQ_CYCLES_ELAPSED = 138,
+ SQ_TCFS_OPT_ALLOC_EXEC = 139,
+ SQ_TCFS_NO_OPT_ALLOC = 140,
+ SQ_ALU0_NO_OPT_ALLOC = 141,
+ SQ_ALU1_NO_OPT_ALLOC = 142,
+ SQ_TCFS_ARB_XFC_CNT = 143,
+ SQ_ALU0_ARB_XFC_CNT = 144,
+ SQ_ALU1_ARB_XFC_CNT = 145,
+ SQ_TCFS_CFS_UPDATE_CNT = 146,
+ SQ_ALU0_CFS_UPDATE_CNT = 147,
+ SQ_ALU1_CFS_UPDATE_CNT = 148,
+ SQ_VTX_PUSH_THREAD_CNT = 149,
+ SQ_VTX_POP_THREAD_CNT = 150,
+ SQ_PIX_PUSH_THREAD_CNT = 151,
+ SQ_PIX_POP_THREAD_CNT = 152,
+ SQ_PIX_TOTAL = 153,
+ SQ_PIX_KILLED = 154,
+} SQ_PERFCNT_SELECT;
+#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SX_PERFCNT_SELECT_H
+#define ENUMS_SX_PERFCNT_SELECT_H
+typedef enum SX_PERFCNT_SELECT {
+ SX_EXPORT_VECTORS = 0,
+ SX_DUMMY_QUADS  = 1,
+ SX_ALPHA_FAIL = 2,
+ SX_RB_QUAD_BUSY = 3,
+ SX_RB_COLOR_BUSY = 4,
+ SX_RB_QUAD_STALL = 5,
+ SX_RB_COLOR_STALL = 6,
+} SX_PERFCNT_SELECT;
+#endif /*ENUMS_SX_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_Abs_modifier_H
+#define ENUMS_Abs_modifier_H
+typedef enum Abs_modifier {
+ NO_ABS_MOD = 0,
+ ABS_MOD = 1
+} Abs_modifier;
+#endif /*ENUMS_Abs_modifier_H*/
+
+#ifndef ENUMS_Exporting_H
+#define ENUMS_Exporting_H
+typedef enum Exporting {
+ NOT_EXPORTING = 0,
+ EXPORTING = 1
+} Exporting;
+#endif /*ENUMS_Exporting_H*/
+
+#ifndef ENUMS_ScalarOpcode_H
+#define ENUMS_ScalarOpcode_H
+typedef enum ScalarOpcode {
+ ADDs = 0,
+ ADD_PREVs = 1,
+ MULs = 2,
+ MUL_PREVs = 3,
+ MUL_PREV2s = 4,
+ MAXs = 5,
+ MINs = 6,
+ SETEs = 7,
+ SETGTs = 8,
+ SETGTEs = 9,
+ SETNEs = 10,
+ FRACs = 11,
+ TRUNCs = 12,
+ FLOORs = 13,
+ EXP_IEEE = 14,
+ LOG_CLAMP = 15,
+ LOG_IEEE = 16,
+ RECIP_CLAMP = 17,
+ RECIP_FF = 18,
+ RECIP_IEEE = 19,
+ RECIPSQ_CLAMP = 20,
+ RECIPSQ_FF = 21,
+ RECIPSQ_IEEE = 22,
+ MOVAs = 23,
+ MOVA_FLOORs = 24,
+ SUBs = 25,
+ SUB_PREVs = 26,
+ PRED_SETEs = 27,
+ PRED_SETNEs = 28,
+ PRED_SETGTs = 29,
+ PRED_SETGTEs = 30,
+ PRED_SET_INVs = 31,
+ PRED_SET_POPs = 32,
+ PRED_SET_CLRs = 33,
+ PRED_SET_RESTOREs = 34,
+ KILLEs = 35,
+ KILLGTs = 36,
+ KILLGTEs = 37,
+ KILLNEs = 38,
+ KILLONEs = 39,
+ SQRT_IEEE = 40,
+ MUL_CONST_0 = 42,
+ MUL_CONST_1 = 43,
+ ADD_CONST_0 = 44,
+ ADD_CONST_1 = 45,
+ SUB_CONST_0 = 46,
+ SUB_CONST_1 = 47,
+ SIN = 48,
+ COS = 49,
+ RETAIN_PREV = 50,
+} ScalarOpcode;
+#endif /*ENUMS_ScalarOpcode_H*/
+
+#ifndef ENUMS_SwizzleType_H
+#define ENUMS_SwizzleType_H
+typedef enum SwizzleType {
+ NO_SWIZZLE = 0,
+ SHIFT_RIGHT_1 = 1,
+ SHIFT_RIGHT_2 = 2,
+ SHIFT_RIGHT_3 = 3
+} SwizzleType;
+#endif /*ENUMS_SwizzleType_H*/
+
+#ifndef ENUMS_InputModifier_H
+#define ENUMS_InputModifier_H
+typedef enum InputModifier {
+ NIL = 0,
+ NEGATE = 1
+} InputModifier;
+#endif /*ENUMS_InputModifier_H*/
+
+#ifndef ENUMS_PredicateSelect_H
+#define ENUMS_PredicateSelect_H
+typedef enum PredicateSelect {
+ NO_PREDICATION = 0,
+ PREDICATE_QUAD = 1,
+ PREDICATED_2 = 2,
+ PREDICATED_3 = 3
+} PredicateSelect;
+#endif /*ENUMS_PredicateSelect_H*/
+
+#ifndef ENUMS_OperandSelect1_H
+#define ENUMS_OperandSelect1_H
+typedef enum OperandSelect1 {
+ ABSOLUTE_REG = 0,
+ RELATIVE_REG = 1
+} OperandSelect1;
+#endif /*ENUMS_OperandSelect1_H*/
+
+#ifndef ENUMS_VectorOpcode_H
+#define ENUMS_VectorOpcode_H
+typedef enum VectorOpcode {
+ ADDv = 0,
+ MULv = 1,
+ MAXv = 2,
+ MINv = 3,
+ SETEv = 4,
+ SETGTv = 5,
+ SETGTEv = 6,
+ SETNEv = 7,
+ FRACv = 8,
+ TRUNCv = 9,
+ FLOORv = 10,
+ MULADDv = 11,
+ CNDEv = 12,
+ CNDGTEv = 13,
+ CNDGTv = 14,
+ DOT4v = 15,
+ DOT3v = 16,
+ DOT2ADDv = 17,
+ CUBEv = 18,
+ MAX4v = 19,
+ PRED_SETE_PUSHv = 20,
+ PRED_SETNE_PUSHv = 21,
+ PRED_SETGT_PUSHv = 22,
+ PRED_SETGTE_PUSHv = 23,
+ KILLEv = 24,
+ KILLGTv = 25,
+ KILLGTEv = 26,
+ KILLNEv = 27,
+ DSTv = 28,
+ MOVAv = 29,
+} VectorOpcode;
+#endif /*ENUMS_VectorOpcode_H*/
+
+#ifndef ENUMS_OperandSelect0_H
+#define ENUMS_OperandSelect0_H
+typedef enum OperandSelect0 {
+ CONSTANT = 0,
+ NON_CONSTANT = 1
+} OperandSelect0;
+#endif /*ENUMS_OperandSelect0_H*/
+
+#ifndef ENUMS_Ressource_type_H
+#define ENUMS_Ressource_type_H
+typedef enum Ressource_type {
+ ALU = 0,
+ TEXTURE = 1
+} Ressource_type;
+#endif /*ENUMS_Ressource_type_H*/
+
+#ifndef ENUMS_Instruction_serial_H
+#define ENUMS_Instruction_serial_H
+typedef enum Instruction_serial {
+ NOT_SERIAL = 0,
+ SERIAL = 1
+} Instruction_serial;
+#endif /*ENUMS_Instruction_serial_H*/
+
+#ifndef ENUMS_VC_type_H
+#define ENUMS_VC_type_H
+typedef enum VC_type {
+ ALU_TP_REQUEST = 0,
+ VC_REQUEST = 1
+} VC_type;
+#endif /*ENUMS_VC_type_H*/
+
+#ifndef ENUMS_Addressing_H
+#define ENUMS_Addressing_H
+typedef enum Addressing {
+ RELATIVE_ADDR = 0,
+ ABSOLUTE_ADDR = 1
+} Addressing;
+#endif /*ENUMS_Addressing_H*/
+
+#ifndef ENUMS_CFOpcode_H
+#define ENUMS_CFOpcode_H
+typedef enum CFOpcode {
+ NOP = 0,
+ EXECUTE = 1,
+ EXECUTE_END = 2,
+ COND_EXECUTE = 3,
+ COND_EXECUTE_END = 4,
+ COND_PRED_EXECUTE = 5,
+ COND_PRED_EXECUTE_END = 6,
+ LOOP_START = 7,
+ LOOP_END = 8,
+ COND_CALL = 9,
+ RETURN = 10,
+ COND_JMP = 11,
+ ALLOCATE = 12,
+ COND_EXECUTE_PRED_CLEAN = 13,
+ COND_EXECUTE_PRED_CLEAN_END = 14,
+ MARK_VS_FETCH_DONE = 15
+} CFOpcode;
+#endif /*ENUMS_CFOpcode_H*/
+
+#ifndef ENUMS_Allocation_type_H
+#define ENUMS_Allocation_type_H
+typedef enum Allocation_type {
+ SQ_NO_ALLOC = 0,
+ SQ_POSITION = 1,
+ SQ_PARAMETER_PIXEL = 2,
+ SQ_MEMORY = 3
+} Allocation_type;
+#endif /*ENUMS_Allocation_type_H*/
+
+#ifndef ENUMS_TexInstOpcode_H
+#define ENUMS_TexInstOpcode_H
+typedef enum TexInstOpcode {
+ TEX_INST_FETCH = 1,
+ TEX_INST_RESERVED_1 = 2,
+ TEX_INST_RESERVED_2 = 3,
+ TEX_INST_RESERVED_3 = 4,
+ TEX_INST_GET_BORDER_COLOR_FRAC = 16,
+ TEX_INST_GET_COMP_TEX_LOD = 17,
+ TEX_INST_GET_GRADIENTS = 18,
+ TEX_INST_GET_WEIGHTS = 19,
+ TEX_INST_SET_TEX_LOD = 24,
+ TEX_INST_SET_GRADIENTS_H = 25,
+ TEX_INST_SET_GRADIENTS_V = 26,
+ TEX_INST_RESERVED_4 = 27,
+} TexInstOpcode;
+#endif /*ENUMS_TexInstOpcode_H*/
+
+#ifndef ENUMS_Addressmode_H
+#define ENUMS_Addressmode_H
+typedef enum Addressmode {
+ LOGICAL = 0,
+ LOOP_RELATIVE = 1
+} Addressmode;
+#endif /*ENUMS_Addressmode_H*/
+
+#ifndef ENUMS_TexCoordDenorm_H
+#define ENUMS_TexCoordDenorm_H
+typedef enum TexCoordDenorm {
+ TEX_COORD_NORMALIZED = 0,
+ TEX_COORD_UNNORMALIZED = 1
+} TexCoordDenorm;
+#endif /*ENUMS_TexCoordDenorm_H*/
+
+#ifndef ENUMS_SrcSel_H
+#define ENUMS_SrcSel_H
+typedef enum SrcSel {
+ SRC_SEL_X = 0,
+ SRC_SEL_Y = 1,
+ SRC_SEL_Z = 2,
+ SRC_SEL_W = 3
+} SrcSel;
+#endif /*ENUMS_SrcSel_H*/
+
+#ifndef ENUMS_DstSel_H
+#define ENUMS_DstSel_H
+typedef enum DstSel {
+ DST_SEL_X = 0,
+ DST_SEL_Y = 1,
+ DST_SEL_Z = 2,
+ DST_SEL_W = 3,
+ DST_SEL_0 = 4,
+ DST_SEL_1 = 5,
+ DST_SEL_RSVD = 6,
+ DST_SEL_MASK = 7
+} DstSel;
+#endif /*ENUMS_DstSel_H*/
+
+#ifndef ENUMS_MagFilter_H
+#define ENUMS_MagFilter_H
+typedef enum MagFilter {
+ MAG_FILTER_POINT = 0,
+ MAG_FILTER_LINEAR = 1,
+ MAG_FILTER_RESERVED_0 = 2,
+ MAG_FILTER_USE_FETCH_CONST = 3
+} MagFilter;
+#endif /*ENUMS_MagFilter_H*/
+
+#ifndef ENUMS_MinFilter_H
+#define ENUMS_MinFilter_H
+typedef enum MinFilter {
+ MIN_FILTER_POINT = 0,
+ MIN_FILTER_LINEAR = 1,
+ MIN_FILTER_RESERVED_0 = 2,
+ MIN_FILTER_USE_FETCH_CONST = 3
+} MinFilter;
+#endif /*ENUMS_MinFilter_H*/
+
+#ifndef ENUMS_MipFilter_H
+#define ENUMS_MipFilter_H
+typedef enum MipFilter {
+ MIP_FILTER_POINT = 0,
+ MIP_FILTER_LINEAR = 1,
+ MIP_FILTER_BASEMAP = 2,
+ MIP_FILTER_USE_FETCH_CONST = 3
+} MipFilter;
+#endif /*ENUMS_MipFilter_H*/
+
+#ifndef ENUMS_AnisoFilter_H
+#define ENUMS_AnisoFilter_H
+typedef enum AnisoFilter {
+ ANISO_FILTER_DISABLED = 0,
+ ANISO_FILTER_MAX_1_1 = 1,
+ ANISO_FILTER_MAX_2_1 = 2,
+ ANISO_FILTER_MAX_4_1 = 3,
+ ANISO_FILTER_MAX_8_1 = 4,
+ ANISO_FILTER_MAX_16_1 = 5,
+ ANISO_FILTER_USE_FETCH_CONST = 7
+} AnisoFilter;
+#endif /*ENUMS_AnisoFilter_H*/
+
+#ifndef ENUMS_ArbitraryFilter_H
+#define ENUMS_ArbitraryFilter_H
+typedef enum ArbitraryFilter {
+ ARBITRARY_FILTER_2X4_SYM = 0,
+ ARBITRARY_FILTER_2X4_ASYM = 1,
+ ARBITRARY_FILTER_4X2_SYM = 2,
+ ARBITRARY_FILTER_4X2_ASYM = 3,
+ ARBITRARY_FILTER_4X4_SYM = 4,
+ ARBITRARY_FILTER_4X4_ASYM = 5,
+ ARBITRARY_FILTER_USE_FETCH_CONST = 7
+} ArbitraryFilter;
+#endif /*ENUMS_ArbitraryFilter_H*/
+
+#ifndef ENUMS_VolMagFilter_H
+#define ENUMS_VolMagFilter_H
+typedef enum VolMagFilter {
+ VOL_MAG_FILTER_POINT = 0,
+ VOL_MAG_FILTER_LINEAR = 1,
+ VOL_MAG_FILTER_USE_FETCH_CONST = 3
+} VolMagFilter;
+#endif /*ENUMS_VolMagFilter_H*/
+
+#ifndef ENUMS_VolMinFilter_H
+#define ENUMS_VolMinFilter_H
+typedef enum VolMinFilter {
+ VOL_MIN_FILTER_POINT = 0,
+ VOL_MIN_FILTER_LINEAR = 1,
+ VOL_MIN_FILTER_USE_FETCH_CONST = 3
+} VolMinFilter;
+#endif /*ENUMS_VolMinFilter_H*/
+
+#ifndef ENUMS_PredSelect_H
+#define ENUMS_PredSelect_H
+typedef enum PredSelect {
+ NOT_PREDICATED = 0,
+ PREDICATED = 1
+} PredSelect;
+#endif /*ENUMS_PredSelect_H*/
+
+#ifndef ENUMS_SampleLocation_H
+#define ENUMS_SampleLocation_H
+typedef enum SampleLocation {
+ SAMPLE_CENTROID = 0,
+ SAMPLE_CENTER = 1
+} SampleLocation;
+#endif /*ENUMS_SampleLocation_H*/
+
+#ifndef ENUMS_VertexMode_H
+#define ENUMS_VertexMode_H
+typedef enum VertexMode {
+ POSITION_1_VECTOR = 0,
+ POSITION_2_VECTORS_UNUSED = 1,
+ POSITION_2_VECTORS_SPRITE = 2,
+ POSITION_2_VECTORS_EDGE = 3,
+ POSITION_2_VECTORS_KILL = 4,
+ POSITION_2_VECTORS_SPRITE_KILL = 5,
+ POSITION_2_VECTORS_EDGE_KILL = 6,
+ MULTIPASS = 7
+} VertexMode;
+#endif /*ENUMS_VertexMode_H*/
+
+#ifndef ENUMS_Sample_Cntl_H
+#define ENUMS_Sample_Cntl_H
+typedef enum Sample_Cntl {
+ CENTROIDS_ONLY = 0,
+ CENTERS_ONLY = 1,
+ CENTROIDS_AND_CENTERS = 2,
+ UNDEF = 3
+} Sample_Cntl;
+#endif /*ENUMS_Sample_Cntl_H*/
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+#ifndef ENUMS_MhPerfEncode_H
+#define ENUMS_MhPerfEncode_H
+typedef enum MhPerfEncode {
+ CP_R0_REQUESTS = 0,
+ CP_R1_REQUESTS = 1,
+ CP_R2_REQUESTS = 2,
+ CP_R3_REQUESTS = 3,
+ CP_R4_REQUESTS = 4,
+ CP_TOTAL_READ_REQUESTS = 5,
+ CP_W_REQUESTS = 6,
+ CP_TOTAL_REQUESTS = 7,
+ CP_DATA_BYTES_WRITTEN = 8,
+ CP_WRITE_CLEAN_RESPONSES = 9,
+ CP_R0_READ_BURSTS_RECEIVED = 10,
+ CP_R1_READ_BURSTS_RECEIVED = 11,
+ CP_R2_READ_BURSTS_RECEIVED = 12,
+ CP_R3_READ_BURSTS_RECEIVED = 13,
+ CP_R4_READ_BURSTS_RECEIVED = 14,
+ CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+ CP_R0_DATA_BEATS_READ = 16,
+ CP_R1_DATA_BEATS_READ = 17,
+ CP_R2_DATA_BEATS_READ = 18,
+ CP_R3_DATA_BEATS_READ = 19,
+ CP_R4_DATA_BEATS_READ = 20,
+ CP_TOTAL_DATA_BEATS_READ = 21,
+ VGT_R0_REQUESTS = 22,
+ VGT_R1_REQUESTS = 23,
+ VGT_TOTAL_REQUESTS = 24,
+ VGT_R0_READ_BURSTS_RECEIVED = 25,
+ VGT_R1_READ_BURSTS_RECEIVED = 26,
+ VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+ VGT_R0_DATA_BEATS_READ = 28,
+ VGT_R1_DATA_BEATS_READ = 29,
+ VGT_TOTAL_DATA_BEATS_READ = 30,
+ TC_REQUESTS = 31,
+ TC_ROQ_REQUESTS = 32,
+ TC_INFO_SENT = 33,
+ TC_READ_BURSTS_RECEIVED = 34,
+ TC_DATA_BEATS_READ = 35,
+ TCD_BURSTS_READ = 36,
+ RB_REQUESTS = 37,
+ RB_DATA_BYTES_WRITTEN = 38,
+ RB_WRITE_CLEAN_RESPONSES = 39,
+ AXI_READ_REQUESTS_ID_0 = 40,
+ AXI_READ_REQUESTS_ID_1 = 41,
+ AXI_READ_REQUESTS_ID_2 = 42,
+ AXI_READ_REQUESTS_ID_3 = 43,
+ AXI_READ_REQUESTS_ID_4 = 44,
+ AXI_READ_REQUESTS_ID_5 = 45,
+ AXI_READ_REQUESTS_ID_6 = 46,
+ AXI_READ_REQUESTS_ID_7 = 47,
+ AXI_TOTAL_READ_REQUESTS = 48,
+ AXI_WRITE_REQUESTS_ID_0 = 49,
+ AXI_WRITE_REQUESTS_ID_1 = 50,
+ AXI_WRITE_REQUESTS_ID_2 = 51,
+ AXI_WRITE_REQUESTS_ID_3 = 52,
+ AXI_WRITE_REQUESTS_ID_4 = 53,
+ AXI_WRITE_REQUESTS_ID_5 = 54,
+ AXI_WRITE_REQUESTS_ID_6 = 55,
+ AXI_WRITE_REQUESTS_ID_7 = 56,
+ AXI_TOTAL_WRITE_REQUESTS = 57,
+ AXI_TOTAL_REQUESTS_ID_0 = 58,
+ AXI_TOTAL_REQUESTS_ID_1 = 59,
+ AXI_TOTAL_REQUESTS_ID_2 = 60,
+ AXI_TOTAL_REQUESTS_ID_3 = 61,
+ AXI_TOTAL_REQUESTS_ID_4 = 62,
+ AXI_TOTAL_REQUESTS_ID_5 = 63,
+ AXI_TOTAL_REQUESTS_ID_6 = 64,
+ AXI_TOTAL_REQUESTS_ID_7 = 65,
+ AXI_TOTAL_REQUESTS = 66,
+ AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+ AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+ AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+ AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+ AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+ AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+ AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+ AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+ AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+ AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+ AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+ AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+ AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+ AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+ AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+ AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+ AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+ AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+ AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+ AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+ AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+ TOTAL_MMU_MISSES = 112,
+ MMU_READ_MISSES = 113,
+ MMU_WRITE_MISSES = 114,
+ TOTAL_MMU_HITS = 115,
+ MMU_READ_HITS = 116,
+ MMU_WRITE_HITS = 117,
+ SPLIT_MODE_TC_HITS = 118,
+ SPLIT_MODE_TC_MISSES = 119,
+ SPLIT_MODE_NON_TC_HITS = 120,
+ SPLIT_MODE_NON_TC_MISSES = 121,
+ STALL_AWAITING_TLB_MISS_FETCH = 122,
+ MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+ MMU_TLB_MISS_DATA_BEATS_READ = 124,
+ CP_CYCLES_HELD_OFF = 125,
+ VGT_CYCLES_HELD_OFF = 126,
+ TC_CYCLES_HELD_OFF = 127,
+ TC_ROQ_CYCLES_HELD_OFF = 128,
+ TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+ RB_CYCLES_HELD_OFF = 130,
+ TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+ TLB_MISS_CYCLES_HELD_OFF = 132,
+ AXI_READ_REQUEST_HELD_OFF = 133,
+ AXI_WRITE_REQUEST_HELD_OFF = 134,
+ AXI_REQUEST_HELD_OFF = 135,
+ AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+ AXI_WRITE_DATA_HELD_OFF = 137,
+ CP_SAME_PAGE_BANK_REQUESTS = 138,
+ VGT_SAME_PAGE_BANK_REQUESTS = 139,
+ TC_SAME_PAGE_BANK_REQUESTS = 140,
+ TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+ RB_SAME_PAGE_BANK_REQUESTS = 142,
+ TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+ CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+ VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+ TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+ RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+ TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+ TOTAL_MH_READ_REQUESTS = 149,
+ TOTAL_MH_WRITE_REQUESTS = 150,
+ TOTAL_MH_REQUESTS = 151,
+ MH_BUSY = 152,
+ CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+ VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+ TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+ RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+ TC_ROQ_N_VALID_ENTRIES = 157,
+ ARQ_N_ENTRIES = 158,
+ WDB_N_ENTRIES = 159,
+ MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+ MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+ MC_TOTAL_READ_REQUESTS = 162,
+ ELAPSED_CYCLES_MH_GATED_CLK = 163,
+} MhPerfEncode;
+#endif /*ENUMS_MhPerfEncode_H*/
+
+#ifndef ENUMS_MmuClntBeh_H
+#define ENUMS_MmuClntBeh_H
+typedef enum MmuClntBeh {
+ BEH_NEVR = 0,
+ BEH_TRAN_RNG = 1,
+ BEH_TRAN_FLT = 2,
+} MmuClntBeh;
+#endif /*ENUMS_MmuClntBeh_H*/
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H
+#define ENUMS_RBBM_PERFCOUNT1_SEL_H
+typedef enum RBBM_PERFCOUNT1_SEL {
+ RBBM1_COUNT = 0,
+ RBBM1_NRT_BUSY = 1,
+ RBBM1_RB_BUSY = 2,
+ RBBM1_SQ_CNTX0_BUSY = 3,
+ RBBM1_SQ_CNTX17_BUSY = 4,
+ RBBM1_VGT_BUSY = 5,
+ RBBM1_VGT_NODMA_BUSY = 6,
+ RBBM1_PA_BUSY = 7,
+ RBBM1_SC_CNTX_BUSY = 8,
+ RBBM1_TPC_BUSY = 9,
+ RBBM1_TC_BUSY = 10,
+ RBBM1_SX_BUSY = 11,
+ RBBM1_CP_COHER_BUSY = 12,
+ RBBM1_CP_NRT_BUSY = 13,
+ RBBM1_GFX_IDLE_STALL = 14,
+ RBBM1_INTERRUPT = 15,
+} RBBM_PERFCOUNT1_SEL;
+#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+#ifndef ENUMS_CP_PERFCOUNT_SEL_H
+#define ENUMS_CP_PERFCOUNT_SEL_H
+typedef enum CP_PERFCOUNT_SEL {
+ ALWAYS_COUNT = 0,
+ TRANS_FIFO_FULL = 1,
+ TRANS_FIFO_AF = 2,
+ RCIU_PFPTRANS_WAIT = 3,
+ Reserved_04 = 4,
+ Reserved_05 = 5,
+ RCIU_NRTTRANS_WAIT = 6,
+ Reserved_07 = 7,
+ CSF_NRT_READ_WAIT = 8,
+ CSF_I1_FIFO_FULL = 9,
+ CSF_I2_FIFO_FULL = 10,
+ CSF_ST_FIFO_FULL = 11,
+ Reserved_12 = 12,
+ CSF_RING_ROQ_FULL = 13,
+ CSF_I1_ROQ_FULL = 14,
+ CSF_I2_ROQ_FULL = 15,
+ CSF_ST_ROQ_FULL = 16,
+ Reserved_17 = 17,
+ MIU_TAG_MEM_FULL = 18,
+ MIU_WRITECLEAN = 19,
+ Reserved_20 = 20,
+ Reserved_21 = 21,
+ MIU_NRT_WRITE_STALLED = 22,
+ MIU_NRT_READ_STALLED = 23,
+ ME_WRITE_CONFIRM_FIFO_FULL = 24,
+ ME_VS_DEALLOC_FIFO_FULL = 25,
+ ME_PS_DEALLOC_FIFO_FULL = 26,
+ ME_REGS_VS_EVENT_FIFO_FULL = 27,
+ ME_REGS_PS_EVENT_FIFO_FULL = 28,
+ ME_REGS_CF_EVENT_FIFO_FULL = 29,
+ ME_MICRO_RB_STARVED = 30,
+ ME_MICRO_I1_STARVED = 31,
+ ME_MICRO_I2_STARVED = 32,
+ ME_MICRO_ST_STARVED = 33,
+ Reserved_34 = 34,
+ Reserved_35 = 35,
+ Reserved_36 = 36,
+ Reserved_37 = 37,
+ Reserved_38 = 38,
+ Reserved_39 = 39,
+ RCIU_RBBM_DWORD_SENT = 40,
+ ME_BUSY_CLOCKS = 41,
+ ME_WAIT_CONTEXT_AVAIL = 42,
+ PFP_TYPE0_PACKET = 43,
+ PFP_TYPE3_PACKET = 44,
+ CSF_RB_WPTR_NEQ_RPTR = 45,
+ CSF_I1_SIZE_NEQ_ZERO = 46,
+ CSF_I2_SIZE_NEQ_ZERO = 47,
+ CSF_RBI1I2_FETCHING = 48,
+ Reserved_49 = 49,
+ Reserved_50 = 50,
+ Reserved_51 = 51,
+ Reserved_52 = 52,
+ Reserved_53 = 53,
+ Reserved_54 = 54,
+ Reserved_55 = 55,
+ Reserved_56 = 56,
+ Reserved_57 = 57,
+ Reserved_58 = 58,
+ Reserved_59 = 59,
+ Reserved_60 = 60,
+ Reserved_61 = 61,
+ Reserved_62 = 62,
+ Reserved_63 = 63
+} CP_PERFCOUNT_SEL;
+#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+#ifndef ENUMS_ColorformatX_H
+#define ENUMS_ColorformatX_H
+typedef enum ColorformatX {
+ COLORX_4_4_4_4 = 0,
+ COLORX_1_5_5_5 = 1,
+ COLORX_5_6_5 = 2,
+ COLORX_8 = 3,
+ COLORX_8_8 = 4,
+ COLORX_8_8_8_8 = 5,
+ COLORX_S8_8_8_8 = 6,
+ COLORX_16_FLOAT = 7,
+ COLORX_16_16_FLOAT = 8,
+ COLORX_16_16_16_16_FLOAT = 9,
+ COLORX_32_FLOAT = 10,
+ COLORX_32_32_FLOAT = 11,
+ COLORX_32_32_32_32_FLOAT = 12,
+ COLORX_2_3_3 = 13,
+ COLORX_8_8_8 = 14,
+} ColorformatX;
+#endif /*ENUMS_ColorformatX_H*/
+
+#ifndef ENUMS_DepthformatX_H
+#define ENUMS_DepthformatX_H
+typedef enum DepthformatX {
+ DEPTHX_16 = 0,
+ DEPTHX_24_8 = 1
+} DepthformatX;
+#endif /*ENUMS_DepthformatX_H*/
+
+#ifndef ENUMS_CompareFrag_H
+#define ENUMS_CompareFrag_H
+typedef enum CompareFrag {
+ FRAG_NEVER = 0,
+ FRAG_LESS = 1,
+ FRAG_EQUAL = 2,
+ FRAG_LEQUAL = 3,
+ FRAG_GREATER = 4,
+ FRAG_NOTEQUAL = 5,
+ FRAG_GEQUAL = 6,
+ FRAG_ALWAYS = 7
+} CompareFrag;
+#endif /*ENUMS_CompareFrag_H*/
+
+#ifndef ENUMS_CompareRef_H
+#define ENUMS_CompareRef_H
+typedef enum CompareRef {
+ REF_NEVER = 0,
+ REF_LESS = 1,
+ REF_EQUAL = 2,
+ REF_LEQUAL = 3,
+ REF_GREATER = 4,
+ REF_NOTEQUAL = 5,
+ REF_GEQUAL = 6,
+ REF_ALWAYS = 7
+} CompareRef;
+#endif /*ENUMS_CompareRef_H*/
+
+#ifndef ENUMS_StencilOp_H
+#define ENUMS_StencilOp_H
+typedef enum StencilOp {
+ STENCIL_KEEP = 0,
+ STENCIL_ZERO = 1,
+ STENCIL_REPLACE = 2,
+ STENCIL_INCR_CLAMP = 3,
+ STENCIL_DECR_CLAMP = 4,
+ STENCIL_INVERT = 5,
+ STENCIL_INCR_WRAP = 6,
+ STENCIL_DECR_WRAP = 7
+} StencilOp;
+#endif /*ENUMS_StencilOp_H*/
+
+#ifndef ENUMS_BlendOpX_H
+#define ENUMS_BlendOpX_H
+typedef enum BlendOpX {
+ BLENDX_ZERO = 0,
+ BLENDX_ONE = 1,
+ BLENDX_SRC_COLOR = 4,
+ BLENDX_ONE_MINUS_SRC_COLOR = 5,
+ BLENDX_SRC_ALPHA = 6,
+ BLENDX_ONE_MINUS_SRC_ALPHA = 7,
+ BLENDX_DST_COLOR = 8,
+ BLENDX_ONE_MINUS_DST_COLOR = 9,
+ BLENDX_DST_ALPHA = 10,
+ BLENDX_ONE_MINUS_DST_ALPHA = 11,
+ BLENDX_CONSTANT_COLOR = 12,
+ BLENDX_ONE_MINUS_CONSTANT_COLOR = 13,
+ BLENDX_CONSTANT_ALPHA = 14,
+ BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15,
+ BLENDX_SRC_ALPHA_SATURATE = 16,
+} BlendOpX;
+#endif /*ENUMS_BlendOpX_H*/
+
+#ifndef ENUMS_CombFuncX_H
+#define ENUMS_CombFuncX_H
+typedef enum CombFuncX {
+ COMB_DST_PLUS_SRC = 0,
+ COMB_SRC_MINUS_DST = 1,
+ COMB_MIN_DST_SRC = 2,
+ COMB_MAX_DST_SRC = 3,
+ COMB_DST_MINUS_SRC = 4,
+ COMB_DST_PLUS_SRC_BIAS = 5,
+} CombFuncX;
+#endif /*ENUMS_CombFuncX_H*/
+
+#ifndef ENUMS_DitherModeX_H
+#define ENUMS_DitherModeX_H
+typedef enum DitherModeX {
+ DITHER_DISABLE = 0,
+ DITHER_ALWAYS = 1,
+ DITHER_IF_ALPHA_OFF = 2,
+} DitherModeX;
+#endif /*ENUMS_DitherModeX_H*/
+
+#ifndef ENUMS_DitherTypeX_H
+#define ENUMS_DitherTypeX_H
+typedef enum DitherTypeX {
+ DITHER_PIXEL = 0,
+ DITHER_SUBPIXEL = 1,
+} DitherTypeX;
+#endif /*ENUMS_DitherTypeX_H*/
+
+#ifndef ENUMS_EdramMode_H
+#define ENUMS_EdramMode_H
+typedef enum EdramMode {
+ EDRAM_NOP = 0,
+ COLOR_DEPTH = 4,
+ DEPTH_ONLY = 5,
+ EDRAM_COPY = 6,
+} EdramMode;
+#endif /*ENUMS_EdramMode_H*/
+
+#ifndef ENUMS_SurfaceEndian_H
+#define ENUMS_SurfaceEndian_H
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0,
+ ENDIAN_8IN16 = 1,
+ ENDIAN_8IN32 = 2,
+ ENDIAN_16IN32 = 3,
+ ENDIAN_8IN64 = 4,
+ ENDIAN_8IN128 = 5,
+} SurfaceEndian;
+#endif /*ENUMS_SurfaceEndian_H*/
+
+#ifndef ENUMS_EdramSizeX_H
+#define ENUMS_EdramSizeX_H
+typedef enum EdramSizeX {
+ EDRAMSIZE_16KB = 0,
+ EDRAMSIZE_32KB = 1,
+ EDRAMSIZE_64KB = 2,
+ EDRAMSIZE_128KB = 3,
+ EDRAMSIZE_256KB = 4,
+ EDRAMSIZE_512KB = 5,
+ EDRAMSIZE_1MB = 6,
+ EDRAMSIZE_2MB = 7,
+ EDRAMSIZE_4MB = 8,
+ EDRAMSIZE_8MB = 9,
+ EDRAMSIZE_16MB = 10,
+} EdramSizeX;
+#endif /*ENUMS_EdramSizeX_H*/
+
+#ifndef ENUMS_RB_PERFCNT_SELECT_H
+#define ENUMS_RB_PERFCNT_SELECT_H
+typedef enum RB_PERFCNT_SELECT {
+ RBPERF_CNTX_BUSY = 0,
+ RBPERF_CNTX_BUSY_MAX = 1,
+ RBPERF_SX_QUAD_STARVED = 2,
+ RBPERF_SX_QUAD_STARVED_MAX = 3,
+ RBPERF_GA_GC_CH0_SYS_REQ = 4,
+ RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+ RBPERF_GA_GC_CH1_SYS_REQ = 6,
+ RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+ RBPERF_MH_STARVED = 8,
+ RBPERF_MH_STARVED_MAX = 9,
+ RBPERF_AZ_BC_COLOR_BUSY = 10,
+ RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+ RBPERF_AZ_BC_Z_BUSY = 12,
+ RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+ RBPERF_RB_SC_TILE_RTR_N = 14,
+ RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+ RBPERF_RB_SC_SAMP_RTR_N = 16,
+ RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+ RBPERF_RB_SX_QUAD_RTR_N = 18,
+ RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+ RBPERF_RB_SX_COLOR_RTR_N = 20,
+ RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+ RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+ RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+ RBPERF_ZXP_STALL = 24,
+ RBPERF_ZXP_STALL_MAX = 25,
+ RBPERF_EVENT_PENDING = 26,
+ RBPERF_EVENT_PENDING_MAX = 27,
+ RBPERF_RB_MH_VALID = 28,
+ RBPERF_RB_MH_VALID_MAX = 29,
+ RBPERF_SX_RB_QUAD_SEND = 30,
+ RBPERF_SX_RB_COLOR_SEND = 31,
+ RBPERF_SC_RB_TILE_SEND = 32,
+ RBPERF_SC_RB_SAMPLE_SEND = 33,
+ RBPERF_SX_RB_MEM_EXPORT = 34,
+ RBPERF_SX_RB_QUAD_EVENT = 35,
+ RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+ RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+ RBPERF_RB_SC_EZ_SEND = 38,
+ RBPERF_RB_SX_INDEX_SEND = 39,
+ RBPERF_GMEM_INTFO_RD = 40,
+ RBPERF_GMEM_INTF1_RD = 41,
+ RBPERF_GMEM_INTFO_WR = 42,
+ RBPERF_GMEM_INTF1_WR = 43,
+ RBPERF_RB_CP_CONTEXT_DONE = 44,
+ RBPERF_RB_CP_CACHE_FLUSH = 45,
+ RBPERF_ZPASS_DONE = 46,
+ RBPERF_ZCMD_VALID = 47,
+ RBPERF_CCMD_VALID = 48,
+ RBPERF_ACCUM_GRANT = 49,
+ RBPERF_ACCUM_C0_GRANT = 50,
+ RBPERF_ACCUM_C1_GRANT = 51,
+ RBPERF_ACCUM_FULL_BE_WR = 52,
+ RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+ RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+ RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+ RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+} RB_PERFCNT_SELECT;
+#endif /*ENUMS_RB_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_DepthFormat_H
+#define ENUMS_DepthFormat_H
+typedef enum DepthFormat {
+ DEPTH_24_8 = 22,
+ DEPTH_24_8_FLOAT = 23,
+ DEPTH_16 = 24,
+} DepthFormat;
+#endif /*ENUMS_DepthFormat_H*/
+
+#ifndef ENUMS_SurfaceSwap_H
+#define ENUMS_SurfaceSwap_H
+typedef enum SurfaceSwap {
+ SWAP_LOWRED = 0,
+ SWAP_LOWBLUE = 1
+} SurfaceSwap;
+#endif /*ENUMS_SurfaceSwap_H*/
+
+#ifndef ENUMS_DepthArray_H
+#define ENUMS_DepthArray_H
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0,
+ ARRAY_2D_DEPTH = 1,
+} DepthArray;
+#endif /*ENUMS_DepthArray_H*/
+
+#ifndef ENUMS_ColorArray_H
+#define ENUMS_ColorArray_H
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0,
+ ARRAY_2D_COLOR = 1,
+ ARRAY_3D_SLICE_COLOR = 3
+} ColorArray;
+#endif /*ENUMS_ColorArray_H*/
+
+#ifndef ENUMS_ColorFormat_H
+#define ENUMS_ColorFormat_H
+typedef enum ColorFormat {
+ COLOR_8 = 2,
+ COLOR_1_5_5_5 = 3,
+ COLOR_5_6_5 = 4,
+ COLOR_6_5_5 = 5,
+ COLOR_8_8_8_8 = 6,
+ COLOR_2_10_10_10 = 7,
+ COLOR_8_A = 8,
+ COLOR_8_B = 9,
+ COLOR_8_8 = 10,
+ COLOR_8_8_8 = 11,
+ COLOR_8_8_8_8_A = 14,
+ COLOR_4_4_4_4 = 15,
+ COLOR_10_11_11 = 16,
+ COLOR_11_11_10 = 17,
+ COLOR_16 = 24,
+ COLOR_16_16 = 25,
+ COLOR_16_16_16_16 = 26,
+ COLOR_16_FLOAT = 30,
+ COLOR_16_16_FLOAT = 31,
+ COLOR_16_16_16_16_FLOAT = 32,
+ COLOR_32_FLOAT = 36,
+ COLOR_32_32_FLOAT = 37,
+ COLOR_32_32_32_32_FLOAT = 38,
+ COLOR_2_3_3 = 39,
+} ColorFormat;
+#endif /*ENUMS_ColorFormat_H*/
+
+#ifndef ENUMS_SurfaceNumber_H
+#define ENUMS_SurfaceNumber_H
+typedef enum SurfaceNumber {
+ NUMBER_UREPEAT = 0,
+ NUMBER_SREPEAT = 1,
+ NUMBER_UINTEGER = 2,
+ NUMBER_SINTEGER = 3,
+ NUMBER_GAMMA = 4,
+ NUMBER_FIXED = 5,
+ NUMBER_FLOAT = 7
+} SurfaceNumber;
+#endif /*ENUMS_SurfaceNumber_H*/
+
+#ifndef ENUMS_SurfaceFormat_H
+#define ENUMS_SurfaceFormat_H
+typedef enum SurfaceFormat {
+ FMT_1_REVERSE = 0,
+ FMT_1 = 1,
+ FMT_8 = 2,
+ FMT_1_5_5_5 = 3,
+ FMT_5_6_5 = 4,
+ FMT_6_5_5 = 5,
+ FMT_8_8_8_8 = 6,
+ FMT_2_10_10_10 = 7,
+ FMT_8_A = 8,
+ FMT_8_B = 9,
+ FMT_8_8 = 10,
+ FMT_Cr_Y1_Cb_Y0 = 11,
+ FMT_Y1_Cr_Y0_Cb = 12,
+ FMT_5_5_5_1 = 13,
+ FMT_8_8_8_8_A = 14,
+ FMT_4_4_4_4 = 15,
+ FMT_8_8_8 = 16,
+ FMT_DXT1 = 18,
+ FMT_DXT2_3 = 19,
+ FMT_DXT4_5 = 20,
+ FMT_10_10_10_2 = 21,
+ FMT_24_8 = 22,
+ FMT_16 = 24,
+ FMT_16_16 = 25,
+ FMT_16_16_16_16 = 26,
+ FMT_16_EXPAND = 27,
+ FMT_16_16_EXPAND = 28,
+ FMT_16_16_16_16_EXPAND = 29,
+ FMT_16_FLOAT = 30,
+ FMT_16_16_FLOAT = 31,
+ FMT_16_16_16_16_FLOAT = 32,
+ FMT_32 = 33,
+ FMT_32_32 = 34,
+ FMT_32_32_32_32 = 35,
+ FMT_32_FLOAT = 36,
+ FMT_32_32_FLOAT = 37,
+ FMT_32_32_32_32_FLOAT = 38,
+ FMT_ATI_TC_RGB = 39,
+ FMT_ATI_TC_RGBA = 40,
+ FMT_ATI_TC_555_565_RGB = 41,
+ FMT_ATI_TC_555_565_RGBA = 42,
+ FMT_ATI_TC_RGBA_INTERP = 43,
+ FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+ FMT_ETC1_RGBA_INTERP = 46,
+ FMT_ETC1_RGB = 47,
+ FMT_ETC1_RGBA = 48,
+ FMT_DXN = 49,
+ FMT_2_3_3 = 51,
+ FMT_2_10_10_10_AS_16_16_16_16 = 54,
+ FMT_10_10_10_2_AS_16_16_16_16 = 55,
+ FMT_32_32_32_FLOAT = 57,
+ FMT_DXT3A = 58,
+ FMT_DXT5A = 59,
+ FMT_CTX1 = 60,
+} SurfaceFormat;
+#endif /*ENUMS_SurfaceFormat_H*/
+
+#ifndef ENUMS_SurfaceTiling_H
+#define ENUMS_SurfaceTiling_H
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0,
+ ARRAY_TILED = 1
+} SurfaceTiling;
+#endif /*ENUMS_SurfaceTiling_H*/
+
+#ifndef ENUMS_SurfaceArray_H
+#define ENUMS_SurfaceArray_H
+typedef enum SurfaceArray {
+ ARRAY_1D = 0,
+ ARRAY_2D = 1,
+ ARRAY_3D = 2,
+ ARRAY_3D_SLICE = 3
+} SurfaceArray;
+#endif /*ENUMS_SurfaceArray_H*/
+
+#ifndef ENUMS_SurfaceNumberX_H
+#define ENUMS_SurfaceNumberX_H
+typedef enum SurfaceNumberX {
+ NUMBERX_UREPEAT = 0,
+ NUMBERX_SREPEAT = 1,
+ NUMBERX_UINTEGER = 2,
+ NUMBERX_SINTEGER = 3,
+ NUMBERX_FLOAT = 7
+} SurfaceNumberX;
+#endif /*ENUMS_SurfaceNumberX_H*/
+
+#ifndef ENUMS_ColorArrayX_H
+#define ENUMS_ColorArrayX_H
+typedef enum ColorArrayX {
+ ARRAYX_2D_COLOR = 0,
+ ARRAYX_3D_SLICE_COLOR = 1,
+} ColorArrayX;
+#endif /*ENUMS_ColorArrayX_H*/
+
+#endif /*_yamato_ENUM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h
new file mode 100644
index 00000000000..f2f4dec63da
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h
@@ -0,0 +1,1674 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_ENUMTYPE(SU_PERFCNT_SELECT)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0)
+    GENERATE_ENUM(UNUSED1, 1)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13)
+    GENERATE_ENUM(UNUSED2, 14)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15)
+    GENERATE_ENUM(UNUSED3, 16)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19)
+    GENERATE_ENUM(UNUSED4, 20)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21)
+    GENERATE_ENUM(UNUSED5, 22)
+    GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36)
+    GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49)
+    GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50)
+    GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51)
+    GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95)
+    GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96)
+    GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97)
+    GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98)
+    GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99)
+    GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100)
+    GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101)
+END_ENUMTYPE(SU_PERFCNT_SELECT)
+
+START_ENUMTYPE(SC_PERFCNT_SELECT)
+    GENERATE_ENUM(SC_SR_WINDOW_VALID, 0)
+    GENERATE_ENUM(SC_CW_WINDOW_VALID, 1)
+    GENERATE_ENUM(SC_QM_WINDOW_VALID, 2)
+    GENERATE_ENUM(SC_FW_WINDOW_VALID, 3)
+    GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4)
+    GENERATE_ENUM(SC_IT_WINDOW_VALID, 5)
+    GENERATE_ENUM(SC_STARVED_BY_PA, 6)
+    GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7)
+    GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8)
+    GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9)
+    GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10)
+    GENERATE_ENUM(SC_STALLED_BY_SQ, 11)
+    GENERATE_ENUM(SC_STALLED_BY_SP, 12)
+    GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13)
+    GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14)
+    GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15)
+    GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16)
+    GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17)
+END_ENUMTYPE(SC_PERFCNT_SELECT)
+
+START_ENUMTYPE(VGT_DI_PRIM_TYPE)
+    GENERATE_ENUM(DI_PT_NONE, 0)
+    GENERATE_ENUM(DI_PT_POINTLIST, 1)
+    GENERATE_ENUM(DI_PT_LINELIST, 2)
+    GENERATE_ENUM(DI_PT_LINESTRIP, 3)
+    GENERATE_ENUM(DI_PT_TRILIST, 4)
+    GENERATE_ENUM(DI_PT_TRIFAN, 5)
+    GENERATE_ENUM(DI_PT_TRISTRIP, 6)
+    GENERATE_ENUM(DI_PT_UNUSED_1, 7)
+    GENERATE_ENUM(DI_PT_RECTLIST, 8)
+    GENERATE_ENUM(DI_PT_UNUSED_2, 9)
+    GENERATE_ENUM(DI_PT_UNUSED_3, 10)
+    GENERATE_ENUM(DI_PT_UNUSED_4, 11)
+    GENERATE_ENUM(DI_PT_UNUSED_5, 12)
+    GENERATE_ENUM(DI_PT_QUADLIST, 13)
+    GENERATE_ENUM(DI_PT_QUADSTRIP, 14)
+    GENERATE_ENUM(DI_PT_POLYGON, 15)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19)
+    GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20)
+    GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21)
+    GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22)
+END_ENUMTYPE(VGT_DI_PRIM_TYPE)
+
+START_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+    GENERATE_ENUM(DI_SRC_SEL_DMA, 0)
+    GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1)
+    GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2)
+    GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3)
+END_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+
+START_ENUMTYPE(VGT_DI_INDEX_SIZE)
+    GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1)
+END_ENUMTYPE(VGT_DI_INDEX_SIZE)
+
+START_ENUMTYPE(VGT_DI_SMALL_INDEX)
+    GENERATE_ENUM(DI_USE_INDEX_SIZE, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1)
+END_ENUMTYPE(VGT_DI_SMALL_INDEX)
+
+START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0)
+    GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0)
+    GENERATE_ENUM(GRP_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_EVENT_TYPE)
+    GENERATE_ENUM(VS_DEALLOC, 0)
+    GENERATE_ENUM(PS_DEALLOC, 1)
+    GENERATE_ENUM(VS_DONE_TS, 2)
+    GENERATE_ENUM(PS_DONE_TS, 3)
+    GENERATE_ENUM(CACHE_FLUSH_TS, 4)
+    GENERATE_ENUM(CONTEXT_DONE, 5)
+    GENERATE_ENUM(CACHE_FLUSH, 6)
+    GENERATE_ENUM(VIZQUERY_START, 7)
+    GENERATE_ENUM(VIZQUERY_END, 8)
+    GENERATE_ENUM(SC_WAIT_WC, 9)
+    GENERATE_ENUM(RST_PIX_CNT, 13)
+    GENERATE_ENUM(RST_VTX_CNT, 14)
+    GENERATE_ENUM(TILE_FLUSH, 15)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20)
+    GENERATE_ENUM(ZPASS_DONE, 21)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22)
+    GENERATE_ENUM(PERFCOUNTER_START, 23)
+    GENERATE_ENUM(PERFCOUNTER_STOP, 24)
+    GENERATE_ENUM(VS_FETCH_DONE, 27)
+END_ENUMTYPE(VGT_EVENT_TYPE)
+
+START_ENUMTYPE(VGT_DMA_SWAP_MODE)
+    GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0)
+    GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1)
+    GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2)
+    GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3)
+END_ENUMTYPE(VGT_DMA_SWAP_MODE)
+
+START_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0)
+    GENERATE_ENUM(VGT_SQ_SEND, 1)
+    GENERATE_ENUM(VGT_SQ_STALLED, 2)
+    GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3)
+    GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4)
+    GENERATE_ENUM(VGT_SQ_STATIC, 5)
+    GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6)
+    GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11)
+    GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16)
+    GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21)
+    GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28)
+    GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29)
+    GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30)
+    GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31)
+    GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32)
+    GENERATE_ENUM(SPARE33, 33)
+    GENERATE_ENUM(SPARE34, 34)
+    GENERATE_ENUM(SPARE35, 35)
+    GENERATE_ENUM(SPARE36, 36)
+    GENERATE_ENUM(SPARE37, 37)
+    GENERATE_ENUM(SPARE38, 38)
+    GENERATE_ENUM(SPARE39, 39)
+    GENERATE_ENUM(TE_SU_IN_VALID, 40)
+    GENERATE_ENUM(TE_SU_IN_READ, 41)
+    GENERATE_ENUM(TE_SU_IN_PRIM, 42)
+    GENERATE_ENUM(TE_SU_IN_EOP, 43)
+    GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44)
+    GENERATE_ENUM(TE_WK_IN_VALID, 45)
+    GENERATE_ENUM(TE_WK_IN_READ, 46)
+    GENERATE_ENUM(TE_OUT_PRIM_VALID, 47)
+    GENERATE_ENUM(TE_OUT_PRIM_READ, 48)
+END_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+    GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0)
+    GENERATE_ENUM(reserved_46, 1)
+    GENERATE_ENUM(reserved_47, 2)
+    GENERATE_ENUM(reserved_48, 3)
+    GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4)
+    GENERATE_ENUM(OPMUX0_L2_WRITES, 5)
+    GENERATE_ENUM(reserved_49, 6)
+    GENERATE_ENUM(reserved_50, 7)
+    GENERATE_ENUM(reserved_51, 8)
+END_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TP_PERFCOUNT_SELECT)
+    GENERATE_ENUM(POINT_QUADS, 0)
+    GENERATE_ENUM(BILIN_QUADS, 1)
+    GENERATE_ENUM(ANISO_QUADS, 2)
+    GENERATE_ENUM(MIP_QUADS, 3)
+    GENERATE_ENUM(VOL_QUADS, 4)
+    GENERATE_ENUM(MIP_VOL_QUADS, 5)
+    GENERATE_ENUM(MIP_ANISO_QUADS, 6)
+    GENERATE_ENUM(VOL_ANISO_QUADS, 7)
+    GENERATE_ENUM(ANISO_2_1_QUADS, 8)
+    GENERATE_ENUM(ANISO_4_1_QUADS, 9)
+    GENERATE_ENUM(ANISO_6_1_QUADS, 10)
+    GENERATE_ENUM(ANISO_8_1_QUADS, 11)
+    GENERATE_ENUM(ANISO_10_1_QUADS, 12)
+    GENERATE_ENUM(ANISO_12_1_QUADS, 13)
+    GENERATE_ENUM(ANISO_14_1_QUADS, 14)
+    GENERATE_ENUM(ANISO_16_1_QUADS, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16)
+    GENERATE_ENUM(ALIGN_2_QUADS, 17)
+    GENERATE_ENUM(ALIGN_4_QUADS, 18)
+    GENERATE_ENUM(PIX_0_QUAD, 19)
+    GENERATE_ENUM(PIX_1_QUAD, 20)
+    GENERATE_ENUM(PIX_2_QUAD, 21)
+    GENERATE_ENUM(PIX_3_QUAD, 22)
+    GENERATE_ENUM(PIX_4_QUAD, 23)
+    GENERATE_ENUM(TP_MIPMAP_LOD0, 24)
+    GENERATE_ENUM(TP_MIPMAP_LOD1, 25)
+    GENERATE_ENUM(TP_MIPMAP_LOD2, 26)
+    GENERATE_ENUM(TP_MIPMAP_LOD3, 27)
+    GENERATE_ENUM(TP_MIPMAP_LOD4, 28)
+    GENERATE_ENUM(TP_MIPMAP_LOD5, 29)
+    GENERATE_ENUM(TP_MIPMAP_LOD6, 30)
+    GENERATE_ENUM(TP_MIPMAP_LOD7, 31)
+    GENERATE_ENUM(TP_MIPMAP_LOD8, 32)
+    GENERATE_ENUM(TP_MIPMAP_LOD9, 33)
+    GENERATE_ENUM(TP_MIPMAP_LOD10, 34)
+    GENERATE_ENUM(TP_MIPMAP_LOD11, 35)
+    GENERATE_ENUM(TP_MIPMAP_LOD12, 36)
+    GENERATE_ENUM(TP_MIPMAP_LOD13, 37)
+    GENERATE_ENUM(TP_MIPMAP_LOD14, 38)
+END_ENUMTYPE(TP_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0)
+    GENERATE_ENUM(reserved_01, 1)
+    GENERATE_ENUM(reserved_02, 2)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6)
+    GENERATE_ENUM(reserved_07, 7)
+    GENERATE_ENUM(reserved_08, 8)
+    GENERATE_ENUM(reserved_09, 9)
+    GENERATE_ENUM(reserved_10, 10)
+    GENERATE_ENUM(reserved_11, 11)
+    GENERATE_ENUM(reserved_12, 12)
+    GENERATE_ENUM(reserved_13, 13)
+    GENERATE_ENUM(reserved_14, 14)
+    GENERATE_ENUM(reserved_15, 15)
+    GENERATE_ENUM(reserved_16, 16)
+    GENERATE_ENUM(reserved_17, 17)
+    GENERATE_ENUM(reserved_18, 18)
+    GENERATE_ENUM(reserved_19, 19)
+    GENERATE_ENUM(reserved_20, 20)
+    GENERATE_ENUM(reserved_21, 21)
+    GENERATE_ENUM(reserved_22, 22)
+    GENERATE_ENUM(reserved_23, 23)
+    GENERATE_ENUM(reserved_24, 24)
+    GENERATE_ENUM(reserved_25, 25)
+    GENERATE_ENUM(reserved_26, 26)
+    GENERATE_ENUM(reserved_27, 27)
+    GENERATE_ENUM(READ_STARVED_QUAD0, 28)
+    GENERATE_ENUM(reserved_29, 29)
+    GENERATE_ENUM(reserved_30, 30)
+    GENERATE_ENUM(reserved_31, 31)
+    GENERATE_ENUM(READ_STARVED, 32)
+    GENERATE_ENUM(READ_STALLED_QUAD0, 33)
+    GENERATE_ENUM(reserved_34, 34)
+    GENERATE_ENUM(reserved_35, 35)
+    GENERATE_ENUM(reserved_36, 36)
+    GENERATE_ENUM(READ_STALLED, 37)
+    GENERATE_ENUM(VALID_READ_QUAD0, 38)
+    GENERATE_ENUM(reserved_39, 39)
+    GENERATE_ENUM(reserved_40, 40)
+    GENERATE_ENUM(reserved_41, 41)
+    GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42)
+    GENERATE_ENUM(reserved_43, 43)
+    GENERATE_ENUM(reserved_44, 44)
+    GENERATE_ENUM(reserved_45, 45)
+    GENERATE_ENUM(TC_TP_STARVED, 46)
+END_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VALID_CYCLES, 0)
+    GENERATE_ENUM(SINGLE_PHASES, 1)
+    GENERATE_ENUM(ANISO_PHASES, 2)
+    GENERATE_ENUM(MIP_PHASES, 3)
+    GENERATE_ENUM(VOL_PHASES, 4)
+    GENERATE_ENUM(MIP_VOL_PHASES, 5)
+    GENERATE_ENUM(MIP_ANISO_PHASES, 6)
+    GENERATE_ENUM(VOL_ANISO_PHASES, 7)
+    GENERATE_ENUM(ANISO_2_1_PHASES, 8)
+    GENERATE_ENUM(ANISO_4_1_PHASES, 9)
+    GENERATE_ENUM(ANISO_6_1_PHASES, 10)
+    GENERATE_ENUM(ANISO_8_1_PHASES, 11)
+    GENERATE_ENUM(ANISO_10_1_PHASES, 12)
+    GENERATE_ENUM(ANISO_12_1_PHASES, 13)
+    GENERATE_ENUM(ANISO_14_1_PHASES, 14)
+    GENERATE_ENUM(ANISO_16_1_PHASES, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16)
+    GENERATE_ENUM(ALIGN_2_PHASES, 17)
+    GENERATE_ENUM(ALIGN_4_PHASES, 18)
+    GENERATE_ENUM(TPC_BUSY, 19)
+    GENERATE_ENUM(TPC_STALLED, 20)
+    GENERATE_ENUM(TPC_STARVED, 21)
+    GENERATE_ENUM(TPC_WORKING, 22)
+    GENERATE_ENUM(TPC_WALKER_BUSY, 23)
+    GENERATE_ENUM(TPC_WALKER_STALLED, 24)
+    GENERATE_ENUM(TPC_WALKER_WORKING, 25)
+    GENERATE_ENUM(TPC_ALIGNER_BUSY, 26)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED, 27)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29)
+    GENERATE_ENUM(TPC_ALIGNER_WORKING, 30)
+    GENERATE_ENUM(TPC_BLEND_BUSY, 31)
+    GENERATE_ENUM(TPC_BLEND_SYNC, 32)
+    GENERATE_ENUM(TPC_BLEND_STARVED, 33)
+    GENERATE_ENUM(TPC_BLEND_WORKING, 34)
+    GENERATE_ENUM(OPCODE_0x00, 35)
+    GENERATE_ENUM(OPCODE_0x01, 36)
+    GENERATE_ENUM(OPCODE_0x04, 37)
+    GENERATE_ENUM(OPCODE_0x10, 38)
+    GENERATE_ENUM(OPCODE_0x11, 39)
+    GENERATE_ENUM(OPCODE_0x12, 40)
+    GENERATE_ENUM(OPCODE_0x13, 41)
+    GENERATE_ENUM(OPCODE_0x18, 42)
+    GENERATE_ENUM(OPCODE_0x19, 43)
+    GENERATE_ENUM(OPCODE_0x1A, 44)
+    GENERATE_ENUM(OPCODE_OTHER, 45)
+    GENERATE_ENUM(IN_FIFO_0_EMPTY, 56)
+    GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57)
+    GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58)
+    GENERATE_ENUM(IN_FIFO_0_FULL, 59)
+    GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72)
+    GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73)
+    GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74)
+    GENERATE_ENUM(IN_FIFO_TPC_FULL, 75)
+    GENERATE_ENUM(TPC_TC_XFC, 76)
+    GENERATE_ENUM(TPC_TC_STATE, 77)
+    GENERATE_ENUM(TC_STALL, 78)
+    GENERATE_ENUM(QUAD0_TAPS, 79)
+    GENERATE_ENUM(QUADS, 83)
+    GENERATE_ENUM(TCA_SYNC_STALL, 84)
+    GENERATE_ENUM(TAG_STALL, 85)
+    GENERATE_ENUM(TCB_SYNC_STALL, 88)
+    GENERATE_ENUM(TCA_VALID, 89)
+    GENERATE_ENUM(PROBES_VALID, 90)
+    GENERATE_ENUM(MISS_STALL, 91)
+    GENERATE_ENUM(FETCH_FIFO_STALL, 92)
+    GENERATE_ENUM(TCO_STALL, 93)
+    GENERATE_ENUM(ANY_STALL, 94)
+    GENERATE_ENUM(TAG_MISSES, 95)
+    GENERATE_ENUM(TAG_HITS, 96)
+    GENERATE_ENUM(SUB_TAG_MISSES, 97)
+    GENERATE_ENUM(SET0_INVALIDATES, 98)
+    GENERATE_ENUM(SET1_INVALIDATES, 99)
+    GENERATE_ENUM(SET2_INVALIDATES, 100)
+    GENERATE_ENUM(SET3_INVALIDATES, 101)
+    GENERATE_ENUM(SET0_TAG_MISSES, 102)
+    GENERATE_ENUM(SET1_TAG_MISSES, 103)
+    GENERATE_ENUM(SET2_TAG_MISSES, 104)
+    GENERATE_ENUM(SET3_TAG_MISSES, 105)
+    GENERATE_ENUM(SET0_TAG_HITS, 106)
+    GENERATE_ENUM(SET1_TAG_HITS, 107)
+    GENERATE_ENUM(SET2_TAG_HITS, 108)
+    GENERATE_ENUM(SET3_TAG_HITS, 109)
+    GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110)
+    GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111)
+    GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112)
+    GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113)
+    GENERATE_ENUM(SET0_EVICT1, 114)
+    GENERATE_ENUM(SET0_EVICT2, 115)
+    GENERATE_ENUM(SET0_EVICT3, 116)
+    GENERATE_ENUM(SET0_EVICT4, 117)
+    GENERATE_ENUM(SET0_EVICT5, 118)
+    GENERATE_ENUM(SET0_EVICT6, 119)
+    GENERATE_ENUM(SET0_EVICT7, 120)
+    GENERATE_ENUM(SET0_EVICT8, 121)
+    GENERATE_ENUM(SET1_EVICT1, 130)
+    GENERATE_ENUM(SET1_EVICT2, 131)
+    GENERATE_ENUM(SET1_EVICT3, 132)
+    GENERATE_ENUM(SET1_EVICT4, 133)
+    GENERATE_ENUM(SET1_EVICT5, 134)
+    GENERATE_ENUM(SET1_EVICT6, 135)
+    GENERATE_ENUM(SET1_EVICT7, 136)
+    GENERATE_ENUM(SET1_EVICT8, 137)
+    GENERATE_ENUM(SET2_EVICT1, 146)
+    GENERATE_ENUM(SET2_EVICT2, 147)
+    GENERATE_ENUM(SET2_EVICT3, 148)
+    GENERATE_ENUM(SET2_EVICT4, 149)
+    GENERATE_ENUM(SET2_EVICT5, 150)
+    GENERATE_ENUM(SET2_EVICT6, 151)
+    GENERATE_ENUM(SET2_EVICT7, 152)
+    GENERATE_ENUM(SET2_EVICT8, 153)
+    GENERATE_ENUM(SET3_EVICT1, 162)
+    GENERATE_ENUM(SET3_EVICT2, 163)
+    GENERATE_ENUM(SET3_EVICT3, 164)
+    GENERATE_ENUM(SET3_EVICT4, 165)
+    GENERATE_ENUM(SET3_EVICT5, 166)
+    GENERATE_ENUM(SET3_EVICT6, 167)
+    GENERATE_ENUM(SET3_EVICT7, 168)
+    GENERATE_ENUM(SET3_EVICT8, 169)
+    GENERATE_ENUM(FF_EMPTY, 178)
+    GENERATE_ENUM(FF_LT_HALF_FULL, 179)
+    GENERATE_ENUM(FF_HALF_FULL, 180)
+    GENERATE_ENUM(FF_FULL, 181)
+    GENERATE_ENUM(FF_XFC, 182)
+    GENERATE_ENUM(FF_STALLED, 183)
+    GENERATE_ENUM(FG_MASKS, 184)
+    GENERATE_ENUM(FG_LEFT_MASKS, 185)
+    GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186)
+    GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187)
+    GENERATE_ENUM(FG_LEFT_FG_STALL, 188)
+    GENERATE_ENUM(FG_LEFT_SECTORS, 189)
+    GENERATE_ENUM(FG0_REQUESTS, 195)
+    GENERATE_ENUM(FG0_STALLED, 196)
+    GENERATE_ENUM(MEM_REQ512, 199)
+    GENERATE_ENUM(MEM_REQ_SENT, 200)
+    GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202)
+    GENERATE_ENUM(TC0_MH_STALLED, 203)
+END_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(SQ_PERFCNT_SELECT)
+    GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0)
+    GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9)
+    GENERATE_ENUM(SQ_EXPORT_CYCLES, 10)
+    GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11)
+    GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12)
+    GENERATE_ENUM(SQ_ALU_CST_STALL, 13)
+    GENERATE_ENUM(SQ_ALU_TEX_STALL, 14)
+    GENERATE_ENUM(SQ_INST_WRITTEN, 15)
+    GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16)
+    GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21)
+    GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22)
+    GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23)
+    GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24)
+    GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25)
+    GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26)
+    GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27)
+    GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28)
+    GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33)
+    GENERATE_ENUM(SQ_ALU_NOPS, 34)
+    GENERATE_ENUM(SQ_PRED_SKIP, 35)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41)
+    GENERATE_ENUM(SQ_GPR_STALL_VTX, 42)
+    GENERATE_ENUM(SQ_GPR_STALL_PIX, 43)
+    GENERATE_ENUM(SQ_VTX_RS_STALL, 44)
+    GENERATE_ENUM(SQ_PIX_RS_STALL, 45)
+    GENERATE_ENUM(SQ_SX_PC_FULL, 46)
+    GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47)
+    GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48)
+    GENERATE_ENUM(SQ_INTERP_QUADS, 49)
+    GENERATE_ENUM(SQ_INTERP_ACTIVE, 50)
+    GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51)
+    GENERATE_ENUM(SQ_IN_VTX_STALL, 52)
+    GENERATE_ENUM(SQ_VTX_CNT, 53)
+    GENERATE_ENUM(SQ_VTX_VECTOR2, 54)
+    GENERATE_ENUM(SQ_VTX_VECTOR3, 55)
+    GENERATE_ENUM(SQ_VTX_VECTOR4, 56)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61)
+    GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD3, 68)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD3, 70)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_VTX, 76)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_PIX, 80)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD3, 85)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD3, 86)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94)
+    GENERATE_ENUM(VC_PERF_STATIC, 95)
+    GENERATE_ENUM(VC_PERF_STALLED, 96)
+    GENERATE_ENUM(VC_PERF_STARVED, 97)
+    GENERATE_ENUM(VC_PERF_SEND, 98)
+    GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99)
+    GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100)
+    GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101)
+    GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102)
+    GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103)
+    GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104)
+    GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105)
+    GENERATE_ENUM(PTRBUFF_EF_PUSH, 106)
+    GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107)
+    GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108)
+    GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112)
+    GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113)
+    GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114)
+    GENERATE_ENUM(PTRBUFF_PI_RTR, 115)
+    GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116)
+    GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117)
+    GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118)
+    GENERATE_ENUM(PTRBUFF_SQ_DEC, 119)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121)
+    GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122)
+    GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123)
+    GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124)
+    GENERATE_ENUM(PTRBUFF_END_BUFFER, 125)
+    GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126)
+    GENERATE_ENUM(VERTS_WRITTEN_SPI, 127)
+    GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128)
+    GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129)
+    GENERATE_ENUM(TP_DATA_RETURN, 130)
+    GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131)
+    GENERATE_ENUM(SPI_WRITES_SP, 132)
+    GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133)
+    GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134)
+    GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135)
+    GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136)
+    GENERATE_ENUM(SP_EXPORTS_TO_SX, 137)
+    GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138)
+    GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139)
+    GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140)
+    GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141)
+    GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142)
+    GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143)
+    GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144)
+    GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145)
+    GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146)
+    GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147)
+    GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148)
+    GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149)
+    GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150)
+    GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151)
+    GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152)
+    GENERATE_ENUM(SQ_PIX_TOTAL, 153)
+    GENERATE_ENUM(SQ_PIX_KILLED, 154)
+END_ENUMTYPE(SQ_PERFCNT_SELECT)
+
+START_ENUMTYPE(SX_PERFCNT_SELECT)
+    GENERATE_ENUM(SX_EXPORT_VECTORS, 0)
+    GENERATE_ENUM(SX_DUMMY_QUADS, 1)
+    GENERATE_ENUM(SX_ALPHA_FAIL, 2)
+    GENERATE_ENUM(SX_RB_QUAD_BUSY, 3)
+    GENERATE_ENUM(SX_RB_COLOR_BUSY, 4)
+    GENERATE_ENUM(SX_RB_QUAD_STALL, 5)
+    GENERATE_ENUM(SX_RB_COLOR_STALL, 6)
+END_ENUMTYPE(SX_PERFCNT_SELECT)
+
+START_ENUMTYPE(Abs_modifier)
+    GENERATE_ENUM(NO_ABS_MOD, 0)
+    GENERATE_ENUM(ABS_MOD, 1)
+END_ENUMTYPE(Abs_modifier)
+
+START_ENUMTYPE(Exporting)
+    GENERATE_ENUM(NOT_EXPORTING, 0)
+    GENERATE_ENUM(EXPORTING, 1)
+END_ENUMTYPE(Exporting)
+
+START_ENUMTYPE(ScalarOpcode)
+    GENERATE_ENUM(ADDs, 0)
+    GENERATE_ENUM(ADD_PREVs, 1)
+    GENERATE_ENUM(MULs, 2)
+    GENERATE_ENUM(MUL_PREVs, 3)
+    GENERATE_ENUM(MUL_PREV2s, 4)
+    GENERATE_ENUM(MAXs, 5)
+    GENERATE_ENUM(MINs, 6)
+    GENERATE_ENUM(SETEs, 7)
+    GENERATE_ENUM(SETGTs, 8)
+    GENERATE_ENUM(SETGTEs, 9)
+    GENERATE_ENUM(SETNEs, 10)
+    GENERATE_ENUM(FRACs, 11)
+    GENERATE_ENUM(TRUNCs, 12)
+    GENERATE_ENUM(FLOORs, 13)
+    GENERATE_ENUM(EXP_IEEE, 14)
+    GENERATE_ENUM(LOG_CLAMP, 15)
+    GENERATE_ENUM(LOG_IEEE, 16)
+    GENERATE_ENUM(RECIP_CLAMP, 17)
+    GENERATE_ENUM(RECIP_FF, 18)
+    GENERATE_ENUM(RECIP_IEEE, 19)
+    GENERATE_ENUM(RECIPSQ_CLAMP, 20)
+    GENERATE_ENUM(RECIPSQ_FF, 21)
+    GENERATE_ENUM(RECIPSQ_IEEE, 22)
+    GENERATE_ENUM(MOVAs, 23)
+    GENERATE_ENUM(MOVA_FLOORs, 24)
+    GENERATE_ENUM(SUBs, 25)
+    GENERATE_ENUM(SUB_PREVs, 26)
+    GENERATE_ENUM(PRED_SETEs, 27)
+    GENERATE_ENUM(PRED_SETNEs, 28)
+    GENERATE_ENUM(PRED_SETGTs, 29)
+    GENERATE_ENUM(PRED_SETGTEs, 30)
+    GENERATE_ENUM(PRED_SET_INVs, 31)
+    GENERATE_ENUM(PRED_SET_POPs, 32)
+    GENERATE_ENUM(PRED_SET_CLRs, 33)
+    GENERATE_ENUM(PRED_SET_RESTOREs, 34)
+    GENERATE_ENUM(KILLEs, 35)
+    GENERATE_ENUM(KILLGTs, 36)
+    GENERATE_ENUM(KILLGTEs, 37)
+    GENERATE_ENUM(KILLNEs, 38)
+    GENERATE_ENUM(KILLONEs, 39)
+    GENERATE_ENUM(SQRT_IEEE, 40)
+    GENERATE_ENUM(MUL_CONST_0, 42)
+    GENERATE_ENUM(MUL_CONST_1, 43)
+    GENERATE_ENUM(ADD_CONST_0, 44)
+    GENERATE_ENUM(ADD_CONST_1, 45)
+    GENERATE_ENUM(SUB_CONST_0, 46)
+    GENERATE_ENUM(SUB_CONST_1, 47)
+    GENERATE_ENUM(SIN, 48)
+    GENERATE_ENUM(COS, 49)
+    GENERATE_ENUM(RETAIN_PREV, 50)
+END_ENUMTYPE(ScalarOpcode)
+
+START_ENUMTYPE(SwizzleType)
+    GENERATE_ENUM(NO_SWIZZLE, 0)
+    GENERATE_ENUM(SHIFT_RIGHT_1, 1)
+    GENERATE_ENUM(SHIFT_RIGHT_2, 2)
+    GENERATE_ENUM(SHIFT_RIGHT_3, 3)
+END_ENUMTYPE(SwizzleType)
+
+START_ENUMTYPE(InputModifier)
+    GENERATE_ENUM(NIL, 0)
+    GENERATE_ENUM(NEGATE, 1)
+END_ENUMTYPE(InputModifier)
+
+START_ENUMTYPE(PredicateSelect)
+    GENERATE_ENUM(NO_PREDICATION, 0)
+    GENERATE_ENUM(PREDICATE_QUAD, 1)
+    GENERATE_ENUM(PREDICATED_2, 2)
+    GENERATE_ENUM(PREDICATED_3, 3)
+END_ENUMTYPE(PredicateSelect)
+
+START_ENUMTYPE(OperandSelect1)
+    GENERATE_ENUM(ABSOLUTE_REG, 0)
+    GENERATE_ENUM(RELATIVE_REG, 1)
+END_ENUMTYPE(OperandSelect1)
+
+START_ENUMTYPE(VectorOpcode)
+    GENERATE_ENUM(ADDv, 0)
+    GENERATE_ENUM(MULv, 1)
+    GENERATE_ENUM(MAXv, 2)
+    GENERATE_ENUM(MINv, 3)
+    GENERATE_ENUM(SETEv, 4)
+    GENERATE_ENUM(SETGTv, 5)
+    GENERATE_ENUM(SETGTEv, 6)
+    GENERATE_ENUM(SETNEv, 7)
+    GENERATE_ENUM(FRACv, 8)
+    GENERATE_ENUM(TRUNCv, 9)
+    GENERATE_ENUM(FLOORv, 10)
+    GENERATE_ENUM(MULADDv, 11)
+    GENERATE_ENUM(CNDEv, 12)
+    GENERATE_ENUM(CNDGTEv, 13)
+    GENERATE_ENUM(CNDGTv, 14)
+    GENERATE_ENUM(DOT4v, 15)
+    GENERATE_ENUM(DOT3v, 16)
+    GENERATE_ENUM(DOT2ADDv, 17)
+    GENERATE_ENUM(CUBEv, 18)
+    GENERATE_ENUM(MAX4v, 19)
+    GENERATE_ENUM(PRED_SETE_PUSHv, 20)
+    GENERATE_ENUM(PRED_SETNE_PUSHv, 21)
+    GENERATE_ENUM(PRED_SETGT_PUSHv, 22)
+    GENERATE_ENUM(PRED_SETGTE_PUSHv, 23)
+    GENERATE_ENUM(KILLEv, 24)
+    GENERATE_ENUM(KILLGTv, 25)
+    GENERATE_ENUM(KILLGTEv, 26)
+    GENERATE_ENUM(KILLNEv, 27)
+    GENERATE_ENUM(DSTv, 28)
+    GENERATE_ENUM(MOVAv, 29)
+END_ENUMTYPE(VectorOpcode)
+
+START_ENUMTYPE(OperandSelect0)
+    GENERATE_ENUM(CONSTANT, 0)
+    GENERATE_ENUM(NON_CONSTANT, 1)
+END_ENUMTYPE(OperandSelect0)
+
+START_ENUMTYPE(Ressource_type)
+    GENERATE_ENUM(ALU, 0)
+    GENERATE_ENUM(TEXTURE, 1)
+END_ENUMTYPE(Ressource_type)
+
+START_ENUMTYPE(Instruction_serial)
+    GENERATE_ENUM(NOT_SERIAL, 0)
+    GENERATE_ENUM(SERIAL, 1)
+END_ENUMTYPE(Instruction_serial)
+
+START_ENUMTYPE(VC_type)
+    GENERATE_ENUM(ALU_TP_REQUEST, 0)
+    GENERATE_ENUM(VC_REQUEST, 1)
+END_ENUMTYPE(VC_type)
+
+START_ENUMTYPE(Addressing)
+    GENERATE_ENUM(RELATIVE_ADDR, 0)
+    GENERATE_ENUM(ABSOLUTE_ADDR, 1)
+END_ENUMTYPE(Addressing)
+
+START_ENUMTYPE(CFOpcode)
+    GENERATE_ENUM(NOP, 0)
+    GENERATE_ENUM(EXECUTE, 1)
+    GENERATE_ENUM(EXECUTE_END, 2)
+    GENERATE_ENUM(COND_EXECUTE, 3)
+    GENERATE_ENUM(COND_EXECUTE_END, 4)
+    GENERATE_ENUM(COND_PRED_EXECUTE, 5)
+    GENERATE_ENUM(COND_PRED_EXECUTE_END, 6)
+    GENERATE_ENUM(LOOP_START, 7)
+    GENERATE_ENUM(LOOP_END, 8)
+    GENERATE_ENUM(COND_CALL, 9)
+    GENERATE_ENUM(RETURN, 10)
+    GENERATE_ENUM(COND_JMP, 11)
+    GENERATE_ENUM(ALLOCATE, 12)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14)
+    GENERATE_ENUM(MARK_VS_FETCH_DONE, 15)
+END_ENUMTYPE(CFOpcode)
+
+START_ENUMTYPE(Allocation_type)
+    GENERATE_ENUM(SQ_NO_ALLOC, 0)
+    GENERATE_ENUM(SQ_POSITION, 1)
+    GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2)
+    GENERATE_ENUM(SQ_MEMORY, 3)
+END_ENUMTYPE(Allocation_type)
+
+START_ENUMTYPE(TexInstOpcode)
+    GENERATE_ENUM(TEX_INST_FETCH, 1)
+    GENERATE_ENUM(TEX_INST_RESERVED_1, 2)
+    GENERATE_ENUM(TEX_INST_RESERVED_2, 3)
+    GENERATE_ENUM(TEX_INST_RESERVED_3, 4)
+    GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16)
+    GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17)
+    GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18)
+    GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19)
+    GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26)
+    GENERATE_ENUM(TEX_INST_RESERVED_4, 27)
+END_ENUMTYPE(TexInstOpcode)
+
+START_ENUMTYPE(Addressmode)
+    GENERATE_ENUM(LOGICAL, 0)
+    GENERATE_ENUM(LOOP_RELATIVE, 1)
+END_ENUMTYPE(Addressmode)
+
+START_ENUMTYPE(TexCoordDenorm)
+    GENERATE_ENUM(TEX_COORD_NORMALIZED, 0)
+    GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1)
+END_ENUMTYPE(TexCoordDenorm)
+
+START_ENUMTYPE(SrcSel)
+    GENERATE_ENUM(SRC_SEL_X, 0)
+    GENERATE_ENUM(SRC_SEL_Y, 1)
+    GENERATE_ENUM(SRC_SEL_Z, 2)
+    GENERATE_ENUM(SRC_SEL_W, 3)
+END_ENUMTYPE(SrcSel)
+
+START_ENUMTYPE(DstSel)
+    GENERATE_ENUM(DST_SEL_X, 0)
+    GENERATE_ENUM(DST_SEL_Y, 1)
+    GENERATE_ENUM(DST_SEL_Z, 2)
+    GENERATE_ENUM(DST_SEL_W, 3)
+    GENERATE_ENUM(DST_SEL_0, 4)
+    GENERATE_ENUM(DST_SEL_1, 5)
+    GENERATE_ENUM(DST_SEL_RSVD, 6)
+    GENERATE_ENUM(DST_SEL_MASK, 7)
+END_ENUMTYPE(DstSel)
+
+START_ENUMTYPE(MagFilter)
+    GENERATE_ENUM(MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MagFilter)
+
+START_ENUMTYPE(MinFilter)
+    GENERATE_ENUM(MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MinFilter)
+
+START_ENUMTYPE(MipFilter)
+    GENERATE_ENUM(MIP_FILTER_POINT, 0)
+    GENERATE_ENUM(MIP_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIP_FILTER_BASEMAP, 2)
+    GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MipFilter)
+
+START_ENUMTYPE(AnisoFilter)
+    GENERATE_ENUM(ANISO_FILTER_DISABLED, 0)
+    GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1)
+    GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2)
+    GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3)
+    GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4)
+    GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5)
+    GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(AnisoFilter)
+
+START_ENUMTYPE(ArbitraryFilter)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5)
+    GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(ArbitraryFilter)
+
+START_ENUMTYPE(VolMagFilter)
+    GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMagFilter)
+
+START_ENUMTYPE(VolMinFilter)
+    GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMinFilter)
+
+START_ENUMTYPE(PredSelect)
+    GENERATE_ENUM(NOT_PREDICATED, 0)
+    GENERATE_ENUM(PREDICATED, 1)
+END_ENUMTYPE(PredSelect)
+
+START_ENUMTYPE(SampleLocation)
+    GENERATE_ENUM(SAMPLE_CENTROID, 0)
+    GENERATE_ENUM(SAMPLE_CENTER, 1)
+END_ENUMTYPE(SampleLocation)
+
+START_ENUMTYPE(VertexMode)
+    GENERATE_ENUM(POSITION_1_VECTOR, 0)
+    GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3)
+    GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6)
+    GENERATE_ENUM(MULTIPASS, 7)
+END_ENUMTYPE(VertexMode)
+
+START_ENUMTYPE(Sample_Cntl)
+    GENERATE_ENUM(CENTROIDS_ONLY, 0)
+    GENERATE_ENUM(CENTERS_ONLY, 1)
+    GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2)
+    GENERATE_ENUM(UNDEF, 3)
+END_ENUMTYPE(Sample_Cntl)
+
+START_ENUMTYPE(MhPerfEncode)
+    GENERATE_ENUM(CP_R0_REQUESTS, 0)
+    GENERATE_ENUM(CP_R1_REQUESTS, 1)
+    GENERATE_ENUM(CP_R2_REQUESTS, 2)
+    GENERATE_ENUM(CP_R3_REQUESTS, 3)
+    GENERATE_ENUM(CP_R4_REQUESTS, 4)
+    GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5)
+    GENERATE_ENUM(CP_W_REQUESTS, 6)
+    GENERATE_ENUM(CP_TOTAL_REQUESTS, 7)
+    GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8)
+    GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9)
+    GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10)
+    GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11)
+    GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12)
+    GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13)
+    GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14)
+    GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15)
+    GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16)
+    GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17)
+    GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18)
+    GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19)
+    GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20)
+    GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21)
+    GENERATE_ENUM(VGT_R0_REQUESTS, 22)
+    GENERATE_ENUM(VGT_R1_REQUESTS, 23)
+    GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24)
+    GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25)
+    GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26)
+    GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27)
+    GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28)
+    GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29)
+    GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30)
+    GENERATE_ENUM(TC_REQUESTS, 31)
+    GENERATE_ENUM(TC_ROQ_REQUESTS, 32)
+    GENERATE_ENUM(TC_INFO_SENT, 33)
+    GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34)
+    GENERATE_ENUM(TC_DATA_BEATS_READ, 35)
+    GENERATE_ENUM(TCD_BURSTS_READ, 36)
+    GENERATE_ENUM(RB_REQUESTS, 37)
+    GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38)
+    GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56)
+    GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111)
+    GENERATE_ENUM(TOTAL_MMU_MISSES, 112)
+    GENERATE_ENUM(MMU_READ_MISSES, 113)
+    GENERATE_ENUM(MMU_WRITE_MISSES, 114)
+    GENERATE_ENUM(TOTAL_MMU_HITS, 115)
+    GENERATE_ENUM(MMU_READ_HITS, 116)
+    GENERATE_ENUM(MMU_WRITE_HITS, 117)
+    GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118)
+    GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121)
+    GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122)
+    GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123)
+    GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124)
+    GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125)
+    GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127)
+    GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129)
+    GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130)
+    GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131)
+    GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132)
+    GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133)
+    GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136)
+    GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140)
+    GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148)
+    GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149)
+    GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150)
+    GENERATE_ENUM(TOTAL_MH_REQUESTS, 151)
+    GENERATE_ENUM(MH_BUSY, 152)
+    GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153)
+    GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154)
+    GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155)
+    GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156)
+    GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157)
+    GENERATE_ENUM(ARQ_N_ENTRIES, 158)
+    GENERATE_ENUM(WDB_N_ENTRIES, 159)
+    GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160)
+    GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161)
+    GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162)
+    GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163)
+END_ENUMTYPE(MhPerfEncode)
+
+START_ENUMTYPE(MmuClntBeh)
+    GENERATE_ENUM(BEH_NEVR, 0)
+    GENERATE_ENUM(BEH_TRAN_RNG, 1)
+    GENERATE_ENUM(BEH_TRAN_FLT, 2)
+END_ENUMTYPE(MmuClntBeh)
+
+START_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+    GENERATE_ENUM(RBBM1_COUNT, 0)
+    GENERATE_ENUM(RBBM1_NRT_BUSY, 1)
+    GENERATE_ENUM(RBBM1_RB_BUSY, 2)
+    GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3)
+    GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4)
+    GENERATE_ENUM(RBBM1_VGT_BUSY, 5)
+    GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6)
+    GENERATE_ENUM(RBBM1_PA_BUSY, 7)
+    GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8)
+    GENERATE_ENUM(RBBM1_TPC_BUSY, 9)
+    GENERATE_ENUM(RBBM1_TC_BUSY, 10)
+    GENERATE_ENUM(RBBM1_SX_BUSY, 11)
+    GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12)
+    GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13)
+    GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14)
+    GENERATE_ENUM(RBBM1_INTERRUPT, 15)
+END_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+
+START_ENUMTYPE(CP_PERFCOUNT_SEL)
+    GENERATE_ENUM(ALWAYS_COUNT, 0)
+    GENERATE_ENUM(TRANS_FIFO_FULL, 1)
+    GENERATE_ENUM(TRANS_FIFO_AF, 2)
+    GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3)
+    GENERATE_ENUM(Reserved_04, 4)
+    GENERATE_ENUM(Reserved_05, 5)
+    GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6)
+    GENERATE_ENUM(Reserved_07, 7)
+    GENERATE_ENUM(CSF_NRT_READ_WAIT, 8)
+    GENERATE_ENUM(CSF_I1_FIFO_FULL, 9)
+    GENERATE_ENUM(CSF_I2_FIFO_FULL, 10)
+    GENERATE_ENUM(CSF_ST_FIFO_FULL, 11)
+    GENERATE_ENUM(Reserved_12, 12)
+    GENERATE_ENUM(CSF_RING_ROQ_FULL, 13)
+    GENERATE_ENUM(CSF_I1_ROQ_FULL, 14)
+    GENERATE_ENUM(CSF_I2_ROQ_FULL, 15)
+    GENERATE_ENUM(CSF_ST_ROQ_FULL, 16)
+    GENERATE_ENUM(Reserved_17, 17)
+    GENERATE_ENUM(MIU_TAG_MEM_FULL, 18)
+    GENERATE_ENUM(MIU_WRITECLEAN, 19)
+    GENERATE_ENUM(Reserved_20, 20)
+    GENERATE_ENUM(Reserved_21, 21)
+    GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22)
+    GENERATE_ENUM(MIU_NRT_READ_STALLED, 23)
+    GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24)
+    GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25)
+    GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26)
+    GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27)
+    GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28)
+    GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29)
+    GENERATE_ENUM(ME_MICRO_RB_STARVED, 30)
+    GENERATE_ENUM(ME_MICRO_I1_STARVED, 31)
+    GENERATE_ENUM(ME_MICRO_I2_STARVED, 32)
+    GENERATE_ENUM(ME_MICRO_ST_STARVED, 33)
+    GENERATE_ENUM(Reserved_34, 34)
+    GENERATE_ENUM(Reserved_35, 35)
+    GENERATE_ENUM(Reserved_36, 36)
+    GENERATE_ENUM(Reserved_37, 37)
+    GENERATE_ENUM(Reserved_38, 38)
+    GENERATE_ENUM(Reserved_39, 39)
+    GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40)
+    GENERATE_ENUM(ME_BUSY_CLOCKS, 41)
+    GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42)
+    GENERATE_ENUM(PFP_TYPE0_PACKET, 43)
+    GENERATE_ENUM(PFP_TYPE3_PACKET, 44)
+    GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45)
+    GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46)
+    GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47)
+    GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48)
+    GENERATE_ENUM(Reserved_49, 49)
+    GENERATE_ENUM(Reserved_50, 50)
+    GENERATE_ENUM(Reserved_51, 51)
+    GENERATE_ENUM(Reserved_52, 52)
+    GENERATE_ENUM(Reserved_53, 53)
+    GENERATE_ENUM(Reserved_54, 54)
+    GENERATE_ENUM(Reserved_55, 55)
+    GENERATE_ENUM(Reserved_56, 56)
+    GENERATE_ENUM(Reserved_57, 57)
+    GENERATE_ENUM(Reserved_58, 58)
+    GENERATE_ENUM(Reserved_59, 59)
+    GENERATE_ENUM(Reserved_60, 60)
+    GENERATE_ENUM(Reserved_61, 61)
+    GENERATE_ENUM(Reserved_62, 62)
+    GENERATE_ENUM(Reserved_63, 63)
+END_ENUMTYPE(CP_PERFCOUNT_SEL)
+
+START_ENUMTYPE(ColorformatX)
+    GENERATE_ENUM(COLORX_4_4_4_4, 0)
+    GENERATE_ENUM(COLORX_1_5_5_5, 1)
+    GENERATE_ENUM(COLORX_5_6_5, 2)
+    GENERATE_ENUM(COLORX_8, 3)
+    GENERATE_ENUM(COLORX_8_8, 4)
+    GENERATE_ENUM(COLORX_8_8_8_8, 5)
+    GENERATE_ENUM(COLORX_S8_8_8_8, 6)
+    GENERATE_ENUM(COLORX_16_FLOAT, 7)
+    GENERATE_ENUM(COLORX_16_16_FLOAT, 8)
+    GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9)
+    GENERATE_ENUM(COLORX_32_FLOAT, 10)
+    GENERATE_ENUM(COLORX_32_32_FLOAT, 11)
+    GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12)
+    GENERATE_ENUM(COLORX_2_3_3, 13)
+    GENERATE_ENUM(COLORX_8_8_8, 14)
+END_ENUMTYPE(ColorformatX)
+
+START_ENUMTYPE(DepthformatX)
+    GENERATE_ENUM(DEPTHX_16, 0)
+    GENERATE_ENUM(DEPTHX_24_8, 1)
+END_ENUMTYPE(DepthformatX)
+
+START_ENUMTYPE(CompareFrag)
+    GENERATE_ENUM(FRAG_NEVER, 0)
+    GENERATE_ENUM(FRAG_LESS, 1)
+    GENERATE_ENUM(FRAG_EQUAL, 2)
+    GENERATE_ENUM(FRAG_LEQUAL, 3)
+    GENERATE_ENUM(FRAG_GREATER, 4)
+    GENERATE_ENUM(FRAG_NOTEQUAL, 5)
+    GENERATE_ENUM(FRAG_GEQUAL, 6)
+    GENERATE_ENUM(FRAG_ALWAYS, 7)
+END_ENUMTYPE(CompareFrag)
+
+START_ENUMTYPE(CompareRef)
+    GENERATE_ENUM(REF_NEVER, 0)
+    GENERATE_ENUM(REF_LESS, 1)
+    GENERATE_ENUM(REF_EQUAL, 2)
+    GENERATE_ENUM(REF_LEQUAL, 3)
+    GENERATE_ENUM(REF_GREATER, 4)
+    GENERATE_ENUM(REF_NOTEQUAL, 5)
+    GENERATE_ENUM(REF_GEQUAL, 6)
+    GENERATE_ENUM(REF_ALWAYS, 7)
+END_ENUMTYPE(CompareRef)
+
+START_ENUMTYPE(StencilOp)
+    GENERATE_ENUM(STENCIL_KEEP, 0)
+    GENERATE_ENUM(STENCIL_ZERO, 1)
+    GENERATE_ENUM(STENCIL_REPLACE, 2)
+    GENERATE_ENUM(STENCIL_INCR_CLAMP, 3)
+    GENERATE_ENUM(STENCIL_DECR_CLAMP, 4)
+    GENERATE_ENUM(STENCIL_INVERT, 5)
+    GENERATE_ENUM(STENCIL_INCR_WRAP, 6)
+    GENERATE_ENUM(STENCIL_DECR_WRAP, 7)
+END_ENUMTYPE(StencilOp)
+
+START_ENUMTYPE(BlendOpX)
+    GENERATE_ENUM(BLENDX_ZERO, 0)
+    GENERATE_ENUM(BLENDX_ONE, 1)
+    GENERATE_ENUM(BLENDX_SRC_COLOR, 4)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA, 6)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7)
+    GENERATE_ENUM(BLENDX_DST_COLOR, 8)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9)
+    GENERATE_ENUM(BLENDX_DST_ALPHA, 10)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11)
+    GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13)
+    GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16)
+END_ENUMTYPE(BlendOpX)
+
+START_ENUMTYPE(CombFuncX)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC, 0)
+    GENERATE_ENUM(COMB_SRC_MINUS_DST, 1)
+    GENERATE_ENUM(COMB_MIN_DST_SRC, 2)
+    GENERATE_ENUM(COMB_MAX_DST_SRC, 3)
+    GENERATE_ENUM(COMB_DST_MINUS_SRC, 4)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5)
+END_ENUMTYPE(CombFuncX)
+
+START_ENUMTYPE(DitherModeX)
+    GENERATE_ENUM(DITHER_DISABLE, 0)
+    GENERATE_ENUM(DITHER_ALWAYS, 1)
+    GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2)
+END_ENUMTYPE(DitherModeX)
+
+START_ENUMTYPE(DitherTypeX)
+    GENERATE_ENUM(DITHER_PIXEL, 0)
+    GENERATE_ENUM(DITHER_SUBPIXEL, 1)
+END_ENUMTYPE(DitherTypeX)
+
+START_ENUMTYPE(EdramMode)
+    GENERATE_ENUM(EDRAM_NOP, 0)
+    GENERATE_ENUM(COLOR_DEPTH, 4)
+    GENERATE_ENUM(DEPTH_ONLY, 5)
+    GENERATE_ENUM(EDRAM_COPY, 6)
+END_ENUMTYPE(EdramMode)
+
+START_ENUMTYPE(SurfaceEndian)
+    GENERATE_ENUM(ENDIAN_NONE, 0)
+    GENERATE_ENUM(ENDIAN_8IN16, 1)
+    GENERATE_ENUM(ENDIAN_8IN32, 2)
+    GENERATE_ENUM(ENDIAN_16IN32, 3)
+    GENERATE_ENUM(ENDIAN_8IN64, 4)
+    GENERATE_ENUM(ENDIAN_8IN128, 5)
+END_ENUMTYPE(SurfaceEndian)
+
+START_ENUMTYPE(EdramSizeX)
+    GENERATE_ENUM(EDRAMSIZE_16KB, 0)
+    GENERATE_ENUM(EDRAMSIZE_32KB, 1)
+    GENERATE_ENUM(EDRAMSIZE_64KB, 2)
+    GENERATE_ENUM(EDRAMSIZE_128KB, 3)
+    GENERATE_ENUM(EDRAMSIZE_256KB, 4)
+    GENERATE_ENUM(EDRAMSIZE_512KB, 5)
+    GENERATE_ENUM(EDRAMSIZE_1MB, 6)
+    GENERATE_ENUM(EDRAMSIZE_2MB, 7)
+    GENERATE_ENUM(EDRAMSIZE_4MB, 8)
+    GENERATE_ENUM(EDRAMSIZE_8MB, 9)
+    GENERATE_ENUM(EDRAMSIZE_16MB, 10)
+END_ENUMTYPE(EdramSizeX)
+
+START_ENUMTYPE(RB_PERFCNT_SELECT)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY, 0)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7)
+    GENERATE_ENUM(RBPERF_MH_STARVED, 8)
+    GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23)
+    GENERATE_ENUM(RBPERF_ZXP_STALL, 24)
+    GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING, 26)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID, 28)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30)
+    GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32)
+    GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33)
+    GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37)
+    GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38)
+    GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43)
+    GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44)
+    GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45)
+    GENERATE_ENUM(RBPERF_ZPASS_DONE, 46)
+    GENERATE_ENUM(RBPERF_ZCMD_VALID, 47)
+    GENERATE_ENUM(RBPERF_CCMD_VALID, 48)
+    GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49)
+    GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50)
+    GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51)
+    GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52)
+    GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53)
+    GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54)
+    GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55)
+    GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56)
+END_ENUMTYPE(RB_PERFCNT_SELECT)
+
+START_ENUMTYPE(DepthFormat)
+    GENERATE_ENUM(DEPTH_24_8, 22)
+    GENERATE_ENUM(DEPTH_24_8_FLOAT, 23)
+    GENERATE_ENUM(DEPTH_16, 24)
+END_ENUMTYPE(DepthFormat)
+
+START_ENUMTYPE(SurfaceSwap)
+    GENERATE_ENUM(SWAP_LOWRED, 0)
+    GENERATE_ENUM(SWAP_LOWBLUE, 1)
+END_ENUMTYPE(SurfaceSwap)
+
+START_ENUMTYPE(DepthArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0)
+    GENERATE_ENUM(ARRAY_2D_DEPTH, 1)
+END_ENUMTYPE(DepthArray)
+
+START_ENUMTYPE(ColorArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0)
+    GENERATE_ENUM(ARRAY_2D_COLOR, 1)
+    GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3)
+END_ENUMTYPE(ColorArray)
+
+START_ENUMTYPE(ColorFormat)
+    GENERATE_ENUM(COLOR_8, 2)
+    GENERATE_ENUM(COLOR_1_5_5_5, 3)
+    GENERATE_ENUM(COLOR_5_6_5, 4)
+    GENERATE_ENUM(COLOR_6_5_5, 5)
+    GENERATE_ENUM(COLOR_8_8_8_8, 6)
+    GENERATE_ENUM(COLOR_2_10_10_10, 7)
+    GENERATE_ENUM(COLOR_8_A, 8)
+    GENERATE_ENUM(COLOR_8_B, 9)
+    GENERATE_ENUM(COLOR_8_8, 10)
+    GENERATE_ENUM(COLOR_8_8_8, 11)
+    GENERATE_ENUM(COLOR_8_8_8_8_A, 14)
+    GENERATE_ENUM(COLOR_4_4_4_4, 15)
+    GENERATE_ENUM(COLOR_10_11_11, 16)
+    GENERATE_ENUM(COLOR_11_11_10, 17)
+    GENERATE_ENUM(COLOR_16, 24)
+    GENERATE_ENUM(COLOR_16_16, 25)
+    GENERATE_ENUM(COLOR_16_16_16_16, 26)
+    GENERATE_ENUM(COLOR_16_FLOAT, 30)
+    GENERATE_ENUM(COLOR_16_16_FLOAT, 31)
+    GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(COLOR_32_FLOAT, 36)
+    GENERATE_ENUM(COLOR_32_32_FLOAT, 37)
+    GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(COLOR_2_3_3, 39)
+END_ENUMTYPE(ColorFormat)
+
+START_ENUMTYPE(SurfaceNumber)
+    GENERATE_ENUM(NUMBER_UREPEAT, 0)
+    GENERATE_ENUM(NUMBER_SREPEAT, 1)
+    GENERATE_ENUM(NUMBER_UINTEGER, 2)
+    GENERATE_ENUM(NUMBER_SINTEGER, 3)
+    GENERATE_ENUM(NUMBER_GAMMA, 4)
+    GENERATE_ENUM(NUMBER_FIXED, 5)
+    GENERATE_ENUM(NUMBER_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumber)
+
+START_ENUMTYPE(SurfaceFormat)
+    GENERATE_ENUM(FMT_1_REVERSE, 0)
+    GENERATE_ENUM(FMT_1, 1)
+    GENERATE_ENUM(FMT_8, 2)
+    GENERATE_ENUM(FMT_1_5_5_5, 3)
+    GENERATE_ENUM(FMT_5_6_5, 4)
+    GENERATE_ENUM(FMT_6_5_5, 5)
+    GENERATE_ENUM(FMT_8_8_8_8, 6)
+    GENERATE_ENUM(FMT_2_10_10_10, 7)
+    GENERATE_ENUM(FMT_8_A, 8)
+    GENERATE_ENUM(FMT_8_B, 9)
+    GENERATE_ENUM(FMT_8_8, 10)
+    GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11)
+    GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12)
+    GENERATE_ENUM(FMT_5_5_5_1, 13)
+    GENERATE_ENUM(FMT_8_8_8_8_A, 14)
+    GENERATE_ENUM(FMT_4_4_4_4, 15)
+    GENERATE_ENUM(FMT_8_8_8, 16)
+    GENERATE_ENUM(FMT_DXT1, 18)
+    GENERATE_ENUM(FMT_DXT2_3, 19)
+    GENERATE_ENUM(FMT_DXT4_5, 20)
+    GENERATE_ENUM(FMT_10_10_10_2, 21)
+    GENERATE_ENUM(FMT_24_8, 22)
+    GENERATE_ENUM(FMT_16, 24)
+    GENERATE_ENUM(FMT_16_16, 25)
+    GENERATE_ENUM(FMT_16_16_16_16, 26)
+    GENERATE_ENUM(FMT_16_EXPAND, 27)
+    GENERATE_ENUM(FMT_16_16_EXPAND, 28)
+    GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29)
+    GENERATE_ENUM(FMT_16_FLOAT, 30)
+    GENERATE_ENUM(FMT_16_16_FLOAT, 31)
+    GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(FMT_32, 33)
+    GENERATE_ENUM(FMT_32_32, 34)
+    GENERATE_ENUM(FMT_32_32_32_32, 35)
+    GENERATE_ENUM(FMT_32_FLOAT, 36)
+    GENERATE_ENUM(FMT_32_32_FLOAT, 37)
+    GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(FMT_ATI_TC_RGB, 39)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA, 40)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44)
+    GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46)
+    GENERATE_ENUM(FMT_ETC1_RGB, 47)
+    GENERATE_ENUM(FMT_ETC1_RGBA, 48)
+    GENERATE_ENUM(FMT_DXN, 49)
+    GENERATE_ENUM(FMT_2_3_3, 51)
+    GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54)
+    GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55)
+    GENERATE_ENUM(FMT_32_32_32_FLOAT, 57)
+    GENERATE_ENUM(FMT_DXT3A, 58)
+    GENERATE_ENUM(FMT_DXT5A, 59)
+    GENERATE_ENUM(FMT_CTX1, 60)
+END_ENUMTYPE(SurfaceFormat)
+
+START_ENUMTYPE(SurfaceTiling)
+    GENERATE_ENUM(ARRAY_LINEAR, 0)
+    GENERATE_ENUM(ARRAY_TILED, 1)
+END_ENUMTYPE(SurfaceTiling)
+
+START_ENUMTYPE(SurfaceArray)
+    GENERATE_ENUM(ARRAY_1D, 0)
+    GENERATE_ENUM(ARRAY_2D, 1)
+    GENERATE_ENUM(ARRAY_3D, 2)
+    GENERATE_ENUM(ARRAY_3D_SLICE, 3)
+END_ENUMTYPE(SurfaceArray)
+
+START_ENUMTYPE(SurfaceNumberX)
+    GENERATE_ENUM(NUMBERX_UREPEAT, 0)
+    GENERATE_ENUM(NUMBERX_SREPEAT, 1)
+    GENERATE_ENUM(NUMBERX_UINTEGER, 2)
+    GENERATE_ENUM(NUMBERX_SINTEGER, 3)
+    GENERATE_ENUM(NUMBERX_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumberX)
+
+START_ENUMTYPE(ColorArrayX)
+    GENERATE_ENUM(ARRAYX_2D_COLOR, 0)
+    GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1)
+END_ENUMTYPE(ColorArrayX)
+
+
+
+
+// **************************************************************************
+// These are ones that had to be added in addition to what's generated
+// by the autoreg (in CSIM)
+// **************************************************************************
+START_ENUMTYPE(DXClipSpaceDef)
+    GENERATE_ENUM(DXCLIP_OPENGL, 0)
+    GENERATE_ENUM(DXCLIP_DIRECTX, 1)
+END_ENUMTYPE(DXClipSpaceDef)
+
+START_ENUMTYPE(PixCenter)
+    GENERATE_ENUM(PIXCENTER_D3D, 0)
+    GENERATE_ENUM(PIXCENTER_OGL, 1)
+END_ENUMTYPE(PixCenter)
+
+START_ENUMTYPE(RoundMode)
+    GENERATE_ENUM(TRUNCATE,   0)
+    GENERATE_ENUM(ROUND,      1)
+    GENERATE_ENUM(ROUNDTOEVEN,    2)
+    GENERATE_ENUM(ROUNDTOODD,     3)
+END_ENUMTYPE(RoundMode)
+
+START_ENUMTYPE(QuantMode)
+    GENERATE_ENUM(ONE_SIXTEENTH,   0)
+    GENERATE_ENUM(ONE_EIGHTH,      1)
+    GENERATE_ENUM(ONE_QUARTER,     2)
+    GENERATE_ENUM(ONE_HALF,    3)
+    GENERATE_ENUM(ONE,         4)
+END_ENUMTYPE(QuantMode)
+
+START_ENUMTYPE(FrontFace)
+    GENERATE_ENUM(FRONT_CCW,        0)
+    GENERATE_ENUM(FRONT_CW,     1)
+END_ENUMTYPE(FrontFace)
+
+START_ENUMTYPE(PolyMode)
+    GENERATE_ENUM(DISABLED,    0)
+    GENERATE_ENUM(DUALMODE,    1)
+END_ENUMTYPE(PolyMode)
+
+START_ENUMTYPE(PType)
+    GENERATE_ENUM(DRAW_POINTS,      0)
+    GENERATE_ENUM(DRAW_LINES,       1)
+    GENERATE_ENUM(DRAW_TRIANGLES,   2)
+END_ENUMTYPE(PType)
+
+START_ENUMTYPE(MSAANumSamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     3)
+END_ENUMTYPE(MSAANumSamples)
+
+START_ENUMTYPE(PatternBitOrder)
+    GENERATE_ENUM(LITTLE,   0)
+    GENERATE_ENUM(BIG,      1)
+END_ENUMTYPE(PatternBitOrder)
+
+START_ENUMTYPE(AutoResetCntl)
+    GENERATE_ENUM(NEVER,        0)
+    GENERATE_ENUM(EACHPRIMITIVE,    1)
+    GENERATE_ENUM(EACHPACKET,       2)
+END_ENUMTYPE(AutoResetCntl)
+
+START_ENUMTYPE(ParamShade)
+    GENERATE_ENUM(FLAT,     0)
+    GENERATE_ENUM(GOURAUD,  1)
+END_ENUMTYPE(ParamShade)
+
+START_ENUMTYPE(SamplingPattern)
+    GENERATE_ENUM(CENTROID, 0)
+    GENERATE_ENUM(PIXCENTER, 1)
+END_ENUMTYPE(SamplingPattern)
+
+START_ENUMTYPE(MSAASamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     2)
+END_ENUMTYPE(MSAASamples)
+
+START_ENUMTYPE(CopySampleSelect)
+    GENERATE_ENUM(SAMPLE_0, 0)
+    GENERATE_ENUM(SAMPLE_1, 1)
+    GENERATE_ENUM(SAMPLE_2, 2)
+    GENERATE_ENUM(SAMPLE_3, 3)
+    GENERATE_ENUM(SAMPLE_01,    4)
+    GENERATE_ENUM(SAMPLE_23,    5)
+    GENERATE_ENUM(SAMPLE_0123,  6)
+END_ENUMTYPE(CopySampleSelect)
+
+
+#undef START_ENUMTYPE
+#undef GENERATE_ENUM
+#undef END_ENUMTYPE
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h
new file mode 100644
index 00000000000..d44be483e95
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h
@@ -0,0 +1,3310 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_REGISTER(PA_CL_VPORT_XSCALE)
+    GENERATE_FIELD(VPORT_XSCALE, float)
+END_REGISTER(PA_CL_VPORT_XSCALE)
+
+START_REGISTER(PA_CL_VPORT_XOFFSET)
+    GENERATE_FIELD(VPORT_XOFFSET, float)
+END_REGISTER(PA_CL_VPORT_XOFFSET)
+
+START_REGISTER(PA_CL_VPORT_YSCALE)
+    GENERATE_FIELD(VPORT_YSCALE, float)
+END_REGISTER(PA_CL_VPORT_YSCALE)
+
+START_REGISTER(PA_CL_VPORT_YOFFSET)
+    GENERATE_FIELD(VPORT_YOFFSET, float)
+END_REGISTER(PA_CL_VPORT_YOFFSET)
+
+START_REGISTER(PA_CL_VPORT_ZSCALE)
+    GENERATE_FIELD(VPORT_ZSCALE, float)
+END_REGISTER(PA_CL_VPORT_ZSCALE)
+
+START_REGISTER(PA_CL_VPORT_ZOFFSET)
+    GENERATE_FIELD(VPORT_ZOFFSET, float)
+END_REGISTER(PA_CL_VPORT_ZOFFSET)
+
+START_REGISTER(PA_CL_VTE_CNTL)
+    GENERATE_FIELD(VPORT_X_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool)
+    GENERATE_FIELD(VTX_XY_FMT, bool)
+    GENERATE_FIELD(VTX_Z_FMT, bool)
+    GENERATE_FIELD(VTX_W0_FMT, bool)
+    GENERATE_FIELD(PERFCOUNTER_REF, bool)
+END_REGISTER(PA_CL_VTE_CNTL)
+
+START_REGISTER(PA_CL_CLIP_CNTL)
+    GENERATE_FIELD(CLIP_DISABLE, bool)
+    GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool)
+    GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef)
+    GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool)
+    GENERATE_FIELD(VTX_KILL_OR, bool)
+    GENERATE_FIELD(XY_NAN_RETAIN, bool)
+    GENERATE_FIELD(Z_NAN_RETAIN, bool)
+    GENERATE_FIELD(W_NAN_RETAIN, bool)
+END_REGISTER(PA_CL_CLIP_CNTL)
+
+START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+
+START_REGISTER(PA_CL_ENHANCE)
+    GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_CL_ENHANCE)
+
+START_REGISTER(PA_SC_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_SC_ENHANCE)
+
+START_REGISTER(PA_SU_VTX_CNTL)
+    GENERATE_FIELD(PIX_CENTER, PixCenter)
+    GENERATE_FIELD(ROUND_MODE, RoundMode)
+    GENERATE_FIELD(QUANT_MODE, QuantMode)
+END_REGISTER(PA_SU_VTX_CNTL)
+
+START_REGISTER(PA_SU_POINT_SIZE)
+    GENERATE_FIELD(HEIGHT, fixed12_4)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_POINT_SIZE)
+
+START_REGISTER(PA_SU_POINT_MINMAX)
+    GENERATE_FIELD(MIN_SIZE, fixed12_4)
+    GENERATE_FIELD(MAX_SIZE, fixed12_4)
+END_REGISTER(PA_SU_POINT_MINMAX)
+
+START_REGISTER(PA_SU_LINE_CNTL)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_LINE_CNTL)
+
+START_REGISTER(PA_SU_SC_MODE_CNTL)
+    GENERATE_FIELD(CULL_FRONT, bool)
+    GENERATE_FIELD(CULL_BACK, bool)
+    GENERATE_FIELD(FACE, FrontFace)
+    GENERATE_FIELD(POLY_MODE, PolyMode)
+    GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType)
+    GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType)
+    GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool)
+    GENERATE_FIELD(MSAA_ENABLE, bool)
+    GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool)
+    GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool)
+    GENERATE_FIELD(PROVOKING_VTX_LAST, bool)
+    GENERATE_FIELD(PERSP_CORR_DIS, bool)
+    GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool)
+    GENERATE_FIELD(QUAD_ORDER_ENABLE, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool)
+END_REGISTER(PA_SU_SC_MODE_CNTL)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT)
+END_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_HI)
+
+START_REGISTER(PA_SC_WINDOW_OFFSET)
+    GENERATE_FIELD(WINDOW_X_OFFSET, signedint15)
+    GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15)
+END_REGISTER(PA_SC_WINDOW_OFFSET)
+
+START_REGISTER(PA_SC_AA_CONFIG)
+    GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples)
+    GENERATE_FIELD(MAX_SAMPLE_DIST, int)
+END_REGISTER(PA_SC_AA_CONFIG)
+
+START_REGISTER(PA_SC_AA_MASK)
+    GENERATE_FIELD(AA_MASK, hex)
+END_REGISTER(PA_SC_AA_MASK)
+
+START_REGISTER(PA_SC_LINE_STIPPLE)
+    GENERATE_FIELD(LINE_PATTERN, hex)
+    GENERATE_FIELD(REPEAT_COUNT, intMinusOne)
+    GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder)
+    GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl)
+END_REGISTER(PA_SC_LINE_STIPPLE)
+
+START_REGISTER(PA_SC_LINE_CNTL)
+    GENERATE_FIELD(BRES_CNTL, int)
+    GENERATE_FIELD(USE_BRES_CNTL, bool)
+    GENERATE_FIELD(EXPAND_LINE_WIDTH, bool)
+    GENERATE_FIELD(LAST_PIXEL, bool)
+END_REGISTER(PA_SC_LINE_CNTL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+
+START_REGISTER(PA_SC_VIZ_QUERY)
+    GENERATE_FIELD(VIZ_QUERY_ENA, bool)
+    GENERATE_FIELD(VIZ_QUERY_ID, int)
+    GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool)
+END_REGISTER(PA_SC_VIZ_QUERY)
+
+START_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+    GENERATE_FIELD(STATUS_BITS, hex)
+END_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+
+START_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+    GENERATE_FIELD(CURRENT_PTR, int)
+    GENERATE_FIELD(CURRENT_COUNT, int)
+END_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT)
+END_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_CL_CNTL_STATUS)
+    GENERATE_FIELD(CL_BUSY, int)
+END_REGISTER(PA_CL_CNTL_STATUS)
+
+START_REGISTER(PA_SU_CNTL_STATUS)
+    GENERATE_FIELD(SU_BUSY, int)
+END_REGISTER(PA_SU_CNTL_STATUS)
+
+START_REGISTER(PA_SC_CNTL_STATUS)
+    GENERATE_FIELD(SC_BUSY, int)
+END_REGISTER(PA_SC_CNTL_STATUS)
+
+START_REGISTER(PA_SU_DEBUG_CNTL)
+    GENERATE_FIELD(SU_DEBUG_INDX, int)
+END_REGISTER(PA_SU_DEBUG_CNTL)
+
+START_REGISTER(PA_SU_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(PA_SU_DEBUG_DATA)
+
+START_REGISTER(PA_SC_DEBUG_CNTL)
+    GENERATE_FIELD(SC_DEBUG_INDX, int)
+END_REGISTER(PA_SC_DEBUG_CNTL)
+
+START_REGISTER(PA_SC_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(PA_SC_DEBUG_DATA)
+
+START_REGISTER(GFX_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(GFX_COPY_STATE)
+
+START_REGISTER(VGT_DRAW_INITIATOR)
+    GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE)
+    GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT)
+    GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE)
+    GENERATE_FIELD(NOT_EOP, bool)
+    GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX)
+    GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_FIELD(NUM_INDICES, uint)
+END_REGISTER(VGT_DRAW_INITIATOR)
+
+START_REGISTER(VGT_EVENT_INITIATOR)
+    GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE)
+END_REGISTER(VGT_EVENT_INITIATOR)
+
+START_REGISTER(VGT_DMA_BASE)
+    GENERATE_FIELD(BASE_ADDR, uint)
+END_REGISTER(VGT_DMA_BASE)
+
+START_REGISTER(VGT_DMA_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+    GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE)
+END_REGISTER(VGT_DMA_SIZE)
+
+START_REGISTER(VGT_BIN_BASE)
+    GENERATE_FIELD(BIN_BASE_ADDR, uint)
+END_REGISTER(VGT_BIN_BASE)
+
+START_REGISTER(VGT_BIN_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+END_REGISTER(VGT_BIN_SIZE)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+
+START_REGISTER(VGT_IMMED_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_IMMED_DATA)
+
+START_REGISTER(VGT_MAX_VTX_INDX)
+    GENERATE_FIELD(MAX_INDX, int)
+END_REGISTER(VGT_MAX_VTX_INDX)
+
+START_REGISTER(VGT_MIN_VTX_INDX)
+    GENERATE_FIELD(MIN_INDX, int)
+END_REGISTER(VGT_MIN_VTX_INDX)
+
+START_REGISTER(VGT_INDX_OFFSET)
+    GENERATE_FIELD(INDX_OFFSET, int)
+END_REGISTER(VGT_INDX_OFFSET)
+
+START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+    GENERATE_FIELD(VTX_REUSE_DEPTH, int)
+END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+
+START_REGISTER(VGT_OUT_DEALLOC_CNTL)
+    GENERATE_FIELD(DEALLOC_DIST, int)
+END_REGISTER(VGT_OUT_DEALLOC_CNTL)
+
+START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+    GENERATE_FIELD(RESET_INDX, int)
+END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+
+START_REGISTER(VGT_ENHANCE)
+    GENERATE_FIELD(MISC, hex)
+END_REGISTER(VGT_ENHANCE)
+
+START_REGISTER(VGT_VTX_VECT_EJECT_REG)
+    GENERATE_FIELD(PRIM_COUNT, int)
+END_REGISTER(VGT_VTX_VECT_EJECT_REG)
+
+START_REGISTER(VGT_LAST_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+    GENERATE_FIELD(DST_STATE_ID, int)
+END_REGISTER(VGT_LAST_COPY_STATE)
+
+START_REGISTER(VGT_DEBUG_CNTL)
+    GENERATE_FIELD(VGT_DEBUG_INDX, int)
+END_REGISTER(VGT_DEBUG_CNTL)
+
+START_REGISTER(VGT_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_DEBUG_DATA)
+
+START_REGISTER(VGT_CNTL_STATUS)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_REQ_BUSY, int)
+    GENERATE_FIELD(VGT_GRP_BUSY, int)
+    GENERATE_FIELD(VGT_VR_BUSY, int)
+    GENERATE_FIELD(VGT_BIN_BUSY, int)
+    GENERATE_FIELD(VGT_PT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_INDX_BUSY, int)
+END_REGISTER(VGT_CNTL_STATUS)
+
+START_REGISTER(VGT_CRC_SQ_DATA)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_DATA)
+
+START_REGISTER(VGT_CRC_SQ_CTRL)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_CTRL)
+
+START_REGISTER(VGT_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER0_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER1_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER2_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER3_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_HI)
+
+START_REGISTER(VGT_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_HI)
+
+START_REGISTER(VGT_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_HI)
+
+START_REGISTER(VGT_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_HI)
+
+START_REGISTER(TC_CNTL_STATUS)
+    GENERATE_FIELD(L2_INVALIDATE, int)
+    GENERATE_FIELD(TC_L2_HIT_MISS, int)
+    GENERATE_FIELD(TC_BUSY, int)
+END_REGISTER(TC_CNTL_STATUS)
+
+START_REGISTER(TCR_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCR_CHICKEN)
+
+START_REGISTER(TCF_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCF_CHICKEN)
+
+START_REGISTER(TCM_CHICKEN)
+    GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int)
+    GENERATE_FIELD(ETC_COLOR_ENDIAN, int)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCM_CHICKEN)
+
+START_REGISTER(TCR_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER0_HI)
+
+START_REGISTER(TCR_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER1_HI)
+
+START_REGISTER(TCR_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCR_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER1_LOW)
+
+START_REGISTER(TP_TC_CLKGATE_CNTL)
+    GENERATE_FIELD(TP_BUSY_EXTEND, int)
+    GENERATE_FIELD(TC_BUSY_EXTEND, int)
+END_REGISTER(TP_TC_CLKGATE_CNTL)
+
+START_REGISTER(TPC_CNTL_STATUS)
+    GENERATE_FIELD(TPC_INPUT_BUSY, int)
+    GENERATE_FIELD(TPC_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TPC_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_BUSY, int)
+    GENERATE_FIELD(TF_TW_RTS, int)
+    GENERATE_FIELD(TF_TW_STATE_RTS, int)
+    GENERATE_FIELD(TF_TW_RTR, int)
+    GENERATE_FIELD(TW_TA_RTS, int)
+    GENERATE_FIELD(TW_TA_TT_RTS, int)
+    GENERATE_FIELD(TW_TA_LAST_RTS, int)
+    GENERATE_FIELD(TW_TA_RTR, int)
+    GENERATE_FIELD(TA_TB_RTS, int)
+    GENERATE_FIELD(TA_TB_TT_RTS, int)
+    GENERATE_FIELD(TA_TB_RTR, int)
+    GENERATE_FIELD(TA_TF_RTS, int)
+    GENERATE_FIELD(TA_TF_TC_FIFO_REN, int)
+    GENERATE_FIELD(TP_SQ_DEC, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+END_REGISTER(TPC_CNTL_STATUS)
+
+START_REGISTER(TPC_DEBUG0)
+    GENERATE_FIELD(LOD_CNTL, int)
+    GENERATE_FIELD(IC_CTR, int)
+    GENERATE_FIELD(WALKER_CNTL, int)
+    GENERATE_FIELD(ALIGNER_CNTL, int)
+    GENERATE_FIELD(PREV_TC_STATE_VALID, int)
+    GENERATE_FIELD(WALKER_STATE, int)
+    GENERATE_FIELD(ALIGNER_STATE, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(TPC_CLK_EN, int)
+    GENERATE_FIELD(SQ_TP_WAKEUP, int)
+END_REGISTER(TPC_DEBUG0)
+
+START_REGISTER(TPC_DEBUG1)
+    GENERATE_FIELD(UNUSED, int)
+END_REGISTER(TPC_DEBUG1)
+
+START_REGISTER(TPC_CHICKEN)
+    GENERATE_FIELD(BLEND_PRECISION, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TPC_CHICKEN)
+
+START_REGISTER(TP0_CNTL_STATUS)
+    GENERATE_FIELD(TP_INPUT_BUSY, int)
+    GENERATE_FIELD(TP_LOD_BUSY, int)
+    GENERATE_FIELD(TP_LOD_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ADDR_BUSY, int)
+    GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TP_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_FETCH_BUSY, int)
+    GENERATE_FIELD(TP_CH_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_TT_BUSY, int)
+    GENERATE_FIELD(TP_HICOLOR_BUSY, int)
+    GENERATE_FIELD(TP_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_OUTPUT_BUSY, int)
+    GENERATE_FIELD(IN_LC_RTS, int)
+    GENERATE_FIELD(LC_LA_RTS, int)
+    GENERATE_FIELD(LA_FL_RTS, int)
+    GENERATE_FIELD(FL_TA_RTS, int)
+    GENERATE_FIELD(TA_FA_RTS, int)
+    GENERATE_FIELD(TA_FA_TT_RTS, int)
+    GENERATE_FIELD(FA_AL_RTS, int)
+    GENERATE_FIELD(FA_AL_TT_RTS, int)
+    GENERATE_FIELD(AL_TF_RTS, int)
+    GENERATE_FIELD(AL_TF_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_RTS, int)
+    GENERATE_FIELD(TF_TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_TT_RESET, int)
+    GENERATE_FIELD(TB_TO_RTS, int)
+    GENERATE_FIELD(TP_BUSY, int)
+END_REGISTER(TP0_CNTL_STATUS)
+
+START_REGISTER(TP0_DEBUG)
+    GENERATE_FIELD(Q_LOD_CNTL, int)
+    GENERATE_FIELD(Q_SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(PERF_CLK_EN, int)
+    GENERATE_FIELD(TP_CLK_EN, int)
+    GENERATE_FIELD(Q_WALKER_CNTL, int)
+    GENERATE_FIELD(Q_ALIGNER_CNTL, int)
+END_REGISTER(TP0_DEBUG)
+
+START_REGISTER(TP0_CHICKEN)
+    GENERATE_FIELD(TT_MODE, int)
+    GENERATE_FIELD(VFETCH_ADDRESS_MODE, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TP0_CHICKEN)
+
+START_REGISTER(TP0_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT)
+END_REGISTER(TP0_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER0_HI)
+
+START_REGISTER(TP0_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER0_LOW)
+
+START_REGISTER(TP0_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, int)
+END_REGISTER(TP0_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER1_HI)
+
+START_REGISTER(TP0_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER0_HI)
+
+START_REGISTER(TCM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER1_HI)
+
+START_REGISTER(TCM_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER2_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER3_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER4_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER4_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER5_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER5_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER6_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER6_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER7_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER7_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER8_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER8_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER9_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER9_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER10_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER10_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER11_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER11_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER0_HI)
+
+START_REGISTER(TCF_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER1_HI)
+
+START_REGISTER(TCF_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER2_HI)
+
+START_REGISTER(TCF_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER3_HI)
+
+START_REGISTER(TCF_PERFCOUNTER4_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER4_HI)
+
+START_REGISTER(TCF_PERFCOUNTER5_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER5_HI)
+
+START_REGISTER(TCF_PERFCOUNTER6_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER6_HI)
+
+START_REGISTER(TCF_PERFCOUNTER7_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER7_HI)
+
+START_REGISTER(TCF_PERFCOUNTER8_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER8_HI)
+
+START_REGISTER(TCF_PERFCOUNTER9_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER9_HI)
+
+START_REGISTER(TCF_PERFCOUNTER10_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER10_HI)
+
+START_REGISTER(TCF_PERFCOUNTER11_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER11_HI)
+
+START_REGISTER(TCF_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER2_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER3_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER4_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER4_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER5_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER5_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER6_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER6_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER7_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER7_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER8_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER8_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER9_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER9_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER10_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER10_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER11_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER11_LOW)
+
+START_REGISTER(TCF_DEBUG)
+    GENERATE_FIELD(not_MH_TC_rtr, int)
+    GENERATE_FIELD(TC_MH_send, int)
+    GENERATE_FIELD(not_FG0_rtr, int)
+    GENERATE_FIELD(not_TCB_TCO_rtr, int)
+    GENERATE_FIELD(TCB_ff_stall, int)
+    GENERATE_FIELD(TCB_miss_stall, int)
+    GENERATE_FIELD(TCA_TCB_stall, int)
+    GENERATE_FIELD(PF0_stall, int)
+    GENERATE_FIELD(TP0_full, int)
+    GENERATE_FIELD(TPC_full, int)
+    GENERATE_FIELD(not_TPC_rtr, int)
+    GENERATE_FIELD(tca_state_rts, int)
+    GENERATE_FIELD(tca_rts, int)
+END_REGISTER(TCF_DEBUG)
+
+START_REGISTER(TCA_FIFO_DEBUG)
+    GENERATE_FIELD(tp0_full, int)
+    GENERATE_FIELD(tpc_full, int)
+    GENERATE_FIELD(load_tpc_fifo, int)
+    GENERATE_FIELD(load_tp_fifos, int)
+    GENERATE_FIELD(FW_full, int)
+    GENERATE_FIELD(not_FW_rtr0, int)
+    GENERATE_FIELD(FW_rts0, int)
+    GENERATE_FIELD(not_FW_tpc_rtr, int)
+    GENERATE_FIELD(FW_tpc_rts, int)
+END_REGISTER(TCA_FIFO_DEBUG)
+
+START_REGISTER(TCA_PROBE_DEBUG)
+    GENERATE_FIELD(ProbeFilter_stall, int)
+END_REGISTER(TCA_PROBE_DEBUG)
+
+START_REGISTER(TCA_TPC_DEBUG)
+    GENERATE_FIELD(captue_state_rts, int)
+    GENERATE_FIELD(capture_tca_rts, int)
+END_REGISTER(TCA_TPC_DEBUG)
+
+START_REGISTER(TCB_CORE_DEBUG)
+    GENERATE_FIELD(access512, int)
+    GENERATE_FIELD(tiled, int)
+    GENERATE_FIELD(opcode, int)
+    GENERATE_FIELD(format, int)
+    GENERATE_FIELD(sector_format, int)
+    GENERATE_FIELD(sector_format512, int)
+END_REGISTER(TCB_CORE_DEBUG)
+
+START_REGISTER(TCB_TAG0_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG0_DEBUG)
+
+START_REGISTER(TCB_TAG1_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG1_DEBUG)
+
+START_REGISTER(TCB_TAG2_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG2_DEBUG)
+
+START_REGISTER(TCB_TAG3_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG3_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+    GENERATE_FIELD(left_done, int)
+    GENERATE_FIELD(fg0_sends_left, int)
+    GENERATE_FIELD(one_sector_to_go_left_q, int)
+    GENERATE_FIELD(no_sectors_to_go, int)
+    GENERATE_FIELD(update_left, int)
+    GENERATE_FIELD(sector_mask_left_count_q, int)
+    GENERATE_FIELD(sector_mask_left_q, int)
+    GENERATE_FIELD(valid_left_q, int)
+END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+    GENERATE_FIELD(quad_sel_left, int)
+    GENERATE_FIELD(set_sel_left, int)
+    GENERATE_FIELD(right_eq_left, int)
+    GENERATE_FIELD(ff_fg_type512, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(setquads_to_send, int)
+END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+    GENERATE_FIELD(tc0_arb_rts, int)
+    GENERATE_FIELD(ga_out_rts, int)
+    GENERATE_FIELD(tc_arb_format, int)
+    GENERATE_FIELD(tc_arb_fmsopcode, int)
+    GENERATE_FIELD(tc_arb_request_type, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(fgo_busy, int)
+    GENERATE_FIELD(ga_busy, int)
+    GENERATE_FIELD(mc_sel_q, int)
+    GENERATE_FIELD(valid_q, int)
+    GENERATE_FIELD(arb_RTR, int)
+END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+
+START_REGISTER(TCD_INPUT0_DEBUG)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(valid_q1, int)
+    GENERATE_FIELD(cnt_q1, int)
+    GENERATE_FIELD(last_send_q1, int)
+    GENERATE_FIELD(ip_send, int)
+    GENERATE_FIELD(ipbuf_dxt_send, int)
+    GENERATE_FIELD(ipbuf_busy, int)
+END_REGISTER(TCD_INPUT0_DEBUG)
+
+START_REGISTER(TCD_DEGAMMA_DEBUG)
+    GENERATE_FIELD(dgmm_ftfconv_dgmmen, int)
+    GENERATE_FIELD(dgmm_ctrl_dgmm8, int)
+    GENERATE_FIELD(dgmm_ctrl_last_send, int)
+    GENERATE_FIELD(dgmm_ctrl_send, int)
+    GENERATE_FIELD(dgmm_stall, int)
+    GENERATE_FIELD(dgmm_pstate, int)
+END_REGISTER(TCD_DEGAMMA_DEBUG)
+
+START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(sctrmx_rtr, int)
+    GENERATE_FIELD(dxtc_rtr, int)
+    GENERATE_FIELD(sctrarb_multcyl_send, int)
+    GENERATE_FIELD(sctrmx0_sctrarb_rts, int)
+    GENERATE_FIELD(dxtc_sctrarb_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_last_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_send, int)
+    GENERATE_FIELD(dcmp_mux_send, int)
+END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+
+START_REGISTER(TCD_DXTC_ARB_DEBUG)
+    GENERATE_FIELD(n0_stall, int)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(arb_dcmp01_last_send, int)
+    GENERATE_FIELD(arb_dcmp01_cnt, int)
+    GENERATE_FIELD(arb_dcmp01_sector, int)
+    GENERATE_FIELD(arb_dcmp01_cacheline, int)
+    GENERATE_FIELD(arb_dcmp01_format, int)
+    GENERATE_FIELD(arb_dcmp01_send, int)
+    GENERATE_FIELD(n0_dxt2_4_types, int)
+END_REGISTER(TCD_DXTC_ARB_DEBUG)
+
+START_REGISTER(TCD_STALLS_DEBUG)
+    GENERATE_FIELD(not_multcyl_sctrarb_rtr, int)
+    GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int)
+    GENERATE_FIELD(not_dcmp0_arb_rtr, int)
+    GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int)
+    GENERATE_FIELD(not_mux_dcmp_rtr, int)
+    GENERATE_FIELD(not_incoming_rtr, int)
+END_REGISTER(TCD_STALLS_DEBUG)
+
+START_REGISTER(TCO_STALLS_DEBUG)
+    GENERATE_FIELD(quad0_sg_crd_RTR, int)
+    GENERATE_FIELD(quad0_rl_sg_RTR, int)
+    GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int)
+END_REGISTER(TCO_STALLS_DEBUG)
+
+START_REGISTER(TCO_QUAD0_DEBUG0)
+    GENERATE_FIELD(rl_sg_sector_format, int)
+    GENERATE_FIELD(rl_sg_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_end_of_sample, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(stageN1_valid_q, int)
+    GENERATE_FIELD(read_cache_q, int)
+    GENERATE_FIELD(cache_read_RTR, int)
+    GENERATE_FIELD(all_sectors_written_set3, int)
+    GENERATE_FIELD(all_sectors_written_set2, int)
+    GENERATE_FIELD(all_sectors_written_set1, int)
+    GENERATE_FIELD(all_sectors_written_set0, int)
+    GENERATE_FIELD(busy, int)
+END_REGISTER(TCO_QUAD0_DEBUG0)
+
+START_REGISTER(TCO_QUAD0_DEBUG1)
+    GENERATE_FIELD(fifo_busy, int)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(write_enable, int)
+    GENERATE_FIELD(fifo_write_ptr, int)
+    GENERATE_FIELD(fifo_read_ptr, int)
+    GENERATE_FIELD(cache_read_busy, int)
+    GENERATE_FIELD(latency_fifo_busy, int)
+    GENERATE_FIELD(input_quad_busy, int)
+    GENERATE_FIELD(tco_quad_pipe_busy, int)
+    GENERATE_FIELD(TCB_TCO_rtr_d, int)
+    GENERATE_FIELD(TCB_TCO_xfc_q, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(TCO_TCB_read_xfc, int)
+END_REGISTER(TCO_QUAD0_DEBUG1)
+
+START_REGISTER(SQ_GPR_MANAGEMENT)
+    GENERATE_FIELD(REG_DYNAMIC, int)
+    GENERATE_FIELD(REG_SIZE_PIX, int)
+    GENERATE_FIELD(REG_SIZE_VTX, int)
+END_REGISTER(SQ_GPR_MANAGEMENT)
+
+START_REGISTER(SQ_FLOW_CONTROL)
+    GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ONE_THREAD, int)
+    GENERATE_FIELD(ONE_ALU, int)
+    GENERATE_FIELD(CF_WR_BASE, hex)
+    GENERATE_FIELD(NO_PV_PS, int)
+    GENERATE_FIELD(NO_LOOP_EXIT, int)
+    GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int)
+    GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(VC_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ALU_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(NO_ARB_EJECT, int)
+    GENERATE_FIELD(NO_CFS_EJECT, int)
+    GENERATE_FIELD(POS_EXP_PRIORITY, int)
+    GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int)
+    GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int)
+END_REGISTER(SQ_FLOW_CONTROL)
+
+START_REGISTER(SQ_INST_STORE_MANAGMENT)
+    GENERATE_FIELD(INST_BASE_PIX, int)
+    GENERATE_FIELD(INST_BASE_VTX, int)
+END_REGISTER(SQ_INST_STORE_MANAGMENT)
+
+START_REGISTER(SQ_RESOURCE_MANAGMENT)
+    GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(EXPORT_BUF_ENTRIES, int)
+END_REGISTER(SQ_RESOURCE_MANAGMENT)
+
+START_REGISTER(SQ_EO_RT)
+    GENERATE_FIELD(EO_CONSTANTS_RT, int)
+    GENERATE_FIELD(EO_TSTATE_RT, int)
+END_REGISTER(SQ_EO_RT)
+
+START_REGISTER(SQ_DEBUG_MISC)
+    GENERATE_FIELD(DB_ALUCST_SIZE, int)
+    GENERATE_FIELD(DB_TSTATE_SIZE, int)
+    GENERATE_FIELD(DB_READ_CTX, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DB_READ_MEMORY, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_0, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_1, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_2, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_3, int)
+END_REGISTER(SQ_DEBUG_MISC)
+
+START_REGISTER(SQ_ACTIVITY_METER_CNTL)
+    GENERATE_FIELD(TIMEBASE, int)
+    GENERATE_FIELD(THRESHOLD_LOW, int)
+    GENERATE_FIELD(THRESHOLD_HIGH, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(SQ_ACTIVITY_METER_CNTL)
+
+START_REGISTER(SQ_ACTIVITY_METER_STATUS)
+    GENERATE_FIELD(PERCENT_BUSY, int)
+END_REGISTER(SQ_ACTIVITY_METER_STATUS)
+
+START_REGISTER(SQ_INPUT_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+END_REGISTER(SQ_INPUT_ARB_PRIORITY)
+
+START_REGISTER(SQ_THREAD_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int)
+END_REGISTER(SQ_THREAD_ARB_PRIORITY)
+
+START_REGISTER(SQ_DEBUG_INPUT_FSM)
+    GENERATE_FIELD(VC_VSR_LD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VC_GPR_LD, int)
+    GENERATE_FIELD(PC_PISM, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PC_AS, int)
+    GENERATE_FIELD(PC_INTERP_CNT, int)
+    GENERATE_FIELD(PC_GPR_SIZE, int)
+END_REGISTER(SQ_DEBUG_INPUT_FSM)
+
+START_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+    GENERATE_FIELD(TEX_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(ALU_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(ALU_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(TEX_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int)
+END_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+
+START_REGISTER(SQ_DEBUG_TP_FSM)
+    GENERATE_FIELD(EX_TP, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_TP, int)
+    GENERATE_FIELD(IF_TP, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(TIS_TP, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(GS_TP, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(FCR_TP, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(FCS_TP, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_TP, int)
+END_REGISTER(SQ_DEBUG_TP_FSM)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_0)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_0)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_1)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_1)
+
+START_REGISTER(SQ_DEBUG_EXP_ALLOC)
+    GENERATE_FIELD(POS_BUF_AVAIL, int)
+    GENERATE_FIELD(COLOR_BUF_AVAIL, int)
+    GENERATE_FIELD(EA_BUF_AVAIL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int)
+END_REGISTER(SQ_DEBUG_EXP_ALLOC)
+
+START_REGISTER(SQ_DEBUG_PTR_BUFF)
+    GENERATE_FIELD(END_OF_BUFFER, int)
+    GENERATE_FIELD(DEALLOC_CNT, int)
+    GENERATE_FIELD(QUAL_NEW_VECTOR, int)
+    GENERATE_FIELD(EVENT_CONTEXT_ID, int)
+    GENERATE_FIELD(SC_EVENT_ID, int)
+    GENERATE_FIELD(QUAL_EVENT, int)
+    GENERATE_FIELD(PRIM_TYPE_POLYGON, int)
+    GENERATE_FIELD(EF_EMPTY, int)
+    GENERATE_FIELD(VTX_SYNC_CNT, int)
+END_REGISTER(SQ_DEBUG_PTR_BUFF)
+
+START_REGISTER(SQ_DEBUG_GPR_VTX)
+    GENERATE_FIELD(VTX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VTX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(VTX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(VTX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_VTX)
+
+START_REGISTER(SQ_DEBUG_GPR_PIX)
+    GENERATE_FIELD(PIX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PIX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(PIX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_PIX)
+
+START_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+    GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VC_THREAD_BUF_DLY, int)
+    GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int)
+END_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_0)
+    GENERATE_FIELD(VTX_HEAD_PTR_Q, int)
+    GENERATE_FIELD(TAIL_PTR_Q, int)
+    GENERATE_FIELD(FULL_CNT_Q, int)
+    GENERATE_FIELD(NXT_POS_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PC_ALLOC_CNT, int)
+    GENERATE_FIELD(SX_EVENT_FULL, int)
+    GENERATE_FIELD(BUSY_Q, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_0)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_1)
+    GENERATE_FIELD(VS_DONE_PTR, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_1)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+    GENERATE_FIELD(VS_STATUS_REG, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+    GENERATE_FIELD(VS_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_0)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(TAIL_PTR, int)
+    GENERATE_FIELD(FULL_CNT, int)
+    GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PIX_EXP_CNT, int)
+    GENERATE_FIELD(BUSY, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_0, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_1, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_2, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_3, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+    GENERATE_FIELD(PIX_TB_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+
+START_REGISTER(SQ_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT)
+END_REGISTER(SQ_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER1_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER2_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER3_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_HI)
+
+START_REGISTER(SQ_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_HI)
+
+START_REGISTER(SQ_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_HI)
+
+START_REGISTER(SX_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT)
+END_REGISTER(SX_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SX_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_LOW)
+
+START_REGISTER(SX_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_0)
+    GENERATE_FIELD(VECTOR_RESULT, int)
+    GENERATE_FIELD(CST_0_ABS_MOD, Abs_modifier)
+    GENERATE_FIELD(LOW_PRECISION_16B_FP, int)
+    GENERATE_FIELD(SCALAR_RESULT, int)
+    GENERATE_FIELD(SST_0_ABS_MOD, int)
+    GENERATE_FIELD(EXPORT_DATA, Exporting)
+    GENERATE_FIELD(VECTOR_WRT_MSK, int)
+    GENERATE_FIELD(SCALAR_WRT_MSK, int)
+    GENERATE_FIELD(VECTOR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode)
+END_REGISTER(SQ_INSTRUCTION_ALU_0)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_1)
+    GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier)
+    GENERATE_FIELD(PRED_SELECT, PredicateSelect)
+    GENERATE_FIELD(RELATIVE_ADDR, int)
+    GENERATE_FIELD(CONST_1_REL_ABS, int)
+    GENERATE_FIELD(CONST_0_REL_ABS, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_1)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_2)
+    GENERATE_FIELD(SRC_C_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_C, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier)
+    GENERATE_FIELD(SRC_B_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_B, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier)
+    GENERATE_FIELD(SRC_A_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_A, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier)
+    GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode)
+    GENERATE_FIELD(SRC_C_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_B_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_A_SEL, OperandSelect0)
+END_REGISTER(SQ_INSTRUCTION_ALU_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(PREDICATED_JMP, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_2, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+    GENERATE_FIELD(OPCODE, TexInstOpcode)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, Addressmode)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, Addressmode)
+    GENERATE_FIELD(FETCH_VALID_ONLY, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm)
+    GENERATE_FIELD(SRC_SEL_X, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Y, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Z, SrcSel)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, DstSel)
+    GENERATE_FIELD(DST_SEL_Y, DstSel)
+    GENERATE_FIELD(DST_SEL_Z, DstSel)
+    GENERATE_FIELD(DST_SEL_W, DstSel)
+    GENERATE_FIELD(MAG_FILTER, MagFilter)
+    GENERATE_FIELD(MIN_FILTER, MinFilter)
+    GENERATE_FIELD(MIP_FILTER, MipFilter)
+    GENERATE_FIELD(ANISO_FILTER, AnisoFilter)
+    GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter)
+    GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter)
+    GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter)
+    GENERATE_FIELD(USE_COMP_LOD, int)
+    GENERATE_FIELD(USE_REG_LOD, int)
+    GENERATE_FIELD(PRED_SELECT, PredSelect)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+    GENERATE_FIELD(USE_REG_GRADIENTS, int)
+    GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation)
+    GENERATE_FIELD(LOD_BIAS, int)
+    GENERATE_FIELD(UNUSED, int)
+    GENERATE_FIELD(OFFSET_X, int)
+    GENERATE_FIELD(OFFSET_Y, int)
+    GENERATE_FIELD(OFFSET_Z, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+    GENERATE_FIELD(OPCODE, int)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, int)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, int)
+    GENERATE_FIELD(MUST_BE_ONE, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(CONST_INDEX_SEL, int)
+    GENERATE_FIELD(SRC_SEL, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, int)
+    GENERATE_FIELD(DST_SEL_Y, int)
+    GENERATE_FIELD(DST_SEL_Z, int)
+    GENERATE_FIELD(DST_SEL_W, int)
+    GENERATE_FIELD(FORMAT_COMP_ALL, int)
+    GENERATE_FIELD(NUM_FORMAT_ALL, int)
+    GENERATE_FIELD(SIGNED_RF_MODE_ALL, int)
+    GENERATE_FIELD(DATA_FORMAT, int)
+    GENERATE_FIELD(EXP_ADJUST_ALL, int)
+    GENERATE_FIELD(PRED_SELECT, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+    GENERATE_FIELD(STRIDE, int)
+    GENERATE_FIELD(OFFSET, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+
+START_REGISTER(SQ_CONSTANT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_0)
+
+START_REGISTER(SQ_CONSTANT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_1)
+
+START_REGISTER(SQ_CONSTANT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_2)
+
+START_REGISTER(SQ_CONSTANT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_3)
+
+START_REGISTER(SQ_FETCH_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_0)
+
+START_REGISTER(SQ_FETCH_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_1)
+
+START_REGISTER(SQ_FETCH_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_2)
+
+START_REGISTER(SQ_FETCH_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_3)
+
+START_REGISTER(SQ_FETCH_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_4)
+
+START_REGISTER(SQ_FETCH_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_5)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_0)
+    GENERATE_FIELD(TYPE, int)
+    GENERATE_FIELD(STATE, int)
+    GENERATE_FIELD(BASE_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_0)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_1)
+    GENERATE_FIELD(ENDIAN_SWAP, int)
+    GENERATE_FIELD(LIMIT_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_1)
+
+START_REGISTER(SQ_CONSTANT_T2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T2)
+
+START_REGISTER(SQ_CONSTANT_T3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T3)
+
+START_REGISTER(SQ_CF_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_BOOLEANS)
+
+START_REGISTER(SQ_CF_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_LOOP)
+
+START_REGISTER(SQ_CONSTANT_RT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_RT_0)
+
+START_REGISTER(SQ_CONSTANT_RT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_RT_1)
+
+START_REGISTER(SQ_CONSTANT_RT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_RT_2)
+
+START_REGISTER(SQ_CONSTANT_RT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_0)
+
+START_REGISTER(SQ_FETCH_RT_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_1)
+
+START_REGISTER(SQ_FETCH_RT_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_2)
+
+START_REGISTER(SQ_FETCH_RT_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_4)
+
+START_REGISTER(SQ_FETCH_RT_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_5)
+
+START_REGISTER(SQ_CF_RT_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_RT_BOOLEANS)
+
+START_REGISTER(SQ_CF_RT_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_RT_LOOP)
+
+START_REGISTER(SQ_VS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_PROGRAM)
+
+START_REGISTER(SQ_PS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_PROGRAM)
+
+START_REGISTER(SQ_CF_PROGRAM_SIZE)
+    GENERATE_FIELD(VS_CF_SIZE, int)
+    GENERATE_FIELD(PS_CF_SIZE, int)
+END_REGISTER(SQ_CF_PROGRAM_SIZE)
+
+START_REGISTER(SQ_INTERPOLATOR_CNTL)
+    GENERATE_FIELD(PARAM_SHADE, ParamShade)
+    GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern)
+END_REGISTER(SQ_INTERPOLATOR_CNTL)
+
+START_REGISTER(SQ_PROGRAM_CNTL)
+    GENERATE_FIELD(VS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(PS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(VS_RESOURCE, int)
+    GENERATE_FIELD(PS_RESOURCE, int)
+    GENERATE_FIELD(PARAM_GEN, int)
+    GENERATE_FIELD(GEN_INDEX_PIX, int)
+    GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne)
+    GENERATE_FIELD(VS_EXPORT_MODE, VertexMode)
+    GENERATE_FIELD(PS_EXPORT_MODE, int)
+    GENERATE_FIELD(GEN_INDEX_VTX, int)
+END_REGISTER(SQ_PROGRAM_CNTL)
+
+START_REGISTER(SQ_WRAPPING_0)
+    GENERATE_FIELD(PARAM_WRAP_0, hex)
+    GENERATE_FIELD(PARAM_WRAP_1, hex)
+    GENERATE_FIELD(PARAM_WRAP_2, hex)
+    GENERATE_FIELD(PARAM_WRAP_3, hex)
+    GENERATE_FIELD(PARAM_WRAP_4, hex)
+    GENERATE_FIELD(PARAM_WRAP_5, hex)
+    GENERATE_FIELD(PARAM_WRAP_6, hex)
+    GENERATE_FIELD(PARAM_WRAP_7, hex)
+END_REGISTER(SQ_WRAPPING_0)
+
+START_REGISTER(SQ_WRAPPING_1)
+    GENERATE_FIELD(PARAM_WRAP_8, hex)
+    GENERATE_FIELD(PARAM_WRAP_9, hex)
+    GENERATE_FIELD(PARAM_WRAP_10, hex)
+    GENERATE_FIELD(PARAM_WRAP_11, hex)
+    GENERATE_FIELD(PARAM_WRAP_12, hex)
+    GENERATE_FIELD(PARAM_WRAP_13, hex)
+    GENERATE_FIELD(PARAM_WRAP_14, hex)
+    GENERATE_FIELD(PARAM_WRAP_15, hex)
+END_REGISTER(SQ_WRAPPING_1)
+
+START_REGISTER(SQ_VS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_CONST)
+
+START_REGISTER(SQ_PS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_CONST)
+
+START_REGISTER(SQ_CONTEXT_MISC)
+    GENERATE_FIELD(INST_PRED_OPTIMIZE, int)
+    GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int)
+    GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl)
+    GENERATE_FIELD(PARAM_GEN_POS, int)
+    GENERATE_FIELD(PERFCOUNTER_REF, int)
+    GENERATE_FIELD(YEILD_OPTIMIZE, int)
+    GENERATE_FIELD(TX_CACHE_SEL, int)
+END_REGISTER(SQ_CONTEXT_MISC)
+
+START_REGISTER(SQ_CF_RD_BASE)
+    GENERATE_FIELD(RD_BASE, hex)
+END_REGISTER(SQ_CF_RD_BASE)
+
+START_REGISTER(SQ_DEBUG_MISC_0)
+    GENERATE_FIELD(DB_PROB_ON, int)
+    GENERATE_FIELD(DB_PROB_BREAK, int)
+    GENERATE_FIELD(DB_PROB_ADDR, int)
+    GENERATE_FIELD(DB_PROB_COUNT, int)
+END_REGISTER(SQ_DEBUG_MISC_0)
+
+START_REGISTER(SQ_DEBUG_MISC_1)
+    GENERATE_FIELD(DB_ON_PIX, int)
+    GENERATE_FIELD(DB_ON_VTX, int)
+    GENERATE_FIELD(DB_INST_COUNT, int)
+    GENERATE_FIELD(DB_BREAK_ADDR, int)
+END_REGISTER(SQ_DEBUG_MISC_1)
+
+START_REGISTER(MH_ARBITER_CONFIG)
+    GENERATE_FIELD(SAME_PAGE_LIMIT, int)
+    GENERATE_FIELD(SAME_PAGE_GRANULARITY, int)
+    GENERATE_FIELD(L1_ARB_ENABLE, bool)
+    GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int)
+    GENERATE_FIELD(L2_ARB_CONTROL, int)
+    GENERATE_FIELD(PAGE_SIZE, int)
+    GENERATE_FIELD(TC_REORDER_ENABLE, bool)
+    GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT, int)
+    GENERATE_FIELD(CP_CLNT_ENABLE, bool)
+    GENERATE_FIELD(VGT_CLNT_ENABLE, bool)
+    GENERATE_FIELD(TC_CLNT_ENABLE, bool)
+    GENERATE_FIELD(RB_CLNT_ENABLE, bool)
+END_REGISTER(MH_ARBITER_CONFIG)
+
+START_REGISTER(MH_CLNT_AXI_ID_REUSE)
+    GENERATE_FIELD(CPw_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RBw_ID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(MMUr_ID, int)
+END_REGISTER(MH_CLNT_AXI_ID_REUSE)
+
+START_REGISTER(MH_INTERRUPT_MASK)
+    GENERATE_FIELD(AXI_READ_ERROR, bool)
+    GENERATE_FIELD(AXI_WRITE_ERROR, bool)
+    GENERATE_FIELD(MMU_PAGE_FAULT, bool)
+END_REGISTER(MH_INTERRUPT_MASK)
+
+START_REGISTER(MH_INTERRUPT_STATUS)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_STATUS)
+
+START_REGISTER(MH_INTERRUPT_CLEAR)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_CLEAR)
+
+START_REGISTER(MH_AXI_ERROR)
+    GENERATE_FIELD(AXI_READ_ID, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ID, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+END_REGISTER(MH_AXI_ERROR)
+
+START_REGISTER(MH_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER0_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER1_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER0_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER0_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER1_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER1_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER0_LOW)
+
+START_REGISTER(MH_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER1_LOW)
+
+START_REGISTER(MH_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER0_HI)
+
+START_REGISTER(MH_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER1_HI)
+
+START_REGISTER(MH_DEBUG_CTRL)
+    GENERATE_FIELD(INDEX, int)
+END_REGISTER(MH_DEBUG_CTRL)
+
+START_REGISTER(MH_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(MH_DEBUG_DATA)
+
+START_REGISTER(MH_MMU_CONFIG)
+    GENERATE_FIELD(MMU_ENABLE, bool)
+    GENERATE_FIELD(SPLIT_MODE_ENABLE, bool)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh)
+END_REGISTER(MH_MMU_CONFIG)
+
+START_REGISTER(MH_MMU_VA_RANGE)
+    GENERATE_FIELD(NUM_64KB_REGIONS, int)
+    GENERATE_FIELD(VA_BASE, int)
+END_REGISTER(MH_MMU_VA_RANGE)
+
+START_REGISTER(MH_MMU_PT_BASE)
+    GENERATE_FIELD(PT_BASE, int)
+END_REGISTER(MH_MMU_PT_BASE)
+
+START_REGISTER(MH_MMU_PAGE_FAULT)
+    GENERATE_FIELD(PAGE_FAULT, int)
+    GENERATE_FIELD(OP_TYPE, int)
+    GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(AXI_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(READ_PROTECTION_ERROR, int)
+    GENERATE_FIELD(WRITE_PROTECTION_ERROR, int)
+    GENERATE_FIELD(REQ_VA, int)
+END_REGISTER(MH_MMU_PAGE_FAULT)
+
+START_REGISTER(MH_MMU_TRAN_ERROR)
+    GENERATE_FIELD(TRAN_ERROR, int)
+END_REGISTER(MH_MMU_TRAN_ERROR)
+
+START_REGISTER(MH_MMU_INVALIDATE)
+    GENERATE_FIELD(INVALIDATE_ALL, int)
+    GENERATE_FIELD(INVALIDATE_TC, int)
+END_REGISTER(MH_MMU_INVALIDATE)
+
+START_REGISTER(MH_MMU_MPU_BASE)
+    GENERATE_FIELD(MPU_BASE, int)
+END_REGISTER(MH_MMU_MPU_BASE)
+
+START_REGISTER(MH_MMU_MPU_END)
+    GENERATE_FIELD(MPU_END, int)
+END_REGISTER(MH_MMU_MPU_END)
+
+START_REGISTER(WAIT_UNTIL)
+    GENERATE_FIELD(WAIT_RE_VSYNC, int)
+    GENERATE_FIELD(WAIT_FE_VSYNC, int)
+    GENERATE_FIELD(WAIT_VSYNC, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID0, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID1, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID2, int)
+    GENERATE_FIELD(WAIT_CMDFIFO, int)
+    GENERATE_FIELD(WAIT_2D_IDLE, int)
+    GENERATE_FIELD(WAIT_3D_IDLE, int)
+    GENERATE_FIELD(WAIT_2D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_3D_IDLECLEAN, int)
+    GENERATE_FIELD(CMDFIFO_ENTRIES, int)
+END_REGISTER(WAIT_UNTIL)
+
+START_REGISTER(RBBM_ISYNC_CNTL)
+    GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int)
+    GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int)
+END_REGISTER(RBBM_ISYNC_CNTL)
+
+START_REGISTER(RBBM_STATUS)
+    GENERATE_FIELD(CMDFIFO_AVAIL, int)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(HIRQ_PENDING, int)
+    GENERATE_FIELD(CPRQ_PENDING, int)
+    GENERATE_FIELD(CFRQ_PENDING, int)
+    GENERATE_FIELD(PFRQ_PENDING, int)
+    GENERATE_FIELD(VGT_BUSY_NO_DMA, int)
+    GENERATE_FIELD(RBBM_WU_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(MH_BUSY, int)
+    GENERATE_FIELD(MH_COHERENCY_BUSY, int)
+    GENERATE_FIELD(SX_BUSY, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(SC_CNTX_BUSY, int)
+    GENERATE_FIELD(PA_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX17_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX0_BUSY, int)
+    GENERATE_FIELD(RB_CNTX_BUSY, int)
+    GENERATE_FIELD(GUI_ACTIVE, int)
+END_REGISTER(RBBM_STATUS)
+
+START_REGISTER(RBBM_DSPLY)
+    GENERATE_FIELD(DISPLAY_ID0_ACTIVE, int)
+    GENERATE_FIELD(DISPLAY_ID1_ACTIVE, int)
+    GENERATE_FIELD(DISPLAY_ID2_ACTIVE, int)
+    GENERATE_FIELD(VSYNC_ACTIVE, int)
+    GENERATE_FIELD(USE_DISPLAY_ID0, int)
+    GENERATE_FIELD(USE_DISPLAY_ID1, int)
+    GENERATE_FIELD(USE_DISPLAY_ID2, int)
+    GENERATE_FIELD(SW_CNTL, int)
+    GENERATE_FIELD(NUM_BUFS, int)
+END_REGISTER(RBBM_DSPLY)
+
+START_REGISTER(RBBM_RENDER_LATEST)
+    GENERATE_FIELD(BUFFER_ID, int)
+END_REGISTER(RBBM_RENDER_LATEST)
+
+START_REGISTER(RBBM_RTL_RELEASE)
+    GENERATE_FIELD(CHANGELIST, int)
+END_REGISTER(RBBM_RTL_RELEASE)
+
+START_REGISTER(RBBM_PATCH_RELEASE)
+    GENERATE_FIELD(PATCH_REVISION, int)
+    GENERATE_FIELD(PATCH_SELECTION, int)
+    GENERATE_FIELD(CUSTOMER_ID, int)
+END_REGISTER(RBBM_PATCH_RELEASE)
+
+START_REGISTER(RBBM_AUXILIARY_CONFIG)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(RBBM_AUXILIARY_CONFIG)
+
+START_REGISTER(RBBM_PERIPHID0)
+    GENERATE_FIELD(PARTNUMBER0, int)
+END_REGISTER(RBBM_PERIPHID0)
+
+START_REGISTER(RBBM_PERIPHID1)
+    GENERATE_FIELD(PARTNUMBER1, int)
+    GENERATE_FIELD(DESIGNER0, int)
+END_REGISTER(RBBM_PERIPHID1)
+
+START_REGISTER(RBBM_PERIPHID2)
+    GENERATE_FIELD(DESIGNER1, int)
+    GENERATE_FIELD(REVISION, int)
+END_REGISTER(RBBM_PERIPHID2)
+
+START_REGISTER(RBBM_PERIPHID3)
+    GENERATE_FIELD(RBBM_HOST_INTERFACE, int)
+    GENERATE_FIELD(GARB_SLAVE_INTERFACE, int)
+    GENERATE_FIELD(MH_INTERFACE, int)
+    GENERATE_FIELD(CONTINUATION, int)
+END_REGISTER(RBBM_PERIPHID3)
+
+START_REGISTER(RBBM_CNTL)
+    GENERATE_FIELD(READ_TIMEOUT, int)
+    GENERATE_FIELD(REGCLK_DEASSERT_TIME, int)
+END_REGISTER(RBBM_CNTL)
+
+START_REGISTER(RBBM_SKEW_CNTL)
+    GENERATE_FIELD(SKEW_TOP_THRESHOLD, int)
+    GENERATE_FIELD(SKEW_COUNT, int)
+END_REGISTER(RBBM_SKEW_CNTL)
+
+START_REGISTER(RBBM_SOFT_RESET)
+    GENERATE_FIELD(SOFT_RESET_CP, int)
+    GENERATE_FIELD(SOFT_RESET_PA, int)
+    GENERATE_FIELD(SOFT_RESET_MH, int)
+    GENERATE_FIELD(SOFT_RESET_BC, int)
+    GENERATE_FIELD(SOFT_RESET_SQ, int)
+    GENERATE_FIELD(SOFT_RESET_SX, int)
+    GENERATE_FIELD(SOFT_RESET_CIB, int)
+    GENERATE_FIELD(SOFT_RESET_SC, int)
+    GENERATE_FIELD(SOFT_RESET_VGT, int)
+END_REGISTER(RBBM_SOFT_RESET)
+
+START_REGISTER(RBBM_PM_OVERRIDE1)
+    GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE1)
+
+START_REGISTER(RBBM_PM_OVERRIDE2)
+    GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE2)
+
+START_REGISTER(GC_SYS_IDLE)
+    GENERATE_FIELD(GC_SYS_IDLE_DELAY, int)
+    GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int)
+END_REGISTER(GC_SYS_IDLE)
+
+START_REGISTER(NQWAIT_UNTIL)
+    GENERATE_FIELD(WAIT_GUI_IDLE, int)
+END_REGISTER(NQWAIT_UNTIL)
+
+START_REGISTER(RBBM_DEBUG)
+    GENERATE_FIELD(IGNORE_RTR, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_WU, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int)
+    GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int)
+    GENERATE_FIELD(IGNORE_RTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(CP_RBBM_NRTRTR, int)
+    GENERATE_FIELD(VGT_RBBM_NRTRTR, int)
+    GENERATE_FIELD(SQ_RBBM_NRTRTR, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int)
+    GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int)
+END_REGISTER(RBBM_DEBUG)
+
+START_REGISTER(RBBM_READ_ERROR)
+    GENERATE_FIELD(READ_ADDRESS, int)
+    GENERATE_FIELD(READ_REQUESTER, int)
+    GENERATE_FIELD(READ_ERROR, int)
+END_REGISTER(RBBM_READ_ERROR)
+
+START_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+    GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int)
+END_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+
+START_REGISTER(RBBM_INT_CNTL)
+    GENERATE_FIELD(RDERR_INT_MASK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_MASK, int)
+END_REGISTER(RBBM_INT_CNTL)
+
+START_REGISTER(RBBM_INT_STATUS)
+    GENERATE_FIELD(RDERR_INT_STAT, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int)
+    GENERATE_FIELD(GUI_IDLE_INT_STAT, int)
+END_REGISTER(RBBM_INT_STATUS)
+
+START_REGISTER(RBBM_INT_ACK)
+    GENERATE_FIELD(RDERR_INT_ACK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_ACK, int)
+END_REGISTER(RBBM_INT_ACK)
+
+START_REGISTER(MASTER_INT_SIGNAL)
+    GENERATE_FIELD(MH_INT_STAT, int)
+    GENERATE_FIELD(CP_INT_STAT, int)
+    GENERATE_FIELD(RBBM_INT_STAT, int)
+END_REGISTER(MASTER_INT_SIGNAL)
+
+START_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL)
+END_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(RBBM_PERFCOUNTER1_LO)
+    GENERATE_FIELD(PERF_COUNT1_LO, int)
+END_REGISTER(RBBM_PERFCOUNTER1_LO)
+
+START_REGISTER(RBBM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT1_HI, int)
+END_REGISTER(RBBM_PERFCOUNTER1_HI)
+
+START_REGISTER(CP_RB_BASE)
+    GENERATE_FIELD(RB_BASE, int)
+END_REGISTER(CP_RB_BASE)
+
+START_REGISTER(CP_RB_CNTL)
+    GENERATE_FIELD(RB_BUFSZ, int)
+    GENERATE_FIELD(RB_BLKSZ, int)
+    GENERATE_FIELD(BUF_SWAP, int)
+    GENERATE_FIELD(RB_POLL_EN, int)
+    GENERATE_FIELD(RB_NO_UPDATE, int)
+    GENERATE_FIELD(RB_RPTR_WR_ENA, int)
+END_REGISTER(CP_RB_CNTL)
+
+START_REGISTER(CP_RB_RPTR_ADDR)
+    GENERATE_FIELD(RB_RPTR_SWAP, int)
+    GENERATE_FIELD(RB_RPTR_ADDR, int)
+END_REGISTER(CP_RB_RPTR_ADDR)
+
+START_REGISTER(CP_RB_RPTR)
+    GENERATE_FIELD(RB_RPTR, int)
+END_REGISTER(CP_RB_RPTR)
+
+START_REGISTER(CP_RB_RPTR_WR)
+    GENERATE_FIELD(RB_RPTR_WR, int)
+END_REGISTER(CP_RB_RPTR_WR)
+
+START_REGISTER(CP_RB_WPTR)
+    GENERATE_FIELD(RB_WPTR, int)
+END_REGISTER(CP_RB_WPTR)
+
+START_REGISTER(CP_RB_WPTR_DELAY)
+    GENERATE_FIELD(PRE_WRITE_TIMER, int)
+    GENERATE_FIELD(PRE_WRITE_LIMIT, int)
+END_REGISTER(CP_RB_WPTR_DELAY)
+
+START_REGISTER(CP_RB_WPTR_BASE)
+    GENERATE_FIELD(RB_WPTR_SWAP, int)
+    GENERATE_FIELD(RB_WPTR_BASE, int)
+END_REGISTER(CP_RB_WPTR_BASE)
+
+START_REGISTER(CP_IB1_BASE)
+    GENERATE_FIELD(IB1_BASE, int)
+END_REGISTER(CP_IB1_BASE)
+
+START_REGISTER(CP_IB1_BUFSZ)
+    GENERATE_FIELD(IB1_BUFSZ, int)
+END_REGISTER(CP_IB1_BUFSZ)
+
+START_REGISTER(CP_IB2_BASE)
+    GENERATE_FIELD(IB2_BASE, int)
+END_REGISTER(CP_IB2_BASE)
+
+START_REGISTER(CP_IB2_BUFSZ)
+    GENERATE_FIELD(IB2_BUFSZ, int)
+END_REGISTER(CP_IB2_BUFSZ)
+
+START_REGISTER(CP_ST_BASE)
+    GENERATE_FIELD(ST_BASE, int)
+END_REGISTER(CP_ST_BASE)
+
+START_REGISTER(CP_ST_BUFSZ)
+    GENERATE_FIELD(ST_BUFSZ, int)
+END_REGISTER(CP_ST_BUFSZ)
+
+START_REGISTER(CP_QUEUE_THRESHOLDS)
+    GENERATE_FIELD(CSQ_IB1_START, int)
+    GENERATE_FIELD(CSQ_IB2_START, int)
+    GENERATE_FIELD(CSQ_ST_START, int)
+END_REGISTER(CP_QUEUE_THRESHOLDS)
+
+START_REGISTER(CP_MEQ_THRESHOLDS)
+    GENERATE_FIELD(MEQ_END, int)
+    GENERATE_FIELD(ROQ_END, int)
+END_REGISTER(CP_MEQ_THRESHOLDS)
+
+START_REGISTER(CP_CSQ_AVAIL)
+    GENERATE_FIELD(CSQ_CNT_RING, int)
+    GENERATE_FIELD(CSQ_CNT_IB1, int)
+    GENERATE_FIELD(CSQ_CNT_IB2, int)
+END_REGISTER(CP_CSQ_AVAIL)
+
+START_REGISTER(CP_STQ_AVAIL)
+    GENERATE_FIELD(STQ_CNT_ST, int)
+END_REGISTER(CP_STQ_AVAIL)
+
+START_REGISTER(CP_MEQ_AVAIL)
+    GENERATE_FIELD(MEQ_CNT, int)
+END_REGISTER(CP_MEQ_AVAIL)
+
+START_REGISTER(CP_CSQ_RB_STAT)
+    GENERATE_FIELD(CSQ_RPTR_PRIMARY, int)
+    GENERATE_FIELD(CSQ_WPTR_PRIMARY, int)
+END_REGISTER(CP_CSQ_RB_STAT)
+
+START_REGISTER(CP_CSQ_IB1_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int)
+END_REGISTER(CP_CSQ_IB1_STAT)
+
+START_REGISTER(CP_CSQ_IB2_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int)
+END_REGISTER(CP_CSQ_IB2_STAT)
+
+START_REGISTER(CP_NON_PREFETCH_CNTRS)
+    GENERATE_FIELD(IB1_COUNTER, int)
+    GENERATE_FIELD(IB2_COUNTER, int)
+END_REGISTER(CP_NON_PREFETCH_CNTRS)
+
+START_REGISTER(CP_STQ_ST_STAT)
+    GENERATE_FIELD(STQ_RPTR_ST, int)
+    GENERATE_FIELD(STQ_WPTR_ST, int)
+END_REGISTER(CP_STQ_ST_STAT)
+
+START_REGISTER(CP_MEQ_STAT)
+    GENERATE_FIELD(MEQ_RPTR, int)
+    GENERATE_FIELD(MEQ_WPTR, int)
+END_REGISTER(CP_MEQ_STAT)
+
+START_REGISTER(CP_MIU_TAG_STAT)
+    GENERATE_FIELD(TAG_0_STAT, int)
+    GENERATE_FIELD(TAG_1_STAT, int)
+    GENERATE_FIELD(TAG_2_STAT, int)
+    GENERATE_FIELD(TAG_3_STAT, int)
+    GENERATE_FIELD(TAG_4_STAT, int)
+    GENERATE_FIELD(TAG_5_STAT, int)
+    GENERATE_FIELD(TAG_6_STAT, int)
+    GENERATE_FIELD(TAG_7_STAT, int)
+    GENERATE_FIELD(TAG_8_STAT, int)
+    GENERATE_FIELD(TAG_9_STAT, int)
+    GENERATE_FIELD(TAG_10_STAT, int)
+    GENERATE_FIELD(TAG_11_STAT, int)
+    GENERATE_FIELD(TAG_12_STAT, int)
+    GENERATE_FIELD(TAG_13_STAT, int)
+    GENERATE_FIELD(TAG_14_STAT, int)
+    GENERATE_FIELD(TAG_15_STAT, int)
+    GENERATE_FIELD(TAG_16_STAT, int)
+    GENERATE_FIELD(TAG_17_STAT, int)
+    GENERATE_FIELD(INVALID_RETURN_TAG, int)
+END_REGISTER(CP_MIU_TAG_STAT)
+
+START_REGISTER(CP_CMD_INDEX)
+    GENERATE_FIELD(CMD_INDEX, int)
+    GENERATE_FIELD(CMD_QUEUE_SEL, int)
+END_REGISTER(CP_CMD_INDEX)
+
+START_REGISTER(CP_CMD_DATA)
+    GENERATE_FIELD(CMD_DATA, int)
+END_REGISTER(CP_CMD_DATA)
+
+START_REGISTER(CP_ME_CNTL)
+    GENERATE_FIELD(ME_STATMUX, int)
+    GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_HALT, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(PROG_CNT_SIZE, int)
+END_REGISTER(CP_ME_CNTL)
+
+START_REGISTER(CP_ME_STATUS)
+    GENERATE_FIELD(ME_DEBUG_DATA, int)
+END_REGISTER(CP_ME_STATUS)
+
+START_REGISTER(CP_ME_RAM_WADDR)
+    GENERATE_FIELD(ME_RAM_WADDR, int)
+END_REGISTER(CP_ME_RAM_WADDR)
+
+START_REGISTER(CP_ME_RAM_RADDR)
+    GENERATE_FIELD(ME_RAM_RADDR, int)
+END_REGISTER(CP_ME_RAM_RADDR)
+
+START_REGISTER(CP_ME_RAM_DATA)
+    GENERATE_FIELD(ME_RAM_DATA, int)
+END_REGISTER(CP_ME_RAM_DATA)
+
+START_REGISTER(CP_ME_RDADDR)
+    GENERATE_FIELD(ME_RDADDR, int)
+END_REGISTER(CP_ME_RDADDR)
+
+START_REGISTER(CP_DEBUG)
+    GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int)
+    GENERATE_FIELD(PREDICATE_DISABLE, int)
+    GENERATE_FIELD(PROG_END_PTR_ENABLE, int)
+    GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int)
+    GENERATE_FIELD(PREFETCH_PASS_NOPS, int)
+    GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int)
+    GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int)
+    GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int)
+    GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int)
+END_REGISTER(CP_DEBUG)
+
+START_REGISTER(SCRATCH_REG0)
+    GENERATE_FIELD(SCRATCH_REG0, int)
+END_REGISTER(SCRATCH_REG0)
+
+START_REGISTER(SCRATCH_REG1)
+    GENERATE_FIELD(SCRATCH_REG1, int)
+END_REGISTER(SCRATCH_REG1)
+
+START_REGISTER(SCRATCH_REG2)
+    GENERATE_FIELD(SCRATCH_REG2, int)
+END_REGISTER(SCRATCH_REG2)
+
+START_REGISTER(SCRATCH_REG3)
+    GENERATE_FIELD(SCRATCH_REG3, int)
+END_REGISTER(SCRATCH_REG3)
+
+START_REGISTER(SCRATCH_REG4)
+    GENERATE_FIELD(SCRATCH_REG4, int)
+END_REGISTER(SCRATCH_REG4)
+
+START_REGISTER(SCRATCH_REG5)
+    GENERATE_FIELD(SCRATCH_REG5, int)
+END_REGISTER(SCRATCH_REG5)
+
+START_REGISTER(SCRATCH_REG6)
+    GENERATE_FIELD(SCRATCH_REG6, int)
+END_REGISTER(SCRATCH_REG6)
+
+START_REGISTER(SCRATCH_REG7)
+    GENERATE_FIELD(SCRATCH_REG7, int)
+END_REGISTER(SCRATCH_REG7)
+
+START_REGISTER(SCRATCH_UMSK)
+    GENERATE_FIELD(SCRATCH_UMSK, int)
+    GENERATE_FIELD(SCRATCH_SWAP, int)
+END_REGISTER(SCRATCH_UMSK)
+
+START_REGISTER(SCRATCH_ADDR)
+    GENERATE_FIELD(SCRATCH_ADDR, hex)
+END_REGISTER(SCRATCH_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_SRC)
+    GENERATE_FIELD(VS_DONE_SWM, int)
+    GENERATE_FIELD(VS_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_EVENT_SRC)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR)
+    GENERATE_FIELD(VS_DONE_SWAP, int)
+    GENERATE_FIELD(VS_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA)
+    GENERATE_FIELD(VS_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(VS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(VS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+    GENERATE_FIELD(VS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_SRC)
+    GENERATE_FIELD(PS_DONE_SWM, int)
+    GENERATE_FIELD(PS_DONE_CNTR, int)
+END_REGISTER(CP_ME_PS_EVENT_SRC)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR)
+    GENERATE_FIELD(PS_DONE_SWAP, int)
+    GENERATE_FIELD(PS_DONE_ADDR, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA)
+    GENERATE_FIELD(PS_DONE_DATA, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(PS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(PS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+    GENERATE_FIELD(PS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_CF_EVENT_SRC)
+    GENERATE_FIELD(CF_DONE_SRC, int)
+END_REGISTER(CP_ME_CF_EVENT_SRC)
+
+START_REGISTER(CP_ME_CF_EVENT_ADDR)
+    GENERATE_FIELD(CF_DONE_SWAP, int)
+    GENERATE_FIELD(CF_DONE_ADDR, int)
+END_REGISTER(CP_ME_CF_EVENT_ADDR)
+
+START_REGISTER(CP_ME_CF_EVENT_DATA)
+    GENERATE_FIELD(CF_DONE_DATA, int)
+END_REGISTER(CP_ME_CF_EVENT_DATA)
+
+START_REGISTER(CP_ME_NRT_ADDR)
+    GENERATE_FIELD(NRT_WRITE_SWAP, int)
+    GENERATE_FIELD(NRT_WRITE_ADDR, int)
+END_REGISTER(CP_ME_NRT_ADDR)
+
+START_REGISTER(CP_ME_NRT_DATA)
+    GENERATE_FIELD(NRT_WRITE_DATA, int)
+END_REGISTER(CP_ME_NRT_DATA)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+    GENERATE_FIELD(VS_FETCH_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+    GENERATE_FIELD(VS_FETCH_DONE_SWAP, int)
+    GENERATE_FIELD(VS_FETCH_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+    GENERATE_FIELD(VS_FETCH_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+
+START_REGISTER(CP_INT_CNTL)
+    GENERATE_FIELD(SW_INT_MASK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int)
+    GENERATE_FIELD(OPCODE_ERROR_MASK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int)
+    GENERATE_FIELD(IB_ERROR_MASK, int)
+    GENERATE_FIELD(IB2_INT_MASK, int)
+    GENERATE_FIELD(IB1_INT_MASK, int)
+    GENERATE_FIELD(RB_INT_MASK, int)
+END_REGISTER(CP_INT_CNTL)
+
+START_REGISTER(CP_INT_STATUS)
+    GENERATE_FIELD(SW_INT_STAT, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int)
+    GENERATE_FIELD(OPCODE_ERROR_STAT, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int)
+    GENERATE_FIELD(IB_ERROR_STAT, int)
+    GENERATE_FIELD(IB2_INT_STAT, int)
+    GENERATE_FIELD(IB1_INT_STAT, int)
+    GENERATE_FIELD(RB_INT_STAT, int)
+END_REGISTER(CP_INT_STATUS)
+
+START_REGISTER(CP_INT_ACK)
+    GENERATE_FIELD(SW_INT_ACK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int)
+    GENERATE_FIELD(OPCODE_ERROR_ACK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int)
+    GENERATE_FIELD(IB_ERROR_ACK, int)
+    GENERATE_FIELD(IB2_INT_ACK, int)
+    GENERATE_FIELD(IB1_INT_ACK, int)
+    GENERATE_FIELD(RB_INT_ACK, int)
+END_REGISTER(CP_INT_ACK)
+
+START_REGISTER(CP_PFP_UCODE_ADDR)
+    GENERATE_FIELD(UCODE_ADDR, hex)
+END_REGISTER(CP_PFP_UCODE_ADDR)
+
+START_REGISTER(CP_PFP_UCODE_DATA)
+    GENERATE_FIELD(UCODE_DATA, hex)
+END_REGISTER(CP_PFP_UCODE_DATA)
+
+START_REGISTER(CP_PERFMON_CNTL)
+    GENERATE_FIELD(PERFMON_STATE, int)
+    GENERATE_FIELD(PERFMON_ENABLE_MODE, int)
+END_REGISTER(CP_PERFMON_CNTL)
+
+START_REGISTER(CP_PERFCOUNTER_SELECT)
+    GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL)
+END_REGISTER(CP_PERFCOUNTER_SELECT)
+
+START_REGISTER(CP_PERFCOUNTER_LO)
+    GENERATE_FIELD(PERFCOUNT_LO, int)
+END_REGISTER(CP_PERFCOUNTER_LO)
+
+START_REGISTER(CP_PERFCOUNTER_HI)
+    GENERATE_FIELD(PERFCOUNT_HI, int)
+END_REGISTER(CP_PERFCOUNTER_HI)
+
+START_REGISTER(CP_BIN_MASK_LO)
+    GENERATE_FIELD(BIN_MASK_LO, int)
+END_REGISTER(CP_BIN_MASK_LO)
+
+START_REGISTER(CP_BIN_MASK_HI)
+    GENERATE_FIELD(BIN_MASK_HI, int)
+END_REGISTER(CP_BIN_MASK_HI)
+
+START_REGISTER(CP_BIN_SELECT_LO)
+    GENERATE_FIELD(BIN_SELECT_LO, int)
+END_REGISTER(CP_BIN_SELECT_LO)
+
+START_REGISTER(CP_BIN_SELECT_HI)
+    GENERATE_FIELD(BIN_SELECT_HI, int)
+END_REGISTER(CP_BIN_SELECT_HI)
+
+START_REGISTER(CP_NV_FLAGS_0)
+    GENERATE_FIELD(DISCARD_0, int)
+    GENERATE_FIELD(END_RCVD_0, int)
+    GENERATE_FIELD(DISCARD_1, int)
+    GENERATE_FIELD(END_RCVD_1, int)
+    GENERATE_FIELD(DISCARD_2, int)
+    GENERATE_FIELD(END_RCVD_2, int)
+    GENERATE_FIELD(DISCARD_3, int)
+    GENERATE_FIELD(END_RCVD_3, int)
+    GENERATE_FIELD(DISCARD_4, int)
+    GENERATE_FIELD(END_RCVD_4, int)
+    GENERATE_FIELD(DISCARD_5, int)
+    GENERATE_FIELD(END_RCVD_5, int)
+    GENERATE_FIELD(DISCARD_6, int)
+    GENERATE_FIELD(END_RCVD_6, int)
+    GENERATE_FIELD(DISCARD_7, int)
+    GENERATE_FIELD(END_RCVD_7, int)
+    GENERATE_FIELD(DISCARD_8, int)
+    GENERATE_FIELD(END_RCVD_8, int)
+    GENERATE_FIELD(DISCARD_9, int)
+    GENERATE_FIELD(END_RCVD_9, int)
+    GENERATE_FIELD(DISCARD_10, int)
+    GENERATE_FIELD(END_RCVD_10, int)
+    GENERATE_FIELD(DISCARD_11, int)
+    GENERATE_FIELD(END_RCVD_11, int)
+    GENERATE_FIELD(DISCARD_12, int)
+    GENERATE_FIELD(END_RCVD_12, int)
+    GENERATE_FIELD(DISCARD_13, int)
+    GENERATE_FIELD(END_RCVD_13, int)
+    GENERATE_FIELD(DISCARD_14, int)
+    GENERATE_FIELD(END_RCVD_14, int)
+    GENERATE_FIELD(DISCARD_15, int)
+    GENERATE_FIELD(END_RCVD_15, int)
+END_REGISTER(CP_NV_FLAGS_0)
+
+START_REGISTER(CP_NV_FLAGS_1)
+    GENERATE_FIELD(DISCARD_16, int)
+    GENERATE_FIELD(END_RCVD_16, int)
+    GENERATE_FIELD(DISCARD_17, int)
+    GENERATE_FIELD(END_RCVD_17, int)
+    GENERATE_FIELD(DISCARD_18, int)
+    GENERATE_FIELD(END_RCVD_18, int)
+    GENERATE_FIELD(DISCARD_19, int)
+    GENERATE_FIELD(END_RCVD_19, int)
+    GENERATE_FIELD(DISCARD_20, int)
+    GENERATE_FIELD(END_RCVD_20, int)
+    GENERATE_FIELD(DISCARD_21, int)
+    GENERATE_FIELD(END_RCVD_21, int)
+    GENERATE_FIELD(DISCARD_22, int)
+    GENERATE_FIELD(END_RCVD_22, int)
+    GENERATE_FIELD(DISCARD_23, int)
+    GENERATE_FIELD(END_RCVD_23, int)
+    GENERATE_FIELD(DISCARD_24, int)
+    GENERATE_FIELD(END_RCVD_24, int)
+    GENERATE_FIELD(DISCARD_25, int)
+    GENERATE_FIELD(END_RCVD_25, int)
+    GENERATE_FIELD(DISCARD_26, int)
+    GENERATE_FIELD(END_RCVD_26, int)
+    GENERATE_FIELD(DISCARD_27, int)
+    GENERATE_FIELD(END_RCVD_27, int)
+    GENERATE_FIELD(DISCARD_28, int)
+    GENERATE_FIELD(END_RCVD_28, int)
+    GENERATE_FIELD(DISCARD_29, int)
+    GENERATE_FIELD(END_RCVD_29, int)
+    GENERATE_FIELD(DISCARD_30, int)
+    GENERATE_FIELD(END_RCVD_30, int)
+    GENERATE_FIELD(DISCARD_31, int)
+    GENERATE_FIELD(END_RCVD_31, int)
+END_REGISTER(CP_NV_FLAGS_1)
+
+START_REGISTER(CP_NV_FLAGS_2)
+    GENERATE_FIELD(DISCARD_32, int)
+    GENERATE_FIELD(END_RCVD_32, int)
+    GENERATE_FIELD(DISCARD_33, int)
+    GENERATE_FIELD(END_RCVD_33, int)
+    GENERATE_FIELD(DISCARD_34, int)
+    GENERATE_FIELD(END_RCVD_34, int)
+    GENERATE_FIELD(DISCARD_35, int)
+    GENERATE_FIELD(END_RCVD_35, int)
+    GENERATE_FIELD(DISCARD_36, int)
+    GENERATE_FIELD(END_RCVD_36, int)
+    GENERATE_FIELD(DISCARD_37, int)
+    GENERATE_FIELD(END_RCVD_37, int)
+    GENERATE_FIELD(DISCARD_38, int)
+    GENERATE_FIELD(END_RCVD_38, int)
+    GENERATE_FIELD(DISCARD_39, int)
+    GENERATE_FIELD(END_RCVD_39, int)
+    GENERATE_FIELD(DISCARD_40, int)
+    GENERATE_FIELD(END_RCVD_40, int)
+    GENERATE_FIELD(DISCARD_41, int)
+    GENERATE_FIELD(END_RCVD_41, int)
+    GENERATE_FIELD(DISCARD_42, int)
+    GENERATE_FIELD(END_RCVD_42, int)
+    GENERATE_FIELD(DISCARD_43, int)
+    GENERATE_FIELD(END_RCVD_43, int)
+    GENERATE_FIELD(DISCARD_44, int)
+    GENERATE_FIELD(END_RCVD_44, int)
+    GENERATE_FIELD(DISCARD_45, int)
+    GENERATE_FIELD(END_RCVD_45, int)
+    GENERATE_FIELD(DISCARD_46, int)
+    GENERATE_FIELD(END_RCVD_46, int)
+    GENERATE_FIELD(DISCARD_47, int)
+    GENERATE_FIELD(END_RCVD_47, int)
+END_REGISTER(CP_NV_FLAGS_2)
+
+START_REGISTER(CP_NV_FLAGS_3)
+    GENERATE_FIELD(DISCARD_48, int)
+    GENERATE_FIELD(END_RCVD_48, int)
+    GENERATE_FIELD(DISCARD_49, int)
+    GENERATE_FIELD(END_RCVD_49, int)
+    GENERATE_FIELD(DISCARD_50, int)
+    GENERATE_FIELD(END_RCVD_50, int)
+    GENERATE_FIELD(DISCARD_51, int)
+    GENERATE_FIELD(END_RCVD_51, int)
+    GENERATE_FIELD(DISCARD_52, int)
+    GENERATE_FIELD(END_RCVD_52, int)
+    GENERATE_FIELD(DISCARD_53, int)
+    GENERATE_FIELD(END_RCVD_53, int)
+    GENERATE_FIELD(DISCARD_54, int)
+    GENERATE_FIELD(END_RCVD_54, int)
+    GENERATE_FIELD(DISCARD_55, int)
+    GENERATE_FIELD(END_RCVD_55, int)
+    GENERATE_FIELD(DISCARD_56, int)
+    GENERATE_FIELD(END_RCVD_56, int)
+    GENERATE_FIELD(DISCARD_57, int)
+    GENERATE_FIELD(END_RCVD_57, int)
+    GENERATE_FIELD(DISCARD_58, int)
+    GENERATE_FIELD(END_RCVD_58, int)
+    GENERATE_FIELD(DISCARD_59, int)
+    GENERATE_FIELD(END_RCVD_59, int)
+    GENERATE_FIELD(DISCARD_60, int)
+    GENERATE_FIELD(END_RCVD_60, int)
+    GENERATE_FIELD(DISCARD_61, int)
+    GENERATE_FIELD(END_RCVD_61, int)
+    GENERATE_FIELD(DISCARD_62, int)
+    GENERATE_FIELD(END_RCVD_62, int)
+    GENERATE_FIELD(DISCARD_63, int)
+    GENERATE_FIELD(END_RCVD_63, int)
+END_REGISTER(CP_NV_FLAGS_3)
+
+START_REGISTER(CP_STATE_DEBUG_INDEX)
+    GENERATE_FIELD(STATE_DEBUG_INDEX, int)
+END_REGISTER(CP_STATE_DEBUG_INDEX)
+
+START_REGISTER(CP_STATE_DEBUG_DATA)
+    GENERATE_FIELD(STATE_DEBUG_DATA, int)
+END_REGISTER(CP_STATE_DEBUG_DATA)
+
+START_REGISTER(CP_PROG_COUNTER)
+    GENERATE_FIELD(COUNTER, int)
+END_REGISTER(CP_PROG_COUNTER)
+
+START_REGISTER(CP_STAT)
+    GENERATE_FIELD(MIU_WR_BUSY, int)
+    GENERATE_FIELD(MIU_RD_REQ_BUSY, int)
+    GENERATE_FIELD(MIU_RD_RETURN_BUSY, int)
+    GENERATE_FIELD(RBIU_BUSY, int)
+    GENERATE_FIELD(RCIU_BUSY, int)
+    GENERATE_FIELD(CSF_RING_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(CSF_ST_BUSY, int)
+    GENERATE_FIELD(CSF_BUSY, int)
+    GENERATE_FIELD(RING_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int)
+    GENERATE_FIELD(ST_QUEUE_BUSY, int)
+    GENERATE_FIELD(PFP_BUSY, int)
+    GENERATE_FIELD(MEQ_RING_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(MIU_WC_STALL, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(_3D_BUSY, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(ME_WC_BUSY, int)
+    GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int)
+    GENERATE_FIELD(CP_BUSY, int)
+END_REGISTER(CP_STAT)
+
+START_REGISTER(BIOS_0_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_0_SCRATCH)
+
+START_REGISTER(BIOS_1_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_1_SCRATCH)
+
+START_REGISTER(BIOS_2_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_2_SCRATCH)
+
+START_REGISTER(BIOS_3_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_3_SCRATCH)
+
+START_REGISTER(BIOS_4_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_4_SCRATCH)
+
+START_REGISTER(BIOS_5_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_5_SCRATCH)
+
+START_REGISTER(BIOS_6_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_6_SCRATCH)
+
+START_REGISTER(BIOS_7_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_7_SCRATCH)
+
+START_REGISTER(BIOS_8_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_8_SCRATCH)
+
+START_REGISTER(BIOS_9_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_9_SCRATCH)
+
+START_REGISTER(BIOS_10_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_10_SCRATCH)
+
+START_REGISTER(BIOS_11_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_11_SCRATCH)
+
+START_REGISTER(BIOS_12_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_12_SCRATCH)
+
+START_REGISTER(BIOS_13_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_13_SCRATCH)
+
+START_REGISTER(BIOS_14_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_14_SCRATCH)
+
+START_REGISTER(BIOS_15_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_15_SCRATCH)
+
+START_REGISTER(COHER_SIZE_PM4)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_PM4)
+
+START_REGISTER(COHER_BASE_PM4)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(COHER_BASE_PM4)
+
+START_REGISTER(COHER_STATUS_PM4)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_PM4)
+
+START_REGISTER(COHER_SIZE_HOST)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_HOST)
+
+START_REGISTER(COHER_BASE_HOST)
+    GENERATE_FIELD(BASE, hex)
+END_REGISTER(COHER_BASE_HOST)
+
+START_REGISTER(COHER_STATUS_HOST)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_HOST)
+
+START_REGISTER(COHER_DEST_BASE_0)
+    GENERATE_FIELD(DEST_BASE_0, hex)
+END_REGISTER(COHER_DEST_BASE_0)
+
+START_REGISTER(COHER_DEST_BASE_1)
+    GENERATE_FIELD(DEST_BASE_1, hex)
+END_REGISTER(COHER_DEST_BASE_1)
+
+START_REGISTER(COHER_DEST_BASE_2)
+    GENERATE_FIELD(DEST_BASE_2, hex)
+END_REGISTER(COHER_DEST_BASE_2)
+
+START_REGISTER(COHER_DEST_BASE_3)
+    GENERATE_FIELD(DEST_BASE_3, hex)
+END_REGISTER(COHER_DEST_BASE_3)
+
+START_REGISTER(COHER_DEST_BASE_4)
+    GENERATE_FIELD(DEST_BASE_4, hex)
+END_REGISTER(COHER_DEST_BASE_4)
+
+START_REGISTER(COHER_DEST_BASE_5)
+    GENERATE_FIELD(DEST_BASE_5, hex)
+END_REGISTER(COHER_DEST_BASE_5)
+
+START_REGISTER(COHER_DEST_BASE_6)
+    GENERATE_FIELD(DEST_BASE_6, hex)
+END_REGISTER(COHER_DEST_BASE_6)
+
+START_REGISTER(COHER_DEST_BASE_7)
+    GENERATE_FIELD(DEST_BASE_7, hex)
+END_REGISTER(COHER_DEST_BASE_7)
+
+START_REGISTER(RB_SURFACE_INFO)
+    GENERATE_FIELD(SURFACE_PITCH, uint)
+    GENERATE_FIELD(MSAA_SAMPLES, MSAASamples)
+END_REGISTER(RB_SURFACE_INFO)
+
+START_REGISTER(RB_COLOR_INFO)
+    GENERATE_FIELD(COLOR_FORMAT, ColorformatX)
+    GENERATE_FIELD(COLOR_ROUND_MODE, uint)
+    GENERATE_FIELD(COLOR_LINEAR, bool)
+    GENERATE_FIELD(COLOR_ENDIAN, uint)
+    GENERATE_FIELD(COLOR_SWAP, uint)
+    GENERATE_FIELD(COLOR_BASE, uint)
+END_REGISTER(RB_COLOR_INFO)
+
+START_REGISTER(RB_DEPTH_INFO)
+    GENERATE_FIELD(DEPTH_FORMAT, DepthformatX)
+    GENERATE_FIELD(DEPTH_BASE, uint)
+END_REGISTER(RB_DEPTH_INFO)
+
+START_REGISTER(RB_STENCILREFMASK)
+    GENERATE_FIELD(STENCILREF, hex)
+    GENERATE_FIELD(STENCILMASK, hex)
+    GENERATE_FIELD(STENCILWRITEMASK, hex)
+END_REGISTER(RB_STENCILREFMASK)
+
+START_REGISTER(RB_ALPHA_REF)
+    GENERATE_FIELD(ALPHA_REF, float)
+END_REGISTER(RB_ALPHA_REF)
+
+START_REGISTER(RB_COLOR_MASK)
+    GENERATE_FIELD(WRITE_RED, bool)
+    GENERATE_FIELD(WRITE_GREEN, bool)
+    GENERATE_FIELD(WRITE_BLUE, bool)
+    GENERATE_FIELD(WRITE_ALPHA, bool)
+END_REGISTER(RB_COLOR_MASK)
+
+START_REGISTER(RB_BLEND_RED)
+    GENERATE_FIELD(BLEND_RED, uint)
+END_REGISTER(RB_BLEND_RED)
+
+START_REGISTER(RB_BLEND_GREEN)
+    GENERATE_FIELD(BLEND_GREEN, uint)
+END_REGISTER(RB_BLEND_GREEN)
+
+START_REGISTER(RB_BLEND_BLUE)
+    GENERATE_FIELD(BLEND_BLUE, uint)
+END_REGISTER(RB_BLEND_BLUE)
+
+START_REGISTER(RB_BLEND_ALPHA)
+    GENERATE_FIELD(BLEND_ALPHA, uint)
+END_REGISTER(RB_BLEND_ALPHA)
+
+START_REGISTER(RB_FOG_COLOR)
+    GENERATE_FIELD(FOG_RED, uint)
+    GENERATE_FIELD(FOG_GREEN, uint)
+    GENERATE_FIELD(FOG_BLUE, uint)
+END_REGISTER(RB_FOG_COLOR)
+
+START_REGISTER(RB_STENCILREFMASK_BF)
+    GENERATE_FIELD(STENCILREF_BF, hex)
+    GENERATE_FIELD(STENCILMASK_BF, hex)
+    GENERATE_FIELD(STENCILWRITEMASK_BF, hex)
+END_REGISTER(RB_STENCILREFMASK_BF)
+
+START_REGISTER(RB_DEPTHCONTROL)
+    GENERATE_FIELD(STENCIL_ENABLE, bool)
+    GENERATE_FIELD(Z_ENABLE, bool)
+    GENERATE_FIELD(Z_WRITE_ENABLE, bool)
+    GENERATE_FIELD(EARLY_Z_ENABLE, bool)
+    GENERATE_FIELD(ZFUNC, CompareFrag)
+    GENERATE_FIELD(BACKFACE_ENABLE, bool)
+    GENERATE_FIELD(STENCILFUNC, CompareRef)
+    GENERATE_FIELD(STENCILFAIL, StencilOp)
+    GENERATE_FIELD(STENCILZPASS, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL, StencilOp)
+    GENERATE_FIELD(STENCILFUNC_BF, CompareRef)
+    GENERATE_FIELD(STENCILFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILZPASS_BF, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL_BF, StencilOp)
+END_REGISTER(RB_DEPTHCONTROL)
+
+START_REGISTER(RB_BLENDCONTROL)
+    GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(BLEND_FORCE_ENABLE, bool)
+    GENERATE_FIELD(BLEND_FORCE, bool)
+END_REGISTER(RB_BLENDCONTROL)
+
+START_REGISTER(RB_COLORCONTROL)
+    GENERATE_FIELD(ALPHA_FUNC, CompareRef)
+    GENERATE_FIELD(ALPHA_TEST_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool)
+    GENERATE_FIELD(BLEND_DISABLE, bool)
+    GENERATE_FIELD(FOG_ENABLE, bool)
+    GENERATE_FIELD(VS_EXPORTS_FOG, bool)
+    GENERATE_FIELD(ROP_CODE, uint)
+    GENERATE_FIELD(DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(PIXEL_FOG, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex)
+END_REGISTER(RB_COLORCONTROL)
+
+START_REGISTER(RB_MODECONTROL)
+    GENERATE_FIELD(EDRAM_MODE, EdramMode)
+END_REGISTER(RB_MODECONTROL)
+
+START_REGISTER(RB_COLOR_DEST_MASK)
+    GENERATE_FIELD(COLOR_DEST_MASK, uint)
+END_REGISTER(RB_COLOR_DEST_MASK)
+
+START_REGISTER(RB_COPY_CONTROL)
+    GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect)
+    GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool)
+    GENERATE_FIELD(CLEAR_MASK, uint)
+END_REGISTER(RB_COPY_CONTROL)
+
+START_REGISTER(RB_COPY_DEST_BASE)
+    GENERATE_FIELD(COPY_DEST_BASE, uint)
+END_REGISTER(RB_COPY_DEST_BASE)
+
+START_REGISTER(RB_COPY_DEST_PITCH)
+    GENERATE_FIELD(COPY_DEST_PITCH, uint)
+END_REGISTER(RB_COPY_DEST_PITCH)
+
+START_REGISTER(RB_COPY_DEST_INFO)
+    GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian)
+    GENERATE_FIELD(COPY_DEST_LINEAR, uint)
+    GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX)
+    GENERATE_FIELD(COPY_DEST_SWAP, uint)
+    GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(COPY_MASK_WRITE_RED, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex)
+END_REGISTER(RB_COPY_DEST_INFO)
+
+START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+    GENERATE_FIELD(OFFSET_X, uint)
+    GENERATE_FIELD(OFFSET_Y, uint)
+END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+
+START_REGISTER(RB_DEPTH_CLEAR)
+    GENERATE_FIELD(DEPTH_CLEAR, uint)
+END_REGISTER(RB_DEPTH_CLEAR)
+
+START_REGISTER(RB_SAMPLE_COUNT_CTL)
+    GENERATE_FIELD(RESET_SAMPLE_COUNT, bool)
+    GENERATE_FIELD(COPY_SAMPLE_COUNT, bool)
+END_REGISTER(RB_SAMPLE_COUNT_CTL)
+
+START_REGISTER(RB_SAMPLE_COUNT_ADDR)
+    GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint)
+END_REGISTER(RB_SAMPLE_COUNT_ADDR)
+
+START_REGISTER(RB_BC_CONTROL)
+    GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint)
+    GENERATE_FIELD(DISABLE_EDRAM_CAM, bool)
+    GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool)
+    GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool)
+    GENERATE_FIELD(AZ_THROTTLE_COUNT, uint)
+    GENERATE_FIELD(ENABLE_CRC_UPDATE, bool)
+    GENERATE_FIELD(CRC_MODE, bool)
+    GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool)
+    GENERATE_FIELD(DISABLE_ACCUM, bool)
+    GENERATE_FIELD(ACCUM_ALLOC_MASK, uint)
+    GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool)
+    GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int)
+    GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(RESERVED9, bool)
+    GENERATE_FIELD(RESERVED10, bool)
+END_REGISTER(RB_BC_CONTROL)
+
+START_REGISTER(RB_EDRAM_INFO)
+    GENERATE_FIELD(EDRAM_SIZE, EdramSizeX)
+    GENERATE_FIELD(EDRAM_MAPPING_MODE, uint)
+    GENERATE_FIELD(EDRAM_RANGE, hex)
+END_REGISTER(RB_EDRAM_INFO)
+
+START_REGISTER(RB_CRC_RD_PORT)
+    GENERATE_FIELD(CRC_DATA, hex)
+END_REGISTER(RB_CRC_RD_PORT)
+
+START_REGISTER(RB_CRC_CONTROL)
+    GENERATE_FIELD(CRC_RD_ADVANCE, bool)
+END_REGISTER(RB_CRC_CONTROL)
+
+START_REGISTER(RB_CRC_MASK)
+    GENERATE_FIELD(CRC_MASK, hex)
+END_REGISTER(RB_CRC_MASK)
+
+START_REGISTER(RB_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT)
+END_REGISTER(RB_PERFCOUNTER0_SELECT)
+
+START_REGISTER(RB_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_LOW)
+
+START_REGISTER(RB_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_HI)
+
+START_REGISTER(RB_TOTAL_SAMPLES)
+    GENERATE_FIELD(TOTAL_SAMPLES, int)
+END_REGISTER(RB_TOTAL_SAMPLES)
+
+START_REGISTER(RB_ZPASS_SAMPLES)
+    GENERATE_FIELD(ZPASS_SAMPLES, int)
+END_REGISTER(RB_ZPASS_SAMPLES)
+
+START_REGISTER(RB_ZFAIL_SAMPLES)
+    GENERATE_FIELD(ZFAIL_SAMPLES, int)
+END_REGISTER(RB_ZFAIL_SAMPLES)
+
+START_REGISTER(RB_SFAIL_SAMPLES)
+    GENERATE_FIELD(SFAIL_SAMPLES, int)
+END_REGISTER(RB_SFAIL_SAMPLES)
+
+START_REGISTER(RB_DEBUG_0)
+    GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z1_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z0_FULL, bool)
+    GENERATE_FIELD(RDREQ_C1_FULL, bool)
+    GENERATE_FIELD(RDREQ_C0_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z1_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z0_FULL, bool)
+    GENERATE_FIELD(WRREQ_C1_FULL, bool)
+    GENERATE_FIELD(WRREQ_C0_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool)
+    GENERATE_FIELD(C_SX_LAT_FULL, bool)
+    GENERATE_FIELD(C_SX_CMD_FULL, bool)
+    GENERATE_FIELD(C_EZ_TILE_FULL, bool)
+    GENERATE_FIELD(C_REQ_FULL, bool)
+    GENERATE_FIELD(C_MASK_FULL, bool)
+    GENERATE_FIELD(EZ_INFSAMP_FULL, bool)
+END_REGISTER(RB_DEBUG_0)
+
+START_REGISTER(RB_DEBUG_1)
+    GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(C_SX_LAT_EMPTY, bool)
+    GENERATE_FIELD(C_SX_CMD_EMPTY, bool)
+    GENERATE_FIELD(C_EZ_TILE_EMPTY, bool)
+    GENERATE_FIELD(C_REQ_EMPTY, bool)
+    GENERATE_FIELD(C_MASK_EMPTY, bool)
+    GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool)
+END_REGISTER(RB_DEBUG_1)
+
+START_REGISTER(RB_DEBUG_2)
+    GENERATE_FIELD(TILE_FIFO_COUNT, bool)
+    GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool)
+    GENERATE_FIELD(MEM_EXPORT_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool)
+    GENERATE_FIELD(CURRENT_TILE_EVENT, bool)
+    GENERATE_FIELD(EZ_INFTILE_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool)
+    GENERATE_FIELD(Z0_MASK_FULL, bool)
+    GENERATE_FIELD(Z1_MASK_FULL, bool)
+    GENERATE_FIELD(Z0_REQ_FULL, bool)
+    GENERATE_FIELD(Z1_REQ_FULL, bool)
+    GENERATE_FIELD(Z_SAMP_FULL, bool)
+    GENERATE_FIELD(Z_TILE_FULL, bool)
+    GENERATE_FIELD(EZ_INFTILE_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool)
+    GENERATE_FIELD(Z0_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z1_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z0_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z1_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z_SAMP_EMPTY, bool)
+    GENERATE_FIELD(Z_TILE_EMPTY, bool)
+END_REGISTER(RB_DEBUG_2)
+
+START_REGISTER(RB_DEBUG_3)
+    GENERATE_FIELD(ACCUM_VALID, bool)
+    GENERATE_FIELD(ACCUM_FLUSHING, bool)
+    GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool)
+    GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool)
+    GENERATE_FIELD(SHD_FULL, bool)
+    GENERATE_FIELD(SHD_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool)
+    GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_LOWER_FULL, bool)
+    GENERATE_FIELD(ZEXP_UPPER_FULL, bool)
+END_REGISTER(RB_DEBUG_3)
+
+START_REGISTER(RB_DEBUG_4)
+    GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool)
+    GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool)
+    GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool)
+END_REGISTER(RB_DEBUG_4)
+
+START_REGISTER(RB_FLAG_CONTROL)
+    GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool)
+END_REGISTER(RB_FLAG_CONTROL)
+
+START_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray)
+    GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX)
+END_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+
+START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX)
+END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h
new file mode 100644
index 00000000000..0e32e421d0a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _R400IPT_H_
+#define _R400IPT_H_
+
+// Hand-generated list from Yamato_PM4_Spec.doc
+
+#define PM4_PACKET0_NOP     0x00000000          // Empty type-0 packet header
+#define PM4_PACKET1_NOP     0x40000000          // Empty type-1 packet header
+#define PM4_PACKET2_NOP     0x80000000          // Empty type-2 packet header (reserved)
+
+#define PM4_COUNT_SHIFT     16  
+#define PM4_COUNT_MASK      
+#define PM4_PACKET_COUNT(__x)   ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000)
+// Type 3 packet headers
+
+#define PM4_PACKET3_NOP                         0xC0001000  // Do nothing.
+#define PM4_PACKET3_IB_PREFETCH_END             0xC0001700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_SUBBLK_PREFETCH             0xC0001F00  // Internal Packet Used Only by CP
+
+#define PM4_PACKET3_INSTR_PREFETCH              0xC0002000  // Internal Packet Used Only by CP
+#define PM4_PACKET3_REG_RMW                     0xC0002100  // Register Read-Modify-Write                               New for R400
+#define PM4_PACKET3_DRAW_INDX                   0xC0002200  // Initiate fetch of index buffer                           New for R400
+#define PM4_PACKET3_VIZ_QUERY                   0xC0002300  // Begin/End initiator for Viz Query extent processing      New for R400
+#define PM4_PACKET3_SET_STATE                   0xC0002500  // Fetch State Sub-Blocks and Initiate Shader Code DMAs     New for R400
+#define PM4_PACKET3_WAIT_FOR_IDLE               0xC0002600  // Wait for the engine to be idle. 
+#define PM4_PACKET3_IM_LOAD                     0xC0002700  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_IM_LOAD_IMMEDIATE           0xC0002B00  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_SET_CONSTANT                0xC0002D00  // Load Constant Into Chip & Shadow to Memory               New for R400
+#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT       0xC0002E00  // Load All Constants from a Location in Memory             New for R400
+#define PM4_PACKET3_LOAD_ALU_CONSTANT           0xC0002F00  // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants
+
+#define PM4_PACKET3_DRAW_INDX_BIN               0xC0003400  // Initiate fetch of index buffer and BIN info used for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2_BIN          0xC0003500  // Draw using supplied indices and initiate fetch of BIN info for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2              0xC0003600  // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt
+#define PM4_PACKET3_INDIRECT_BUFFER_PFD         0xC0003700
+#define PM4_PACKET3_INVALIDATE_STATE            0xC0003B00  // Selective Invalidation of State Pointers                 New for R400
+#define PM4_PACKET3_WAIT_REG_MEM                0xC0003C00  // Wait Until a Register or Memory Location is a Specific Value.   New for R400
+#define PM4_PACKET3_MEM_WRITE                   0xC0003D00  // Write DWORD to Memory For Synchronization                New for R400
+#define PM4_PACKET3_REG_TO_MEM                  0xC0003E00  // Reads Register in Chip and Writes to Memory              New for R400
+#define PM4_PACKET3_INDIRECT_BUFFER             0xC0003F00  // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer.  Supported
+
+#define PM4_PACKET3_CP_INTERRUPT                0xC0004000  // Generate Interrupt from the Command Stream               New for R400
+#define PM4_PACKET3_COND_EXEC                   0xC0004400  // Conditional execution of a sequence of packets
+#define PM4_PACKET3_COND_WRITE                  0xC0004500  // Conditional Write to Memory                              New for R400
+#define PM4_PACKET3_EVENT_WRITE                 0xC0004600  // Generate An Event that Creates a Write to Memory when Completed  New for R400
+#define PM4_PACKET3_INSTR_MATCH                 0xC0004700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_ME_INIT                     0xC0004800  // Initialize CP's Micro Engine                             New for R400
+#define PM4_PACKET3_CONST_PREFETCH              0xC0004900  // Internal packet used only by CP
+#define PM4_PACKET3_MEM_WRITE_CNTR              0xC0004F00
+
+#define PM4_PACKET3_SET_BIN_MASK                0xC0005000  // Sets the 64-bit BIN_MASK register in the PFP
+#define PM4_PACKET3_SET_BIN_SELECT              0xC0005100  // Sets the 64-bit BIN_SELECT register in the PFP
+#define PM4_PACKET3_WAIT_REG_EQ                 0xC0005200  // Wait until a register location is equal to a specific value
+#define PM4_PACKET3_WAIT_REG_GTE                0xC0005300  // Wait until a register location is greater than or equal to a specific value
+#define PM4_PACKET3_INCR_UPDT_STATE             0xC0005500  // Internal Packet Used Only by CP  
+#define PM4_PACKET3_INCR_UPDT_CONST             0xC0005600  // Internal Packet Used Only by CP
+#define PM4_PACKET3_INCR_UPDT_INSTR             0xC0005700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_EVENT_WRITE_SHD             0xC0005800  // Generate a VS|PS_Done Event.
+#define PM4_PACKET3_EVENT_WRITE_CFL             0xC0005900  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_EVENT_WRITE_ZPD             0xC0005B00  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_WAIT_UNTIL_READ             0xC0005C00  // Wait Until a Read completes.
+#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE        0xC0005D00  // Wait Until all Base/Size writes from an IB_PFD packet have completed.
+#define PM4_PACKET3_CONTEXT_UPDATE              0xC0005E00  // Updates the current context if needed.
+
+    /****** New Opcodes For R400 (all decode values are TBD) ******/
+
+
+#endif //  _R400IPT_H_
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h
new file mode 100644
index 00000000000..ad3d829bc94
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h
@@ -0,0 +1,5739 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_MASK_HEADER)
+#define _yamato_MASK_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK            0xffffffffL
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK             0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA                  0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK            0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA                 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK             0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA                  0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK            0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA                 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK             0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA                  0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK            0x00000020L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA                 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                    0x00000100L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT                         0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                     0x00000200L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT                          0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                    0x00000400L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT                         0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK               0x00000800L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF                    0x00000800L
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                 0x00010000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE                      0x00010000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK       0x00040000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA            0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK            0x00080000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF                 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK          0x00100000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT               0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                  0x00200000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR                       0x00200000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK                0x00400000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN                     0x00400000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK                 0x00800000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN                      0x00800000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK                 0x01000000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN                      0x01000000L
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK           0x00000001L
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA                0x00000001L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_CL_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_SC_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                    0x00000001L
+#define PA_SU_VTX_CNTL__PIX_CENTER                         0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                    0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                    0x00000038L
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT_MASK                      0x0000ffffL
+#define PA_SU_POINT_SIZE__WIDTH_MASK                       0xffff0000L
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                  0x0000ffffL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                  0xffff0000L
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH_MASK                        0x0000ffffL
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT                     0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                 0x00000002L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK                      0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK                      0x00000004L
+#define PA_SU_SC_MODE_CNTL__FACE                           0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK      0x000000e0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK       0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK  0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE       0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK   0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE        0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK   0x00002000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE        0x00002000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK               0x00008000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE                    0x00008000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK  0x00010000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE       0x00010000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK       0x00040000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE            0x00040000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK        0x00080000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST             0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK            0x00100000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS                 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK         0x00200000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA              0x00200000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK         0x00800000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE              0x00800000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK      0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI           0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK          0xffffffffL
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK        0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK           0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK         0xffffffffL
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK          0x00007fffL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK          0x7fff0000L
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK             0x00000007L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK              0x0001e000L
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK_MASK                        0x0000ffffL
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK              0x0000ffffL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK              0x00ff0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK         0x10000000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER              0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK           0x60000000L
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL_MASK                    0x000000ffL
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK                0x00000100L
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL                     0x00000100L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK            0x00000200L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH                 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                   0x00000400L
+#define PA_SC_LINE_CNTL__LAST_PIXEL                        0x00000400L
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                 0x3fff0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE     0x80000000L
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                 0x3fff0000L
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                 0x7fff0000L
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                 0x7fff0000L
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK                0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA                     0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK                 0x0000003eL
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK        0x00000080L
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z             0x00000080L
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK           0xffffffffL
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK         0x0000000fL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK       0x0000ff00L
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                    0x80000000L
+#define PA_CL_CNTL_STATUS__CL_BUSY                         0x80000000L
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                    0x80000000L
+#define PA_SU_CNTL_STATUS__SU_BUSY                         0x80000000L
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY_MASK                    0x80000000L
+#define PA_SC_CNTL_STATUS__SC_BUSY                         0x80000000L
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK    0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write         0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK     0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full          0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK    0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write         0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK     0x00000008L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full          0x00000008L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty   0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full    0x00000020L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty      0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK  0x00000080L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full       0x00000080L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK  0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty       0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK   0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full        0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK  0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty       0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK   0x00000800L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full        0x00000800L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty      0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK       0x00002000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full            0x00002000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty  0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full   0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty  0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full   0x00020000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty    0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full     0x00080000L
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK              0xfff00000L
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet   0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim    0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive  0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK      0x00380000L
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK              0xff000000L
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK             0x001fffffL
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK             0x7f000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK             0x000fff00L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK             0xfc000000L
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event  0x00000080L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK             0xffffff00L
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK             0x00000006L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK             0x00c00000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK             0xf0000000L
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK     0x00000001L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event          0x00000001L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK             0x000000c0L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK             0x00003000L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK             0x000c0000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK          0x00100000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid               0x00100000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait      0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK     0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty          0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK      0x20000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full           0x20000000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK             0x00000030L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK             0x00000c00L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK             0x00180000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet  0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK  0xfc000000L
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK              0xfffffff0L
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK             0x0000001cL
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK   0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty        0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK             0x00007800L
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK   0x00200000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid        0x00200000L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK             0xffc00000L
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK        0x0000000fL
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK       0x000007f0L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK             0x00003800L
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK      0x0003c000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1  0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0  0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK        0x07f00000L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK             0xf8000000L
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK             0x0000000fL
+#define SXIFCCG_DEBUG_REG0__position_address_MASK          0x00000070L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK              0x00000380L
+#define SXIFCCG_DEBUG_REG0__point_address_MASK             0x00001c00L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK              0x0000e000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx   0x00010000L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK              0x00060000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK    0x00780000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK         0x3f800000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK     0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc          0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK     0x80000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel          0x80000000L
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK              0x00000003L
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK            0x0000000cL
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK       0x00000070L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK              0x00000780L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK        0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance             0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK           0x00007000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector  0x00008000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK              0x000f0000L
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK                   0x00100000L
+#define SXIFCCG_DEBUG_REG1__aux_sel                        0x00100000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK              0x00600000L
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK              0x01800000L
+#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK          0xfe000000L
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent_MASK                   0x00000001L
+#define SXIFCCG_DEBUG_REG2__sx_sent                        0x00000001L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK              0x00000002L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3                   0x00000002L
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK                    0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_aux                         0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK           0x000001f8L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK          0x0000fe00L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK              0x00010000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2                   0x00010000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx    0x00020000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK              0x000c0000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK              0x03c00000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK   0x04000000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded        0x04000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK     0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty          0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK      0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full           0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK  0xe0000000L
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK              0x00000010L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3                   0x00000010L
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK       0x000000e0L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK              0x00000f00L
+#define SXIFCCG_DEBUG_REG3__current_state_MASK             0x00003000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK         0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty              0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK          0x00008000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full               0x00008000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK              0x00030000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK    0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty         0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK     0x00080000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full          0x00080000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK   0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty        0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK    0x00200000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full         0x00200000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK              0xffc00000L
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK               0x0000001fL
+#define SETUP_DEBUG_REG0__pmode_state_MASK                 0x000007e0L
+#define SETUP_DEBUG_REG0__ge_stallb_MASK                   0x00000800L
+#define SETUP_DEBUG_REG0__ge_stallb                        0x00000800L
+#define SETUP_DEBUG_REG0__geom_enable_MASK                 0x00001000L
+#define SETUP_DEBUG_REG0__geom_enable                      0x00001000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK           0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr                0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK                 0x00004000L
+#define SETUP_DEBUG_REG0__su_clip_rtr                      0x00004000L
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK                  0x00008000L
+#define SETUP_DEBUG_REG0__pfifo_busy                       0x00008000L
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK                0x00010000L
+#define SETUP_DEBUG_REG0__su_cntl_busy                     0x00010000L
+#define SETUP_DEBUG_REG0__geom_busy_MASK                   0x00020000L
+#define SETUP_DEBUG_REG0__geom_busy                        0x00020000L
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK             0x00000800L
+#define SETUP_DEBUG_REG4__null_prim_gated                  0x00000800L
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK            0x00001000L
+#define SETUP_DEBUG_REG4__backfacing_gated                 0x00001000L
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK               0x0000e000L
+#define SETUP_DEBUG_REG4__clipped_gated_MASK               0x00010000L
+#define SETUP_DEBUG_REG4__clipped_gated                    0x00010000L
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK          0x000e0000L
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK                0x00100000L
+#define SETUP_DEBUG_REG4__xmajor_gated                     0x00100000L
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK          0x00600000L
+#define SETUP_DEBUG_REG4__type_gated_MASK                  0x03800000L
+#define SETUP_DEBUG_REG4__fpov_gated_MASK                  0x04000000L
+#define SETUP_DEBUG_REG4__fpov_gated                       0x04000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK            0x08000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated                 0x08000000L
+#define SETUP_DEBUG_REG4__event_gated_MASK                 0x10000000L
+#define SETUP_DEBUG_REG4__event_gated                      0x10000000L
+#define SETUP_DEBUG_REG4__eop_gated_MASK                   0x20000000L
+#define SETUP_DEBUG_REG4__eop_gated                        0x20000000L
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK       0x003ff800L
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK         0x00c00000L
+#define SETUP_DEBUG_REG5__event_id_gated_MASK              0x1f000000L
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1_MASK                      0x00000001L
+#define SC_DEBUG_0__pa_freeze_b1                           0x00000001L
+#define SC_DEBUG_0__pa_sc_valid_MASK                       0x00000002L
+#define SC_DEBUG_0__pa_sc_valid                            0x00000002L
+#define SC_DEBUG_0__pa_sc_phase_MASK                       0x0000001cL
+#define SC_DEBUG_0__cntx_cnt_MASK                          0x00000fe0L
+#define SC_DEBUG_0__decr_cntx_cnt_MASK                     0x00001000L
+#define SC_DEBUG_0__decr_cntx_cnt                          0x00001000L
+#define SC_DEBUG_0__incr_cntx_cnt_MASK                     0x00002000L
+#define SC_DEBUG_0__incr_cntx_cnt                          0x00002000L
+#define SC_DEBUG_0__trigger_MASK                           0x80000000L
+#define SC_DEBUG_0__trigger                                0x80000000L
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state_MASK                          0x00000007L
+#define SC_DEBUG_1__em1_data_ready_MASK                    0x00000008L
+#define SC_DEBUG_1__em1_data_ready                         0x00000008L
+#define SC_DEBUG_1__em2_data_ready_MASK                    0x00000010L
+#define SC_DEBUG_1__em2_data_ready                         0x00000010L
+#define SC_DEBUG_1__move_em1_to_em2_MASK                   0x00000020L
+#define SC_DEBUG_1__move_em1_to_em2                        0x00000020L
+#define SC_DEBUG_1__ef_data_ready_MASK                     0x00000040L
+#define SC_DEBUG_1__ef_data_ready                          0x00000040L
+#define SC_DEBUG_1__ef_state_MASK                          0x00000180L
+#define SC_DEBUG_1__pipe_valid_MASK                        0x00000200L
+#define SC_DEBUG_1__pipe_valid                             0x00000200L
+#define SC_DEBUG_1__trigger_MASK                           0x80000000L
+#define SC_DEBUG_1__trigger                                0x80000000L
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly_MASK                        0x00000001L
+#define SC_DEBUG_2__rc_rtr_dly                             0x00000001L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK              0x00000002L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1                   0x00000002L
+#define SC_DEBUG_2__pipe_freeze_b_MASK                     0x00000008L
+#define SC_DEBUG_2__pipe_freeze_b                          0x00000008L
+#define SC_DEBUG_2__prim_rts_MASK                          0x00000010L
+#define SC_DEBUG_2__prim_rts                               0x00000010L
+#define SC_DEBUG_2__next_prim_rts_dly_MASK                 0x00000020L
+#define SC_DEBUG_2__next_prim_rts_dly                      0x00000020L
+#define SC_DEBUG_2__next_prim_rtr_dly_MASK                 0x00000040L
+#define SC_DEBUG_2__next_prim_rtr_dly                      0x00000040L
+#define SC_DEBUG_2__pre_stage1_rts_d1_MASK                 0x00000080L
+#define SC_DEBUG_2__pre_stage1_rts_d1                      0x00000080L
+#define SC_DEBUG_2__stage0_rts_MASK                        0x00000100L
+#define SC_DEBUG_2__stage0_rts                             0x00000100L
+#define SC_DEBUG_2__phase_rts_dly_MASK                     0x00000200L
+#define SC_DEBUG_2__phase_rts_dly                          0x00000200L
+#define SC_DEBUG_2__end_of_prim_s1_dly_MASK                0x00008000L
+#define SC_DEBUG_2__end_of_prim_s1_dly                     0x00008000L
+#define SC_DEBUG_2__pass_empty_prim_s1_MASK                0x00010000L
+#define SC_DEBUG_2__pass_empty_prim_s1                     0x00010000L
+#define SC_DEBUG_2__event_id_s1_MASK                       0x003e0000L
+#define SC_DEBUG_2__event_s1_MASK                          0x00400000L
+#define SC_DEBUG_2__event_s1                               0x00400000L
+#define SC_DEBUG_2__trigger_MASK                           0x80000000L
+#define SC_DEBUG_2__trigger                                0x80000000L
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1_MASK                         0x000007ffL
+#define SC_DEBUG_3__y_curr_s1_MASK                         0x003ff800L
+#define SC_DEBUG_3__trigger_MASK                           0x80000000L
+#define SC_DEBUG_3__trigger                                0x80000000L
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_4__y_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_4__y_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_4__y_dir_s1                               0x10000000L
+#define SC_DEBUG_4__trigger_MASK                           0x80000000L
+#define SC_DEBUG_4__trigger                                0x80000000L
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_5__x_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_5__x_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_5__x_dir_s1                               0x10000000L
+#define SC_DEBUG_5__trigger_MASK                           0x80000000L
+#define SC_DEBUG_5__trigger                                0x80000000L
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty_MASK                        0x00000001L
+#define SC_DEBUG_6__z_ff_empty                             0x00000001L
+#define SC_DEBUG_6__qmcntl_ff_empty_MASK                   0x00000002L
+#define SC_DEBUG_6__qmcntl_ff_empty                        0x00000002L
+#define SC_DEBUG_6__xy_ff_empty_MASK                       0x00000004L
+#define SC_DEBUG_6__xy_ff_empty                            0x00000004L
+#define SC_DEBUG_6__event_flag_MASK                        0x00000008L
+#define SC_DEBUG_6__event_flag                             0x00000008L
+#define SC_DEBUG_6__z_mask_needed_MASK                     0x00000010L
+#define SC_DEBUG_6__z_mask_needed                          0x00000010L
+#define SC_DEBUG_6__state_MASK                             0x000000e0L
+#define SC_DEBUG_6__state_delayed_MASK                     0x00000700L
+#define SC_DEBUG_6__data_valid_MASK                        0x00000800L
+#define SC_DEBUG_6__data_valid                             0x00000800L
+#define SC_DEBUG_6__data_valid_d_MASK                      0x00001000L
+#define SC_DEBUG_6__data_valid_d                           0x00001000L
+#define SC_DEBUG_6__tilex_delayed_MASK                     0x003fe000L
+#define SC_DEBUG_6__tiley_delayed_MASK                     0x7fc00000L
+#define SC_DEBUG_6__trigger_MASK                           0x80000000L
+#define SC_DEBUG_6__trigger                                0x80000000L
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag_MASK                        0x00000001L
+#define SC_DEBUG_7__event_flag                             0x00000001L
+#define SC_DEBUG_7__deallocate_MASK                        0x0000000eL
+#define SC_DEBUG_7__fpos_MASK                              0x00000010L
+#define SC_DEBUG_7__fpos                                   0x00000010L
+#define SC_DEBUG_7__sr_prim_we_MASK                        0x00000020L
+#define SC_DEBUG_7__sr_prim_we                             0x00000020L
+#define SC_DEBUG_7__last_tile_MASK                         0x00000040L
+#define SC_DEBUG_7__last_tile                              0x00000040L
+#define SC_DEBUG_7__tile_ff_we_MASK                        0x00000080L
+#define SC_DEBUG_7__tile_ff_we                             0x00000080L
+#define SC_DEBUG_7__qs_data_valid_MASK                     0x00000100L
+#define SC_DEBUG_7__qs_data_valid                          0x00000100L
+#define SC_DEBUG_7__qs_q0_y_MASK                           0x00000600L
+#define SC_DEBUG_7__qs_q0_x_MASK                           0x00001800L
+#define SC_DEBUG_7__qs_q0_valid_MASK                       0x00002000L
+#define SC_DEBUG_7__qs_q0_valid                            0x00002000L
+#define SC_DEBUG_7__prim_ff_we_MASK                        0x00004000L
+#define SC_DEBUG_7__prim_ff_we                             0x00004000L
+#define SC_DEBUG_7__tile_ff_re_MASK                        0x00008000L
+#define SC_DEBUG_7__tile_ff_re                             0x00008000L
+#define SC_DEBUG_7__fw_prim_data_valid_MASK                0x00010000L
+#define SC_DEBUG_7__fw_prim_data_valid                     0x00010000L
+#define SC_DEBUG_7__last_quad_of_tile_MASK                 0x00020000L
+#define SC_DEBUG_7__last_quad_of_tile                      0x00020000L
+#define SC_DEBUG_7__first_quad_of_tile_MASK                0x00040000L
+#define SC_DEBUG_7__first_quad_of_tile                     0x00040000L
+#define SC_DEBUG_7__first_quad_of_prim_MASK                0x00080000L
+#define SC_DEBUG_7__first_quad_of_prim                     0x00080000L
+#define SC_DEBUG_7__new_prim_MASK                          0x00100000L
+#define SC_DEBUG_7__new_prim                               0x00100000L
+#define SC_DEBUG_7__load_new_tile_data_MASK                0x00200000L
+#define SC_DEBUG_7__load_new_tile_data                     0x00200000L
+#define SC_DEBUG_7__state_MASK                             0x00c00000L
+#define SC_DEBUG_7__fifos_ready_MASK                       0x01000000L
+#define SC_DEBUG_7__fifos_ready                            0x01000000L
+#define SC_DEBUG_7__trigger_MASK                           0x80000000L
+#define SC_DEBUG_7__trigger                                0x80000000L
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last_MASK                       0x00000001L
+#define SC_DEBUG_8__sample_last                            0x00000001L
+#define SC_DEBUG_8__sample_mask_MASK                       0x0000001eL
+#define SC_DEBUG_8__sample_y_MASK                          0x00000060L
+#define SC_DEBUG_8__sample_x_MASK                          0x00000180L
+#define SC_DEBUG_8__sample_send_MASK                       0x00000200L
+#define SC_DEBUG_8__sample_send                            0x00000200L
+#define SC_DEBUG_8__next_cycle_MASK                        0x00000c00L
+#define SC_DEBUG_8__ez_sample_ff_full_MASK                 0x00001000L
+#define SC_DEBUG_8__ez_sample_ff_full                      0x00001000L
+#define SC_DEBUG_8__rb_sc_samp_rtr_MASK                    0x00002000L
+#define SC_DEBUG_8__rb_sc_samp_rtr                         0x00002000L
+#define SC_DEBUG_8__num_samples_MASK                       0x0000c000L
+#define SC_DEBUG_8__last_quad_of_tile_MASK                 0x00010000L
+#define SC_DEBUG_8__last_quad_of_tile                      0x00010000L
+#define SC_DEBUG_8__last_quad_of_prim_MASK                 0x00020000L
+#define SC_DEBUG_8__last_quad_of_prim                      0x00020000L
+#define SC_DEBUG_8__first_quad_of_prim_MASK                0x00040000L
+#define SC_DEBUG_8__first_quad_of_prim                     0x00040000L
+#define SC_DEBUG_8__sample_we_MASK                         0x00080000L
+#define SC_DEBUG_8__sample_we                              0x00080000L
+#define SC_DEBUG_8__fpos_MASK                              0x00100000L
+#define SC_DEBUG_8__fpos                                   0x00100000L
+#define SC_DEBUG_8__event_id_MASK                          0x03e00000L
+#define SC_DEBUG_8__event_flag_MASK                        0x04000000L
+#define SC_DEBUG_8__event_flag                             0x04000000L
+#define SC_DEBUG_8__fw_prim_data_valid_MASK                0x08000000L
+#define SC_DEBUG_8__fw_prim_data_valid                     0x08000000L
+#define SC_DEBUG_8__trigger_MASK                           0x80000000L
+#define SC_DEBUG_8__trigger                                0x80000000L
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send_MASK                        0x00000001L
+#define SC_DEBUG_9__rb_sc_send                             0x00000001L
+#define SC_DEBUG_9__rb_sc_ez_mask_MASK                     0x0000001eL
+#define SC_DEBUG_9__fifo_data_ready_MASK                   0x00000020L
+#define SC_DEBUG_9__fifo_data_ready                        0x00000020L
+#define SC_DEBUG_9__early_z_enable_MASK                    0x00000040L
+#define SC_DEBUG_9__early_z_enable                         0x00000040L
+#define SC_DEBUG_9__mask_state_MASK                        0x00000180L
+#define SC_DEBUG_9__next_ez_mask_MASK                      0x01fffe00L
+#define SC_DEBUG_9__mask_ready_MASK                        0x02000000L
+#define SC_DEBUG_9__mask_ready                             0x02000000L
+#define SC_DEBUG_9__drop_sample_MASK                       0x04000000L
+#define SC_DEBUG_9__drop_sample                            0x04000000L
+#define SC_DEBUG_9__fetch_new_sample_data_MASK             0x08000000L
+#define SC_DEBUG_9__fetch_new_sample_data                  0x08000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK          0x10000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask               0x10000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK         0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data              0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK           0x40000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data                0x40000000L
+#define SC_DEBUG_9__trigger_MASK                           0x80000000L
+#define SC_DEBUG_9__trigger                                0x80000000L
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask_MASK             0x0000ffffL
+#define SC_DEBUG_10__trigger_MASK                          0x80000000L
+#define SC_DEBUG_10__trigger                               0x80000000L
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready_MASK             0x00000001L
+#define SC_DEBUG_11__ez_sample_data_ready                  0x00000001L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK        0x00000002L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data             0x00000002L
+#define SC_DEBUG_11__ez_prim_data_ready_MASK               0x00000004L
+#define SC_DEBUG_11__ez_prim_data_ready                    0x00000004L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK          0x00000008L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data               0x00000008L
+#define SC_DEBUG_11__iterator_input_fz_MASK                0x00000010L
+#define SC_DEBUG_11__iterator_input_fz                     0x00000010L
+#define SC_DEBUG_11__packer_send_quads_MASK                0x00000020L
+#define SC_DEBUG_11__packer_send_quads                     0x00000020L
+#define SC_DEBUG_11__packer_send_cmd_MASK                  0x00000040L
+#define SC_DEBUG_11__packer_send_cmd                       0x00000040L
+#define SC_DEBUG_11__packer_send_event_MASK                0x00000080L
+#define SC_DEBUG_11__packer_send_event                     0x00000080L
+#define SC_DEBUG_11__next_state_MASK                       0x00000700L
+#define SC_DEBUG_11__state_MASK                            0x00003800L
+#define SC_DEBUG_11__stall_MASK                            0x00004000L
+#define SC_DEBUG_11__stall                                 0x00004000L
+#define SC_DEBUG_11__trigger_MASK                          0x80000000L
+#define SC_DEBUG_11__trigger                               0x80000000L
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff_MASK            0x00000001L
+#define SC_DEBUG_12__SQ_iterator_free_buff                 0x00000001L
+#define SC_DEBUG_12__event_id_MASK                         0x0000003eL
+#define SC_DEBUG_12__event_flag_MASK                       0x00000040L
+#define SC_DEBUG_12__event_flag                            0x00000040L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK          0x00000080L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly               0x00000080L
+#define SC_DEBUG_12__itercmdfifo_full_MASK                 0x00000100L
+#define SC_DEBUG_12__itercmdfifo_full                      0x00000100L
+#define SC_DEBUG_12__itercmdfifo_empty_MASK                0x00000200L
+#define SC_DEBUG_12__itercmdfifo_empty                     0x00000200L
+#define SC_DEBUG_12__iter_ds_one_clk_command_MASK          0x00000400L
+#define SC_DEBUG_12__iter_ds_one_clk_command               0x00000400L
+#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK             0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_prim0                  0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_vector_MASK            0x00001000L
+#define SC_DEBUG_12__iter_ds_end_of_vector                 0x00001000L
+#define SC_DEBUG_12__iter_qdhit0_MASK                      0x00002000L
+#define SC_DEBUG_12__iter_qdhit0                           0x00002000L
+#define SC_DEBUG_12__bc_use_centers_reg_MASK               0x00004000L
+#define SC_DEBUG_12__bc_use_centers_reg                    0x00004000L
+#define SC_DEBUG_12__bc_output_xy_reg_MASK                 0x00008000L
+#define SC_DEBUG_12__bc_output_xy_reg                      0x00008000L
+#define SC_DEBUG_12__iter_phase_out_MASK                   0x00030000L
+#define SC_DEBUG_12__iter_phase_reg_MASK                   0x000c0000L
+#define SC_DEBUG_12__iterator_SP_valid_MASK                0x00100000L
+#define SC_DEBUG_12__iterator_SP_valid                     0x00100000L
+#define SC_DEBUG_12__eopv_reg_MASK                         0x00200000L
+#define SC_DEBUG_12__eopv_reg                              0x00200000L
+#define SC_DEBUG_12__one_clk_cmd_reg_MASK                  0x00400000L
+#define SC_DEBUG_12__one_clk_cmd_reg                       0x00400000L
+#define SC_DEBUG_12__iter_dx_end_of_prim_MASK              0x00800000L
+#define SC_DEBUG_12__iter_dx_end_of_prim                   0x00800000L
+#define SC_DEBUG_12__trigger_MASK                          0x80000000L
+#define SC_DEBUG_12__trigger                               0x80000000L
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK                  0x00000001L
+#define GFX_COPY_STATE__SRC_STATE_ID                       0x00000001L
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK                 0x0000003fL
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK             0x000000c0L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK                0x00000800L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE                     0x00000800L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                   0x00001000L
+#define VGT_DRAW_INITIATOR__NOT_EOP                        0x00001000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK               0x00002000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX                    0x00002000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK     0x00004000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE          0x00004000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK           0x00008000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE                0x00008000L
+#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK               0xffff0000L
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK               0x0000003fL
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR_MASK                       0xffffffffL
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_DMA_SIZE__SWAP_MODE_MASK                       0xc0000000L
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK                   0xffffffffL
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                    0x00ffffffL
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                    0x00ffffffL
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                  0x00ffffffL
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK  0x00000007L
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK            0x00000003L
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK      0x00ffffffL
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC_MASK                             0x0000ffffL
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK            0x0000001fL
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK             0x00000001L
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID                  0x00000001L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK             0x00010000L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID                  0x00010000L
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK                0x0000001fL
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK                     0x00000001L
+#define VGT_CNTL_STATUS__VGT_BUSY                          0x00000001L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK                 0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY                      0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK             0x00000004L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY                  0x00000004L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK                 0x00000008L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY                      0x00000008L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                  0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY                       0x00000010L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK                 0x00000020L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY                      0x00000020L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                  0x00000040L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY                       0x00000040L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                 0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY                      0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK            0x00000100L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY                 0x00000100L
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy_MASK                   0x00000001L
+#define VGT_DEBUG_REG0__te_grp_busy                        0x00000001L
+#define VGT_DEBUG_REG0__pt_grp_busy_MASK                   0x00000002L
+#define VGT_DEBUG_REG0__pt_grp_busy                        0x00000002L
+#define VGT_DEBUG_REG0__vr_grp_busy_MASK                   0x00000004L
+#define VGT_DEBUG_REG0__vr_grp_busy                        0x00000004L
+#define VGT_DEBUG_REG0__dma_request_busy_MASK              0x00000008L
+#define VGT_DEBUG_REG0__dma_request_busy                   0x00000008L
+#define VGT_DEBUG_REG0__out_busy_MASK                      0x00000010L
+#define VGT_DEBUG_REG0__out_busy                           0x00000010L
+#define VGT_DEBUG_REG0__grp_backend_busy_MASK              0x00000020L
+#define VGT_DEBUG_REG0__grp_backend_busy                   0x00000020L
+#define VGT_DEBUG_REG0__grp_busy_MASK                      0x00000040L
+#define VGT_DEBUG_REG0__grp_busy                           0x00000040L
+#define VGT_DEBUG_REG0__dma_busy_MASK                      0x00000080L
+#define VGT_DEBUG_REG0__dma_busy                           0x00000080L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK         0x00000100L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy              0x00000100L
+#define VGT_DEBUG_REG0__rbiu_busy_MASK                     0x00000200L
+#define VGT_DEBUG_REG0__rbiu_busy                          0x00000200L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK      0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended           0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK               0x00000800L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy                    0x00000800L
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK             0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_extended                  0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_MASK                      0x00002000L
+#define VGT_DEBUG_REG0__vgt_busy                           0x00002000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK       0x00004000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out            0x00004000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK          0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy               0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK                 0x00010000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy                      0x00010000L
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read_MASK              0x00000001L
+#define VGT_DEBUG_REG1__out_te_data_read                   0x00000001L
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK             0x00000002L
+#define VGT_DEBUG_REG1__te_out_data_valid                  0x00000002L
+#define VGT_DEBUG_REG1__out_pt_prim_read_MASK              0x00000004L
+#define VGT_DEBUG_REG1__out_pt_prim_read                   0x00000004L
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK             0x00000008L
+#define VGT_DEBUG_REG1__pt_out_prim_valid                  0x00000008L
+#define VGT_DEBUG_REG1__out_pt_data_read_MASK              0x00000010L
+#define VGT_DEBUG_REG1__out_pt_data_read                   0x00000010L
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK             0x00000020L
+#define VGT_DEBUG_REG1__pt_out_indx_valid                  0x00000020L
+#define VGT_DEBUG_REG1__out_vr_prim_read_MASK              0x00000040L
+#define VGT_DEBUG_REG1__out_vr_prim_read                   0x00000040L
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK             0x00000080L
+#define VGT_DEBUG_REG1__vr_out_prim_valid                  0x00000080L
+#define VGT_DEBUG_REG1__out_vr_indx_read_MASK              0x00000100L
+#define VGT_DEBUG_REG1__out_vr_indx_read                   0x00000100L
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK             0x00000200L
+#define VGT_DEBUG_REG1__vr_out_indx_valid                  0x00000200L
+#define VGT_DEBUG_REG1__te_grp_read_MASK                   0x00000400L
+#define VGT_DEBUG_REG1__te_grp_read                        0x00000400L
+#define VGT_DEBUG_REG1__grp_te_valid_MASK                  0x00000800L
+#define VGT_DEBUG_REG1__grp_te_valid                       0x00000800L
+#define VGT_DEBUG_REG1__pt_grp_read_MASK                   0x00001000L
+#define VGT_DEBUG_REG1__pt_grp_read                        0x00001000L
+#define VGT_DEBUG_REG1__grp_pt_valid_MASK                  0x00002000L
+#define VGT_DEBUG_REG1__grp_pt_valid                       0x00002000L
+#define VGT_DEBUG_REG1__vr_grp_read_MASK                   0x00004000L
+#define VGT_DEBUG_REG1__vr_grp_read                        0x00004000L
+#define VGT_DEBUG_REG1__grp_vr_valid_MASK                  0x00008000L
+#define VGT_DEBUG_REG1__grp_vr_valid                       0x00008000L
+#define VGT_DEBUG_REG1__grp_dma_read_MASK                  0x00010000L
+#define VGT_DEBUG_REG1__grp_dma_read                       0x00010000L
+#define VGT_DEBUG_REG1__dma_grp_valid_MASK                 0x00020000L
+#define VGT_DEBUG_REG1__dma_grp_valid                      0x00020000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK              0x00040000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read                   0x00040000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK             0x00080000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid                  0x00080000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK                    0x00100000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr                         0x00100000L
+#define VGT_DEBUG_REG1__VGT_MH_send_MASK                   0x00200000L
+#define VGT_DEBUG_REG1__VGT_MH_send                        0x00200000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK             0x00400000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr                  0x00400000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK            0x00800000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send                 0x00800000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK             0x01000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr                  0x01000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK            0x02000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send                 0x02000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK             0x04000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr                  0x04000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK            0x08000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send                 0x08000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK                    0x10000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr                         0x10000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send_MASK                   0x20000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send                        0x20000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK                0x40000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q                     0x40000000L
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en_MASK                    0x00000001L
+#define VGT_DEBUG_REG3__vgt_clk_en                         0x00000001L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK              0x00000002L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en                   0x00000002L
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK          0x0000001fL
+#define VGT_DEBUG_REG6__right_word_indx_q_MASK             0x000003e0L
+#define VGT_DEBUG_REG6__input_data_valid_MASK              0x00000400L
+#define VGT_DEBUG_REG6__input_data_valid                   0x00000400L
+#define VGT_DEBUG_REG6__input_data_xfer_MASK               0x00000800L
+#define VGT_DEBUG_REG6__input_data_xfer                    0x00000800L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK        0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q             0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK        0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d             0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK    0x00004000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d         0x00004000L
+#define VGT_DEBUG_REG6__space_avail_from_shift_MASK        0x00008000L
+#define VGT_DEBUG_REG6__space_avail_from_shift             0x00008000L
+#define VGT_DEBUG_REG6__shifter_first_load_MASK            0x00010000L
+#define VGT_DEBUG_REG6__shifter_first_load                 0x00010000L
+#define VGT_DEBUG_REG6__di_state_sel_q_MASK                0x00020000L
+#define VGT_DEBUG_REG6__di_state_sel_q                     0x00020000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q   0x00040000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK         0x00080000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q              0x00080000L
+#define VGT_DEBUG_REG6__di_event_flag_q_MASK               0x00100000L
+#define VGT_DEBUG_REG6__di_event_flag_q                    0x00100000L
+#define VGT_DEBUG_REG6__read_draw_initiator_MASK           0x00200000L
+#define VGT_DEBUG_REG6__read_draw_initiator                0x00200000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK   0x00400000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter        0x00400000L
+#define VGT_DEBUG_REG6__last_shift_of_packet_MASK          0x00800000L
+#define VGT_DEBUG_REG6__last_shift_of_packet               0x00800000L
+#define VGT_DEBUG_REG6__last_decr_of_packet_MASK           0x01000000L
+#define VGT_DEBUG_REG6__last_decr_of_packet                0x01000000L
+#define VGT_DEBUG_REG6__extract_vector_MASK                0x02000000L
+#define VGT_DEBUG_REG6__extract_vector                     0x02000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr_MASK                0x04000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr                     0x04000000L
+#define VGT_DEBUG_REG6__destination_rtr_MASK               0x08000000L
+#define VGT_DEBUG_REG6__destination_rtr                    0x08000000L
+#define VGT_DEBUG_REG6__grp_trigger_MASK                   0x10000000L
+#define VGT_DEBUG_REG6__grp_trigger                        0x10000000L
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q_MASK            0x0000ffffL
+#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK       0x000f0000L
+#define VGT_DEBUG_REG7__shift_amount_extract_MASK          0x00f00000L
+#define VGT_DEBUG_REG7__di_prim_type_q_MASK                0x3f000000L
+#define VGT_DEBUG_REG7__current_source_sel_MASK            0xc0000000L
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel_MASK            0x00000003L
+#define VGT_DEBUG_REG8__left_word_indx_q_MASK              0x0000007cL
+#define VGT_DEBUG_REG8__input_data_cnt_MASK                0x00000f80L
+#define VGT_DEBUG_REG8__input_data_lsw_MASK                0x0001f000L
+#define VGT_DEBUG_REG8__input_data_msw_MASK                0x003e0000L
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q_MASK                 0x0000001fL
+#define VGT_DEBUG_REG9__next_stride_d_MASK                 0x000003e0L
+#define VGT_DEBUG_REG9__current_shift_q_MASK               0x00007c00L
+#define VGT_DEBUG_REG9__current_shift_d_MASK               0x000f8000L
+#define VGT_DEBUG_REG9__current_stride_q_MASK              0x01f00000L
+#define VGT_DEBUG_REG9__current_stride_d_MASK              0x3e000000L
+#define VGT_DEBUG_REG9__grp_trigger_MASK                   0x40000000L
+#define VGT_DEBUG_REG9__grp_trigger                        0x40000000L
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0      0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0    0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0    0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L
+#define VGT_DEBUG_REG10__di_state_sel_q_MASK               0x00000010L
+#define VGT_DEBUG_REG10__di_state_sel_q                    0x00000010L
+#define VGT_DEBUG_REG10__last_decr_of_packet_MASK          0x00000020L
+#define VGT_DEBUG_REG10__last_decr_of_packet               0x00000020L
+#define VGT_DEBUG_REG10__bin_valid_MASK                    0x00000040L
+#define VGT_DEBUG_REG10__bin_valid                         0x00000040L
+#define VGT_DEBUG_REG10__read_block_MASK                   0x00000080L
+#define VGT_DEBUG_REG10__read_block                        0x00000080L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK       0x00000100L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read            0x00000100L
+#define VGT_DEBUG_REG10__last_bit_enable_q_MASK            0x00000200L
+#define VGT_DEBUG_REG10__last_bit_enable_q                 0x00000200L
+#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK            0x00000400L
+#define VGT_DEBUG_REG10__last_bit_end_di_q                 0x00000400L
+#define VGT_DEBUG_REG10__selected_data_MASK                0x0007f800L
+#define VGT_DEBUG_REG10__mask_input_data_MASK              0x07f80000L
+#define VGT_DEBUG_REG10__gap_q_MASK                        0x08000000L
+#define VGT_DEBUG_REG10__gap_q                             0x08000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK            0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z                 0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK            0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y                 0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK            0x40000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x                 0x40000000L
+#define VGT_DEBUG_REG10__grp_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG10__grp_trigger                       0x80000000L
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK         0x0000001fL
+#define VGT_DEBUG_REG12__right_word_indx_q_MASK            0x000003e0L
+#define VGT_DEBUG_REG12__input_data_valid_MASK             0x00000400L
+#define VGT_DEBUG_REG12__input_data_valid                  0x00000400L
+#define VGT_DEBUG_REG12__input_data_xfer_MASK              0x00000800L
+#define VGT_DEBUG_REG12__input_data_xfer                   0x00000800L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK       0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q            0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK       0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d            0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK   0x00004000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d        0x00004000L
+#define VGT_DEBUG_REG12__space_avail_from_shift_MASK       0x00008000L
+#define VGT_DEBUG_REG12__space_avail_from_shift            0x00008000L
+#define VGT_DEBUG_REG12__shifter_first_load_MASK           0x00010000L
+#define VGT_DEBUG_REG12__shifter_first_load                0x00010000L
+#define VGT_DEBUG_REG12__di_state_sel_q_MASK               0x00020000L
+#define VGT_DEBUG_REG12__di_state_sel_q                    0x00020000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q  0x00040000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK        0x00080000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q             0x00080000L
+#define VGT_DEBUG_REG12__di_event_flag_q_MASK              0x00100000L
+#define VGT_DEBUG_REG12__di_event_flag_q                   0x00100000L
+#define VGT_DEBUG_REG12__read_draw_initiator_MASK          0x00200000L
+#define VGT_DEBUG_REG12__read_draw_initiator               0x00200000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK  0x00400000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter       0x00400000L
+#define VGT_DEBUG_REG12__last_shift_of_packet_MASK         0x00800000L
+#define VGT_DEBUG_REG12__last_shift_of_packet              0x00800000L
+#define VGT_DEBUG_REG12__last_decr_of_packet_MASK          0x01000000L
+#define VGT_DEBUG_REG12__last_decr_of_packet               0x01000000L
+#define VGT_DEBUG_REG12__extract_vector_MASK               0x02000000L
+#define VGT_DEBUG_REG12__extract_vector                    0x02000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr_MASK               0x04000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr                    0x04000000L
+#define VGT_DEBUG_REG12__destination_rtr_MASK              0x08000000L
+#define VGT_DEBUG_REG12__destination_rtr                   0x08000000L
+#define VGT_DEBUG_REG12__bgrp_trigger_MASK                 0x10000000L
+#define VGT_DEBUG_REG12__bgrp_trigger                      0x10000000L
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q_MASK           0x0000ffffL
+#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK      0x000f0000L
+#define VGT_DEBUG_REG13__shift_amount_extract_MASK         0x00f00000L
+#define VGT_DEBUG_REG13__di_prim_type_q_MASK               0x3f000000L
+#define VGT_DEBUG_REG13__current_source_sel_MASK           0xc0000000L
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel_MASK           0x00000003L
+#define VGT_DEBUG_REG14__left_word_indx_q_MASK             0x0000007cL
+#define VGT_DEBUG_REG14__input_data_cnt_MASK               0x00000f80L
+#define VGT_DEBUG_REG14__input_data_lsw_MASK               0x0001f000L
+#define VGT_DEBUG_REG14__input_data_msw_MASK               0x003e0000L
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q_MASK                0x0000001fL
+#define VGT_DEBUG_REG15__next_stride_d_MASK                0x000003e0L
+#define VGT_DEBUG_REG15__current_shift_q_MASK              0x00007c00L
+#define VGT_DEBUG_REG15__current_shift_d_MASK              0x000f8000L
+#define VGT_DEBUG_REG15__current_stride_q_MASK             0x01f00000L
+#define VGT_DEBUG_REG15__current_stride_d_MASK             0x3e000000L
+#define VGT_DEBUG_REG15__bgrp_trigger_MASK                 0x40000000L
+#define VGT_DEBUG_REG15__bgrp_trigger                      0x40000000L
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK    0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full         0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK   0x00000002L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty        0x00000002L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK     0x00000004L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read          0x00000004L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK      0x00000008L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we           0x00000008L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK     0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full          0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK    0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty         0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK     0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q          0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK       0x00000080L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we            0x00000080L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK           0x00000100L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill                0x00000100L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK           0x00000200L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid                0x00000200L
+#define VGT_DEBUG_REG16__rst_last_bit_MASK                 0x00000400L
+#define VGT_DEBUG_REG16__rst_last_bit                      0x00000400L
+#define VGT_DEBUG_REG16__current_state_q_MASK              0x00000800L
+#define VGT_DEBUG_REG16__current_state_q                   0x00000800L
+#define VGT_DEBUG_REG16__old_state_q_MASK                  0x00001000L
+#define VGT_DEBUG_REG16__old_state_q                       0x00001000L
+#define VGT_DEBUG_REG16__old_state_en_MASK                 0x00002000L
+#define VGT_DEBUG_REG16__old_state_en                      0x00002000L
+#define VGT_DEBUG_REG16__prev_last_bit_q_MASK              0x00004000L
+#define VGT_DEBUG_REG16__prev_last_bit_q                   0x00004000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK               0x00008000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q                    0x00008000L
+#define VGT_DEBUG_REG16__last_bit_block_q_MASK             0x00010000L
+#define VGT_DEBUG_REG16__last_bit_block_q                  0x00010000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK             0x00020000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q                  0x00020000L
+#define VGT_DEBUG_REG16__load_empty_reg_MASK               0x00040000L
+#define VGT_DEBUG_REG16__load_empty_reg                    0x00040000L
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK     0x07f80000L
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK  0x18000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable      0x20000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK     0x40000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q          0x40000000L
+#define VGT_DEBUG_REG16__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG16__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q_MASK                  0x00000001L
+#define VGT_DEBUG_REG17__save_read_q                       0x00000001L
+#define VGT_DEBUG_REG17__extend_read_q_MASK                0x00000002L
+#define VGT_DEBUG_REG17__extend_read_q                     0x00000002L
+#define VGT_DEBUG_REG17__grp_indx_size_MASK                0x0000000cL
+#define VGT_DEBUG_REG17__cull_prim_true_MASK               0x00000010L
+#define VGT_DEBUG_REG17__cull_prim_true                    0x00000010L
+#define VGT_DEBUG_REG17__reset_bit2_q_MASK                 0x00000020L
+#define VGT_DEBUG_REG17__reset_bit2_q                      0x00000020L
+#define VGT_DEBUG_REG17__reset_bit1_q_MASK                 0x00000040L
+#define VGT_DEBUG_REG17__reset_bit1_q                      0x00000040L
+#define VGT_DEBUG_REG17__first_reg_first_q_MASK            0x00000080L
+#define VGT_DEBUG_REG17__first_reg_first_q                 0x00000080L
+#define VGT_DEBUG_REG17__check_second_reg_MASK             0x00000100L
+#define VGT_DEBUG_REG17__check_second_reg                  0x00000100L
+#define VGT_DEBUG_REG17__check_first_reg_MASK              0x00000200L
+#define VGT_DEBUG_REG17__check_first_reg                   0x00000200L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK   0x00000400L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata        0x00000400L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK      0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q           0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK      0x00001000L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q           0x00001000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK       0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q            0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK       0x00004000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q            0x00004000L
+#define VGT_DEBUG_REG17__to_second_reg_q_MASK              0x00008000L
+#define VGT_DEBUG_REG17__to_second_reg_q                   0x00008000L
+#define VGT_DEBUG_REG17__roll_over_msk_q_MASK              0x00010000L
+#define VGT_DEBUG_REG17__roll_over_msk_q                   0x00010000L
+#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK                0x00fe0000L
+#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK                0x7f000000L
+#define VGT_DEBUG_REG17__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG17__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK      0x0000003fL
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK      0x00000fc0L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK   0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re        0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK  0x00006000L
+#define VGT_DEBUG_REG18__dma_mem_full_MASK                 0x00008000L
+#define VGT_DEBUG_REG18__dma_mem_full                      0x00008000L
+#define VGT_DEBUG_REG18__dma_ram_re_MASK                   0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_re                        0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_we_MASK                   0x00020000L
+#define VGT_DEBUG_REG18__dma_ram_we                        0x00020000L
+#define VGT_DEBUG_REG18__dma_mem_empty_MASK                0x00040000L
+#define VGT_DEBUG_REG18__dma_mem_empty                     0x00040000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK         0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re              0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK         0x00100000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we              0x00100000L
+#define VGT_DEBUG_REG18__bin_mem_full_MASK                 0x00200000L
+#define VGT_DEBUG_REG18__bin_mem_full                      0x00200000L
+#define VGT_DEBUG_REG18__bin_ram_we_MASK                   0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_we                        0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_re_MASK                   0x00800000L
+#define VGT_DEBUG_REG18__bin_ram_re                        0x00800000L
+#define VGT_DEBUG_REG18__bin_mem_empty_MASK                0x01000000L
+#define VGT_DEBUG_REG18__bin_mem_empty                     0x01000000L
+#define VGT_DEBUG_REG18__start_bin_req_MASK                0x02000000L
+#define VGT_DEBUG_REG18__start_bin_req                     0x02000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK          0x04000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used               0x04000000L
+#define VGT_DEBUG_REG18__dma_req_xfer_MASK                 0x08000000L
+#define VGT_DEBUG_REG18__dma_req_xfer                      0x08000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req_MASK           0x10000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req                0x10000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req_MASK           0x20000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req                0x20000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK  0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable       0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK         0x00000001L
+#define VGT_DEBUG_REG20__prim_side_indx_valid              0x00000001L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK         0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty              0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK            0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_re                 0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK            0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_we                 0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK          0x00000010L
+#define VGT_DEBUG_REG20__indx_side_fifo_full               0x00000010L
+#define VGT_DEBUG_REG20__prim_buffer_empty_MASK            0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_empty                 0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_re_MASK               0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_re                    0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_we_MASK               0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_we                    0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_full_MASK             0x00000100L
+#define VGT_DEBUG_REG20__prim_buffer_full                  0x00000100L
+#define VGT_DEBUG_REG20__indx_buffer_empty_MASK            0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_empty                 0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_re_MASK               0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_re                    0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_we_MASK               0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_we                    0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_full_MASK             0x00001000L
+#define VGT_DEBUG_REG20__indx_buffer_full                  0x00001000L
+#define VGT_DEBUG_REG20__hold_prim_MASK                    0x00002000L
+#define VGT_DEBUG_REG20__hold_prim                         0x00002000L
+#define VGT_DEBUG_REG20__sent_cnt_MASK                     0x0003c000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK          0x00040000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector               0x00040000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK         0x00080000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim              0x00080000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK         0x00100000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim              0x00100000L
+#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK     0x03e00000L
+#define VGT_DEBUG_REG20__out_trigger_MASK                  0x04000000L
+#define VGT_DEBUG_REG20__out_trigger                       0x04000000L
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK    0x00000001L
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector         0x00000001L
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK   0x0000000eL
+#define VGT_DEBUG_REG21__alloc_counter_q_MASK              0x00000070L
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK      0x00000380L
+#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK            0x00003c00L
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK      0x0003c000L
+#define VGT_DEBUG_REG21__new_packet_q_MASK                 0x00040000L
+#define VGT_DEBUG_REG21__new_packet_q                      0x00040000L
+#define VGT_DEBUG_REG21__new_allocate_q_MASK               0x00080000L
+#define VGT_DEBUG_REG21__new_allocate_q                    0x00080000L
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK      0x00300000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK         0x00400000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q              0x00400000L
+#define VGT_DEBUG_REG21__insert_null_prim_MASK             0x00800000L
+#define VGT_DEBUG_REG21__insert_null_prim                  0x00800000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK        0x01000000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux             0x01000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK        0x02000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux             0x02000000L
+#define VGT_DEBUG_REG21__buffered_thread_size_MASK         0x04000000L
+#define VGT_DEBUG_REG21__buffered_thread_size              0x04000000L
+#define VGT_DEBUG_REG21__out_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG21__out_trigger                       0x80000000L
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC_MASK                          0xffffffffL
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC_MASK                          0xffffffffL
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE_MASK                 0x00000001L
+#define TC_CNTL_STATUS__L2_INVALIDATE                      0x00000001L
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK                0x000c0000L
+#define TC_CNTL_STATUS__TC_BUSY_MASK                       0x80000000L
+#define TC_CNTL_STATUS__TC_BUSY                            0x80000000L
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK                 0x00000100L
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN                      0x00000100L
+#define TCM_CHICKEN__SPARE_MASK                            0xfffffe00L
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK            0x00000007L
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK            0x00000038L
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK               0x00000001L
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY                    0x00000001L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK             0x00000002L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY                  0x00000002L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK          0x00000004L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY               0x00000004L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK          0x00000008L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY               0x00000008L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK         0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY              0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK           0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY                0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK              0x00000040L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY                   0x00000040L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK        0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY             0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK          0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY               0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK             0x00000400L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY                  0x00000400L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK             0x00001000L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY                  0x00001000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK          0x00002000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY               0x00002000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK            0x00004000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY                 0x00004000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK               0x00008000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY                    0x00008000L
+#define TPC_CNTL_STATUS__TF_TW_RTS_MASK                    0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_RTS                         0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK              0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS                   0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_RTR_MASK                    0x00080000L
+#define TPC_CNTL_STATUS__TF_TW_RTR                         0x00080000L
+#define TPC_CNTL_STATUS__TW_TA_RTS_MASK                    0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_RTS                         0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK                 0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS                      0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK               0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS                    0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_RTR_MASK                    0x00800000L
+#define TPC_CNTL_STATUS__TW_TA_RTR                         0x00800000L
+#define TPC_CNTL_STATUS__TA_TB_RTS_MASK                    0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_RTS                         0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK                 0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS                      0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR_MASK                    0x08000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR                         0x08000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS_MASK                    0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS                         0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK            0x20000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN                 0x20000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK                    0x40000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC                         0x40000000L
+#define TPC_CNTL_STATUS__TPC_BUSY_MASK                     0x80000000L
+#define TPC_CNTL_STATUS__TPC_BUSY                          0x80000000L
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL_MASK                          0x00000003L
+#define TPC_DEBUG0__IC_CTR_MASK                            0x0000000cL
+#define TPC_DEBUG0__WALKER_CNTL_MASK                       0x000000f0L
+#define TPC_DEBUG0__ALIGNER_CNTL_MASK                      0x00000700L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK               0x00001000L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID                    0x00001000L
+#define TPC_DEBUG0__WALKER_STATE_MASK                      0x03ff0000L
+#define TPC_DEBUG0__ALIGNER_STATE_MASK                     0x0c000000L
+#define TPC_DEBUG0__REG_CLK_EN_MASK                        0x20000000L
+#define TPC_DEBUG0__REG_CLK_EN                             0x20000000L
+#define TPC_DEBUG0__TPC_CLK_EN_MASK                        0x40000000L
+#define TPC_DEBUG0__TPC_CLK_EN                             0x40000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK                      0x80000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP                           0x80000000L
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED_MASK                            0x00000001L
+#define TPC_DEBUG1__UNUSED                                 0x00000001L
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION_MASK                  0x00000001L
+#define TPC_CHICKEN__BLEND_PRECISION                       0x00000001L
+#define TPC_CHICKEN__SPARE_MASK                            0xfffffffeL
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK                0x00000001L
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY                     0x00000001L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK                  0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY                       0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK             0x00000004L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY                  0x00000004L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK                 0x00000008L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY                      0x00000008L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK           0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY                0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK              0x00000020L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY                   0x00000020L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK              0x00000040L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY                   0x00000040L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK              0x00000080L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY                   0x00000080L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK                0x00000100L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY                     0x00000100L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK             0x00000200L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY                  0x00000200L
+#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK                   0x00000400L
+#define TP0_CNTL_STATUS__TP_TT_BUSY                        0x00000400L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK              0x00000800L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY                   0x00000800L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK                0x00001000L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY                     0x00001000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK             0x00002000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY                  0x00002000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK               0x00004000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY                    0x00004000L
+#define TP0_CNTL_STATUS__IN_LC_RTS_MASK                    0x00010000L
+#define TP0_CNTL_STATUS__IN_LC_RTS                         0x00010000L
+#define TP0_CNTL_STATUS__LC_LA_RTS_MASK                    0x00020000L
+#define TP0_CNTL_STATUS__LC_LA_RTS                         0x00020000L
+#define TP0_CNTL_STATUS__LA_FL_RTS_MASK                    0x00040000L
+#define TP0_CNTL_STATUS__LA_FL_RTS                         0x00040000L
+#define TP0_CNTL_STATUS__FL_TA_RTS_MASK                    0x00080000L
+#define TP0_CNTL_STATUS__FL_TA_RTS                         0x00080000L
+#define TP0_CNTL_STATUS__TA_FA_RTS_MASK                    0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_RTS                         0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK                 0x00200000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS                      0x00200000L
+#define TP0_CNTL_STATUS__FA_AL_RTS_MASK                    0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_RTS                         0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK                 0x00800000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS                      0x00800000L
+#define TP0_CNTL_STATUS__AL_TF_RTS_MASK                    0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_RTS                         0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK                 0x02000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS                      0x02000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS_MASK                    0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS                         0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK                 0x08000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS                      0x08000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS_MASK                    0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS                         0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK               0x20000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET                    0x20000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS_MASK                    0x40000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS                         0x40000000L
+#define TP0_CNTL_STATUS__TP_BUSY_MASK                      0x80000000L
+#define TP0_CNTL_STATUS__TP_BUSY                           0x80000000L
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL_MASK                         0x00000003L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK                     0x00000008L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP                          0x00000008L
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK               0x001ffff0L
+#define TP0_DEBUG__REG_CLK_EN_MASK                         0x00200000L
+#define TP0_DEBUG__REG_CLK_EN                              0x00200000L
+#define TP0_DEBUG__PERF_CLK_EN_MASK                        0x00400000L
+#define TP0_DEBUG__PERF_CLK_EN                             0x00400000L
+#define TP0_DEBUG__TP_CLK_EN_MASK                          0x00800000L
+#define TP0_DEBUG__TP_CLK_EN                               0x00800000L
+#define TP0_DEBUG__Q_WALKER_CNTL_MASK                      0x0f000000L
+#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK                     0x70000000L
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE_MASK                          0x00000001L
+#define TP0_CHICKEN__TT_MODE                               0x00000001L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK              0x00000002L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE                   0x00000002L
+#define TP0_CHICKEN__SPARE_MASK                            0xfffffffcL
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr_MASK                      0x00000040L
+#define TCF_DEBUG__not_MH_TC_rtr                           0x00000040L
+#define TCF_DEBUG__TC_MH_send_MASK                         0x00000080L
+#define TCF_DEBUG__TC_MH_send                              0x00000080L
+#define TCF_DEBUG__not_FG0_rtr_MASK                        0x00000100L
+#define TCF_DEBUG__not_FG0_rtr                             0x00000100L
+#define TCF_DEBUG__not_TCB_TCO_rtr_MASK                    0x00001000L
+#define TCF_DEBUG__not_TCB_TCO_rtr                         0x00001000L
+#define TCF_DEBUG__TCB_ff_stall_MASK                       0x00002000L
+#define TCF_DEBUG__TCB_ff_stall                            0x00002000L
+#define TCF_DEBUG__TCB_miss_stall_MASK                     0x00004000L
+#define TCF_DEBUG__TCB_miss_stall                          0x00004000L
+#define TCF_DEBUG__TCA_TCB_stall_MASK                      0x00008000L
+#define TCF_DEBUG__TCA_TCB_stall                           0x00008000L
+#define TCF_DEBUG__PF0_stall_MASK                          0x00010000L
+#define TCF_DEBUG__PF0_stall                               0x00010000L
+#define TCF_DEBUG__TP0_full_MASK                           0x00100000L
+#define TCF_DEBUG__TP0_full                                0x00100000L
+#define TCF_DEBUG__TPC_full_MASK                           0x01000000L
+#define TCF_DEBUG__TPC_full                                0x01000000L
+#define TCF_DEBUG__not_TPC_rtr_MASK                        0x02000000L
+#define TCF_DEBUG__not_TPC_rtr                             0x02000000L
+#define TCF_DEBUG__tca_state_rts_MASK                      0x04000000L
+#define TCF_DEBUG__tca_state_rts                           0x04000000L
+#define TCF_DEBUG__tca_rts_MASK                            0x08000000L
+#define TCF_DEBUG__tca_rts                                 0x08000000L
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full_MASK                      0x00000001L
+#define TCA_FIFO_DEBUG__tp0_full                           0x00000001L
+#define TCA_FIFO_DEBUG__tpc_full_MASK                      0x00000010L
+#define TCA_FIFO_DEBUG__tpc_full                           0x00000010L
+#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK                 0x00000020L
+#define TCA_FIFO_DEBUG__load_tpc_fifo                      0x00000020L
+#define TCA_FIFO_DEBUG__load_tp_fifos_MASK                 0x00000040L
+#define TCA_FIFO_DEBUG__load_tp_fifos                      0x00000040L
+#define TCA_FIFO_DEBUG__FW_full_MASK                       0x00000080L
+#define TCA_FIFO_DEBUG__FW_full                            0x00000080L
+#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK                   0x00000100L
+#define TCA_FIFO_DEBUG__not_FW_rtr0                        0x00000100L
+#define TCA_FIFO_DEBUG__FW_rts0_MASK                       0x00001000L
+#define TCA_FIFO_DEBUG__FW_rts0                            0x00001000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK                0x00010000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr                     0x00010000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK                    0x00020000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts                         0x00020000L
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK            0x00000001L
+#define TCA_PROBE_DEBUG__ProbeFilter_stall                 0x00000001L
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts_MASK               0x00001000L
+#define TCA_TPC_DEBUG__captue_state_rts                    0x00001000L
+#define TCA_TPC_DEBUG__capture_tca_rts_MASK                0x00002000L
+#define TCA_TPC_DEBUG__capture_tca_rts                     0x00002000L
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512_MASK                     0x00000001L
+#define TCB_CORE_DEBUG__access512                          0x00000001L
+#define TCB_CORE_DEBUG__tiled_MASK                         0x00000002L
+#define TCB_CORE_DEBUG__tiled                              0x00000002L
+#define TCB_CORE_DEBUG__opcode_MASK                        0x00000070L
+#define TCB_CORE_DEBUG__format_MASK                        0x00003f00L
+#define TCB_CORE_DEBUG__sector_format_MASK                 0x001f0000L
+#define TCB_CORE_DEBUG__sector_format512_MASK              0x07000000L
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG0_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG0_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG0_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG0_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG0_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG1_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG1_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG1_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG1_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG1_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG2_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG2_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG2_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG2_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG2_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG3_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG3_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG3_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG3_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG3_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done      0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left    0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q   0x10000000L
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK     0x00000030L
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK      0x000000c0L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK     0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left          0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK     0x00007000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK              0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy                   0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK  0x000f0000L
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK        0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts             0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK         0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts              0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK      0x0000fff0L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK   0x001f0000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK               0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy                    0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK           0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy                0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK            0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy                 0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK           0x0c000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK            0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q                 0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK            0x40000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR                 0x40000000L
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty_MASK                       0x00010000L
+#define TCD_INPUT0_DEBUG__empty                            0x00010000L
+#define TCD_INPUT0_DEBUG__full_MASK                        0x00020000L
+#define TCD_INPUT0_DEBUG__full                             0x00020000L
+#define TCD_INPUT0_DEBUG__valid_q1_MASK                    0x00100000L
+#define TCD_INPUT0_DEBUG__valid_q1                         0x00100000L
+#define TCD_INPUT0_DEBUG__cnt_q1_MASK                      0x00600000L
+#define TCD_INPUT0_DEBUG__last_send_q1_MASK                0x00800000L
+#define TCD_INPUT0_DEBUG__last_send_q1                     0x00800000L
+#define TCD_INPUT0_DEBUG__ip_send_MASK                     0x01000000L
+#define TCD_INPUT0_DEBUG__ip_send                          0x01000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK              0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send                   0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK                  0x04000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy                       0x04000000L
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK        0x00000003L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK            0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8                 0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK        0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send             0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK             0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send                  0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK                 0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall                      0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK                0x00000040L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate                     0x00000040L
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK               0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate                    0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK           0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr                0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK             0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr                  0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send      0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK  0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts       0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK    0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send         0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send     0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK     0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send          0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK        0x20000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send             0x20000000L
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK                  0x00000010L
+#define TCD_DXTC_ARB_DEBUG__n0_stall                       0x00000010L
+#define TCD_DXTC_ARB_DEBUG__pstate_MASK                    0x00000020L
+#define TCD_DXTC_ARB_DEBUG__pstate                         0x00000020L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK      0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send           0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK            0x00000180L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK         0x00000e00L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK      0x0003f000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK         0x3ffc0000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK           0x40000000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send                0x40000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK           0x80000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types                0x80000000L
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK     0x00000400L
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr          0x00000400L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK     0x00000800L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr          0x00000800L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK           0x00020000L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr                0x00020000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK         0x00040000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr              0x00040000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK            0x00080000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr                 0x00080000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK            0x80000000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr                 0x80000000L
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK            0x00000020L
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR                 0x00000020L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK             0x00000040L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR                  0x00000040L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK         0x00000080L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d              0x00000080L
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK         0x000000ffL
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK         0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample              0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK                   0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr                        0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK                   0x00000400L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts                        0x00000400L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK        0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample             0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK                  0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr                       0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK                  0x00002000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts                       0x00002000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK             0x00010000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q                  0x00010000L
+#define TCO_QUAD0_DEBUG0__read_cache_q_MASK                0x01000000L
+#define TCO_QUAD0_DEBUG0__read_cache_q                     0x01000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK              0x02000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR                   0x02000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK    0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3         0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK    0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2         0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK    0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1         0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK    0x20000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0         0x20000000L
+#define TCO_QUAD0_DEBUG0__busy_MASK                        0x40000000L
+#define TCO_QUAD0_DEBUG0__busy                             0x40000000L
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy_MASK                   0x00000001L
+#define TCO_QUAD0_DEBUG1__fifo_busy                        0x00000001L
+#define TCO_QUAD0_DEBUG1__empty_MASK                       0x00000002L
+#define TCO_QUAD0_DEBUG1__empty                            0x00000002L
+#define TCO_QUAD0_DEBUG1__full_MASK                        0x00000004L
+#define TCO_QUAD0_DEBUG1__full                             0x00000004L
+#define TCO_QUAD0_DEBUG1__write_enable_MASK                0x00000008L
+#define TCO_QUAD0_DEBUG1__write_enable                     0x00000008L
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK              0x000007f0L
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK               0x0003f800L
+#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK             0x00100000L
+#define TCO_QUAD0_DEBUG1__cache_read_busy                  0x00100000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK           0x00200000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy                0x00200000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK             0x00400000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy                  0x00400000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK          0x00800000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy               0x00800000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK               0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d                    0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK               0x02000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q                    0x02000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK                   0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr                        0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK                   0x08000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts                        0x08000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK                  0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr                       0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK                  0x20000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts                       0x20000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK            0x40000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc                 0x40000000L
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK                0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC                     0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK               0x000007f0L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK               0x0007f000L
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK     0x00000003L
+#define SQ_FLOW_CONTROL__ONE_THREAD_MASK                   0x00000010L
+#define SQ_FLOW_CONTROL__ONE_THREAD                        0x00000010L
+#define SQ_FLOW_CONTROL__ONE_ALU_MASK                      0x00000100L
+#define SQ_FLOW_CONTROL__ONE_ALU                           0x00000100L
+#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK                   0x0000f000L
+#define SQ_FLOW_CONTROL__NO_PV_PS_MASK                     0x00010000L
+#define SQ_FLOW_CONTROL__NO_PV_PS                          0x00010000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK                 0x00020000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT                      0x00020000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK            0x00040000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE                 0x00040000L
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK   0x00180000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK        0x00200000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY             0x00200000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK       0x00400000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY            0x00400000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK                 0x00800000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT                      0x00800000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK                 0x01000000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT                      0x01000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK             0x02000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY                  0x02000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK  0x04000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION       0x04000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK      0x08000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC           0x08000000L
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK        0x00000fffL
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK        0x0fff0000L
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK     0x01ff0000L
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT_MASK                     0x000000ffL
+#define SQ_EO_RT__EO_TSTATE_RT_MASK                        0x00ff0000L
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK                 0x000007ffL
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK                 0x000ff000L
+#define SQ_DEBUG_MISC__DB_READ_CTX_MASK                    0x00100000L
+#define SQ_DEBUG_MISC__DB_READ_CTX                         0x00100000L
+#define SQ_DEBUG_MISC__RESERVED_MASK                       0x00600000L
+#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK                 0x01800000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK                0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0                     0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK                0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1                     0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK                0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2                     0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK                0x10000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3                     0x10000000L
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK              0x000000ffL
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK         0x0000ff00L
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK        0x00ff0000L
+#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK                 0xff000000L
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK        0x000000ffL
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK        0x00000007L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK          0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN               0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK        0x00000070L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK          0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN               0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK              0x0003ff00L
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK       0x00000007L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK         0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN              0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK       0x00000070L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK         0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN              0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK             0x0003ff00L
+#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK              0x000c0000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK  0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL       0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK  0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL       0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK                 0x00000007L
+#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK                  0x00000008L
+#define SQ_DEBUG_INPUT_FSM__RESERVED                       0x00000008L
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK                 0x000000f0L
+#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK                   0x00000700L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1                      0x00000800L
+#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK                     0x00007000L
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK             0x000f8000L
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK               0x0ff00000L
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK             0x000000e0L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK             0x0000e000L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK  0x00030000L
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK  0x000c0000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK  0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE       0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK  0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE       0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK  0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE       0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK  0x00800000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE       0x00800000L
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP_MASK                        0x00000007L
+#define SQ_DEBUG_TP_FSM__RESERVED0_MASK                    0x00000008L
+#define SQ_DEBUG_TP_FSM__RESERVED0                         0x00000008L
+#define SQ_DEBUG_TP_FSM__CF_TP_MASK                        0x000000f0L
+#define SQ_DEBUG_TP_FSM__IF_TP_MASK                        0x00000700L
+#define SQ_DEBUG_TP_FSM__RESERVED1_MASK                    0x00000800L
+#define SQ_DEBUG_TP_FSM__RESERVED1                         0x00000800L
+#define SQ_DEBUG_TP_FSM__TIS_TP_MASK                       0x00003000L
+#define SQ_DEBUG_TP_FSM__RESERVED2_MASK                    0x0000c000L
+#define SQ_DEBUG_TP_FSM__GS_TP_MASK                        0x00030000L
+#define SQ_DEBUG_TP_FSM__RESERVED3_MASK                    0x000c0000L
+#define SQ_DEBUG_TP_FSM__FCR_TP_MASK                       0x00300000L
+#define SQ_DEBUG_TP_FSM__RESERVED4_MASK                    0x00c00000L
+#define SQ_DEBUG_TP_FSM__FCS_TP_MASK                       0x03000000L
+#define SQ_DEBUG_TP_FSM__RESERVED5_MASK                    0x0c000000L
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK                    0x70000000L
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK             0x0000000fL
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK           0x00000ff0L
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK              0x00007000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK                  0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED                       0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK       0x003f0000L
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK              0x00000001L
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER                   0x00000001L
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK                0x0000001eL
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK            0x00000020L
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR                 0x00000020L
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK           0x000001c0L
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK                0x00003e00L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK                 0x00004000L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT                      0x00004000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK          0x00008000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON               0x00008000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK                   0x00010000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY                        0x00010000L
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK               0x0ffe0000L
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_VTX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_VTX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_VTX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_PIX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_PIX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_PIX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN     0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN     0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK     0x60000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC    0x80000000L
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK             0x0000000fL
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK                 0x000000f0L
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK                 0x00000f00L
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK          0x0000f000L
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK           0x000f0000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK              0x00100000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL                   0x00100000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK                     0x00200000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q                          0x00200000L
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK                0x0000ffffL
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK     0xffffffffL
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK       0xffffffffL
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK               0x0000003fL
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK                   0x00000fc0L
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK                   0x0007f000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK          0x01f80000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK            0x7e000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY_MASK                       0x80000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY                            0x80000000L
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK   0xffffffffL
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD_MASK           0x00000040L
+#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD                0x00000040L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK    0x00000080L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP         0x00000080L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD_MASK           0x00004000L
+#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD                0x00004000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK             0x00008000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA                  0x00008000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK          0x000f0000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK          0x00f00000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK            0x01000000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP                 0x01000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK            0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP                 0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK           0xfc000000L
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK         0x00000003L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK         0x0000000cL
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK         0x00000030L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK         0x000000c0L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK         0x00000300L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK         0x00000c00L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK         0x00003000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK         0x0000c000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK         0x00030000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK         0x000c0000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK         0x00300000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK         0x00c00000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK           0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD                0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK           0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD                0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK           0x04000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD                0x04000000L
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK             0x18000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK           0x20000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR                0x20000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK         0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS              0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK         0x80000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS              0x80000000L
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK            0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C                 0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK           0x00000080L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C                0x00000080L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK            0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B                 0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK           0x00008000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B                0x00008000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK           0x003f0000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK            0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A                 0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK           0x00800000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A                0x00800000L
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK           0x1f000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK               0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL                    0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK               0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL                    0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK               0x80000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK             0x000001ffL
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK            0x00000e00L
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK               0x00007000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK               0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD                    0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK         0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0              0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0            0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK         0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1              0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK       0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1            0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK         0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2              0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK       0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2            0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK         0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3              0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK       0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3            0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK         0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4              0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK       0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4            0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK         0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5              0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK       0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5            0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK           0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0                0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK           0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1                0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK           0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2                0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK           0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3                0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK           0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4                0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK           0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5                0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK           0x000003fcL
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK           0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION                0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK             0x01ff0000L
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK            0x0e000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK               0x70000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK               0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK         0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0              0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0            0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK         0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1              0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK       0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1            0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK         0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2              0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK       0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2            0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK         0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3              0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK       0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3            0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK         0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4              0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK       0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4            0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK         0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5              0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK       0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5            0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK           0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0                0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK           0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1                0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK           0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2                0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK           0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3                0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK           0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4                0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK           0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5                0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK           0x03fc0000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK           0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION                0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK             0x000003ffL
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK          0x0000fc00L
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK             0x001f0000L
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK          0xffe00000L
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK          0x000007ffL
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK             0x03ff0000L
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK          0xfc000000L
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK             0x0000001fL
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK            0x07ffffe0L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK         0x000003ffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK      0x00001c00L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK      0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL           0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK  0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP       0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK      0xffff8000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK      0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0           0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION            0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK       0x000003fcL
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK       0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION            0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK    0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE         0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK          0x0000f000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK         0x03ff0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK      0x1c000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK      0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL           0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK      0xc0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK        0x0001ffffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION            0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK       0x03fc0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK       0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION            0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK    0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE         0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK          0xf0000000L
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK               0x0000000fL
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK           0xfffffff0L
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK         0x000000ffL
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK          0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL               0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK      0x00000600L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK         0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE              0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK             0x0000f000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK               0x000f0000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK         0xfff00000L
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK           0x00ffffffL
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK          0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL               0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK      0x06000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK         0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE              0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK             0xf0000000L
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK     0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY          0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK      0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM           0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK            0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK            0x30000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK            0xc0000000L
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK           0x00003000L
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK           0x0000c000L
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK           0x00030000L
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK         0x001c0000L
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK     0x00e00000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK       0x03000000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK       0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK         0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD              0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK          0x60000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK    0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS         0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK      0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION           0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK             0x000001fcL
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK               0x0000fe00L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK             0x001f0000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK             0x03e00000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK             0x7c000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK          0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE               0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK      0x06000000L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK              0xc0000000L
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK      0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL           0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK       0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL            0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK   0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL        0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK          0x003f0000L
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK       0x3f800000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK               0x000000ffL
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK               0x00ff0000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED_MASK                            0xffffffffL
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN_MASK                          0xffffffffL
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE_MASK                           0xffffffffL
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA_MASK                          0xffffffffL
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE_MASK                             0xffffffffL
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE_MASK                    0x00000001L
+#define SQ_CONSTANT_VFETCH_0__TYPE                         0x00000001L
+#define SQ_CONSTANT_VFETCH_0__STATE_MASK                   0x00000002L
+#define SQ_CONSTANT_VFETCH_0__STATE                        0x00000002L
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK            0xfffffffcL
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK             0x00000003L
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK           0xfffffffcL
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE_MASK                         0xffffffffL
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE_MASK                         0xffffffffL
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK                 0x000000ffL
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK                 0x0000ff00L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK                 0x00ff0000L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK                 0xff000000L
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK                     0x000000ffL
+#define SQ_CF_LOOP__CF_LOOP_START_MASK                     0x0000ff00L
+#define SQ_CF_LOOP__CF_LOOP_STEP_MASK                      0x00ff0000L
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED_MASK                         0xffffffffL
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN_MASK                       0xffffffffL
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE_MASK                        0xffffffffL
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA_MASK                       0xffffffffL
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE_MASK                          0xffffffffL
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK              0x000000ffL
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK              0x0000ff00L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK              0x00ff0000L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK              0xff000000L
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK                  0x000000ffL
+#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK                  0x0000ff00L
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK                   0x00ff0000L
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_VS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_PS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK                0x000007ffL
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK                0x007ff000L
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK             0x0000ffffL
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK        0xffff0000L
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK                   0x0000003fL
+#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK                   0x00003f00L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK                  0x00010000L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE                       0x00010000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK                  0x00020000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE                       0x00020000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK                    0x00040000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN                         0x00040000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK                0x00080000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX                     0x00080000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK              0x00f00000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK               0x07000000L
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK               0x78000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK                0x80000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX                     0x80000000L
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK                   0x0000000fL
+#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK                   0x000000f0L
+#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK                   0x00000f00L
+#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK                   0x0000f000L
+#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK                   0x000f0000L
+#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK                   0x00f00000L
+#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK                   0x0f000000L
+#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK                   0xf0000000L
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK                   0x0000000fL
+#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK                   0x000000f0L
+#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK                  0x00000f00L
+#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK                  0x0000f000L
+#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK                  0x000f0000L
+#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK                  0x00f00000L
+#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK                  0x0f000000L
+#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK                  0xf0000000L
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_VS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_PS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK           0x00000001L
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE                0x00000001L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK          0x00000002L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY               0x00000002L
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK               0x0000000cL
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK                0x0000ff00L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK              0x00010000L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF                   0x00010000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK               0x00020000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE                    0x00020000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK                 0x00040000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL                      0x00040000L
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE_MASK                        0x00000007L
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK                   0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_ON                        0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK                0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK                     0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK                 0x0007ff00L
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK                0xff000000L
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK                    0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_PIX                         0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK                    0x00000002L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX                         0x00000002L
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK                0x0000ff00L
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK                0x07ff0000L
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK            0x0000003fL
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK      0x00000040L
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY           0x00000040L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK              0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE                   0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK         0x00000100L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE              0x00000100L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK             0x00000200L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL                  0x00000200L
+#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK                  0x00001c00L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK          0x00002000L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE               0x00002000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK         0x00004000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE              0x00004000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK     0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE          0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK            0x003f0000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK             0x00400000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE                  0x00400000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK            0x00800000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE                 0x00800000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK             0x01000000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE                  0x01000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK             0x02000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE                  0x02000000L
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK                  0x00000007L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK               0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1                    0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK                  0x00000070L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK               0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2                    0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK                 0x00000700L
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK             0x00000001L
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR                  0x00000001L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK            0x00000002L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR                 0x00000002L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK             0x00000004L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT                  0x00000004L
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK           0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR                0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK          0x00000002L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR               0x00000002L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK           0x00000004L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT                0x00000004L
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK            0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR                 0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK           0x00000002L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR                0x00000002L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK            0x00000004L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT                 0x00000004L
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID_MASK                     0x00000007L
+#define MH_AXI_ERROR__AXI_READ_ERROR_MASK                  0x00000008L
+#define MH_AXI_ERROR__AXI_READ_ERROR                       0x00000008L
+#define MH_AXI_ERROR__AXI_WRITE_ID_MASK                    0x00000070L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK                 0x00000080L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR                      0x00000080L
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX_MASK                          0x0000003fL
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA_MASK                           0xffffffffL
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY_MASK                       0x00000001L
+#define MH_DEBUG_REG00__MH_BUSY                            0x00000001L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK             0x00000002L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING                  0x00000002L
+#define MH_DEBUG_REG00__CP_REQUEST_MASK                    0x00000004L
+#define MH_DEBUG_REG00__CP_REQUEST                         0x00000004L
+#define MH_DEBUG_REG00__VGT_REQUEST_MASK                   0x00000008L
+#define MH_DEBUG_REG00__VGT_REQUEST                        0x00000008L
+#define MH_DEBUG_REG00__TC_REQUEST_MASK                    0x00000010L
+#define MH_DEBUG_REG00__TC_REQUEST                         0x00000010L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK                  0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY                       0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_FULL_MASK                   0x00000040L
+#define MH_DEBUG_REG00__TC_CAM_FULL                        0x00000040L
+#define MH_DEBUG_REG00__TCD_EMPTY_MASK                     0x00000080L
+#define MH_DEBUG_REG00__TCD_EMPTY                          0x00000080L
+#define MH_DEBUG_REG00__TCD_FULL_MASK                      0x00000100L
+#define MH_DEBUG_REG00__TCD_FULL                           0x00000100L
+#define MH_DEBUG_REG00__RB_REQUEST_MASK                    0x00000200L
+#define MH_DEBUG_REG00__RB_REQUEST                         0x00000200L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK               0x00000400L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE                    0x00000400L
+#define MH_DEBUG_REG00__ARQ_EMPTY_MASK                     0x00000800L
+#define MH_DEBUG_REG00__ARQ_EMPTY                          0x00000800L
+#define MH_DEBUG_REG00__ARQ_FULL_MASK                      0x00001000L
+#define MH_DEBUG_REG00__ARQ_FULL                           0x00001000L
+#define MH_DEBUG_REG00__WDB_EMPTY_MASK                     0x00002000L
+#define MH_DEBUG_REG00__WDB_EMPTY                          0x00002000L
+#define MH_DEBUG_REG00__WDB_FULL_MASK                      0x00004000L
+#define MH_DEBUG_REG00__WDB_FULL                           0x00004000L
+#define MH_DEBUG_REG00__AXI_AVALID_MASK                    0x00008000L
+#define MH_DEBUG_REG00__AXI_AVALID                         0x00008000L
+#define MH_DEBUG_REG00__AXI_AREADY_MASK                    0x00010000L
+#define MH_DEBUG_REG00__AXI_AREADY                         0x00010000L
+#define MH_DEBUG_REG00__AXI_ARVALID_MASK                   0x00020000L
+#define MH_DEBUG_REG00__AXI_ARVALID                        0x00020000L
+#define MH_DEBUG_REG00__AXI_ARREADY_MASK                   0x00040000L
+#define MH_DEBUG_REG00__AXI_ARREADY                        0x00040000L
+#define MH_DEBUG_REG00__AXI_WVALID_MASK                    0x00080000L
+#define MH_DEBUG_REG00__AXI_WVALID                         0x00080000L
+#define MH_DEBUG_REG00__AXI_WREADY_MASK                    0x00100000L
+#define MH_DEBUG_REG00__AXI_WREADY                         0x00100000L
+#define MH_DEBUG_REG00__AXI_RVALID_MASK                    0x00200000L
+#define MH_DEBUG_REG00__AXI_RVALID                         0x00200000L
+#define MH_DEBUG_REG00__AXI_RREADY_MASK                    0x00400000L
+#define MH_DEBUG_REG00__AXI_RREADY                         0x00400000L
+#define MH_DEBUG_REG00__AXI_BVALID_MASK                    0x00800000L
+#define MH_DEBUG_REG00__AXI_BVALID                         0x00800000L
+#define MH_DEBUG_REG00__AXI_BREADY_MASK                    0x01000000L
+#define MH_DEBUG_REG00__AXI_BREADY                         0x01000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK                  0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ                       0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK                  0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK                       0x04000000L
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q_MASK                     0x00000001L
+#define MH_DEBUG_REG01__CP_SEND_q                          0x00000001L
+#define MH_DEBUG_REG01__CP_RTR_q_MASK                      0x00000002L
+#define MH_DEBUG_REG01__CP_RTR_q                           0x00000002L
+#define MH_DEBUG_REG01__CP_WRITE_q_MASK                    0x00000004L
+#define MH_DEBUG_REG01__CP_WRITE_q                         0x00000004L
+#define MH_DEBUG_REG01__CP_TAG_q_MASK                      0x00000038L
+#define MH_DEBUG_REG01__CP_BE_q_MASK                       0x00003fc0L
+#define MH_DEBUG_REG01__VGT_SEND_q_MASK                    0x00004000L
+#define MH_DEBUG_REG01__VGT_SEND_q                         0x00004000L
+#define MH_DEBUG_REG01__VGT_RTR_q_MASK                     0x00008000L
+#define MH_DEBUG_REG01__VGT_RTR_q                          0x00008000L
+#define MH_DEBUG_REG01__VGT_TAG_q_MASK                     0x00010000L
+#define MH_DEBUG_REG01__VGT_TAG_q                          0x00010000L
+#define MH_DEBUG_REG01__TC_SEND_q_MASK                     0x00020000L
+#define MH_DEBUG_REG01__TC_SEND_q                          0x00020000L
+#define MH_DEBUG_REG01__TC_RTR_q_MASK                      0x00040000L
+#define MH_DEBUG_REG01__TC_RTR_q                           0x00040000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK                 0x00080000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q                      0x00080000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK                  0x00100000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q                       0x00100000L
+#define MH_DEBUG_REG01__TC_MH_written_MASK                 0x00200000L
+#define MH_DEBUG_REG01__TC_MH_written                      0x00200000L
+#define MH_DEBUG_REG01__RB_SEND_q_MASK                     0x00400000L
+#define MH_DEBUG_REG01__RB_SEND_q                          0x00400000L
+#define MH_DEBUG_REG01__RB_RTR_q_MASK                      0x00800000L
+#define MH_DEBUG_REG01__RB_RTR_q                           0x00800000L
+#define MH_DEBUG_REG01__RB_BE_q_MASK                       0xff000000L
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG02__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG02__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG02__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG02__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK                 0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_rlast                      0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_tag_MASK                   0x00000070L
+#define MH_DEBUG_REG02__RDC_RID_MASK                       0x00000380L
+#define MH_DEBUG_REG02__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG02__MH_CP_writeclean_MASK              0x00001000L
+#define MH_DEBUG_REG02__MH_CP_writeclean                   0x00001000L
+#define MH_DEBUG_REG02__MH_RB_writeclean_MASK              0x00002000L
+#define MH_DEBUG_REG02__MH_RB_writeclean                   0x00002000L
+#define MH_DEBUG_REG02__BRC_BID_MASK                       0x0001c000L
+#define MH_DEBUG_REG02__BRC_BRESP_MASK                     0x00060000L
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK             0xffffffffL
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK            0xffffffffL
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG05__CP_MH_send                         0x00000001L
+#define MH_DEBUG_REG05__CP_MH_write_MASK                   0x00000002L
+#define MH_DEBUG_REG05__CP_MH_write                        0x00000002L
+#define MH_DEBUG_REG05__CP_MH_tag_MASK                     0x0000001cL
+#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK                 0xffffffe0L
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__ALWAYS_ZERO_MASK                   0x00000007L
+#define MH_DEBUG_REG08__VGT_MH_send_MASK                   0x00000008L
+#define MH_DEBUG_REG08__VGT_MH_send                        0x00000008L
+#define MH_DEBUG_REG08__VGT_MH_tagbe_MASK                  0x00000010L
+#define MH_DEBUG_REG08__VGT_MH_tagbe                       0x00000010L
+#define MH_DEBUG_REG08__VGT_MH_ad_31_5_MASK                0xffffffe0L
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG09__TC_MH_send_MASK                    0x00000004L
+#define MH_DEBUG_REG09__TC_MH_send                         0x00000004L
+#define MH_DEBUG_REG09__TC_MH_mask_MASK                    0x00000018L
+#define MH_DEBUG_REG09__TC_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__TC_MH_info_MASK                    0x01ffffffL
+#define MH_DEBUG_REG10__TC_MH_send_MASK                    0x02000000L
+#define MH_DEBUG_REG10__TC_MH_send                         0x02000000L
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__MH_TC_mcinfo_MASK                  0x01ffffffL
+#define MH_DEBUG_REG11__MH_TC_mcinfo_send_MASK             0x02000000L
+#define MH_DEBUG_REG11__MH_TC_mcinfo_send                  0x02000000L
+#define MH_DEBUG_REG11__TC_MH_written_MASK                 0x04000000L
+#define MH_DEBUG_REG11__TC_MH_written                      0x04000000L
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG12__TC_ROQ_SEND_MASK                   0x00000004L
+#define MH_DEBUG_REG12__TC_ROQ_SEND                        0x00000004L
+#define MH_DEBUG_REG12__TC_ROQ_MASK_MASK                   0x00000018L
+#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5_MASK              0xffffffe0L
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__TC_ROQ_INFO_MASK                   0x01ffffffL
+#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK                   0x02000000L
+#define MH_DEBUG_REG13__TC_ROQ_SEND                        0x02000000L
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG14__RB_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG14__RB_MH_send                         0x00000010L
+#define MH_DEBUG_REG14__RB_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__RB_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG17__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG17__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG17__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG17__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG17__ALEN_q_2_0_MASK                    0x000000e0L
+#define MH_DEBUG_REG17__ARVALID_q_MASK                     0x00000100L
+#define MH_DEBUG_REG17__ARVALID_q                          0x00000100L
+#define MH_DEBUG_REG17__ARREADY_q_MASK                     0x00000200L
+#define MH_DEBUG_REG17__ARREADY_q                          0x00000200L
+#define MH_DEBUG_REG17__ARID_q_MASK                        0x00001c00L
+#define MH_DEBUG_REG17__ARLEN_q_1_0_MASK                   0x00006000L
+#define MH_DEBUG_REG17__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG17__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG17__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG17__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG17__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG17__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG17__RID_q_MASK                         0x001c0000L
+#define MH_DEBUG_REG17__WVALID_q_MASK                      0x00200000L
+#define MH_DEBUG_REG17__WVALID_q                           0x00200000L
+#define MH_DEBUG_REG17__WREADY_q_MASK                      0x00400000L
+#define MH_DEBUG_REG17__WREADY_q                           0x00400000L
+#define MH_DEBUG_REG17__WLAST_q_MASK                       0x00800000L
+#define MH_DEBUG_REG17__WLAST_q                            0x00800000L
+#define MH_DEBUG_REG17__WID_q_MASK                         0x07000000L
+#define MH_DEBUG_REG17__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG17__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG17__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG17__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG17__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG18__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG18__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG18__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG18__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG18__ALEN_q_1_0_MASK                    0x00000060L
+#define MH_DEBUG_REG18__ARVALID_q_MASK                     0x00000080L
+#define MH_DEBUG_REG18__ARVALID_q                          0x00000080L
+#define MH_DEBUG_REG18__ARREADY_q_MASK                     0x00000100L
+#define MH_DEBUG_REG18__ARREADY_q                          0x00000100L
+#define MH_DEBUG_REG18__ARID_q_MASK                        0x00000e00L
+#define MH_DEBUG_REG18__ARLEN_q_1_1_MASK                   0x00001000L
+#define MH_DEBUG_REG18__ARLEN_q_1_1                        0x00001000L
+#define MH_DEBUG_REG18__WVALID_q_MASK                      0x00002000L
+#define MH_DEBUG_REG18__WVALID_q                           0x00002000L
+#define MH_DEBUG_REG18__WREADY_q_MASK                      0x00004000L
+#define MH_DEBUG_REG18__WREADY_q                           0x00004000L
+#define MH_DEBUG_REG18__WLAST_q_MASK                       0x00008000L
+#define MH_DEBUG_REG18__WLAST_q                            0x00008000L
+#define MH_DEBUG_REG18__WID_q_MASK                         0x00070000L
+#define MH_DEBUG_REG18__WSTRB_q_MASK                       0x07f80000L
+#define MH_DEBUG_REG18__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG18__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG18__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG18__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG18__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__ARC_CTRL_RE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG19__ARC_CTRL_RE_q                      0x00000001L
+#define MH_DEBUG_REG19__CTRL_ARC_ID_MASK                   0x0000000eL
+#define MH_DEBUG_REG19__CTRL_ARC_PAD_MASK                  0xfffffff0L
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG20__REG_A_MASK                         0x0000fffcL
+#define MH_DEBUG_REG20__REG_RE_MASK                        0x00010000L
+#define MH_DEBUG_REG20__REG_RE                             0x00010000L
+#define MH_DEBUG_REG20__REG_WE_MASK                        0x00020000L
+#define MH_DEBUG_REG20__REG_WE                             0x00020000L
+#define MH_DEBUG_REG20__BLOCK_RS_MASK                      0x00040000L
+#define MH_DEBUG_REG20__BLOCK_RS                           0x00040000L
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__REG_WD_MASK                        0xffffffffL
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__CIB_MH_axi_halt_req_MASK           0x00000001L
+#define MH_DEBUG_REG22__CIB_MH_axi_halt_req                0x00000001L
+#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack_MASK           0x00000002L
+#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack                0x00000002L
+#define MH_DEBUG_REG22__MH_RBBM_busy_MASK                  0x00000004L
+#define MH_DEBUG_REG22__MH_RBBM_busy                       0x00000004L
+#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int_MASK          0x00000008L
+#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int               0x00000008L
+#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int_MASK         0x00000010L
+#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int              0x00000010L
+#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int_MASK       0x00000020L
+#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int            0x00000020L
+#define MH_DEBUG_REG22__GAT_CLK_ENA_MASK                   0x00000040L
+#define MH_DEBUG_REG22__GAT_CLK_ENA                        0x00000040L
+#define MH_DEBUG_REG22__AXI_RDY_ENA_MASK                   0x00000080L
+#define MH_DEBUG_REG22__AXI_RDY_ENA                        0x00000080L
+#define MH_DEBUG_REG22__RBBM_MH_clk_en_override_MASK       0x00000100L
+#define MH_DEBUG_REG22__RBBM_MH_clk_en_override            0x00000100L
+#define MH_DEBUG_REG22__CNT_q_MASK                         0x00007e00L
+#define MH_DEBUG_REG22__TCD_EMPTY_q_MASK                   0x00008000L
+#define MH_DEBUG_REG22__TCD_EMPTY_q                        0x00008000L
+#define MH_DEBUG_REG22__TC_ROQ_EMPTY_MASK                  0x00010000L
+#define MH_DEBUG_REG22__TC_ROQ_EMPTY                       0x00010000L
+#define MH_DEBUG_REG22__MH_BUSY_d_MASK                     0x00020000L
+#define MH_DEBUG_REG22__MH_BUSY_d                          0x00020000L
+#define MH_DEBUG_REG22__ANY_CLNT_BUSY_MASK                 0x00040000L
+#define MH_DEBUG_REG22__ANY_CLNT_BUSY                      0x00040000L
+#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000L
+#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL   0x00080000L
+#define MH_DEBUG_REG22__CP_SEND_q_MASK                     0x00100000L
+#define MH_DEBUG_REG22__CP_SEND_q                          0x00100000L
+#define MH_DEBUG_REG22__CP_RTR_q_MASK                      0x00200000L
+#define MH_DEBUG_REG22__CP_RTR_q                           0x00200000L
+#define MH_DEBUG_REG22__VGT_SEND_q_MASK                    0x00400000L
+#define MH_DEBUG_REG22__VGT_SEND_q                         0x00400000L
+#define MH_DEBUG_REG22__VGT_RTR_q_MASK                     0x00800000L
+#define MH_DEBUG_REG22__VGT_RTR_q                          0x00800000L
+#define MH_DEBUG_REG22__TC_ROQ_SEND_q_MASK                 0x01000000L
+#define MH_DEBUG_REG22__TC_ROQ_SEND_q                      0x01000000L
+#define MH_DEBUG_REG22__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG22__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG22__RB_SEND_q_MASK                     0x04000000L
+#define MH_DEBUG_REG22__RB_SEND_q                          0x04000000L
+#define MH_DEBUG_REG22__RB_RTR_q_MASK                      0x08000000L
+#define MH_DEBUG_REG22__RB_RTR_q                           0x08000000L
+#define MH_DEBUG_REG22__RDC_VALID_MASK                     0x10000000L
+#define MH_DEBUG_REG22__RDC_VALID                          0x10000000L
+#define MH_DEBUG_REG22__RDC_RLAST_MASK                     0x20000000L
+#define MH_DEBUG_REG22__RDC_RLAST                          0x20000000L
+#define MH_DEBUG_REG22__TLBMISS_VALID_MASK                 0x40000000L
+#define MH_DEBUG_REG22__TLBMISS_VALID                      0x40000000L
+#define MH_DEBUG_REG22__BRC_VALID_MASK                     0x80000000L
+#define MH_DEBUG_REG22__BRC_VALID                          0x80000000L
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__EFF2_FP_WINNER_MASK                0x00000007L
+#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out_MASK           0x00000038L
+#define MH_DEBUG_REG23__EFF1_WINNER_MASK                   0x000001c0L
+#define MH_DEBUG_REG23__ARB_WINNER_MASK                    0x00000e00L
+#define MH_DEBUG_REG23__ARB_WINNER_q_MASK                  0x00007000L
+#define MH_DEBUG_REG23__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG23__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG23__KILL_EFF1_MASK                     0x00010000L
+#define MH_DEBUG_REG23__KILL_EFF1                          0x00010000L
+#define MH_DEBUG_REG23__ARB_HOLD_MASK                      0x00020000L
+#define MH_DEBUG_REG23__ARB_HOLD                           0x00020000L
+#define MH_DEBUG_REG23__ARB_RTR_q_MASK                     0x00040000L
+#define MH_DEBUG_REG23__ARB_RTR_q                          0x00040000L
+#define MH_DEBUG_REG23__CP_SEND_QUAL_MASK                  0x00080000L
+#define MH_DEBUG_REG23__CP_SEND_QUAL                       0x00080000L
+#define MH_DEBUG_REG23__VGT_SEND_QUAL_MASK                 0x00100000L
+#define MH_DEBUG_REG23__VGT_SEND_QUAL                      0x00100000L
+#define MH_DEBUG_REG23__TC_SEND_QUAL_MASK                  0x00200000L
+#define MH_DEBUG_REG23__TC_SEND_QUAL                       0x00200000L
+#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL_MASK             0x00400000L
+#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL                  0x00400000L
+#define MH_DEBUG_REG23__RB_SEND_QUAL_MASK                  0x00800000L
+#define MH_DEBUG_REG23__RB_SEND_QUAL                       0x00800000L
+#define MH_DEBUG_REG23__ARB_QUAL_MASK                      0x01000000L
+#define MH_DEBUG_REG23__ARB_QUAL                           0x01000000L
+#define MH_DEBUG_REG23__CP_EFF1_REQ_MASK                   0x02000000L
+#define MH_DEBUG_REG23__CP_EFF1_REQ                        0x02000000L
+#define MH_DEBUG_REG23__VGT_EFF1_REQ_MASK                  0x04000000L
+#define MH_DEBUG_REG23__VGT_EFF1_REQ                       0x04000000L
+#define MH_DEBUG_REG23__TC_EFF1_REQ_MASK                   0x08000000L
+#define MH_DEBUG_REG23__TC_EFF1_REQ                        0x08000000L
+#define MH_DEBUG_REG23__RB_EFF1_REQ_MASK                   0x10000000L
+#define MH_DEBUG_REG23__RB_EFF1_REQ                        0x10000000L
+#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK_MASK             0x20000000L
+#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK                  0x20000000L
+#define MH_DEBUG_REG23__TCD_NEARFULL_q_MASK                0x40000000L
+#define MH_DEBUG_REG23__TCD_NEARFULL_q                     0x40000000L
+#define MH_DEBUG_REG23__TCHOLD_IP_q_MASK                   0x80000000L
+#define MH_DEBUG_REG23__TCHOLD_IP_q                        0x80000000L
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__EFF1_WINNER_MASK                   0x00000007L
+#define MH_DEBUG_REG24__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG24__CP_SEND_QUAL_MASK                  0x00000040L
+#define MH_DEBUG_REG24__CP_SEND_QUAL                       0x00000040L
+#define MH_DEBUG_REG24__VGT_SEND_QUAL_MASK                 0x00000080L
+#define MH_DEBUG_REG24__VGT_SEND_QUAL                      0x00000080L
+#define MH_DEBUG_REG24__TC_SEND_QUAL_MASK                  0x00000100L
+#define MH_DEBUG_REG24__TC_SEND_QUAL                       0x00000100L
+#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL_MASK             0x00000200L
+#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL                  0x00000200L
+#define MH_DEBUG_REG24__RB_SEND_QUAL_MASK                  0x00000400L
+#define MH_DEBUG_REG24__RB_SEND_QUAL                       0x00000400L
+#define MH_DEBUG_REG24__ARB_QUAL_MASK                      0x00000800L
+#define MH_DEBUG_REG24__ARB_QUAL                           0x00000800L
+#define MH_DEBUG_REG24__CP_EFF1_REQ_MASK                   0x00001000L
+#define MH_DEBUG_REG24__CP_EFF1_REQ                        0x00001000L
+#define MH_DEBUG_REG24__VGT_EFF1_REQ_MASK                  0x00002000L
+#define MH_DEBUG_REG24__VGT_EFF1_REQ                       0x00002000L
+#define MH_DEBUG_REG24__TC_EFF1_REQ_MASK                   0x00004000L
+#define MH_DEBUG_REG24__TC_EFF1_REQ                        0x00004000L
+#define MH_DEBUG_REG24__RB_EFF1_REQ_MASK                   0x00008000L
+#define MH_DEBUG_REG24__RB_EFF1_REQ                        0x00008000L
+#define MH_DEBUG_REG24__EFF1_WIN_MASK                      0x00010000L
+#define MH_DEBUG_REG24__EFF1_WIN                           0x00010000L
+#define MH_DEBUG_REG24__KILL_EFF1_MASK                     0x00020000L
+#define MH_DEBUG_REG24__KILL_EFF1                          0x00020000L
+#define MH_DEBUG_REG24__TCD_NEARFULL_q_MASK                0x00040000L
+#define MH_DEBUG_REG24__TCD_NEARFULL_q                     0x00040000L
+#define MH_DEBUG_REG24__TC_ARB_HOLD_MASK                   0x00080000L
+#define MH_DEBUG_REG24__TC_ARB_HOLD                        0x00080000L
+#define MH_DEBUG_REG24__ARB_HOLD_MASK                      0x00100000L
+#define MH_DEBUG_REG24__ARB_HOLD                           0x00100000L
+#define MH_DEBUG_REG24__ARB_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG24__ARB_RTR_q                          0x00200000L
+#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q_MASK       0xffc00000L
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out_MASK           0x00000007L
+#define MH_DEBUG_REG25__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d_MASK          0x000001c0L
+#define MH_DEBUG_REG25__LEAST_RECENT_d_MASK                0x00000e00L
+#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d_MASK         0x00001000L
+#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d              0x00001000L
+#define MH_DEBUG_REG25__ARB_HOLD_MASK                      0x00002000L
+#define MH_DEBUG_REG25__ARB_HOLD                           0x00002000L
+#define MH_DEBUG_REG25__ARB_RTR_q_MASK                     0x00004000L
+#define MH_DEBUG_REG25__ARB_RTR_q                          0x00004000L
+#define MH_DEBUG_REG25__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG25__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG25__CLNT_REQ_MASK                      0x000f0000L
+#define MH_DEBUG_REG25__RECENT_d_0_MASK                    0x00700000L
+#define MH_DEBUG_REG25__RECENT_d_1_MASK                    0x03800000L
+#define MH_DEBUG_REG25__RECENT_d_2_MASK                    0x1c000000L
+#define MH_DEBUG_REG25__RECENT_d_3_MASK                    0xe0000000L
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__TC_ARB_HOLD_MASK                   0x00000001L
+#define MH_DEBUG_REG26__TC_ARB_HOLD                        0x00000001L
+#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK_MASK        0x00000002L
+#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK             0x00000002L
+#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK_MASK          0x00000004L
+#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK               0x00000004L
+#define MH_DEBUG_REG26__TCD_NEARFULL_q_MASK                0x00000008L
+#define MH_DEBUG_REG26__TCD_NEARFULL_q                     0x00000008L
+#define MH_DEBUG_REG26__TCHOLD_IP_q_MASK                   0x00000010L
+#define MH_DEBUG_REG26__TCHOLD_IP_q                        0x00000010L
+#define MH_DEBUG_REG26__TCHOLD_CNT_q_MASK                  0x000000e0L
+#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L
+#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK              0x00000200L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q                   0x00000200L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK                 0x00000400L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q                      0x00000400L
+#define MH_DEBUG_REG26__TC_MH_written_MASK                 0x00000800L
+#define MH_DEBUG_REG26__TC_MH_written                      0x00000800L
+#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q_MASK            0x0007f000L
+#define MH_DEBUG_REG26__WBURST_ACTIVE_MASK                 0x00080000L
+#define MH_DEBUG_REG26__WBURST_ACTIVE                      0x00080000L
+#define MH_DEBUG_REG26__WLAST_q_MASK                       0x00100000L
+#define MH_DEBUG_REG26__WLAST_q                            0x00100000L
+#define MH_DEBUG_REG26__WBURST_IP_q_MASK                   0x00200000L
+#define MH_DEBUG_REG26__WBURST_IP_q                        0x00200000L
+#define MH_DEBUG_REG26__WBURST_CNT_q_MASK                  0x01c00000L
+#define MH_DEBUG_REG26__CP_SEND_QUAL_MASK                  0x02000000L
+#define MH_DEBUG_REG26__CP_SEND_QUAL                       0x02000000L
+#define MH_DEBUG_REG26__CP_MH_write_MASK                   0x04000000L
+#define MH_DEBUG_REG26__CP_MH_write                        0x04000000L
+#define MH_DEBUG_REG26__RB_SEND_QUAL_MASK                  0x08000000L
+#define MH_DEBUG_REG26__RB_SEND_QUAL                       0x08000000L
+#define MH_DEBUG_REG26__ARB_WINNER_MASK                    0x70000000L
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q_MASK           0x03ffffffL
+#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0x1c000000L
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG28__ROQ_MARK_q_MASK                    0x0000ff00L
+#define MH_DEBUG_REG28__ROQ_VALID_q_MASK                   0x00ff0000L
+#define MH_DEBUG_REG28__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG28__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG28__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG28__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG28__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG28__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG28__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG28__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG28__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG28__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG28__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG28__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG29__ROQ_MARK_d_MASK                    0x0000ff00L
+#define MH_DEBUG_REG29__ROQ_VALID_d_MASK                   0x00ff0000L
+#define MH_DEBUG_REG29__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG29__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG29__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG29__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG29__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG29__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG29__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG29__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG29__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG29__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG29__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG29__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN_MASK             0x000000ffL
+#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ_MASK             0x0000ff00L
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN_MASK         0x00ff0000L
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ_MASK         0xff000000L
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG31__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG31__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG31__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG31__ROQ_MARK_q_0_MASK                  0x00000004L
+#define MH_DEBUG_REG31__ROQ_MARK_q_0                       0x00000004L
+#define MH_DEBUG_REG31__ROQ_VALID_q_0_MASK                 0x00000008L
+#define MH_DEBUG_REG31__ROQ_VALID_q_0                      0x00000008L
+#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0_MASK             0x00000010L
+#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0                  0x00000010L
+#define MH_DEBUG_REG31__ROQ_ADDR_0_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG32__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG32__ROQ_MARK_q_1_MASK                  0x00000004L
+#define MH_DEBUG_REG32__ROQ_MARK_q_1                       0x00000004L
+#define MH_DEBUG_REG32__ROQ_VALID_q_1_MASK                 0x00000008L
+#define MH_DEBUG_REG32__ROQ_VALID_q_1                      0x00000008L
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1_MASK             0x00000010L
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1                  0x00000010L
+#define MH_DEBUG_REG32__ROQ_ADDR_1_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG33__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG33__ROQ_MARK_q_2_MASK                  0x00000004L
+#define MH_DEBUG_REG33__ROQ_MARK_q_2                       0x00000004L
+#define MH_DEBUG_REG33__ROQ_VALID_q_2_MASK                 0x00000008L
+#define MH_DEBUG_REG33__ROQ_VALID_q_2                      0x00000008L
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2_MASK             0x00000010L
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2                  0x00000010L
+#define MH_DEBUG_REG33__ROQ_ADDR_2_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG34__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG34__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG34__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG34__ROQ_MARK_q_3_MASK                  0x00000004L
+#define MH_DEBUG_REG34__ROQ_MARK_q_3                       0x00000004L
+#define MH_DEBUG_REG34__ROQ_VALID_q_3_MASK                 0x00000008L
+#define MH_DEBUG_REG34__ROQ_VALID_q_3                      0x00000008L
+#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3_MASK             0x00000010L
+#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3                  0x00000010L
+#define MH_DEBUG_REG34__ROQ_ADDR_3_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG35__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG35__ROQ_MARK_q_4_MASK                  0x00000004L
+#define MH_DEBUG_REG35__ROQ_MARK_q_4                       0x00000004L
+#define MH_DEBUG_REG35__ROQ_VALID_q_4_MASK                 0x00000008L
+#define MH_DEBUG_REG35__ROQ_VALID_q_4                      0x00000008L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4_MASK             0x00000010L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4                  0x00000010L
+#define MH_DEBUG_REG35__ROQ_ADDR_4_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG36__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG36__ROQ_MARK_q_5_MASK                  0x00000004L
+#define MH_DEBUG_REG36__ROQ_MARK_q_5                       0x00000004L
+#define MH_DEBUG_REG36__ROQ_VALID_q_5_MASK                 0x00000008L
+#define MH_DEBUG_REG36__ROQ_VALID_q_5                      0x00000008L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5_MASK             0x00000010L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5                  0x00000010L
+#define MH_DEBUG_REG36__ROQ_ADDR_5_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG37__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG37__ROQ_MARK_q_6_MASK                  0x00000004L
+#define MH_DEBUG_REG37__ROQ_MARK_q_6                       0x00000004L
+#define MH_DEBUG_REG37__ROQ_VALID_q_6_MASK                 0x00000008L
+#define MH_DEBUG_REG37__ROQ_VALID_q_6                      0x00000008L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6_MASK             0x00000010L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6                  0x00000010L
+#define MH_DEBUG_REG37__ROQ_ADDR_6_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG38__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG38__ROQ_MARK_q_7_MASK                  0x00000004L
+#define MH_DEBUG_REG38__ROQ_MARK_q_7                       0x00000004L
+#define MH_DEBUG_REG38__ROQ_VALID_q_7_MASK                 0x00000008L
+#define MH_DEBUG_REG38__ROQ_VALID_q_7                      0x00000008L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7_MASK             0x00000010L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7                  0x00000010L
+#define MH_DEBUG_REG38__ROQ_ADDR_7_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG39__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG39__MMU_RTR_MASK                       0x00000002L
+#define MH_DEBUG_REG39__MMU_RTR                            0x00000002L
+#define MH_DEBUG_REG39__ARB_ID_q_MASK                      0x0000001cL
+#define MH_DEBUG_REG39__ARB_WRITE_q_MASK                   0x00000020L
+#define MH_DEBUG_REG39__ARB_WRITE_q                        0x00000020L
+#define MH_DEBUG_REG39__ARB_BLEN_q_MASK                    0x00000040L
+#define MH_DEBUG_REG39__ARB_BLEN_q                         0x00000040L
+#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY_MASK                0x00000080L
+#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY                     0x00000080L
+#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q_MASK                0x00000700L
+#define MH_DEBUG_REG39__MMU_WE_MASK                        0x00000800L
+#define MH_DEBUG_REG39__MMU_WE                             0x00000800L
+#define MH_DEBUG_REG39__ARQ_RTR_MASK                       0x00001000L
+#define MH_DEBUG_REG39__ARQ_RTR                            0x00001000L
+#define MH_DEBUG_REG39__MMU_ID_MASK                        0x0000e000L
+#define MH_DEBUG_REG39__MMU_WRITE_MASK                     0x00010000L
+#define MH_DEBUG_REG39__MMU_WRITE                          0x00010000L
+#define MH_DEBUG_REG39__MMU_BLEN_MASK                      0x00020000L
+#define MH_DEBUG_REG39__MMU_BLEN                           0x00020000L
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG40__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG40__ARB_ID_q_MASK                      0x0000000eL
+#define MH_DEBUG_REG40__ARB_VAD_q_MASK                     0xfffffff0L
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__MMU_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG41__MMU_WE                             0x00000001L
+#define MH_DEBUG_REG41__MMU_ID_MASK                        0x0000000eL
+#define MH_DEBUG_REG41__MMU_PAD_MASK                       0xfffffff0L
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__WDB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG42__WDB_WE                             0x00000001L
+#define MH_DEBUG_REG42__WDB_RTR_SKID_MASK                  0x00000002L
+#define MH_DEBUG_REG42__WDB_RTR_SKID                       0x00000002L
+#define MH_DEBUG_REG42__ARB_WSTRB_q_MASK                   0x000003fcL
+#define MH_DEBUG_REG42__ARB_WLAST_MASK                     0x00000400L
+#define MH_DEBUG_REG42__ARB_WLAST                          0x00000400L
+#define MH_DEBUG_REG42__WDB_CTRL_EMPTY_MASK                0x00000800L
+#define MH_DEBUG_REG42__WDB_CTRL_EMPTY                     0x00000800L
+#define MH_DEBUG_REG42__WDB_FIFO_CNT_q_MASK                0x0001f000L
+#define MH_DEBUG_REG42__WDC_WDB_RE_q_MASK                  0x00020000L
+#define MH_DEBUG_REG42__WDC_WDB_RE_q                       0x00020000L
+#define MH_DEBUG_REG42__WDB_WDC_WID_MASK                   0x001c0000L
+#define MH_DEBUG_REG42__WDB_WDC_WLAST_MASK                 0x00200000L
+#define MH_DEBUG_REG42__WDB_WDC_WLAST                      0x00200000L
+#define MH_DEBUG_REG42__WDB_WDC_WSTRB_MASK                 0x3fc00000L
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_WDATA_q_31_0_MASK              0xffffffffL
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WDATA_q_63_32_MASK             0xffffffffL
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0_MASK            0xffffffffL
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32_MASK           0xffffffffL
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__CTRL_ARC_EMPTY_MASK                0x00000001L
+#define MH_DEBUG_REG47__CTRL_ARC_EMPTY                     0x00000001L
+#define MH_DEBUG_REG47__CTRL_RARC_EMPTY_MASK               0x00000002L
+#define MH_DEBUG_REG47__CTRL_RARC_EMPTY                    0x00000002L
+#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY_MASK                0x00000004L
+#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY                     0x00000004L
+#define MH_DEBUG_REG47__ARQ_CTRL_WRITE_MASK                0x00000008L
+#define MH_DEBUG_REG47__ARQ_CTRL_WRITE                     0x00000008L
+#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS_MASK              0x00000010L
+#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS                   0x00000010L
+#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q_MASK             0x00000020L
+#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q                  0x00000020L
+#define MH_DEBUG_REG47__INFLT_LIMIT_q_MASK                 0x00000040L
+#define MH_DEBUG_REG47__INFLT_LIMIT_q                      0x00000040L
+#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q_MASK             0x00001f80L
+#define MH_DEBUG_REG47__ARC_CTRL_RE_q_MASK                 0x00002000L
+#define MH_DEBUG_REG47__ARC_CTRL_RE_q                      0x00002000L
+#define MH_DEBUG_REG47__RARC_CTRL_RE_q_MASK                0x00004000L
+#define MH_DEBUG_REG47__RARC_CTRL_RE_q                     0x00004000L
+#define MH_DEBUG_REG47__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG47__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG47__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG47__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG47__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG47__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG47__BVALID_q_MASK                      0x00040000L
+#define MH_DEBUG_REG47__BVALID_q                           0x00040000L
+#define MH_DEBUG_REG47__BREADY_q_MASK                      0x00080000L
+#define MH_DEBUG_REG47__BREADY_q                           0x00080000L
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG48__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG48__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG48__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG48__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG48__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG48__MH_TLBMISS_SEND_MASK               0x00000008L
+#define MH_DEBUG_REG48__MH_TLBMISS_SEND                    0x00000008L
+#define MH_DEBUG_REG48__TLBMISS_VALID_MASK                 0x00000010L
+#define MH_DEBUG_REG48__TLBMISS_VALID                      0x00000010L
+#define MH_DEBUG_REG48__RDC_VALID_MASK                     0x00000020L
+#define MH_DEBUG_REG48__RDC_VALID                          0x00000020L
+#define MH_DEBUG_REG48__RDC_RID_MASK                       0x000001c0L
+#define MH_DEBUG_REG48__RDC_RLAST_MASK                     0x00000200L
+#define MH_DEBUG_REG48__RDC_RLAST                          0x00000200L
+#define MH_DEBUG_REG48__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS_MASK              0x00001000L
+#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS                   0x00001000L
+#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q_MASK             0x00002000L
+#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q                  0x00002000L
+#define MH_DEBUG_REG48__MMU_ID_REQUEST_q_MASK              0x00004000L
+#define MH_DEBUG_REG48__MMU_ID_REQUEST_q                   0x00004000L
+#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q_MASK       0x001f8000L
+#define MH_DEBUG_REG48__MMU_ID_RESPONSE_MASK               0x00200000L
+#define MH_DEBUG_REG48__MMU_ID_RESPONSE                    0x00200000L
+#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q_MASK          0x0fc00000L
+#define MH_DEBUG_REG48__CNT_HOLD_q1_MASK                   0x10000000L
+#define MH_DEBUG_REG48__CNT_HOLD_q1                        0x10000000L
+#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0xe0000000L
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT_MASK             0xffffffffL
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__RF_MMU_CONFIG_q_MASK               0x00ffffffL
+#define MH_DEBUG_REG50__ARB_ID_q_MASK                      0x07000000L
+#define MH_DEBUG_REG50__ARB_WRITE_q_MASK                   0x08000000L
+#define MH_DEBUG_REG50__ARB_WRITE_q                        0x08000000L
+#define MH_DEBUG_REG50__client_behavior_q_MASK             0x30000000L
+#define MH_DEBUG_REG50__ARB_WE_MASK                        0x40000000L
+#define MH_DEBUG_REG50__ARB_WE                             0x40000000L
+#define MH_DEBUG_REG50__MMU_RTR_MASK                       0x80000000L
+#define MH_DEBUG_REG50__MMU_RTR                            0x80000000L
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__stage1_valid_MASK                  0x00000001L
+#define MH_DEBUG_REG51__stage1_valid                       0x00000001L
+#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q_MASK             0x00000002L
+#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q                  0x00000002L
+#define MH_DEBUG_REG51__pa_in_mpu_range_MASK               0x00000004L
+#define MH_DEBUG_REG51__pa_in_mpu_range                    0x00000004L
+#define MH_DEBUG_REG51__tag_match_q_MASK                   0x00000008L
+#define MH_DEBUG_REG51__tag_match_q                        0x00000008L
+#define MH_DEBUG_REG51__tag_miss_q_MASK                    0x00000010L
+#define MH_DEBUG_REG51__tag_miss_q                         0x00000010L
+#define MH_DEBUG_REG51__va_in_range_q_MASK                 0x00000020L
+#define MH_DEBUG_REG51__va_in_range_q                      0x00000020L
+#define MH_DEBUG_REG51__MMU_MISS_MASK                      0x00000040L
+#define MH_DEBUG_REG51__MMU_MISS                           0x00000040L
+#define MH_DEBUG_REG51__MMU_READ_MISS_MASK                 0x00000080L
+#define MH_DEBUG_REG51__MMU_READ_MISS                      0x00000080L
+#define MH_DEBUG_REG51__MMU_WRITE_MISS_MASK                0x00000100L
+#define MH_DEBUG_REG51__MMU_WRITE_MISS                     0x00000100L
+#define MH_DEBUG_REG51__MMU_HIT_MASK                       0x00000200L
+#define MH_DEBUG_REG51__MMU_HIT                            0x00000200L
+#define MH_DEBUG_REG51__MMU_READ_HIT_MASK                  0x00000400L
+#define MH_DEBUG_REG51__MMU_READ_HIT                       0x00000400L
+#define MH_DEBUG_REG51__MMU_WRITE_HIT_MASK                 0x00000800L
+#define MH_DEBUG_REG51__MMU_WRITE_HIT                      0x00000800L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS_MASK        0x00001000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS             0x00001000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT_MASK         0x00002000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT              0x00002000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS_MASK     0x00004000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS          0x00004000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT_MASK      0x00008000L
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT           0x00008000L
+#define MH_DEBUG_REG51__REQ_VA_OFFSET_q_MASK               0xffff0000L
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__ARQ_RTR_MASK                       0x00000001L
+#define MH_DEBUG_REG52__ARQ_RTR                            0x00000001L
+#define MH_DEBUG_REG52__MMU_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG52__MMU_WE                             0x00000002L
+#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q_MASK             0x00000004L
+#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q                  0x00000004L
+#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS_MASK              0x00000008L
+#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS                   0x00000008L
+#define MH_DEBUG_REG52__MH_TLBMISS_SEND_MASK               0x00000010L
+#define MH_DEBUG_REG52__MH_TLBMISS_SEND                    0x00000010L
+#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L
+#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH  0x00000020L
+#define MH_DEBUG_REG52__pa_in_mpu_range_MASK               0x00000040L
+#define MH_DEBUG_REG52__pa_in_mpu_range                    0x00000040L
+#define MH_DEBUG_REG52__stage1_valid_MASK                  0x00000080L
+#define MH_DEBUG_REG52__stage1_valid                       0x00000080L
+#define MH_DEBUG_REG52__stage2_valid_MASK                  0x00000100L
+#define MH_DEBUG_REG52__stage2_valid                       0x00000100L
+#define MH_DEBUG_REG52__client_behavior_q_MASK             0x00000600L
+#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q_MASK             0x00000800L
+#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q                  0x00000800L
+#define MH_DEBUG_REG52__tag_match_q_MASK                   0x00001000L
+#define MH_DEBUG_REG52__tag_match_q                        0x00001000L
+#define MH_DEBUG_REG52__tag_miss_q_MASK                    0x00002000L
+#define MH_DEBUG_REG52__tag_miss_q                         0x00002000L
+#define MH_DEBUG_REG52__va_in_range_q_MASK                 0x00004000L
+#define MH_DEBUG_REG52__va_in_range_q                      0x00004000L
+#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q_MASK          0x00008000L
+#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q               0x00008000L
+#define MH_DEBUG_REG52__TAG_valid_q_MASK                   0xffff0000L
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__TAG0_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG53__TAG_valid_q_0_MASK                 0x00002000L
+#define MH_DEBUG_REG53__TAG_valid_q_0                      0x00002000L
+#define MH_DEBUG_REG53__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG53__TAG1_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG53__TAG_valid_q_1_MASK                 0x20000000L
+#define MH_DEBUG_REG53__TAG_valid_q_1                      0x20000000L
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__TAG2_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG54__TAG_valid_q_2_MASK                 0x00002000L
+#define MH_DEBUG_REG54__TAG_valid_q_2                      0x00002000L
+#define MH_DEBUG_REG54__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG54__TAG3_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG54__TAG_valid_q_3_MASK                 0x20000000L
+#define MH_DEBUG_REG54__TAG_valid_q_3                      0x20000000L
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG4_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG55__TAG_valid_q_4_MASK                 0x00002000L
+#define MH_DEBUG_REG55__TAG_valid_q_4                      0x00002000L
+#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG55__TAG5_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG55__TAG_valid_q_5_MASK                 0x20000000L
+#define MH_DEBUG_REG55__TAG_valid_q_5                      0x20000000L
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG6_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG56__TAG_valid_q_6_MASK                 0x00002000L
+#define MH_DEBUG_REG56__TAG_valid_q_6                      0x00002000L
+#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG56__TAG7_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG56__TAG_valid_q_7_MASK                 0x20000000L
+#define MH_DEBUG_REG56__TAG_valid_q_7                      0x20000000L
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG8_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG57__TAG_valid_q_8_MASK                 0x00002000L
+#define MH_DEBUG_REG57__TAG_valid_q_8                      0x00002000L
+#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG57__TAG9_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG57__TAG_valid_q_9_MASK                 0x20000000L
+#define MH_DEBUG_REG57__TAG_valid_q_9                      0x20000000L
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG10_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG58__TAG_valid_q_10_MASK                0x00002000L
+#define MH_DEBUG_REG58__TAG_valid_q_10                     0x00002000L
+#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG58__TAG11_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG58__TAG_valid_q_11_MASK                0x20000000L
+#define MH_DEBUG_REG58__TAG_valid_q_11                     0x20000000L
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG12_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG59__TAG_valid_q_12_MASK                0x00002000L
+#define MH_DEBUG_REG59__TAG_valid_q_12                     0x00002000L
+#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG59__TAG13_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG59__TAG_valid_q_13_MASK                0x20000000L
+#define MH_DEBUG_REG59__TAG_valid_q_13                     0x20000000L
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG14_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG60__TAG_valid_q_14_MASK                0x00002000L
+#define MH_DEBUG_REG60__TAG_valid_q_14                     0x00002000L
+#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG60__TAG15_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG60__TAG_valid_q_15_MASK                0x20000000L
+#define MH_DEBUG_REG60__TAG_valid_q_15                     0x20000000L
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE_MASK                     0x00000001L
+#define MH_MMU_CONFIG__MMU_ENABLE                          0x00000001L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK              0x00000002L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE                   0x00000002L
+#define MH_MMU_CONFIG__RESERVED1_MASK                      0x0000000cL
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK             0x00000030L
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK             0x000000c0L
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK            0x00000300L
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK            0x00000c00L
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK            0x00003000L
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK            0x0000c000L
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK            0x00030000L
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK           0x000c0000L
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK           0x00300000L
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK             0x00c00000L
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK             0x00000fffL
+#define MH_MMU_VA_RANGE__VA_BASE_MASK                      0xfffff000L
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE_MASK                       0xfffff000L
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK                 0x00000001L
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT                      0x00000001L
+#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK                    0x00000002L
+#define MH_MMU_PAGE_FAULT__OP_TYPE                         0x00000002L
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK              0x0000000cL
+#define MH_MMU_PAGE_FAULT__AXI_ID_MASK                     0x00000070L
+#define MH_MMU_PAGE_FAULT__RESERVED1_MASK                  0x00000080L
+#define MH_MMU_PAGE_FAULT__RESERVED1                       0x00000080L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK   0x00000100L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE        0x00000100L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK       0x00000200L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE            0x00000200L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK      0x00000400L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR           0x00000400L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK     0x00000800L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR          0x00000800L
+#define MH_MMU_PAGE_FAULT__REQ_VA_MASK                     0xfffff000L
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK                 0xffffffe0L
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK             0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL                  0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK              0x00000002L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC                   0x00000002L
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE_MASK                     0xfffff000L
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END_MASK                       0xfffff000L
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK                     0x00000002L
+#define WAIT_UNTIL__WAIT_RE_VSYNC                          0x00000002L
+#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK                     0x00000004L
+#define WAIT_UNTIL__WAIT_FE_VSYNC                          0x00000004L
+#define WAIT_UNTIL__WAIT_VSYNC_MASK                        0x00000008L
+#define WAIT_UNTIL__WAIT_VSYNC                             0x00000008L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK                    0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0                         0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK                    0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1                         0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK                    0x00000040L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2                         0x00000040L
+#define WAIT_UNTIL__WAIT_CMDFIFO_MASK                      0x00000400L
+#define WAIT_UNTIL__WAIT_CMDFIFO                           0x00000400L
+#define WAIT_UNTIL__WAIT_2D_IDLE_MASK                      0x00004000L
+#define WAIT_UNTIL__WAIT_2D_IDLE                           0x00004000L
+#define WAIT_UNTIL__WAIT_3D_IDLE_MASK                      0x00008000L
+#define WAIT_UNTIL__WAIT_3D_IDLE                           0x00008000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK                 0x00010000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN                      0x00010000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK                 0x00020000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN                      0x00020000L
+#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK                   0x00f00000L
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK           0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI                0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK      0x00000020L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI           0x00000020L
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL_MASK                    0x0000001fL
+#define RBBM_STATUS__TC_BUSY_MASK                          0x00000020L
+#define RBBM_STATUS__TC_BUSY                               0x00000020L
+#define RBBM_STATUS__HIRQ_PENDING_MASK                     0x00000100L
+#define RBBM_STATUS__HIRQ_PENDING                          0x00000100L
+#define RBBM_STATUS__CPRQ_PENDING_MASK                     0x00000200L
+#define RBBM_STATUS__CPRQ_PENDING                          0x00000200L
+#define RBBM_STATUS__CFRQ_PENDING_MASK                     0x00000400L
+#define RBBM_STATUS__CFRQ_PENDING                          0x00000400L
+#define RBBM_STATUS__PFRQ_PENDING_MASK                     0x00000800L
+#define RBBM_STATUS__PFRQ_PENDING                          0x00000800L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK                  0x00001000L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA                       0x00001000L
+#define RBBM_STATUS__RBBM_WU_BUSY_MASK                     0x00004000L
+#define RBBM_STATUS__RBBM_WU_BUSY                          0x00004000L
+#define RBBM_STATUS__CP_NRT_BUSY_MASK                      0x00010000L
+#define RBBM_STATUS__CP_NRT_BUSY                           0x00010000L
+#define RBBM_STATUS__MH_BUSY_MASK                          0x00040000L
+#define RBBM_STATUS__MH_BUSY                               0x00040000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK                0x00080000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY                     0x00080000L
+#define RBBM_STATUS__SX_BUSY_MASK                          0x00200000L
+#define RBBM_STATUS__SX_BUSY                               0x00200000L
+#define RBBM_STATUS__TPC_BUSY_MASK                         0x00400000L
+#define RBBM_STATUS__TPC_BUSY                              0x00400000L
+#define RBBM_STATUS__SC_CNTX_BUSY_MASK                     0x01000000L
+#define RBBM_STATUS__SC_CNTX_BUSY                          0x01000000L
+#define RBBM_STATUS__PA_BUSY_MASK                          0x02000000L
+#define RBBM_STATUS__PA_BUSY                               0x02000000L
+#define RBBM_STATUS__VGT_BUSY_MASK                         0x04000000L
+#define RBBM_STATUS__VGT_BUSY                              0x04000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK                   0x08000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY                        0x08000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK                    0x10000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY                         0x10000000L
+#define RBBM_STATUS__RB_CNTX_BUSY_MASK                     0x40000000L
+#define RBBM_STATUS__RB_CNTX_BUSY                          0x40000000L
+#define RBBM_STATUS__GUI_ACTIVE_MASK                       0x80000000L
+#define RBBM_STATUS__GUI_ACTIVE                            0x80000000L
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE_MASK                0x00000001L
+#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE                     0x00000001L
+#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE_MASK                0x00000002L
+#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE                     0x00000002L
+#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE_MASK                0x00000004L
+#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE                     0x00000004L
+#define RBBM_DSPLY__VSYNC_ACTIVE_MASK                      0x00000008L
+#define RBBM_DSPLY__VSYNC_ACTIVE                           0x00000008L
+#define RBBM_DSPLY__USE_DISPLAY_ID0_MASK                   0x00000010L
+#define RBBM_DSPLY__USE_DISPLAY_ID0                        0x00000010L
+#define RBBM_DSPLY__USE_DISPLAY_ID1_MASK                   0x00000020L
+#define RBBM_DSPLY__USE_DISPLAY_ID1                        0x00000020L
+#define RBBM_DSPLY__USE_DISPLAY_ID2_MASK                   0x00000040L
+#define RBBM_DSPLY__USE_DISPLAY_ID2                        0x00000040L
+#define RBBM_DSPLY__SW_CNTL_MASK                           0x00000080L
+#define RBBM_DSPLY__SW_CNTL                                0x00000080L
+#define RBBM_DSPLY__NUM_BUFS_MASK                          0x00000300L
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__BUFFER_ID_MASK                 0x00000003L
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST_MASK                  0xffffffffL
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK            0x0000ffffL
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK           0x00ff0000L
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK               0xff000000L
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK               0xffffffffL
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0_MASK                   0x000000ffL
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1_MASK                   0x0000000fL
+#define RBBM_PERIPHID1__DESIGNER0_MASK                     0x000000f0L
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1_MASK                     0x0000000fL
+#define RBBM_PERIPHID2__REVISION_MASK                      0x000000f0L
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK           0x00000003L
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK          0x0000000cL
+#define RBBM_PERIPHID3__MH_INTERFACE_MASK                  0x00000030L
+#define RBBM_PERIPHID3__CONTINUATION_MASK                  0x00000080L
+#define RBBM_PERIPHID3__CONTINUATION                       0x00000080L
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT_MASK                       0x000000ffL
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK               0x0001ff00L
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK            0x0000001fL
+#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK                    0x000003e0L
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK                0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_CP                     0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK                0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA                     0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK                0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH                     0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK                0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC                     0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK                0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ                     0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK                0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX                     0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK               0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB                    0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK                0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC                     0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK               0x00010000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT                    0x00010000L
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK    0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE         0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK        0x00000004L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE             0x00000004L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK    0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE         0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK     0x00000010L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE          0x00000010L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK    0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE         0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK     0x00000100L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE          0x00000100L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK        0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE             0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK   0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE        0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK   0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE        0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK   0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE        0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK   0x00004000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE        0x00004000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK   0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE        0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK   0x00010000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE        0x00010000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK   0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE        0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK   0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE        0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK     0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE          0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK    0x00200000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE         0x00200000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK      0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE           0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK    0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE         0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK  0x01000000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE       0x01000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK       0x02000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE            0x02000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK    0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE         0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK        0x08000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE             0x08000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK     0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE          0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK    0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE         0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK    0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE         0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK  0x80000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000L
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK     0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE          0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK     0x00000004L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE          0x00000004L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK   0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE        0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE      0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK   0x00000020L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE        0x00000020L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE     0x00000040L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK      0x00000080L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE           0x00000080L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK    0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE         0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK    0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE         0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK    0x00000800L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE         0x00000800L
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK                0x0000ffffL
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK             0x80000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE                  0x80000000L
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK                   0x00000001L
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE                        0x00000001L
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR_MASK                        0x00000002L
+#define RBBM_DEBUG__IGNORE_RTR                             0x00000002L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK                0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU                     0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK             0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC                  0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK             0x00000010L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI                  0x00000010L
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK         0x00000f00L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK                 0x00010000L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI                      0x00010000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK      0x00020000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI           0x00020000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK     0x00040000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI          0x00040000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK      0x00080000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI           0x00080000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK                    0x00100000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR                         0x00100000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK                   0x00200000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR                        0x00200000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK                    0x00400000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR                         0x00400000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK        0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI             0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK               0x01000000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR                    0x01000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK               0x80000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY                    0x80000000L
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS_MASK                 0x0001fffcL
+#define RBBM_READ_ERROR__READ_REQUESTER_MASK               0x40000000L
+#define RBBM_READ_ERROR__READ_REQUESTER                    0x40000000L
+#define RBBM_READ_ERROR__READ_ERROR_MASK                   0x80000000L
+#define RBBM_READ_ERROR__READ_ERROR                        0x80000000L
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK   0x000000ffL
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK                 0x00000001L
+#define RBBM_INT_CNTL__RDERR_INT_MASK                      0x00000001L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK        0x00000002L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK             0x00000002L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK              0x00080000L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK                   0x00080000L
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK               0x00000001L
+#define RBBM_INT_STATUS__RDERR_INT_STAT                    0x00000001L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK      0x00000002L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT           0x00000002L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK            0x00080000L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT                 0x00080000L
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK_MASK                   0x00000001L
+#define RBBM_INT_ACK__RDERR_INT_ACK                        0x00000001L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK          0x00000002L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK               0x00000002L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK                0x00080000L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK                     0x00080000L
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK                0x00000020L
+#define MASTER_INT_SIGNAL__MH_INT_STAT                     0x00000020L
+#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK                0x40000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT                     0x40000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK              0x80000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT                   0x80000000L
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK     0x0000003fL
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK          0xffffffffL
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK          0x0000ffffL
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE_MASK                           0xffffffe0L
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ_MASK                          0x0000003fL
+#define CP_RB_CNTL__RB_BLKSZ_MASK                          0x00003f00L
+#define CP_RB_CNTL__BUF_SWAP_MASK                          0x00030000L
+#define CP_RB_CNTL__RB_POLL_EN_MASK                        0x00100000L
+#define CP_RB_CNTL__RB_POLL_EN                             0x00100000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK                      0x08000000L
+#define CP_RB_CNTL__RB_NO_UPDATE                           0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                    0x80000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA                         0x80000000L
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                 0xfffffffcL
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR_MASK                           0x000fffffL
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                     0x000fffffL
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR_MASK                           0x000fffffL
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK             0x0fffffffL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK             0xf0000000L
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK                 0xfffffffcL
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE_MASK                         0xfffffffcL
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                       0x000fffffL
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE_MASK                         0xfffffffcL
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                       0x000fffffL
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE_MASK                           0xfffffffcL
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK                         0x000fffffL
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK            0x0000000fL
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK            0x00000f00L
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK             0x000f0000L
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END_MASK                    0x001f0000L
+#define CP_MEQ_THRESHOLDS__ROQ_END_MASK                    0x1f000000L
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK                    0x0000007fL
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK                     0x00007f00L
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK                     0x007f0000L
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST_MASK                      0x0000007fL
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK                         0x0000001fL
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK              0x0000007fL
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK              0x007f0000L
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK           0x0000007fL
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK           0x007f0000L
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK           0x0000007fL
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK           0x007f0000L
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK            0x00000007L
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK            0x00000700L
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK                   0x0000007fL
+#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK                   0x007f0000L
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR_MASK                         0x000003ffL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK                         0x03ff0000L
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK                   0x00000001L
+#define CP_MIU_TAG_STAT__TAG_0_STAT                        0x00000001L
+#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK                   0x00000002L
+#define CP_MIU_TAG_STAT__TAG_1_STAT                        0x00000002L
+#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK                   0x00000004L
+#define CP_MIU_TAG_STAT__TAG_2_STAT                        0x00000004L
+#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK                   0x00000008L
+#define CP_MIU_TAG_STAT__TAG_3_STAT                        0x00000008L
+#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK                   0x00000010L
+#define CP_MIU_TAG_STAT__TAG_4_STAT                        0x00000010L
+#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK                   0x00000020L
+#define CP_MIU_TAG_STAT__TAG_5_STAT                        0x00000020L
+#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK                   0x00000040L
+#define CP_MIU_TAG_STAT__TAG_6_STAT                        0x00000040L
+#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK                   0x00000080L
+#define CP_MIU_TAG_STAT__TAG_7_STAT                        0x00000080L
+#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK                   0x00000100L
+#define CP_MIU_TAG_STAT__TAG_8_STAT                        0x00000100L
+#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK                   0x00000200L
+#define CP_MIU_TAG_STAT__TAG_9_STAT                        0x00000200L
+#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK                  0x00000400L
+#define CP_MIU_TAG_STAT__TAG_10_STAT                       0x00000400L
+#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK                  0x00000800L
+#define CP_MIU_TAG_STAT__TAG_11_STAT                       0x00000800L
+#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK                  0x00001000L
+#define CP_MIU_TAG_STAT__TAG_12_STAT                       0x00001000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK                  0x00002000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT                       0x00002000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK                  0x00004000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT                       0x00004000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK                  0x00008000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT                       0x00008000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK                  0x00010000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT                       0x00010000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK                  0x00020000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT                       0x00020000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK           0x80000000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG                0x80000000L
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX_MASK                       0x0000007fL
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                   0x00030000L
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA_MASK                         0xffffffffL
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX_MASK                        0x0000ffffL
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK            0x02000000L
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY                 0x02000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK            0x04000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY                 0x04000000L
+#define CP_ME_CNTL__ME_HALT_MASK                           0x10000000L
+#define CP_ME_CNTL__ME_HALT                                0x10000000L
+#define CP_ME_CNTL__ME_BUSY_MASK                           0x20000000L
+#define CP_ME_CNTL__ME_BUSY                                0x20000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE_MASK                     0x80000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE                          0x80000000L
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA_MASK                   0xffffffffL
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                   0xffffffffL
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR_MASK                       0xffffffffL
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK             0x007fffffL
+#define CP_DEBUG__PREDICATE_DISABLE_MASK                   0x00800000L
+#define CP_DEBUG__PREDICATE_DISABLE                        0x00800000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK                 0x01000000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE                      0x01000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK             0x02000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE                  0x02000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK                  0x04000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS                       0x04000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK                 0x08000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE                      0x08000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK              0x10000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE                   0x10000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK              0x40000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL                   0x40000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK              0x80000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE                   0x80000000L
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK                0xffffffffL
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK                0xffffffffL
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK                0xffffffffL
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK                0xffffffffL
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK                0xffffffffL
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK                0xffffffffL
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK                0xffffffffL
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK                0xffffffffL
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK_MASK                    0x000000ffL
+#define SCRATCH_UMSK__SCRATCH_SWAP_MASK                    0x00030000L
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR_MASK                    0xffffffe0L
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM                    0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR                   0x00000002L
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM                    0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR                   0x00000002L
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK               0x00000001L
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC                    0x00000001L
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK                0x00000003L
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK                0xfffffffcL
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK                0xffffffffL
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK   0x00000001L
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR        0x00000001L
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK  0x00000003L
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK  0xfffffffcL
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK  0xffffffffL
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK_MASK                      0x00080000L
+#define CP_INT_CNTL__SW_INT_MASK                           0x00080000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK             0x00800000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK                  0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK                0x01000000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK                     0x01000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK        0x02000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK             0x02000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK          0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK               0x04000000L
+#define CP_INT_CNTL__IB_ERROR_MASK_MASK                    0x08000000L
+#define CP_INT_CNTL__IB_ERROR_MASK                         0x08000000L
+#define CP_INT_CNTL__IB2_INT_MASK_MASK                     0x20000000L
+#define CP_INT_CNTL__IB2_INT_MASK                          0x20000000L
+#define CP_INT_CNTL__IB1_INT_MASK_MASK                     0x40000000L
+#define CP_INT_CNTL__IB1_INT_MASK                          0x40000000L
+#define CP_INT_CNTL__RB_INT_MASK_MASK                      0x80000000L
+#define CP_INT_CNTL__RB_INT_MASK                           0x80000000L
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT_MASK                    0x00080000L
+#define CP_INT_STATUS__SW_INT_STAT                         0x00080000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK           0x00800000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT                0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK              0x01000000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT                   0x01000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK      0x02000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT           0x02000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK        0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT             0x04000000L
+#define CP_INT_STATUS__IB_ERROR_STAT_MASK                  0x08000000L
+#define CP_INT_STATUS__IB_ERROR_STAT                       0x08000000L
+#define CP_INT_STATUS__IB2_INT_STAT_MASK                   0x20000000L
+#define CP_INT_STATUS__IB2_INT_STAT                        0x20000000L
+#define CP_INT_STATUS__IB1_INT_STAT_MASK                   0x40000000L
+#define CP_INT_STATUS__IB1_INT_STAT                        0x40000000L
+#define CP_INT_STATUS__RB_INT_STAT_MASK                    0x80000000L
+#define CP_INT_STATUS__RB_INT_STAT                         0x80000000L
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK_MASK                        0x00080000L
+#define CP_INT_ACK__SW_INT_ACK                             0x00080000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK               0x00800000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK                    0x00800000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK                  0x01000000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK                       0x01000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK          0x02000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK               0x02000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK            0x04000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK                 0x04000000L
+#define CP_INT_ACK__IB_ERROR_ACK_MASK                      0x08000000L
+#define CP_INT_ACK__IB_ERROR_ACK                           0x08000000L
+#define CP_INT_ACK__IB2_INT_ACK_MASK                       0x20000000L
+#define CP_INT_ACK__IB2_INT_ACK                            0x20000000L
+#define CP_INT_ACK__IB1_INT_ACK_MASK                       0x40000000L
+#define CP_INT_ACK__IB1_INT_ACK                            0x40000000L
+#define CP_INT_ACK__RB_INT_ACK_MASK                        0x80000000L
+#define CP_INT_ACK__RB_INT_ACK                             0x80000000L
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                 0x000001ffL
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                 0x00ffffffL
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                0x0000000fL
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK          0x00000300L
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK          0x0000003fL
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK               0xffffffffL
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK               0x0000ffffL
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK                   0xffffffffL
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK                   0xffffffffL
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK               0xffffffffL
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK               0xffffffffL
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0_MASK                      0x00000001L
+#define CP_NV_FLAGS_0__DISCARD_0                           0x00000001L
+#define CP_NV_FLAGS_0__END_RCVD_0_MASK                     0x00000002L
+#define CP_NV_FLAGS_0__END_RCVD_0                          0x00000002L
+#define CP_NV_FLAGS_0__DISCARD_1_MASK                      0x00000004L
+#define CP_NV_FLAGS_0__DISCARD_1                           0x00000004L
+#define CP_NV_FLAGS_0__END_RCVD_1_MASK                     0x00000008L
+#define CP_NV_FLAGS_0__END_RCVD_1                          0x00000008L
+#define CP_NV_FLAGS_0__DISCARD_2_MASK                      0x00000010L
+#define CP_NV_FLAGS_0__DISCARD_2                           0x00000010L
+#define CP_NV_FLAGS_0__END_RCVD_2_MASK                     0x00000020L
+#define CP_NV_FLAGS_0__END_RCVD_2                          0x00000020L
+#define CP_NV_FLAGS_0__DISCARD_3_MASK                      0x00000040L
+#define CP_NV_FLAGS_0__DISCARD_3                           0x00000040L
+#define CP_NV_FLAGS_0__END_RCVD_3_MASK                     0x00000080L
+#define CP_NV_FLAGS_0__END_RCVD_3                          0x00000080L
+#define CP_NV_FLAGS_0__DISCARD_4_MASK                      0x00000100L
+#define CP_NV_FLAGS_0__DISCARD_4                           0x00000100L
+#define CP_NV_FLAGS_0__END_RCVD_4_MASK                     0x00000200L
+#define CP_NV_FLAGS_0__END_RCVD_4                          0x00000200L
+#define CP_NV_FLAGS_0__DISCARD_5_MASK                      0x00000400L
+#define CP_NV_FLAGS_0__DISCARD_5                           0x00000400L
+#define CP_NV_FLAGS_0__END_RCVD_5_MASK                     0x00000800L
+#define CP_NV_FLAGS_0__END_RCVD_5                          0x00000800L
+#define CP_NV_FLAGS_0__DISCARD_6_MASK                      0x00001000L
+#define CP_NV_FLAGS_0__DISCARD_6                           0x00001000L
+#define CP_NV_FLAGS_0__END_RCVD_6_MASK                     0x00002000L
+#define CP_NV_FLAGS_0__END_RCVD_6                          0x00002000L
+#define CP_NV_FLAGS_0__DISCARD_7_MASK                      0x00004000L
+#define CP_NV_FLAGS_0__DISCARD_7                           0x00004000L
+#define CP_NV_FLAGS_0__END_RCVD_7_MASK                     0x00008000L
+#define CP_NV_FLAGS_0__END_RCVD_7                          0x00008000L
+#define CP_NV_FLAGS_0__DISCARD_8_MASK                      0x00010000L
+#define CP_NV_FLAGS_0__DISCARD_8                           0x00010000L
+#define CP_NV_FLAGS_0__END_RCVD_8_MASK                     0x00020000L
+#define CP_NV_FLAGS_0__END_RCVD_8                          0x00020000L
+#define CP_NV_FLAGS_0__DISCARD_9_MASK                      0x00040000L
+#define CP_NV_FLAGS_0__DISCARD_9                           0x00040000L
+#define CP_NV_FLAGS_0__END_RCVD_9_MASK                     0x00080000L
+#define CP_NV_FLAGS_0__END_RCVD_9                          0x00080000L
+#define CP_NV_FLAGS_0__DISCARD_10_MASK                     0x00100000L
+#define CP_NV_FLAGS_0__DISCARD_10                          0x00100000L
+#define CP_NV_FLAGS_0__END_RCVD_10_MASK                    0x00200000L
+#define CP_NV_FLAGS_0__END_RCVD_10                         0x00200000L
+#define CP_NV_FLAGS_0__DISCARD_11_MASK                     0x00400000L
+#define CP_NV_FLAGS_0__DISCARD_11                          0x00400000L
+#define CP_NV_FLAGS_0__END_RCVD_11_MASK                    0x00800000L
+#define CP_NV_FLAGS_0__END_RCVD_11                         0x00800000L
+#define CP_NV_FLAGS_0__DISCARD_12_MASK                     0x01000000L
+#define CP_NV_FLAGS_0__DISCARD_12                          0x01000000L
+#define CP_NV_FLAGS_0__END_RCVD_12_MASK                    0x02000000L
+#define CP_NV_FLAGS_0__END_RCVD_12                         0x02000000L
+#define CP_NV_FLAGS_0__DISCARD_13_MASK                     0x04000000L
+#define CP_NV_FLAGS_0__DISCARD_13                          0x04000000L
+#define CP_NV_FLAGS_0__END_RCVD_13_MASK                    0x08000000L
+#define CP_NV_FLAGS_0__END_RCVD_13                         0x08000000L
+#define CP_NV_FLAGS_0__DISCARD_14_MASK                     0x10000000L
+#define CP_NV_FLAGS_0__DISCARD_14                          0x10000000L
+#define CP_NV_FLAGS_0__END_RCVD_14_MASK                    0x20000000L
+#define CP_NV_FLAGS_0__END_RCVD_14                         0x20000000L
+#define CP_NV_FLAGS_0__DISCARD_15_MASK                     0x40000000L
+#define CP_NV_FLAGS_0__DISCARD_15                          0x40000000L
+#define CP_NV_FLAGS_0__END_RCVD_15_MASK                    0x80000000L
+#define CP_NV_FLAGS_0__END_RCVD_15                         0x80000000L
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16_MASK                     0x00000001L
+#define CP_NV_FLAGS_1__DISCARD_16                          0x00000001L
+#define CP_NV_FLAGS_1__END_RCVD_16_MASK                    0x00000002L
+#define CP_NV_FLAGS_1__END_RCVD_16                         0x00000002L
+#define CP_NV_FLAGS_1__DISCARD_17_MASK                     0x00000004L
+#define CP_NV_FLAGS_1__DISCARD_17                          0x00000004L
+#define CP_NV_FLAGS_1__END_RCVD_17_MASK                    0x00000008L
+#define CP_NV_FLAGS_1__END_RCVD_17                         0x00000008L
+#define CP_NV_FLAGS_1__DISCARD_18_MASK                     0x00000010L
+#define CP_NV_FLAGS_1__DISCARD_18                          0x00000010L
+#define CP_NV_FLAGS_1__END_RCVD_18_MASK                    0x00000020L
+#define CP_NV_FLAGS_1__END_RCVD_18                         0x00000020L
+#define CP_NV_FLAGS_1__DISCARD_19_MASK                     0x00000040L
+#define CP_NV_FLAGS_1__DISCARD_19                          0x00000040L
+#define CP_NV_FLAGS_1__END_RCVD_19_MASK                    0x00000080L
+#define CP_NV_FLAGS_1__END_RCVD_19                         0x00000080L
+#define CP_NV_FLAGS_1__DISCARD_20_MASK                     0x00000100L
+#define CP_NV_FLAGS_1__DISCARD_20                          0x00000100L
+#define CP_NV_FLAGS_1__END_RCVD_20_MASK                    0x00000200L
+#define CP_NV_FLAGS_1__END_RCVD_20                         0x00000200L
+#define CP_NV_FLAGS_1__DISCARD_21_MASK                     0x00000400L
+#define CP_NV_FLAGS_1__DISCARD_21                          0x00000400L
+#define CP_NV_FLAGS_1__END_RCVD_21_MASK                    0x00000800L
+#define CP_NV_FLAGS_1__END_RCVD_21                         0x00000800L
+#define CP_NV_FLAGS_1__DISCARD_22_MASK                     0x00001000L
+#define CP_NV_FLAGS_1__DISCARD_22                          0x00001000L
+#define CP_NV_FLAGS_1__END_RCVD_22_MASK                    0x00002000L
+#define CP_NV_FLAGS_1__END_RCVD_22                         0x00002000L
+#define CP_NV_FLAGS_1__DISCARD_23_MASK                     0x00004000L
+#define CP_NV_FLAGS_1__DISCARD_23                          0x00004000L
+#define CP_NV_FLAGS_1__END_RCVD_23_MASK                    0x00008000L
+#define CP_NV_FLAGS_1__END_RCVD_23                         0x00008000L
+#define CP_NV_FLAGS_1__DISCARD_24_MASK                     0x00010000L
+#define CP_NV_FLAGS_1__DISCARD_24                          0x00010000L
+#define CP_NV_FLAGS_1__END_RCVD_24_MASK                    0x00020000L
+#define CP_NV_FLAGS_1__END_RCVD_24                         0x00020000L
+#define CP_NV_FLAGS_1__DISCARD_25_MASK                     0x00040000L
+#define CP_NV_FLAGS_1__DISCARD_25                          0x00040000L
+#define CP_NV_FLAGS_1__END_RCVD_25_MASK                    0x00080000L
+#define CP_NV_FLAGS_1__END_RCVD_25                         0x00080000L
+#define CP_NV_FLAGS_1__DISCARD_26_MASK                     0x00100000L
+#define CP_NV_FLAGS_1__DISCARD_26                          0x00100000L
+#define CP_NV_FLAGS_1__END_RCVD_26_MASK                    0x00200000L
+#define CP_NV_FLAGS_1__END_RCVD_26                         0x00200000L
+#define CP_NV_FLAGS_1__DISCARD_27_MASK                     0x00400000L
+#define CP_NV_FLAGS_1__DISCARD_27                          0x00400000L
+#define CP_NV_FLAGS_1__END_RCVD_27_MASK                    0x00800000L
+#define CP_NV_FLAGS_1__END_RCVD_27                         0x00800000L
+#define CP_NV_FLAGS_1__DISCARD_28_MASK                     0x01000000L
+#define CP_NV_FLAGS_1__DISCARD_28                          0x01000000L
+#define CP_NV_FLAGS_1__END_RCVD_28_MASK                    0x02000000L
+#define CP_NV_FLAGS_1__END_RCVD_28                         0x02000000L
+#define CP_NV_FLAGS_1__DISCARD_29_MASK                     0x04000000L
+#define CP_NV_FLAGS_1__DISCARD_29                          0x04000000L
+#define CP_NV_FLAGS_1__END_RCVD_29_MASK                    0x08000000L
+#define CP_NV_FLAGS_1__END_RCVD_29                         0x08000000L
+#define CP_NV_FLAGS_1__DISCARD_30_MASK                     0x10000000L
+#define CP_NV_FLAGS_1__DISCARD_30                          0x10000000L
+#define CP_NV_FLAGS_1__END_RCVD_30_MASK                    0x20000000L
+#define CP_NV_FLAGS_1__END_RCVD_30                         0x20000000L
+#define CP_NV_FLAGS_1__DISCARD_31_MASK                     0x40000000L
+#define CP_NV_FLAGS_1__DISCARD_31                          0x40000000L
+#define CP_NV_FLAGS_1__END_RCVD_31_MASK                    0x80000000L
+#define CP_NV_FLAGS_1__END_RCVD_31                         0x80000000L
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32_MASK                     0x00000001L
+#define CP_NV_FLAGS_2__DISCARD_32                          0x00000001L
+#define CP_NV_FLAGS_2__END_RCVD_32_MASK                    0x00000002L
+#define CP_NV_FLAGS_2__END_RCVD_32                         0x00000002L
+#define CP_NV_FLAGS_2__DISCARD_33_MASK                     0x00000004L
+#define CP_NV_FLAGS_2__DISCARD_33                          0x00000004L
+#define CP_NV_FLAGS_2__END_RCVD_33_MASK                    0x00000008L
+#define CP_NV_FLAGS_2__END_RCVD_33                         0x00000008L
+#define CP_NV_FLAGS_2__DISCARD_34_MASK                     0x00000010L
+#define CP_NV_FLAGS_2__DISCARD_34                          0x00000010L
+#define CP_NV_FLAGS_2__END_RCVD_34_MASK                    0x00000020L
+#define CP_NV_FLAGS_2__END_RCVD_34                         0x00000020L
+#define CP_NV_FLAGS_2__DISCARD_35_MASK                     0x00000040L
+#define CP_NV_FLAGS_2__DISCARD_35                          0x00000040L
+#define CP_NV_FLAGS_2__END_RCVD_35_MASK                    0x00000080L
+#define CP_NV_FLAGS_2__END_RCVD_35                         0x00000080L
+#define CP_NV_FLAGS_2__DISCARD_36_MASK                     0x00000100L
+#define CP_NV_FLAGS_2__DISCARD_36                          0x00000100L
+#define CP_NV_FLAGS_2__END_RCVD_36_MASK                    0x00000200L
+#define CP_NV_FLAGS_2__END_RCVD_36                         0x00000200L
+#define CP_NV_FLAGS_2__DISCARD_37_MASK                     0x00000400L
+#define CP_NV_FLAGS_2__DISCARD_37                          0x00000400L
+#define CP_NV_FLAGS_2__END_RCVD_37_MASK                    0x00000800L
+#define CP_NV_FLAGS_2__END_RCVD_37                         0x00000800L
+#define CP_NV_FLAGS_2__DISCARD_38_MASK                     0x00001000L
+#define CP_NV_FLAGS_2__DISCARD_38                          0x00001000L
+#define CP_NV_FLAGS_2__END_RCVD_38_MASK                    0x00002000L
+#define CP_NV_FLAGS_2__END_RCVD_38                         0x00002000L
+#define CP_NV_FLAGS_2__DISCARD_39_MASK                     0x00004000L
+#define CP_NV_FLAGS_2__DISCARD_39                          0x00004000L
+#define CP_NV_FLAGS_2__END_RCVD_39_MASK                    0x00008000L
+#define CP_NV_FLAGS_2__END_RCVD_39                         0x00008000L
+#define CP_NV_FLAGS_2__DISCARD_40_MASK                     0x00010000L
+#define CP_NV_FLAGS_2__DISCARD_40                          0x00010000L
+#define CP_NV_FLAGS_2__END_RCVD_40_MASK                    0x00020000L
+#define CP_NV_FLAGS_2__END_RCVD_40                         0x00020000L
+#define CP_NV_FLAGS_2__DISCARD_41_MASK                     0x00040000L
+#define CP_NV_FLAGS_2__DISCARD_41                          0x00040000L
+#define CP_NV_FLAGS_2__END_RCVD_41_MASK                    0x00080000L
+#define CP_NV_FLAGS_2__END_RCVD_41                         0x00080000L
+#define CP_NV_FLAGS_2__DISCARD_42_MASK                     0x00100000L
+#define CP_NV_FLAGS_2__DISCARD_42                          0x00100000L
+#define CP_NV_FLAGS_2__END_RCVD_42_MASK                    0x00200000L
+#define CP_NV_FLAGS_2__END_RCVD_42                         0x00200000L
+#define CP_NV_FLAGS_2__DISCARD_43_MASK                     0x00400000L
+#define CP_NV_FLAGS_2__DISCARD_43                          0x00400000L
+#define CP_NV_FLAGS_2__END_RCVD_43_MASK                    0x00800000L
+#define CP_NV_FLAGS_2__END_RCVD_43                         0x00800000L
+#define CP_NV_FLAGS_2__DISCARD_44_MASK                     0x01000000L
+#define CP_NV_FLAGS_2__DISCARD_44                          0x01000000L
+#define CP_NV_FLAGS_2__END_RCVD_44_MASK                    0x02000000L
+#define CP_NV_FLAGS_2__END_RCVD_44                         0x02000000L
+#define CP_NV_FLAGS_2__DISCARD_45_MASK                     0x04000000L
+#define CP_NV_FLAGS_2__DISCARD_45                          0x04000000L
+#define CP_NV_FLAGS_2__END_RCVD_45_MASK                    0x08000000L
+#define CP_NV_FLAGS_2__END_RCVD_45                         0x08000000L
+#define CP_NV_FLAGS_2__DISCARD_46_MASK                     0x10000000L
+#define CP_NV_FLAGS_2__DISCARD_46                          0x10000000L
+#define CP_NV_FLAGS_2__END_RCVD_46_MASK                    0x20000000L
+#define CP_NV_FLAGS_2__END_RCVD_46                         0x20000000L
+#define CP_NV_FLAGS_2__DISCARD_47_MASK                     0x40000000L
+#define CP_NV_FLAGS_2__DISCARD_47                          0x40000000L
+#define CP_NV_FLAGS_2__END_RCVD_47_MASK                    0x80000000L
+#define CP_NV_FLAGS_2__END_RCVD_47                         0x80000000L
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48_MASK                     0x00000001L
+#define CP_NV_FLAGS_3__DISCARD_48                          0x00000001L
+#define CP_NV_FLAGS_3__END_RCVD_48_MASK                    0x00000002L
+#define CP_NV_FLAGS_3__END_RCVD_48                         0x00000002L
+#define CP_NV_FLAGS_3__DISCARD_49_MASK                     0x00000004L
+#define CP_NV_FLAGS_3__DISCARD_49                          0x00000004L
+#define CP_NV_FLAGS_3__END_RCVD_49_MASK                    0x00000008L
+#define CP_NV_FLAGS_3__END_RCVD_49                         0x00000008L
+#define CP_NV_FLAGS_3__DISCARD_50_MASK                     0x00000010L
+#define CP_NV_FLAGS_3__DISCARD_50                          0x00000010L
+#define CP_NV_FLAGS_3__END_RCVD_50_MASK                    0x00000020L
+#define CP_NV_FLAGS_3__END_RCVD_50                         0x00000020L
+#define CP_NV_FLAGS_3__DISCARD_51_MASK                     0x00000040L
+#define CP_NV_FLAGS_3__DISCARD_51                          0x00000040L
+#define CP_NV_FLAGS_3__END_RCVD_51_MASK                    0x00000080L
+#define CP_NV_FLAGS_3__END_RCVD_51                         0x00000080L
+#define CP_NV_FLAGS_3__DISCARD_52_MASK                     0x00000100L
+#define CP_NV_FLAGS_3__DISCARD_52                          0x00000100L
+#define CP_NV_FLAGS_3__END_RCVD_52_MASK                    0x00000200L
+#define CP_NV_FLAGS_3__END_RCVD_52                         0x00000200L
+#define CP_NV_FLAGS_3__DISCARD_53_MASK                     0x00000400L
+#define CP_NV_FLAGS_3__DISCARD_53                          0x00000400L
+#define CP_NV_FLAGS_3__END_RCVD_53_MASK                    0x00000800L
+#define CP_NV_FLAGS_3__END_RCVD_53                         0x00000800L
+#define CP_NV_FLAGS_3__DISCARD_54_MASK                     0x00001000L
+#define CP_NV_FLAGS_3__DISCARD_54                          0x00001000L
+#define CP_NV_FLAGS_3__END_RCVD_54_MASK                    0x00002000L
+#define CP_NV_FLAGS_3__END_RCVD_54                         0x00002000L
+#define CP_NV_FLAGS_3__DISCARD_55_MASK                     0x00004000L
+#define CP_NV_FLAGS_3__DISCARD_55                          0x00004000L
+#define CP_NV_FLAGS_3__END_RCVD_55_MASK                    0x00008000L
+#define CP_NV_FLAGS_3__END_RCVD_55                         0x00008000L
+#define CP_NV_FLAGS_3__DISCARD_56_MASK                     0x00010000L
+#define CP_NV_FLAGS_3__DISCARD_56                          0x00010000L
+#define CP_NV_FLAGS_3__END_RCVD_56_MASK                    0x00020000L
+#define CP_NV_FLAGS_3__END_RCVD_56                         0x00020000L
+#define CP_NV_FLAGS_3__DISCARD_57_MASK                     0x00040000L
+#define CP_NV_FLAGS_3__DISCARD_57                          0x00040000L
+#define CP_NV_FLAGS_3__END_RCVD_57_MASK                    0x00080000L
+#define CP_NV_FLAGS_3__END_RCVD_57                         0x00080000L
+#define CP_NV_FLAGS_3__DISCARD_58_MASK                     0x00100000L
+#define CP_NV_FLAGS_3__DISCARD_58                          0x00100000L
+#define CP_NV_FLAGS_3__END_RCVD_58_MASK                    0x00200000L
+#define CP_NV_FLAGS_3__END_RCVD_58                         0x00200000L
+#define CP_NV_FLAGS_3__DISCARD_59_MASK                     0x00400000L
+#define CP_NV_FLAGS_3__DISCARD_59                          0x00400000L
+#define CP_NV_FLAGS_3__END_RCVD_59_MASK                    0x00800000L
+#define CP_NV_FLAGS_3__END_RCVD_59                         0x00800000L
+#define CP_NV_FLAGS_3__DISCARD_60_MASK                     0x01000000L
+#define CP_NV_FLAGS_3__DISCARD_60                          0x01000000L
+#define CP_NV_FLAGS_3__END_RCVD_60_MASK                    0x02000000L
+#define CP_NV_FLAGS_3__END_RCVD_60                         0x02000000L
+#define CP_NV_FLAGS_3__DISCARD_61_MASK                     0x04000000L
+#define CP_NV_FLAGS_3__DISCARD_61                          0x04000000L
+#define CP_NV_FLAGS_3__END_RCVD_61_MASK                    0x08000000L
+#define CP_NV_FLAGS_3__END_RCVD_61                         0x08000000L
+#define CP_NV_FLAGS_3__DISCARD_62_MASK                     0x10000000L
+#define CP_NV_FLAGS_3__DISCARD_62                          0x10000000L
+#define CP_NV_FLAGS_3__END_RCVD_62_MASK                    0x20000000L
+#define CP_NV_FLAGS_3__END_RCVD_62                         0x20000000L
+#define CP_NV_FLAGS_3__DISCARD_63_MASK                     0x40000000L
+#define CP_NV_FLAGS_3__DISCARD_63                          0x40000000L
+#define CP_NV_FLAGS_3__END_RCVD_63_MASK                    0x80000000L
+#define CP_NV_FLAGS_3__END_RCVD_63                         0x80000000L
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK       0x0000001fL
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK         0xffffffffL
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER_MASK                      0xffffffffL
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY_MASK                          0x00000001L
+#define CP_STAT__MIU_WR_BUSY                               0x00000001L
+#define CP_STAT__MIU_RD_REQ_BUSY_MASK                      0x00000002L
+#define CP_STAT__MIU_RD_REQ_BUSY                           0x00000002L
+#define CP_STAT__MIU_RD_RETURN_BUSY_MASK                   0x00000004L
+#define CP_STAT__MIU_RD_RETURN_BUSY                        0x00000004L
+#define CP_STAT__RBIU_BUSY_MASK                            0x00000008L
+#define CP_STAT__RBIU_BUSY                                 0x00000008L
+#define CP_STAT__RCIU_BUSY_MASK                            0x00000010L
+#define CP_STAT__RCIU_BUSY                                 0x00000010L
+#define CP_STAT__CSF_RING_BUSY_MASK                        0x00000020L
+#define CP_STAT__CSF_RING_BUSY                             0x00000020L
+#define CP_STAT__CSF_INDIRECTS_BUSY_MASK                   0x00000040L
+#define CP_STAT__CSF_INDIRECTS_BUSY                        0x00000040L
+#define CP_STAT__CSF_INDIRECT2_BUSY_MASK                   0x00000080L
+#define CP_STAT__CSF_INDIRECT2_BUSY                        0x00000080L
+#define CP_STAT__CSF_ST_BUSY_MASK                          0x00000200L
+#define CP_STAT__CSF_ST_BUSY                               0x00000200L
+#define CP_STAT__CSF_BUSY_MASK                             0x00000400L
+#define CP_STAT__CSF_BUSY                                  0x00000400L
+#define CP_STAT__RING_QUEUE_BUSY_MASK                      0x00000800L
+#define CP_STAT__RING_QUEUE_BUSY                           0x00000800L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK                 0x00001000L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY                      0x00001000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK                 0x00002000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY                      0x00002000L
+#define CP_STAT__ST_QUEUE_BUSY_MASK                        0x00010000L
+#define CP_STAT__ST_QUEUE_BUSY                             0x00010000L
+#define CP_STAT__PFP_BUSY_MASK                             0x00020000L
+#define CP_STAT__PFP_BUSY                                  0x00020000L
+#define CP_STAT__MEQ_RING_BUSY_MASK                        0x00040000L
+#define CP_STAT__MEQ_RING_BUSY                             0x00040000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK                   0x00080000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY                        0x00080000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK                   0x00100000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY                        0x00100000L
+#define CP_STAT__MIU_WC_STALL_MASK                         0x00200000L
+#define CP_STAT__MIU_WC_STALL                              0x00200000L
+#define CP_STAT__CP_NRT_BUSY_MASK                          0x00400000L
+#define CP_STAT__CP_NRT_BUSY                               0x00400000L
+#define CP_STAT___3D_BUSY_MASK                             0x00800000L
+#define CP_STAT___3D_BUSY                                  0x00800000L
+#define CP_STAT__ME_BUSY_MASK                              0x04000000L
+#define CP_STAT__ME_BUSY                                   0x04000000L
+#define CP_STAT__ME_WC_BUSY_MASK                           0x20000000L
+#define CP_STAT__ME_WC_BUSY                                0x20000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK              0x40000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY                   0x40000000L
+#define CP_STAT__CP_BUSY_MASK                              0x80000000L
+#define CP_STAT__CP_BUSY                                   0x80000000L
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE_MASK                          0xffffffffL
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE_MASK                          0xffffffffL
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK           0x000000ffL
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK       0x00000100L
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA            0x00000100L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK             0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA                  0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK             0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA                  0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK             0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA                  0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK             0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA                  0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK             0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA                  0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK             0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA                  0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK             0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA                  0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK             0x00010000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA                  0x00010000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK               0x02000000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA                    0x02000000L
+#define COHER_STATUS_PM4__STATUS_MASK                      0x80000000L
+#define COHER_STATUS_PM4__STATUS                           0x80000000L
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE_MASK                         0xffffffffL
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE_MASK                         0xffffffffL
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK          0x000000ffL
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK      0x00000100L
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA           0x00000100L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK            0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA                 0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK            0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA                 0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK            0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA                 0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK            0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA                 0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK            0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA                 0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK            0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA                 0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK            0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA                 0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK            0x00010000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA                 0x00010000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK              0x02000000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA                   0x02000000L
+#define COHER_STATUS_HOST__STATUS_MASK                     0x80000000L
+#define COHER_STATUS_HOST__STATUS                          0x80000000L
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0_MASK                0xfffff000L
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1_MASK                0xfffff000L
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2_MASK                0xfffff000L
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3_MASK                0xfffff000L
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4_MASK                0xfffff000L
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5_MASK                0xfffff000L
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6_MASK                0xfffff000L
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7_MASK                0xfffff000L
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH_MASK                0x00003fffL
+#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK                 0x0000c000L
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT_MASK                   0x0000000fL
+#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK               0x00000030L
+#define RB_COLOR_INFO__COLOR_LINEAR_MASK                   0x00000040L
+#define RB_COLOR_INFO__COLOR_LINEAR                        0x00000040L
+#define RB_COLOR_INFO__COLOR_ENDIAN_MASK                   0x00000180L
+#define RB_COLOR_INFO__COLOR_SWAP_MASK                     0x00000600L
+#define RB_COLOR_INFO__COLOR_BASE_MASK                     0xfffff000L
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK                   0x00000001L
+#define RB_DEPTH_INFO__DEPTH_FORMAT                        0x00000001L
+#define RB_DEPTH_INFO__DEPTH_BASE_MASK                     0xfffff000L
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF_MASK                 0x000000ffL
+#define RB_STENCILREFMASK__STENCILMASK_MASK                0x0000ff00L
+#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK           0x00ff0000L
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF_MASK                       0xffffffffL
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED_MASK                      0x00000001L
+#define RB_COLOR_MASK__WRITE_RED                           0x00000001L
+#define RB_COLOR_MASK__WRITE_GREEN_MASK                    0x00000002L
+#define RB_COLOR_MASK__WRITE_GREEN                         0x00000002L
+#define RB_COLOR_MASK__WRITE_BLUE_MASK                     0x00000004L
+#define RB_COLOR_MASK__WRITE_BLUE                          0x00000004L
+#define RB_COLOR_MASK__WRITE_ALPHA_MASK                    0x00000008L
+#define RB_COLOR_MASK__WRITE_ALPHA                         0x00000008L
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED_MASK                       0x000000ffL
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN_MASK                   0x000000ffL
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE_MASK                     0x000000ffL
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK                   0x000000ffL
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED_MASK                         0x000000ffL
+#define RB_FOG_COLOR__FOG_GREEN_MASK                       0x0000ff00L
+#define RB_FOG_COLOR__FOG_BLUE_MASK                        0x00ff0000L
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK           0x000000ffL
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK          0x0000ff00L
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK     0x00ff0000L
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK               0x00000001L
+#define RB_DEPTHCONTROL__STENCIL_ENABLE                    0x00000001L
+#define RB_DEPTHCONTROL__Z_ENABLE_MASK                     0x00000002L
+#define RB_DEPTHCONTROL__Z_ENABLE                          0x00000002L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK               0x00000004L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE                    0x00000004L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK               0x00000008L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE                    0x00000008L
+#define RB_DEPTHCONTROL__ZFUNC_MASK                        0x00000070L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK              0x00000080L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE                   0x00000080L
+#define RB_DEPTHCONTROL__STENCILFUNC_MASK                  0x00000700L
+#define RB_DEPTHCONTROL__STENCILFAIL_MASK                  0x00003800L
+#define RB_DEPTHCONTROL__STENCILZPASS_MASK                 0x0001c000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_MASK                 0x000e0000L
+#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK               0x00700000L
+#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK               0x03800000L
+#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK              0x1c000000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK              0xe0000000L
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK               0x0000001fL
+#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK               0x000000e0L
+#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK              0x00001f00L
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK               0x001f0000L
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK               0x00e00000L
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK              0x1f000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK           0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE                0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_MASK                  0x40000000L
+#define RB_BLENDCONTROL__BLEND_FORCE                       0x40000000L
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC_MASK                   0x00000007L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK            0x00000008L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE                 0x00000008L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK         0x00000010L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE              0x00000010L
+#define RB_COLORCONTROL__BLEND_DISABLE_MASK                0x00000020L
+#define RB_COLORCONTROL__BLEND_DISABLE                     0x00000020L
+#define RB_COLORCONTROL__FOG_ENABLE_MASK                   0x00000040L
+#define RB_COLORCONTROL__FOG_ENABLE                        0x00000040L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK               0x00000080L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG                    0x00000080L
+#define RB_COLORCONTROL__ROP_CODE_MASK                     0x00000f00L
+#define RB_COLORCONTROL__DITHER_MODE_MASK                  0x00003000L
+#define RB_COLORCONTROL__DITHER_TYPE_MASK                  0x0000c000L
+#define RB_COLORCONTROL__PIXEL_FOG_MASK                    0x00010000L
+#define RB_COLORCONTROL__PIXEL_FOG                         0x00010000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK        0x03000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK        0x0c000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK        0x30000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK        0xc0000000L
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE_MASK                    0x00000007L
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK           0xffffffffL
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK           0x00000007L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK           0x00000008L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE                0x00000008L
+#define RB_COPY_CONTROL__CLEAR_MASK_MASK                   0x000000f0L
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK             0xfffff000L
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK           0x000001ffL
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK           0x00000007L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK           0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR                0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK           0x000000f0L
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK             0x00000300L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK      0x00000c00L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK      0x00003000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK        0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED             0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK      0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN           0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK       0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE            0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK      0x00020000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA           0x00020000L
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK           0x00001fffL
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK           0x03ffe000L
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                   0xffffffffL
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK       0x00000001L
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT            0x00000001L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK        0x00000002L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT             0x00000002L
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK       0xffffffffL
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK       0x00000001L
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE            0x00000001L
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK           0x00000006L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK              0x00000008L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM                   0x00000008L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK      0x00000020L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP           0x00000020L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK      0x00000040L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP           0x00000040L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK             0x00000080L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE                  0x00000080L
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK              0x00001f00L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK              0x00004000L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE                   0x00004000L
+#define RB_BC_CONTROL__CRC_MODE_MASK                       0x00008000L
+#define RB_BC_CONTROL__CRC_MODE                            0x00008000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK        0x00010000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS             0x00010000L
+#define RB_BC_CONTROL__DISABLE_ACCUM_MASK                  0x00020000L
+#define RB_BC_CONTROL__DISABLE_ACCUM                       0x00020000L
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK               0x003c0000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK      0x00400000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE           0x00400000L
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK          0x07800000L
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK      0x18000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK  0x20000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000L
+#define RB_BC_CONTROL__RESERVED9_MASK                      0x40000000L
+#define RB_BC_CONTROL__RESERVED9                           0x40000000L
+#define RB_BC_CONTROL__RESERVED10_MASK                     0x80000000L
+#define RB_BC_CONTROL__RESERVED10                          0x80000000L
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE_MASK                     0x0000000fL
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK             0x00000030L
+#define RB_EDRAM_INFO__EDRAM_RANGE_MASK                    0xffffc000L
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA_MASK                      0xffffffffL
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK                0x00000001L
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE                     0x00000001L
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK_MASK                         0xffffffffL
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK               0xffffffffL
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK               0xffffffffL
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK             0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL                  0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK             0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL                  0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK             0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL                  0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK             0x00000008L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL                  0x00000008L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK            0x00000010L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL                 0x00000010L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK            0x00000020L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL                 0x00000020L
+#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK                     0x00000040L
+#define RB_DEBUG_0__RDREQ_Z1_FULL                          0x00000040L
+#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK                     0x00000080L
+#define RB_DEBUG_0__RDREQ_Z0_FULL                          0x00000080L
+#define RB_DEBUG_0__RDREQ_C1_FULL_MASK                     0x00000100L
+#define RB_DEBUG_0__RDREQ_C1_FULL                          0x00000100L
+#define RB_DEBUG_0__RDREQ_C0_FULL_MASK                     0x00000200L
+#define RB_DEBUG_0__RDREQ_C0_FULL                          0x00000200L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK            0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL                 0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK            0x00000800L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL                 0x00000800L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK            0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL                 0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK            0x00002000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL                 0x00002000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK                0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL                     0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK                0x00008000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL                     0x00008000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK                     0x00010000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL                          0x00010000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK                     0x00020000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL                          0x00020000L
+#define RB_DEBUG_0__WRREQ_C1_FULL_MASK                     0x00040000L
+#define RB_DEBUG_0__WRREQ_C1_FULL                          0x00040000L
+#define RB_DEBUG_0__WRREQ_C0_FULL_MASK                     0x00080000L
+#define RB_DEBUG_0__WRREQ_C0_FULL                          0x00080000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK              0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL                   0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK              0x00200000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL                   0x00200000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK              0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL                   0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK              0x00800000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL                   0x00800000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK           0x01000000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL                0x01000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK           0x02000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL                0x02000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL_MASK                     0x04000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL                          0x04000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL_MASK                     0x08000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL                          0x08000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK                    0x10000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL                         0x10000000L
+#define RB_DEBUG_0__C_REQ_FULL_MASK                        0x20000000L
+#define RB_DEBUG_0__C_REQ_FULL                             0x20000000L
+#define RB_DEBUG_0__C_MASK_FULL_MASK                       0x40000000L
+#define RB_DEBUG_0__C_MASK_FULL                            0x40000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK                   0x80000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL                        0x80000000L
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK                0x00000001L
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY                     0x00000001L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK                0x00000002L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY                     0x00000002L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK                0x00000004L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY                     0x00000004L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK                0x00000008L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY                     0x00000008L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK           0x00000010L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY                0x00000010L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK           0x00000020L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY                0x00000020L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK                    0x00000040L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY                         0x00000040L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK                    0x00000080L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY                         0x00000080L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK                    0x00000100L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY                         0x00000100L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK                    0x00000200L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY                         0x00000200L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK           0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY                0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK           0x00000800L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY                0x00000800L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK           0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY                0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK           0x00002000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY                0x00002000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK               0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY                    0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK               0x00008000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY                    0x00008000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK                    0x00010000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY                         0x00010000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK                    0x00020000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY                         0x00020000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK                0x00040000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY                     0x00040000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK                0x00080000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY                     0x00080000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK             0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY                  0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY                  0x00200000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY                  0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK             0x00800000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY                  0x00800000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK          0x01000000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY               0x01000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK          0x02000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY               0x02000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK                    0x04000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY                         0x04000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK                    0x08000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY                         0x08000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK                   0x10000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY                        0x10000000L
+#define RB_DEBUG_1__C_REQ_EMPTY_MASK                       0x20000000L
+#define RB_DEBUG_1__C_REQ_EMPTY                            0x20000000L
+#define RB_DEBUG_1__C_MASK_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_1__C_MASK_EMPTY                           0x40000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK                  0x80000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY                       0x80000000L
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK                   0x0000000fL
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK                 0x000007f0L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK                   0x00000800L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG                        0x00000800L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK                 0x00001000L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG                      0x00001000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK                0x00002000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT                     0x00002000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK                   0x00004000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL                        0x00004000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK                0x00008000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL                     0x00008000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK                0x00010000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL                     0x00010000L
+#define RB_DEBUG_2__Z0_MASK_FULL_MASK                      0x00020000L
+#define RB_DEBUG_2__Z0_MASK_FULL                           0x00020000L
+#define RB_DEBUG_2__Z1_MASK_FULL_MASK                      0x00040000L
+#define RB_DEBUG_2__Z1_MASK_FULL                           0x00040000L
+#define RB_DEBUG_2__Z0_REQ_FULL_MASK                       0x00080000L
+#define RB_DEBUG_2__Z0_REQ_FULL                            0x00080000L
+#define RB_DEBUG_2__Z1_REQ_FULL_MASK                       0x00100000L
+#define RB_DEBUG_2__Z1_REQ_FULL                            0x00100000L
+#define RB_DEBUG_2__Z_SAMP_FULL_MASK                       0x00200000L
+#define RB_DEBUG_2__Z_SAMP_FULL                            0x00200000L
+#define RB_DEBUG_2__Z_TILE_FULL_MASK                       0x00400000L
+#define RB_DEBUG_2__Z_TILE_FULL                            0x00400000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK                  0x00800000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY                       0x00800000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK               0x01000000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY                    0x01000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK               0x02000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY                    0x02000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK                     0x04000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY                          0x04000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK                     0x08000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY                          0x08000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK                      0x10000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY                           0x10000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK                      0x20000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY                           0x20000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY                           0x40000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY_MASK                      0x80000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY                           0x80000000L
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID_MASK                       0x0000000fL
+#define RB_DEBUG_3__ACCUM_FLUSHING_MASK                    0x000000f0L
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK           0x00003f00L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK             0x00004000L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID                  0x00004000L
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK               0x00078000L
+#define RB_DEBUG_3__SHD_FULL_MASK                          0x00080000L
+#define RB_DEBUG_3__SHD_FULL                               0x00080000L
+#define RB_DEBUG_3__SHD_EMPTY_MASK                         0x00100000L
+#define RB_DEBUG_3__SHD_EMPTY                              0x00100000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY                  0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY                  0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK              0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL                   0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK              0x01000000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL                   0x01000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK                  0x02000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY                       0x02000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK                  0x04000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY                       0x04000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK                   0x08000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL                        0x08000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK                   0x10000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL                        0x10000000L
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK               0x00000001L
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG                    0x00000001L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK               0x00000002L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG                    0x00000002L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK             0x00000004L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG                  0x00000004L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK             0x00000008L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG                  0x00000008L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK             0x00000010L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY                  0x00000010L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK            0x00000020L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY                 0x00000020L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK              0x00000040L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL                   0x00000040L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK             0x00000080L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL                  0x00000080L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK       0x00000100L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW            0x00000100L
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK               0x00001e00L
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK             0x00000001L
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR                  0x00000001L
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP   0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK     0x00000600L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h
new file mode 100644
index 00000000000..6a229a8e79e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h
@@ -0,0 +1,581 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamato_OFFSET_HEADER
+#define _yamato_OFFSET_HEADER
+
+
+// Registers from PA block
+
+#define mmPA_CL_VPORT_XSCALE           0x210F
+#define mmPA_CL_VPORT_XOFFSET          0x2110
+#define mmPA_CL_VPORT_YSCALE           0x2111
+#define mmPA_CL_VPORT_YOFFSET          0x2112
+#define mmPA_CL_VPORT_ZSCALE           0x2113
+#define mmPA_CL_VPORT_ZOFFSET          0x2114
+#define mmPA_CL_VTE_CNTL               0x2206
+#define mmPA_CL_CLIP_CNTL              0x2204
+#define mmPA_CL_GB_VERT_CLIP_ADJ       0x2303
+#define mmPA_CL_GB_VERT_DISC_ADJ       0x2304
+#define mmPA_CL_GB_HORZ_CLIP_ADJ       0x2305
+#define mmPA_CL_GB_HORZ_DISC_ADJ       0x2306
+#define mmPA_CL_ENHANCE                0x0C85
+#define mmPA_SC_ENHANCE                0x0CA5
+#define mmPA_SU_VTX_CNTL               0x2302
+#define mmPA_SU_POINT_SIZE             0x2280
+#define mmPA_SU_POINT_MINMAX           0x2281
+#define mmPA_SU_LINE_CNTL              0x2282
+#define mmPA_SU_SC_MODE_CNTL           0x2205
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
+#define mmPA_SU_PERFCOUNTER0_SELECT    0x0C88
+#define mmPA_SU_PERFCOUNTER1_SELECT    0x0C89
+#define mmPA_SU_PERFCOUNTER2_SELECT    0x0C8A
+#define mmPA_SU_PERFCOUNTER3_SELECT    0x0C8B
+#define mmPA_SU_PERFCOUNTER0_LOW       0x0C8C
+#define mmPA_SU_PERFCOUNTER0_HI        0x0C8D
+#define mmPA_SU_PERFCOUNTER1_LOW       0x0C8E
+#define mmPA_SU_PERFCOUNTER1_HI        0x0C8F
+#define mmPA_SU_PERFCOUNTER2_LOW       0x0C90
+#define mmPA_SU_PERFCOUNTER2_HI        0x0C91
+#define mmPA_SU_PERFCOUNTER3_LOW       0x0C92
+#define mmPA_SU_PERFCOUNTER3_HI        0x0C93
+#define mmPA_SC_WINDOW_OFFSET          0x2080
+#define mmPA_SC_AA_CONFIG              0x2301
+#define mmPA_SC_AA_MASK                0x2312
+#define mmPA_SC_LINE_STIPPLE           0x2283
+#define mmPA_SC_LINE_CNTL              0x2300
+#define mmPA_SC_WINDOW_SCISSOR_TL      0x2081
+#define mmPA_SC_WINDOW_SCISSOR_BR      0x2082
+#define mmPA_SC_SCREEN_SCISSOR_TL      0x200E
+#define mmPA_SC_SCREEN_SCISSOR_BR      0x200F
+#define mmPA_SC_VIZ_QUERY              0x2293
+#define mmPA_SC_VIZ_QUERY_STATUS       0x0C44
+#define mmPA_SC_LINE_STIPPLE_STATE     0x0C40
+#define mmPA_SC_PERFCOUNTER0_SELECT    0x0C98
+#define mmPA_SC_PERFCOUNTER0_LOW       0x0C99
+#define mmPA_SC_PERFCOUNTER0_HI        0x0C9A
+#define mmPA_CL_CNTL_STATUS            0x0C84
+#define mmPA_SU_CNTL_STATUS            0x0C94
+#define mmPA_SC_CNTL_STATUS            0x0CA4
+#define mmPA_SU_DEBUG_CNTL             0x0C80
+#define mmPA_SU_DEBUG_DATA             0x0C81
+#define mmPA_SC_DEBUG_CNTL             0x0C82
+#define mmPA_SC_DEBUG_DATA             0x0C83
+
+
+// Registers from VGT block
+
+#define mmGFX_COPY_STATE               0x21F4
+#define mmVGT_DRAW_INITIATOR           0x21FC
+#define mmVGT_EVENT_INITIATOR          0x21F9
+#define mmVGT_DMA_BASE                 0x21FA
+#define mmVGT_DMA_SIZE                 0x21FB
+#define mmVGT_BIN_BASE                 0x21FE
+#define mmVGT_BIN_SIZE                 0x21FF
+#define mmVGT_CURRENT_BIN_ID_MIN       0x2207
+#define mmVGT_CURRENT_BIN_ID_MAX       0x2203
+#define mmVGT_IMMED_DATA               0x21FD
+#define mmVGT_MAX_VTX_INDX             0x2100
+#define mmVGT_MIN_VTX_INDX             0x2101
+#define mmVGT_INDX_OFFSET              0x2102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL  0x2316
+#define mmVGT_OUT_DEALLOC_CNTL         0x2317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103
+#define mmVGT_ENHANCE                  0x2294
+#define mmVGT_VTX_VECT_EJECT_REG       0x0C2C
+#define mmVGT_LAST_COPY_STATE          0x0C30
+#define mmVGT_DEBUG_CNTL               0x0C38
+#define mmVGT_DEBUG_DATA               0x0C39
+#define mmVGT_CNTL_STATUS              0x0C3C
+#define mmVGT_CRC_SQ_DATA              0x0C3A
+#define mmVGT_CRC_SQ_CTRL              0x0C3B
+#define mmVGT_PERFCOUNTER0_SELECT      0x0C48
+#define mmVGT_PERFCOUNTER1_SELECT      0x0C49
+#define mmVGT_PERFCOUNTER2_SELECT      0x0C4A
+#define mmVGT_PERFCOUNTER3_SELECT      0x0C4B
+#define mmVGT_PERFCOUNTER0_LOW         0x0C4C
+#define mmVGT_PERFCOUNTER1_LOW         0x0C4E
+#define mmVGT_PERFCOUNTER2_LOW         0x0C50
+#define mmVGT_PERFCOUNTER3_LOW         0x0C52
+#define mmVGT_PERFCOUNTER0_HI          0x0C4D
+#define mmVGT_PERFCOUNTER1_HI          0x0C4F
+#define mmVGT_PERFCOUNTER2_HI          0x0C51
+#define mmVGT_PERFCOUNTER3_HI          0x0C53
+
+
+// Registers from TP block
+
+#define mmTC_CNTL_STATUS               0x0E00
+#define mmTCR_CHICKEN                  0x0E02
+#define mmTCF_CHICKEN                  0x0E03
+#define mmTCM_CHICKEN                  0x0E04
+#define mmTCR_PERFCOUNTER0_SELECT      0x0E05
+#define mmTCR_PERFCOUNTER1_SELECT      0x0E08
+#define mmTCR_PERFCOUNTER0_HI          0x0E06
+#define mmTCR_PERFCOUNTER1_HI          0x0E09
+#define mmTCR_PERFCOUNTER0_LOW         0x0E07
+#define mmTCR_PERFCOUNTER1_LOW         0x0E0A
+#define mmTP_TC_CLKGATE_CNTL           0x0E17
+#define mmTPC_CNTL_STATUS              0x0E18
+#define mmTPC_DEBUG0                   0x0E19
+#define mmTPC_DEBUG1                   0x0E1A
+#define mmTPC_CHICKEN                  0x0E1B
+#define mmTP0_CNTL_STATUS              0x0E1C
+#define mmTP0_DEBUG                    0x0E1D
+#define mmTP0_CHICKEN                  0x0E1E
+#define mmTP0_PERFCOUNTER0_SELECT      0x0E1F
+#define mmTP0_PERFCOUNTER0_HI          0x0E20
+#define mmTP0_PERFCOUNTER0_LOW         0x0E21
+#define mmTP0_PERFCOUNTER1_SELECT      0x0E22
+#define mmTP0_PERFCOUNTER1_HI          0x0E23
+#define mmTP0_PERFCOUNTER1_LOW         0x0E24
+#define mmTCM_PERFCOUNTER0_SELECT      0x0E54
+#define mmTCM_PERFCOUNTER1_SELECT      0x0E57
+#define mmTCM_PERFCOUNTER0_HI          0x0E55
+#define mmTCM_PERFCOUNTER1_HI          0x0E58
+#define mmTCM_PERFCOUNTER0_LOW         0x0E56
+#define mmTCM_PERFCOUNTER1_LOW         0x0E59
+#define mmTCF_PERFCOUNTER0_SELECT      0x0E5A
+#define mmTCF_PERFCOUNTER1_SELECT      0x0E5D
+#define mmTCF_PERFCOUNTER2_SELECT      0x0E60
+#define mmTCF_PERFCOUNTER3_SELECT      0x0E63
+#define mmTCF_PERFCOUNTER4_SELECT      0x0E66
+#define mmTCF_PERFCOUNTER5_SELECT      0x0E69
+#define mmTCF_PERFCOUNTER6_SELECT      0x0E6C
+#define mmTCF_PERFCOUNTER7_SELECT      0x0E6F
+#define mmTCF_PERFCOUNTER8_SELECT      0x0E72
+#define mmTCF_PERFCOUNTER9_SELECT      0x0E75
+#define mmTCF_PERFCOUNTER10_SELECT     0x0E78
+#define mmTCF_PERFCOUNTER11_SELECT     0x0E7B
+#define mmTCF_PERFCOUNTER0_HI          0x0E5B
+#define mmTCF_PERFCOUNTER1_HI          0x0E5E
+#define mmTCF_PERFCOUNTER2_HI          0x0E61
+#define mmTCF_PERFCOUNTER3_HI          0x0E64
+#define mmTCF_PERFCOUNTER4_HI          0x0E67
+#define mmTCF_PERFCOUNTER5_HI          0x0E6A
+#define mmTCF_PERFCOUNTER6_HI          0x0E6D
+#define mmTCF_PERFCOUNTER7_HI          0x0E70
+#define mmTCF_PERFCOUNTER8_HI          0x0E73
+#define mmTCF_PERFCOUNTER9_HI          0x0E76
+#define mmTCF_PERFCOUNTER10_HI         0x0E79
+#define mmTCF_PERFCOUNTER11_HI         0x0E7C
+#define mmTCF_PERFCOUNTER0_LOW         0x0E5C
+#define mmTCF_PERFCOUNTER1_LOW         0x0E5F
+#define mmTCF_PERFCOUNTER2_LOW         0x0E62
+#define mmTCF_PERFCOUNTER3_LOW         0x0E65
+#define mmTCF_PERFCOUNTER4_LOW         0x0E68
+#define mmTCF_PERFCOUNTER5_LOW         0x0E6B
+#define mmTCF_PERFCOUNTER6_LOW         0x0E6E
+#define mmTCF_PERFCOUNTER7_LOW         0x0E71
+#define mmTCF_PERFCOUNTER8_LOW         0x0E74
+#define mmTCF_PERFCOUNTER9_LOW         0x0E77
+#define mmTCF_PERFCOUNTER10_LOW        0x0E7A
+#define mmTCF_PERFCOUNTER11_LOW        0x0E7D
+#define mmTCF_DEBUG                    0x0EC0
+#define mmTCA_FIFO_DEBUG               0x0EC1
+#define mmTCA_PROBE_DEBUG              0x0EC2
+#define mmTCA_TPC_DEBUG                0x0EC3
+#define mmTCB_CORE_DEBUG               0x0EC4
+#define mmTCB_TAG0_DEBUG               0x0EC5
+#define mmTCB_TAG1_DEBUG               0x0EC6
+#define mmTCB_TAG2_DEBUG               0x0EC7
+#define mmTCB_TAG3_DEBUG               0x0EC8
+#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9
+#define mmTCB_FETCH_GEN_WALKER_DEBUG   0x0ECB
+#define mmTCB_FETCH_GEN_PIPE0_DEBUG    0x0ECC
+#define mmTCD_INPUT0_DEBUG             0x0ED0
+#define mmTCD_DEGAMMA_DEBUG            0x0ED4
+#define mmTCD_DXTMUX_SCTARB_DEBUG      0x0ED5
+#define mmTCD_DXTC_ARB_DEBUG           0x0ED6
+#define mmTCD_STALLS_DEBUG             0x0ED7
+#define mmTCO_STALLS_DEBUG             0x0EE0
+#define mmTCO_QUAD0_DEBUG0             0x0EE1
+#define mmTCO_QUAD0_DEBUG1             0x0EE2
+
+
+// Registers from TC block
+
+
+
+// Registers from SQ block
+
+#define mmSQ_GPR_MANAGEMENT            0x0D00
+#define mmSQ_FLOW_CONTROL              0x0D01
+#define mmSQ_INST_STORE_MANAGMENT      0x0D02
+#define mmSQ_RESOURCE_MANAGMENT        0x0D03
+#define mmSQ_EO_RT                     0x0D04
+#define mmSQ_DEBUG_MISC                0x0D05
+#define mmSQ_ACTIVITY_METER_CNTL       0x0D06
+#define mmSQ_ACTIVITY_METER_STATUS     0x0D07
+#define mmSQ_INPUT_ARB_PRIORITY        0x0D08
+#define mmSQ_THREAD_ARB_PRIORITY       0x0D09
+#define mmSQ_DEBUG_INPUT_FSM           0x0DAE
+#define mmSQ_DEBUG_CONST_MGR_FSM       0x0DAF
+#define mmSQ_DEBUG_TP_FSM              0x0DB0
+#define mmSQ_DEBUG_FSM_ALU_0           0x0DB1
+#define mmSQ_DEBUG_FSM_ALU_1           0x0DB2
+#define mmSQ_DEBUG_EXP_ALLOC           0x0DB3
+#define mmSQ_DEBUG_PTR_BUFF            0x0DB4
+#define mmSQ_DEBUG_GPR_VTX             0x0DB5
+#define mmSQ_DEBUG_GPR_PIX             0x0DB6
+#define mmSQ_DEBUG_TB_STATUS_SEL       0x0DB7
+#define mmSQ_DEBUG_VTX_TB_0            0x0DB8
+#define mmSQ_DEBUG_VTX_TB_1            0x0DB9
+#define mmSQ_DEBUG_VTX_TB_STATUS_REG   0x0DBA
+#define mmSQ_DEBUG_VTX_TB_STATE_MEM    0x0DBB
+#define mmSQ_DEBUG_PIX_TB_0            0x0DBC
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
+#define mmSQ_DEBUG_PIX_TB_STATE_MEM    0x0DC1
+#define mmSQ_PERFCOUNTER0_SELECT       0x0DC8
+#define mmSQ_PERFCOUNTER1_SELECT       0x0DC9
+#define mmSQ_PERFCOUNTER2_SELECT       0x0DCA
+#define mmSQ_PERFCOUNTER3_SELECT       0x0DCB
+#define mmSQ_PERFCOUNTER0_LOW          0x0DCC
+#define mmSQ_PERFCOUNTER0_HI           0x0DCD
+#define mmSQ_PERFCOUNTER1_LOW          0x0DCE
+#define mmSQ_PERFCOUNTER1_HI           0x0DCF
+#define mmSQ_PERFCOUNTER2_LOW          0x0DD0
+#define mmSQ_PERFCOUNTER2_HI           0x0DD1
+#define mmSQ_PERFCOUNTER3_LOW          0x0DD2
+#define mmSQ_PERFCOUNTER3_HI           0x0DD3
+#define mmSX_PERFCOUNTER0_SELECT       0x0DD4
+#define mmSX_PERFCOUNTER0_LOW          0x0DD8
+#define mmSX_PERFCOUNTER0_HI           0x0DD9
+#define mmSQ_INSTRUCTION_ALU_0         0x5000
+#define mmSQ_INSTRUCTION_ALU_1         0x5001
+#define mmSQ_INSTRUCTION_ALU_2         0x5002
+#define mmSQ_INSTRUCTION_CF_EXEC_0     0x5080
+#define mmSQ_INSTRUCTION_CF_EXEC_1     0x5081
+#define mmSQ_INSTRUCTION_CF_EXEC_2     0x5082
+#define mmSQ_INSTRUCTION_CF_LOOP_0     0x5083
+#define mmSQ_INSTRUCTION_CF_LOOP_1     0x5084
+#define mmSQ_INSTRUCTION_CF_LOOP_2     0x5085
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088
+#define mmSQ_INSTRUCTION_CF_ALLOC_0    0x5089
+#define mmSQ_INSTRUCTION_CF_ALLOC_1    0x508A
+#define mmSQ_INSTRUCTION_CF_ALLOC_2    0x508B
+#define mmSQ_INSTRUCTION_TFETCH_0      0x5043
+#define mmSQ_INSTRUCTION_TFETCH_1      0x5044
+#define mmSQ_INSTRUCTION_TFETCH_2      0x5045
+#define mmSQ_INSTRUCTION_VFETCH_0      0x5040
+#define mmSQ_INSTRUCTION_VFETCH_1      0x5041
+#define mmSQ_INSTRUCTION_VFETCH_2      0x5042
+#define mmSQ_CONSTANT_0                0x4000
+#define mmSQ_CONSTANT_1                0x4001
+#define mmSQ_CONSTANT_2                0x4002
+#define mmSQ_CONSTANT_3                0x4003
+#define mmSQ_FETCH_0                   0x4800
+#define mmSQ_FETCH_1                   0x4801
+#define mmSQ_FETCH_2                   0x4802
+#define mmSQ_FETCH_3                   0x4803
+#define mmSQ_FETCH_4                   0x4804
+#define mmSQ_FETCH_5                   0x4805
+#define mmSQ_CONSTANT_VFETCH_0         0x4806
+#define mmSQ_CONSTANT_VFETCH_1         0x4808
+#define mmSQ_CONSTANT_T2               0x480C
+#define mmSQ_CONSTANT_T3               0x4812
+#define mmSQ_CF_BOOLEANS               0x4900
+#define mmSQ_CF_LOOP                   0x4908
+#define mmSQ_CONSTANT_RT_0             0x4940
+#define mmSQ_CONSTANT_RT_1             0x4941
+#define mmSQ_CONSTANT_RT_2             0x4942
+#define mmSQ_CONSTANT_RT_3             0x4943
+#define mmSQ_FETCH_RT_0                0x4D40
+#define mmSQ_FETCH_RT_1                0x4D41
+#define mmSQ_FETCH_RT_2                0x4D42
+#define mmSQ_FETCH_RT_3                0x4D43
+#define mmSQ_FETCH_RT_4                0x4D44
+#define mmSQ_FETCH_RT_5                0x4D45
+#define mmSQ_CF_RT_BOOLEANS            0x4E00
+#define mmSQ_CF_RT_LOOP                0x4E14
+#define mmSQ_VS_PROGRAM                0x21F7
+#define mmSQ_PS_PROGRAM                0x21F6
+#define mmSQ_CF_PROGRAM_SIZE           0x2315
+#define mmSQ_INTERPOLATOR_CNTL         0x2182
+#define mmSQ_PROGRAM_CNTL              0x2180
+#define mmSQ_WRAPPING_0                0x2183
+#define mmSQ_WRAPPING_1                0x2184
+#define mmSQ_VS_CONST                  0x2307
+#define mmSQ_PS_CONST                  0x2308
+#define mmSQ_CONTEXT_MISC              0x2181
+#define mmSQ_CF_RD_BASE                0x21F5
+#define mmSQ_DEBUG_MISC_0              0x2309
+#define mmSQ_DEBUG_MISC_1              0x230A
+
+
+// Registers from SX block
+
+
+
+// Registers from MH block
+
+#define mmMH_ARBITER_CONFIG            0x0A40
+#define mmMH_CLNT_AXI_ID_REUSE         0x0A41
+#define mmMH_INTERRUPT_MASK            0x0A42
+#define mmMH_INTERRUPT_STATUS          0x0A43
+#define mmMH_INTERRUPT_CLEAR           0x0A44
+#define mmMH_AXI_ERROR                 0x0A45
+#define mmMH_PERFCOUNTER0_SELECT       0x0A46
+#define mmMH_PERFCOUNTER1_SELECT       0x0A4A
+#define mmMH_PERFCOUNTER0_CONFIG       0x0A47
+#define mmMH_PERFCOUNTER1_CONFIG       0x0A4B
+#define mmMH_PERFCOUNTER0_LOW          0x0A48
+#define mmMH_PERFCOUNTER1_LOW          0x0A4C
+#define mmMH_PERFCOUNTER0_HI           0x0A49
+#define mmMH_PERFCOUNTER1_HI           0x0A4D
+#define mmMH_DEBUG_CTRL                0x0A4E
+#define mmMH_DEBUG_DATA                0x0A4F
+#define mmMH_MMU_CONFIG                0x0040
+#define mmMH_MMU_VA_RANGE              0x0041
+#define mmMH_MMU_PT_BASE               0x0042
+#define mmMH_MMU_PAGE_FAULT            0x0043
+#define mmMH_MMU_TRAN_ERROR            0x0044
+#define mmMH_MMU_INVALIDATE            0x0045
+#define mmMH_MMU_MPU_BASE              0x0046
+#define mmMH_MMU_MPU_END               0x0047
+
+
+// Registers from RBBM block
+
+#define mmWAIT_UNTIL                   0x05C8
+#define mmRBBM_ISYNC_CNTL              0x05C9
+#define mmRBBM_STATUS                  0x05D0
+#define mmRBBM_DSPLY                   0x0391
+#define mmRBBM_RENDER_LATEST           0x0392
+#define mmRBBM_RTL_RELEASE             0x0000
+#define mmRBBM_PATCH_RELEASE           0x0001
+#define mmRBBM_AUXILIARY_CONFIG        0x0002
+#define mmRBBM_PERIPHID0               0x03F8
+#define mmRBBM_PERIPHID1               0x03F9
+#define mmRBBM_PERIPHID2               0x03FA
+#define mmRBBM_PERIPHID3               0x03FB
+#define mmRBBM_CNTL                    0x003B
+#define mmRBBM_SKEW_CNTL               0x003D
+#define mmRBBM_SOFT_RESET              0x003C
+#define mmRBBM_PM_OVERRIDE1            0x039C
+#define mmRBBM_PM_OVERRIDE2            0x039D
+#define mmGC_SYS_IDLE                  0x039E
+#define mmNQWAIT_UNTIL                 0x0394
+#define mmRBBM_DEBUG                   0x039B
+#define mmRBBM_READ_ERROR              0x03B3
+#define mmRBBM_WAIT_IDLE_CLOCKS        0x03B2
+#define mmRBBM_INT_CNTL                0x03B4
+#define mmRBBM_INT_STATUS              0x03B5
+#define mmRBBM_INT_ACK                 0x03B6
+#define mmMASTER_INT_SIGNAL            0x03B7
+#define mmRBBM_PERFCOUNTER1_SELECT     0x0395
+#define mmRBBM_PERFCOUNTER1_LO         0x0397
+#define mmRBBM_PERFCOUNTER1_HI         0x0398
+
+
+// Registers from CP block
+
+#define mmCP_RB_BASE                   0x01C0
+#define mmCP_RB_CNTL                   0x01C1
+#define mmCP_RB_RPTR_ADDR              0x01C3
+#define mmCP_RB_RPTR                   0x01C4
+#define mmCP_RB_RPTR_WR                0x01C7
+#define mmCP_RB_WPTR                   0x01C5
+#define mmCP_RB_WPTR_DELAY             0x01C6
+#define mmCP_RB_WPTR_BASE              0x01C8
+#define mmCP_IB1_BASE                  0x01CC
+#define mmCP_IB1_BUFSZ                 0x01CD
+#define mmCP_IB2_BASE                  0x01CE
+#define mmCP_IB2_BUFSZ                 0x01CF
+#define mmCP_ST_BASE                   0x044D
+#define mmCP_ST_BUFSZ                  0x044E
+#define mmCP_QUEUE_THRESHOLDS          0x01D5
+#define mmCP_MEQ_THRESHOLDS            0x01D6
+#define mmCP_CSQ_AVAIL                 0x01D7
+#define mmCP_STQ_AVAIL                 0x01D8
+#define mmCP_MEQ_AVAIL                 0x01D9
+#define mmCP_CSQ_RB_STAT               0x01FD
+#define mmCP_CSQ_IB1_STAT              0x01FE
+#define mmCP_CSQ_IB2_STAT              0x01FF
+#define mmCP_NON_PREFETCH_CNTRS        0x0440
+#define mmCP_STQ_ST_STAT               0x0443
+#define mmCP_MEQ_STAT                  0x044F
+#define mmCP_MIU_TAG_STAT              0x0452
+#define mmCP_CMD_INDEX                 0x01DA
+#define mmCP_CMD_DATA                  0x01DB
+#define mmCP_ME_CNTL                   0x01F6
+#define mmCP_ME_STATUS                 0x01F7
+#define mmCP_ME_RAM_WADDR              0x01F8
+#define mmCP_ME_RAM_RADDR              0x01F9
+#define mmCP_ME_RAM_DATA               0x01FA
+#define mmCP_ME_RDADDR                 0x01EA
+#define mmCP_DEBUG                     0x01FC
+#define mmSCRATCH_REG0                 0x0578
+#define mmGUI_SCRATCH_REG0             0x0578
+#define mmSCRATCH_REG1                 0x0579
+#define mmGUI_SCRATCH_REG1             0x0579
+#define mmSCRATCH_REG2                 0x057A
+#define mmGUI_SCRATCH_REG2             0x057A
+#define mmSCRATCH_REG3                 0x057B
+#define mmGUI_SCRATCH_REG3             0x057B
+#define mmSCRATCH_REG4                 0x057C
+#define mmGUI_SCRATCH_REG4             0x057C
+#define mmSCRATCH_REG5                 0x057D
+#define mmGUI_SCRATCH_REG5             0x057D
+#define mmSCRATCH_REG6                 0x057E
+#define mmGUI_SCRATCH_REG6             0x057E
+#define mmSCRATCH_REG7                 0x057F
+#define mmGUI_SCRATCH_REG7             0x057F
+#define mmSCRATCH_UMSK                 0x01DC
+#define mmSCRATCH_ADDR                 0x01DD
+#define mmCP_ME_VS_EVENT_SRC           0x0600
+#define mmCP_ME_VS_EVENT_ADDR          0x0601
+#define mmCP_ME_VS_EVENT_DATA          0x0602
+#define mmCP_ME_VS_EVENT_ADDR_SWM      0x0603
+#define mmCP_ME_VS_EVENT_DATA_SWM      0x0604
+#define mmCP_ME_PS_EVENT_SRC           0x0605
+#define mmCP_ME_PS_EVENT_ADDR          0x0606
+#define mmCP_ME_PS_EVENT_DATA          0x0607
+#define mmCP_ME_PS_EVENT_ADDR_SWM      0x0608
+#define mmCP_ME_PS_EVENT_DATA_SWM      0x0609
+#define mmCP_ME_CF_EVENT_SRC           0x060A
+#define mmCP_ME_CF_EVENT_ADDR          0x060B
+#define mmCP_ME_CF_EVENT_DATA          0x060C
+#define mmCP_ME_NRT_ADDR               0x060D
+#define mmCP_ME_NRT_DATA               0x060E
+#define mmCP_ME_VS_FETCH_DONE_SRC      0x0612
+#define mmCP_ME_VS_FETCH_DONE_ADDR     0x0613
+#define mmCP_ME_VS_FETCH_DONE_DATA     0x0614
+#define mmCP_INT_CNTL                  0x01F2
+#define mmCP_INT_STATUS                0x01F3
+#define mmCP_INT_ACK                   0x01F4
+#define mmCP_PFP_UCODE_ADDR            0x045F
+#define mmCP_PFP_UCODE_DATA            0x0460
+#define mmCP_PERFMON_CNTL              0x01F5
+#define mmCP_PERFCOUNTER_SELECT        0x01E6
+#define mmCP_PERFCOUNTER_LO            0x01E7
+#define mmCP_PERFCOUNTER_HI            0x01E8
+#define mmCP_BIN_MASK_LO               0x0454
+#define mmCP_BIN_MASK_HI               0x0455
+#define mmCP_BIN_SELECT_LO             0x0456
+#define mmCP_BIN_SELECT_HI             0x0457
+#define mmCP_NV_FLAGS_0                0x01EE
+#define mmCP_NV_FLAGS_1                0x01EF
+#define mmCP_NV_FLAGS_2                0x01F0
+#define mmCP_NV_FLAGS_3                0x01F1
+#define mmCP_STATE_DEBUG_INDEX         0x01EC
+#define mmCP_STATE_DEBUG_DATA          0x01ED
+#define mmCP_PROG_COUNTER              0x044B
+#define mmCP_STAT                      0x047F
+#define mmBIOS_0_SCRATCH               0x0004
+#define mmBIOS_1_SCRATCH               0x0005
+#define mmBIOS_2_SCRATCH               0x0006
+#define mmBIOS_3_SCRATCH               0x0007
+#define mmBIOS_4_SCRATCH               0x0008
+#define mmBIOS_5_SCRATCH               0x0009
+#define mmBIOS_6_SCRATCH               0x000A
+#define mmBIOS_7_SCRATCH               0x000B
+#define mmBIOS_8_SCRATCH               0x0580
+#define mmBIOS_9_SCRATCH               0x0581
+#define mmBIOS_10_SCRATCH              0x0582
+#define mmBIOS_11_SCRATCH              0x0583
+#define mmBIOS_12_SCRATCH              0x0584
+#define mmBIOS_13_SCRATCH              0x0585
+#define mmBIOS_14_SCRATCH              0x0586
+#define mmBIOS_15_SCRATCH              0x0587
+#define mmCOHER_SIZE_PM4               0x0A29
+#define mmCOHER_BASE_PM4               0x0A2A
+#define mmCOHER_STATUS_PM4             0x0A2B
+#define mmCOHER_SIZE_HOST              0x0A2F
+#define mmCOHER_BASE_HOST              0x0A30
+#define mmCOHER_STATUS_HOST            0x0A31
+#define mmCOHER_DEST_BASE_0            0x2006
+#define mmCOHER_DEST_BASE_1            0x2007
+#define mmCOHER_DEST_BASE_2            0x2008
+#define mmCOHER_DEST_BASE_3            0x2009
+#define mmCOHER_DEST_BASE_4            0x200A
+#define mmCOHER_DEST_BASE_5            0x200B
+#define mmCOHER_DEST_BASE_6            0x200C
+#define mmCOHER_DEST_BASE_7            0x200D
+
+
+// Registers from SC block
+
+
+
+// Registers from BC block
+
+#define mmRB_SURFACE_INFO              0x2000
+#define mmRB_COLOR_INFO                0x2001
+#define mmRB_DEPTH_INFO                0x2002
+#define mmRB_STENCILREFMASK            0x210D
+#define mmRB_ALPHA_REF                 0x210E
+#define mmRB_COLOR_MASK                0x2104
+#define mmRB_BLEND_RED                 0x2105
+#define mmRB_BLEND_GREEN               0x2106
+#define mmRB_BLEND_BLUE                0x2107
+#define mmRB_BLEND_ALPHA               0x2108
+#define mmRB_FOG_COLOR                 0x2109
+#define mmRB_STENCILREFMASK_BF         0x210C
+#define mmRB_DEPTHCONTROL              0x2200
+#define mmRB_BLENDCONTROL              0x2201
+#define mmRB_COLORCONTROL              0x2202
+#define mmRB_MODECONTROL               0x2208
+#define mmRB_COLOR_DEST_MASK           0x2326
+#define mmRB_COPY_CONTROL              0x2318
+#define mmRB_COPY_DEST_BASE            0x2319
+#define mmRB_COPY_DEST_PITCH           0x231A
+#define mmRB_COPY_DEST_INFO            0x231B
+#define mmRB_COPY_DEST_PIXEL_OFFSET    0x231C
+#define mmRB_DEPTH_CLEAR               0x231D
+#define mmRB_SAMPLE_COUNT_CTL          0x2324
+#define mmRB_SAMPLE_COUNT_ADDR         0x2325
+#define mmRB_BC_CONTROL                0x0F01
+#define mmRB_EDRAM_INFO                0x0F02
+#define mmRB_CRC_RD_PORT               0x0F0C
+#define mmRB_CRC_CONTROL               0x0F0D
+#define mmRB_CRC_MASK                  0x0F0E
+#define mmRB_PERFCOUNTER0_SELECT       0x0F04
+#define mmRB_PERFCOUNTER0_LOW          0x0F08
+#define mmRB_PERFCOUNTER0_HI           0x0F09
+#define mmRB_TOTAL_SAMPLES             0x0F0F
+#define mmRB_ZPASS_SAMPLES             0x0F10
+#define mmRB_ZFAIL_SAMPLES             0x0F11
+#define mmRB_SFAIL_SAMPLES             0x0F12
+#define mmRB_DEBUG_0                   0x0F26
+#define mmRB_DEBUG_1                   0x0F27
+#define mmRB_DEBUG_2                   0x0F28
+#define mmRB_DEBUG_3                   0x0F29
+#define mmRB_DEBUG_4                   0x0F2A
+#define mmRB_FLAG_CONTROL              0x0F2B
+#define mmBC_DUMMY_CRAYRB_ENUMS        0x0F15
+#define mmBC_DUMMY_CRAYRB_MOREENUMS    0x0F16
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h
new file mode 100644
index 00000000000..7e293b371bc
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h
@@ -0,0 +1,221 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_RANDOM_HEADER)
+#define _yamato_RANDOM_HEADER
+
+/*************************************************************
+ * THIS FILE IS AUTOMATICALLY CREATED.  DO NOT EDIT THIS FILE.
+ *************************************************************/
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SU_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SC_PERFCNT_SELECT>;
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRIM_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SOURCE_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_INDEX_SIZE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SMALL_INDEX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRE_FETCH_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_GRP_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_EVENT_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DMA_SWAP_MODE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCR_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TP_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCM_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCF_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SQ_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SX_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Abs_modifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Exporting>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ScalarOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SwizzleType>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<InputModifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredicateSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect1>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VectorOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect0>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Ressource_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Instruction_serial>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VC_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressing>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CFOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Allocation_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexInstOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressmode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexCoordDenorm>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SrcSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DstSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MipFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<AnisoFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ArbitraryFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SampleLocation>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VertexMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Sample_Cntl>;
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MhPerfEncode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MmuClntBeh>;
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RBBM_PERFCOUNT1_SEL>;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CP_PERFCOUNT_SEL>;
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareFrag>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareRef>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<StencilOp>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<BlendOpX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CombFuncX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherModeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherTypeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceEndian>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramSizeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RB_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceSwap>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumber>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceTiling>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumberX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArrayX>;
+
+#endif /*_yamato_RANDOM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h
new file mode 100644
index 00000000000..b021d446a22
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h
@@ -0,0 +1,13962 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_REG_HEADER)
+#define _yamato_REG_HEADER
+
+    union PA_CL_VPORT_XSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_XSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_XSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_XOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_XOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_XOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_YSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_YSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_YOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_YOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_ZSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_ZSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_ZOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_ZOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VTE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int                                 : 2;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                                 : 2;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CLIP_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+        unsigned int                                 : 27;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 27;
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 28;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_VTX_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PIX_CENTER : 1;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      PIX_CENTER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          HEIGHT : 16;
+        unsigned int                           WIDTH : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           WIDTH : 16;
+        unsigned int                          HEIGHT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_MINMAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_SIZE : 16;
+        unsigned int                        MAX_SIZE : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MAX_SIZE : 16;
+        unsigned int                        MIN_SIZE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           WIDTH : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                           WIDTH : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_SC_MODE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CULL_FRONT : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                            FACE : 1;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int                            FACE : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                      CULL_FRONT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 WINDOW_X_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_X_OFFSET : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+        unsigned int                                 : 10;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 10;
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         AA_MASK : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                         AA_MASK : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    LINE_PATTERN : 16;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                                 : 4;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                    LINE_PATTERN : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BRES_CNTL : 8;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int                       BRES_CNTL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 1;
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VIZ_QUERY_ENA : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                                 : 1;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                   VIZ_QUERY_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STATUS_BITS : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     STATUS_BITS : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CURRENT_PTR : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int                     CURRENT_PTR : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         CL_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CL_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SU_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SU_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SC_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SU_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SU_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           clip_ga_bc_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int                     ALWAYS_ZERO : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 12;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_ga_bc_fifo_write : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int                     ALWAYS_ZERO : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 8;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO1 : 21;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO1 : 21;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO0 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 6;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO3 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO0 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 24;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            clprim_in_back_event : 1;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int     clip_priority_seq_indx_load : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int     clip_priority_seq_indx_load : 2;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int            clprim_in_back_event : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int         clprim_in_back_event_id : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         clprim_in_back_event_id : 6;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+        unsigned int                     ALWAYS_ZERO : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 28;
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clip_priority_available_vte_out_clip : 2;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clip_priority_available_vte_out_clip : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               sm0_clip_vert_cnt : 4;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int               sm0_current_state : 7;
+        unsigned int                    ALWAYS_ZERO0 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 5;
+        unsigned int               sm0_current_state : 7;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int               sm0_clip_vert_cnt : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   nan_kill_flag : 4;
+        unsigned int                position_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int           sx_pending_rd_aux_sel : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           sx_pending_rd_aux_sel : 1;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                position_address : 3;
+        unsigned int                   nan_kill_flag : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                param_cache_base : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                param_cache_base : 7;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         sx_sent : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                          sx_aux : 1;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                req_active_verts : 7;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int        sx_pending_fifo_contents : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int        sx_pending_fifo_contents : 3;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int                req_active_verts : 7;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                          sx_aux : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                         sx_sent : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    vertex_fifo_entriesavailable : 4;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int                   current_state : 2;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                   current_state : 2;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int    vertex_fifo_entriesavailable : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   su_cntl_state : 5;
+        unsigned int                     pmode_state : 6;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                       geom_busy : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       geom_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     pmode_state : 6;
+        unsigned int                   su_cntl_state : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort0_gated_17_4 : 14;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int              y_sort0_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort1_gated_17_4 : 14;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int              y_sort1_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort2_gated_17_4 : 14;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int              y_sort2_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort0_gated : 11;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                      type_gated : 3;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                       eop_gated : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                       eop_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                      type_gated : 3;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int           attr_indx_sort0_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort2_gated : 11;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int                  event_id_gated : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                  event_id_gated : 5;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int           attr_indx_sort2_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SC_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SC_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    pa_freeze_b1 : 1;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                                 : 17;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 17;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                    pa_freeze_b1 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        em_state : 3;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                                 : 21;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 21;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                        em_state : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rc_rtr_dly : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                                 : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int                        event_s1 : 1;
+        unsigned int                                 : 8;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 8;
+        unsigned int                        event_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                                 : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                      rc_rtr_dly : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       x_curr_s1 : 11;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                                 : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 9;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                       x_curr_s1 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        y_end_s1 : 14;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        x_end_s1 : 14;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      z_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                           state : 3;
+        unsigned int                   state_delayed : 3;
+        unsigned int                      data_valid : 1;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                      data_valid : 1;
+        unsigned int                   state_delayed : 3;
+        unsigned int                           state : 3;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                      z_ff_empty : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      event_flag : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                            fpos : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                           state : 2;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                                 : 6;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 6;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                           state : 2;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                            fpos : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                      event_flag : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     sample_last : 1;
+        unsigned int                     sample_mask : 4;
+        unsigned int                        sample_y : 2;
+        unsigned int                        sample_x : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int                            fpos : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                                 : 3;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 3;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                            fpos : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                        sample_x : 2;
+        unsigned int                        sample_y : 2;
+        unsigned int                     sample_mask : 4;
+        unsigned int                     sample_last : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rb_sc_send : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                      mask_state : 2;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_ready : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int                      mask_ready : 1;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_state : 2;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                      rb_sc_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            combined_sample_mask : 16;
+        unsigned int                                 : 15;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 15;
+        unsigned int            combined_sample_mask : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            ez_sample_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_event : 1;
+        unsigned int                      next_state : 3;
+        unsigned int                           state : 3;
+        unsigned int                           stall : 1;
+        unsigned int                                 : 16;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 16;
+        unsigned int                           stall : 1;
+        unsigned int                           state : 3;
+        unsigned int                      next_state : 3;
+        unsigned int               packer_send_event : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int            ez_sample_data_ready : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SQ_iterator_free_buff : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                                 : 7;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 7;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int           SQ_iterator_free_buff : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GFX_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DRAW_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       PRIM_TYPE : 6;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                                 : 3;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int                     NUM_INDICES : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     NUM_INDICES : 16;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                                 : 3;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                       PRIM_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_EVENT_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EVENT_TYPE : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      EVENT_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                       SWAP_MODE : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SWAP_MODE : 2;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MIN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_IMMED_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MAX_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MAX_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MAX_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MIN_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MIN_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_INDX_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INDX_OFFSET : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                     INDX_OFFSET : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VERTEX_REUSE_BLOCK_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_OUT_DEALLOC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEALLOC_DIST : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    DEALLOC_DIST : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MULTI_PRIM_IB_RESET_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESET_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      RESET_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            MISC : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                            MISC : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VTX_VECT_EJECT_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PRIM_COUNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                      PRIM_COUNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_LAST_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VGT_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                  VGT_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     te_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     te_grp_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                out_te_data_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_te_data_read : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      vgt_clk_en : 1;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                      vgt_clk_en : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int                      read_block : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int                   selected_data : 8;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                           gap_q : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int                     grp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     grp_trigger : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int                           gap_q : 1;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                   selected_data : 8;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int                      read_block : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     save_read_q : 1;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                     save_read_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            prim_side_indx_valid : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                       hold_prim : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int                       hold_prim : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int            prim_side_indx_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       null_terminate_vtx_vector : 1;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int                    new_packet_q : 1;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int                                 : 4;
+        unsigned int                     out_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 4;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int                    new_packet_q : 1;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int       null_terminate_vtx_vector : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   L2_INVALIDATE : 1;
+        unsigned int                                 : 17;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 11;
+        unsigned int                         TC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 11;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 17;
+        unsigned int                   L2_INVALIDATE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int                           SPARE : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 23;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP_TC_CLKGATE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TP_BUSY_EXTEND : 3;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                  TP_BUSY_EXTEND : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TPC_INPUT_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int                        TPC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int                  TPC_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        LOD_CNTL : 2;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                                 : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                    SQ_TP_WAKEUP : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SQ_TP_WAKEUP : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                                 : 3;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 1;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                        LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          UNUSED : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                          UNUSED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 BLEND_PRECISION : 1;
+        unsigned int                           SPARE : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 31;
+        unsigned int                 BLEND_PRECISION : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TP_INPUT_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                         TP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TP_BUSY : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                   TP_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      Q_LOD_CNTL : 2;
+        unsigned int                                 : 1;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int                                 : 1;
+        unsigned int                      Q_LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TT_MODE : 1;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                           SPARE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 30;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                         TT_MODE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 6;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TPC_full : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                         tca_rts : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                         tca_rts : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                        TPC_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                                 : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_FIFO_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        tp0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tpc_full : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                        tpc_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tp0_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_PROBE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ProbeFilter_stall : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int               ProbeFilter_stall : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_TPC_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                                 : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 18;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_CORE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       access512 : 1;
+        unsigned int                           tiled : 1;
+        unsigned int                                 : 2;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 1;
+        unsigned int                          format : 6;
+        unsigned int                                 : 2;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 3;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 3;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 2;
+        unsigned int                          format : 6;
+        unsigned int                                 : 1;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 2;
+        unsigned int                           tiled : 1;
+        unsigned int                       access512 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG1_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG2_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG3_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       left_done : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int                     update_left : 1;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int                    valid_left_q : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    valid_left_q : 1;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int                     update_left : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int                       left_done : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_WALKER_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                                 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                            busy : 1;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                            busy : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                                 : 3;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_PIPE0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     tc0_arb_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                            busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         valid_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                         valid_q : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                            busy : 1;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                     tc0_arb_rts : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_INPUT0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                                 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DEGAMMA_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTMUX_SCTARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 9;
+        unsigned int                          pstate : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int                                 : 3;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 6;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                                 : 6;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 3;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int                                 : 3;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                                 : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTC_ARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                        n0_stall : 1;
+        unsigned int                          pstate : 1;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int                 n0_dxt2_4_types : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 n0_dxt2_4_types : 1;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                        n0_stall : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 10;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_incoming_rtr : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                not_incoming_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int                                 : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             rl_sg_sector_format : 8;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                                 : 2;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int                            busy : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            busy : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 2;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int             rl_sg_sector_format : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       fifo_busy : 1;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                    write_enable : 1;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                                 : 2;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int                                 : 2;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                    write_enable : 1;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                       fifo_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_GPR_MANAGEMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     REG_DYNAMIC : 1;
+        unsigned int                                 : 3;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 3;
+        unsigned int                     REG_DYNAMIC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FLOW_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+        unsigned int                                 : 2;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 2;
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INST_STORE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   INST_BASE_PIX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_PIX : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_RESOURCE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_EO_RT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 EO_CONSTANTS_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                 EO_CONSTANTS_RT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  DB_ALUCST_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                        RESERVED : 2;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                                 : 1;
+        unsigned int                  DB_ALUCST_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TIMEBASE : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                           SPARE : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                        TIMEBASE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERCENT_BUSY : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    PERCENT_BUSY : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INPUT_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_THREAD_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                        RESERVED : 2;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_INPUT_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       VC_VSR_LD : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           PC_AS : 3;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                           PC_AS : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_VSR_LD : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_CONST_MGR_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TP_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           EX_TP : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           CF_TP : 4;
+        unsigned int                           IF_TP : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           IF_TP : 3;
+        unsigned int                           CF_TP : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           EX_TP : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_EXP_ALLOC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   POS_BUF_AVAIL : 4;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                   POS_BUF_AVAIL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PTR_BUFF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   END_OF_BUFFER : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                   END_OF_BUFFER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_VTX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VTX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_PIX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TB_STATUS_SEL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int                                 : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_PTR : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                     VS_DONE_PTR : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATUS_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VS_STATUS_REG : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VS_STATUS_REG : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_HEAD_PTR : 6;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int                            BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BUSY : 1;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                    PIX_HEAD_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VECTOR_RESULT : 6;
+        unsigned int                   CST_0_ABS_MOD : 1;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int                   SST_0_ABS_MOD : 1;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                   SCALAR_OPCODE : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SCALAR_OPCODE : 6;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                   SST_0_ABS_MOD : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   CST_0_ABS_MOD : 1;
+        unsigned int                   VECTOR_RESULT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                 CONST_0_REL_ABS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CONST_0_REL_ABS : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SRC_C_REG_PTR : 6;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_A_SEL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_A_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   SRC_C_REG_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_1 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 11;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 11;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 6;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                      RESERVED_0 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                        RESERVED : 22;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                        RESERVED : 22;
+        unsigned int                         LOOP_ID : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      RESERVED_1 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 17;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 1;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_2 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_2 : 2;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                      RESERVED_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 17;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                        RESERVED : 17;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 4;
+        unsigned int                        RESERVED : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 28;
+        unsigned int                            SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 8;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                            SIZE : 4;
+        unsigned int                      RESERVED_1 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 12;
+        unsigned int                            SIZE : 4;
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                      RESERVED_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 24;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                        RESERVED : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_Z : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_SEL_Z : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               USE_REG_GRADIENTS : 1;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int               USE_REG_GRADIENTS : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                         SRC_SEL : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SRC_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          STRIDE : 8;
+        unsigned int                                 : 8;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 7;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                                 : 7;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 8;
+        unsigned int                          STRIDE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TYPE : 1;
+        unsigned int                           STATE : 1;
+        unsigned int                    BASE_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BASE_ADDRESS : 30;
+        unsigned int                           STATE : 1;
+        unsigned int                            TYPE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ENDIAN_SWAP : 2;
+        unsigned int                   LIMIT_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   LIMIT_ADDRESS : 30;
+        unsigned int                     ENDIAN_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_PROGRAM_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      VS_CF_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INTERPOLATOR_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARAM_SHADE : 16;
+        unsigned int                SAMPLING_PATTERN : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                SAMPLING_PATTERN : 16;
+        unsigned int                     PARAM_SHADE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PROGRAM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                   GEN_INDEX_VTX : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   GEN_INDEX_VTX : 1;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      VS_NUM_REG : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_0 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_7 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PARAM_WRAP_7 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_0 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_8 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_15 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PARAM_WRAP_15 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                    PARAM_WRAP_8 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONTEXT_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                                 : 4;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RD_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RD_BASE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                         RD_BASE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DB_PROB_ON : 1;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 5;
+        unsigned int                   DB_PROB_COUNT : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DB_PROB_COUNT : 8;
+        unsigned int                                 : 5;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      DB_PROB_ON : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DB_ON_PIX : 1;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                                 : 6;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                                 : 6;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                       DB_ON_PIX : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_ARBITER_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_CLNT_AXI_ID_REUSE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          CPw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          CPw_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     AXI_READ_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                     AXI_READ_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           INDEX : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                           INDEX : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                         MH_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                         CP_BE_q : 8;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                         RB_BE_q : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BE_q : 8;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                         CP_BE_q : 8;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CP_MH_send : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                   CP_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CP_MH_ad_31_5 : 27;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                      CP_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG06 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 CP_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CP_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG07 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CP_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                CP_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG08 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 3;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                 TC_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 TC_MH_addr_31_5 : 27;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_info : 25;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_info : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_TC_mcinfo : 25;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                    MH_TC_mcinfo : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ROQ_INFO : 25;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_INFO : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                 RB_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_addr_31_5 : 27;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RB_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                RB_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                RB_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG19 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                    CTRL_ARC_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CTRL_ARC_PAD : 28;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                           REG_A : 14;
+        unsigned int                          REG_RE : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                          REG_RE : 1;
+        unsigned int                           REG_A : 14;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          REG_WD : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REG_WD : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG22 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             CIB_MH_axi_halt_req : 1;
+        unsigned int             MH_CIB_axi_halt_ack : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       BRC_VALID : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BRC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int             MH_CIB_axi_halt_ack : 1;
+        unsigned int             CIB_MH_axi_halt_req : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG23 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  EFF2_FP_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                  EFF2_FP_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG24 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG25 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                        CLNT_REQ : 4;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                        CLNT_REQ : 4;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG26 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG27 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG28 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG29 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG30 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG31 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                      ROQ_ADDR_0 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_0 : 27;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG32 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                      ROQ_ADDR_1 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_1 : 27;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG33 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                      ROQ_ADDR_2 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_2 : 27;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG34 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                      ROQ_ADDR_3 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_3 : 27;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG35 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                      ROQ_ADDR_4 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_4 : 27;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG36 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                      ROQ_ADDR_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_5 : 27;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG37 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                      ROQ_ADDR_6 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_6 : 27;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG38 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                      ROQ_ADDR_7 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_7 : 27;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG39 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG40 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                       ARB_VAD_q : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ARB_VAD_q : 28;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG41 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          MMU_WE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         MMU_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_PAD : 28;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                          MMU_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG42 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          WDB_WE : 1;
+        unsigned int                    WDB_RTR_SKID : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                    WDB_RTR_SKID : 1;
+        unsigned int                          WDB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG43 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                ARB_WDATA_q_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                ARB_WDATA_q_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG44 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ARB_WDATA_q_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               ARB_WDATA_q_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG45 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG46 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG47 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG48 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG49 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG50 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RF_MMU_CONFIG_q : 24;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                 RF_MMU_CONFIG_q : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG51 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    stage1_valid : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                    stage1_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG52 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                    stage2_valid : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                     TAG_valid_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TAG_valid_q : 16;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                    stage2_valid : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG53 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG0_VA : 13;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                         TAG0_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG54 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG2_VA : 13;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                         TAG2_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG55 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG4_VA : 13;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                         TAG4_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG56 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG6_VA : 13;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                         TAG6_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG57 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG8_VA : 13;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                         TAG8_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG58 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG10_VA : 13;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                        TAG10_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG59 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG12_VA : 13;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                        TAG12_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG60 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG14_VA : 13;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                        TAG14_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG61 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG62 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG63 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      MMU_ENABLE : 1;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                      MMU_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_VA_RANGE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                NUM_64KB_REGIONS : 12;
+        unsigned int                         VA_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         VA_BASE : 20;
+        unsigned int                NUM_64KB_REGIONS : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PT_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         PT_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         PT_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PAGE_FAULT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PAGE_FAULT : 1;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int                          REQ_VA : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REQ_VA : 20;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                      PAGE_FAULT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_TRAN_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                      TRAN_ERROR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      TRAN_ERROR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_INVALIDATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  INVALIDATE_ALL : 1;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                  INVALIDATE_ALL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                        MPU_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MPU_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_END {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         MPU_END : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MPU_END : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union WAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int                                 : 2;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 2;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_ISYNC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CMDFIFO_AVAIL : 5;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                      GUI_ACTIVE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      GUI_ACTIVE : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                                 : 2;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                   CMDFIFO_AVAIL : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DSPLY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              DISPLAY_ID0_ACTIVE : 1;
+        unsigned int              DISPLAY_ID1_ACTIVE : 1;
+        unsigned int              DISPLAY_ID2_ACTIVE : 1;
+        unsigned int                    VSYNC_ACTIVE : 1;
+        unsigned int                 USE_DISPLAY_ID0 : 1;
+        unsigned int                 USE_DISPLAY_ID1 : 1;
+        unsigned int                 USE_DISPLAY_ID2 : 1;
+        unsigned int                         SW_CNTL : 1;
+        unsigned int                        NUM_BUFS : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                        NUM_BUFS : 2;
+        unsigned int                         SW_CNTL : 1;
+        unsigned int                 USE_DISPLAY_ID2 : 1;
+        unsigned int                 USE_DISPLAY_ID1 : 1;
+        unsigned int                 USE_DISPLAY_ID0 : 1;
+        unsigned int                    VSYNC_ACTIVE : 1;
+        unsigned int              DISPLAY_ID2_ACTIVE : 1;
+        unsigned int              DISPLAY_ID1_ACTIVE : 1;
+        unsigned int              DISPLAY_ID0_ACTIVE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RENDER_LATEST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BUFFER_ID : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                       BUFFER_ID : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RTL_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CHANGELIST : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      CHANGELIST : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PATCH_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PATCH_REVISION : 16;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                     CUSTOMER_ID : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     CUSTOMER_ID : 8;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                  PATCH_REVISION : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_AUXILIARY_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER0 : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     PARTNUMBER0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER1 : 4;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                     PARTNUMBER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DESIGNER1 : 4;
+        unsigned int                        REVISION : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        REVISION : 4;
+        unsigned int                       DESIGNER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int                                 : 1;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 1;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    READ_TIMEOUT : 8;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                    READ_TIMEOUT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SKEW_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SOFT_RESET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SOFT_RESET_CP : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                                 : 5;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 2;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                                 : 2;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 5;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_CP : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GC_SYS_IDLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+        unsigned int                                 : 15;
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+        unsigned int                                 : 15;
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union NQWAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WAIT_GUI_IDLE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                   WAIT_GUI_IDLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int                                 : 3;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 4;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int                                 : 6;
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+        unsigned int                                 : 6;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int                                 : 4;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 3;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_READ_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 13;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                      READ_ERROR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      READ_ERROR : 1;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                                 : 13;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_WAIT_IDLE_CLOCKS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_MASK : 1;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                  RDERR_INT_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_STAT : 1;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                  RDERR_INT_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   RDERR_INT_ACK : 1;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                   RDERR_INT_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MASTER_INT_SIGNAL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 24;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                   RBBM_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   RBBM_INT_STAT : 1;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                                 : 24;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNT1_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                 PERF_COUNT1_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PERF_COUNT1_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERF_COUNT1_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                         RB_BASE : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BASE : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RB_BUFSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 6;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 3;
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+        unsigned int                                 : 3;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 6;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BUFSZ : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_RPTR_SWAP : 2;
+        unsigned int                    RB_RPTR_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_RPTR_ADDR : 30;
+        unsigned int                    RB_RPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_RPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_RPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_WR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RB_RPTR_WR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                      RB_RPTR_WR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_WPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_WPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_DELAY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PRE_WRITE_TIMER : 28;
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+        unsigned int                 PRE_WRITE_TIMER : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_WPTR_SWAP : 2;
+        unsigned int                    RB_WPTR_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_WPTR_BASE : 30;
+        unsigned int                    RB_WPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB1_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB1_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB1_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB1_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB2_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB2_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB2_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB2_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                         ST_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         ST_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        ST_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        ST_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_QUEUE_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CSQ_IB1_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB1_START : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CSQ_CNT_RING : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                    CSQ_CNT_RING : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STQ_CNT_ST : 7;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                      STQ_CNT_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MEQ_CNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                         MEQ_CNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_RB_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB1_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB2_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NON_PREFETCH_CNTRS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     IB1_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB1_COUNTER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_ST_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STQ_RPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_RPTR_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MEQ_RPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_RPTR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MIU_TAG_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TAG_0_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                                 : 13;
+        unsigned int              INVALID_RETURN_TAG : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              INVALID_RETURN_TAG : 1;
+        unsigned int                                 : 13;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_0_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CMD_INDEX : 7;
+        unsigned int                                 : 9;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 9;
+        unsigned int                       CMD_INDEX : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CMD_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CMD_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ME_STATMUX : 16;
+        unsigned int                                 : 9;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   PROG_CNT_SIZE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PROG_CNT_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                                 : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 9;
+        unsigned int                      ME_STATMUX : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ME_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ME_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_WADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_WADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_WADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_RADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_RADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_RADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ME_RAM_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ME_RAM_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RDADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ME_RDADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ME_RDADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int                                 : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG4 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG4 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG5 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG5 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG6 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG6 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG7 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG7 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_UMSK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_UMSK : 8;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_UMSK : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                    SCRATCH_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_SWM : 1;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                     VS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_SWAP : 2;
+        unsigned int                    VS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_ADDR : 30;
+        unsigned int                    VS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PS_DONE_SWM : 1;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                     PS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_SWAP : 2;
+        unsigned int                    PS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_ADDR : 30;
+        unsigned int                    PS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CF_DONE_SRC : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                     CF_DONE_SRC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_SWAP : 2;
+        unsigned int                    CF_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_ADDR : 30;
+        unsigned int                    CF_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_SWAP : 2;
+        unsigned int                  NRT_WRITE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_ADDR : 30;
+        unsigned int                  NRT_WRITE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                     RB_INT_MASK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                     RB_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                      RB_INT_ACK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RB_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_ADDR : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      UCODE_ADDR : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_DATA : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      UCODE_DATA : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFMON_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFMON_STATE : 4;
+        unsigned int                                 : 4;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PERFMON_STATE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFCOUNT_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                   PERFCOUNT_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PERFCOUNT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    PERFCOUNT_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DISCARD_0 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_15 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_15 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_16 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_31 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_31 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_16 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_32 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_47 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_47 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_32 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_48 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_63 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_63 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_48 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               STATE_DEBUG_INDEX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int               STATE_DEBUG_INDEX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                STATE_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                STATE_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PROG_COUNTER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         COUNTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         COUNTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     MIU_WR_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                         CP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CP_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int                     MIU_WR_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_0_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_1_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_2_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_3_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_4_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_5_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_6_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_7_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_8_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_9_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_10_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_11_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_12_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_13_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_14_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_15_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 8;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_0 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_0 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_1 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_1 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_2 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_2 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_3 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_3 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_4 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_4 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_5 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_5 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_6 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_6 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_7 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_7 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SURFACE_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SURFACE_PITCH : 14;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                   SURFACE_PITCH : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    COLOR_FORMAT : 4;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      COLOR_BASE : 20;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_FORMAT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEPTH_FORMAT : 1;
+        unsigned int                                 : 11;
+        unsigned int                      DEPTH_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      DEPTH_BASE : 20;
+        unsigned int                                 : 11;
+        unsigned int                    DEPTH_FORMAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STENCILREF : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                      STENCILREF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ALPHA_REF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ALPHA_REF : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ALPHA_REF : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       WRITE_RED : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                                 : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 28;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                       WRITE_RED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_RED {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BLEND_RED : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       BLEND_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_GREEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_GREEN : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_GREEN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_BLUE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      BLEND_BLUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      BLEND_BLUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_ALPHA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_ALPHA : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_ALPHA : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FOG_COLOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         FOG_RED : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                         FOG_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK_BF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   STENCILREF_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int                   STENCILREF_BF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTHCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  STENCIL_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                 STENCILZFAIL_BF : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 STENCILZFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  STENCIL_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLENDCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  COLOR_SRCBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                  COLOR_SRCBLEND : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLORCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ALPHA_FUNC : 3;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                                 : 7;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int                                 : 7;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int                      ALPHA_FUNC : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_MODECONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_MODE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                      EDRAM_MODE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_DEST_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COLOR_DEST_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 COLOR_DEST_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                  COPY_DEST_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  COPY_DEST_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PITCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COPY_DEST_PITCH : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                 COPY_DEST_PITCH : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                COPY_DEST_ENDIAN : 3;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_ENDIAN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PIXEL_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        OFFSET_X : 13;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                        OFFSET_X : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     DEPTH_CLEAR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEPTH_CLEAR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_CTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int                                 : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int                       RESERVED9 : 1;
+        unsigned int                      RESERVED10 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED10 : 1;
+        unsigned int                       RESERVED9 : 1;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                                 : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_EDRAM_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_SIZE : 4;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                                 : 8;
+        unsigned int                     EDRAM_RANGE : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     EDRAM_RANGE : 18;
+        unsigned int                                 : 8;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                      EDRAM_SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_RD_PORT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CRC_RD_ADVANCE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                  CRC_RD_ADVANCE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_TOTAL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TOTAL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TOTAL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZPASS_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZPASS_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZPASS_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 TILE_FIFO_COUNT : 4;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z_TILE_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    Z_TILE_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 TILE_FIFO_COUNT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ACCUM_VALID : 4;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int                     ACCUM_VALID : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int                                 : 19;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 19;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FLAG_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_ENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_MOREENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h
new file mode 100644
index 00000000000..2049d0f7bd1
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h
@@ -0,0 +1,4078 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_SHIFT_HEADER)
+#define _yamato_SHIFT_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT          0x00000000
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT           0x00000000
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT          0x00000001
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT           0x00000002
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT          0x00000003
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT           0x00000004
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT          0x00000005
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                  0x00000008
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                   0x00000009
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                  0x0000000a
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT             0x0000000b
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT               0x00000010
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT     0x00000012
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT          0x00000013
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT        0x00000014
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                0x00000015
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT              0x00000016
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT               0x00000017
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT               0x00000018
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT         0x00000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                  0x00000000
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                  0x00000001
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                  0x00000003
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                    0x00000000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT                     0x00000010
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                0x00000000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                0x00000010
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT                      0x00000000
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT              0x00000000
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT               0x00000001
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                    0x00000002
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT               0x00000003
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT    0x00000005
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT     0x00000008
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT             0x0000000f
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT     0x00000012
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT      0x00000013
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT          0x00000014
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT       0x00000015
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT       0x00000017
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT    0x00000019
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT        0x00000000
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT      0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT         0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT       0x00000000
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT        0x00000000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT        0x00000010
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT           0x00000000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT            0x0000000d
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK__SHIFT                      0x00000000
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT            0x00000000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT            0x00000010
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT       0x0000001c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT         0x0000001d
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT                  0x00000000
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT              0x00000008
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT          0x00000009
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                 0x0000000a
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT              0x00000000
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT               0x00000001
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT      0x00000007
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT         0x00000000
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT       0x00000000
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT     0x00000008
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                  0x0000001f
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT  0x00000000
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT   0x00000001
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT  0x00000002
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT   0x00000003
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT     0x0000000d
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT            0x00000014
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT    0x00000013
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT            0x00000018
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT           0x00000018
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT           0x00000008
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT           0x0000001a
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT           0x00000008
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT           0x00000001
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT           0x00000016
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT           0x0000001c
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT   0x00000000
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT           0x00000006
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT           0x0000000c
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT           0x00000012
+#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT        0x00000014
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT   0x0000001c
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT    0x0000001d
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT           0x0000000a
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT           0x00000013
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT            0x00000004
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT           0x00000002
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT           0x00000016
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT      0x00000000
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT     0x00000004
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT    0x0000000e
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT      0x00000014
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT           0x0000001b
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT           0x00000000
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT        0x00000004
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT           0x0000000a
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT            0x0000000d
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT            0x00000011
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT  0x00000013
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT       0x00000017
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT   0x0000001e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT   0x0000001f
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT            0x00000000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT          0x00000002
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT     0x00000004
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT      0x0000000b
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT         0x0000000c
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT                 0x00000014
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT            0x00000015
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT            0x00000017
+#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT        0x00000019
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT                 0x00000000
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT            0x00000001
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT                  0x00000002
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT         0x00000003
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT        0x00000009
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT            0x00000012
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT            0x00000016
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT   0x0000001b
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT    0x0000001c
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT            0x00000004
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT     0x00000005
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT            0x00000008
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT           0x0000000c
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT       0x0000000e
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT        0x0000000f
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT  0x00000012
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT   0x00000013
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT  0x00000015
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT            0x00000016
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT             0x00000000
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT               0x00000005
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT                 0x0000000b
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT               0x0000000c
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT         0x0000000d
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT               0x0000000e
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT                0x0000000f
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT              0x00000010
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT                 0x00000011
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT           0x0000000b
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT          0x0000000c
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT             0x0000000d
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT             0x00000010
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT        0x00000011
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT              0x00000014
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT        0x00000015
+#define SETUP_DEBUG_REG4__type_gated__SHIFT                0x00000017
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT                0x0000001a
+#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT          0x0000001b
+#define SETUP_DEBUG_REG4__event_gated__SHIFT               0x0000001c
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT                 0x0000001d
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT     0x0000000b
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT       0x00000016
+#define SETUP_DEBUG_REG5__event_id_gated__SHIFT            0x00000018
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1__SHIFT                    0x00000000
+#define SC_DEBUG_0__pa_sc_valid__SHIFT                     0x00000001
+#define SC_DEBUG_0__pa_sc_phase__SHIFT                     0x00000002
+#define SC_DEBUG_0__cntx_cnt__SHIFT                        0x00000005
+#define SC_DEBUG_0__decr_cntx_cnt__SHIFT                   0x0000000c
+#define SC_DEBUG_0__incr_cntx_cnt__SHIFT                   0x0000000d
+#define SC_DEBUG_0__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state__SHIFT                        0x00000000
+#define SC_DEBUG_1__em1_data_ready__SHIFT                  0x00000003
+#define SC_DEBUG_1__em2_data_ready__SHIFT                  0x00000004
+#define SC_DEBUG_1__move_em1_to_em2__SHIFT                 0x00000005
+#define SC_DEBUG_1__ef_data_ready__SHIFT                   0x00000006
+#define SC_DEBUG_1__ef_state__SHIFT                        0x00000007
+#define SC_DEBUG_1__pipe_valid__SHIFT                      0x00000009
+#define SC_DEBUG_1__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly__SHIFT                      0x00000000
+#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT            0x00000001
+#define SC_DEBUG_2__pipe_freeze_b__SHIFT                   0x00000003
+#define SC_DEBUG_2__prim_rts__SHIFT                        0x00000004
+#define SC_DEBUG_2__next_prim_rts_dly__SHIFT               0x00000005
+#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT               0x00000006
+#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT               0x00000007
+#define SC_DEBUG_2__stage0_rts__SHIFT                      0x00000008
+#define SC_DEBUG_2__phase_rts_dly__SHIFT                   0x00000009
+#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT              0x0000000f
+#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT              0x00000010
+#define SC_DEBUG_2__event_id_s1__SHIFT                     0x00000011
+#define SC_DEBUG_2__event_s1__SHIFT                        0x00000016
+#define SC_DEBUG_2__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1__SHIFT                       0x00000000
+#define SC_DEBUG_3__y_curr_s1__SHIFT                       0x0000000b
+#define SC_DEBUG_3__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_4__y_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_4__y_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_4__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_5__x_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_5__x_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_5__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty__SHIFT                      0x00000000
+#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT                 0x00000001
+#define SC_DEBUG_6__xy_ff_empty__SHIFT                     0x00000002
+#define SC_DEBUG_6__event_flag__SHIFT                      0x00000003
+#define SC_DEBUG_6__z_mask_needed__SHIFT                   0x00000004
+#define SC_DEBUG_6__state__SHIFT                           0x00000005
+#define SC_DEBUG_6__state_delayed__SHIFT                   0x00000008
+#define SC_DEBUG_6__data_valid__SHIFT                      0x0000000b
+#define SC_DEBUG_6__data_valid_d__SHIFT                    0x0000000c
+#define SC_DEBUG_6__tilex_delayed__SHIFT                   0x0000000d
+#define SC_DEBUG_6__tiley_delayed__SHIFT                   0x00000016
+#define SC_DEBUG_6__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag__SHIFT                      0x00000000
+#define SC_DEBUG_7__deallocate__SHIFT                      0x00000001
+#define SC_DEBUG_7__fpos__SHIFT                            0x00000004
+#define SC_DEBUG_7__sr_prim_we__SHIFT                      0x00000005
+#define SC_DEBUG_7__last_tile__SHIFT                       0x00000006
+#define SC_DEBUG_7__tile_ff_we__SHIFT                      0x00000007
+#define SC_DEBUG_7__qs_data_valid__SHIFT                   0x00000008
+#define SC_DEBUG_7__qs_q0_y__SHIFT                         0x00000009
+#define SC_DEBUG_7__qs_q0_x__SHIFT                         0x0000000b
+#define SC_DEBUG_7__qs_q0_valid__SHIFT                     0x0000000d
+#define SC_DEBUG_7__prim_ff_we__SHIFT                      0x0000000e
+#define SC_DEBUG_7__tile_ff_re__SHIFT                      0x0000000f
+#define SC_DEBUG_7__fw_prim_data_valid__SHIFT              0x00000010
+#define SC_DEBUG_7__last_quad_of_tile__SHIFT               0x00000011
+#define SC_DEBUG_7__first_quad_of_tile__SHIFT              0x00000012
+#define SC_DEBUG_7__first_quad_of_prim__SHIFT              0x00000013
+#define SC_DEBUG_7__new_prim__SHIFT                        0x00000014
+#define SC_DEBUG_7__load_new_tile_data__SHIFT              0x00000015
+#define SC_DEBUG_7__state__SHIFT                           0x00000016
+#define SC_DEBUG_7__fifos_ready__SHIFT                     0x00000018
+#define SC_DEBUG_7__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last__SHIFT                     0x00000000
+#define SC_DEBUG_8__sample_mask__SHIFT                     0x00000001
+#define SC_DEBUG_8__sample_y__SHIFT                        0x00000005
+#define SC_DEBUG_8__sample_x__SHIFT                        0x00000007
+#define SC_DEBUG_8__sample_send__SHIFT                     0x00000009
+#define SC_DEBUG_8__next_cycle__SHIFT                      0x0000000a
+#define SC_DEBUG_8__ez_sample_ff_full__SHIFT               0x0000000c
+#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT                  0x0000000d
+#define SC_DEBUG_8__num_samples__SHIFT                     0x0000000e
+#define SC_DEBUG_8__last_quad_of_tile__SHIFT               0x00000010
+#define SC_DEBUG_8__last_quad_of_prim__SHIFT               0x00000011
+#define SC_DEBUG_8__first_quad_of_prim__SHIFT              0x00000012
+#define SC_DEBUG_8__sample_we__SHIFT                       0x00000013
+#define SC_DEBUG_8__fpos__SHIFT                            0x00000014
+#define SC_DEBUG_8__event_id__SHIFT                        0x00000015
+#define SC_DEBUG_8__event_flag__SHIFT                      0x0000001a
+#define SC_DEBUG_8__fw_prim_data_valid__SHIFT              0x0000001b
+#define SC_DEBUG_8__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send__SHIFT                      0x00000000
+#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT                   0x00000001
+#define SC_DEBUG_9__fifo_data_ready__SHIFT                 0x00000005
+#define SC_DEBUG_9__early_z_enable__SHIFT                  0x00000006
+#define SC_DEBUG_9__mask_state__SHIFT                      0x00000007
+#define SC_DEBUG_9__next_ez_mask__SHIFT                    0x00000009
+#define SC_DEBUG_9__mask_ready__SHIFT                      0x00000019
+#define SC_DEBUG_9__drop_sample__SHIFT                     0x0000001a
+#define SC_DEBUG_9__fetch_new_sample_data__SHIFT           0x0000001b
+#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT        0x0000001c
+#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT       0x0000001d
+#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT         0x0000001e
+#define SC_DEBUG_9__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask__SHIFT           0x00000000
+#define SC_DEBUG_10__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready__SHIFT           0x00000000
+#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT      0x00000001
+#define SC_DEBUG_11__ez_prim_data_ready__SHIFT             0x00000002
+#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT        0x00000003
+#define SC_DEBUG_11__iterator_input_fz__SHIFT              0x00000004
+#define SC_DEBUG_11__packer_send_quads__SHIFT              0x00000005
+#define SC_DEBUG_11__packer_send_cmd__SHIFT                0x00000006
+#define SC_DEBUG_11__packer_send_event__SHIFT              0x00000007
+#define SC_DEBUG_11__next_state__SHIFT                     0x00000008
+#define SC_DEBUG_11__state__SHIFT                          0x0000000b
+#define SC_DEBUG_11__stall__SHIFT                          0x0000000e
+#define SC_DEBUG_11__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT          0x00000000
+#define SC_DEBUG_12__event_id__SHIFT                       0x00000001
+#define SC_DEBUG_12__event_flag__SHIFT                     0x00000006
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT        0x00000007
+#define SC_DEBUG_12__itercmdfifo_full__SHIFT               0x00000008
+#define SC_DEBUG_12__itercmdfifo_empty__SHIFT              0x00000009
+#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT        0x0000000a
+#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT           0x0000000b
+#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT          0x0000000c
+#define SC_DEBUG_12__iter_qdhit0__SHIFT                    0x0000000d
+#define SC_DEBUG_12__bc_use_centers_reg__SHIFT             0x0000000e
+#define SC_DEBUG_12__bc_output_xy_reg__SHIFT               0x0000000f
+#define SC_DEBUG_12__iter_phase_out__SHIFT                 0x00000010
+#define SC_DEBUG_12__iter_phase_reg__SHIFT                 0x00000012
+#define SC_DEBUG_12__iterator_SP_valid__SHIFT              0x00000014
+#define SC_DEBUG_12__eopv_reg__SHIFT                       0x00000015
+#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT                0x00000016
+#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT            0x00000017
+#define SC_DEBUG_12__trigger__SHIFT                        0x0000001f
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                0x00000000
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT               0x00000000
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT           0x00000006
+#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT              0x0000000b
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                 0x0000000c
+#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT             0x0000000d
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT   0x0000000e
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT         0x0000000f
+#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT             0x00000010
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT             0x00000000
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT                     0x00000000
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_DMA_SIZE__SWAP_MODE__SHIFT                     0x0000001e
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT                 0x00000000
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS__SHIFT                     0x00000000
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                  0x00000000
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                  0x00000000
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                0x00000000
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT          0x00000000
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT    0x00000000
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT                           0x00000000
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT          0x00000000
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT           0x00000000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT           0x00000010
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT              0x00000000
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                   0x00000000
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT               0x00000001
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT           0x00000002
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT               0x00000003
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                0x00000004
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT               0x00000005
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                0x00000006
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT               0x00000007
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT          0x00000008
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy__SHIFT                 0x00000000
+#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT                 0x00000001
+#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT                 0x00000002
+#define VGT_DEBUG_REG0__dma_request_busy__SHIFT            0x00000003
+#define VGT_DEBUG_REG0__out_busy__SHIFT                    0x00000004
+#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT            0x00000005
+#define VGT_DEBUG_REG0__grp_busy__SHIFT                    0x00000006
+#define VGT_DEBUG_REG0__dma_busy__SHIFT                    0x00000007
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT       0x00000008
+#define VGT_DEBUG_REG0__rbiu_busy__SHIFT                   0x00000009
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT    0x0000000a
+#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT             0x0000000b
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT           0x0000000c
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT                    0x0000000d
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT     0x0000000e
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT        0x0000000f
+#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT               0x00000010
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read__SHIFT            0x00000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT           0x00000001
+#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT            0x00000002
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT           0x00000003
+#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT            0x00000004
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT           0x00000005
+#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT            0x00000006
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT           0x00000007
+#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT            0x00000008
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT           0x00000009
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT                 0x0000000a
+#define VGT_DEBUG_REG1__grp_te_valid__SHIFT                0x0000000b
+#define VGT_DEBUG_REG1__pt_grp_read__SHIFT                 0x0000000c
+#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT                0x0000000d
+#define VGT_DEBUG_REG1__vr_grp_read__SHIFT                 0x0000000e
+#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT                0x0000000f
+#define VGT_DEBUG_REG1__grp_dma_read__SHIFT                0x00000010
+#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT               0x00000011
+#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT            0x00000012
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT           0x00000013
+#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT                  0x00000014
+#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT                 0x00000015
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT           0x00000016
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT          0x00000017
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT           0x00000018
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT          0x00000019
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT           0x0000001a
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT          0x0000001b
+#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT                  0x0000001c
+#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT                 0x0000001d
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT              0x0000001e
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT                  0x00000000
+#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT            0x00000001
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT        0x00000000
+#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT           0x00000005
+#define VGT_DEBUG_REG6__input_data_valid__SHIFT            0x0000000a
+#define VGT_DEBUG_REG6__input_data_xfer__SHIFT             0x0000000b
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT      0x0000000c
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT      0x0000000d
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT  0x0000000e
+#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT      0x0000000f
+#define VGT_DEBUG_REG6__shifter_first_load__SHIFT          0x00000010
+#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT       0x00000013
+#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT             0x00000014
+#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT         0x00000015
+#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT        0x00000017
+#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT         0x00000018
+#define VGT_DEBUG_REG6__extract_vector__SHIFT              0x00000019
+#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT              0x0000001a
+#define VGT_DEBUG_REG6__destination_rtr__SHIFT             0x0000001b
+#define VGT_DEBUG_REG6__grp_trigger__SHIFT                 0x0000001c
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT          0x00000000
+#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT     0x00000010
+#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT        0x00000014
+#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG7__current_source_sel__SHIFT          0x0000001e
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel__SHIFT          0x00000000
+#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT            0x00000002
+#define VGT_DEBUG_REG8__input_data_cnt__SHIFT              0x00000007
+#define VGT_DEBUG_REG8__input_data_lsw__SHIFT              0x0000000c
+#define VGT_DEBUG_REG8__input_data_msw__SHIFT              0x00000011
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q__SHIFT               0x00000000
+#define VGT_DEBUG_REG9__next_stride_d__SHIFT               0x00000005
+#define VGT_DEBUG_REG9__current_shift_q__SHIFT             0x0000000a
+#define VGT_DEBUG_REG9__current_shift_d__SHIFT             0x0000000f
+#define VGT_DEBUG_REG9__current_stride_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG9__current_stride_d__SHIFT            0x00000019
+#define VGT_DEBUG_REG9__grp_trigger__SHIFT                 0x0000001e
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003
+#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT             0x00000004
+#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT        0x00000005
+#define VGT_DEBUG_REG10__bin_valid__SHIFT                  0x00000006
+#define VGT_DEBUG_REG10__read_block__SHIFT                 0x00000007
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT     0x00000008
+#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT          0x00000009
+#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG10__selected_data__SHIFT              0x0000000b
+#define VGT_DEBUG_REG10__mask_input_data__SHIFT            0x00000013
+#define VGT_DEBUG_REG10__gap_q__SHIFT                      0x0000001b
+#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT          0x0000001c
+#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT          0x0000001d
+#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT          0x0000001e
+#define VGT_DEBUG_REG10__grp_trigger__SHIFT                0x0000001f
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT       0x00000000
+#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT          0x00000005
+#define VGT_DEBUG_REG12__input_data_valid__SHIFT           0x0000000a
+#define VGT_DEBUG_REG12__input_data_xfer__SHIFT            0x0000000b
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT     0x0000000c
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT     0x0000000d
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e
+#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT     0x0000000f
+#define VGT_DEBUG_REG12__shifter_first_load__SHIFT         0x00000010
+#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT             0x00000011
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT      0x00000013
+#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT        0x00000015
+#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT       0x00000017
+#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT        0x00000018
+#define VGT_DEBUG_REG12__extract_vector__SHIFT             0x00000019
+#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT             0x0000001a
+#define VGT_DEBUG_REG12__destination_rtr__SHIFT            0x0000001b
+#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT               0x0000001c
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT         0x00000000
+#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT    0x00000010
+#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT       0x00000014
+#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT             0x00000018
+#define VGT_DEBUG_REG13__current_source_sel__SHIFT         0x0000001e
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel__SHIFT         0x00000000
+#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT           0x00000002
+#define VGT_DEBUG_REG14__input_data_cnt__SHIFT             0x00000007
+#define VGT_DEBUG_REG14__input_data_lsw__SHIFT             0x0000000c
+#define VGT_DEBUG_REG14__input_data_msw__SHIFT             0x00000011
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q__SHIFT              0x00000000
+#define VGT_DEBUG_REG15__next_stride_d__SHIFT              0x00000005
+#define VGT_DEBUG_REG15__current_shift_q__SHIFT            0x0000000a
+#define VGT_DEBUG_REG15__current_shift_d__SHIFT            0x0000000f
+#define VGT_DEBUG_REG15__current_stride_q__SHIFT           0x00000014
+#define VGT_DEBUG_REG15__current_stride_d__SHIFT           0x00000019
+#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT               0x0000001e
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT  0x00000000
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT   0x00000002
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT    0x00000003
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT   0x00000004
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT  0x00000005
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT   0x00000006
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT     0x00000007
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT         0x00000008
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT         0x00000009
+#define VGT_DEBUG_REG16__rst_last_bit__SHIFT               0x0000000a
+#define VGT_DEBUG_REG16__current_state_q__SHIFT            0x0000000b
+#define VGT_DEBUG_REG16__old_state_q__SHIFT                0x0000000c
+#define VGT_DEBUG_REG16__old_state_en__SHIFT               0x0000000d
+#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT            0x0000000e
+#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT             0x0000000f
+#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT           0x00000010
+#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT           0x00000011
+#define VGT_DEBUG_REG16__load_empty_reg__SHIFT             0x00000012
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT   0x00000013
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT   0x0000001e
+#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q__SHIFT                0x00000000
+#define VGT_DEBUG_REG17__extend_read_q__SHIFT              0x00000001
+#define VGT_DEBUG_REG17__grp_indx_size__SHIFT              0x00000002
+#define VGT_DEBUG_REG17__cull_prim_true__SHIFT             0x00000004
+#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT               0x00000005
+#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT               0x00000006
+#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT          0x00000007
+#define VGT_DEBUG_REG17__check_second_reg__SHIFT           0x00000008
+#define VGT_DEBUG_REG17__check_first_reg__SHIFT            0x00000009
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT    0x0000000b
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT    0x0000000c
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT     0x0000000d
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT     0x0000000e
+#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT            0x0000000f
+#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT            0x00000010
+#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT    0x00000000
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT    0x00000006
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d
+#define VGT_DEBUG_REG18__dma_mem_full__SHIFT               0x0000000f
+#define VGT_DEBUG_REG18__dma_ram_re__SHIFT                 0x00000010
+#define VGT_DEBUG_REG18__dma_ram_we__SHIFT                 0x00000011
+#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT              0x00000012
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT       0x00000013
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT       0x00000014
+#define VGT_DEBUG_REG18__bin_mem_full__SHIFT               0x00000015
+#define VGT_DEBUG_REG18__bin_ram_we__SHIFT                 0x00000016
+#define VGT_DEBUG_REG18__bin_ram_re__SHIFT                 0x00000017
+#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT              0x00000018
+#define VGT_DEBUG_REG18__start_bin_req__SHIFT              0x00000019
+#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT        0x0000001a
+#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT               0x0000001b
+#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT         0x0000001c
+#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT         0x0000001d
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT       0x00000000
+#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT       0x00000001
+#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT          0x00000002
+#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT          0x00000003
+#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT        0x00000004
+#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT          0x00000005
+#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT             0x00000006
+#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT             0x00000007
+#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT           0x00000008
+#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT          0x00000009
+#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT             0x0000000a
+#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT             0x0000000b
+#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT           0x0000000c
+#define VGT_DEBUG_REG20__hold_prim__SHIFT                  0x0000000d
+#define VGT_DEBUG_REG20__sent_cnt__SHIFT                   0x0000000e
+#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT        0x00000012
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT       0x00000013
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT       0x00000014
+#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT   0x00000015
+#define VGT_DEBUG_REG20__out_trigger__SHIFT                0x0000001a
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT  0x00000000
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001
+#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT            0x00000004
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT    0x00000007
+#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT    0x0000000e
+#define VGT_DEBUG_REG21__new_packet_q__SHIFT               0x00000012
+#define VGT_DEBUG_REG21__new_allocate_q__SHIFT             0x00000013
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT    0x00000014
+#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT       0x00000016
+#define VGT_DEBUG_REG21__insert_null_prim__SHIFT           0x00000017
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT      0x00000018
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT      0x00000019
+#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT       0x0000001a
+#define VGT_DEBUG_REG21__out_trigger__SHIFT                0x0000001f
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC__SHIFT                        0x00000000
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC__SHIFT                        0x00000000
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT             0x00000000
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT               0x00000000
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT              0x00000012
+#define TC_CNTL_STATUS__TC_BUSY__SHIFT                     0x0000001f
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT               0x00000008
+#define TCM_CHICKEN__SPARE__SHIFT                          0x00000009
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT          0x00000000
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT          0x00000003
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT             0x00000000
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT           0x00000001
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT        0x00000002
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT        0x00000003
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT       0x00000004
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT         0x00000005
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT            0x00000006
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT      0x00000008
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT        0x00000009
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT           0x0000000a
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT           0x0000000c
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT        0x0000000d
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT          0x0000000e
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT             0x0000000f
+#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT                  0x00000010
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT            0x00000011
+#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT                  0x00000013
+#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT                  0x00000014
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT               0x00000015
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT             0x00000016
+#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT                  0x00000017
+#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT                  0x00000018
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT               0x00000019
+#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT                  0x0000001b
+#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT                  0x0000001c
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT          0x0000001d
+#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT                  0x0000001e
+#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT                   0x0000001f
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL__SHIFT                        0x00000000
+#define TPC_DEBUG0__IC_CTR__SHIFT                          0x00000002
+#define TPC_DEBUG0__WALKER_CNTL__SHIFT                     0x00000004
+#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT                    0x00000008
+#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT             0x0000000c
+#define TPC_DEBUG0__WALKER_STATE__SHIFT                    0x00000010
+#define TPC_DEBUG0__ALIGNER_STATE__SHIFT                   0x0000001a
+#define TPC_DEBUG0__REG_CLK_EN__SHIFT                      0x0000001d
+#define TPC_DEBUG0__TPC_CLK_EN__SHIFT                      0x0000001e
+#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT                    0x0000001f
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED__SHIFT                          0x00000000
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION__SHIFT                0x00000000
+#define TPC_CHICKEN__SPARE__SHIFT                          0x00000001
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT              0x00000000
+#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT                0x00000001
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT           0x00000002
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT               0x00000003
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT         0x00000004
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT            0x00000005
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT            0x00000006
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT            0x00000007
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT              0x00000008
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT           0x00000009
+#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT                 0x0000000a
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT            0x0000000b
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT              0x0000000c
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT           0x0000000d
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT             0x0000000e
+#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT                  0x00000010
+#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT                  0x00000011
+#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT                  0x00000012
+#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT                  0x00000013
+#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT                  0x00000014
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT               0x00000015
+#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT                  0x00000016
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT               0x00000017
+#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT                  0x00000018
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT               0x00000019
+#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT                  0x0000001a
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT               0x0000001b
+#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT                  0x0000001c
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT             0x0000001d
+#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT                  0x0000001e
+#define TP0_CNTL_STATUS__TP_BUSY__SHIFT                    0x0000001f
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL__SHIFT                       0x00000000
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT                   0x00000003
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT             0x00000004
+#define TP0_DEBUG__REG_CLK_EN__SHIFT                       0x00000015
+#define TP0_DEBUG__PERF_CLK_EN__SHIFT                      0x00000016
+#define TP0_DEBUG__TP_CLK_EN__SHIFT                        0x00000017
+#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT                    0x00000018
+#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT                   0x0000001c
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE__SHIFT                        0x00000000
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT            0x00000001
+#define TP0_CHICKEN__SPARE__SHIFT                          0x00000002
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr__SHIFT                    0x00000006
+#define TCF_DEBUG__TC_MH_send__SHIFT                       0x00000007
+#define TCF_DEBUG__not_FG0_rtr__SHIFT                      0x00000008
+#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT                  0x0000000c
+#define TCF_DEBUG__TCB_ff_stall__SHIFT                     0x0000000d
+#define TCF_DEBUG__TCB_miss_stall__SHIFT                   0x0000000e
+#define TCF_DEBUG__TCA_TCB_stall__SHIFT                    0x0000000f
+#define TCF_DEBUG__PF0_stall__SHIFT                        0x00000010
+#define TCF_DEBUG__TP0_full__SHIFT                         0x00000014
+#define TCF_DEBUG__TPC_full__SHIFT                         0x00000018
+#define TCF_DEBUG__not_TPC_rtr__SHIFT                      0x00000019
+#define TCF_DEBUG__tca_state_rts__SHIFT                    0x0000001a
+#define TCF_DEBUG__tca_rts__SHIFT                          0x0000001b
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full__SHIFT                    0x00000000
+#define TCA_FIFO_DEBUG__tpc_full__SHIFT                    0x00000004
+#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT               0x00000005
+#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT               0x00000006
+#define TCA_FIFO_DEBUG__FW_full__SHIFT                     0x00000007
+#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT                 0x00000008
+#define TCA_FIFO_DEBUG__FW_rts0__SHIFT                     0x0000000c
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT              0x00000010
+#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT                  0x00000011
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT          0x00000000
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts__SHIFT             0x0000000c
+#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT              0x0000000d
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512__SHIFT                   0x00000000
+#define TCB_CORE_DEBUG__tiled__SHIFT                       0x00000001
+#define TCB_CORE_DEBUG__opcode__SHIFT                      0x00000004
+#define TCB_CORE_DEBUG__format__SHIFT                      0x00000008
+#define TCB_CORE_DEBUG__sector_format__SHIFT               0x00000010
+#define TCB_CORE_DEBUG__sector_format512__SHIFT            0x00000018
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG0_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG0_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG1_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG1_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG2_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG2_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG3_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG3_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT   0x00000004
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT    0x00000006
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT   0x0000000b
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT   0x0000000c
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT            0x0000000f
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT      0x00000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT       0x00000002
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT    0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT             0x00000017
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT         0x00000018
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT          0x00000019
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT         0x0000001a
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT          0x0000001c
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT          0x0000001e
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty__SHIFT                     0x00000010
+#define TCD_INPUT0_DEBUG__full__SHIFT                      0x00000011
+#define TCD_INPUT0_DEBUG__valid_q1__SHIFT                  0x00000014
+#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT                    0x00000015
+#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT              0x00000017
+#define TCD_INPUT0_DEBUG__ip_send__SHIFT                   0x00000018
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT            0x00000019
+#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT                0x0000001a
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT      0x00000000
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT          0x00000002
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT      0x00000003
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT           0x00000004
+#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT               0x00000005
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT              0x00000006
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT             0x00000009
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT         0x0000000a
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT           0x0000000b
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT  0x00000014
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT   0x0000001c
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT      0x0000001d
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT                0x00000004
+#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT                  0x00000005
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT    0x00000006
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT          0x00000007
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT       0x00000009
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT    0x0000000c
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT       0x00000012
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT         0x0000001e
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT         0x0000001f
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT   0x0000000a
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT   0x0000000b
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT         0x00000011
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT       0x00000012
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT          0x00000013
+#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT          0x0000001f
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT          0x00000005
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT           0x00000006
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT       0x00000007
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT       0x00000000
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT       0x00000008
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT                 0x00000009
+#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT                 0x0000000a
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT      0x0000000b
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT                0x0000000c
+#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT                0x0000000d
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT           0x00000010
+#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT              0x00000018
+#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT            0x00000019
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT  0x0000001a
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT  0x0000001b
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT  0x0000001c
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT  0x0000001d
+#define TCO_QUAD0_DEBUG0__busy__SHIFT                      0x0000001e
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT                 0x00000000
+#define TCO_QUAD0_DEBUG1__empty__SHIFT                     0x00000001
+#define TCO_QUAD0_DEBUG1__full__SHIFT                      0x00000002
+#define TCO_QUAD0_DEBUG1__write_enable__SHIFT              0x00000003
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT            0x00000004
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT             0x0000000b
+#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT           0x00000014
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT         0x00000015
+#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT           0x00000016
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT        0x00000017
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT             0x00000018
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT             0x00000019
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT                 0x0000001a
+#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT                 0x0000001b
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT                0x0000001c
+#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT                0x0000001d
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT          0x0000001e
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT              0x00000000
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT             0x00000004
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT             0x0000000c
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT   0x00000000
+#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT                 0x00000004
+#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT                    0x00000008
+#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT                 0x0000000c
+#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT                   0x00000010
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT               0x00000011
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT          0x00000012
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT      0x00000015
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT     0x00000016
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT               0x00000017
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT               0x00000018
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT           0x00000019
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT    0x0000001b
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT      0x00000000
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT      0x00000010
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT   0x00000010
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT                   0x00000000
+#define SQ_EO_RT__EO_TSTATE_RT__SHIFT                      0x00000010
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT               0x00000000
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT               0x0000000c
+#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT                  0x00000014
+#define SQ_DEBUG_MISC__RESERVED__SHIFT                     0x00000015
+#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT               0x00000017
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT              0x00000019
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT              0x0000001a
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT              0x0000001b
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT              0x0000001c
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT            0x00000000
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT       0x00000008
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT      0x00000010
+#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT               0x00000018
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT      0x00000000
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT      0x00000000
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT        0x00000003
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT      0x00000004
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT        0x00000007
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT            0x00000008
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT     0x00000000
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT       0x00000003
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT     0x00000004
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT       0x00000007
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT           0x00000008
+#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT            0x00000012
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT               0x00000000
+#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT                0x00000003
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT               0x00000004
+#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT                 0x00000008
+#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT                   0x0000000c
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT           0x0000000f
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT             0x00000014
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT           0x00000005
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT           0x0000000d
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT                      0x00000000
+#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT                  0x00000003
+#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT                      0x00000004
+#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT                      0x00000008
+#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT                  0x0000000b
+#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT                     0x0000000c
+#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT                  0x0000000e
+#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT                      0x00000010
+#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT                  0x00000012
+#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT                     0x00000014
+#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT                  0x00000016
+#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT                     0x00000018
+#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT                  0x0000001a
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT                  0x0000001c
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT           0x00000000
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT         0x00000004
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT            0x0000000c
+#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT                0x0000000f
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT     0x00000010
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT            0x00000000
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT              0x00000001
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT          0x00000005
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT         0x00000006
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT              0x00000009
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT               0x0000000e
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT        0x0000000f
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT                 0x00000010
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT             0x00000011
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT   0x0000001d
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT           0x00000000
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT               0x00000004
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT               0x00000008
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT        0x0000000c
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT         0x00000010
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT            0x00000014
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT                   0x00000015
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT              0x00000000
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT   0x00000000
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT     0x00000000
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT             0x00000000
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT                 0x00000006
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT                 0x0000000c
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT        0x00000013
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT          0x00000019
+#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT                     0x0000001f
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD__SHIFT         0x00000006
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT  0x00000007
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT           0x0000000f
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT        0x00000010
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT        0x00000014
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT          0x00000018
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT          0x00000019
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT         0x0000001a
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT       0x00000000
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT       0x00000002
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT       0x00000004
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT       0x00000006
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT       0x00000008
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT       0x0000000c
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT       0x0000000e
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT       0x00000010
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT       0x00000012
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT       0x00000014
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT       0x00000016
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT         0x00000019
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT           0x0000001b
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT       0x0000001e
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT       0x0000001f
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT          0x00000006
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT         0x00000007
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT          0x0000000e
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT         0x00000010
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT          0x00000016
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT         0x00000017
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT             0x0000001d
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT             0x0000001e
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT          0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT             0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT             0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT       0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT     0x00000013
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT       0x00000014
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT     0x00000015
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT       0x00000016
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT     0x00000017
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT       0x00000018
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT     0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT       0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT     0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT         0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT         0x0000001e
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT         0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT         0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT         0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT         0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT          0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT             0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT       0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT     0x00000003
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT       0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT     0x00000005
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT       0x00000006
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT     0x00000007
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT       0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT     0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT     0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT         0x0000000d
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT         0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT         0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT         0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT        0x0000000a
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT        0x00000015
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT        0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT        0x0000001a
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT          0x00000005
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT    0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT    0x0000000d
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT    0x0000000f
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT    0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT     0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT     0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT  0x0000000b
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT        0x0000000c
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT    0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT    0x0000001d
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT    0x0000001e
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT      0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT     0x00000012
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT  0x0000001b
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT        0x0000001c
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT         0x00000004
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT        0x00000008
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT    0x00000009
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT       0x0000000b
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT           0x0000000c
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT             0x00000010
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT       0x00000014
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT        0x00000018
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT    0x00000019
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT       0x0000001b
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT           0x0000001c
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT   0x00000013
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT    0x00000019
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT          0x0000001a
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT          0x0000001c
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT          0x0000001e
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT         0x00000010
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT       0x00000012
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT   0x00000015
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT     0x00000018
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT       0x0000001c
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT        0x0000001d
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT  0x00000000
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT    0x00000001
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT           0x00000002
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT             0x00000009
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT           0x00000010
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT           0x00000015
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT           0x0000001a
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT        0x00000013
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT    0x00000019
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT            0x0000001e
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT    0x0000000c
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT     0x0000000d
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT        0x00000010
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT     0x00000017
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT             0x00000010
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED__SHIFT                          0x00000000
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN__SHIFT                        0x00000000
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE__SHIFT                         0x00000000
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA__SHIFT                        0x00000000
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE__SHIFT                           0x00000000
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT                  0x00000000
+#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT                 0x00000001
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT          0x00000002
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT           0x00000000
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT         0x00000002
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE__SHIFT                       0x00000000
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE__SHIFT                       0x00000000
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT               0x00000000
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT               0x00000008
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT               0x00000010
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT               0x00000018
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT                   0x00000000
+#define SQ_CF_LOOP__CF_LOOP_START__SHIFT                   0x00000008
+#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT                    0x00000010
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED__SHIFT                       0x00000000
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN__SHIFT                     0x00000000
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE__SHIFT                      0x00000000
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA__SHIFT                     0x00000000
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE__SHIFT                        0x00000000
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT            0x00000000
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT            0x00000008
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT            0x00000010
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT            0x00000018
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT                0x00000000
+#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT                0x00000008
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT                 0x00000010
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_VS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_PS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT              0x00000000
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT              0x0000000c
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT           0x00000000
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT      0x00000010
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT                 0x00000000
+#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT                 0x00000008
+#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT                0x00000010
+#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT                0x00000011
+#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT                  0x00000012
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT              0x00000013
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT            0x00000014
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT             0x00000018
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT             0x0000001b
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT              0x0000001f
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT                 0x00000000
+#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT                 0x00000004
+#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT                 0x00000008
+#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT                 0x0000000c
+#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT                 0x00000010
+#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT                 0x00000014
+#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT                 0x00000018
+#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT                 0x0000001c
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT                 0x00000000
+#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT                 0x00000004
+#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT                0x00000008
+#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT                0x0000000c
+#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT                0x00000010
+#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT                0x00000014
+#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT                0x00000018
+#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT                0x0000001c
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_VS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_PS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT         0x00000000
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT        0x00000001
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT             0x00000002
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT              0x00000008
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT            0x00000010
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT             0x00000011
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT               0x00000012
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE__SHIFT                      0x00000000
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT                 0x00000000
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT              0x00000004
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT               0x00000008
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT              0x00000018
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT                  0x00000000
+#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT                  0x00000001
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT              0x00000008
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT              0x00000010
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT          0x00000000
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT    0x00000006
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT            0x00000007
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT       0x00000008
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT           0x00000009
+#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT                0x0000000a
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT        0x0000000d
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT       0x0000000e
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT   0x0000000f
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT          0x00000010
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT           0x00000016
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT          0x00000017
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT           0x00000018
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT           0x00000019
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT                0x00000000
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT             0x00000003
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT                0x00000004
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT             0x00000007
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT               0x00000008
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT           0x00000000
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT          0x00000001
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT           0x00000002
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT         0x00000000
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT        0x00000001
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT         0x00000002
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT          0x00000000
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT         0x00000001
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT          0x00000002
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID__SHIFT                   0x00000000
+#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT                0x00000003
+#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT                  0x00000004
+#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT               0x00000007
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX__SHIFT                        0x00000000
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA__SHIFT                         0x00000000
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY__SHIFT                     0x00000000
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT           0x00000001
+#define MH_DEBUG_REG00__CP_REQUEST__SHIFT                  0x00000002
+#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT                 0x00000003
+#define MH_DEBUG_REG00__TC_REQUEST__SHIFT                  0x00000004
+#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT                0x00000005
+#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT                 0x00000006
+#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT                   0x00000007
+#define MH_DEBUG_REG00__TCD_FULL__SHIFT                    0x00000008
+#define MH_DEBUG_REG00__RB_REQUEST__SHIFT                  0x00000009
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT             0x0000000a
+#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT                   0x0000000b
+#define MH_DEBUG_REG00__ARQ_FULL__SHIFT                    0x0000000c
+#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT                   0x0000000d
+#define MH_DEBUG_REG00__WDB_FULL__SHIFT                    0x0000000e
+#define MH_DEBUG_REG00__AXI_AVALID__SHIFT                  0x0000000f
+#define MH_DEBUG_REG00__AXI_AREADY__SHIFT                  0x00000010
+#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT                 0x00000011
+#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT                 0x00000012
+#define MH_DEBUG_REG00__AXI_WVALID__SHIFT                  0x00000013
+#define MH_DEBUG_REG00__AXI_WREADY__SHIFT                  0x00000014
+#define MH_DEBUG_REG00__AXI_RVALID__SHIFT                  0x00000015
+#define MH_DEBUG_REG00__AXI_RREADY__SHIFT                  0x00000016
+#define MH_DEBUG_REG00__AXI_BVALID__SHIFT                  0x00000017
+#define MH_DEBUG_REG00__AXI_BREADY__SHIFT                  0x00000018
+#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT                0x00000019
+#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT                0x0000001a
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q__SHIFT                   0x00000000
+#define MH_DEBUG_REG01__CP_RTR_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT                  0x00000002
+#define MH_DEBUG_REG01__CP_TAG_q__SHIFT                    0x00000003
+#define MH_DEBUG_REG01__CP_BE_q__SHIFT                     0x00000006
+#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT                  0x0000000e
+#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT                   0x0000000f
+#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT                   0x00000010
+#define MH_DEBUG_REG01__TC_SEND_q__SHIFT                   0x00000011
+#define MH_DEBUG_REG01__TC_RTR_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT               0x00000013
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT                0x00000014
+#define MH_DEBUG_REG01__TC_MH_written__SHIFT               0x00000015
+#define MH_DEBUG_REG01__RB_SEND_q__SHIFT                   0x00000016
+#define MH_DEBUG_REG01__RB_RTR_q__SHIFT                    0x00000017
+#define MH_DEBUG_REG01__RB_BE_q__SHIFT                     0x00000018
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT               0x00000003
+#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT                 0x00000004
+#define MH_DEBUG_REG02__RDC_RID__SHIFT                     0x00000007
+#define MH_DEBUG_REG02__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT            0x0000000c
+#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT            0x0000000d
+#define MH_DEBUG_REG02__BRC_BID__SHIFT                     0x0000000e
+#define MH_DEBUG_REG02__BRC_BRESP__SHIFT                   0x00000011
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT           0x00000000
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT          0x00000000
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG05__CP_MH_write__SHIFT                 0x00000001
+#define MH_DEBUG_REG05__CP_MH_tag__SHIFT                   0x00000002
+#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT               0x00000005
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG08__VGT_MH_send__SHIFT                 0x00000003
+#define MH_DEBUG_REG08__VGT_MH_tagbe__SHIFT                0x00000004
+#define MH_DEBUG_REG08__VGT_MH_ad_31_5__SHIFT              0x00000005
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG09__TC_MH_send__SHIFT                  0x00000002
+#define MH_DEBUG_REG09__TC_MH_mask__SHIFT                  0x00000003
+#define MH_DEBUG_REG09__TC_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__TC_MH_info__SHIFT                  0x00000000
+#define MH_DEBUG_REG10__TC_MH_send__SHIFT                  0x00000019
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__MH_TC_mcinfo__SHIFT                0x00000000
+#define MH_DEBUG_REG11__MH_TC_mcinfo_send__SHIFT           0x00000019
+#define MH_DEBUG_REG11__TC_MH_written__SHIFT               0x0000001a
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG12__TC_ROQ_SEND__SHIFT                 0x00000002
+#define MH_DEBUG_REG12__TC_ROQ_MASK__SHIFT                 0x00000003
+#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5__SHIFT            0x00000005
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__TC_ROQ_INFO__SHIFT                 0x00000000
+#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT                 0x00000019
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG14__RB_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG14__RB_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__RB_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG17__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG17__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG17__ALEN_q_2_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG17__ARVALID_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG17__ARREADY_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG17__ARID_q__SHIFT                      0x0000000a
+#define MH_DEBUG_REG17__ARLEN_q_1_0__SHIFT                 0x0000000d
+#define MH_DEBUG_REG17__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG17__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG17__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG17__RID_q__SHIFT                       0x00000012
+#define MH_DEBUG_REG17__WVALID_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG17__WREADY_q__SHIFT                    0x00000016
+#define MH_DEBUG_REG17__WLAST_q__SHIFT                     0x00000017
+#define MH_DEBUG_REG17__WID_q__SHIFT                       0x00000018
+#define MH_DEBUG_REG17__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG17__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG17__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG18__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG18__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG18__ALEN_q_1_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG18__ARVALID_q__SHIFT                   0x00000007
+#define MH_DEBUG_REG18__ARREADY_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG18__ARID_q__SHIFT                      0x00000009
+#define MH_DEBUG_REG18__ARLEN_q_1_1__SHIFT                 0x0000000c
+#define MH_DEBUG_REG18__WVALID_q__SHIFT                    0x0000000d
+#define MH_DEBUG_REG18__WREADY_q__SHIFT                    0x0000000e
+#define MH_DEBUG_REG18__WLAST_q__SHIFT                     0x0000000f
+#define MH_DEBUG_REG18__WID_q__SHIFT                       0x00000010
+#define MH_DEBUG_REG18__WSTRB_q__SHIFT                     0x00000013
+#define MH_DEBUG_REG18__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG18__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG18__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__ARC_CTRL_RE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG19__CTRL_ARC_ID__SHIFT                 0x00000001
+#define MH_DEBUG_REG19__CTRL_ARC_PAD__SHIFT                0x00000004
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG20__REG_A__SHIFT                       0x00000002
+#define MH_DEBUG_REG20__REG_RE__SHIFT                      0x00000010
+#define MH_DEBUG_REG20__REG_WE__SHIFT                      0x00000011
+#define MH_DEBUG_REG20__BLOCK_RS__SHIFT                    0x00000012
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__REG_WD__SHIFT                      0x00000000
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__CIB_MH_axi_halt_req__SHIFT         0x00000000
+#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack__SHIFT         0x00000001
+#define MH_DEBUG_REG22__MH_RBBM_busy__SHIFT                0x00000002
+#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int__SHIFT        0x00000003
+#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int__SHIFT       0x00000004
+#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int__SHIFT     0x00000005
+#define MH_DEBUG_REG22__GAT_CLK_ENA__SHIFT                 0x00000006
+#define MH_DEBUG_REG22__AXI_RDY_ENA__SHIFT                 0x00000007
+#define MH_DEBUG_REG22__RBBM_MH_clk_en_override__SHIFT     0x00000008
+#define MH_DEBUG_REG22__CNT_q__SHIFT                       0x00000009
+#define MH_DEBUG_REG22__TCD_EMPTY_q__SHIFT                 0x0000000f
+#define MH_DEBUG_REG22__TC_ROQ_EMPTY__SHIFT                0x00000010
+#define MH_DEBUG_REG22__MH_BUSY_d__SHIFT                   0x00000011
+#define MH_DEBUG_REG22__ANY_CLNT_BUSY__SHIFT               0x00000012
+#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000013
+#define MH_DEBUG_REG22__CP_SEND_q__SHIFT                   0x00000014
+#define MH_DEBUG_REG22__CP_RTR_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG22__VGT_SEND_q__SHIFT                  0x00000016
+#define MH_DEBUG_REG22__VGT_RTR_q__SHIFT                   0x00000017
+#define MH_DEBUG_REG22__TC_ROQ_SEND_q__SHIFT               0x00000018
+#define MH_DEBUG_REG22__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG22__RB_SEND_q__SHIFT                   0x0000001a
+#define MH_DEBUG_REG22__RB_RTR_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG22__RDC_VALID__SHIFT                   0x0000001c
+#define MH_DEBUG_REG22__RDC_RLAST__SHIFT                   0x0000001d
+#define MH_DEBUG_REG22__TLBMISS_VALID__SHIFT               0x0000001e
+#define MH_DEBUG_REG22__BRC_VALID__SHIFT                   0x0000001f
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__EFF2_FP_WINNER__SHIFT              0x00000000
+#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out__SHIFT         0x00000003
+#define MH_DEBUG_REG23__EFF1_WINNER__SHIFT                 0x00000006
+#define MH_DEBUG_REG23__ARB_WINNER__SHIFT                  0x00000009
+#define MH_DEBUG_REG23__ARB_WINNER_q__SHIFT                0x0000000c
+#define MH_DEBUG_REG23__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG23__KILL_EFF1__SHIFT                   0x00000010
+#define MH_DEBUG_REG23__ARB_HOLD__SHIFT                    0x00000011
+#define MH_DEBUG_REG23__ARB_RTR_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG23__CP_SEND_QUAL__SHIFT                0x00000013
+#define MH_DEBUG_REG23__VGT_SEND_QUAL__SHIFT               0x00000014
+#define MH_DEBUG_REG23__TC_SEND_QUAL__SHIFT                0x00000015
+#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL__SHIFT           0x00000016
+#define MH_DEBUG_REG23__RB_SEND_QUAL__SHIFT                0x00000017
+#define MH_DEBUG_REG23__ARB_QUAL__SHIFT                    0x00000018
+#define MH_DEBUG_REG23__CP_EFF1_REQ__SHIFT                 0x00000019
+#define MH_DEBUG_REG23__VGT_EFF1_REQ__SHIFT                0x0000001a
+#define MH_DEBUG_REG23__TC_EFF1_REQ__SHIFT                 0x0000001b
+#define MH_DEBUG_REG23__RB_EFF1_REQ__SHIFT                 0x0000001c
+#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK__SHIFT           0x0000001d
+#define MH_DEBUG_REG23__TCD_NEARFULL_q__SHIFT              0x0000001e
+#define MH_DEBUG_REG23__TCHOLD_IP_q__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__EFF1_WINNER__SHIFT                 0x00000000
+#define MH_DEBUG_REG24__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG24__CP_SEND_QUAL__SHIFT                0x00000006
+#define MH_DEBUG_REG24__VGT_SEND_QUAL__SHIFT               0x00000007
+#define MH_DEBUG_REG24__TC_SEND_QUAL__SHIFT                0x00000008
+#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL__SHIFT           0x00000009
+#define MH_DEBUG_REG24__RB_SEND_QUAL__SHIFT                0x0000000a
+#define MH_DEBUG_REG24__ARB_QUAL__SHIFT                    0x0000000b
+#define MH_DEBUG_REG24__CP_EFF1_REQ__SHIFT                 0x0000000c
+#define MH_DEBUG_REG24__VGT_EFF1_REQ__SHIFT                0x0000000d
+#define MH_DEBUG_REG24__TC_EFF1_REQ__SHIFT                 0x0000000e
+#define MH_DEBUG_REG24__RB_EFF1_REQ__SHIFT                 0x0000000f
+#define MH_DEBUG_REG24__EFF1_WIN__SHIFT                    0x00000010
+#define MH_DEBUG_REG24__KILL_EFF1__SHIFT                   0x00000011
+#define MH_DEBUG_REG24__TCD_NEARFULL_q__SHIFT              0x00000012
+#define MH_DEBUG_REG24__TC_ARB_HOLD__SHIFT                 0x00000013
+#define MH_DEBUG_REG24__ARB_HOLD__SHIFT                    0x00000014
+#define MH_DEBUG_REG24__ARB_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q__SHIFT     0x00000016
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out__SHIFT         0x00000000
+#define MH_DEBUG_REG25__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d__SHIFT        0x00000006
+#define MH_DEBUG_REG25__LEAST_RECENT_d__SHIFT              0x00000009
+#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d__SHIFT       0x0000000c
+#define MH_DEBUG_REG25__ARB_HOLD__SHIFT                    0x0000000d
+#define MH_DEBUG_REG25__ARB_RTR_q__SHIFT                   0x0000000e
+#define MH_DEBUG_REG25__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG25__CLNT_REQ__SHIFT                    0x00000010
+#define MH_DEBUG_REG25__RECENT_d_0__SHIFT                  0x00000014
+#define MH_DEBUG_REG25__RECENT_d_1__SHIFT                  0x00000017
+#define MH_DEBUG_REG25__RECENT_d_2__SHIFT                  0x0000001a
+#define MH_DEBUG_REG25__RECENT_d_3__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__TC_ARB_HOLD__SHIFT                 0x00000000
+#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK__SHIFT      0x00000001
+#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK__SHIFT        0x00000002
+#define MH_DEBUG_REG26__TCD_NEARFULL_q__SHIFT              0x00000003
+#define MH_DEBUG_REG26__TCHOLD_IP_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG26__TCHOLD_CNT_q__SHIFT                0x00000005
+#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT            0x00000009
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT               0x0000000a
+#define MH_DEBUG_REG26__TC_MH_written__SHIFT               0x0000000b
+#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q__SHIFT          0x0000000c
+#define MH_DEBUG_REG26__WBURST_ACTIVE__SHIFT               0x00000013
+#define MH_DEBUG_REG26__WLAST_q__SHIFT                     0x00000014
+#define MH_DEBUG_REG26__WBURST_IP_q__SHIFT                 0x00000015
+#define MH_DEBUG_REG26__WBURST_CNT_q__SHIFT                0x00000016
+#define MH_DEBUG_REG26__CP_SEND_QUAL__SHIFT                0x00000019
+#define MH_DEBUG_REG26__CP_MH_write__SHIFT                 0x0000001a
+#define MH_DEBUG_REG26__RB_SEND_QUAL__SHIFT                0x0000001b
+#define MH_DEBUG_REG26__ARB_WINNER__SHIFT                  0x0000001c
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q__SHIFT         0x00000000
+#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG28__ROQ_MARK_q__SHIFT                  0x00000008
+#define MH_DEBUG_REG28__ROQ_VALID_q__SHIFT                 0x00000010
+#define MH_DEBUG_REG28__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG28__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG28__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG28__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG28__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG28__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG29__ROQ_MARK_d__SHIFT                  0x00000008
+#define MH_DEBUG_REG29__ROQ_VALID_d__SHIFT                 0x00000010
+#define MH_DEBUG_REG29__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG29__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG29__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG29__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG29__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG29__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN__SHIFT           0x00000000
+#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ__SHIFT           0x00000008
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN__SHIFT       0x00000010
+#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ__SHIFT       0x00000018
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG31__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG31__ROQ_MARK_q_0__SHIFT                0x00000002
+#define MH_DEBUG_REG31__ROQ_VALID_q_0__SHIFT               0x00000003
+#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0__SHIFT           0x00000004
+#define MH_DEBUG_REG31__ROQ_ADDR_0__SHIFT                  0x00000005
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG32__ROQ_MARK_q_1__SHIFT                0x00000002
+#define MH_DEBUG_REG32__ROQ_VALID_q_1__SHIFT               0x00000003
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1__SHIFT           0x00000004
+#define MH_DEBUG_REG32__ROQ_ADDR_1__SHIFT                  0x00000005
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG33__ROQ_MARK_q_2__SHIFT                0x00000002
+#define MH_DEBUG_REG33__ROQ_VALID_q_2__SHIFT               0x00000003
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2__SHIFT           0x00000004
+#define MH_DEBUG_REG33__ROQ_ADDR_2__SHIFT                  0x00000005
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG34__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG34__ROQ_MARK_q_3__SHIFT                0x00000002
+#define MH_DEBUG_REG34__ROQ_VALID_q_3__SHIFT               0x00000003
+#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3__SHIFT           0x00000004
+#define MH_DEBUG_REG34__ROQ_ADDR_3__SHIFT                  0x00000005
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG35__ROQ_MARK_q_4__SHIFT                0x00000002
+#define MH_DEBUG_REG35__ROQ_VALID_q_4__SHIFT               0x00000003
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4__SHIFT           0x00000004
+#define MH_DEBUG_REG35__ROQ_ADDR_4__SHIFT                  0x00000005
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG36__ROQ_MARK_q_5__SHIFT                0x00000002
+#define MH_DEBUG_REG36__ROQ_VALID_q_5__SHIFT               0x00000003
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5__SHIFT           0x00000004
+#define MH_DEBUG_REG36__ROQ_ADDR_5__SHIFT                  0x00000005
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG37__ROQ_MARK_q_6__SHIFT                0x00000002
+#define MH_DEBUG_REG37__ROQ_VALID_q_6__SHIFT               0x00000003
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6__SHIFT           0x00000004
+#define MH_DEBUG_REG37__ROQ_ADDR_6__SHIFT                  0x00000005
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG38__ROQ_MARK_q_7__SHIFT                0x00000002
+#define MH_DEBUG_REG38__ROQ_VALID_q_7__SHIFT               0x00000003
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7__SHIFT           0x00000004
+#define MH_DEBUG_REG38__ROQ_ADDR_7__SHIFT                  0x00000005
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG39__MMU_RTR__SHIFT                     0x00000001
+#define MH_DEBUG_REG39__ARB_ID_q__SHIFT                    0x00000002
+#define MH_DEBUG_REG39__ARB_WRITE_q__SHIFT                 0x00000005
+#define MH_DEBUG_REG39__ARB_BLEN_q__SHIFT                  0x00000006
+#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY__SHIFT              0x00000007
+#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q__SHIFT              0x00000008
+#define MH_DEBUG_REG39__MMU_WE__SHIFT                      0x0000000b
+#define MH_DEBUG_REG39__ARQ_RTR__SHIFT                     0x0000000c
+#define MH_DEBUG_REG39__MMU_ID__SHIFT                      0x0000000d
+#define MH_DEBUG_REG39__MMU_WRITE__SHIFT                   0x00000010
+#define MH_DEBUG_REG39__MMU_BLEN__SHIFT                    0x00000011
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG40__ARB_ID_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG40__ARB_VAD_q__SHIFT                   0x00000004
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__MMU_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG41__MMU_ID__SHIFT                      0x00000001
+#define MH_DEBUG_REG41__MMU_PAD__SHIFT                     0x00000004
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__WDB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG42__WDB_RTR_SKID__SHIFT                0x00000001
+#define MH_DEBUG_REG42__ARB_WSTRB_q__SHIFT                 0x00000002
+#define MH_DEBUG_REG42__ARB_WLAST__SHIFT                   0x0000000a
+#define MH_DEBUG_REG42__WDB_CTRL_EMPTY__SHIFT              0x0000000b
+#define MH_DEBUG_REG42__WDB_FIFO_CNT_q__SHIFT              0x0000000c
+#define MH_DEBUG_REG42__WDC_WDB_RE_q__SHIFT                0x00000011
+#define MH_DEBUG_REG42__WDB_WDC_WID__SHIFT                 0x00000012
+#define MH_DEBUG_REG42__WDB_WDC_WLAST__SHIFT               0x00000015
+#define MH_DEBUG_REG42__WDB_WDC_WSTRB__SHIFT               0x00000016
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_WDATA_q_31_0__SHIFT            0x00000000
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WDATA_q_63_32__SHIFT           0x00000000
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0__SHIFT          0x00000000
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32__SHIFT         0x00000000
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__CTRL_ARC_EMPTY__SHIFT              0x00000000
+#define MH_DEBUG_REG47__CTRL_RARC_EMPTY__SHIFT             0x00000001
+#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY__SHIFT              0x00000002
+#define MH_DEBUG_REG47__ARQ_CTRL_WRITE__SHIFT              0x00000003
+#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS__SHIFT            0x00000004
+#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q__SHIFT           0x00000005
+#define MH_DEBUG_REG47__INFLT_LIMIT_q__SHIFT               0x00000006
+#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q__SHIFT           0x00000007
+#define MH_DEBUG_REG47__ARC_CTRL_RE_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG47__RARC_CTRL_RE_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG47__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG47__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG47__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG47__BVALID_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG47__BREADY_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG48__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG48__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG48__MH_TLBMISS_SEND__SHIFT             0x00000003
+#define MH_DEBUG_REG48__TLBMISS_VALID__SHIFT               0x00000004
+#define MH_DEBUG_REG48__RDC_VALID__SHIFT                   0x00000005
+#define MH_DEBUG_REG48__RDC_RID__SHIFT                     0x00000006
+#define MH_DEBUG_REG48__RDC_RLAST__SHIFT                   0x00000009
+#define MH_DEBUG_REG48__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS__SHIFT            0x0000000c
+#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q__SHIFT           0x0000000d
+#define MH_DEBUG_REG48__MMU_ID_REQUEST_q__SHIFT            0x0000000e
+#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q__SHIFT     0x0000000f
+#define MH_DEBUG_REG48__MMU_ID_RESPONSE__SHIFT             0x00000015
+#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q__SHIFT        0x00000016
+#define MH_DEBUG_REG48__CNT_HOLD_q1__SHIFT                 0x0000001c
+#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT__SHIFT           0x00000000
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__RF_MMU_CONFIG_q__SHIFT             0x00000000
+#define MH_DEBUG_REG50__ARB_ID_q__SHIFT                    0x00000018
+#define MH_DEBUG_REG50__ARB_WRITE_q__SHIFT                 0x0000001b
+#define MH_DEBUG_REG50__client_behavior_q__SHIFT           0x0000001c
+#define MH_DEBUG_REG50__ARB_WE__SHIFT                      0x0000001e
+#define MH_DEBUG_REG50__MMU_RTR__SHIFT                     0x0000001f
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__stage1_valid__SHIFT                0x00000000
+#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q__SHIFT           0x00000001
+#define MH_DEBUG_REG51__pa_in_mpu_range__SHIFT             0x00000002
+#define MH_DEBUG_REG51__tag_match_q__SHIFT                 0x00000003
+#define MH_DEBUG_REG51__tag_miss_q__SHIFT                  0x00000004
+#define MH_DEBUG_REG51__va_in_range_q__SHIFT               0x00000005
+#define MH_DEBUG_REG51__MMU_MISS__SHIFT                    0x00000006
+#define MH_DEBUG_REG51__MMU_READ_MISS__SHIFT               0x00000007
+#define MH_DEBUG_REG51__MMU_WRITE_MISS__SHIFT              0x00000008
+#define MH_DEBUG_REG51__MMU_HIT__SHIFT                     0x00000009
+#define MH_DEBUG_REG51__MMU_READ_HIT__SHIFT                0x0000000a
+#define MH_DEBUG_REG51__MMU_WRITE_HIT__SHIFT               0x0000000b
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS__SHIFT      0x0000000c
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT__SHIFT       0x0000000d
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS__SHIFT   0x0000000e
+#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT__SHIFT    0x0000000f
+#define MH_DEBUG_REG51__REQ_VA_OFFSET_q__SHIFT             0x00000010
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__ARQ_RTR__SHIFT                     0x00000000
+#define MH_DEBUG_REG52__MMU_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q__SHIFT           0x00000002
+#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS__SHIFT            0x00000003
+#define MH_DEBUG_REG52__MH_TLBMISS_SEND__SHIFT             0x00000004
+#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005
+#define MH_DEBUG_REG52__pa_in_mpu_range__SHIFT             0x00000006
+#define MH_DEBUG_REG52__stage1_valid__SHIFT                0x00000007
+#define MH_DEBUG_REG52__stage2_valid__SHIFT                0x00000008
+#define MH_DEBUG_REG52__client_behavior_q__SHIFT           0x00000009
+#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q__SHIFT           0x0000000b
+#define MH_DEBUG_REG52__tag_match_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG52__tag_miss_q__SHIFT                  0x0000000d
+#define MH_DEBUG_REG52__va_in_range_q__SHIFT               0x0000000e
+#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q__SHIFT        0x0000000f
+#define MH_DEBUG_REG52__TAG_valid_q__SHIFT                 0x00000010
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__TAG0_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG53__TAG_valid_q_0__SHIFT               0x0000000d
+#define MH_DEBUG_REG53__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG53__TAG1_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG53__TAG_valid_q_1__SHIFT               0x0000001d
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__TAG2_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG54__TAG_valid_q_2__SHIFT               0x0000000d
+#define MH_DEBUG_REG54__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG54__TAG3_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG54__TAG_valid_q_3__SHIFT               0x0000001d
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG4_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG55__TAG_valid_q_4__SHIFT               0x0000000d
+#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG55__TAG5_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG55__TAG_valid_q_5__SHIFT               0x0000001d
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG6_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG56__TAG_valid_q_6__SHIFT               0x0000000d
+#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG56__TAG7_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG56__TAG_valid_q_7__SHIFT               0x0000001d
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG8_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG57__TAG_valid_q_8__SHIFT               0x0000000d
+#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG57__TAG9_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG57__TAG_valid_q_9__SHIFT               0x0000001d
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG10_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG58__TAG_valid_q_10__SHIFT              0x0000000d
+#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG58__TAG11_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG58__TAG_valid_q_11__SHIFT              0x0000001d
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG12_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG59__TAG_valid_q_12__SHIFT              0x0000000d
+#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG59__TAG13_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG59__TAG_valid_q_13__SHIFT              0x0000001d
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG14_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG60__TAG_valid_q_14__SHIFT              0x0000000d
+#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG60__TAG15_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG60__TAG_valid_q_15__SHIFT              0x0000001d
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT                   0x00000000
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT            0x00000001
+#define MH_MMU_CONFIG__RESERVED1__SHIFT                    0x00000002
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT           0x00000004
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT           0x00000006
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT          0x00000008
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT          0x0000000a
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT          0x0000000c
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT          0x0000000e
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT          0x00000010
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT         0x00000012
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT         0x00000014
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT           0x00000016
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT           0x00000000
+#define MH_MMU_VA_RANGE__VA_BASE__SHIFT                    0x0000000c
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE__SHIFT                     0x0000000c
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT               0x00000000
+#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT                  0x00000001
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT            0x00000002
+#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT                   0x00000004
+#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT                0x00000007
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT     0x00000009
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT    0x0000000a
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT   0x0000000b
+#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT                   0x0000000c
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT               0x00000005
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT           0x00000000
+#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT            0x00000001
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT                   0x0000000c
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END__SHIFT                     0x0000000c
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT                   0x00000001
+#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT                   0x00000002
+#define WAIT_UNTIL__WAIT_VSYNC__SHIFT                      0x00000003
+#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT                  0x00000004
+#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT                  0x00000005
+#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT                  0x00000006
+#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT                    0x0000000a
+#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT                    0x0000000e
+#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT                    0x0000000f
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT               0x00000010
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT               0x00000011
+#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT                 0x00000014
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT         0x00000004
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT    0x00000005
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT                  0x00000000
+#define RBBM_STATUS__TC_BUSY__SHIFT                        0x00000005
+#define RBBM_STATUS__HIRQ_PENDING__SHIFT                   0x00000008
+#define RBBM_STATUS__CPRQ_PENDING__SHIFT                   0x00000009
+#define RBBM_STATUS__CFRQ_PENDING__SHIFT                   0x0000000a
+#define RBBM_STATUS__PFRQ_PENDING__SHIFT                   0x0000000b
+#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT                0x0000000c
+#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT                   0x0000000e
+#define RBBM_STATUS__CP_NRT_BUSY__SHIFT                    0x00000010
+#define RBBM_STATUS__MH_BUSY__SHIFT                        0x00000012
+#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT              0x00000013
+#define RBBM_STATUS__SX_BUSY__SHIFT                        0x00000015
+#define RBBM_STATUS__TPC_BUSY__SHIFT                       0x00000016
+#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT                   0x00000018
+#define RBBM_STATUS__PA_BUSY__SHIFT                        0x00000019
+#define RBBM_STATUS__VGT_BUSY__SHIFT                       0x0000001a
+#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT                 0x0000001b
+#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT                  0x0000001c
+#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT                   0x0000001e
+#define RBBM_STATUS__GUI_ACTIVE__SHIFT                     0x0000001f
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE__SHIFT              0x00000000
+#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE__SHIFT              0x00000001
+#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE__SHIFT              0x00000002
+#define RBBM_DSPLY__VSYNC_ACTIVE__SHIFT                    0x00000003
+#define RBBM_DSPLY__USE_DISPLAY_ID0__SHIFT                 0x00000004
+#define RBBM_DSPLY__USE_DISPLAY_ID1__SHIFT                 0x00000005
+#define RBBM_DSPLY__USE_DISPLAY_ID2__SHIFT                 0x00000006
+#define RBBM_DSPLY__SW_CNTL__SHIFT                         0x00000007
+#define RBBM_DSPLY__NUM_BUFS__SHIFT                        0x00000008
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__BUFFER_ID__SHIFT               0x00000000
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT                0x00000000
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT          0x00000000
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT         0x00000010
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT             0x00000018
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT             0x00000000
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT                 0x00000000
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT                 0x00000000
+#define RBBM_PERIPHID1__DESIGNER0__SHIFT                   0x00000004
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1__SHIFT                   0x00000000
+#define RBBM_PERIPHID2__REVISION__SHIFT                    0x00000004
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT         0x00000000
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT        0x00000002
+#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT                0x00000004
+#define RBBM_PERIPHID3__CONTINUATION__SHIFT                0x00000007
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT__SHIFT                     0x00000000
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT             0x00000008
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT          0x00000000
+#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT                  0x00000005
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT              0x00000000
+#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT              0x00000002
+#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT              0x00000003
+#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT              0x00000004
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT              0x00000005
+#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT              0x00000006
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT             0x0000000c
+#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT              0x0000000f
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT             0x00000010
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000001
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT      0x00000002
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT  0x00000003
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT   0x00000004
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000005
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT   0x00000008
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT      0x00000009
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT   0x00000014
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000015
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT    0x00000016
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000017
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT     0x00000019
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001a
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT      0x0000001b
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT   0x0000001c
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001d
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT  0x0000001e
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT   0x00000001
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT   0x00000002
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT    0x00000007
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT  0x00000008
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT  0x00000009
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT  0x0000000b
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT              0x00000000
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT           0x0000001f
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT                 0x00000000
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR__SHIFT                      0x00000001
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT              0x00000002
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT           0x00000003
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT           0x00000004
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT       0x00000008
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT               0x00000010
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000011
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT   0x00000012
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000013
+#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT                  0x00000014
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT                 0x00000015
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT                  0x00000016
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT      0x00000017
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT             0x00000018
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT             0x0000001f
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT               0x00000002
+#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT             0x0000001e
+#define RBBM_READ_ERROR__READ_ERROR__SHIFT                 0x0000001f
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT               0x00000000
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT      0x00000001
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT            0x00000013
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT             0x00000000
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT    0x00000001
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT          0x00000013
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT                 0x00000000
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT        0x00000001
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT              0x00000013
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT              0x00000005
+#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT              0x0000001e
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT            0x0000001f
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT   0x00000000
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT        0x00000000
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT        0x00000000
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT                         0x00000005
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT                        0x00000000
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT                        0x00000008
+#define CP_RB_CNTL__BUF_SWAP__SHIFT                        0x00000010
+#define CP_RB_CNTL__RB_POLL_EN__SHIFT                      0x00000014
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                    0x0000001b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                  0x0000001f
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT               0x00000002
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT                         0x00000000
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                   0x00000000
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT                         0x00000000
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT           0x00000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT           0x0000001c
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT               0x00000002
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE__SHIFT                       0x00000002
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                     0x00000000
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE__SHIFT                       0x00000002
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                     0x00000000
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE__SHIFT                         0x00000002
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                       0x00000000
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT          0x00000000
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT          0x00000008
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT           0x00000010
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT                  0x00000010
+#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT                  0x00000018
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT                  0x00000000
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT                   0x00000008
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT                   0x00000010
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT                    0x00000000
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                       0x00000000
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT            0x00000000
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT            0x00000010
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT         0x00000000
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT         0x00000010
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT         0x00000000
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT         0x00000010
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT          0x00000000
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT          0x00000008
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT                 0x00000000
+#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT                 0x00000010
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                       0x00000000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                       0x00000010
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT                 0x00000000
+#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT                 0x00000001
+#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT                 0x00000002
+#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT                 0x00000003
+#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT                 0x00000004
+#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT                 0x00000005
+#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT                 0x00000006
+#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT                 0x00000007
+#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT                 0x00000008
+#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT                 0x00000009
+#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT                0x0000000a
+#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT                0x0000000b
+#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT                0x0000000c
+#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT                0x0000000d
+#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT                0x0000000e
+#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT                0x0000000f
+#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT                0x00000010
+#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT                0x00000011
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT         0x0000001f
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT                     0x00000000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                 0x00000010
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT                       0x00000000
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX__SHIFT                      0x00000000
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT          0x00000019
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT          0x0000001a
+#define CP_ME_CNTL__ME_HALT__SHIFT                         0x0000001c
+#define CP_ME_CNTL__ME_BUSY__SHIFT                         0x0000001d
+#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT                   0x0000001f
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT                 0x00000000
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                 0x00000000
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR__SHIFT                     0x00000000
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT           0x00000000
+#define CP_DEBUG__PREDICATE_DISABLE__SHIFT                 0x00000017
+#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT               0x00000018
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT           0x00000019
+#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT                0x0000001a
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT               0x0000001b
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT            0x0000001c
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT            0x0000001e
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT            0x0000001f
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT              0x00000000
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT              0x00000000
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT              0x00000000
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT              0x00000000
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT              0x00000000
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT              0x00000000
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT              0x00000000
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT              0x00000000
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT                  0x00000000
+#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT                  0x00000010
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT                  0x00000005
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT             0x00000000
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT              0x00000000
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT              0x00000002
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT              0x00000000
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK__SHIFT                    0x00000013
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT           0x00000017
+#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT              0x00000018
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT      0x00000019
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT        0x0000001a
+#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT                  0x0000001b
+#define CP_INT_CNTL__IB2_INT_MASK__SHIFT                   0x0000001d
+#define CP_INT_CNTL__IB1_INT_MASK__SHIFT                   0x0000001e
+#define CP_INT_CNTL__RB_INT_MASK__SHIFT                    0x0000001f
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT__SHIFT                  0x00000013
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT         0x00000017
+#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT            0x00000018
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT    0x00000019
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT      0x0000001a
+#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT                0x0000001b
+#define CP_INT_STATUS__IB2_INT_STAT__SHIFT                 0x0000001d
+#define CP_INT_STATUS__IB1_INT_STAT__SHIFT                 0x0000001e
+#define CP_INT_STATUS__RB_INT_STAT__SHIFT                  0x0000001f
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK__SHIFT                      0x00000013
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT             0x00000017
+#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT                0x00000018
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT        0x00000019
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT          0x0000001a
+#define CP_INT_ACK__IB_ERROR_ACK__SHIFT                    0x0000001b
+#define CP_INT_ACK__IB2_INT_ACK__SHIFT                     0x0000001d
+#define CP_INT_ACK__IB1_INT_ACK__SHIFT                     0x0000001e
+#define CP_INT_ACK__RB_INT_ACK__SHIFT                      0x0000001f
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT               0x00000000
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT               0x00000000
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT              0x00000000
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT        0x00000008
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT        0x00000000
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT             0x00000000
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT             0x00000000
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT                 0x00000000
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT                 0x00000000
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT             0x00000000
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT             0x00000000
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0__SHIFT                    0x00000000
+#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT                   0x00000001
+#define CP_NV_FLAGS_0__DISCARD_1__SHIFT                    0x00000002
+#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT                   0x00000003
+#define CP_NV_FLAGS_0__DISCARD_2__SHIFT                    0x00000004
+#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT                   0x00000005
+#define CP_NV_FLAGS_0__DISCARD_3__SHIFT                    0x00000006
+#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT                   0x00000007
+#define CP_NV_FLAGS_0__DISCARD_4__SHIFT                    0x00000008
+#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT                   0x00000009
+#define CP_NV_FLAGS_0__DISCARD_5__SHIFT                    0x0000000a
+#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT                   0x0000000b
+#define CP_NV_FLAGS_0__DISCARD_6__SHIFT                    0x0000000c
+#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT                   0x0000000d
+#define CP_NV_FLAGS_0__DISCARD_7__SHIFT                    0x0000000e
+#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT                   0x0000000f
+#define CP_NV_FLAGS_0__DISCARD_8__SHIFT                    0x00000010
+#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT                   0x00000011
+#define CP_NV_FLAGS_0__DISCARD_9__SHIFT                    0x00000012
+#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT                   0x00000013
+#define CP_NV_FLAGS_0__DISCARD_10__SHIFT                   0x00000014
+#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT                  0x00000015
+#define CP_NV_FLAGS_0__DISCARD_11__SHIFT                   0x00000016
+#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT                  0x00000017
+#define CP_NV_FLAGS_0__DISCARD_12__SHIFT                   0x00000018
+#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT                  0x00000019
+#define CP_NV_FLAGS_0__DISCARD_13__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_0__DISCARD_14__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_0__DISCARD_15__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16__SHIFT                   0x00000000
+#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT                  0x00000001
+#define CP_NV_FLAGS_1__DISCARD_17__SHIFT                   0x00000002
+#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT                  0x00000003
+#define CP_NV_FLAGS_1__DISCARD_18__SHIFT                   0x00000004
+#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT                  0x00000005
+#define CP_NV_FLAGS_1__DISCARD_19__SHIFT                   0x00000006
+#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT                  0x00000007
+#define CP_NV_FLAGS_1__DISCARD_20__SHIFT                   0x00000008
+#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT                  0x00000009
+#define CP_NV_FLAGS_1__DISCARD_21__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_1__DISCARD_22__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_1__DISCARD_23__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_1__DISCARD_24__SHIFT                   0x00000010
+#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT                  0x00000011
+#define CP_NV_FLAGS_1__DISCARD_25__SHIFT                   0x00000012
+#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT                  0x00000013
+#define CP_NV_FLAGS_1__DISCARD_26__SHIFT                   0x00000014
+#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT                  0x00000015
+#define CP_NV_FLAGS_1__DISCARD_27__SHIFT                   0x00000016
+#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT                  0x00000017
+#define CP_NV_FLAGS_1__DISCARD_28__SHIFT                   0x00000018
+#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT                  0x00000019
+#define CP_NV_FLAGS_1__DISCARD_29__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_1__DISCARD_30__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_1__DISCARD_31__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32__SHIFT                   0x00000000
+#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT                  0x00000001
+#define CP_NV_FLAGS_2__DISCARD_33__SHIFT                   0x00000002
+#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT                  0x00000003
+#define CP_NV_FLAGS_2__DISCARD_34__SHIFT                   0x00000004
+#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT                  0x00000005
+#define CP_NV_FLAGS_2__DISCARD_35__SHIFT                   0x00000006
+#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT                  0x00000007
+#define CP_NV_FLAGS_2__DISCARD_36__SHIFT                   0x00000008
+#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT                  0x00000009
+#define CP_NV_FLAGS_2__DISCARD_37__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_2__DISCARD_38__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_2__DISCARD_39__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_2__DISCARD_40__SHIFT                   0x00000010
+#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT                  0x00000011
+#define CP_NV_FLAGS_2__DISCARD_41__SHIFT                   0x00000012
+#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT                  0x00000013
+#define CP_NV_FLAGS_2__DISCARD_42__SHIFT                   0x00000014
+#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT                  0x00000015
+#define CP_NV_FLAGS_2__DISCARD_43__SHIFT                   0x00000016
+#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT                  0x00000017
+#define CP_NV_FLAGS_2__DISCARD_44__SHIFT                   0x00000018
+#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT                  0x00000019
+#define CP_NV_FLAGS_2__DISCARD_45__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_2__DISCARD_46__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_2__DISCARD_47__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48__SHIFT                   0x00000000
+#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT                  0x00000001
+#define CP_NV_FLAGS_3__DISCARD_49__SHIFT                   0x00000002
+#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT                  0x00000003
+#define CP_NV_FLAGS_3__DISCARD_50__SHIFT                   0x00000004
+#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT                  0x00000005
+#define CP_NV_FLAGS_3__DISCARD_51__SHIFT                   0x00000006
+#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT                  0x00000007
+#define CP_NV_FLAGS_3__DISCARD_52__SHIFT                   0x00000008
+#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT                  0x00000009
+#define CP_NV_FLAGS_3__DISCARD_53__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_3__DISCARD_54__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_3__DISCARD_55__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_3__DISCARD_56__SHIFT                   0x00000010
+#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT                  0x00000011
+#define CP_NV_FLAGS_3__DISCARD_57__SHIFT                   0x00000012
+#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT                  0x00000013
+#define CP_NV_FLAGS_3__DISCARD_58__SHIFT                   0x00000014
+#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT                  0x00000015
+#define CP_NV_FLAGS_3__DISCARD_59__SHIFT                   0x00000016
+#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT                  0x00000017
+#define CP_NV_FLAGS_3__DISCARD_60__SHIFT                   0x00000018
+#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT                  0x00000019
+#define CP_NV_FLAGS_3__DISCARD_61__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_3__DISCARD_62__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_3__DISCARD_63__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT                  0x0000001f
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT     0x00000000
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT       0x00000000
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER__SHIFT                    0x00000000
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY__SHIFT                        0x00000000
+#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT                    0x00000001
+#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT                 0x00000002
+#define CP_STAT__RBIU_BUSY__SHIFT                          0x00000003
+#define CP_STAT__RCIU_BUSY__SHIFT                          0x00000004
+#define CP_STAT__CSF_RING_BUSY__SHIFT                      0x00000005
+#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT                 0x00000006
+#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT                 0x00000007
+#define CP_STAT__CSF_ST_BUSY__SHIFT                        0x00000009
+#define CP_STAT__CSF_BUSY__SHIFT                           0x0000000a
+#define CP_STAT__RING_QUEUE_BUSY__SHIFT                    0x0000000b
+#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT               0x0000000c
+#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT               0x0000000d
+#define CP_STAT__ST_QUEUE_BUSY__SHIFT                      0x00000010
+#define CP_STAT__PFP_BUSY__SHIFT                           0x00000011
+#define CP_STAT__MEQ_RING_BUSY__SHIFT                      0x00000012
+#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT                 0x00000013
+#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT                 0x00000014
+#define CP_STAT__MIU_WC_STALL__SHIFT                       0x00000015
+#define CP_STAT__CP_NRT_BUSY__SHIFT                        0x00000016
+#define CP_STAT___3D_BUSY__SHIFT                           0x00000017
+#define CP_STAT__ME_BUSY__SHIFT                            0x0000001a
+#define CP_STAT__ME_WC_BUSY__SHIFT                         0x0000001d
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT            0x0000001e
+#define CP_STAT__CP_BUSY__SHIFT                            0x0000001f
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE__SHIFT                        0x00000000
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE__SHIFT                        0x00000000
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT         0x00000000
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT     0x00000008
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT           0x00000009
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT           0x0000000a
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT           0x0000000b
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT           0x0000000c
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT           0x0000000d
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT           0x0000000e
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT           0x0000000f
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT           0x00000010
+#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT             0x00000019
+#define COHER_STATUS_PM4__STATUS__SHIFT                    0x0000001f
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE__SHIFT                       0x00000000
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE__SHIFT                       0x00000000
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT        0x00000000
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT    0x00000008
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT          0x00000009
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT          0x0000000a
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT          0x0000000b
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT          0x0000000c
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT          0x0000000d
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT          0x0000000e
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT          0x0000000f
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT          0x00000010
+#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT            0x00000019
+#define COHER_STATUS_HOST__STATUS__SHIFT                   0x0000001f
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT              0x0000000c
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT              0x00000000
+#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT               0x0000000e
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT                 0x00000000
+#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT             0x00000004
+#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT                 0x00000006
+#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT                 0x00000007
+#define RB_COLOR_INFO__COLOR_SWAP__SHIFT                   0x00000009
+#define RB_COLOR_INFO__COLOR_BASE__SHIFT                   0x0000000c
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT                 0x00000000
+#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT                   0x0000000c
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF__SHIFT               0x00000000
+#define RB_STENCILREFMASK__STENCILMASK__SHIFT              0x00000008
+#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT         0x00000010
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF__SHIFT                     0x00000000
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED__SHIFT                    0x00000000
+#define RB_COLOR_MASK__WRITE_GREEN__SHIFT                  0x00000001
+#define RB_COLOR_MASK__WRITE_BLUE__SHIFT                   0x00000002
+#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT                  0x00000003
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED__SHIFT                     0x00000000
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT                 0x00000000
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT                   0x00000000
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                 0x00000000
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED__SHIFT                       0x00000000
+#define RB_FOG_COLOR__FOG_GREEN__SHIFT                     0x00000008
+#define RB_FOG_COLOR__FOG_BLUE__SHIFT                      0x00000010
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT         0x00000000
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT        0x00000008
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT   0x00000010
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT             0x00000000
+#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT                   0x00000001
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT             0x00000002
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT             0x00000003
+#define RB_DEPTHCONTROL__ZFUNC__SHIFT                      0x00000004
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT            0x00000007
+#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT                0x00000008
+#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT                0x0000000b
+#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT               0x0000000e
+#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT               0x00000011
+#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT             0x00000014
+#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT             0x00000017
+#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT            0x0000001a
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT            0x0000001d
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT             0x00000000
+#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT             0x00000005
+#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT            0x00000008
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT             0x00000010
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT             0x00000015
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT            0x00000018
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT         0x0000001d
+#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT                0x0000001e
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT                 0x00000000
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT          0x00000003
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT       0x00000004
+#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT              0x00000005
+#define RB_COLORCONTROL__FOG_ENABLE__SHIFT                 0x00000006
+#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT             0x00000007
+#define RB_COLORCONTROL__ROP_CODE__SHIFT                   0x00000008
+#define RB_COLORCONTROL__DITHER_MODE__SHIFT                0x0000000c
+#define RB_COLORCONTROL__DITHER_TYPE__SHIFT                0x0000000e
+#define RB_COLORCONTROL__PIXEL_FOG__SHIFT                  0x00000010
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT      0x00000018
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT      0x0000001a
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT      0x0000001c
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT      0x0000001e
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE__SHIFT                  0x00000000
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT         0x00000000
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT         0x00000000
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT         0x00000003
+#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT                 0x00000004
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT           0x0000000c
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT         0x00000000
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT         0x00000000
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT         0x00000003
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT         0x00000004
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT           0x00000008
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT    0x0000000a
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT    0x0000000c
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT      0x0000000e
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT    0x0000000f
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT     0x00000010
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT    0x00000011
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT         0x00000000
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT         0x0000000d
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                 0x00000000
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT     0x00000000
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT      0x00000001
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT     0x00000000
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT     0x00000000
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT         0x00000001
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT            0x00000003
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT    0x00000005
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT    0x00000006
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT           0x00000007
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT            0x00000008
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT            0x0000000e
+#define RB_BC_CONTROL__CRC_MODE__SHIFT                     0x0000000f
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT      0x00000010
+#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT                0x00000011
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT             0x00000012
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT    0x00000016
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT        0x00000017
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT    0x0000001b
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d
+#define RB_BC_CONTROL__RESERVED9__SHIFT                    0x0000001e
+#define RB_BC_CONTROL__RESERVED10__SHIFT                   0x0000001f
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT                   0x00000000
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT           0x00000004
+#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT                  0x0000000e
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA__SHIFT                    0x00000000
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT              0x00000000
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK__SHIFT                       0x00000000
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT             0x00000000
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT             0x00000000
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT           0x00000000
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT           0x00000001
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT           0x00000002
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT           0x00000003
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT          0x00000004
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT          0x00000005
+#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT                   0x00000006
+#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT                   0x00000007
+#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT                   0x00000008
+#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT                   0x00000009
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT          0x0000000a
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT          0x0000000b
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT          0x0000000c
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT          0x0000000d
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT              0x0000000e
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT                   0x00000010
+#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT                   0x00000011
+#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT                   0x00000012
+#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT                   0x00000013
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT            0x00000014
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT            0x00000015
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT            0x00000016
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT            0x00000017
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT         0x00000018
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT         0x00000019
+#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT                   0x0000001a
+#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT                   0x0000001b
+#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT                  0x0000001c
+#define RB_DEBUG_0__C_REQ_FULL__SHIFT                      0x0000001d
+#define RB_DEBUG_0__C_MASK_FULL__SHIFT                     0x0000001e
+#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT                 0x0000001f
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT              0x00000000
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT              0x00000001
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT              0x00000002
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT              0x00000003
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT         0x00000004
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT         0x00000005
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT                  0x00000006
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT                  0x00000007
+#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT                  0x00000008
+#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT                  0x00000009
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT         0x0000000a
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT         0x0000000b
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT         0x0000000c
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT         0x0000000d
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT             0x0000000e
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT             0x0000000f
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT                  0x00000010
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT                  0x00000011
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT              0x00000012
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT              0x00000013
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT           0x00000014
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT           0x00000017
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT        0x00000018
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT        0x00000019
+#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT                  0x0000001a
+#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT                  0x0000001b
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT                 0x0000001c
+#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT                     0x0000001d
+#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT                0x0000001f
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT                 0x00000000
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT               0x00000004
+#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT                 0x0000000b
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT               0x0000000c
+#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT              0x0000000d
+#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT                 0x0000000e
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT              0x00000010
+#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT                    0x00000011
+#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT                    0x00000012
+#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT                     0x00000013
+#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT                     0x00000014
+#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT                     0x00000015
+#define RB_DEBUG_2__Z_TILE_FULL__SHIFT                     0x00000016
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT                0x00000017
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT             0x00000018
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT             0x00000019
+#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT                   0x0000001a
+#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT                   0x0000001b
+#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT                    0x0000001c
+#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT                    0x0000001d
+#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT                    0x0000001f
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID__SHIFT                     0x00000000
+#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT                  0x00000004
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT         0x00000008
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT           0x0000000e
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT             0x0000000f
+#define RB_DEBUG_3__SHD_FULL__SHIFT                        0x00000013
+#define RB_DEBUG_3__SHD_EMPTY__SHIFT                       0x00000014
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT            0x00000017
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT            0x00000018
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT                0x00000019
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT                0x0000001a
+#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT                 0x0000001b
+#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT                 0x0000001c
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT             0x00000000
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT             0x00000001
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT           0x00000002
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT           0x00000003
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT           0x00000004
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT          0x00000005
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT            0x00000006
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT           0x00000007
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT     0x00000008
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT             0x00000009
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT           0x00000000
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT   0x00000009
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h
new file mode 100644
index 00000000000..e8402cda446
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h
@@ -0,0 +1,51151 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_CP_FIDDLE_H)
+#define _CP_FIDDLE_H
+
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * CP_RB_BASE struct
+ */
+
+#define CP_RB_BASE_RB_BASE_SIZE        27
+
+#define CP_RB_BASE_RB_BASE_SHIFT       5
+
+#define CP_RB_BASE_RB_BASE_MASK        0xffffffe0
+
+#define CP_RB_BASE_MASK \
+     (CP_RB_BASE_RB_BASE_MASK)
+
+#define CP_RB_BASE(rb_base) \
+     ((rb_base << CP_RB_BASE_RB_BASE_SHIFT))
+
+#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \
+     ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT)
+
+#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \
+     cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int                                : 5;
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+     } cp_rb_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+          unsigned int                                : 5;
+     } cp_rb_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+
+/*
+ * CP_RB_CNTL struct
+ */
+
+#define CP_RB_CNTL_RB_BUFSZ_SIZE       6
+#define CP_RB_CNTL_RB_BLKSZ_SIZE       6
+#define CP_RB_CNTL_BUF_SWAP_SIZE       2
+#define CP_RB_CNTL_RB_POLL_EN_SIZE     1
+#define CP_RB_CNTL_RB_NO_UPDATE_SIZE   1
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
+
+#define CP_RB_CNTL_RB_BUFSZ_SHIFT      0
+#define CP_RB_CNTL_RB_BLKSZ_SHIFT      8
+#define CP_RB_CNTL_BUF_SWAP_SHIFT      16
+#define CP_RB_CNTL_RB_POLL_EN_SHIFT    20
+#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT  27
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31
+
+#define CP_RB_CNTL_RB_BUFSZ_MASK       0x0000003f
+#define CP_RB_CNTL_RB_BLKSZ_MASK       0x00003f00
+#define CP_RB_CNTL_BUF_SWAP_MASK       0x00030000
+#define CP_RB_CNTL_RB_POLL_EN_MASK     0x00100000
+#define CP_RB_CNTL_RB_NO_UPDATE_MASK   0x08000000
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000
+
+#define CP_RB_CNTL_MASK \
+     (CP_RB_CNTL_RB_BUFSZ_MASK | \
+      CP_RB_CNTL_RB_BLKSZ_MASK | \
+      CP_RB_CNTL_BUF_SWAP_MASK | \
+      CP_RB_CNTL_RB_POLL_EN_MASK | \
+      CP_RB_CNTL_RB_NO_UPDATE_MASK | \
+      CP_RB_CNTL_RB_RPTR_WR_ENA_MASK)
+
+#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \
+     ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \
+      (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \
+      (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \
+      (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \
+      (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \
+      (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT))
+
+#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+     } cp_rb_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+     } cp_rb_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+
+/*
+ * CP_RB_RPTR_ADDR struct
+ */
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc
+
+#define CP_RB_RPTR_ADDR_MASK \
+     (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \
+      CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK)
+
+#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \
+     ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \
+      (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT))
+
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+
+/*
+ * CP_RB_RPTR struct
+ */
+
+#define CP_RB_RPTR_RB_RPTR_SIZE        20
+
+#define CP_RB_RPTR_RB_RPTR_SHIFT       0
+
+#define CP_RB_RPTR_RB_RPTR_MASK        0x000fffff
+
+#define CP_RB_RPTR_MASK \
+     (CP_RB_RPTR_RB_RPTR_MASK)
+
+#define CP_RB_RPTR(rb_rptr) \
+     ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT))
+
+#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \
+     ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \
+     cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+     } cp_rb_rptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+
+/*
+ * CP_RB_RPTR_WR struct
+ */
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE  20
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK  0x000fffff
+
+#define CP_RB_RPTR_WR_MASK \
+     (CP_RB_RPTR_WR_RB_RPTR_WR_MASK)
+
+#define CP_RB_RPTR_WR(rb_rptr_wr) \
+     ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT))
+
+#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \
+     ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \
+     cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_wr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+     } cp_rb_rptr_wr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+
+/*
+ * CP_RB_WPTR struct
+ */
+
+#define CP_RB_WPTR_RB_WPTR_SIZE        20
+
+#define CP_RB_WPTR_RB_WPTR_SHIFT       0
+
+#define CP_RB_WPTR_RB_WPTR_MASK        0x000fffff
+
+#define CP_RB_WPTR_MASK \
+     (CP_RB_WPTR_RB_WPTR_MASK)
+
+#define CP_RB_WPTR(rb_wptr) \
+     ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT))
+
+#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \
+     ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \
+     cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_wptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+     } cp_rb_wptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+
+/*
+ * CP_RB_WPTR_DELAY struct
+ */
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000
+
+#define CP_RB_WPTR_DELAY_MASK \
+     (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \
+      CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK)
+
+#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \
+     ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \
+      (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT))
+
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_delay_t f;
+} cp_rb_wptr_delay_u;
+
+
+/*
+ * CP_RB_WPTR_BASE struct
+ */
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc
+
+#define CP_RB_WPTR_BASE_MASK \
+     (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \
+      CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK)
+
+#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \
+     ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \
+      (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT))
+
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+     } cp_rb_wptr_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+     } cp_rb_wptr_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_base_t f;
+} cp_rb_wptr_base_u;
+
+
+/*
+ * CP_IB1_BASE struct
+ */
+
+#define CP_IB1_BASE_IB1_BASE_SIZE      30
+
+#define CP_IB1_BASE_IB1_BASE_SHIFT     2
+
+#define CP_IB1_BASE_IB1_BASE_MASK      0xfffffffc
+
+#define CP_IB1_BASE_MASK \
+     (CP_IB1_BASE_IB1_BASE_MASK)
+
+#define CP_IB1_BASE(ib1_base) \
+     ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT))
+
+#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \
+     ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \
+     cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int                                : 2;
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+     } cp_ib1_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib1_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_base_t f;
+} cp_ib1_base_u;
+
+
+/*
+ * CP_IB1_BUFSZ struct
+ */
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE    20
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT   0
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK    0x000fffff
+
+#define CP_IB1_BUFSZ_MASK \
+     (CP_IB1_BUFSZ_IB1_BUFSZ_MASK)
+
+#define CP_IB1_BUFSZ(ib1_bufsz) \
+     ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT))
+
+#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \
+     ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \
+     cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib1_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+     } cp_ib1_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_bufsz_t f;
+} cp_ib1_bufsz_u;
+
+
+/*
+ * CP_IB2_BASE struct
+ */
+
+#define CP_IB2_BASE_IB2_BASE_SIZE      30
+
+#define CP_IB2_BASE_IB2_BASE_SHIFT     2
+
+#define CP_IB2_BASE_IB2_BASE_MASK      0xfffffffc
+
+#define CP_IB2_BASE_MASK \
+     (CP_IB2_BASE_IB2_BASE_MASK)
+
+#define CP_IB2_BASE(ib2_base) \
+     ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT))
+
+#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \
+     ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \
+     cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int                                : 2;
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+     } cp_ib2_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib2_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_base_t f;
+} cp_ib2_base_u;
+
+
+/*
+ * CP_IB2_BUFSZ struct
+ */
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE    20
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT   0
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK    0x000fffff
+
+#define CP_IB2_BUFSZ_MASK \
+     (CP_IB2_BUFSZ_IB2_BUFSZ_MASK)
+
+#define CP_IB2_BUFSZ(ib2_bufsz) \
+     ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT))
+
+#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \
+     ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \
+     cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib2_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+     } cp_ib2_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_bufsz_t f;
+} cp_ib2_bufsz_u;
+
+
+/*
+ * CP_ST_BASE struct
+ */
+
+#define CP_ST_BASE_ST_BASE_SIZE        30
+
+#define CP_ST_BASE_ST_BASE_SHIFT       2
+
+#define CP_ST_BASE_ST_BASE_MASK        0xfffffffc
+
+#define CP_ST_BASE_MASK \
+     (CP_ST_BASE_ST_BASE_MASK)
+
+#define CP_ST_BASE(st_base) \
+     ((st_base << CP_ST_BASE_ST_BASE_SHIFT))
+
+#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \
+     ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT)
+
+#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \
+     cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int                                : 2;
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+     } cp_st_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_st_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_base_t f;
+} cp_st_base_u;
+
+
+/*
+ * CP_ST_BUFSZ struct
+ */
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SIZE      20
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT     0
+
+#define CP_ST_BUFSZ_ST_BUFSZ_MASK      0x000fffff
+
+#define CP_ST_BUFSZ_MASK \
+     (CP_ST_BUFSZ_ST_BUFSZ_MASK)
+
+#define CP_ST_BUFSZ(st_bufsz) \
+     ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT))
+
+#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \
+     ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \
+     cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_st_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+     } cp_st_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_bufsz_t f;
+} cp_st_bufsz_u;
+
+
+/*
+ * CP_QUEUE_THRESHOLDS struct
+ */
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000
+
+#define CP_QUEUE_THRESHOLDS_MASK \
+     (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK)
+
+#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \
+     ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \
+      (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \
+      (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT))
+
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 12;
+     } cp_queue_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int                                : 12;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+     } cp_queue_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_queue_thresholds_t f;
+} cp_queue_thresholds_u;
+
+
+/*
+ * CP_MEQ_THRESHOLDS struct
+ */
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5
+#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16
+#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000
+#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000
+
+#define CP_MEQ_THRESHOLDS_MASK \
+     (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \
+      CP_MEQ_THRESHOLDS_ROQ_END_MASK)
+
+#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \
+     ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \
+      (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT))
+
+#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 16;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+     } cp_meq_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 16;
+     } cp_meq_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_thresholds_t f;
+} cp_meq_thresholds_u;
+
+
+/*
+ * CP_CSQ_AVAIL struct
+ */
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE  7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE  7
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK  0x00007f00
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK  0x007f0000
+
+#define CP_CSQ_AVAIL_MASK \
+     (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK)
+
+#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \
+     ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \
+      (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \
+      (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT))
+
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int                                : 9;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+     } cp_csq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_avail_t f;
+} cp_csq_avail_u;
+
+
+/*
+ * CP_STQ_AVAIL struct
+ */
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE   7
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT  0
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_MASK   0x0000007f
+
+#define CP_STQ_AVAIL_MASK \
+     (CP_STQ_AVAIL_STQ_CNT_ST_MASK)
+
+#define CP_STQ_AVAIL(stq_cnt_st) \
+     ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT))
+
+#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \
+     ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \
+     cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+          unsigned int                                : 25;
+     } cp_stq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int                                : 25;
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+     } cp_stq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_avail_t f;
+} cp_stq_avail_u;
+
+
+/*
+ * CP_MEQ_AVAIL struct
+ */
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SIZE      5
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT     0
+
+#define CP_MEQ_AVAIL_MEQ_CNT_MASK      0x0000001f
+
+#define CP_MEQ_AVAIL_MASK \
+     (CP_MEQ_AVAIL_MEQ_CNT_MASK)
+
+#define CP_MEQ_AVAIL(meq_cnt) \
+     ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT))
+
+#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \
+     ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \
+     cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+          unsigned int                                : 27;
+     } cp_meq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int                                : 27;
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+     } cp_meq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_avail_t f;
+} cp_meq_avail_u;
+
+
+/*
+ * CP_CSQ_RB_STAT struct
+ */
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000
+
+#define CP_CSQ_RB_STAT_MASK \
+     (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \
+      CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK)
+
+#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \
+     ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \
+      (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT))
+
+#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_rb_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+     } cp_csq_rb_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_rb_stat_t f;
+} cp_csq_rb_stat_u;
+
+
+/*
+ * CP_CSQ_IB1_STAT struct
+ */
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000
+
+#define CP_CSQ_IB1_STAT_MASK \
+     (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \
+      CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK)
+
+#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \
+     ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \
+      (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT))
+
+#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib1_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+     } cp_csq_ib1_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib1_stat_t f;
+} cp_csq_ib1_stat_u;
+
+
+/*
+ * CP_CSQ_IB2_STAT struct
+ */
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000
+
+#define CP_CSQ_IB2_STAT_MASK \
+     (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \
+      CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK)
+
+#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \
+     ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \
+      (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT))
+
+#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib2_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+     } cp_csq_ib2_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib2_stat_t f;
+} cp_csq_ib2_stat_u;
+
+
+/*
+ * CP_NON_PREFETCH_CNTRS struct
+ */
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700
+
+#define CP_NON_PREFETCH_CNTRS_MASK \
+     (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \
+      CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK)
+
+#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \
+     ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \
+      (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT))
+
+#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 21;
+     } cp_non_prefetch_cntrs_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int                                : 21;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+     } cp_non_prefetch_cntrs_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_non_prefetch_cntrs_t f;
+} cp_non_prefetch_cntrs_u;
+
+
+/*
+ * CP_STQ_ST_STAT struct
+ */
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000
+
+#define CP_STQ_ST_STAT_MASK \
+     (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \
+      CP_STQ_ST_STAT_STQ_WPTR_ST_MASK)
+
+#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \
+     ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \
+      (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT))
+
+#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+     } cp_stq_st_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+     } cp_stq_st_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_st_stat_t f;
+} cp_stq_st_stat_u;
+
+
+/*
+ * CP_MEQ_STAT struct
+ */
+
+#define CP_MEQ_STAT_MEQ_RPTR_SIZE      10
+#define CP_MEQ_STAT_MEQ_WPTR_SIZE      10
+
+#define CP_MEQ_STAT_MEQ_RPTR_SHIFT     0
+#define CP_MEQ_STAT_MEQ_WPTR_SHIFT     16
+
+#define CP_MEQ_STAT_MEQ_RPTR_MASK      0x000003ff
+#define CP_MEQ_STAT_MEQ_WPTR_MASK      0x03ff0000
+
+#define CP_MEQ_STAT_MASK \
+     (CP_MEQ_STAT_MEQ_RPTR_MASK | \
+      CP_MEQ_STAT_MEQ_WPTR_MASK)
+
+#define CP_MEQ_STAT(meq_rptr, meq_wptr) \
+     ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \
+      (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT))
+
+#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+     } cp_meq_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+     } cp_meq_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_stat_t f;
+} cp_meq_stat_u;
+
+
+/*
+ * CP_MIU_TAG_STAT struct
+ */
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001
+#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002
+#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004
+#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008
+#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010
+#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020
+#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040
+#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080
+#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100
+#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200
+#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400
+#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800
+#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000
+#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000
+#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000
+#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000
+#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000
+#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000
+
+#define CP_MIU_TAG_STAT_MASK \
+     (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \
+      CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK)
+
+#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \
+     ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \
+      (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \
+      (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \
+      (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \
+      (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \
+      (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \
+      (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \
+      (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \
+      (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \
+      (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \
+      (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \
+      (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \
+      (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \
+      (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \
+      (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \
+      (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \
+      (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \
+      (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \
+      (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT))
+
+#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int                                : 13;
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+     } cp_miu_tag_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+          unsigned int                                : 13;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+     } cp_miu_tag_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_miu_tag_stat_t f;
+} cp_miu_tag_stat_u;
+
+
+/*
+ * CP_CMD_INDEX struct
+ */
+
+#define CP_CMD_INDEX_CMD_INDEX_SIZE    7
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2
+
+#define CP_CMD_INDEX_CMD_INDEX_SHIFT   0
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16
+
+#define CP_CMD_INDEX_CMD_INDEX_MASK    0x0000007f
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000
+
+#define CP_CMD_INDEX_MASK \
+     (CP_CMD_INDEX_CMD_INDEX_MASK | \
+      CP_CMD_INDEX_CMD_QUEUE_SEL_MASK)
+
+#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \
+     ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \
+      (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT))
+
+#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 14;
+     } cp_cmd_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int                                : 14;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+     } cp_cmd_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_index_t f;
+} cp_cmd_index_u;
+
+
+/*
+ * CP_CMD_DATA struct
+ */
+
+#define CP_CMD_DATA_CMD_DATA_SIZE      32
+
+#define CP_CMD_DATA_CMD_DATA_SHIFT     0
+
+#define CP_CMD_DATA_CMD_DATA_MASK      0xffffffff
+
+#define CP_CMD_DATA_MASK \
+     (CP_CMD_DATA_CMD_DATA_MASK)
+
+#define CP_CMD_DATA(cmd_data) \
+     ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT))
+
+#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \
+     ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \
+     cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_data_t f;
+} cp_cmd_data_u;
+
+
+/*
+ * CP_ME_CNTL struct
+ */
+
+#define CP_ME_CNTL_ME_STATMUX_SIZE     16
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_ME_HALT_SIZE        1
+#define CP_ME_CNTL_ME_BUSY_SIZE        1
+#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE  1
+
+#define CP_ME_CNTL_ME_STATMUX_SHIFT    0
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26
+#define CP_ME_CNTL_ME_HALT_SHIFT       28
+#define CP_ME_CNTL_ME_BUSY_SHIFT       29
+#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31
+
+#define CP_ME_CNTL_ME_STATMUX_MASK     0x0000ffff
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000
+#define CP_ME_CNTL_ME_HALT_MASK        0x10000000
+#define CP_ME_CNTL_ME_BUSY_MASK        0x20000000
+#define CP_ME_CNTL_PROG_CNT_SIZE_MASK  0x80000000
+
+#define CP_ME_CNTL_MASK \
+     (CP_ME_CNTL_ME_STATMUX_MASK | \
+      CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_ME_HALT_MASK | \
+      CP_ME_CNTL_ME_BUSY_MASK | \
+      CP_ME_CNTL_PROG_CNT_SIZE_MASK)
+
+#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \
+     ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \
+      (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \
+      (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \
+      (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT))
+
+#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+          unsigned int                                : 9;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+     } cp_me_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 9;
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+     } cp_me_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+
+/*
+ * CP_ME_STATUS struct
+ */
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_ME_STATUS_MASK \
+     (CP_ME_STATUS_ME_DEBUG_DATA_MASK)
+
+#define CP_ME_STATUS(me_debug_data) \
+     ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT))
+
+#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \
+     ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \
+     cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_status_t f;
+} cp_me_status_u;
+
+
+/*
+ * CP_ME_RAM_WADDR struct
+ */
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_WADDR_MASK \
+     (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK)
+
+#define CP_ME_RAM_WADDR(me_ram_waddr) \
+     ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT))
+
+#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \
+     ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \
+     cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_waddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+     } cp_me_ram_waddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_waddr_t f;
+} cp_me_ram_waddr_u;
+
+
+/*
+ * CP_ME_RAM_RADDR struct
+ */
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_RADDR_MASK \
+     (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK)
+
+#define CP_ME_RAM_RADDR(me_ram_raddr) \
+     ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT))
+
+#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \
+     ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \
+     cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_raddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+     } cp_me_ram_raddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+
+/*
+ * CP_ME_RAM_DATA struct
+ */
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff
+
+#define CP_ME_RAM_DATA_MASK \
+     (CP_ME_RAM_DATA_ME_RAM_DATA_MASK)
+
+#define CP_ME_RAM_DATA(me_ram_data) \
+     ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT))
+
+#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \
+     ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \
+     cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_data_t f;
+} cp_me_ram_data_u;
+
+
+/*
+ * CP_ME_RDADDR struct
+ */
+
+#define CP_ME_RDADDR_ME_RDADDR_SIZE    32
+
+#define CP_ME_RDADDR_ME_RDADDR_SHIFT   0
+
+#define CP_ME_RDADDR_ME_RDADDR_MASK    0xffffffff
+
+#define CP_ME_RDADDR_MASK \
+     (CP_ME_RDADDR_ME_RDADDR_MASK)
+
+#define CP_ME_RDADDR(me_rdaddr) \
+     ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT))
+
+#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \
+     ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \
+     cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_rdaddr_t f;
+} cp_me_rdaddr_u;
+
+
+/*
+ * CP_DEBUG struct
+ */
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23
+#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0
+#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff
+#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000
+#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000
+#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000
+
+#define CP_DEBUG_MASK \
+     (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \
+      CP_DEBUG_PREDICATE_DISABLE_MASK | \
+      CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \
+      CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \
+      CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \
+      CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \
+      CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \
+      CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \
+      CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK)
+
+#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \
+     ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \
+      (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \
+      (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \
+      (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \
+      (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \
+      (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \
+      (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \
+      (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \
+      (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT))
+
+#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \
+     ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \
+     ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+     } cp_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+     } cp_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+
+/*
+ * SCRATCH_REG0 struct
+ */
+
+#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32
+
+#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0
+
+#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff
+
+#define SCRATCH_REG0_MASK \
+     (SCRATCH_REG0_SCRATCH_REG0_MASK)
+
+#define SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT))
+
+#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \
+     scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+
+/*
+ * SCRATCH_REG1 struct
+ */
+
+#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32
+
+#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0
+
+#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff
+
+#define SCRATCH_REG1_MASK \
+     (SCRATCH_REG1_SCRATCH_REG1_MASK)
+
+#define SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT))
+
+#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \
+     scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+
+/*
+ * SCRATCH_REG2 struct
+ */
+
+#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32
+
+#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0
+
+#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff
+
+#define SCRATCH_REG2_MASK \
+     (SCRATCH_REG2_SCRATCH_REG2_MASK)
+
+#define SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT))
+
+#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \
+     scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+
+/*
+ * SCRATCH_REG3 struct
+ */
+
+#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32
+
+#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0
+
+#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff
+
+#define SCRATCH_REG3_MASK \
+     (SCRATCH_REG3_SCRATCH_REG3_MASK)
+
+#define SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT))
+
+#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \
+     scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+
+/*
+ * SCRATCH_REG4 struct
+ */
+
+#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32
+
+#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0
+
+#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff
+
+#define SCRATCH_REG4_MASK \
+     (SCRATCH_REG4_SCRATCH_REG4_MASK)
+
+#define SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT))
+
+#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \
+     scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+
+/*
+ * SCRATCH_REG5 struct
+ */
+
+#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32
+
+#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0
+
+#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff
+
+#define SCRATCH_REG5_MASK \
+     (SCRATCH_REG5_SCRATCH_REG5_MASK)
+
+#define SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT))
+
+#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \
+     scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+
+/*
+ * SCRATCH_REG6 struct
+ */
+
+#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32
+
+#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0
+
+#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff
+
+#define SCRATCH_REG6_MASK \
+     (SCRATCH_REG6_SCRATCH_REG6_MASK)
+
+#define SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT))
+
+#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \
+     scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg6_t f;
+} scratch_reg6_u;
+
+
+/*
+ * SCRATCH_REG7 struct
+ */
+
+#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32
+
+#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0
+
+#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff
+
+#define SCRATCH_REG7_MASK \
+     (SCRATCH_REG7_SCRATCH_REG7_MASK)
+
+#define SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT))
+
+#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \
+     scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg7_t f;
+} scratch_reg7_u;
+
+
+/*
+ * SCRATCH_UMSK struct
+ */
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8
+#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0
+#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff
+#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000
+
+#define SCRATCH_UMSK_MASK \
+     (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \
+      SCRATCH_UMSK_SCRATCH_SWAP_MASK)
+
+#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \
+     ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \
+      (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT))
+
+#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 14;
+     } scratch_umsk_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int                                : 14;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+     } scratch_umsk_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+
+/*
+ * SCRATCH_ADDR struct
+ */
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0
+
+#define SCRATCH_ADDR_MASK \
+     (SCRATCH_ADDR_SCRATCH_ADDR_MASK)
+
+#define SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT))
+
+#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \
+     scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int                                : 5;
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+     } scratch_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+          unsigned int                                : 5;
+     } scratch_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_SRC struct
+ */
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_VS_EVENT_SRC_MASK \
+     (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \
+      CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK)
+
+#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \
+     ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \
+      (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_vs_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int                                : 30;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+     } cp_me_vs_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_src_t f;
+} cp_me_vs_event_src_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_MASK \
+     (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \
+      CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK)
+
+#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \
+     ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \
+      (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_t f;
+} cp_me_vs_event_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_MASK \
+     (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK)
+
+#define CP_ME_VS_EVENT_DATA(vs_done_data) \
+     ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \
+     ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \
+     cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_t f;
+} cp_me_vs_event_data_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \
+      CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \
+     ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \
+      (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_swm_t f;
+} cp_me_vs_event_addr_swm_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_SWM_MASK \
+     (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \
+     ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \
+     ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \
+     cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_swm_t f;
+} cp_me_vs_event_data_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_SRC struct
+ */
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_PS_EVENT_SRC_MASK \
+     (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \
+      CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK)
+
+#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \
+     ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \
+      (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT))
+
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_ps_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int                                : 30;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+     } cp_me_ps_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_src_t f;
+} cp_me_ps_event_src_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_MASK \
+     (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \
+      CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK)
+
+#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \
+     ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \
+      (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_t f;
+} cp_me_ps_event_addr_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_MASK \
+     (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK)
+
+#define CP_ME_PS_EVENT_DATA(ps_done_data) \
+     ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \
+     ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \
+     cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_t f;
+} cp_me_ps_event_data_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \
+      CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \
+     ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \
+      (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_swm_t f;
+} cp_me_ps_event_addr_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_SWM_MASK \
+     (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \
+     ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \
+     ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \
+     cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_swm_t f;
+} cp_me_ps_event_data_swm_u;
+
+
+/*
+ * CP_ME_CF_EVENT_SRC struct
+ */
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001
+
+#define CP_ME_CF_EVENT_SRC_MASK \
+     (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK)
+
+#define CP_ME_CF_EVENT_SRC(cf_done_src) \
+     ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT))
+
+#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \
+     ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \
+     cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+          unsigned int                                : 31;
+     } cp_me_cf_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int                                : 31;
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+     } cp_me_cf_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_src_t f;
+} cp_me_cf_event_src_u;
+
+
+/*
+ * CP_ME_CF_EVENT_ADDR struct
+ */
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_CF_EVENT_ADDR_MASK \
+     (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \
+      CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK)
+
+#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \
+     ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \
+      (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT))
+
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_addr_t f;
+} cp_me_cf_event_addr_u;
+
+
+/*
+ * CP_ME_CF_EVENT_DATA struct
+ */
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_CF_EVENT_DATA_MASK \
+     (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK)
+
+#define CP_ME_CF_EVENT_DATA(cf_done_data) \
+     ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT))
+
+#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \
+     ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \
+     cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_data_t f;
+} cp_me_cf_event_data_u;
+
+
+/*
+ * CP_ME_NRT_ADDR struct
+ */
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_NRT_ADDR_MASK \
+     (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \
+      CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK)
+
+#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \
+     ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \
+      (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT))
+
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+     } cp_me_nrt_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+     } cp_me_nrt_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_addr_t f;
+} cp_me_nrt_addr_u;
+
+
+/*
+ * CP_ME_NRT_DATA struct
+ */
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff
+
+#define CP_ME_NRT_DATA_MASK \
+     (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK)
+
+#define CP_ME_NRT_DATA(nrt_write_data) \
+     ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT))
+
+#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \
+     ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \
+     cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_data_t f;
+} cp_me_nrt_data_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_SRC struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001
+
+#define CP_ME_VS_FETCH_DONE_SRC_MASK \
+     (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \
+     ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \
+     ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \
+     cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+          unsigned int                                : 31;
+     } cp_me_vs_fetch_done_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int                                : 31;
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+     } cp_me_vs_fetch_done_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_src_t f;
+} cp_me_vs_fetch_done_src_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_ADDR struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_FETCH_DONE_ADDR_MASK \
+     (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \
+      CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \
+     ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \
+      (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_addr_t f;
+} cp_me_vs_fetch_done_addr_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_DATA struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_FETCH_DONE_DATA_MASK \
+     (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK)
+
+#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \
+     ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \
+     ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \
+     cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_data_t f;
+} cp_me_vs_fetch_done_data_u;
+
+
+/*
+ * CP_INT_CNTL struct
+ */
+
+#define CP_INT_CNTL_SW_INT_MASK_SIZE   1
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB2_INT_MASK_SIZE  1
+#define CP_INT_CNTL_IB1_INT_MASK_SIZE  1
+#define CP_INT_CNTL_RB_INT_MASK_SIZE   1
+
+#define CP_INT_CNTL_SW_INT_MASK_SHIFT  19
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26
+#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27
+#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29
+#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30
+#define CP_INT_CNTL_RB_INT_MASK_SHIFT  31
+
+#define CP_INT_CNTL_SW_INT_MASK_MASK   0x00080000
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000
+#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000
+#define CP_INT_CNTL_IB2_INT_MASK_MASK  0x20000000
+#define CP_INT_CNTL_IB1_INT_MASK_MASK  0x40000000
+#define CP_INT_CNTL_RB_INT_MASK_MASK   0x80000000
+
+#define CP_INT_CNTL_MASK \
+     (CP_INT_CNTL_SW_INT_MASK_MASK | \
+      CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \
+      CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB2_INT_MASK_MASK | \
+      CP_INT_CNTL_IB1_INT_MASK_MASK | \
+      CP_INT_CNTL_RB_INT_MASK_MASK)
+
+#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \
+     ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \
+      (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \
+      (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \
+      (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \
+      (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \
+      (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \
+      (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \
+      (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \
+      (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT))
+
+#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+     } cp_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_cntl_t f;
+} cp_int_cntl_u;
+
+
+/*
+ * CP_INT_STATUS struct
+ */
+
+#define CP_INT_STATUS_SW_INT_STAT_SIZE 1
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1
+#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1
+#define CP_INT_STATUS_RB_INT_STAT_SIZE 1
+
+#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26
+#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27
+#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29
+#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30
+#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31
+
+#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000
+#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000
+#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000
+
+#define CP_INT_STATUS_MASK \
+     (CP_INT_STATUS_SW_INT_STAT_MASK | \
+      CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \
+      CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB2_INT_STAT_MASK | \
+      CP_INT_STATUS_IB1_INT_STAT_MASK | \
+      CP_INT_STATUS_RB_INT_STAT_MASK)
+
+#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \
+     ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \
+      (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \
+      (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \
+      (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \
+      (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \
+      (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \
+      (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \
+      (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \
+      (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT))
+
+#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+     } cp_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 19;
+     } cp_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_status_t f;
+} cp_int_status_u;
+
+
+/*
+ * CP_INT_ACK struct
+ */
+
+#define CP_INT_ACK_SW_INT_ACK_SIZE     1
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_IB_ERROR_ACK_SIZE   1
+#define CP_INT_ACK_IB2_INT_ACK_SIZE    1
+#define CP_INT_ACK_IB1_INT_ACK_SIZE    1
+#define CP_INT_ACK_RB_INT_ACK_SIZE     1
+
+#define CP_INT_ACK_SW_INT_ACK_SHIFT    19
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26
+#define CP_INT_ACK_IB_ERROR_ACK_SHIFT  27
+#define CP_INT_ACK_IB2_INT_ACK_SHIFT   29
+#define CP_INT_ACK_IB1_INT_ACK_SHIFT   30
+#define CP_INT_ACK_RB_INT_ACK_SHIFT    31
+
+#define CP_INT_ACK_SW_INT_ACK_MASK     0x00080000
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000
+#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000
+#define CP_INT_ACK_IB_ERROR_ACK_MASK   0x08000000
+#define CP_INT_ACK_IB2_INT_ACK_MASK    0x20000000
+#define CP_INT_ACK_IB1_INT_ACK_MASK    0x40000000
+#define CP_INT_ACK_RB_INT_ACK_MASK     0x80000000
+
+#define CP_INT_ACK_MASK \
+     (CP_INT_ACK_SW_INT_ACK_MASK | \
+      CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \
+      CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB2_INT_ACK_MASK | \
+      CP_INT_ACK_IB1_INT_ACK_MASK | \
+      CP_INT_ACK_RB_INT_ACK_MASK)
+
+#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \
+     ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \
+      (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \
+      (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \
+      (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \
+      (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \
+      (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \
+      (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \
+      (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \
+      (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT))
+
+#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+     } cp_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_ack_t f;
+} cp_int_ack_u;
+
+
+/*
+ * CP_PFP_UCODE_ADDR struct
+ */
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff
+
+#define CP_PFP_UCODE_ADDR_MASK \
+     (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK)
+
+#define CP_PFP_UCODE_ADDR(ucode_addr) \
+     ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT))
+
+#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \
+     ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \
+     cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+          unsigned int                                : 23;
+     } cp_pfp_ucode_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int                                : 23;
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+     } cp_pfp_ucode_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_addr_t f;
+} cp_pfp_ucode_addr_u;
+
+
+/*
+ * CP_PFP_UCODE_DATA struct
+ */
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff
+
+#define CP_PFP_UCODE_DATA_MASK \
+     (CP_PFP_UCODE_DATA_UCODE_DATA_MASK)
+
+#define CP_PFP_UCODE_DATA(ucode_data) \
+     ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT))
+
+#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \
+     ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \
+     cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+          unsigned int                                : 8;
+     } cp_pfp_ucode_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int                                : 8;
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+     } cp_pfp_ucode_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_data_t f;
+} cp_pfp_ucode_data_u;
+
+
+/*
+ * CP_PERFMON_CNTL struct
+ */
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300
+
+#define CP_PERFMON_CNTL_MASK \
+     (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \
+      CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK)
+
+#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \
+     ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \
+      (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT))
+
+#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 22;
+     } cp_perfmon_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int                                : 22;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+     } cp_perfmon_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfmon_cntl_t f;
+} cp_perfmon_cntl_u;
+
+
+/*
+ * CP_PERFCOUNTER_SELECT struct
+ */
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f
+
+#define CP_PERFCOUNTER_SELECT_MASK \
+     (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK)
+
+#define CP_PERFCOUNTER_SELECT(perfcount_sel) \
+     ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT))
+
+#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \
+     ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \
+     cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+          unsigned int                                : 26;
+     } cp_perfcounter_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int                                : 26;
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+     } cp_perfcounter_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_select_t f;
+} cp_perfcounter_select_u;
+
+
+/*
+ * CP_PERFCOUNTER_LO struct
+ */
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff
+
+#define CP_PERFCOUNTER_LO_MASK \
+     (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK)
+
+#define CP_PERFCOUNTER_LO(perfcount_lo) \
+     ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT))
+
+#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \
+     ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \
+     cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_lo_t f;
+} cp_perfcounter_lo_u;
+
+
+/*
+ * CP_PERFCOUNTER_HI struct
+ */
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff
+
+#define CP_PERFCOUNTER_HI_MASK \
+     (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK)
+
+#define CP_PERFCOUNTER_HI(perfcount_hi) \
+     ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT))
+
+#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \
+     ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \
+     cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+          unsigned int                                : 16;
+     } cp_perfcounter_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+     } cp_perfcounter_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_hi_t f;
+} cp_perfcounter_hi_u;
+
+
+/*
+ * CP_BIN_MASK_LO struct
+ */
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff
+
+#define CP_BIN_MASK_LO_MASK \
+     (CP_BIN_MASK_LO_BIN_MASK_LO_MASK)
+
+#define CP_BIN_MASK_LO(bin_mask_lo) \
+     ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT))
+
+#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \
+     ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \
+     cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_lo_t f;
+} cp_bin_mask_lo_u;
+
+
+/*
+ * CP_BIN_MASK_HI struct
+ */
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff
+
+#define CP_BIN_MASK_HI_MASK \
+     (CP_BIN_MASK_HI_BIN_MASK_HI_MASK)
+
+#define CP_BIN_MASK_HI(bin_mask_hi) \
+     ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT))
+
+#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \
+     ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \
+     cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_hi_t f;
+} cp_bin_mask_hi_u;
+
+
+/*
+ * CP_BIN_SELECT_LO struct
+ */
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff
+
+#define CP_BIN_SELECT_LO_MASK \
+     (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK)
+
+#define CP_BIN_SELECT_LO(bin_select_lo) \
+     ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT))
+
+#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \
+     ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \
+     cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_lo_t f;
+} cp_bin_select_lo_u;
+
+
+/*
+ * CP_BIN_SELECT_HI struct
+ */
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff
+
+#define CP_BIN_SELECT_HI_MASK \
+     (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK)
+
+#define CP_BIN_SELECT_HI(bin_select_hi) \
+     ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT))
+
+#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \
+     ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \
+     cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_hi_t f;
+} cp_bin_select_hi_u;
+
+
+/*
+ * CP_NV_FLAGS_0 struct
+ */
+
+#define CP_NV_FLAGS_0_DISCARD_0_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_0_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_1_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_1_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_2_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_2_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_3_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_3_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_4_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_4_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_5_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_5_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_6_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_6_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_7_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_7_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_8_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_8_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_9_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_9_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_10_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_11_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_12_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_13_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_14_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_15_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1
+
+#define CP_NV_FLAGS_0_DISCARD_0_SHIFT  0
+#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1
+#define CP_NV_FLAGS_0_DISCARD_1_SHIFT  2
+#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3
+#define CP_NV_FLAGS_0_DISCARD_2_SHIFT  4
+#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5
+#define CP_NV_FLAGS_0_DISCARD_3_SHIFT  6
+#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7
+#define CP_NV_FLAGS_0_DISCARD_4_SHIFT  8
+#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9
+#define CP_NV_FLAGS_0_DISCARD_5_SHIFT  10
+#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11
+#define CP_NV_FLAGS_0_DISCARD_6_SHIFT  12
+#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13
+#define CP_NV_FLAGS_0_DISCARD_7_SHIFT  14
+#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15
+#define CP_NV_FLAGS_0_DISCARD_8_SHIFT  16
+#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17
+#define CP_NV_FLAGS_0_DISCARD_9_SHIFT  18
+#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19
+#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20
+#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21
+#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22
+#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23
+#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24
+#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25
+#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26
+#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27
+#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28
+#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29
+#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30
+#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31
+
+#define CP_NV_FLAGS_0_DISCARD_0_MASK   0x00000001
+#define CP_NV_FLAGS_0_END_RCVD_0_MASK  0x00000002
+#define CP_NV_FLAGS_0_DISCARD_1_MASK   0x00000004
+#define CP_NV_FLAGS_0_END_RCVD_1_MASK  0x00000008
+#define CP_NV_FLAGS_0_DISCARD_2_MASK   0x00000010
+#define CP_NV_FLAGS_0_END_RCVD_2_MASK  0x00000020
+#define CP_NV_FLAGS_0_DISCARD_3_MASK   0x00000040
+#define CP_NV_FLAGS_0_END_RCVD_3_MASK  0x00000080
+#define CP_NV_FLAGS_0_DISCARD_4_MASK   0x00000100
+#define CP_NV_FLAGS_0_END_RCVD_4_MASK  0x00000200
+#define CP_NV_FLAGS_0_DISCARD_5_MASK   0x00000400
+#define CP_NV_FLAGS_0_END_RCVD_5_MASK  0x00000800
+#define CP_NV_FLAGS_0_DISCARD_6_MASK   0x00001000
+#define CP_NV_FLAGS_0_END_RCVD_6_MASK  0x00002000
+#define CP_NV_FLAGS_0_DISCARD_7_MASK   0x00004000
+#define CP_NV_FLAGS_0_END_RCVD_7_MASK  0x00008000
+#define CP_NV_FLAGS_0_DISCARD_8_MASK   0x00010000
+#define CP_NV_FLAGS_0_END_RCVD_8_MASK  0x00020000
+#define CP_NV_FLAGS_0_DISCARD_9_MASK   0x00040000
+#define CP_NV_FLAGS_0_END_RCVD_9_MASK  0x00080000
+#define CP_NV_FLAGS_0_DISCARD_10_MASK  0x00100000
+#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000
+#define CP_NV_FLAGS_0_DISCARD_11_MASK  0x00400000
+#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000
+#define CP_NV_FLAGS_0_DISCARD_12_MASK  0x01000000
+#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000
+#define CP_NV_FLAGS_0_DISCARD_13_MASK  0x04000000
+#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000
+#define CP_NV_FLAGS_0_DISCARD_14_MASK  0x10000000
+#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000
+#define CP_NV_FLAGS_0_DISCARD_15_MASK  0x40000000
+#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000
+
+#define CP_NV_FLAGS_0_MASK \
+     (CP_NV_FLAGS_0_DISCARD_0_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_0_MASK | \
+      CP_NV_FLAGS_0_DISCARD_1_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_1_MASK | \
+      CP_NV_FLAGS_0_DISCARD_2_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_2_MASK | \
+      CP_NV_FLAGS_0_DISCARD_3_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_3_MASK | \
+      CP_NV_FLAGS_0_DISCARD_4_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_4_MASK | \
+      CP_NV_FLAGS_0_DISCARD_5_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_5_MASK | \
+      CP_NV_FLAGS_0_DISCARD_6_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_6_MASK | \
+      CP_NV_FLAGS_0_DISCARD_7_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_7_MASK | \
+      CP_NV_FLAGS_0_DISCARD_8_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_8_MASK | \
+      CP_NV_FLAGS_0_DISCARD_9_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_9_MASK | \
+      CP_NV_FLAGS_0_DISCARD_10_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_10_MASK | \
+      CP_NV_FLAGS_0_DISCARD_11_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_11_MASK | \
+      CP_NV_FLAGS_0_DISCARD_12_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_12_MASK | \
+      CP_NV_FLAGS_0_DISCARD_13_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_13_MASK | \
+      CP_NV_FLAGS_0_DISCARD_14_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_14_MASK | \
+      CP_NV_FLAGS_0_DISCARD_15_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_15_MASK)
+
+#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \
+     ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \
+      (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \
+      (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \
+      (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \
+      (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \
+      (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \
+      (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \
+      (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \
+      (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \
+      (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \
+      (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \
+      (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \
+      (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \
+      (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \
+      (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \
+      (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \
+      (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \
+      (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \
+      (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \
+      (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \
+      (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \
+      (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \
+      (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \
+      (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \
+      (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \
+      (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \
+      (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \
+      (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \
+      (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \
+      (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \
+      (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \
+      (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT))
+
+#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+     } cp_nv_flags_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+     } cp_nv_flags_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_0_t f;
+} cp_nv_flags_0_u;
+
+
+/*
+ * CP_NV_FLAGS_1 struct
+ */
+
+#define CP_NV_FLAGS_1_DISCARD_16_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_17_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_18_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_19_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_20_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_21_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_22_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_23_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_24_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_25_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_26_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_27_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_28_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_29_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_30_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_31_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1
+
+#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0
+#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1
+#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2
+#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3
+#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4
+#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5
+#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6
+#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7
+#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8
+#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9
+#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10
+#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11
+#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12
+#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13
+#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14
+#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15
+#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16
+#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17
+#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18
+#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19
+#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20
+#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21
+#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22
+#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23
+#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24
+#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25
+#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26
+#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27
+#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28
+#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29
+#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30
+#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31
+
+#define CP_NV_FLAGS_1_DISCARD_16_MASK  0x00000001
+#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002
+#define CP_NV_FLAGS_1_DISCARD_17_MASK  0x00000004
+#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008
+#define CP_NV_FLAGS_1_DISCARD_18_MASK  0x00000010
+#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020
+#define CP_NV_FLAGS_1_DISCARD_19_MASK  0x00000040
+#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080
+#define CP_NV_FLAGS_1_DISCARD_20_MASK  0x00000100
+#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200
+#define CP_NV_FLAGS_1_DISCARD_21_MASK  0x00000400
+#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800
+#define CP_NV_FLAGS_1_DISCARD_22_MASK  0x00001000
+#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000
+#define CP_NV_FLAGS_1_DISCARD_23_MASK  0x00004000
+#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000
+#define CP_NV_FLAGS_1_DISCARD_24_MASK  0x00010000
+#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000
+#define CP_NV_FLAGS_1_DISCARD_25_MASK  0x00040000
+#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000
+#define CP_NV_FLAGS_1_DISCARD_26_MASK  0x00100000
+#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000
+#define CP_NV_FLAGS_1_DISCARD_27_MASK  0x00400000
+#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000
+#define CP_NV_FLAGS_1_DISCARD_28_MASK  0x01000000
+#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000
+#define CP_NV_FLAGS_1_DISCARD_29_MASK  0x04000000
+#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000
+#define CP_NV_FLAGS_1_DISCARD_30_MASK  0x10000000
+#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000
+#define CP_NV_FLAGS_1_DISCARD_31_MASK  0x40000000
+#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000
+
+#define CP_NV_FLAGS_1_MASK \
+     (CP_NV_FLAGS_1_DISCARD_16_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_16_MASK | \
+      CP_NV_FLAGS_1_DISCARD_17_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_17_MASK | \
+      CP_NV_FLAGS_1_DISCARD_18_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_18_MASK | \
+      CP_NV_FLAGS_1_DISCARD_19_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_19_MASK | \
+      CP_NV_FLAGS_1_DISCARD_20_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_20_MASK | \
+      CP_NV_FLAGS_1_DISCARD_21_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_21_MASK | \
+      CP_NV_FLAGS_1_DISCARD_22_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_22_MASK | \
+      CP_NV_FLAGS_1_DISCARD_23_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_23_MASK | \
+      CP_NV_FLAGS_1_DISCARD_24_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_24_MASK | \
+      CP_NV_FLAGS_1_DISCARD_25_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_25_MASK | \
+      CP_NV_FLAGS_1_DISCARD_26_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_26_MASK | \
+      CP_NV_FLAGS_1_DISCARD_27_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_27_MASK | \
+      CP_NV_FLAGS_1_DISCARD_28_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_28_MASK | \
+      CP_NV_FLAGS_1_DISCARD_29_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_29_MASK | \
+      CP_NV_FLAGS_1_DISCARD_30_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_30_MASK | \
+      CP_NV_FLAGS_1_DISCARD_31_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_31_MASK)
+
+#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \
+     ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \
+      (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \
+      (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \
+      (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \
+      (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \
+      (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \
+      (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \
+      (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \
+      (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \
+      (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \
+      (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \
+      (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \
+      (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \
+      (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \
+      (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \
+      (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \
+      (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \
+      (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \
+      (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \
+      (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \
+      (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \
+      (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \
+      (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \
+      (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \
+      (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \
+      (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \
+      (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \
+      (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \
+      (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \
+      (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \
+      (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \
+      (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT))
+
+#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+     } cp_nv_flags_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+     } cp_nv_flags_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_1_t f;
+} cp_nv_flags_1_u;
+
+
+/*
+ * CP_NV_FLAGS_2 struct
+ */
+
+#define CP_NV_FLAGS_2_DISCARD_32_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_33_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_34_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_35_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_36_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_37_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_38_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_39_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_40_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_41_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_42_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_43_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_44_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_45_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_46_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_47_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1
+
+#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0
+#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1
+#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2
+#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3
+#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4
+#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5
+#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6
+#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7
+#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8
+#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9
+#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10
+#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11
+#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12
+#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13
+#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14
+#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15
+#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16
+#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17
+#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18
+#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19
+#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20
+#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21
+#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22
+#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23
+#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24
+#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25
+#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26
+#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27
+#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28
+#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29
+#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30
+#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31
+
+#define CP_NV_FLAGS_2_DISCARD_32_MASK  0x00000001
+#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002
+#define CP_NV_FLAGS_2_DISCARD_33_MASK  0x00000004
+#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008
+#define CP_NV_FLAGS_2_DISCARD_34_MASK  0x00000010
+#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020
+#define CP_NV_FLAGS_2_DISCARD_35_MASK  0x00000040
+#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080
+#define CP_NV_FLAGS_2_DISCARD_36_MASK  0x00000100
+#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200
+#define CP_NV_FLAGS_2_DISCARD_37_MASK  0x00000400
+#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800
+#define CP_NV_FLAGS_2_DISCARD_38_MASK  0x00001000
+#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000
+#define CP_NV_FLAGS_2_DISCARD_39_MASK  0x00004000
+#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000
+#define CP_NV_FLAGS_2_DISCARD_40_MASK  0x00010000
+#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000
+#define CP_NV_FLAGS_2_DISCARD_41_MASK  0x00040000
+#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000
+#define CP_NV_FLAGS_2_DISCARD_42_MASK  0x00100000
+#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000
+#define CP_NV_FLAGS_2_DISCARD_43_MASK  0x00400000
+#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000
+#define CP_NV_FLAGS_2_DISCARD_44_MASK  0x01000000
+#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000
+#define CP_NV_FLAGS_2_DISCARD_45_MASK  0x04000000
+#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000
+#define CP_NV_FLAGS_2_DISCARD_46_MASK  0x10000000
+#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000
+#define CP_NV_FLAGS_2_DISCARD_47_MASK  0x40000000
+#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000
+
+#define CP_NV_FLAGS_2_MASK \
+     (CP_NV_FLAGS_2_DISCARD_32_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_32_MASK | \
+      CP_NV_FLAGS_2_DISCARD_33_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_33_MASK | \
+      CP_NV_FLAGS_2_DISCARD_34_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_34_MASK | \
+      CP_NV_FLAGS_2_DISCARD_35_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_35_MASK | \
+      CP_NV_FLAGS_2_DISCARD_36_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_36_MASK | \
+      CP_NV_FLAGS_2_DISCARD_37_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_37_MASK | \
+      CP_NV_FLAGS_2_DISCARD_38_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_38_MASK | \
+      CP_NV_FLAGS_2_DISCARD_39_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_39_MASK | \
+      CP_NV_FLAGS_2_DISCARD_40_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_40_MASK | \
+      CP_NV_FLAGS_2_DISCARD_41_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_41_MASK | \
+      CP_NV_FLAGS_2_DISCARD_42_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_42_MASK | \
+      CP_NV_FLAGS_2_DISCARD_43_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_43_MASK | \
+      CP_NV_FLAGS_2_DISCARD_44_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_44_MASK | \
+      CP_NV_FLAGS_2_DISCARD_45_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_45_MASK | \
+      CP_NV_FLAGS_2_DISCARD_46_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_46_MASK | \
+      CP_NV_FLAGS_2_DISCARD_47_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_47_MASK)
+
+#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \
+     ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \
+      (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \
+      (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \
+      (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \
+      (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \
+      (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \
+      (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \
+      (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \
+      (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \
+      (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \
+      (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \
+      (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \
+      (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \
+      (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \
+      (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \
+      (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \
+      (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \
+      (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \
+      (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \
+      (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \
+      (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \
+      (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \
+      (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \
+      (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \
+      (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \
+      (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \
+      (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \
+      (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \
+      (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \
+      (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \
+      (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \
+      (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT))
+
+#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+     } cp_nv_flags_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+     } cp_nv_flags_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_2_t f;
+} cp_nv_flags_2_u;
+
+
+/*
+ * CP_NV_FLAGS_3 struct
+ */
+
+#define CP_NV_FLAGS_3_DISCARD_48_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_49_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_50_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_51_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_52_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_53_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_54_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_55_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_56_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_57_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_58_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_59_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_60_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_61_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_62_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_63_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1
+
+#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0
+#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1
+#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2
+#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3
+#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4
+#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5
+#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6
+#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7
+#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8
+#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9
+#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10
+#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11
+#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12
+#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13
+#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14
+#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15
+#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16
+#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17
+#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18
+#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19
+#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20
+#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21
+#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22
+#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23
+#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24
+#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25
+#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26
+#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27
+#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28
+#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29
+#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30
+#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31
+
+#define CP_NV_FLAGS_3_DISCARD_48_MASK  0x00000001
+#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002
+#define CP_NV_FLAGS_3_DISCARD_49_MASK  0x00000004
+#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008
+#define CP_NV_FLAGS_3_DISCARD_50_MASK  0x00000010
+#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020
+#define CP_NV_FLAGS_3_DISCARD_51_MASK  0x00000040
+#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080
+#define CP_NV_FLAGS_3_DISCARD_52_MASK  0x00000100
+#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200
+#define CP_NV_FLAGS_3_DISCARD_53_MASK  0x00000400
+#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800
+#define CP_NV_FLAGS_3_DISCARD_54_MASK  0x00001000
+#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000
+#define CP_NV_FLAGS_3_DISCARD_55_MASK  0x00004000
+#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000
+#define CP_NV_FLAGS_3_DISCARD_56_MASK  0x00010000
+#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000
+#define CP_NV_FLAGS_3_DISCARD_57_MASK  0x00040000
+#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000
+#define CP_NV_FLAGS_3_DISCARD_58_MASK  0x00100000
+#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000
+#define CP_NV_FLAGS_3_DISCARD_59_MASK  0x00400000
+#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000
+#define CP_NV_FLAGS_3_DISCARD_60_MASK  0x01000000
+#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000
+#define CP_NV_FLAGS_3_DISCARD_61_MASK  0x04000000
+#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000
+#define CP_NV_FLAGS_3_DISCARD_62_MASK  0x10000000
+#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000
+#define CP_NV_FLAGS_3_DISCARD_63_MASK  0x40000000
+#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000
+
+#define CP_NV_FLAGS_3_MASK \
+     (CP_NV_FLAGS_3_DISCARD_48_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_48_MASK | \
+      CP_NV_FLAGS_3_DISCARD_49_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_49_MASK | \
+      CP_NV_FLAGS_3_DISCARD_50_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_50_MASK | \
+      CP_NV_FLAGS_3_DISCARD_51_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_51_MASK | \
+      CP_NV_FLAGS_3_DISCARD_52_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_52_MASK | \
+      CP_NV_FLAGS_3_DISCARD_53_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_53_MASK | \
+      CP_NV_FLAGS_3_DISCARD_54_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_54_MASK | \
+      CP_NV_FLAGS_3_DISCARD_55_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_55_MASK | \
+      CP_NV_FLAGS_3_DISCARD_56_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_56_MASK | \
+      CP_NV_FLAGS_3_DISCARD_57_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_57_MASK | \
+      CP_NV_FLAGS_3_DISCARD_58_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_58_MASK | \
+      CP_NV_FLAGS_3_DISCARD_59_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_59_MASK | \
+      CP_NV_FLAGS_3_DISCARD_60_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_60_MASK | \
+      CP_NV_FLAGS_3_DISCARD_61_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_61_MASK | \
+      CP_NV_FLAGS_3_DISCARD_62_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_62_MASK | \
+      CP_NV_FLAGS_3_DISCARD_63_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_63_MASK)
+
+#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \
+     ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \
+      (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \
+      (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \
+      (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \
+      (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \
+      (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \
+      (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \
+      (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \
+      (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \
+      (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \
+      (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \
+      (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \
+      (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \
+      (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \
+      (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \
+      (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \
+      (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \
+      (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \
+      (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \
+      (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \
+      (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \
+      (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \
+      (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \
+      (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \
+      (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \
+      (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \
+      (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \
+      (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \
+      (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \
+      (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \
+      (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \
+      (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT))
+
+#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+     } cp_nv_flags_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+     } cp_nv_flags_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_3_t f;
+} cp_nv_flags_3_u;
+
+
+/*
+ * CP_STATE_DEBUG_INDEX struct
+ */
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f
+
+#define CP_STATE_DEBUG_INDEX_MASK \
+     (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK)
+
+#define CP_STATE_DEBUG_INDEX(state_debug_index) \
+     ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT))
+
+#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \
+     ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \
+     cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+          unsigned int                                : 27;
+     } cp_state_debug_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int                                : 27;
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+     } cp_state_debug_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_index_t f;
+} cp_state_debug_index_u;
+
+
+/*
+ * CP_STATE_DEBUG_DATA struct
+ */
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_STATE_DEBUG_DATA_MASK \
+     (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK)
+
+#define CP_STATE_DEBUG_DATA(state_debug_data) \
+     ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT))
+
+#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \
+     ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \
+     cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_data_t f;
+} cp_state_debug_data_u;
+
+
+/*
+ * CP_PROG_COUNTER struct
+ */
+
+#define CP_PROG_COUNTER_COUNTER_SIZE   32
+
+#define CP_PROG_COUNTER_COUNTER_SHIFT  0
+
+#define CP_PROG_COUNTER_COUNTER_MASK   0xffffffff
+
+#define CP_PROG_COUNTER_MASK \
+     (CP_PROG_COUNTER_COUNTER_MASK)
+
+#define CP_PROG_COUNTER(counter) \
+     ((counter << CP_PROG_COUNTER_COUNTER_SHIFT))
+
+#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \
+     ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \
+     cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_prog_counter_t f;
+} cp_prog_counter_u;
+
+
+/*
+ * CP_STAT struct
+ */
+
+#define CP_STAT_MIU_WR_BUSY_SIZE       1
+#define CP_STAT_MIU_RD_REQ_BUSY_SIZE   1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1
+#define CP_STAT_RBIU_BUSY_SIZE         1
+#define CP_STAT_RCIU_BUSY_SIZE         1
+#define CP_STAT_CSF_RING_BUSY_SIZE     1
+#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_CSF_ST_BUSY_SIZE       1
+#define CP_STAT_CSF_BUSY_SIZE          1
+#define CP_STAT_RING_QUEUE_BUSY_SIZE   1
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1
+#define CP_STAT_ST_QUEUE_BUSY_SIZE     1
+#define CP_STAT_PFP_BUSY_SIZE          1
+#define CP_STAT_MEQ_RING_BUSY_SIZE     1
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_MIU_WC_STALL_SIZE      1
+#define CP_STAT_CP_NRT_BUSY_SIZE       1
+#define CP_STAT__3D_BUSY_SIZE          1
+#define CP_STAT_ME_BUSY_SIZE           1
+#define CP_STAT_ME_WC_BUSY_SIZE        1
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1
+#define CP_STAT_CP_BUSY_SIZE           1
+
+#define CP_STAT_MIU_WR_BUSY_SHIFT      0
+#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT  1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2
+#define CP_STAT_RBIU_BUSY_SHIFT        3
+#define CP_STAT_RCIU_BUSY_SHIFT        4
+#define CP_STAT_CSF_RING_BUSY_SHIFT    5
+#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6
+#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7
+#define CP_STAT_CSF_ST_BUSY_SHIFT      9
+#define CP_STAT_CSF_BUSY_SHIFT         10
+#define CP_STAT_RING_QUEUE_BUSY_SHIFT  11
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13
+#define CP_STAT_ST_QUEUE_BUSY_SHIFT    16
+#define CP_STAT_PFP_BUSY_SHIFT         17
+#define CP_STAT_MEQ_RING_BUSY_SHIFT    18
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20
+#define CP_STAT_MIU_WC_STALL_SHIFT     21
+#define CP_STAT_CP_NRT_BUSY_SHIFT      22
+#define CP_STAT__3D_BUSY_SHIFT         23
+#define CP_STAT_ME_BUSY_SHIFT          26
+#define CP_STAT_ME_WC_BUSY_SHIFT       29
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30
+#define CP_STAT_CP_BUSY_SHIFT          31
+
+#define CP_STAT_MIU_WR_BUSY_MASK       0x00000001
+#define CP_STAT_MIU_RD_REQ_BUSY_MASK   0x00000002
+#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004
+#define CP_STAT_RBIU_BUSY_MASK         0x00000008
+#define CP_STAT_RCIU_BUSY_MASK         0x00000010
+#define CP_STAT_CSF_RING_BUSY_MASK     0x00000020
+#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040
+#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080
+#define CP_STAT_CSF_ST_BUSY_MASK       0x00000200
+#define CP_STAT_CSF_BUSY_MASK          0x00000400
+#define CP_STAT_RING_QUEUE_BUSY_MASK   0x00000800
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000
+#define CP_STAT_ST_QUEUE_BUSY_MASK     0x00010000
+#define CP_STAT_PFP_BUSY_MASK          0x00020000
+#define CP_STAT_MEQ_RING_BUSY_MASK     0x00040000
+#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000
+#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000
+#define CP_STAT_MIU_WC_STALL_MASK      0x00200000
+#define CP_STAT_CP_NRT_BUSY_MASK       0x00400000
+#define CP_STAT__3D_BUSY_MASK          0x00800000
+#define CP_STAT_ME_BUSY_MASK           0x04000000
+#define CP_STAT_ME_WC_BUSY_MASK        0x20000000
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000
+#define CP_STAT_CP_BUSY_MASK           0x80000000
+
+#define CP_STAT_MASK \
+     (CP_STAT_MIU_WR_BUSY_MASK | \
+      CP_STAT_MIU_RD_REQ_BUSY_MASK | \
+      CP_STAT_MIU_RD_RETURN_BUSY_MASK | \
+      CP_STAT_RBIU_BUSY_MASK | \
+      CP_STAT_RCIU_BUSY_MASK | \
+      CP_STAT_CSF_RING_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECTS_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECT2_BUSY_MASK | \
+      CP_STAT_CSF_ST_BUSY_MASK | \
+      CP_STAT_CSF_BUSY_MASK | \
+      CP_STAT_RING_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \
+      CP_STAT_ST_QUEUE_BUSY_MASK | \
+      CP_STAT_PFP_BUSY_MASK | \
+      CP_STAT_MEQ_RING_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \
+      CP_STAT_MIU_WC_STALL_MASK | \
+      CP_STAT_CP_NRT_BUSY_MASK | \
+      CP_STAT__3D_BUSY_MASK | \
+      CP_STAT_ME_BUSY_MASK | \
+      CP_STAT_ME_WC_BUSY_MASK | \
+      CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \
+      CP_STAT_CP_BUSY_MASK)
+
+#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \
+     ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \
+      (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \
+      (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \
+      (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \
+      (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \
+      (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \
+      (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \
+      (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \
+      (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \
+      (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \
+      (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \
+      (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \
+      (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \
+      (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \
+      (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \
+      (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \
+      (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \
+      (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \
+      (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \
+      (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \
+      (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \
+      (me_busy << CP_STAT_ME_BUSY_SHIFT) | \
+      (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \
+      (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \
+      (cp_busy << CP_STAT_CP_BUSY_SHIFT))
+
+#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_GET_RBIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_GET_RCIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_PFP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_GET__3D_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_GET_ME_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_GET_CP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT)
+
+#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+     } cp_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+     } cp_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+
+/*
+ * BIOS_0_SCRATCH struct
+ */
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_0_SCRATCH_MASK \
+     (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_0_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \
+     ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \
+     bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_0_scratch_t f;
+} bios_0_scratch_u;
+
+
+/*
+ * BIOS_1_SCRATCH struct
+ */
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_1_SCRATCH_MASK \
+     (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_1_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \
+     ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \
+     bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_1_scratch_t f;
+} bios_1_scratch_u;
+
+
+/*
+ * BIOS_2_SCRATCH struct
+ */
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_2_SCRATCH_MASK \
+     (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_2_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \
+     ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \
+     bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_2_scratch_t f;
+} bios_2_scratch_u;
+
+
+/*
+ * BIOS_3_SCRATCH struct
+ */
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_3_SCRATCH_MASK \
+     (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_3_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \
+     ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \
+     bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_3_scratch_t f;
+} bios_3_scratch_u;
+
+
+/*
+ * BIOS_4_SCRATCH struct
+ */
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_4_SCRATCH_MASK \
+     (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_4_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \
+     ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \
+     bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_4_scratch_t f;
+} bios_4_scratch_u;
+
+
+/*
+ * BIOS_5_SCRATCH struct
+ */
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_5_SCRATCH_MASK \
+     (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_5_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \
+     ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \
+     bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_5_scratch_t f;
+} bios_5_scratch_u;
+
+
+/*
+ * BIOS_6_SCRATCH struct
+ */
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_6_SCRATCH_MASK \
+     (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_6_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \
+     ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \
+     bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_6_scratch_t f;
+} bios_6_scratch_u;
+
+
+/*
+ * BIOS_7_SCRATCH struct
+ */
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_7_SCRATCH_MASK \
+     (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_7_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \
+     ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \
+     bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_7_scratch_t f;
+} bios_7_scratch_u;
+
+
+/*
+ * BIOS_8_SCRATCH struct
+ */
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_8_SCRATCH_MASK \
+     (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_8_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \
+     ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \
+     bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_8_scratch_t f;
+} bios_8_scratch_u;
+
+
+/*
+ * BIOS_9_SCRATCH struct
+ */
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_9_SCRATCH_MASK \
+     (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_9_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \
+     ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \
+     bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_9_scratch_t f;
+} bios_9_scratch_u;
+
+
+/*
+ * BIOS_10_SCRATCH struct
+ */
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_10_SCRATCH_MASK \
+     (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_10_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \
+     ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \
+     bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_10_scratch_t f;
+} bios_10_scratch_u;
+
+
+/*
+ * BIOS_11_SCRATCH struct
+ */
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_11_SCRATCH_MASK \
+     (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_11_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \
+     ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \
+     bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_11_scratch_t f;
+} bios_11_scratch_u;
+
+
+/*
+ * BIOS_12_SCRATCH struct
+ */
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_12_SCRATCH_MASK \
+     (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_12_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \
+     ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \
+     bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_12_scratch_t f;
+} bios_12_scratch_u;
+
+
+/*
+ * BIOS_13_SCRATCH struct
+ */
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_13_SCRATCH_MASK \
+     (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_13_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \
+     ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \
+     bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_13_scratch_t f;
+} bios_13_scratch_u;
+
+
+/*
+ * BIOS_14_SCRATCH struct
+ */
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_14_SCRATCH_MASK \
+     (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_14_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \
+     ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \
+     bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_14_scratch_t f;
+} bios_14_scratch_u;
+
+
+/*
+ * BIOS_15_SCRATCH struct
+ */
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_15_SCRATCH_MASK \
+     (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_15_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \
+     ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \
+     bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_15_scratch_t f;
+} bios_15_scratch_u;
+
+
+/*
+ * COHER_SIZE_PM4 struct
+ */
+
+#define COHER_SIZE_PM4_SIZE_SIZE       32
+
+#define COHER_SIZE_PM4_SIZE_SHIFT      0
+
+#define COHER_SIZE_PM4_SIZE_MASK       0xffffffff
+
+#define COHER_SIZE_PM4_MASK \
+     (COHER_SIZE_PM4_SIZE_MASK)
+
+#define COHER_SIZE_PM4(size) \
+     ((size << COHER_SIZE_PM4_SIZE_SHIFT))
+
+#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \
+     ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT)
+
+#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \
+     coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_pm4_t f;
+} coher_size_pm4_u;
+
+
+/*
+ * COHER_BASE_PM4 struct
+ */
+
+#define COHER_BASE_PM4_BASE_SIZE       32
+
+#define COHER_BASE_PM4_BASE_SHIFT      0
+
+#define COHER_BASE_PM4_BASE_MASK       0xffffffff
+
+#define COHER_BASE_PM4_MASK \
+     (COHER_BASE_PM4_BASE_MASK)
+
+#define COHER_BASE_PM4(base) \
+     ((base << COHER_BASE_PM4_BASE_SHIFT))
+
+#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \
+     ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT)
+
+#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \
+     coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_pm4_t f;
+} coher_base_pm4_u;
+
+
+/*
+ * COHER_STATUS_PM4 struct
+ */
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_PM4_STATUS_SIZE   1
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_PM4_STATUS_SHIFT  31
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_PM4_STATUS_MASK   0x80000000
+
+#define COHER_STATUS_PM4_MASK \
+     (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_PM4_STATUS_MASK)
+
+#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_PM4_STATUS_SHIFT))
+
+#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT)
+
+#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+     } coher_status_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+     } coher_status_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_pm4_t f;
+} coher_status_pm4_u;
+
+
+/*
+ * COHER_SIZE_HOST struct
+ */
+
+#define COHER_SIZE_HOST_SIZE_SIZE      32
+
+#define COHER_SIZE_HOST_SIZE_SHIFT     0
+
+#define COHER_SIZE_HOST_SIZE_MASK      0xffffffff
+
+#define COHER_SIZE_HOST_MASK \
+     (COHER_SIZE_HOST_SIZE_MASK)
+
+#define COHER_SIZE_HOST(size) \
+     ((size << COHER_SIZE_HOST_SIZE_SHIFT))
+
+#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \
+     ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT)
+
+#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \
+     coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_host_t f;
+} coher_size_host_u;
+
+
+/*
+ * COHER_BASE_HOST struct
+ */
+
+#define COHER_BASE_HOST_BASE_SIZE      32
+
+#define COHER_BASE_HOST_BASE_SHIFT     0
+
+#define COHER_BASE_HOST_BASE_MASK      0xffffffff
+
+#define COHER_BASE_HOST_MASK \
+     (COHER_BASE_HOST_BASE_MASK)
+
+#define COHER_BASE_HOST(base) \
+     ((base << COHER_BASE_HOST_BASE_SHIFT))
+
+#define COHER_BASE_HOST_GET_BASE(coher_base_host) \
+     ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT)
+
+#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \
+     coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_host_t f;
+} coher_base_host_u;
+
+
+/*
+ * COHER_STATUS_HOST struct
+ */
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_HOST_STATUS_SIZE  1
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_HOST_STATUS_SHIFT 31
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_HOST_STATUS_MASK  0x80000000
+
+#define COHER_STATUS_HOST_MASK \
+     (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_HOST_STATUS_MASK)
+
+#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_HOST_STATUS_SHIFT))
+
+#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT)
+
+#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+     } coher_status_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 8;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+     } coher_status_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_host_t f;
+} coher_status_host_u;
+
+
+/*
+ * COHER_DEST_BASE_0 struct
+ */
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000
+
+#define COHER_DEST_BASE_0_MASK \
+     (COHER_DEST_BASE_0_DEST_BASE_0_MASK)
+
+#define COHER_DEST_BASE_0(dest_base_0) \
+     ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT))
+
+#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \
+     ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \
+     coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+     } coher_dest_base_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_0_t f;
+} coher_dest_base_0_u;
+
+
+/*
+ * COHER_DEST_BASE_1 struct
+ */
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000
+
+#define COHER_DEST_BASE_1_MASK \
+     (COHER_DEST_BASE_1_DEST_BASE_1_MASK)
+
+#define COHER_DEST_BASE_1(dest_base_1) \
+     ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT))
+
+#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \
+     ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \
+     coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+     } coher_dest_base_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_1_t f;
+} coher_dest_base_1_u;
+
+
+/*
+ * COHER_DEST_BASE_2 struct
+ */
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000
+
+#define COHER_DEST_BASE_2_MASK \
+     (COHER_DEST_BASE_2_DEST_BASE_2_MASK)
+
+#define COHER_DEST_BASE_2(dest_base_2) \
+     ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT))
+
+#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \
+     ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \
+     coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+     } coher_dest_base_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_2_t f;
+} coher_dest_base_2_u;
+
+
+/*
+ * COHER_DEST_BASE_3 struct
+ */
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000
+
+#define COHER_DEST_BASE_3_MASK \
+     (COHER_DEST_BASE_3_DEST_BASE_3_MASK)
+
+#define COHER_DEST_BASE_3(dest_base_3) \
+     ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT))
+
+#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \
+     ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \
+     coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+     } coher_dest_base_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_3_t f;
+} coher_dest_base_3_u;
+
+
+/*
+ * COHER_DEST_BASE_4 struct
+ */
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000
+
+#define COHER_DEST_BASE_4_MASK \
+     (COHER_DEST_BASE_4_DEST_BASE_4_MASK)
+
+#define COHER_DEST_BASE_4(dest_base_4) \
+     ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT))
+
+#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \
+     ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \
+     coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+     } coher_dest_base_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_4_t f;
+} coher_dest_base_4_u;
+
+
+/*
+ * COHER_DEST_BASE_5 struct
+ */
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000
+
+#define COHER_DEST_BASE_5_MASK \
+     (COHER_DEST_BASE_5_DEST_BASE_5_MASK)
+
+#define COHER_DEST_BASE_5(dest_base_5) \
+     ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT))
+
+#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \
+     ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \
+     coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+     } coher_dest_base_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_5_t f;
+} coher_dest_base_5_u;
+
+
+/*
+ * COHER_DEST_BASE_6 struct
+ */
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000
+
+#define COHER_DEST_BASE_6_MASK \
+     (COHER_DEST_BASE_6_DEST_BASE_6_MASK)
+
+#define COHER_DEST_BASE_6(dest_base_6) \
+     ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT))
+
+#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \
+     ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \
+     coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+     } coher_dest_base_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_6_t f;
+} coher_dest_base_6_u;
+
+
+/*
+ * COHER_DEST_BASE_7 struct
+ */
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000
+
+#define COHER_DEST_BASE_7_MASK \
+     (COHER_DEST_BASE_7_DEST_BASE_7_MASK)
+
+#define COHER_DEST_BASE_7(dest_base_7) \
+     ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT))
+
+#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \
+     ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \
+     coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+     } coher_dest_base_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_7_t f;
+} coher_dest_base_7_u;
+
+
+#endif
+
+
+#if !defined (_RBBM_FIDDLE_H)
+#define _RBBM_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * WAIT_UNTIL struct
+ */
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_VSYNC_SIZE     1
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1
+#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2
+#define WAIT_UNTIL_WAIT_VSYNC_SHIFT    3
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6
+#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT  10
+#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT  14
+#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT  15
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK  0x00000002
+#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK  0x00000004
+#define WAIT_UNTIL_WAIT_VSYNC_MASK     0x00000008
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040
+#define WAIT_UNTIL_WAIT_CMDFIFO_MASK   0x00000400
+#define WAIT_UNTIL_WAIT_2D_IDLE_MASK   0x00004000
+#define WAIT_UNTIL_WAIT_3D_IDLE_MASK   0x00008000
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000
+
+#define WAIT_UNTIL_MASK \
+     (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \
+      WAIT_UNTIL_WAIT_CMDFIFO_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_CMDFIFO_ENTRIES_MASK)
+
+#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \
+     ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \
+      (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \
+      (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \
+      (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \
+      (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \
+      (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \
+      (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \
+      (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \
+      (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \
+      (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \
+      (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \
+      (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT))
+
+#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \
+     ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 1;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int                                : 2;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 8;
+     } wait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 8;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int                                : 1;
+     } wait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+
+/*
+ * RBBM_ISYNC_CNTL struct
+ */
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020
+
+#define RBBM_ISYNC_CNTL_MASK \
+     (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \
+      RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK)
+
+#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \
+     ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \
+      (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT))
+
+#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 4;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int                                : 26;
+     } rbbm_isync_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 26;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int                                : 4;
+     } rbbm_isync_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_isync_cntl_t f;
+} rbbm_isync_cntl_u;
+
+
+/*
+ * RBBM_STATUS struct
+ */
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5
+#define RBBM_STATUS_TC_BUSY_SIZE       1
+#define RBBM_STATUS_HIRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CPRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_PFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1
+#define RBBM_STATUS_RBBM_WU_BUSY_SIZE  1
+#define RBBM_STATUS_CP_NRT_BUSY_SIZE   1
+#define RBBM_STATUS_MH_BUSY_SIZE       1
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1
+#define RBBM_STATUS_SX_BUSY_SIZE       1
+#define RBBM_STATUS_TPC_BUSY_SIZE      1
+#define RBBM_STATUS_SC_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_PA_BUSY_SIZE       1
+#define RBBM_STATUS_VGT_BUSY_SIZE      1
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1
+#define RBBM_STATUS_RB_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_GUI_ACTIVE_SIZE    1
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0
+#define RBBM_STATUS_TC_BUSY_SHIFT      5
+#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8
+#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9
+#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10
+#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12
+#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14
+#define RBBM_STATUS_CP_NRT_BUSY_SHIFT  16
+#define RBBM_STATUS_MH_BUSY_SHIFT      18
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19
+#define RBBM_STATUS_SX_BUSY_SHIFT      21
+#define RBBM_STATUS_TPC_BUSY_SHIFT     22
+#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24
+#define RBBM_STATUS_PA_BUSY_SHIFT      25
+#define RBBM_STATUS_VGT_BUSY_SHIFT     26
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28
+#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30
+#define RBBM_STATUS_GUI_ACTIVE_SHIFT   31
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f
+#define RBBM_STATUS_TC_BUSY_MASK       0x00000020
+#define RBBM_STATUS_HIRQ_PENDING_MASK  0x00000100
+#define RBBM_STATUS_CPRQ_PENDING_MASK  0x00000200
+#define RBBM_STATUS_CFRQ_PENDING_MASK  0x00000400
+#define RBBM_STATUS_PFRQ_PENDING_MASK  0x00000800
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000
+#define RBBM_STATUS_RBBM_WU_BUSY_MASK  0x00004000
+#define RBBM_STATUS_CP_NRT_BUSY_MASK   0x00010000
+#define RBBM_STATUS_MH_BUSY_MASK       0x00040000
+#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000
+#define RBBM_STATUS_SX_BUSY_MASK       0x00200000
+#define RBBM_STATUS_TPC_BUSY_MASK      0x00400000
+#define RBBM_STATUS_SC_CNTX_BUSY_MASK  0x01000000
+#define RBBM_STATUS_PA_BUSY_MASK       0x02000000
+#define RBBM_STATUS_VGT_BUSY_MASK      0x04000000
+#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000
+#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000
+#define RBBM_STATUS_RB_CNTX_BUSY_MASK  0x40000000
+#define RBBM_STATUS_GUI_ACTIVE_MASK    0x80000000
+
+#define RBBM_STATUS_MASK \
+     (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \
+      RBBM_STATUS_TC_BUSY_MASK | \
+      RBBM_STATUS_HIRQ_PENDING_MASK | \
+      RBBM_STATUS_CPRQ_PENDING_MASK | \
+      RBBM_STATUS_CFRQ_PENDING_MASK | \
+      RBBM_STATUS_PFRQ_PENDING_MASK | \
+      RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \
+      RBBM_STATUS_RBBM_WU_BUSY_MASK | \
+      RBBM_STATUS_CP_NRT_BUSY_MASK | \
+      RBBM_STATUS_MH_BUSY_MASK | \
+      RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \
+      RBBM_STATUS_SX_BUSY_MASK | \
+      RBBM_STATUS_TPC_BUSY_MASK | \
+      RBBM_STATUS_SC_CNTX_BUSY_MASK | \
+      RBBM_STATUS_PA_BUSY_MASK | \
+      RBBM_STATUS_VGT_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \
+      RBBM_STATUS_RB_CNTX_BUSY_MASK | \
+      RBBM_STATUS_GUI_ACTIVE_MASK)
+
+#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \
+     ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \
+      (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \
+      (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \
+      (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \
+      (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \
+      (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \
+      (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \
+      (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \
+      (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \
+      (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \
+      (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \
+      (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \
+      (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \
+      (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \
+      (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \
+      (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \
+      (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \
+      (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \
+      (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \
+      (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT))
+
+#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+     } rbbm_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int                                : 2;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+     } rbbm_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+
+/*
+ * RBBM_DSPLY struct
+ */
+
+#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE 1
+#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE 1
+#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE 1
+#define RBBM_DSPLY_VSYNC_ACTIVE_SIZE   1
+#define RBBM_DSPLY_USE_DISPLAY_ID0_SIZE 1
+#define RBBM_DSPLY_USE_DISPLAY_ID1_SIZE 1
+#define RBBM_DSPLY_USE_DISPLAY_ID2_SIZE 1
+#define RBBM_DSPLY_SW_CNTL_SIZE        1
+#define RBBM_DSPLY_NUM_BUFS_SIZE       2
+
+#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT 0
+#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT 1
+#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT 2
+#define RBBM_DSPLY_VSYNC_ACTIVE_SHIFT  3
+#define RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT 4
+#define RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT 5
+#define RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT 6
+#define RBBM_DSPLY_SW_CNTL_SHIFT       7
+#define RBBM_DSPLY_NUM_BUFS_SHIFT      8
+
+#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK 0x00000001
+#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK 0x00000002
+#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK 0x00000004
+#define RBBM_DSPLY_VSYNC_ACTIVE_MASK   0x00000008
+#define RBBM_DSPLY_USE_DISPLAY_ID0_MASK 0x00000010
+#define RBBM_DSPLY_USE_DISPLAY_ID1_MASK 0x00000020
+#define RBBM_DSPLY_USE_DISPLAY_ID2_MASK 0x00000040
+#define RBBM_DSPLY_SW_CNTL_MASK        0x00000080
+#define RBBM_DSPLY_NUM_BUFS_MASK       0x00000300
+
+#define RBBM_DSPLY_MASK \
+     (RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK | \
+      RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK | \
+      RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK | \
+      RBBM_DSPLY_VSYNC_ACTIVE_MASK | \
+      RBBM_DSPLY_USE_DISPLAY_ID0_MASK | \
+      RBBM_DSPLY_USE_DISPLAY_ID1_MASK | \
+      RBBM_DSPLY_USE_DISPLAY_ID2_MASK | \
+      RBBM_DSPLY_SW_CNTL_MASK | \
+      RBBM_DSPLY_NUM_BUFS_MASK)
+
+#define RBBM_DSPLY(display_id0_active, display_id1_active, display_id2_active, vsync_active, use_display_id0, use_display_id1, use_display_id2, sw_cntl, num_bufs) \
+     ((display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) | \
+      (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) | \
+      (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) | \
+      (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) | \
+      (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) | \
+      (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) | \
+      (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) | \
+      (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT) | \
+      (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT))
+
+#define RBBM_DSPLY_GET_DISPLAY_ID0_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_DISPLAY_ID1_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_DISPLAY_ID2_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_VSYNC_ACTIVE(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_VSYNC_ACTIVE_MASK) >> RBBM_DSPLY_VSYNC_ACTIVE_SHIFT)
+#define RBBM_DSPLY_GET_USE_DISPLAY_ID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID0_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT)
+#define RBBM_DSPLY_GET_USE_DISPLAY_ID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID1_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT)
+#define RBBM_DSPLY_GET_USE_DISPLAY_ID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID2_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT)
+#define RBBM_DSPLY_GET_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SW_CNTL_MASK) >> RBBM_DSPLY_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_NUM_BUFS_MASK) >> RBBM_DSPLY_NUM_BUFS_SHIFT)
+
+#define RBBM_DSPLY_SET_DISPLAY_ID0_ACTIVE(rbbm_dsply_reg, display_id0_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) | (display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_DISPLAY_ID1_ACTIVE(rbbm_dsply_reg, display_id1_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) | (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_DISPLAY_ID2_ACTIVE(rbbm_dsply_reg, display_id2_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) | (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_VSYNC_ACTIVE(rbbm_dsply_reg, vsync_active) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_VSYNC_ACTIVE_MASK) | (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT)
+#define RBBM_DSPLY_SET_USE_DISPLAY_ID0(rbbm_dsply_reg, use_display_id0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID0_MASK) | (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT)
+#define RBBM_DSPLY_SET_USE_DISPLAY_ID1(rbbm_dsply_reg, use_display_id1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID1_MASK) | (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT)
+#define RBBM_DSPLY_SET_USE_DISPLAY_ID2(rbbm_dsply_reg, use_display_id2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID2_MASK) | (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT)
+#define RBBM_DSPLY_SET_SW_CNTL(rbbm_dsply_reg, sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SW_CNTL_MASK) | (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_NUM_BUFS(rbbm_dsply_reg, num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_NUM_BUFS_MASK) | (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int display_id0_active             : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE;
+          unsigned int display_id1_active             : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE;
+          unsigned int display_id2_active             : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE;
+          unsigned int vsync_active                   : RBBM_DSPLY_VSYNC_ACTIVE_SIZE;
+          unsigned int use_display_id0                : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE;
+          unsigned int use_display_id1                : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE;
+          unsigned int use_display_id2                : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE;
+          unsigned int sw_cntl                        : RBBM_DSPLY_SW_CNTL_SIZE;
+          unsigned int num_bufs                       : RBBM_DSPLY_NUM_BUFS_SIZE;
+          unsigned int                                : 22;
+     } rbbm_dsply_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int                                : 22;
+          unsigned int num_bufs                       : RBBM_DSPLY_NUM_BUFS_SIZE;
+          unsigned int sw_cntl                        : RBBM_DSPLY_SW_CNTL_SIZE;
+          unsigned int use_display_id2                : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE;
+          unsigned int use_display_id1                : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE;
+          unsigned int use_display_id0                : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE;
+          unsigned int vsync_active                   : RBBM_DSPLY_VSYNC_ACTIVE_SIZE;
+          unsigned int display_id2_active             : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE;
+          unsigned int display_id1_active             : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE;
+          unsigned int display_id0_active             : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE;
+     } rbbm_dsply_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_dsply_t f;
+} rbbm_dsply_u;
+
+
+/*
+ * RBBM_RENDER_LATEST struct
+ */
+
+#define RBBM_RENDER_LATEST_BUFFER_ID_SIZE 2
+
+#define RBBM_RENDER_LATEST_BUFFER_ID_SHIFT 0
+
+#define RBBM_RENDER_LATEST_BUFFER_ID_MASK 0x00000003
+
+#define RBBM_RENDER_LATEST_MASK \
+     (RBBM_RENDER_LATEST_BUFFER_ID_MASK)
+
+#define RBBM_RENDER_LATEST(buffer_id) \
+     ((buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT))
+
+#define RBBM_RENDER_LATEST_GET_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_BUFFER_ID_SHIFT)
+
+#define RBBM_RENDER_LATEST_SET_BUFFER_ID(rbbm_render_latest_reg, buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_BUFFER_ID_MASK) | (buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int buffer_id                      : RBBM_RENDER_LATEST_BUFFER_ID_SIZE;
+          unsigned int                                : 30;
+     } rbbm_render_latest_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int                                : 30;
+          unsigned int buffer_id                      : RBBM_RENDER_LATEST_BUFFER_ID_SIZE;
+     } rbbm_render_latest_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_render_latest_t f;
+} rbbm_render_latest_u;
+
+
+/*
+ * RBBM_RTL_RELEASE struct
+ */
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0
+
+#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff
+
+#define RBBM_RTL_RELEASE_MASK \
+     (RBBM_RTL_RELEASE_CHANGELIST_MASK)
+
+#define RBBM_RTL_RELEASE(changelist) \
+     ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT))
+
+#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \
+     ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \
+     rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_rtl_release_t f;
+} rbbm_rtl_release_u;
+
+
+/*
+ * RBBM_PATCH_RELEASE struct
+ */
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000
+
+#define RBBM_PATCH_RELEASE_MASK \
+     (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \
+      RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \
+      RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK)
+
+#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \
+     ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \
+      (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \
+      (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT))
+
+#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+     } rbbm_patch_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+     } rbbm_patch_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_patch_release_t f;
+} rbbm_patch_release_u;
+
+
+/*
+ * RBBM_AUXILIARY_CONFIG struct
+ */
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff
+
+#define RBBM_AUXILIARY_CONFIG_MASK \
+     (RBBM_AUXILIARY_CONFIG_RESERVED_MASK)
+
+#define RBBM_AUXILIARY_CONFIG(reserved) \
+     ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT))
+
+#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \
+     ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \
+     rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_auxiliary_config_t f;
+} rbbm_auxiliary_config_u;
+
+
+/*
+ * RBBM_PERIPHID0 struct
+ */
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0
+
+#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff
+
+#define RBBM_PERIPHID0_MASK \
+     (RBBM_PERIPHID0_PARTNUMBER0_MASK)
+
+#define RBBM_PERIPHID0(partnumber0) \
+     ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT))
+
+#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \
+     ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \
+     rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int                                : 24;
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+     } rbbm_periphid0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid0_t f;
+} rbbm_periphid0_u;
+
+
+/*
+ * RBBM_PERIPHID1 struct
+ */
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4
+#define RBBM_PERIPHID1_DESIGNER0_SIZE  4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0
+#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f
+#define RBBM_PERIPHID1_DESIGNER0_MASK  0x000000f0
+
+#define RBBM_PERIPHID1_MASK \
+     (RBBM_PERIPHID1_PARTNUMBER1_MASK | \
+      RBBM_PERIPHID1_DESIGNER0_MASK)
+
+#define RBBM_PERIPHID1(partnumber1, designer0) \
+     ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \
+      (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT))
+
+#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int                                : 24;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+     } rbbm_periphid1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid1_t f;
+} rbbm_periphid1_u;
+
+
+/*
+ * RBBM_PERIPHID2 struct
+ */
+
+#define RBBM_PERIPHID2_DESIGNER1_SIZE  4
+#define RBBM_PERIPHID2_REVISION_SIZE   4
+
+#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0
+#define RBBM_PERIPHID2_REVISION_SHIFT  4
+
+#define RBBM_PERIPHID2_DESIGNER1_MASK  0x0000000f
+#define RBBM_PERIPHID2_REVISION_MASK   0x000000f0
+
+#define RBBM_PERIPHID2_MASK \
+     (RBBM_PERIPHID2_DESIGNER1_MASK | \
+      RBBM_PERIPHID2_REVISION_MASK)
+
+#define RBBM_PERIPHID2(designer1, revision) \
+     ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \
+      (revision << RBBM_PERIPHID2_REVISION_SHIFT))
+
+#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT)
+
+#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int                                : 24;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+     } rbbm_periphid2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid2_t f;
+} rbbm_periphid2_u;
+
+
+/*
+ * RBBM_PERIPHID3 struct
+ */
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_CONTINUATION_SIZE 1
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4
+#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c
+#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030
+#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080
+
+#define RBBM_PERIPHID3_MASK \
+     (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \
+      RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \
+      RBBM_PERIPHID3_MH_INTERFACE_MASK | \
+      RBBM_PERIPHID3_CONTINUATION_MASK)
+
+#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \
+     ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \
+      (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \
+      (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \
+      (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT))
+
+#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int                                : 1;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int                                : 24;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+     } rbbm_periphid3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid3_t f;
+} rbbm_periphid3_u;
+
+
+/*
+ * RBBM_CNTL struct
+ */
+
+#define RBBM_CNTL_READ_TIMEOUT_SIZE    8
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9
+
+#define RBBM_CNTL_READ_TIMEOUT_SHIFT   0
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8
+
+#define RBBM_CNTL_READ_TIMEOUT_MASK    0x000000ff
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00
+
+#define RBBM_CNTL_MASK \
+     (RBBM_CNTL_READ_TIMEOUT_MASK | \
+      RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK)
+
+#define RBBM_CNTL(read_timeout, regclk_deassert_time) \
+     ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \
+      (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT))
+
+#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int                                : 15;
+     } rbbm_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int                                : 15;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+     } rbbm_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+
+/*
+ * RBBM_SKEW_CNTL struct
+ */
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f
+#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0
+
+#define RBBM_SKEW_CNTL_MASK \
+     (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \
+      RBBM_SKEW_CNTL_SKEW_COUNT_MASK)
+
+#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \
+     ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \
+      (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT))
+
+#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int                                : 22;
+     } rbbm_skew_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int                                : 22;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+     } rbbm_skew_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_skew_cntl_t f;
+} rbbm_skew_cntl_u;
+
+
+/*
+ * RBBM_SOFT_RESET struct
+ */
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000
+
+#define RBBM_SOFT_RESET_MASK \
+     (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK)
+
+#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \
+     ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \
+      (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \
+      (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \
+      (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \
+      (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \
+      (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \
+      (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \
+      (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \
+      (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT))
+
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int                                : 15;
+     } rbbm_soft_reset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int                                : 15;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+     } rbbm_soft_reset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE1 struct
+ */
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000
+
+#define RBBM_PM_OVERRIDE1_MASK \
+     (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \
+     ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override1_t f;
+} rbbm_pm_override1_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE2 struct
+ */
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800
+
+#define RBBM_PM_OVERRIDE2_MASK \
+     (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \
+     ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \
+      (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \
+      (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int                                : 20;
+     } rbbm_pm_override2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int                                : 20;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override2_t f;
+} rbbm_pm_override2_u;
+
+
+/*
+ * GC_SYS_IDLE struct
+ */
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000
+
+#define GC_SYS_IDLE_MASK \
+     (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \
+      GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK)
+
+#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_idle_override) \
+     ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \
+      (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT))
+
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+          unsigned int                                : 15;
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+     } gc_sys_idle_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+          unsigned int                                : 15;
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+     } gc_sys_idle_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gc_sys_idle_t f;
+} gc_sys_idle_u;
+
+
+/*
+ * NQWAIT_UNTIL struct
+ */
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001
+
+#define NQWAIT_UNTIL_MASK \
+     (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK)
+
+#define NQWAIT_UNTIL(wait_gui_idle) \
+     ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT))
+
+#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \
+     ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \
+     nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+          unsigned int                                : 31;
+     } nqwait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int                                : 31;
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+     } nqwait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+
+/*
+ * RBBM_DEBUG struct
+ */
+
+#define RBBM_DEBUG_IGNORE_RTR_SIZE     1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1
+
+#define RBBM_DEBUG_IGNORE_RTR_SHIFT    1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31
+
+#define RBBM_DEBUG_IGNORE_RTR_MASK     0x00000002
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000
+
+#define RBBM_DEBUG_MASK \
+     (RBBM_DEBUG_IGNORE_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \
+      RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \
+      RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK)
+
+#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \
+     ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \
+      (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \
+      (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \
+      (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \
+      (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \
+      (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \
+      (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \
+      (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \
+      (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \
+      (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \
+      (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \
+      (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT))
+
+#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int                                : 1;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int                                : 3;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 4;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+     } rbbm_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+          unsigned int                                : 6;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int                                : 4;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 3;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int                                : 1;
+     } rbbm_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+
+/*
+ * RBBM_READ_ERROR struct
+ */
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
+#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
+#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2
+#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30
+#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31
+
+#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000
+#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000
+
+#define RBBM_READ_ERROR_MASK \
+     (RBBM_READ_ERROR_READ_ADDRESS_MASK | \
+      RBBM_READ_ERROR_READ_REQUESTER_MASK | \
+      RBBM_READ_ERROR_READ_ERROR_MASK)
+
+#define RBBM_READ_ERROR(read_address, read_requester, read_error) \
+     ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \
+      (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \
+      (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT))
+
+#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int                                : 2;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+     } rbbm_read_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 2;
+     } rbbm_read_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_read_error_t f;
+} rbbm_read_error_u;
+
+
+/*
+ * RBBM_WAIT_IDLE_CLOCKS struct
+ */
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff
+
+#define RBBM_WAIT_IDLE_CLOCKS_MASK \
+     (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK)
+
+#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \
+     ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT))
+
+#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \
+     ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \
+     rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+          unsigned int                                : 24;
+     } rbbm_wait_idle_clocks_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int                                : 24;
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+     } rbbm_wait_idle_clocks_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_wait_idle_clocks_t f;
+} rbbm_wait_idle_clocks_u;
+
+
+/*
+ * RBBM_INT_CNTL struct
+ */
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000
+
+#define RBBM_INT_CNTL_MASK \
+     (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \
+      RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \
+      RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK)
+
+#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \
+     ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \
+      (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \
+      (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT))
+
+#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+     } rbbm_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_cntl_t f;
+} rbbm_int_cntl_u;
+
+
+/*
+ * RBBM_INT_STATUS struct
+ */
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000
+
+#define RBBM_INT_STATUS_MASK \
+     (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \
+      RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \
+      RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK)
+
+#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \
+     ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \
+      (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \
+      (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT))
+
+#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+     } rbbm_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_status_t f;
+} rbbm_int_status_u;
+
+
+/*
+ * RBBM_INT_ACK struct
+ */
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000
+
+#define RBBM_INT_ACK_MASK \
+     (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \
+      RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \
+      RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK)
+
+#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \
+     ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \
+      (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \
+      (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT))
+
+#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+     } rbbm_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_ack_t f;
+} rbbm_int_ack_u;
+
+
+/*
+ * MASTER_INT_SIGNAL struct
+ */
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020
+#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000
+
+#define MASTER_INT_SIGNAL_MASK \
+     (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK)
+
+#define MASTER_INT_SIGNAL(mh_int_stat, cp_int_stat, rbbm_int_stat) \
+     ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \
+      (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \
+      (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT))
+
+#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int                                : 5;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 24;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+     } master_int_signal_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int                                : 24;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 5;
+     } master_int_signal_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     master_int_signal_t f;
+} master_int_signal_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_SELECT struct
+ */
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f
+
+#define RBBM_PERFCOUNTER1_SELECT_MASK \
+     (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK)
+
+#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \
+     ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT))
+
+#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \
+     ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \
+     rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+          unsigned int                                : 26;
+     } rbbm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int                                : 26;
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+     } rbbm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_select_t f;
+} rbbm_perfcounter1_select_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_LO struct
+ */
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff
+
+#define RBBM_PERFCOUNTER1_LO_MASK \
+     (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK)
+
+#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \
+     ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT))
+
+#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \
+     ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \
+     rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_lo_t f;
+} rbbm_perfcounter1_lo_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_HI struct
+ */
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff
+
+#define RBBM_PERFCOUNTER1_HI_MASK \
+     (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK)
+
+#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \
+     ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT))
+
+#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \
+     ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \
+     rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+          unsigned int                                : 16;
+     } rbbm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+     } rbbm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_hi_t f;
+} rbbm_perfcounter1_hi_u;
+
+
+#endif
+
+
+#if !defined (_MH_FIDDLE_H)
+#define _MH_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * MH_ARBITER_CONFIG struct
+ */
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200
+#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000
+
+#define MH_ARBITER_CONFIG_MASK \
+     (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \
+      MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \
+      MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK)
+
+#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable) \
+     ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \
+      (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \
+      (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \
+      (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \
+      (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \
+      (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \
+      (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \
+      (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \
+      (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \
+      (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \
+      (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \
+      (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \
+      (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT))
+
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int                                : 6;
+     } mh_arbiter_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int                                : 6;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+     } mh_arbiter_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_arbiter_config_t f;
+} mh_arbiter_config_u;
+
+
+/*
+ * MH_CLNT_AXI_ID_REUSE struct
+ */
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700
+
+#define MH_CLNT_AXI_ID_REUSE_MASK \
+     (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \
+      MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id) \
+     ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \
+      (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \
+      (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \
+      (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \
+      (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 21;
+     } mh_clnt_axi_id_reuse_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int                                : 21;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+     } mh_clnt_axi_id_reuse_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_clnt_axi_id_reuse_t f;
+} mh_clnt_axi_id_reuse_u;
+
+
+/*
+ * MH_INTERRUPT_MASK struct
+ */
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_MASK_MASK \
+     (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_mask_t f;
+} mh_interrupt_mask_u;
+
+
+/*
+ * MH_INTERRUPT_STATUS struct
+ */
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_STATUS_MASK \
+     (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_status_t f;
+} mh_interrupt_status_u;
+
+
+/*
+ * MH_INTERRUPT_CLEAR struct
+ */
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_CLEAR_MASK \
+     (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_clear_t f;
+} mh_interrupt_clear_u;
+
+
+/*
+ * MH_AXI_ERROR struct
+ */
+
+#define MH_AXI_ERROR_AXI_READ_ID_SIZE  3
+#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1
+#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1
+
+#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3
+#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7
+
+#define MH_AXI_ERROR_AXI_READ_ID_MASK  0x00000007
+#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008
+#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080
+
+#define MH_AXI_ERROR_MASK \
+     (MH_AXI_ERROR_AXI_READ_ID_MASK | \
+      MH_AXI_ERROR_AXI_READ_ERROR_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ID_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ERROR_MASK)
+
+#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \
+     ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \
+      (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \
+      (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT))
+
+#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int                                : 24;
+     } mh_axi_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int                                : 24;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+     } mh_axi_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_error_t f;
+} mh_axi_error_u;
+
+
+/*
+ * MH_PERFCOUNTER0_SELECT struct
+ */
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_SELECT_MASK \
+     (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \
+     ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \
+     mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_select_t f;
+} mh_perfcounter0_select_u;
+
+
+/*
+ * MH_PERFCOUNTER1_SELECT struct
+ */
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_SELECT_MASK \
+     (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \
+     ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \
+     mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_select_t f;
+} mh_perfcounter1_select_u;
+
+
+/*
+ * MH_PERFCOUNTER0_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_CONFIG_MASK \
+     (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER0_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \
+     ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \
+     mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter0_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_config_t f;
+} mh_perfcounter0_config_u;
+
+
+/*
+ * MH_PERFCOUNTER1_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_CONFIG_MASK \
+     (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER1_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \
+     ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \
+     mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter1_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_config_t f;
+} mh_perfcounter1_config_u;
+
+
+/*
+ * MH_PERFCOUNTER0_LOW struct
+ */
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER0_LOW_MASK \
+     (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER0_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \
+     ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \
+     mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_low_t f;
+} mh_perfcounter0_low_u;
+
+
+/*
+ * MH_PERFCOUNTER1_LOW struct
+ */
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER1_LOW_MASK \
+     (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER1_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \
+     ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \
+     mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_low_t f;
+} mh_perfcounter1_low_u;
+
+
+/*
+ * MH_PERFCOUNTER0_HI struct
+ */
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER0_HI_MASK \
+     (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER0_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \
+     ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \
+     mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_hi_t f;
+} mh_perfcounter0_hi_u;
+
+
+/*
+ * MH_PERFCOUNTER1_HI struct
+ */
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER1_HI_MASK \
+     (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER1_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \
+     ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \
+     mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_hi_t f;
+} mh_perfcounter1_hi_u;
+
+
+/*
+ * MH_DEBUG_CTRL struct
+ */
+
+#define MH_DEBUG_CTRL_INDEX_SIZE       6
+
+#define MH_DEBUG_CTRL_INDEX_SHIFT      0
+
+#define MH_DEBUG_CTRL_INDEX_MASK       0x0000003f
+
+#define MH_DEBUG_CTRL_MASK \
+     (MH_DEBUG_CTRL_INDEX_MASK)
+
+#define MH_DEBUG_CTRL(index) \
+     ((index << MH_DEBUG_CTRL_INDEX_SHIFT))
+
+#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \
+     ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \
+     mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+          unsigned int                                : 26;
+     } mh_debug_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int                                : 26;
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+     } mh_debug_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_ctrl_t f;
+} mh_debug_ctrl_u;
+
+
+/*
+ * MH_DEBUG_DATA struct
+ */
+
+#define MH_DEBUG_DATA_DATA_SIZE        32
+
+#define MH_DEBUG_DATA_DATA_SHIFT       0
+
+#define MH_DEBUG_DATA_DATA_MASK        0xffffffff
+
+#define MH_DEBUG_DATA_MASK \
+     (MH_DEBUG_DATA_DATA_MASK)
+
+#define MH_DEBUG_DATA(data) \
+     ((data << MH_DEBUG_DATA_DATA_SHIFT))
+
+#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \
+     ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT)
+
+#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \
+     mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_data_t f;
+} mh_debug_data_u;
+
+
+/*
+ * MH_DEBUG_REG00 struct
+ */
+
+#define MH_DEBUG_REG00_MH_BUSY_SIZE    1
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1
+#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1
+#define MH_DEBUG_REG00_TCD_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_TCD_FULL_SIZE   1
+#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1
+#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_ARQ_FULL_SIZE   1
+#define MH_DEBUG_REG00_WDB_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_WDB_FULL_SIZE   1
+#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1
+
+#define MH_DEBUG_REG00_MH_BUSY_SHIFT   0
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1
+#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2
+#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3
+#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5
+#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6
+#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7
+#define MH_DEBUG_REG00_TCD_FULL_SHIFT  8
+#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 10
+#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 11
+#define MH_DEBUG_REG00_ARQ_FULL_SHIFT  12
+#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 13
+#define MH_DEBUG_REG00_WDB_FULL_SHIFT  14
+#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 15
+#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 16
+#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 17
+#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 18
+#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 19
+#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 20
+#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 21
+#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 22
+#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 23
+#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 24
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 25
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 26
+
+#define MH_DEBUG_REG00_MH_BUSY_MASK    0x00000001
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002
+#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004
+#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008
+#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020
+#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040
+#define MH_DEBUG_REG00_TCD_EMPTY_MASK  0x00000080
+#define MH_DEBUG_REG00_TCD_FULL_MASK   0x00000100
+#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000400
+#define MH_DEBUG_REG00_ARQ_EMPTY_MASK  0x00000800
+#define MH_DEBUG_REG00_ARQ_FULL_MASK   0x00001000
+#define MH_DEBUG_REG00_WDB_EMPTY_MASK  0x00002000
+#define MH_DEBUG_REG00_WDB_FULL_MASK   0x00004000
+#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00008000
+#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00010000
+#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00020000
+#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00040000
+#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00080000
+#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00100000
+#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00200000
+#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00400000
+#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x00800000
+#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x01000000
+#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x02000000
+#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x04000000
+
+#define MH_DEBUG_REG00_MASK \
+     (MH_DEBUG_REG00_MH_BUSY_MASK | \
+      MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \
+      MH_DEBUG_REG00_CP_REQUEST_MASK | \
+      MH_DEBUG_REG00_VGT_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \
+      MH_DEBUG_REG00_TC_CAM_FULL_MASK | \
+      MH_DEBUG_REG00_TCD_EMPTY_MASK | \
+      MH_DEBUG_REG00_TCD_FULL_MASK | \
+      MH_DEBUG_REG00_RB_REQUEST_MASK | \
+      MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \
+      MH_DEBUG_REG00_ARQ_EMPTY_MASK | \
+      MH_DEBUG_REG00_ARQ_FULL_MASK | \
+      MH_DEBUG_REG00_WDB_EMPTY_MASK | \
+      MH_DEBUG_REG00_WDB_FULL_MASK | \
+      MH_DEBUG_REG00_AXI_AVALID_MASK | \
+      MH_DEBUG_REG00_AXI_AREADY_MASK | \
+      MH_DEBUG_REG00_AXI_ARVALID_MASK | \
+      MH_DEBUG_REG00_AXI_ARREADY_MASK | \
+      MH_DEBUG_REG00_AXI_WVALID_MASK | \
+      MH_DEBUG_REG00_AXI_WREADY_MASK | \
+      MH_DEBUG_REG00_AXI_RVALID_MASK | \
+      MH_DEBUG_REG00_AXI_RREADY_MASK | \
+      MH_DEBUG_REG00_AXI_BVALID_MASK | \
+      MH_DEBUG_REG00_AXI_BREADY_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_ACK_MASK)
+
+#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack) \
+     ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \
+      (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \
+      (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \
+      (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \
+      (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \
+      (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \
+      (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \
+      (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \
+      (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \
+      (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \
+      (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \
+      (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \
+      (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \
+      (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \
+      (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \
+      (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \
+      (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \
+      (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \
+      (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \
+      (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \
+      (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \
+      (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \
+      (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \
+      (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \
+      (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \
+      (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \
+      (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT))
+
+#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+
+#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int                                : 5;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+     } mh_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg00_t f;
+} mh_debug_reg00_u;
+
+
+/*
+ * MH_DEBUG_REG01 struct
+ */
+
+#define MH_DEBUG_REG01_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1
+#define MH_DEBUG_REG01_CP_TAG_q_SIZE   3
+#define MH_DEBUG_REG01_CP_BE_q_SIZE    8
+#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_TAG_q_SIZE  1
+#define MH_DEBUG_REG01_TC_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_TC_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG01_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG01_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_RB_BE_q_SIZE    8
+
+#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0
+#define MH_DEBUG_REG01_CP_RTR_q_SHIFT  1
+#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2
+#define MH_DEBUG_REG01_CP_TAG_q_SHIFT  3
+#define MH_DEBUG_REG01_CP_BE_q_SHIFT   6
+#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 14
+#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 15
+#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 16
+#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 17
+#define MH_DEBUG_REG01_TC_RTR_q_SHIFT  18
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 19
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 20
+#define MH_DEBUG_REG01_TC_MH_written_SHIFT 21
+#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 22
+#define MH_DEBUG_REG01_RB_RTR_q_SHIFT  23
+#define MH_DEBUG_REG01_RB_BE_q_SHIFT   24
+
+#define MH_DEBUG_REG01_CP_SEND_q_MASK  0x00000001
+#define MH_DEBUG_REG01_CP_RTR_q_MASK   0x00000002
+#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004
+#define MH_DEBUG_REG01_CP_TAG_q_MASK   0x00000038
+#define MH_DEBUG_REG01_CP_BE_q_MASK    0x00003fc0
+#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00004000
+#define MH_DEBUG_REG01_VGT_RTR_q_MASK  0x00008000
+#define MH_DEBUG_REG01_VGT_TAG_q_MASK  0x00010000
+#define MH_DEBUG_REG01_TC_SEND_q_MASK  0x00020000
+#define MH_DEBUG_REG01_TC_RTR_q_MASK   0x00040000
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00080000
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00100000
+#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00200000
+#define MH_DEBUG_REG01_RB_SEND_q_MASK  0x00400000
+#define MH_DEBUG_REG01_RB_RTR_q_MASK   0x00800000
+#define MH_DEBUG_REG01_RB_BE_q_MASK    0xff000000
+
+#define MH_DEBUG_REG01_MASK \
+     (MH_DEBUG_REG01_CP_SEND_q_MASK | \
+      MH_DEBUG_REG01_CP_RTR_q_MASK | \
+      MH_DEBUG_REG01_CP_WRITE_q_MASK | \
+      MH_DEBUG_REG01_CP_TAG_q_MASK | \
+      MH_DEBUG_REG01_CP_BE_q_MASK | \
+      MH_DEBUG_REG01_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG01_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG01_VGT_TAG_q_MASK | \
+      MH_DEBUG_REG01_TC_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_MH_written_MASK | \
+      MH_DEBUG_REG01_RB_SEND_q_MASK | \
+      MH_DEBUG_REG01_RB_RTR_q_MASK | \
+      MH_DEBUG_REG01_RB_BE_q_MASK)
+
+#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_be_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, rb_be_q) \
+     ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \
+      (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \
+      (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \
+      (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \
+      (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \
+      (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \
+      (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \
+      (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT))
+
+#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_BE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BE_q_MASK) >> MH_DEBUG_REG01_CP_BE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_BE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_BE_q_MASK) >> MH_DEBUG_REG01_RB_BE_q_SHIFT)
+
+#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_BE_q(mh_debug_reg01_reg, cp_be_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BE_q_MASK) | (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_BE_q(mh_debug_reg01_reg, rb_be_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_BE_q_MASK) | (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_be_q                        : MH_DEBUG_REG01_CP_BE_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_be_q                        : MH_DEBUG_REG01_RB_BE_q_SIZE;
+     } mh_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int rb_be_q                        : MH_DEBUG_REG01_RB_BE_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int cp_be_q                        : MH_DEBUG_REG01_CP_BE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+     } mh_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg01_t f;
+} mh_debug_reg01_u;
+
+
+/*
+ * MH_DEBUG_REG02 struct
+ */
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3
+#define MH_DEBUG_REG02_RDC_RID_SIZE    3
+#define MH_DEBUG_REG02_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1
+#define MH_DEBUG_REG02_BRC_BID_SIZE    3
+#define MH_DEBUG_REG02_BRC_BRESP_SIZE  2
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3
+#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4
+#define MH_DEBUG_REG02_RDC_RID_SHIFT   7
+#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12
+#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13
+#define MH_DEBUG_REG02_BRC_BID_SHIFT   14
+#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 17
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008
+#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070
+#define MH_DEBUG_REG02_RDC_RID_MASK    0x00000380
+#define MH_DEBUG_REG02_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000
+#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000
+#define MH_DEBUG_REG02_BRC_BID_MASK    0x0001c000
+#define MH_DEBUG_REG02_BRC_BRESP_MASK  0x00060000
+
+#define MH_DEBUG_REG02_MASK \
+     (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_tag_MASK | \
+      MH_DEBUG_REG02_RDC_RID_MASK | \
+      MH_DEBUG_REG02_RDC_RRESP_MASK | \
+      MH_DEBUG_REG02_MH_CP_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_RB_writeclean_MASK | \
+      MH_DEBUG_REG02_BRC_BID_MASK | \
+      MH_DEBUG_REG02_BRC_BRESP_MASK)
+
+#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, brc_bid, brc_bresp) \
+     ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \
+      (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \
+      (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \
+      (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \
+      (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \
+      (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \
+      (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT))
+
+#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int                                : 13;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+     } mh_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg02_t f;
+} mh_debug_reg02_u;
+
+
+/*
+ * MH_DEBUG_REG03 struct
+ */
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG03_MASK \
+     (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK)
+
+#define MH_DEBUG_REG03(mh_clnt_data_31_0) \
+     ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \
+     ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \
+     mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg03_t f;
+} mh_debug_reg03_u;
+
+
+/*
+ * MH_DEBUG_REG04 struct
+ */
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG04_MASK \
+     (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK)
+
+#define MH_DEBUG_REG04(mh_clnt_data_63_32) \
+     ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \
+     ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \
+     mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg04_t f;
+} mh_debug_reg04_u;
+
+
+/*
+ * MH_DEBUG_REG05 struct
+ */
+
+#define MH_DEBUG_REG05_CP_MH_send_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_tag_SIZE  3
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0
+#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1
+#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002
+#define MH_DEBUG_REG05_CP_MH_tag_MASK  0x0000001c
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG05_MASK \
+     (MH_DEBUG_REG05_CP_MH_send_MASK | \
+      MH_DEBUG_REG05_CP_MH_write_MASK | \
+      MH_DEBUG_REG05_CP_MH_tag_MASK | \
+      MH_DEBUG_REG05_CP_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \
+     ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \
+      (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \
+      (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+     } mh_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+     } mh_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg05_t f;
+} mh_debug_reg05_u;
+
+
+/*
+ * MH_DEBUG_REG06 struct
+ */
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG06_MASK \
+     (MH_DEBUG_REG06_CP_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG06(cp_mh_data_31_0) \
+     ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \
+     ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \
+     mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg06_t f;
+} mh_debug_reg06_u;
+
+
+/*
+ * MH_DEBUG_REG07 struct
+ */
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG07_MASK \
+     (MH_DEBUG_REG07_CP_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG07(cp_mh_data_63_32) \
+     ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \
+     ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \
+     mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg07_t f;
+} mh_debug_reg07_u;
+
+
+/*
+ * MH_DEBUG_REG08 struct
+ */
+
+#define MH_DEBUG_REG08_ALWAYS_ZERO_SIZE 3
+#define MH_DEBUG_REG08_VGT_MH_send_SIZE 1
+#define MH_DEBUG_REG08_VGT_MH_tagbe_SIZE 1
+#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG08_VGT_MH_send_SHIFT 3
+#define MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT 4
+#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG08_ALWAYS_ZERO_MASK 0x00000007
+#define MH_DEBUG_REG08_VGT_MH_send_MASK 0x00000008
+#define MH_DEBUG_REG08_VGT_MH_tagbe_MASK 0x00000010
+#define MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG08_MASK \
+     (MH_DEBUG_REG08_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG08_VGT_MH_send_MASK | \
+      MH_DEBUG_REG08_VGT_MH_tagbe_MASK | \
+      MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG08(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \
+     ((always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) | \
+      (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT) | \
+      (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) | \
+      (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG08_GET_ALWAYS_ZERO(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG08_GET_VGT_MH_send(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_send_MASK) >> MH_DEBUG_REG08_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG08_GET_VGT_MH_tagbe(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG08_GET_VGT_MH_ad_31_5(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG08_SET_ALWAYS_ZERO(mh_debug_reg08_reg, always_zero) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG08_SET_VGT_MH_send(mh_debug_reg08_reg, vgt_mh_send) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG08_SET_VGT_MH_tagbe(mh_debug_reg08_reg, vgt_mh_tagbe) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG08_SET_VGT_MH_ad_31_5(mh_debug_reg08_reg, vgt_mh_ad_31_5) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int always_zero                    : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG08_VGT_MH_send_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE;
+     } mh_debug_reg08_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG08_VGT_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg08_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg08_t f;
+} mh_debug_reg08_u;
+
+
+/*
+ * MH_DEBUG_REG09 struct
+ */
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG09_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG09_TC_MH_mask_SIZE 2
+#define MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG09_TC_MH_send_SHIFT 2
+#define MH_DEBUG_REG09_TC_MH_mask_SHIFT 3
+#define MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG09_TC_MH_send_MASK 0x00000004
+#define MH_DEBUG_REG09_TC_MH_mask_MASK 0x00000018
+#define MH_DEBUG_REG09_TC_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG09_MASK \
+     (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG09_TC_MH_send_MASK | \
+      MH_DEBUG_REG09_TC_MH_mask_MASK | \
+      MH_DEBUG_REG09_TC_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG09(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT) | \
+      (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT) | \
+      (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_GET_TC_MH_send(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_send_MASK) >> MH_DEBUG_REG09_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG09_GET_TC_MH_mask(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_mask_MASK) >> MH_DEBUG_REG09_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG09_GET_TC_MH_addr_31_5(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_SET_TC_MH_send(mh_debug_reg09_reg, tc_mh_send) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG09_SET_TC_MH_mask(mh_debug_reg09_reg, tc_mh_mask) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG09_SET_TC_MH_addr_31_5(mh_debug_reg09_reg, tc_mh_addr_31_5) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG09_TC_MH_send_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG09_TC_MH_mask_SIZE;
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE;
+     } mh_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG09_TC_MH_mask_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG09_TC_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg09_t f;
+} mh_debug_reg09_u;
+
+
+/*
+ * MH_DEBUG_REG10 struct
+ */
+
+#define MH_DEBUG_REG10_TC_MH_info_SIZE 25
+#define MH_DEBUG_REG10_TC_MH_send_SIZE 1
+
+#define MH_DEBUG_REG10_TC_MH_info_SHIFT 0
+#define MH_DEBUG_REG10_TC_MH_send_SHIFT 25
+
+#define MH_DEBUG_REG10_TC_MH_info_MASK 0x01ffffff
+#define MH_DEBUG_REG10_TC_MH_send_MASK 0x02000000
+
+#define MH_DEBUG_REG10_MASK \
+     (MH_DEBUG_REG10_TC_MH_info_MASK | \
+      MH_DEBUG_REG10_TC_MH_send_MASK)
+
+#define MH_DEBUG_REG10(tc_mh_info, tc_mh_send) \
+     ((tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT))
+
+#define MH_DEBUG_REG10_GET_TC_MH_info(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_info_MASK) >> MH_DEBUG_REG10_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT)
+
+#define MH_DEBUG_REG10_SET_TC_MH_info(mh_debug_reg10_reg, tc_mh_info) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int tc_mh_info                     : MH_DEBUG_REG10_TC_MH_info_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int                                : 6;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int tc_mh_info                     : MH_DEBUG_REG10_TC_MH_info_SIZE;
+     } mh_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg10_t f;
+} mh_debug_reg10_u;
+
+
+/*
+ * MH_DEBUG_REG11 struct
+ */
+
+#define MH_DEBUG_REG11_MH_TC_mcinfo_SIZE 25
+#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE 1
+#define MH_DEBUG_REG11_TC_MH_written_SIZE 1
+
+#define MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT 0
+#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT 25
+#define MH_DEBUG_REG11_TC_MH_written_SHIFT 26
+
+#define MH_DEBUG_REG11_MH_TC_mcinfo_MASK 0x01ffffff
+#define MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK 0x02000000
+#define MH_DEBUG_REG11_TC_MH_written_MASK 0x04000000
+
+#define MH_DEBUG_REG11_MASK \
+     (MH_DEBUG_REG11_MH_TC_mcinfo_MASK | \
+      MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK | \
+      MH_DEBUG_REG11_TC_MH_written_MASK)
+
+#define MH_DEBUG_REG11(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \
+     ((mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) | \
+      (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT))
+
+#define MH_DEBUG_REG11_GET_MH_TC_mcinfo(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG11_GET_MH_TC_mcinfo_send(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG11_GET_TC_MH_written(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_written_MASK) >> MH_DEBUG_REG11_TC_MH_written_SHIFT)
+
+#define MH_DEBUG_REG11_SET_MH_TC_mcinfo(mh_debug_reg11_reg, mh_tc_mcinfo) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG11_SET_MH_TC_mcinfo_send(mh_debug_reg11_reg, mh_tc_mcinfo_send) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG11_SET_TC_MH_written(mh_debug_reg11_reg, tc_mh_written) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG11_TC_MH_written_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int                                : 5;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG11_TC_MH_written_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE;
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE;
+     } mh_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg11_t f;
+} mh_debug_reg11_u;
+
+
+/*
+ * MH_DEBUG_REG12 struct
+ */
+
+#define MH_DEBUG_REG12_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG12_TC_ROQ_SEND_SIZE 1
+#define MH_DEBUG_REG12_TC_ROQ_MASK_SIZE 2
+#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE 27
+
+#define MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT 2
+#define MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT 3
+#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT 5
+
+#define MH_DEBUG_REG12_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG12_TC_ROQ_SEND_MASK 0x00000004
+#define MH_DEBUG_REG12_TC_ROQ_MASK_MASK 0x00000018
+#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG12_MASK \
+     (MH_DEBUG_REG12_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG12_TC_ROQ_SEND_MASK | \
+      MH_DEBUG_REG12_TC_ROQ_MASK_MASK | \
+      MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK)
+
+#define MH_DEBUG_REG12(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) | \
+      (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) | \
+      (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT))
+
+#define MH_DEBUG_REG12_GET_ALWAYS_ZERO(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_ROQ_SEND(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_ROQ_MASK(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_ROQ_ADDR_31_5(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT)
+
+#define MH_DEBUG_REG12_SET_ALWAYS_ZERO(mh_debug_reg12_reg, always_zero) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_ROQ_SEND(mh_debug_reg12_reg, tc_roq_send) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_ROQ_MASK(mh_debug_reg12_reg, tc_roq_mask) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_ROQ_ADDR_31_5(mh_debug_reg12_reg, tc_roq_addr_31_5) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int always_zero                    : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE;
+     } mh_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg12_t f;
+} mh_debug_reg12_u;
+
+
+/*
+ * MH_DEBUG_REG13 struct
+ */
+
+#define MH_DEBUG_REG13_TC_ROQ_INFO_SIZE 25
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1
+
+#define MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT 0
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 25
+
+#define MH_DEBUG_REG13_TC_ROQ_INFO_MASK 0x01ffffff
+#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x02000000
+
+#define MH_DEBUG_REG13_MASK \
+     (MH_DEBUG_REG13_TC_ROQ_INFO_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_SEND_MASK)
+
+#define MH_DEBUG_REG13(tc_roq_info, tc_roq_send) \
+     ((tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT))
+
+#define MH_DEBUG_REG13_GET_TC_ROQ_INFO(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+
+#define MH_DEBUG_REG13_SET_TC_ROQ_INFO(mh_debug_reg13_reg, tc_roq_info) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int tc_roq_info                    : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int                                : 6;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_info                    : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE;
+     } mh_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg13_t f;
+} mh_debug_reg13_u;
+
+
+/*
+ * MH_DEBUG_REG14 struct
+ */
+
+#define MH_DEBUG_REG14_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG14_RB_MH_send_SIZE 1
+#define MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG14_RB_MH_send_SHIFT 4
+#define MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG14_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG14_RB_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG14_RB_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG14_MASK \
+     (MH_DEBUG_REG14_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG14_RB_MH_send_MASK | \
+      MH_DEBUG_REG14_RB_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG14(always_zero, rb_mh_send, rb_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) | \
+      (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT) | \
+      (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG14_GET_ALWAYS_ZERO(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG14_GET_RB_MH_send(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_send_MASK) >> MH_DEBUG_REG14_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG14_GET_RB_MH_addr_31_5(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG14_SET_ALWAYS_ZERO(mh_debug_reg14_reg, always_zero) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG14_SET_RB_MH_send(mh_debug_reg14_reg, rb_mh_send) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG14_SET_RB_MH_addr_31_5(mh_debug_reg14_reg, rb_mh_addr_31_5) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int always_zero                    : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG14_RB_MH_send_SIZE;
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE;
+     } mh_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG14_RB_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg14_t f;
+} mh_debug_reg14_u;
+
+
+/*
+ * MH_DEBUG_REG15 struct
+ */
+
+#define MH_DEBUG_REG15_RB_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG15_RB_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG15_MASK \
+     (MH_DEBUG_REG15_RB_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG15(rb_mh_data_31_0) \
+     ((rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG15_GET_RB_MH_data_31_0(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG15_SET_RB_MH_data_31_0(mh_debug_reg15_reg, rb_mh_data_31_0) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg15_t f;
+} mh_debug_reg15_u;
+
+
+/*
+ * MH_DEBUG_REG16 struct
+ */
+
+#define MH_DEBUG_REG16_RB_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG16_RB_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG16_MASK \
+     (MH_DEBUG_REG16_RB_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG16(rb_mh_data_63_32) \
+     ((rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG16_GET_RB_MH_data_63_32(mh_debug_reg16) \
+     ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG16_SET_RB_MH_data_63_32(mh_debug_reg16_reg, rb_mh_data_63_32) \
+     mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg16_t f;
+} mh_debug_reg16_u;
+
+
+/*
+ * MH_DEBUG_REG17 struct
+ */
+
+#define MH_DEBUG_REG17_AVALID_q_SIZE   1
+#define MH_DEBUG_REG17_AREADY_q_SIZE   1
+#define MH_DEBUG_REG17_AID_q_SIZE      3
+#define MH_DEBUG_REG17_ALEN_q_2_0_SIZE 3
+#define MH_DEBUG_REG17_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG17_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG17_ARID_q_SIZE     3
+#define MH_DEBUG_REG17_ARLEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG17_RVALID_q_SIZE   1
+#define MH_DEBUG_REG17_RREADY_q_SIZE   1
+#define MH_DEBUG_REG17_RLAST_q_SIZE    1
+#define MH_DEBUG_REG17_RID_q_SIZE      3
+#define MH_DEBUG_REG17_WVALID_q_SIZE   1
+#define MH_DEBUG_REG17_WREADY_q_SIZE   1
+#define MH_DEBUG_REG17_WLAST_q_SIZE    1
+#define MH_DEBUG_REG17_WID_q_SIZE      3
+#define MH_DEBUG_REG17_BVALID_q_SIZE   1
+#define MH_DEBUG_REG17_BREADY_q_SIZE   1
+#define MH_DEBUG_REG17_BID_q_SIZE      3
+
+#define MH_DEBUG_REG17_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG17_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG17_AID_q_SHIFT     2
+#define MH_DEBUG_REG17_ALEN_q_2_0_SHIFT 5
+#define MH_DEBUG_REG17_ARVALID_q_SHIFT 8
+#define MH_DEBUG_REG17_ARREADY_q_SHIFT 9
+#define MH_DEBUG_REG17_ARID_q_SHIFT    10
+#define MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT 13
+#define MH_DEBUG_REG17_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG17_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG17_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG17_RID_q_SHIFT     18
+#define MH_DEBUG_REG17_WVALID_q_SHIFT  21
+#define MH_DEBUG_REG17_WREADY_q_SHIFT  22
+#define MH_DEBUG_REG17_WLAST_q_SHIFT   23
+#define MH_DEBUG_REG17_WID_q_SHIFT     24
+#define MH_DEBUG_REG17_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG17_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG17_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG17_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG17_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG17_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG17_ALEN_q_2_0_MASK 0x000000e0
+#define MH_DEBUG_REG17_ARVALID_q_MASK  0x00000100
+#define MH_DEBUG_REG17_ARREADY_q_MASK  0x00000200
+#define MH_DEBUG_REG17_ARID_q_MASK     0x00001c00
+#define MH_DEBUG_REG17_ARLEN_q_1_0_MASK 0x00006000
+#define MH_DEBUG_REG17_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG17_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG17_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG17_RID_q_MASK      0x001c0000
+#define MH_DEBUG_REG17_WVALID_q_MASK   0x00200000
+#define MH_DEBUG_REG17_WREADY_q_MASK   0x00400000
+#define MH_DEBUG_REG17_WLAST_q_MASK    0x00800000
+#define MH_DEBUG_REG17_WID_q_MASK      0x07000000
+#define MH_DEBUG_REG17_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG17_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG17_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG17_MASK \
+     (MH_DEBUG_REG17_AVALID_q_MASK | \
+      MH_DEBUG_REG17_AREADY_q_MASK | \
+      MH_DEBUG_REG17_AID_q_MASK | \
+      MH_DEBUG_REG17_ALEN_q_2_0_MASK | \
+      MH_DEBUG_REG17_ARVALID_q_MASK | \
+      MH_DEBUG_REG17_ARREADY_q_MASK | \
+      MH_DEBUG_REG17_ARID_q_MASK | \
+      MH_DEBUG_REG17_ARLEN_q_1_0_MASK | \
+      MH_DEBUG_REG17_RVALID_q_MASK | \
+      MH_DEBUG_REG17_RREADY_q_MASK | \
+      MH_DEBUG_REG17_RLAST_q_MASK | \
+      MH_DEBUG_REG17_RID_q_MASK | \
+      MH_DEBUG_REG17_WVALID_q_MASK | \
+      MH_DEBUG_REG17_WREADY_q_MASK | \
+      MH_DEBUG_REG17_WLAST_q_MASK | \
+      MH_DEBUG_REG17_WID_q_MASK | \
+      MH_DEBUG_REG17_BVALID_q_MASK | \
+      MH_DEBUG_REG17_BREADY_q_MASK | \
+      MH_DEBUG_REG17_BID_q_MASK)
+
+#define MH_DEBUG_REG17(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG17_AID_q_SHIFT) | \
+      (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT) | \
+      (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT) | \
+      (rid_q << MH_DEBUG_REG17_RID_q_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG17_WID_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG17_BID_q_SHIFT))
+
+#define MH_DEBUG_REG17_GET_AVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_AVALID_q_MASK) >> MH_DEBUG_REG17_AVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_AREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_AREADY_q_MASK) >> MH_DEBUG_REG17_AREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_AID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_AID_q_MASK) >> MH_DEBUG_REG17_AID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ALEN_q_2_0(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ALEN_q_2_0_MASK) >> MH_DEBUG_REG17_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG17_GET_ARVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARVALID_q_MASK) >> MH_DEBUG_REG17_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ARREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARREADY_q_MASK) >> MH_DEBUG_REG17_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ARID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARID_q_MASK) >> MH_DEBUG_REG17_ARID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_ARLEN_q_1_0(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG17_GET_RVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RVALID_q_MASK) >> MH_DEBUG_REG17_RVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_RREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RREADY_q_MASK) >> MH_DEBUG_REG17_RREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_RLAST_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RLAST_q_MASK) >> MH_DEBUG_REG17_RLAST_q_SHIFT)
+#define MH_DEBUG_REG17_GET_RID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RID_q_MASK) >> MH_DEBUG_REG17_RID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WVALID_q_MASK) >> MH_DEBUG_REG17_WVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WREADY_q_MASK) >> MH_DEBUG_REG17_WREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WLAST_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WLAST_q_MASK) >> MH_DEBUG_REG17_WLAST_q_SHIFT)
+#define MH_DEBUG_REG17_GET_WID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_WID_q_MASK) >> MH_DEBUG_REG17_WID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_BVALID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_BVALID_q_MASK) >> MH_DEBUG_REG17_BVALID_q_SHIFT)
+#define MH_DEBUG_REG17_GET_BREADY_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_BREADY_q_MASK) >> MH_DEBUG_REG17_BREADY_q_SHIFT)
+#define MH_DEBUG_REG17_GET_BID_q(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_BID_q_MASK) >> MH_DEBUG_REG17_BID_q_SHIFT)
+
+#define MH_DEBUG_REG17_SET_AVALID_q(mh_debug_reg17_reg, avalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_AREADY_q(mh_debug_reg17_reg, aready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_AID_q(mh_debug_reg17_reg, aid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AID_q_MASK) | (aid_q << MH_DEBUG_REG17_AID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ALEN_q_2_0(mh_debug_reg17_reg, alen_q_2_0) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG17_SET_ARVALID_q(mh_debug_reg17_reg, arvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ARREADY_q(mh_debug_reg17_reg, arready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ARID_q(mh_debug_reg17_reg, arid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARID_q_MASK) | (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_ARLEN_q_1_0(mh_debug_reg17_reg, arlen_q_1_0) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG17_SET_RVALID_q(mh_debug_reg17_reg, rvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_RREADY_q(mh_debug_reg17_reg, rready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_RLAST_q(mh_debug_reg17_reg, rlast_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT)
+#define MH_DEBUG_REG17_SET_RID_q(mh_debug_reg17_reg, rid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RID_q_MASK) | (rid_q << MH_DEBUG_REG17_RID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WVALID_q(mh_debug_reg17_reg, wvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WREADY_q(mh_debug_reg17_reg, wready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WLAST_q(mh_debug_reg17_reg, wlast_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT)
+#define MH_DEBUG_REG17_SET_WID_q(mh_debug_reg17_reg, wid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WID_q_MASK) | (wid_q << MH_DEBUG_REG17_WID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_BVALID_q(mh_debug_reg17_reg, bvalid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT)
+#define MH_DEBUG_REG17_SET_BREADY_q(mh_debug_reg17_reg, bready_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT)
+#define MH_DEBUG_REG17_SET_BID_q(mh_debug_reg17_reg, bid_q) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BID_q_MASK) | (bid_q << MH_DEBUG_REG17_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG17_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG17_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG17_AID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG17_ALEN_q_2_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG17_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG17_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG17_ARID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG17_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG17_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG17_RLAST_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG17_RID_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG17_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG17_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG17_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG17_WID_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG17_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG17_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG17_BID_q_SIZE;
+     } mh_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int bid_q                          : MH_DEBUG_REG17_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG17_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG17_BVALID_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG17_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG17_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG17_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG17_WVALID_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG17_RID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG17_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG17_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG17_RVALID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG17_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG17_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG17_ARVALID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG17_ALEN_q_2_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG17_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG17_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG17_AVALID_q_SIZE;
+     } mh_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg17_t f;
+} mh_debug_reg17_u;
+
+
+/*
+ * MH_DEBUG_REG18 struct
+ */
+
+#define MH_DEBUG_REG18_AVALID_q_SIZE   1
+#define MH_DEBUG_REG18_AREADY_q_SIZE   1
+#define MH_DEBUG_REG18_AID_q_SIZE      3
+#define MH_DEBUG_REG18_ALEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG18_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG18_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG18_ARID_q_SIZE     3
+#define MH_DEBUG_REG18_ARLEN_q_1_1_SIZE 1
+#define MH_DEBUG_REG18_WVALID_q_SIZE   1
+#define MH_DEBUG_REG18_WREADY_q_SIZE   1
+#define MH_DEBUG_REG18_WLAST_q_SIZE    1
+#define MH_DEBUG_REG18_WID_q_SIZE      3
+#define MH_DEBUG_REG18_WSTRB_q_SIZE    8
+#define MH_DEBUG_REG18_BVALID_q_SIZE   1
+#define MH_DEBUG_REG18_BREADY_q_SIZE   1
+#define MH_DEBUG_REG18_BID_q_SIZE      3
+
+#define MH_DEBUG_REG18_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG18_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG18_AID_q_SHIFT     2
+#define MH_DEBUG_REG18_ALEN_q_1_0_SHIFT 5
+#define MH_DEBUG_REG18_ARVALID_q_SHIFT 7
+#define MH_DEBUG_REG18_ARREADY_q_SHIFT 8
+#define MH_DEBUG_REG18_ARID_q_SHIFT    9
+#define MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT 12
+#define MH_DEBUG_REG18_WVALID_q_SHIFT  13
+#define MH_DEBUG_REG18_WREADY_q_SHIFT  14
+#define MH_DEBUG_REG18_WLAST_q_SHIFT   15
+#define MH_DEBUG_REG18_WID_q_SHIFT     16
+#define MH_DEBUG_REG18_WSTRB_q_SHIFT   19
+#define MH_DEBUG_REG18_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG18_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG18_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG18_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG18_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG18_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG18_ALEN_q_1_0_MASK 0x00000060
+#define MH_DEBUG_REG18_ARVALID_q_MASK  0x00000080
+#define MH_DEBUG_REG18_ARREADY_q_MASK  0x00000100
+#define MH_DEBUG_REG18_ARID_q_MASK     0x00000e00
+#define MH_DEBUG_REG18_ARLEN_q_1_1_MASK 0x00001000
+#define MH_DEBUG_REG18_WVALID_q_MASK   0x00002000
+#define MH_DEBUG_REG18_WREADY_q_MASK   0x00004000
+#define MH_DEBUG_REG18_WLAST_q_MASK    0x00008000
+#define MH_DEBUG_REG18_WID_q_MASK      0x00070000
+#define MH_DEBUG_REG18_WSTRB_q_MASK    0x07f80000
+#define MH_DEBUG_REG18_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG18_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG18_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG18_MASK \
+     (MH_DEBUG_REG18_AVALID_q_MASK | \
+      MH_DEBUG_REG18_AREADY_q_MASK | \
+      MH_DEBUG_REG18_AID_q_MASK | \
+      MH_DEBUG_REG18_ALEN_q_1_0_MASK | \
+      MH_DEBUG_REG18_ARVALID_q_MASK | \
+      MH_DEBUG_REG18_ARREADY_q_MASK | \
+      MH_DEBUG_REG18_ARID_q_MASK | \
+      MH_DEBUG_REG18_ARLEN_q_1_1_MASK | \
+      MH_DEBUG_REG18_WVALID_q_MASK | \
+      MH_DEBUG_REG18_WREADY_q_MASK | \
+      MH_DEBUG_REG18_WLAST_q_MASK | \
+      MH_DEBUG_REG18_WID_q_MASK | \
+      MH_DEBUG_REG18_WSTRB_q_MASK | \
+      MH_DEBUG_REG18_BVALID_q_MASK | \
+      MH_DEBUG_REG18_BREADY_q_MASK | \
+      MH_DEBUG_REG18_BID_q_MASK)
+
+#define MH_DEBUG_REG18(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG18_AID_q_SHIFT) | \
+      (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT) | \
+      (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG18_WID_q_SHIFT) | \
+      (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG18_BID_q_SHIFT))
+
+#define MH_DEBUG_REG18_GET_AVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_AVALID_q_MASK) >> MH_DEBUG_REG18_AVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_AREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_AREADY_q_MASK) >> MH_DEBUG_REG18_AREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_AID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_AID_q_MASK) >> MH_DEBUG_REG18_AID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ALEN_q_1_0(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ALEN_q_1_0_MASK) >> MH_DEBUG_REG18_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG18_GET_ARVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARVALID_q_MASK) >> MH_DEBUG_REG18_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ARREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARREADY_q_MASK) >> MH_DEBUG_REG18_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ARID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARID_q_MASK) >> MH_DEBUG_REG18_ARID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_ARLEN_q_1_1(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG18_GET_WVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WVALID_q_MASK) >> MH_DEBUG_REG18_WVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WREADY_q_MASK) >> MH_DEBUG_REG18_WREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WLAST_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WLAST_q_MASK) >> MH_DEBUG_REG18_WLAST_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WID_q_MASK) >> MH_DEBUG_REG18_WID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_WSTRB_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_WSTRB_q_MASK) >> MH_DEBUG_REG18_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG18_GET_BVALID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_BVALID_q_MASK) >> MH_DEBUG_REG18_BVALID_q_SHIFT)
+#define MH_DEBUG_REG18_GET_BREADY_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_BREADY_q_MASK) >> MH_DEBUG_REG18_BREADY_q_SHIFT)
+#define MH_DEBUG_REG18_GET_BID_q(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_BID_q_MASK) >> MH_DEBUG_REG18_BID_q_SHIFT)
+
+#define MH_DEBUG_REG18_SET_AVALID_q(mh_debug_reg18_reg, avalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_AREADY_q(mh_debug_reg18_reg, aready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_AID_q(mh_debug_reg18_reg, aid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AID_q_MASK) | (aid_q << MH_DEBUG_REG18_AID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ALEN_q_1_0(mh_debug_reg18_reg, alen_q_1_0) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG18_SET_ARVALID_q(mh_debug_reg18_reg, arvalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ARREADY_q(mh_debug_reg18_reg, arready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ARID_q(mh_debug_reg18_reg, arid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARID_q_MASK) | (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_ARLEN_q_1_1(mh_debug_reg18_reg, arlen_q_1_1) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG18_SET_WVALID_q(mh_debug_reg18_reg, wvalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WREADY_q(mh_debug_reg18_reg, wready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WLAST_q(mh_debug_reg18_reg, wlast_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WID_q(mh_debug_reg18_reg, wid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WID_q_MASK) | (wid_q << MH_DEBUG_REG18_WID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_WSTRB_q(mh_debug_reg18_reg, wstrb_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG18_SET_BVALID_q(mh_debug_reg18_reg, bvalid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT)
+#define MH_DEBUG_REG18_SET_BREADY_q(mh_debug_reg18_reg, bready_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT)
+#define MH_DEBUG_REG18_SET_BID_q(mh_debug_reg18_reg, bid_q) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BID_q_MASK) | (bid_q << MH_DEBUG_REG18_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG18_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG18_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG18_AID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG18_ALEN_q_1_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG18_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG18_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG18_ARID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG18_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG18_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG18_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG18_WID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG18_WSTRB_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG18_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG18_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG18_BID_q_SIZE;
+     } mh_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int bid_q                          : MH_DEBUG_REG18_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG18_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG18_BVALID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG18_WSTRB_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG18_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG18_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG18_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG18_WVALID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG18_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG18_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG18_ARVALID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG18_ALEN_q_1_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG18_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG18_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG18_AVALID_q_SIZE;
+     } mh_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg18_t f;
+} mh_debug_reg18_u;
+
+
+/*
+ * MH_DEBUG_REG19 struct
+ */
+
+#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG19_CTRL_ARC_ID_SIZE 3
+#define MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE 28
+
+#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT 0
+#define MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT 1
+#define MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT 4
+
+#define MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK 0x00000001
+#define MH_DEBUG_REG19_CTRL_ARC_ID_MASK 0x0000000e
+#define MH_DEBUG_REG19_CTRL_ARC_PAD_MASK 0xfffffff0
+
+#define MH_DEBUG_REG19_MASK \
+     (MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG19_CTRL_ARC_ID_MASK | \
+      MH_DEBUG_REG19_CTRL_ARC_PAD_MASK)
+
+#define MH_DEBUG_REG19(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \
+     ((arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) | \
+      (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) | \
+      (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT))
+
+#define MH_DEBUG_REG19_GET_ARC_CTRL_RE_q(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG19_GET_CTRL_ARC_ID(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG19_GET_CTRL_ARC_PAD(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT)
+
+#define MH_DEBUG_REG19_SET_ARC_CTRL_RE_q(mh_debug_reg19_reg, arc_ctrl_re_q) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG19_SET_CTRL_ARC_ID(mh_debug_reg19_reg, ctrl_arc_id) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG19_SET_CTRL_ARC_PAD(mh_debug_reg19_reg, ctrl_arc_pad) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE;
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE;
+     } mh_debug_reg19_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE;
+     } mh_debug_reg19_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg19_t f;
+} mh_debug_reg19_u;
+
+
+/*
+ * MH_DEBUG_REG20 struct
+ */
+
+#define MH_DEBUG_REG20_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG20_REG_A_SIZE      14
+#define MH_DEBUG_REG20_REG_RE_SIZE     1
+#define MH_DEBUG_REG20_REG_WE_SIZE     1
+#define MH_DEBUG_REG20_BLOCK_RS_SIZE   1
+
+#define MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG20_REG_A_SHIFT     2
+#define MH_DEBUG_REG20_REG_RE_SHIFT    16
+#define MH_DEBUG_REG20_REG_WE_SHIFT    17
+#define MH_DEBUG_REG20_BLOCK_RS_SHIFT  18
+
+#define MH_DEBUG_REG20_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG20_REG_A_MASK      0x0000fffc
+#define MH_DEBUG_REG20_REG_RE_MASK     0x00010000
+#define MH_DEBUG_REG20_REG_WE_MASK     0x00020000
+#define MH_DEBUG_REG20_BLOCK_RS_MASK   0x00040000
+
+#define MH_DEBUG_REG20_MASK \
+     (MH_DEBUG_REG20_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG20_REG_A_MASK | \
+      MH_DEBUG_REG20_REG_RE_MASK | \
+      MH_DEBUG_REG20_REG_WE_MASK | \
+      MH_DEBUG_REG20_BLOCK_RS_MASK)
+
+#define MH_DEBUG_REG20(always_zero, reg_a, reg_re, reg_we, block_rs) \
+     ((always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) | \
+      (reg_a << MH_DEBUG_REG20_REG_A_SHIFT) | \
+      (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT) | \
+      (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT) | \
+      (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT))
+
+#define MH_DEBUG_REG20_GET_ALWAYS_ZERO(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG20_GET_REG_A(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_REG_A_MASK) >> MH_DEBUG_REG20_REG_A_SHIFT)
+#define MH_DEBUG_REG20_GET_REG_RE(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_REG_RE_MASK) >> MH_DEBUG_REG20_REG_RE_SHIFT)
+#define MH_DEBUG_REG20_GET_REG_WE(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_REG_WE_MASK) >> MH_DEBUG_REG20_REG_WE_SHIFT)
+#define MH_DEBUG_REG20_GET_BLOCK_RS(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_BLOCK_RS_MASK) >> MH_DEBUG_REG20_BLOCK_RS_SHIFT)
+
+#define MH_DEBUG_REG20_SET_ALWAYS_ZERO(mh_debug_reg20_reg, always_zero) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG20_SET_REG_A(mh_debug_reg20_reg, reg_a) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_A_MASK) | (reg_a << MH_DEBUG_REG20_REG_A_SHIFT)
+#define MH_DEBUG_REG20_SET_REG_RE(mh_debug_reg20_reg, reg_re) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_RE_MASK) | (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT)
+#define MH_DEBUG_REG20_SET_REG_WE(mh_debug_reg20_reg, reg_we) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_WE_MASK) | (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT)
+#define MH_DEBUG_REG20_SET_BLOCK_RS(mh_debug_reg20_reg, block_rs) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int always_zero                    : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG20_REG_A_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG20_REG_RE_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG20_REG_WE_SIZE;
+          unsigned int block_rs                       : MH_DEBUG_REG20_BLOCK_RS_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int                                : 13;
+          unsigned int block_rs                       : MH_DEBUG_REG20_BLOCK_RS_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG20_REG_WE_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG20_REG_RE_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG20_REG_A_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg20_t f;
+} mh_debug_reg20_u;
+
+
+/*
+ * MH_DEBUG_REG21 struct
+ */
+
+#define MH_DEBUG_REG21_REG_WD_SIZE     32
+
+#define MH_DEBUG_REG21_REG_WD_SHIFT    0
+
+#define MH_DEBUG_REG21_REG_WD_MASK     0xffffffff
+
+#define MH_DEBUG_REG21_MASK \
+     (MH_DEBUG_REG21_REG_WD_MASK)
+
+#define MH_DEBUG_REG21(reg_wd) \
+     ((reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT))
+
+#define MH_DEBUG_REG21_GET_REG_WD(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_REG_WD_MASK) >> MH_DEBUG_REG21_REG_WD_SHIFT)
+
+#define MH_DEBUG_REG21_SET_REG_WD(mh_debug_reg21_reg, reg_wd) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG21_REG_WD_SIZE;
+     } mh_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG21_REG_WD_SIZE;
+     } mh_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg21_t f;
+} mh_debug_reg21_u;
+
+
+/*
+ * MH_DEBUG_REG22 struct
+ */
+
+#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE 1
+#define MH_DEBUG_REG22_MH_RBBM_busy_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE 1
+#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE 1
+#define MH_DEBUG_REG22_GAT_CLK_ENA_SIZE 1
+#define MH_DEBUG_REG22_AXI_RDY_ENA_SIZE 1
+#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE 1
+#define MH_DEBUG_REG22_CNT_q_SIZE      6
+#define MH_DEBUG_REG22_TCD_EMPTY_q_SIZE 1
+#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG22_MH_BUSY_d_SIZE  1
+#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE 1
+#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_DEBUG_REG22_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG22_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG22_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG22_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG22_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG22_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG22_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG22_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG22_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG22_BRC_VALID_SIZE  1
+
+#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT 0
+#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT 1
+#define MH_DEBUG_REG22_MH_RBBM_busy_SHIFT 2
+#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT 3
+#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT 4
+#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT 5
+#define MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT 6
+#define MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT 7
+#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT 8
+#define MH_DEBUG_REG22_CNT_q_SHIFT     9
+#define MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT 15
+#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT 16
+#define MH_DEBUG_REG22_MH_BUSY_d_SHIFT 17
+#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT 18
+#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 19
+#define MH_DEBUG_REG22_CP_SEND_q_SHIFT 20
+#define MH_DEBUG_REG22_CP_RTR_q_SHIFT  21
+#define MH_DEBUG_REG22_VGT_SEND_q_SHIFT 22
+#define MH_DEBUG_REG22_VGT_RTR_q_SHIFT 23
+#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT 24
+#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG22_RB_SEND_q_SHIFT 26
+#define MH_DEBUG_REG22_RB_RTR_q_SHIFT  27
+#define MH_DEBUG_REG22_RDC_VALID_SHIFT 28
+#define MH_DEBUG_REG22_RDC_RLAST_SHIFT 29
+#define MH_DEBUG_REG22_TLBMISS_VALID_SHIFT 30
+#define MH_DEBUG_REG22_BRC_VALID_SHIFT 31
+
+#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK 0x00000001
+#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK 0x00000002
+#define MH_DEBUG_REG22_MH_RBBM_busy_MASK 0x00000004
+#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK 0x00000008
+#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK 0x00000010
+#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK 0x00000020
+#define MH_DEBUG_REG22_GAT_CLK_ENA_MASK 0x00000040
+#define MH_DEBUG_REG22_AXI_RDY_ENA_MASK 0x00000080
+#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK 0x00000100
+#define MH_DEBUG_REG22_CNT_q_MASK      0x00007e00
+#define MH_DEBUG_REG22_TCD_EMPTY_q_MASK 0x00008000
+#define MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK 0x00010000
+#define MH_DEBUG_REG22_MH_BUSY_d_MASK  0x00020000
+#define MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK 0x00040000
+#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000
+#define MH_DEBUG_REG22_CP_SEND_q_MASK  0x00100000
+#define MH_DEBUG_REG22_CP_RTR_q_MASK   0x00200000
+#define MH_DEBUG_REG22_VGT_SEND_q_MASK 0x00400000
+#define MH_DEBUG_REG22_VGT_RTR_q_MASK  0x00800000
+#define MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK 0x01000000
+#define MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG22_RB_SEND_q_MASK  0x04000000
+#define MH_DEBUG_REG22_RB_RTR_q_MASK   0x08000000
+#define MH_DEBUG_REG22_RDC_VALID_MASK  0x10000000
+#define MH_DEBUG_REG22_RDC_RLAST_MASK  0x20000000
+#define MH_DEBUG_REG22_TLBMISS_VALID_MASK 0x40000000
+#define MH_DEBUG_REG22_BRC_VALID_MASK  0x80000000
+
+#define MH_DEBUG_REG22_MASK \
+     (MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK | \
+      MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK | \
+      MH_DEBUG_REG22_MH_RBBM_busy_MASK | \
+      MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK | \
+      MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK | \
+      MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK | \
+      MH_DEBUG_REG22_GAT_CLK_ENA_MASK | \
+      MH_DEBUG_REG22_AXI_RDY_ENA_MASK | \
+      MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK | \
+      MH_DEBUG_REG22_CNT_q_MASK | \
+      MH_DEBUG_REG22_TCD_EMPTY_q_MASK | \
+      MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG22_MH_BUSY_d_MASK | \
+      MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK | \
+      MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_DEBUG_REG22_CP_SEND_q_MASK | \
+      MH_DEBUG_REG22_CP_RTR_q_MASK | \
+      MH_DEBUG_REG22_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG22_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG22_RB_SEND_q_MASK | \
+      MH_DEBUG_REG22_RB_RTR_q_MASK | \
+      MH_DEBUG_REG22_RDC_VALID_MASK | \
+      MH_DEBUG_REG22_RDC_RLAST_MASK | \
+      MH_DEBUG_REG22_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG22_BRC_VALID_MASK)
+
+#define MH_DEBUG_REG22(cib_mh_axi_halt_req, mh_cib_axi_halt_ack, mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, axi_rdy_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_q, rb_send_q, rb_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \
+     ((cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) | \
+      (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) | \
+      (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) | \
+      (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) | \
+      (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) | \
+      (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) | \
+      (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) | \
+      (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) | \
+      (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) | \
+      (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT) | \
+      (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) | \
+      (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT) | \
+      (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) | \
+      (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT))
+
+#define MH_DEBUG_REG22_GET_CIB_MH_axi_halt_req(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) >> MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_axi_halt_ack(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) >> MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_RBBM_busy(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_RBBM_busy_MASK) >> MH_DEBUG_REG22_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_mh_clk_en_int(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_GET_GAT_CLK_ENA(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG22_GET_AXI_RDY_ENA(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT)
+#define MH_DEBUG_REG22_GET_RBBM_MH_clk_en_override(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG22_GET_CNT_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CNT_q_MASK) >> MH_DEBUG_REG22_CNT_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TCD_EMPTY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TC_ROQ_EMPTY(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_BUSY_d(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_BUSY_d_MASK) >> MH_DEBUG_REG22_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG22_GET_ANY_CLNT_BUSY(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG22_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG22_GET_CP_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CP_SEND_q_MASK) >> MH_DEBUG_REG22_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_CP_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_CP_RTR_q_MASK) >> MH_DEBUG_REG22_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_VGT_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_SEND_q_MASK) >> MH_DEBUG_REG22_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_VGT_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_RTR_q_MASK) >> MH_DEBUG_REG22_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TC_ROQ_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_TC_ROQ_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_RB_SEND_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RB_SEND_q_MASK) >> MH_DEBUG_REG22_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_GET_RB_RTR_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RB_RTR_q_MASK) >> MH_DEBUG_REG22_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_GET_RDC_VALID(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_VALID_MASK) >> MH_DEBUG_REG22_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG22_GET_RDC_RLAST(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_RLAST_MASK) >> MH_DEBUG_REG22_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG22_GET_TLBMISS_VALID(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_TLBMISS_VALID_MASK) >> MH_DEBUG_REG22_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG22_GET_BRC_VALID(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BRC_VALID_MASK) >> MH_DEBUG_REG22_BRC_VALID_SHIFT)
+
+#define MH_DEBUG_REG22_SET_CIB_MH_axi_halt_req(mh_debug_reg22_reg, cib_mh_axi_halt_req) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) | (cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_axi_halt_ack(mh_debug_reg22_reg, mh_cib_axi_halt_ack) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) | (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_RBBM_busy(mh_debug_reg22_reg, mh_rbbm_busy) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_mh_clk_en_int(mh_debug_reg22_reg, mh_cib_mh_clk_en_int) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg22_reg, mh_cib_mmu_clk_en_int) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22_reg, mh_cib_tcroq_clk_en_int) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG22_SET_GAT_CLK_ENA(mh_debug_reg22_reg, gat_clk_ena) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG22_SET_AXI_RDY_ENA(mh_debug_reg22_reg, axi_rdy_ena) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT)
+#define MH_DEBUG_REG22_SET_RBBM_MH_clk_en_override(mh_debug_reg22_reg, rbbm_mh_clk_en_override) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG22_SET_CNT_q(mh_debug_reg22_reg, cnt_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TCD_EMPTY_q(mh_debug_reg22_reg, tcd_empty_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TC_ROQ_EMPTY(mh_debug_reg22_reg, tc_roq_empty) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_BUSY_d(mh_debug_reg22_reg, mh_busy_d) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG22_SET_ANY_CLNT_BUSY(mh_debug_reg22_reg, any_clnt_busy) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG22_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22_reg, mh_mmu_invalidate_invalidate_all) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG22_SET_CP_SEND_q(mh_debug_reg22_reg, cp_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_CP_RTR_q(mh_debug_reg22_reg, cp_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_VGT_SEND_q(mh_debug_reg22_reg, vgt_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_VGT_RTR_q(mh_debug_reg22_reg, vgt_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TC_ROQ_SEND_q(mh_debug_reg22_reg, tc_roq_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_TC_ROQ_RTR_q(mh_debug_reg22_reg, tc_roq_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_RB_SEND_q(mh_debug_reg22_reg, rb_send_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG22_SET_RB_RTR_q(mh_debug_reg22_reg, rb_rtr_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG22_SET_RDC_VALID(mh_debug_reg22_reg, rdc_valid) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG22_SET_RDC_RLAST(mh_debug_reg22_reg, rdc_rlast) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG22_SET_TLBMISS_VALID(mh_debug_reg22_reg, tlbmiss_valid) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG22_SET_BRC_VALID(mh_debug_reg22_reg, brc_valid) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int cib_mh_axi_halt_req            : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE;
+          unsigned int mh_cib_axi_halt_ack            : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG22_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG22_CNT_q_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG22_MH_BUSY_d_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG22_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG22_CP_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG22_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG22_VGT_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG22_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG22_RB_RTR_q_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG22_RDC_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG22_RDC_RLAST_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG22_TLBMISS_VALID_SIZE;
+          unsigned int brc_valid                      : MH_DEBUG_REG22_BRC_VALID_SIZE;
+     } mh_debug_reg22_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int brc_valid                      : MH_DEBUG_REG22_BRC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG22_TLBMISS_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG22_RDC_RLAST_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG22_RDC_VALID_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG22_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG22_RB_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG22_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG22_VGT_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG22_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG22_CP_SEND_q_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG22_MH_BUSY_d_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG22_CNT_q_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG22_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_axi_halt_ack            : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE;
+          unsigned int cib_mh_axi_halt_req            : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE;
+     } mh_debug_reg22_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg22_t f;
+} mh_debug_reg22_u;
+
+
+/*
+ * MH_DEBUG_REG23 struct
+ */
+
+#define MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE 3
+#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG23_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG23_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG23_ARB_WINNER_q_SIZE 3
+#define MH_DEBUG_REG23_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG23_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG23_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG23_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG23_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG23_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG23_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG23_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG23_TCHOLD_IP_q_SIZE 1
+
+#define MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT 0
+#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT 3
+#define MH_DEBUG_REG23_EFF1_WINNER_SHIFT 6
+#define MH_DEBUG_REG23_ARB_WINNER_SHIFT 9
+#define MH_DEBUG_REG23_ARB_WINNER_q_SHIFT 12
+#define MH_DEBUG_REG23_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG23_KILL_EFF1_SHIFT 16
+#define MH_DEBUG_REG23_ARB_HOLD_SHIFT  17
+#define MH_DEBUG_REG23_ARB_RTR_q_SHIFT 18
+#define MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT 19
+#define MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT 20
+#define MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT 21
+#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT 22
+#define MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT 23
+#define MH_DEBUG_REG23_ARB_QUAL_SHIFT  24
+#define MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT 25
+#define MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT 26
+#define MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT 27
+#define MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT 28
+#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT 29
+#define MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT 30
+#define MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT 31
+
+#define MH_DEBUG_REG23_EFF2_FP_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK 0x00000038
+#define MH_DEBUG_REG23_EFF1_WINNER_MASK 0x000001c0
+#define MH_DEBUG_REG23_ARB_WINNER_MASK 0x00000e00
+#define MH_DEBUG_REG23_ARB_WINNER_q_MASK 0x00007000
+#define MH_DEBUG_REG23_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG23_KILL_EFF1_MASK  0x00010000
+#define MH_DEBUG_REG23_ARB_HOLD_MASK   0x00020000
+#define MH_DEBUG_REG23_ARB_RTR_q_MASK  0x00040000
+#define MH_DEBUG_REG23_CP_SEND_QUAL_MASK 0x00080000
+#define MH_DEBUG_REG23_VGT_SEND_QUAL_MASK 0x00100000
+#define MH_DEBUG_REG23_TC_SEND_QUAL_MASK 0x00200000
+#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK 0x00400000
+#define MH_DEBUG_REG23_RB_SEND_QUAL_MASK 0x00800000
+#define MH_DEBUG_REG23_ARB_QUAL_MASK   0x01000000
+#define MH_DEBUG_REG23_CP_EFF1_REQ_MASK 0x02000000
+#define MH_DEBUG_REG23_VGT_EFF1_REQ_MASK 0x04000000
+#define MH_DEBUG_REG23_TC_EFF1_REQ_MASK 0x08000000
+#define MH_DEBUG_REG23_RB_EFF1_REQ_MASK 0x10000000
+#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK 0x20000000
+#define MH_DEBUG_REG23_TCD_NEARFULL_q_MASK 0x40000000
+#define MH_DEBUG_REG23_TCHOLD_IP_q_MASK 0x80000000
+
+#define MH_DEBUG_REG23_MASK \
+     (MH_DEBUG_REG23_EFF2_FP_WINNER_MASK | \
+      MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG23_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG23_ARB_WINNER_MASK | \
+      MH_DEBUG_REG23_ARB_WINNER_q_MASK | \
+      MH_DEBUG_REG23_EFF1_WIN_MASK | \
+      MH_DEBUG_REG23_KILL_EFF1_MASK | \
+      MH_DEBUG_REG23_ARB_HOLD_MASK | \
+      MH_DEBUG_REG23_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG23_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG23_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG23_ARB_QUAL_MASK | \
+      MH_DEBUG_REG23_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG23_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG23_TCHOLD_IP_q_MASK)
+
+#define MH_DEBUG_REG23(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, any_same_row_bank, tcd_nearfull_q, tchold_ip_q) \
+     ((eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) | \
+      (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) | \
+      (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT) | \
+      (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT))
+
+#define MH_DEBUG_REG23_GET_EFF2_FP_WINNER(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG23_GET_EFF2_LRU_WINNER_out(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG23_GET_EFF1_WINNER(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WINNER_MASK) >> MH_DEBUG_REG23_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_WINNER(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_MASK) >> MH_DEBUG_REG23_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_WINNER_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_q_MASK) >> MH_DEBUG_REG23_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG23_GET_EFF1_WIN(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WIN_MASK) >> MH_DEBUG_REG23_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG23_GET_KILL_EFF1(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_KILL_EFF1_MASK) >> MH_DEBUG_REG23_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_HOLD(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_HOLD_MASK) >> MH_DEBUG_REG23_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_RTR_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_RTR_q_MASK) >> MH_DEBUG_REG23_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG23_GET_CP_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_VGT_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_TC_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_TC_SEND_EFF1_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_RB_SEND_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_ARB_QUAL(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_QUAL_MASK) >> MH_DEBUG_REG23_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG23_GET_CP_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_VGT_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_TC_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_RB_EFF1_REQ(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_GET_ANY_SAME_ROW_BANK(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG23_GET_TCD_NEARFULL_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG23_GET_TCHOLD_IP_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT)
+
+#define MH_DEBUG_REG23_SET_EFF2_FP_WINNER(mh_debug_reg23_reg, eff2_fp_winner) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG23_SET_EFF2_LRU_WINNER_out(mh_debug_reg23_reg, eff2_lru_winner_out) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG23_SET_EFF1_WINNER(mh_debug_reg23_reg, eff1_winner) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_WINNER(mh_debug_reg23_reg, arb_winner) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_WINNER_q(mh_debug_reg23_reg, arb_winner_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG23_SET_EFF1_WIN(mh_debug_reg23_reg, eff1_win) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG23_SET_KILL_EFF1(mh_debug_reg23_reg, kill_eff1) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_HOLD(mh_debug_reg23_reg, arb_hold) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_RTR_q(mh_debug_reg23_reg, arb_rtr_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG23_SET_CP_SEND_QUAL(mh_debug_reg23_reg, cp_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_VGT_SEND_QUAL(mh_debug_reg23_reg, vgt_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_TC_SEND_QUAL(mh_debug_reg23_reg, tc_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_TC_SEND_EFF1_QUAL(mh_debug_reg23_reg, tc_send_eff1_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_RB_SEND_QUAL(mh_debug_reg23_reg, rb_send_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_ARB_QUAL(mh_debug_reg23_reg, arb_qual) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG23_SET_CP_EFF1_REQ(mh_debug_reg23_reg, cp_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_VGT_EFF1_REQ(mh_debug_reg23_reg, vgt_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_TC_EFF1_REQ(mh_debug_reg23_reg, tc_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_RB_EFF1_REQ(mh_debug_reg23_reg, rb_eff1_req) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG23_SET_ANY_SAME_ROW_BANK(mh_debug_reg23_reg, any_same_row_bank) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG23_SET_TCD_NEARFULL_q(mh_debug_reg23_reg, tcd_nearfull_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG23_SET_TCHOLD_IP_q(mh_debug_reg23_reg, tchold_ip_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG23_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG23_ARB_WINNER_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG23_ARB_WINNER_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG23_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG23_KILL_EFF1_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG23_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG23_ARB_RTR_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG23_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE;
+     } mh_debug_reg23_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG23_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG23_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG23_ARB_HOLD_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG23_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG23_EFF1_WIN_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG23_ARB_WINNER_q_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG23_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG23_EFF1_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE;
+     } mh_debug_reg23_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg23_t f;
+} mh_debug_reg23_u;
+
+
+/*
+ * MH_DEBUG_REG24 struct
+ */
+
+#define MH_DEBUG_REG24_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG24_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG24_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG24_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG24_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG24_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG24_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG24_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG24_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG24_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG24_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE 10
+
+#define MH_DEBUG_REG24_EFF1_WINNER_SHIFT 0
+#define MH_DEBUG_REG24_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT 6
+#define MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT 7
+#define MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT 8
+#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT 9
+#define MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT 10
+#define MH_DEBUG_REG24_ARB_QUAL_SHIFT  11
+#define MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT 12
+#define MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT 13
+#define MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT 14
+#define MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT 15
+#define MH_DEBUG_REG24_EFF1_WIN_SHIFT  16
+#define MH_DEBUG_REG24_KILL_EFF1_SHIFT 17
+#define MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT 18
+#define MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT 19
+#define MH_DEBUG_REG24_ARB_HOLD_SHIFT  20
+#define MH_DEBUG_REG24_ARB_RTR_q_SHIFT 21
+#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22
+
+#define MH_DEBUG_REG24_EFF1_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG24_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG24_CP_SEND_QUAL_MASK 0x00000040
+#define MH_DEBUG_REG24_VGT_SEND_QUAL_MASK 0x00000080
+#define MH_DEBUG_REG24_TC_SEND_QUAL_MASK 0x00000100
+#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK 0x00000200
+#define MH_DEBUG_REG24_RB_SEND_QUAL_MASK 0x00000400
+#define MH_DEBUG_REG24_ARB_QUAL_MASK   0x00000800
+#define MH_DEBUG_REG24_CP_EFF1_REQ_MASK 0x00001000
+#define MH_DEBUG_REG24_VGT_EFF1_REQ_MASK 0x00002000
+#define MH_DEBUG_REG24_TC_EFF1_REQ_MASK 0x00004000
+#define MH_DEBUG_REG24_RB_EFF1_REQ_MASK 0x00008000
+#define MH_DEBUG_REG24_EFF1_WIN_MASK   0x00010000
+#define MH_DEBUG_REG24_KILL_EFF1_MASK  0x00020000
+#define MH_DEBUG_REG24_TCD_NEARFULL_q_MASK 0x00040000
+#define MH_DEBUG_REG24_TC_ARB_HOLD_MASK 0x00080000
+#define MH_DEBUG_REG24_ARB_HOLD_MASK   0x00100000
+#define MH_DEBUG_REG24_ARB_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000
+
+#define MH_DEBUG_REG24_MASK \
+     (MH_DEBUG_REG24_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG24_ARB_WINNER_MASK | \
+      MH_DEBUG_REG24_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG24_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG24_ARB_QUAL_MASK | \
+      MH_DEBUG_REG24_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG24_EFF1_WIN_MASK | \
+      MH_DEBUG_REG24_KILL_EFF1_MASK | \
+      MH_DEBUG_REG24_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG24_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG24_ARB_HOLD_MASK | \
+      MH_DEBUG_REG24_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK)
+
+#define MH_DEBUG_REG24(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \
+     ((eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) | \
+      (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT) | \
+      (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT))
+
+#define MH_DEBUG_REG24_GET_EFF1_WINNER(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WINNER_MASK) >> MH_DEBUG_REG24_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_WINNER(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_WINNER_MASK) >> MH_DEBUG_REG24_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG24_GET_CP_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_VGT_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_SEND_EFF1_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_RB_SEND_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_QUAL(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_QUAL_MASK) >> MH_DEBUG_REG24_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG24_GET_CP_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_VGT_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_RB_EFF1_REQ(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_GET_EFF1_WIN(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WIN_MASK) >> MH_DEBUG_REG24_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG24_GET_KILL_EFF1(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_KILL_EFF1_MASK) >> MH_DEBUG_REG24_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG24_GET_TCD_NEARFULL_q(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG24_GET_TC_ARB_HOLD(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_HOLD(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_HOLD_MASK) >> MH_DEBUG_REG24_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_GET_ARB_RTR_q(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_RTR_q_MASK) >> MH_DEBUG_REG24_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG24_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#define MH_DEBUG_REG24_SET_EFF1_WINNER(mh_debug_reg24_reg, eff1_winner) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_WINNER(mh_debug_reg24_reg, arb_winner) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG24_SET_CP_SEND_QUAL(mh_debug_reg24_reg, cp_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_VGT_SEND_QUAL(mh_debug_reg24_reg, vgt_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_SEND_QUAL(mh_debug_reg24_reg, tc_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_SEND_EFF1_QUAL(mh_debug_reg24_reg, tc_send_eff1_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_RB_SEND_QUAL(mh_debug_reg24_reg, rb_send_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_QUAL(mh_debug_reg24_reg, arb_qual) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG24_SET_CP_EFF1_REQ(mh_debug_reg24_reg, cp_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_VGT_EFF1_REQ(mh_debug_reg24_reg, vgt_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_EFF1_REQ(mh_debug_reg24_reg, tc_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_RB_EFF1_REQ(mh_debug_reg24_reg, rb_eff1_req) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG24_SET_EFF1_WIN(mh_debug_reg24_reg, eff1_win) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG24_SET_KILL_EFF1(mh_debug_reg24_reg, kill_eff1) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG24_SET_TCD_NEARFULL_q(mh_debug_reg24_reg, tcd_nearfull_q) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG24_SET_TC_ARB_HOLD(mh_debug_reg24_reg, tc_arb_hold) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_HOLD(mh_debug_reg24_reg, arb_hold) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG24_SET_ARB_RTR_q(mh_debug_reg24_reg, arb_rtr_q) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG24_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24_reg, same_page_limit_count_q) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int eff1_winner                    : MH_DEBUG_REG24_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG24_ARB_WINNER_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG24_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG24_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG24_KILL_EFF1_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG24_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG24_ARB_RTR_q_SIZE;
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+     } mh_debug_reg24_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG24_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG24_ARB_HOLD_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG24_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG24_EFF1_WIN_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG24_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG24_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG24_EFF1_WINNER_SIZE;
+     } mh_debug_reg24_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg24_t f;
+} mh_debug_reg24_u;
+
+
+/*
+ * MH_DEBUG_REG25 struct
+ */
+
+#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG25_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE 3
+#define MH_DEBUG_REG25_LEAST_RECENT_d_SIZE 3
+#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE 1
+#define MH_DEBUG_REG25_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG25_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG25_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG25_CLNT_REQ_SIZE   4
+#define MH_DEBUG_REG25_RECENT_d_0_SIZE 3
+#define MH_DEBUG_REG25_RECENT_d_1_SIZE 3
+#define MH_DEBUG_REG25_RECENT_d_2_SIZE 3
+#define MH_DEBUG_REG25_RECENT_d_3_SIZE 3
+
+#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT 0
+#define MH_DEBUG_REG25_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT 6
+#define MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT 9
+#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT 12
+#define MH_DEBUG_REG25_ARB_HOLD_SHIFT  13
+#define MH_DEBUG_REG25_ARB_RTR_q_SHIFT 14
+#define MH_DEBUG_REG25_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG25_CLNT_REQ_SHIFT  16
+#define MH_DEBUG_REG25_RECENT_d_0_SHIFT 20
+#define MH_DEBUG_REG25_RECENT_d_1_SHIFT 23
+#define MH_DEBUG_REG25_RECENT_d_2_SHIFT 26
+#define MH_DEBUG_REG25_RECENT_d_3_SHIFT 29
+
+#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK 0x00000007
+#define MH_DEBUG_REG25_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK 0x000001c0
+#define MH_DEBUG_REG25_LEAST_RECENT_d_MASK 0x00000e00
+#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK 0x00001000
+#define MH_DEBUG_REG25_ARB_HOLD_MASK   0x00002000
+#define MH_DEBUG_REG25_ARB_RTR_q_MASK  0x00004000
+#define MH_DEBUG_REG25_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG25_CLNT_REQ_MASK   0x000f0000
+#define MH_DEBUG_REG25_RECENT_d_0_MASK 0x00700000
+#define MH_DEBUG_REG25_RECENT_d_1_MASK 0x03800000
+#define MH_DEBUG_REG25_RECENT_d_2_MASK 0x1c000000
+#define MH_DEBUG_REG25_RECENT_d_3_MASK 0xe0000000
+
+#define MH_DEBUG_REG25_MASK \
+     (MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG25_ARB_WINNER_MASK | \
+      MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK | \
+      MH_DEBUG_REG25_LEAST_RECENT_d_MASK | \
+      MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK | \
+      MH_DEBUG_REG25_ARB_HOLD_MASK | \
+      MH_DEBUG_REG25_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG25_EFF1_WIN_MASK | \
+      MH_DEBUG_REG25_CLNT_REQ_MASK | \
+      MH_DEBUG_REG25_RECENT_d_0_MASK | \
+      MH_DEBUG_REG25_RECENT_d_1_MASK | \
+      MH_DEBUG_REG25_RECENT_d_2_MASK | \
+      MH_DEBUG_REG25_RECENT_d_3_MASK)
+
+#define MH_DEBUG_REG25(eff2_lru_winner_out, arb_winner, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, eff1_win, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3) \
+     ((eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT) | \
+      (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) | \
+      (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) | \
+      (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT) | \
+      (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT) | \
+      (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT) | \
+      (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT) | \
+      (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT) | \
+      (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT))
+
+#define MH_DEBUG_REG25_GET_EFF2_LRU_WINNER_out(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG25_GET_ARB_WINNER(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_WINNER_MASK) >> MH_DEBUG_REG25_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG25_GET_LEAST_RECENT_INDEX_d(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG25_GET_LEAST_RECENT_d(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG25_GET_UPDATE_RECENT_STACK_d(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG25_GET_ARB_HOLD(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_HOLD_MASK) >> MH_DEBUG_REG25_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG25_GET_ARB_RTR_q(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_RTR_q_MASK) >> MH_DEBUG_REG25_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG25_GET_EFF1_WIN(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_EFF1_WIN_MASK) >> MH_DEBUG_REG25_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG25_GET_CLNT_REQ(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_CLNT_REQ_MASK) >> MH_DEBUG_REG25_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_0(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_0_MASK) >> MH_DEBUG_REG25_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_1(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_1_MASK) >> MH_DEBUG_REG25_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_2(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_2_MASK) >> MH_DEBUG_REG25_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG25_GET_RECENT_d_3(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_3_MASK) >> MH_DEBUG_REG25_RECENT_d_3_SHIFT)
+
+#define MH_DEBUG_REG25_SET_EFF2_LRU_WINNER_out(mh_debug_reg25_reg, eff2_lru_winner_out) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG25_SET_ARB_WINNER(mh_debug_reg25_reg, arb_winner) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG25_SET_LEAST_RECENT_INDEX_d(mh_debug_reg25_reg, least_recent_index_d) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG25_SET_LEAST_RECENT_d(mh_debug_reg25_reg, least_recent_d) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG25_SET_UPDATE_RECENT_STACK_d(mh_debug_reg25_reg, update_recent_stack_d) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG25_SET_ARB_HOLD(mh_debug_reg25_reg, arb_hold) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG25_SET_ARB_RTR_q(mh_debug_reg25_reg, arb_rtr_q) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG25_SET_EFF1_WIN(mh_debug_reg25_reg, eff1_win) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG25_SET_CLNT_REQ(mh_debug_reg25_reg, clnt_req) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_0(mh_debug_reg25_reg, recent_d_0) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_1(mh_debug_reg25_reg, recent_d_1) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_2(mh_debug_reg25_reg, recent_d_2) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG25_SET_RECENT_d_3(mh_debug_reg25_reg, recent_d_3) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG25_ARB_WINNER_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG25_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG25_ARB_RTR_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG25_EFF1_WIN_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG25_CLNT_REQ_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG25_RECENT_d_0_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG25_RECENT_d_1_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG25_RECENT_d_2_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG25_RECENT_d_3_SIZE;
+     } mh_debug_reg25_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int recent_d_3                     : MH_DEBUG_REG25_RECENT_d_3_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG25_RECENT_d_2_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG25_RECENT_d_1_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG25_RECENT_d_0_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG25_CLNT_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG25_EFF1_WIN_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG25_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG25_ARB_HOLD_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG25_ARB_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE;
+     } mh_debug_reg25_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg25_t f;
+} mh_debug_reg25_u;
+
+
+/*
+ * MH_DEBUG_REG26 struct
+ */
+
+#define MH_DEBUG_REG26_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG26_TCHOLD_IP_q_SIZE 1
+#define MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE 3
+#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE 7
+#define MH_DEBUG_REG26_WBURST_ACTIVE_SIZE 1
+#define MH_DEBUG_REG26_WLAST_q_SIZE    1
+#define MH_DEBUG_REG26_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG26_WBURST_CNT_q_SIZE 3
+#define MH_DEBUG_REG26_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG26_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG26_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG26_ARB_WINNER_SIZE 3
+
+#define MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT 0
+#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT 1
+#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT 2
+#define MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT 3
+#define MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT 4
+#define MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT 5
+#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 9
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 10
+#define MH_DEBUG_REG26_TC_MH_written_SHIFT 11
+#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT 12
+#define MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT 19
+#define MH_DEBUG_REG26_WLAST_q_SHIFT   20
+#define MH_DEBUG_REG26_WBURST_IP_q_SHIFT 21
+#define MH_DEBUG_REG26_WBURST_CNT_q_SHIFT 22
+#define MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT 25
+#define MH_DEBUG_REG26_CP_MH_write_SHIFT 26
+#define MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT 27
+#define MH_DEBUG_REG26_ARB_WINNER_SHIFT 28
+
+#define MH_DEBUG_REG26_TC_ARB_HOLD_MASK 0x00000001
+#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002
+#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004
+#define MH_DEBUG_REG26_TCD_NEARFULL_q_MASK 0x00000008
+#define MH_DEBUG_REG26_TCHOLD_IP_q_MASK 0x00000010
+#define MH_DEBUG_REG26_TCHOLD_CNT_q_MASK 0x000000e0
+#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00000200
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00000400
+#define MH_DEBUG_REG26_TC_MH_written_MASK 0x00000800
+#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK 0x0007f000
+#define MH_DEBUG_REG26_WBURST_ACTIVE_MASK 0x00080000
+#define MH_DEBUG_REG26_WLAST_q_MASK    0x00100000
+#define MH_DEBUG_REG26_WBURST_IP_q_MASK 0x00200000
+#define MH_DEBUG_REG26_WBURST_CNT_q_MASK 0x01c00000
+#define MH_DEBUG_REG26_CP_SEND_QUAL_MASK 0x02000000
+#define MH_DEBUG_REG26_CP_MH_write_MASK 0x04000000
+#define MH_DEBUG_REG26_RB_SEND_QUAL_MASK 0x08000000
+#define MH_DEBUG_REG26_ARB_WINNER_MASK 0x70000000
+
+#define MH_DEBUG_REG26_MASK \
+     (MH_DEBUG_REG26_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG26_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG26_TCHOLD_IP_q_MASK | \
+      MH_DEBUG_REG26_TCHOLD_CNT_q_MASK | \
+      MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG26_TC_MH_written_MASK | \
+      MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK | \
+      MH_DEBUG_REG26_WBURST_ACTIVE_MASK | \
+      MH_DEBUG_REG26_WLAST_q_MASK | \
+      MH_DEBUG_REG26_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG26_WBURST_CNT_q_MASK | \
+      MH_DEBUG_REG26_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG26_CP_MH_write_MASK | \
+      MH_DEBUG_REG26_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG26_ARB_WINNER_MASK)
+
+#define MH_DEBUG_REG26(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, arb_winner) \
+     ((tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) | \
+      (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \
+      (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) | \
+      (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) | \
+      (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT) | \
+      (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) | \
+      (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT) | \
+      (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT))
+
+#define MH_DEBUG_REG26_GET_TC_ARB_HOLD(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_NEARFULL_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCHOLD_IP_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCHOLD_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_MH_written(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_MH_written_MASK) >> MH_DEBUG_REG26_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_FULLNESS_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_WBURST_ACTIVE(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG26_GET_WLAST_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WLAST_q_MASK) >> MH_DEBUG_REG26_WLAST_q_SHIFT)
+#define MH_DEBUG_REG26_GET_WBURST_IP_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_IP_q_MASK) >> MH_DEBUG_REG26_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG26_GET_WBURST_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_CNT_q_MASK) >> MH_DEBUG_REG26_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_SEND_QUAL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_MH_write(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_MH_write_MASK) >> MH_DEBUG_REG26_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_SEND_QUAL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_GET_ARB_WINNER(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_ARB_WINNER_MASK) >> MH_DEBUG_REG26_ARB_WINNER_SHIFT)
+
+#define MH_DEBUG_REG26_SET_TC_ARB_HOLD(mh_debug_reg26_reg, tc_arb_hold) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_noroq_same_row_bank) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_roq_same_row_bank) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_NEARFULL_q(mh_debug_reg26_reg, tcd_nearfull_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCHOLD_IP_q(mh_debug_reg26_reg, tchold_ip_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCHOLD_CNT_q(mh_debug_reg26_reg, tchold_cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26_reg, mh_arbiter_config_tc_reorder_enable) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_MH_written(mh_debug_reg26_reg, tc_mh_written) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_FULLNESS_CNT_q(mh_debug_reg26_reg, tcd_fullness_cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_WBURST_ACTIVE(mh_debug_reg26_reg, wburst_active) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG26_SET_WLAST_q(mh_debug_reg26_reg, wlast_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT)
+#define MH_DEBUG_REG26_SET_WBURST_IP_q(mh_debug_reg26_reg, wburst_ip_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG26_SET_WBURST_CNT_q(mh_debug_reg26_reg, wburst_cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_SEND_QUAL(mh_debug_reg26_reg, cp_send_qual) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_MH_write(mh_debug_reg26_reg, cp_mh_write) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_SEND_QUAL(mh_debug_reg26_reg, rb_send_qual) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG26_SET_ARB_WINNER(mh_debug_reg26_reg, arb_winner) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG26_TC_MH_written_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG26_WLAST_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG26_WBURST_IP_q_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG26_WBURST_CNT_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG26_CP_MH_write_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG26_ARB_WINNER_SIZE;
+          unsigned int                                : 1;
+     } mh_debug_reg26_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int                                : 1;
+          unsigned int arb_winner                     : MH_DEBUG_REG26_ARB_WINNER_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG26_CP_MH_write_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG26_WBURST_CNT_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG26_WBURST_IP_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG26_WLAST_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG26_TC_MH_written_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE;
+     } mh_debug_reg26_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg26_t f;
+} mh_debug_reg26_u;
+
+
+/*
+ * MH_DEBUG_REG27 struct
+ */
+
+#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE 26
+#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26
+
+#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK 0x03ffffff
+#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000
+
+#define MH_DEBUG_REG27_MASK \
+     (MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK | \
+      MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG27(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \
+     ((rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG27_GET_RF_ARBITER_CONFIG_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG27_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG27_SET_RF_ARBITER_CONFIG_q(mh_debug_reg27_reg, rf_arbiter_config_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG27_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg27_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int                                : 3;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE;
+     } mh_debug_reg27_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg27_t f;
+} mh_debug_reg27_u;
+
+
+/*
+ * MH_DEBUG_REG28 struct
+ */
+
+#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG28_ROQ_MARK_q_SIZE 8
+#define MH_DEBUG_REG28_ROQ_VALID_q_SIZE 8
+#define MH_DEBUG_REG28_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG28_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG28_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG28_ROQ_MARK_q_SHIFT 8
+#define MH_DEBUG_REG28_ROQ_VALID_q_SHIFT 16
+#define MH_DEBUG_REG28_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG28_ROQ_MARK_q_MASK 0x0000ff00
+#define MH_DEBUG_REG28_ROQ_VALID_q_MASK 0x00ff0000
+#define MH_DEBUG_REG28_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG28_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG28_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG28_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG28_MASK \
+     (MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG28_ROQ_MARK_q_MASK | \
+      MH_DEBUG_REG28_ROQ_VALID_q_MASK | \
+      MH_DEBUG_REG28_TC_MH_send_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG28_KILL_EFF1_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG28_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG28_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG28(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) | \
+      (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG28_GET_SAME_ROW_BANK_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG28_GET_ROQ_MARK_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_MARK_q_MASK) >> MH_DEBUG_REG28_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG28_GET_ROQ_VALID_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_VALID_q_MASK) >> MH_DEBUG_REG28_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_MH_send(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_MH_send_MASK) >> MH_DEBUG_REG28_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_RTR_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG28_GET_ANY_SAME_ROW_BANK(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_EFF1_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_EMPTY(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ROQ_FULL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG28_SET_SAME_ROW_BANK_q(mh_debug_reg28_reg, same_row_bank_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG28_SET_ROQ_MARK_q(mh_debug_reg28_reg, roq_mark_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG28_SET_ROQ_VALID_q(mh_debug_reg28_reg, roq_valid_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_MH_send(mh_debug_reg28_reg, tc_mh_send) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_RTR_q(mh_debug_reg28_reg, tc_roq_rtr_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG28_SET_ANY_SAME_ROW_BANK(mh_debug_reg28_reg, any_same_row_bank) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_EFF1_QUAL(mh_debug_reg28_reg, tc_eff1_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_EMPTY(mh_debug_reg28_reg, tc_roq_empty) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ROQ_FULL(mh_debug_reg28_reg, tc_roq_full) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG28_ROQ_MARK_q_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG28_ROQ_VALID_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG28_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg28_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG28_TC_MH_send_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG28_ROQ_VALID_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG28_ROQ_MARK_q_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg28_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg28_t f;
+} mh_debug_reg28_u;
+
+
+/*
+ * MH_DEBUG_REG29 struct
+ */
+
+#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG29_ROQ_MARK_d_SIZE 8
+#define MH_DEBUG_REG29_ROQ_VALID_d_SIZE 8
+#define MH_DEBUG_REG29_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG29_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG29_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG29_ROQ_MARK_d_SHIFT 8
+#define MH_DEBUG_REG29_ROQ_VALID_d_SHIFT 16
+#define MH_DEBUG_REG29_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG29_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG29_ROQ_MARK_d_MASK 0x0000ff00
+#define MH_DEBUG_REG29_ROQ_VALID_d_MASK 0x00ff0000
+#define MH_DEBUG_REG29_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG29_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG29_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG29_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG29_MASK \
+     (MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG29_ROQ_MARK_d_MASK | \
+      MH_DEBUG_REG29_ROQ_VALID_d_MASK | \
+      MH_DEBUG_REG29_TC_MH_send_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG29_KILL_EFF1_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG29_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG29_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG29(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) | \
+      (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG29_GET_SAME_ROW_BANK_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG29_GET_ROQ_MARK_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_MARK_d_MASK) >> MH_DEBUG_REG29_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG29_GET_ROQ_VALID_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_VALID_d_MASK) >> MH_DEBUG_REG29_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_MH_send(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_MH_send_MASK) >> MH_DEBUG_REG29_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_RTR_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_GET_KILL_EFF1(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_KILL_EFF1_MASK) >> MH_DEBUG_REG29_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG29_GET_ANY_SAME_ROW_BANK(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_EFF1_QUAL(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_EMPTY(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG29_GET_TC_ROQ_FULL(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG29_SET_SAME_ROW_BANK_q(mh_debug_reg29_reg, same_row_bank_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG29_SET_ROQ_MARK_d(mh_debug_reg29_reg, roq_mark_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG29_SET_ROQ_VALID_d(mh_debug_reg29_reg, roq_valid_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_MH_send(mh_debug_reg29_reg, tc_mh_send) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_RTR_q(mh_debug_reg29_reg, tc_roq_rtr_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_SET_KILL_EFF1(mh_debug_reg29_reg, kill_eff1) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG29_SET_ANY_SAME_ROW_BANK(mh_debug_reg29_reg, any_same_row_bank) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_EFF1_QUAL(mh_debug_reg29_reg, tc_eff1_qual) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_EMPTY(mh_debug_reg29_reg, tc_roq_empty) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG29_SET_TC_ROQ_FULL(mh_debug_reg29_reg, tc_roq_full) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG29_ROQ_MARK_d_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG29_ROQ_VALID_d_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG29_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG29_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg29_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG29_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG29_TC_MH_send_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG29_ROQ_VALID_d_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG29_ROQ_MARK_d_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg29_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg29_t f;
+} mh_debug_reg29_u;
+
+
+/*
+ * MH_DEBUG_REG30 struct
+ */
+
+#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE 8
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE 8
+
+#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT 0
+#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT 8
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT 16
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT 24
+
+#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK 0x000000ff
+#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK 0x0000ff00
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000
+#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK 0xff000000
+
+#define MH_DEBUG_REG30_MASK \
+     (MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK | \
+      MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK)
+
+#define MH_DEBUG_REG30(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \
+     ((same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) | \
+      (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) | \
+      (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) | \
+      (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT))
+
+#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_WIN(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_REQ(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, same_row_bank_win) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, same_row_bank_req) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, non_same_row_bank_win) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, non_same_row_bank_req) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int same_row_bank_win              : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE;
+     } mh_debug_reg30_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int same_row_bank_win              : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE;
+     } mh_debug_reg30_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg30_t f;
+} mh_debug_reg30_u;
+
+
+/*
+ * MH_DEBUG_REG31 struct
+ */
+
+#define MH_DEBUG_REG31_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE 1
+#define MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE 1
+#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE 1
+#define MH_DEBUG_REG31_ROQ_ADDR_0_SIZE 27
+
+#define MH_DEBUG_REG31_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT 2
+#define MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT 3
+#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT 4
+#define MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT 5
+
+#define MH_DEBUG_REG31_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG31_ROQ_MARK_q_0_MASK 0x00000004
+#define MH_DEBUG_REG31_ROQ_VALID_q_0_MASK 0x00000008
+#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK 0x00000010
+#define MH_DEBUG_REG31_ROQ_ADDR_0_MASK 0xffffffe0
+
+#define MH_DEBUG_REG31_MASK \
+     (MH_DEBUG_REG31_TC_MH_send_MASK | \
+      MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG31_ROQ_MARK_q_0_MASK | \
+      MH_DEBUG_REG31_ROQ_VALID_q_0_MASK | \
+      MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK | \
+      MH_DEBUG_REG31_ROQ_ADDR_0_MASK)
+
+#define MH_DEBUG_REG31(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \
+     ((tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) | \
+      (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) | \
+      (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) | \
+      (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT))
+
+#define MH_DEBUG_REG31_GET_TC_MH_send(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_TC_MH_send_MASK) >> MH_DEBUG_REG31_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG31_GET_TC_ROQ_RTR_q(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG31_GET_ROQ_MARK_q_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG31_GET_ROQ_VALID_q_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG31_GET_SAME_ROW_BANK_q_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG31_GET_ROQ_ADDR_0(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT)
+
+#define MH_DEBUG_REG31_SET_TC_MH_send(mh_debug_reg31_reg, tc_mh_send) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG31_SET_TC_ROQ_RTR_q(mh_debug_reg31_reg, tc_roq_rtr_q) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG31_SET_ROQ_MARK_q_0(mh_debug_reg31_reg, roq_mark_q_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG31_SET_ROQ_VALID_q_0(mh_debug_reg31_reg, roq_valid_q_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG31_SET_SAME_ROW_BANK_q_0(mh_debug_reg31_reg, same_row_bank_q_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG31_SET_ROQ_ADDR_0(mh_debug_reg31_reg, roq_addr_0) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG31_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_addr_0                     : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE;
+     } mh_debug_reg31_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int roq_addr_0                     : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG31_TC_MH_send_SIZE;
+     } mh_debug_reg31_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg31_t f;
+} mh_debug_reg31_u;
+
+
+/*
+ * MH_DEBUG_REG32 struct
+ */
+
+#define MH_DEBUG_REG32_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE 1
+#define MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE 1
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE 1
+#define MH_DEBUG_REG32_ROQ_ADDR_1_SIZE 27
+
+#define MH_DEBUG_REG32_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT 2
+#define MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT 3
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT 4
+#define MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT 5
+
+#define MH_DEBUG_REG32_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG32_ROQ_MARK_q_1_MASK 0x00000004
+#define MH_DEBUG_REG32_ROQ_VALID_q_1_MASK 0x00000008
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK 0x00000010
+#define MH_DEBUG_REG32_ROQ_ADDR_1_MASK 0xffffffe0
+
+#define MH_DEBUG_REG32_MASK \
+     (MH_DEBUG_REG32_TC_MH_send_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG32_ROQ_MARK_q_1_MASK | \
+      MH_DEBUG_REG32_ROQ_VALID_q_1_MASK | \
+      MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK | \
+      MH_DEBUG_REG32_ROQ_ADDR_1_MASK)
+
+#define MH_DEBUG_REG32(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \
+     ((tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) | \
+      (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) | \
+      (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) | \
+      (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT))
+
+#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_MARK_q_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_VALID_q_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_ADDR_1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT)
+
+#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_MARK_q_1(mh_debug_reg32_reg, roq_mark_q_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_VALID_q_1(mh_debug_reg32_reg, roq_valid_q_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q_1(mh_debug_reg32_reg, same_row_bank_q_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_ADDR_1(mh_debug_reg32_reg, roq_addr_1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_addr_1                     : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE;
+     } mh_debug_reg32_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int roq_addr_1                     : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+     } mh_debug_reg32_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg32_t f;
+} mh_debug_reg32_u;
+
+
+/*
+ * MH_DEBUG_REG33 struct
+ */
+
+#define MH_DEBUG_REG33_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE 1
+#define MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE 1
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE 1
+#define MH_DEBUG_REG33_ROQ_ADDR_2_SIZE 27
+
+#define MH_DEBUG_REG33_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT 2
+#define MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT 3
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT 4
+#define MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT 5
+
+#define MH_DEBUG_REG33_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG33_ROQ_MARK_q_2_MASK 0x00000004
+#define MH_DEBUG_REG33_ROQ_VALID_q_2_MASK 0x00000008
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK 0x00000010
+#define MH_DEBUG_REG33_ROQ_ADDR_2_MASK 0xffffffe0
+
+#define MH_DEBUG_REG33_MASK \
+     (MH_DEBUG_REG33_TC_MH_send_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG33_ROQ_MARK_q_2_MASK | \
+      MH_DEBUG_REG33_ROQ_VALID_q_2_MASK | \
+      MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK | \
+      MH_DEBUG_REG33_ROQ_ADDR_2_MASK)
+
+#define MH_DEBUG_REG33(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \
+     ((tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) | \
+      (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) | \
+      (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) | \
+      (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT))
+
+#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_MARK_q_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_VALID_q_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_ADDR_2(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT)
+
+#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_MARK_q_2(mh_debug_reg33_reg, roq_mark_q_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_VALID_q_2(mh_debug_reg33_reg, roq_valid_q_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q_2(mh_debug_reg33_reg, same_row_bank_q_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_ADDR_2(mh_debug_reg33_reg, roq_addr_2) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_addr_2                     : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE;
+     } mh_debug_reg33_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int roq_addr_2                     : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+     } mh_debug_reg33_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg33_t f;
+} mh_debug_reg33_u;
+
+
+/*
+ * MH_DEBUG_REG34 struct
+ */
+
+#define MH_DEBUG_REG34_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE 1
+#define MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE 1
+#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE 1
+#define MH_DEBUG_REG34_ROQ_ADDR_3_SIZE 27
+
+#define MH_DEBUG_REG34_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT 2
+#define MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT 3
+#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT 4
+#define MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT 5
+
+#define MH_DEBUG_REG34_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG34_ROQ_MARK_q_3_MASK 0x00000004
+#define MH_DEBUG_REG34_ROQ_VALID_q_3_MASK 0x00000008
+#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK 0x00000010
+#define MH_DEBUG_REG34_ROQ_ADDR_3_MASK 0xffffffe0
+
+#define MH_DEBUG_REG34_MASK \
+     (MH_DEBUG_REG34_TC_MH_send_MASK | \
+      MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG34_ROQ_MARK_q_3_MASK | \
+      MH_DEBUG_REG34_ROQ_VALID_q_3_MASK | \
+      MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK | \
+      MH_DEBUG_REG34_ROQ_ADDR_3_MASK)
+
+#define MH_DEBUG_REG34(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \
+     ((tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) | \
+      (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) | \
+      (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) | \
+      (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT))
+
+#define MH_DEBUG_REG34_GET_TC_MH_send(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_TC_MH_send_MASK) >> MH_DEBUG_REG34_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG34_GET_TC_ROQ_RTR_q(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG34_GET_ROQ_MARK_q_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG34_GET_ROQ_VALID_q_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_q_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG34_GET_ROQ_ADDR_3(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT)
+
+#define MH_DEBUG_REG34_SET_TC_MH_send(mh_debug_reg34_reg, tc_mh_send) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG34_SET_TC_ROQ_RTR_q(mh_debug_reg34_reg, tc_roq_rtr_q) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG34_SET_ROQ_MARK_q_3(mh_debug_reg34_reg, roq_mark_q_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG34_SET_ROQ_VALID_q_3(mh_debug_reg34_reg, roq_valid_q_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_q_3(mh_debug_reg34_reg, same_row_bank_q_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG34_SET_ROQ_ADDR_3(mh_debug_reg34_reg, roq_addr_3) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG34_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_addr_3                     : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE;
+     } mh_debug_reg34_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int roq_addr_3                     : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG34_TC_MH_send_SIZE;
+     } mh_debug_reg34_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg34_t f;
+} mh_debug_reg34_u;
+
+
+/*
+ * MH_DEBUG_REG35 struct
+ */
+
+#define MH_DEBUG_REG35_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE 1
+#define MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE 1
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE 1
+#define MH_DEBUG_REG35_ROQ_ADDR_4_SIZE 27
+
+#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT 2
+#define MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT 3
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT 4
+#define MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT 5
+
+#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG35_ROQ_MARK_q_4_MASK 0x00000004
+#define MH_DEBUG_REG35_ROQ_VALID_q_4_MASK 0x00000008
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK 0x00000010
+#define MH_DEBUG_REG35_ROQ_ADDR_4_MASK 0xffffffe0
+
+#define MH_DEBUG_REG35_MASK \
+     (MH_DEBUG_REG35_TC_MH_send_MASK | \
+      MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG35_ROQ_MARK_q_4_MASK | \
+      MH_DEBUG_REG35_ROQ_VALID_q_4_MASK | \
+      MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK | \
+      MH_DEBUG_REG35_ROQ_ADDR_4_MASK)
+
+#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \
+     ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) | \
+      (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) | \
+      (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) | \
+      (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT))
+
+#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_MARK_q_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_VALID_q_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_ADDR_4(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT)
+
+#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_MARK_q_4(mh_debug_reg35_reg, roq_mark_q_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_VALID_q_4(mh_debug_reg35_reg, roq_valid_q_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_4(mh_debug_reg35_reg, same_row_bank_q_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_ADDR_4(mh_debug_reg35_reg, roq_addr_4) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_addr_4                     : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE;
+     } mh_debug_reg35_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int roq_addr_4                     : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+     } mh_debug_reg35_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg35_t f;
+} mh_debug_reg35_u;
+
+
+/*
+ * MH_DEBUG_REG36 struct
+ */
+
+#define MH_DEBUG_REG36_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE 1
+#define MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE 1
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE 1
+#define MH_DEBUG_REG36_ROQ_ADDR_5_SIZE 27
+
+#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT 2
+#define MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT 3
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT 4
+#define MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT 5
+
+#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG36_ROQ_MARK_q_5_MASK 0x00000004
+#define MH_DEBUG_REG36_ROQ_VALID_q_5_MASK 0x00000008
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK 0x00000010
+#define MH_DEBUG_REG36_ROQ_ADDR_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG36_MASK \
+     (MH_DEBUG_REG36_TC_MH_send_MASK | \
+      MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG36_ROQ_MARK_q_5_MASK | \
+      MH_DEBUG_REG36_ROQ_VALID_q_5_MASK | \
+      MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK | \
+      MH_DEBUG_REG36_ROQ_ADDR_5_MASK)
+
+#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \
+     ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) | \
+      (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) | \
+      (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) | \
+      (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT))
+
+#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_MARK_q_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_VALID_q_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_ADDR_5(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT)
+
+#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_MARK_q_5(mh_debug_reg36_reg, roq_mark_q_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_VALID_q_5(mh_debug_reg36_reg, roq_valid_q_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_5(mh_debug_reg36_reg, same_row_bank_q_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_ADDR_5(mh_debug_reg36_reg, roq_addr_5) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_addr_5                     : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE;
+     } mh_debug_reg36_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int roq_addr_5                     : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+     } mh_debug_reg36_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg36_t f;
+} mh_debug_reg36_u;
+
+
+/*
+ * MH_DEBUG_REG37 struct
+ */
+
+#define MH_DEBUG_REG37_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE 1
+#define MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE 1
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE 1
+#define MH_DEBUG_REG37_ROQ_ADDR_6_SIZE 27
+
+#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT 2
+#define MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT 3
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT 4
+#define MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT 5
+
+#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG37_ROQ_MARK_q_6_MASK 0x00000004
+#define MH_DEBUG_REG37_ROQ_VALID_q_6_MASK 0x00000008
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK 0x00000010
+#define MH_DEBUG_REG37_ROQ_ADDR_6_MASK 0xffffffe0
+
+#define MH_DEBUG_REG37_MASK \
+     (MH_DEBUG_REG37_TC_MH_send_MASK | \
+      MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG37_ROQ_MARK_q_6_MASK | \
+      MH_DEBUG_REG37_ROQ_VALID_q_6_MASK | \
+      MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK | \
+      MH_DEBUG_REG37_ROQ_ADDR_6_MASK)
+
+#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \
+     ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) | \
+      (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) | \
+      (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) | \
+      (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT))
+
+#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_MARK_q_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_VALID_q_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_ADDR_6(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT)
+
+#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_MARK_q_6(mh_debug_reg37_reg, roq_mark_q_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_VALID_q_6(mh_debug_reg37_reg, roq_valid_q_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_6(mh_debug_reg37_reg, same_row_bank_q_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_ADDR_6(mh_debug_reg37_reg, roq_addr_6) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_addr_6                     : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE;
+     } mh_debug_reg37_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int roq_addr_6                     : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+     } mh_debug_reg37_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg37_t f;
+} mh_debug_reg37_u;
+
+
+/*
+ * MH_DEBUG_REG38 struct
+ */
+
+#define MH_DEBUG_REG38_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE 1
+#define MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE 1
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE 1
+#define MH_DEBUG_REG38_ROQ_ADDR_7_SIZE 27
+
+#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT 2
+#define MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT 3
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT 4
+#define MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT 5
+
+#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG38_ROQ_MARK_q_7_MASK 0x00000004
+#define MH_DEBUG_REG38_ROQ_VALID_q_7_MASK 0x00000008
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK 0x00000010
+#define MH_DEBUG_REG38_ROQ_ADDR_7_MASK 0xffffffe0
+
+#define MH_DEBUG_REG38_MASK \
+     (MH_DEBUG_REG38_TC_MH_send_MASK | \
+      MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG38_ROQ_MARK_q_7_MASK | \
+      MH_DEBUG_REG38_ROQ_VALID_q_7_MASK | \
+      MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK | \
+      MH_DEBUG_REG38_ROQ_ADDR_7_MASK)
+
+#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \
+     ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) | \
+      (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) | \
+      (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) | \
+      (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT))
+
+#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_MARK_q_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_VALID_q_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_ADDR_7(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT)
+
+#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_MARK_q_7(mh_debug_reg38_reg, roq_mark_q_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_VALID_q_7(mh_debug_reg38_reg, roq_valid_q_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_7(mh_debug_reg38_reg, same_row_bank_q_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_ADDR_7(mh_debug_reg38_reg, roq_addr_7) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_addr_7                     : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE;
+     } mh_debug_reg38_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int roq_addr_7                     : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+     } mh_debug_reg38_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg38_t f;
+} mh_debug_reg38_u;
+
+
+/*
+ * MH_DEBUG_REG39 struct
+ */
+
+#define MH_DEBUG_REG39_ARB_WE_SIZE     1
+#define MH_DEBUG_REG39_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG39_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG39_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG39_ARB_BLEN_q_SIZE 1
+#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE 3
+#define MH_DEBUG_REG39_MMU_WE_SIZE     1
+#define MH_DEBUG_REG39_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG39_MMU_ID_SIZE     3
+#define MH_DEBUG_REG39_MMU_WRITE_SIZE  1
+#define MH_DEBUG_REG39_MMU_BLEN_SIZE   1
+
+#define MH_DEBUG_REG39_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG39_MMU_RTR_SHIFT   1
+#define MH_DEBUG_REG39_ARB_ID_q_SHIFT  2
+#define MH_DEBUG_REG39_ARB_WRITE_q_SHIFT 5
+#define MH_DEBUG_REG39_ARB_BLEN_q_SHIFT 6
+#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT 7
+#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT 8
+#define MH_DEBUG_REG39_MMU_WE_SHIFT    11
+#define MH_DEBUG_REG39_ARQ_RTR_SHIFT   12
+#define MH_DEBUG_REG39_MMU_ID_SHIFT    13
+#define MH_DEBUG_REG39_MMU_WRITE_SHIFT 16
+#define MH_DEBUG_REG39_MMU_BLEN_SHIFT  17
+
+#define MH_DEBUG_REG39_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG39_MMU_RTR_MASK    0x00000002
+#define MH_DEBUG_REG39_ARB_ID_q_MASK   0x0000001c
+#define MH_DEBUG_REG39_ARB_WRITE_q_MASK 0x00000020
+#define MH_DEBUG_REG39_ARB_BLEN_q_MASK 0x00000040
+#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK 0x00000080
+#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK 0x00000700
+#define MH_DEBUG_REG39_MMU_WE_MASK     0x00000800
+#define MH_DEBUG_REG39_ARQ_RTR_MASK    0x00001000
+#define MH_DEBUG_REG39_MMU_ID_MASK     0x0000e000
+#define MH_DEBUG_REG39_MMU_WRITE_MASK  0x00010000
+#define MH_DEBUG_REG39_MMU_BLEN_MASK   0x00020000
+
+#define MH_DEBUG_REG39_MASK \
+     (MH_DEBUG_REG39_ARB_WE_MASK | \
+      MH_DEBUG_REG39_MMU_RTR_MASK | \
+      MH_DEBUG_REG39_ARB_ID_q_MASK | \
+      MH_DEBUG_REG39_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG39_ARB_BLEN_q_MASK | \
+      MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG39_MMU_WE_MASK | \
+      MH_DEBUG_REG39_ARQ_RTR_MASK | \
+      MH_DEBUG_REG39_MMU_ID_MASK | \
+      MH_DEBUG_REG39_MMU_WRITE_MASK | \
+      MH_DEBUG_REG39_MMU_BLEN_MASK)
+
+#define MH_DEBUG_REG39(arb_we, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen) \
+     ((arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) | \
+      (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT) | \
+      (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT) | \
+      (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT) | \
+      (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT))
+
+#define MH_DEBUG_REG39_GET_ARB_WE(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WE_MASK) >> MH_DEBUG_REG39_ARB_WE_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_RTR(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_RTR_MASK) >> MH_DEBUG_REG39_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG39_GET_ARB_ID_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_ID_q_MASK) >> MH_DEBUG_REG39_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ARB_WRITE_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WRITE_q_MASK) >> MH_DEBUG_REG39_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ARB_BLEN_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_BLEN_q_MASK) >> MH_DEBUG_REG39_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ARQ_CTRL_EMPTY(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG39_GET_ARQ_FIFO_CNT_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_WE(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WE_MASK) >> MH_DEBUG_REG39_MMU_WE_SHIFT)
+#define MH_DEBUG_REG39_GET_ARQ_RTR(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_RTR_MASK) >> MH_DEBUG_REG39_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_ID(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_ID_MASK) >> MH_DEBUG_REG39_MMU_ID_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_WRITE(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WRITE_MASK) >> MH_DEBUG_REG39_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG39_GET_MMU_BLEN(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_BLEN_MASK) >> MH_DEBUG_REG39_MMU_BLEN_SHIFT)
+
+#define MH_DEBUG_REG39_SET_ARB_WE(mh_debug_reg39_reg, arb_we) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_RTR(mh_debug_reg39_reg, mmu_rtr) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG39_SET_ARB_ID_q(mh_debug_reg39_reg, arb_id_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ARB_WRITE_q(mh_debug_reg39_reg, arb_write_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ARB_BLEN_q(mh_debug_reg39_reg, arb_blen_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ARQ_CTRL_EMPTY(mh_debug_reg39_reg, arq_ctrl_empty) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG39_SET_ARQ_FIFO_CNT_q(mh_debug_reg39_reg, arq_fifo_cnt_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_WE(mh_debug_reg39_reg, mmu_we) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT)
+#define MH_DEBUG_REG39_SET_ARQ_RTR(mh_debug_reg39_reg, arq_rtr) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_ID(mh_debug_reg39_reg, mmu_id) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_WRITE(mh_debug_reg39_reg, mmu_write) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG39_SET_MMU_BLEN(mh_debug_reg39_reg, mmu_blen) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int arb_we                         : MH_DEBUG_REG39_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG39_MMU_RTR_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG39_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG39_ARB_WRITE_q_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG39_ARB_BLEN_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG39_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG39_ARQ_RTR_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG39_MMU_ID_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG39_MMU_WRITE_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG39_MMU_BLEN_SIZE;
+          unsigned int                                : 14;
+     } mh_debug_reg39_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int                                : 14;
+          unsigned int mmu_blen                       : MH_DEBUG_REG39_MMU_BLEN_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG39_MMU_WRITE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG39_MMU_ID_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG39_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG39_MMU_WE_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG39_ARB_BLEN_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG39_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG39_ARB_ID_q_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG39_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG39_ARB_WE_SIZE;
+     } mh_debug_reg39_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg39_t f;
+} mh_debug_reg39_u;
+
+
+/*
+ * MH_DEBUG_REG40 struct
+ */
+
+#define MH_DEBUG_REG40_ARB_WE_SIZE     1
+#define MH_DEBUG_REG40_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG40_ARB_VAD_q_SIZE  28
+
+#define MH_DEBUG_REG40_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG40_ARB_ID_q_SHIFT  1
+#define MH_DEBUG_REG40_ARB_VAD_q_SHIFT 4
+
+#define MH_DEBUG_REG40_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG40_ARB_ID_q_MASK   0x0000000e
+#define MH_DEBUG_REG40_ARB_VAD_q_MASK  0xfffffff0
+
+#define MH_DEBUG_REG40_MASK \
+     (MH_DEBUG_REG40_ARB_WE_MASK | \
+      MH_DEBUG_REG40_ARB_ID_q_MASK | \
+      MH_DEBUG_REG40_ARB_VAD_q_MASK)
+
+#define MH_DEBUG_REG40(arb_we, arb_id_q, arb_vad_q) \
+     ((arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT) | \
+      (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT))
+
+#define MH_DEBUG_REG40_GET_ARB_WE(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_WE_MASK) >> MH_DEBUG_REG40_ARB_WE_SHIFT)
+#define MH_DEBUG_REG40_GET_ARB_ID_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_ID_q_MASK) >> MH_DEBUG_REG40_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG40_GET_ARB_VAD_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_VAD_q_MASK) >> MH_DEBUG_REG40_ARB_VAD_q_SHIFT)
+
+#define MH_DEBUG_REG40_SET_ARB_WE(mh_debug_reg40_reg, arb_we) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT)
+#define MH_DEBUG_REG40_SET_ARB_ID_q(mh_debug_reg40_reg, arb_id_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG40_SET_ARB_VAD_q(mh_debug_reg40_reg, arb_vad_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int arb_we                         : MH_DEBUG_REG40_ARB_WE_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG40_ARB_ID_q_SIZE;
+          unsigned int arb_vad_q                      : MH_DEBUG_REG40_ARB_VAD_q_SIZE;
+     } mh_debug_reg40_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int arb_vad_q                      : MH_DEBUG_REG40_ARB_VAD_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG40_ARB_ID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG40_ARB_WE_SIZE;
+     } mh_debug_reg40_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg40_t f;
+} mh_debug_reg40_u;
+
+
+/*
+ * MH_DEBUG_REG41 struct
+ */
+
+#define MH_DEBUG_REG41_MMU_WE_SIZE     1
+#define MH_DEBUG_REG41_MMU_ID_SIZE     3
+#define MH_DEBUG_REG41_MMU_PAD_SIZE    28
+
+#define MH_DEBUG_REG41_MMU_WE_SHIFT    0
+#define MH_DEBUG_REG41_MMU_ID_SHIFT    1
+#define MH_DEBUG_REG41_MMU_PAD_SHIFT   4
+
+#define MH_DEBUG_REG41_MMU_WE_MASK     0x00000001
+#define MH_DEBUG_REG41_MMU_ID_MASK     0x0000000e
+#define MH_DEBUG_REG41_MMU_PAD_MASK    0xfffffff0
+
+#define MH_DEBUG_REG41_MASK \
+     (MH_DEBUG_REG41_MMU_WE_MASK | \
+      MH_DEBUG_REG41_MMU_ID_MASK | \
+      MH_DEBUG_REG41_MMU_PAD_MASK)
+
+#define MH_DEBUG_REG41(mmu_we, mmu_id, mmu_pad) \
+     ((mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT) | \
+      (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT))
+
+#define MH_DEBUG_REG41_GET_MMU_WE(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_WE_MASK) >> MH_DEBUG_REG41_MMU_WE_SHIFT)
+#define MH_DEBUG_REG41_GET_MMU_ID(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_ID_MASK) >> MH_DEBUG_REG41_MMU_ID_SHIFT)
+#define MH_DEBUG_REG41_GET_MMU_PAD(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_PAD_MASK) >> MH_DEBUG_REG41_MMU_PAD_SHIFT)
+
+#define MH_DEBUG_REG41_SET_MMU_WE(mh_debug_reg41_reg, mmu_we) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT)
+#define MH_DEBUG_REG41_SET_MMU_ID(mh_debug_reg41_reg, mmu_id) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT)
+#define MH_DEBUG_REG41_SET_MMU_PAD(mh_debug_reg41_reg, mmu_pad) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int mmu_we                         : MH_DEBUG_REG41_MMU_WE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG41_MMU_ID_SIZE;
+          unsigned int mmu_pad                        : MH_DEBUG_REG41_MMU_PAD_SIZE;
+     } mh_debug_reg41_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int mmu_pad                        : MH_DEBUG_REG41_MMU_PAD_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG41_MMU_ID_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG41_MMU_WE_SIZE;
+     } mh_debug_reg41_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg41_t f;
+} mh_debug_reg41_u;
+
+
+/*
+ * MH_DEBUG_REG42 struct
+ */
+
+#define MH_DEBUG_REG42_WDB_WE_SIZE     1
+#define MH_DEBUG_REG42_WDB_RTR_SKID_SIZE 1
+#define MH_DEBUG_REG42_ARB_WSTRB_q_SIZE 8
+#define MH_DEBUG_REG42_ARB_WLAST_SIZE  1
+#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE 5
+#define MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE 1
+#define MH_DEBUG_REG42_WDB_WDC_WID_SIZE 3
+#define MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE 1
+#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE 8
+
+#define MH_DEBUG_REG42_WDB_WE_SHIFT    0
+#define MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT 1
+#define MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT 2
+#define MH_DEBUG_REG42_ARB_WLAST_SHIFT 10
+#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT 11
+#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT 12
+#define MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT 17
+#define MH_DEBUG_REG42_WDB_WDC_WID_SHIFT 18
+#define MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT 21
+#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT 22
+
+#define MH_DEBUG_REG42_WDB_WE_MASK     0x00000001
+#define MH_DEBUG_REG42_WDB_RTR_SKID_MASK 0x00000002
+#define MH_DEBUG_REG42_ARB_WSTRB_q_MASK 0x000003fc
+#define MH_DEBUG_REG42_ARB_WLAST_MASK  0x00000400
+#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK 0x00000800
+#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK 0x0001f000
+#define MH_DEBUG_REG42_WDC_WDB_RE_q_MASK 0x00020000
+#define MH_DEBUG_REG42_WDB_WDC_WID_MASK 0x001c0000
+#define MH_DEBUG_REG42_WDB_WDC_WLAST_MASK 0x00200000
+#define MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK 0x3fc00000
+
+#define MH_DEBUG_REG42_MASK \
+     (MH_DEBUG_REG42_WDB_WE_MASK | \
+      MH_DEBUG_REG42_WDB_RTR_SKID_MASK | \
+      MH_DEBUG_REG42_ARB_WSTRB_q_MASK | \
+      MH_DEBUG_REG42_ARB_WLAST_MASK | \
+      MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG42_WDC_WDB_RE_q_MASK | \
+      MH_DEBUG_REG42_WDB_WDC_WID_MASK | \
+      MH_DEBUG_REG42_WDB_WDC_WLAST_MASK | \
+      MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK)
+
+#define MH_DEBUG_REG42(wdb_we, wdb_rtr_skid, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \
+     ((wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT) | \
+      (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) | \
+      (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) | \
+      (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT) | \
+      (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) | \
+      (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) | \
+      (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) | \
+      (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) | \
+      (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) | \
+      (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT))
+
+#define MH_DEBUG_REG42_GET_WDB_WE(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WE_MASK) >> MH_DEBUG_REG42_WDB_WE_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_RTR_SKID(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_RTR_SKID_MASK) >> MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT)
+#define MH_DEBUG_REG42_GET_ARB_WSTRB_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG42_GET_ARB_WLAST(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WLAST_MASK) >> MH_DEBUG_REG42_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_CTRL_EMPTY(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_FIFO_CNT_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG42_GET_WDC_WDB_RE_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_WDC_WID(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WID_MASK) >> MH_DEBUG_REG42_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_WDC_WLAST(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG42_GET_WDB_WDC_WSTRB(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT)
+
+#define MH_DEBUG_REG42_SET_WDB_WE(mh_debug_reg42_reg, wdb_we) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_RTR_SKID(mh_debug_reg42_reg, wdb_rtr_skid) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_RTR_SKID_MASK) | (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT)
+#define MH_DEBUG_REG42_SET_ARB_WSTRB_q(mh_debug_reg42_reg, arb_wstrb_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG42_SET_ARB_WLAST(mh_debug_reg42_reg, arb_wlast) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_CTRL_EMPTY(mh_debug_reg42_reg, wdb_ctrl_empty) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_FIFO_CNT_q(mh_debug_reg42_reg, wdb_fifo_cnt_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG42_SET_WDC_WDB_RE_q(mh_debug_reg42_reg, wdc_wdb_re_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_WDC_WID(mh_debug_reg42_reg, wdb_wdc_wid) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_WDC_WLAST(mh_debug_reg42_reg, wdb_wdc_wlast) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG42_SET_WDB_WDC_WSTRB(mh_debug_reg42_reg, wdb_wdc_wstrb) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int wdb_we                         : MH_DEBUG_REG42_WDB_WE_SIZE;
+          unsigned int wdb_rtr_skid                   : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG42_ARB_WLAST_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG42_WDB_WDC_WID_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg42_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int                                : 2;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG42_WDB_WDC_WID_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG42_ARB_WLAST_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE;
+          unsigned int wdb_rtr_skid                   : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG42_WDB_WE_SIZE;
+     } mh_debug_reg42_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg42_t f;
+} mh_debug_reg42_u;
+
+
+/*
+ * MH_DEBUG_REG43 struct
+ */
+
+#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE 32
+
+#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT 0
+
+#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG43_MASK \
+     (MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK)
+
+#define MH_DEBUG_REG43(arb_wdata_q_31_0) \
+     ((arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT))
+
+#define MH_DEBUG_REG43_GET_ARB_WDATA_q_31_0(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) >> MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT)
+
+#define MH_DEBUG_REG43_SET_ARB_WDATA_q_31_0(mh_debug_reg43_reg, arb_wdata_q_31_0) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) | (arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_wdata_q_31_0               : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE;
+     } mh_debug_reg43_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_wdata_q_31_0               : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE;
+     } mh_debug_reg43_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg43_t f;
+} mh_debug_reg43_u;
+
+
+/*
+ * MH_DEBUG_REG44 struct
+ */
+
+#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE 32
+
+#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT 0
+
+#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG44_MASK \
+     (MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK)
+
+#define MH_DEBUG_REG44(arb_wdata_q_63_32) \
+     ((arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT))
+
+#define MH_DEBUG_REG44_GET_ARB_WDATA_q_63_32(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) >> MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT)
+
+#define MH_DEBUG_REG44_SET_ARB_WDATA_q_63_32(mh_debug_reg44_reg, arb_wdata_q_63_32) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) | (arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_wdata_q_63_32              : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE;
+     } mh_debug_reg44_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_wdata_q_63_32              : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE;
+     } mh_debug_reg44_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg44_t f;
+} mh_debug_reg44_u;
+
+
+/*
+ * MH_DEBUG_REG45 struct
+ */
+
+#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE 32
+
+#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT 0
+
+#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG45_MASK \
+     (MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK)
+
+#define MH_DEBUG_REG45(wdb_wdc_wdata_31_0) \
+     ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT))
+
+#define MH_DEBUG_REG45_GET_WDB_WDC_WDATA_31_0(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT)
+
+#define MH_DEBUG_REG45_SET_WDB_WDC_WDATA_31_0(mh_debug_reg45_reg, wdb_wdc_wdata_31_0) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg45_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg45_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg45_t f;
+} mh_debug_reg45_u;
+
+
+/*
+ * MH_DEBUG_REG46 struct
+ */
+
+#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE 32
+
+#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT 0
+
+#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG46_MASK \
+     (MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK)
+
+#define MH_DEBUG_REG46(wdb_wdc_wdata_63_32) \
+     ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT))
+
+#define MH_DEBUG_REG46_GET_WDB_WDC_WDATA_63_32(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT)
+
+#define MH_DEBUG_REG46_SET_WDB_WDC_WDATA_63_32(mh_debug_reg46_reg, wdb_wdc_wdata_63_32) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg46_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg46_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg46_t f;
+} mh_debug_reg46_u;
+
+
+/*
+ * MH_DEBUG_REG47 struct
+ */
+
+#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE 1
+#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE 1
+#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE 6
+#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG47_RVALID_q_SIZE   1
+#define MH_DEBUG_REG47_RREADY_q_SIZE   1
+#define MH_DEBUG_REG47_RLAST_q_SIZE    1
+#define MH_DEBUG_REG47_BVALID_q_SIZE   1
+#define MH_DEBUG_REG47_BREADY_q_SIZE   1
+
+#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT 0
+#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT 1
+#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT 2
+#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT 3
+#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT 4
+#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT 5
+#define MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT 6
+#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT 7
+#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT 13
+#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT 14
+#define MH_DEBUG_REG47_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG47_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG47_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG47_BVALID_q_SHIFT  18
+#define MH_DEBUG_REG47_BREADY_q_SHIFT  19
+
+#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK 0x00000001
+#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK 0x00000002
+#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK 0x00000004
+#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK 0x00000008
+#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK 0x00000010
+#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK 0x00000020
+#define MH_DEBUG_REG47_INFLT_LIMIT_q_MASK 0x00000040
+#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK 0x00001f80
+#define MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK 0x00004000
+#define MH_DEBUG_REG47_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG47_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG47_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG47_BVALID_q_MASK   0x00040000
+#define MH_DEBUG_REG47_BREADY_q_MASK   0x00080000
+
+#define MH_DEBUG_REG47_MASK \
+     (MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK | \
+      MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK | \
+      MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK | \
+      MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG47_INFLT_LIMIT_q_MASK | \
+      MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK | \
+      MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG47_RVALID_q_MASK | \
+      MH_DEBUG_REG47_RREADY_q_MASK | \
+      MH_DEBUG_REG47_RLAST_q_MASK | \
+      MH_DEBUG_REG47_BVALID_q_MASK | \
+      MH_DEBUG_REG47_BREADY_q_MASK)
+
+#define MH_DEBUG_REG47(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \
+     ((ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) | \
+      (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) | \
+      (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) | \
+      (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) | \
+      (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT))
+
+#define MH_DEBUG_REG47_GET_CTRL_ARC_EMPTY(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_GET_CTRL_RARC_EMPTY(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_GET_ARQ_CTRL_EMPTY(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_GET_ARQ_CTRL_WRITE(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG47_GET_TLBMISS_CTRL_RTS(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG47_GET_CTRL_TLBMISS_RE_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG47_GET_INFLT_LIMIT_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG47_GET_INFLT_LIMIT_CNT_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG47_GET_ARC_CTRL_RE_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RARC_CTRL_RE_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RVALID_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RVALID_q_MASK) >> MH_DEBUG_REG47_RVALID_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RREADY_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RREADY_q_MASK) >> MH_DEBUG_REG47_RREADY_q_SHIFT)
+#define MH_DEBUG_REG47_GET_RLAST_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_RLAST_q_MASK) >> MH_DEBUG_REG47_RLAST_q_SHIFT)
+#define MH_DEBUG_REG47_GET_BVALID_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_BVALID_q_MASK) >> MH_DEBUG_REG47_BVALID_q_SHIFT)
+#define MH_DEBUG_REG47_GET_BREADY_q(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_BREADY_q_MASK) >> MH_DEBUG_REG47_BREADY_q_SHIFT)
+
+#define MH_DEBUG_REG47_SET_CTRL_ARC_EMPTY(mh_debug_reg47_reg, ctrl_arc_empty) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_SET_CTRL_RARC_EMPTY(mh_debug_reg47_reg, ctrl_rarc_empty) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_SET_ARQ_CTRL_EMPTY(mh_debug_reg47_reg, arq_ctrl_empty) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG47_SET_ARQ_CTRL_WRITE(mh_debug_reg47_reg, arq_ctrl_write) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG47_SET_TLBMISS_CTRL_RTS(mh_debug_reg47_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG47_SET_CTRL_TLBMISS_RE_q(mh_debug_reg47_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG47_SET_INFLT_LIMIT_q(mh_debug_reg47_reg, inflt_limit_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG47_SET_INFLT_LIMIT_CNT_q(mh_debug_reg47_reg, inflt_limit_cnt_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG47_SET_ARC_CTRL_RE_q(mh_debug_reg47_reg, arc_ctrl_re_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RARC_CTRL_RE_q(mh_debug_reg47_reg, rarc_ctrl_re_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RVALID_q(mh_debug_reg47_reg, rvalid_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RREADY_q(mh_debug_reg47_reg, rready_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT)
+#define MH_DEBUG_REG47_SET_RLAST_q(mh_debug_reg47_reg, rlast_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT)
+#define MH_DEBUG_REG47_SET_BVALID_q(mh_debug_reg47_reg, bvalid_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT)
+#define MH_DEBUG_REG47_SET_BREADY_q(mh_debug_reg47_reg, bready_q) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG47_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG47_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG47_RLAST_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG47_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG47_BREADY_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg47_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int                                : 12;
+          unsigned int bready_q                       : MH_DEBUG_REG47_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG47_BVALID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG47_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG47_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG47_RVALID_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE;
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE;
+     } mh_debug_reg47_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg47_t f;
+} mh_debug_reg47_u;
+
+
+/*
+ * MH_DEBUG_REG48 struct
+ */
+
+#define MH_DEBUG_REG48_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG48_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG48_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG48_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG48_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG48_RDC_RID_SIZE    3
+#define MH_DEBUG_REG48_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG48_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE 1
+#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE 6
+#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE 1
+#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE 6
+#define MH_DEBUG_REG48_CNT_HOLD_q1_SIZE 1
+#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG48_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG48_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT 3
+#define MH_DEBUG_REG48_TLBMISS_VALID_SHIFT 4
+#define MH_DEBUG_REG48_RDC_VALID_SHIFT 5
+#define MH_DEBUG_REG48_RDC_RID_SHIFT   6
+#define MH_DEBUG_REG48_RDC_RLAST_SHIFT 9
+#define MH_DEBUG_REG48_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT 12
+#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT 13
+#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT 14
+#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT 15
+#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT 21
+#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT 22
+#define MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT 28
+#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29
+
+#define MH_DEBUG_REG48_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG48_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG48_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK 0x00000008
+#define MH_DEBUG_REG48_TLBMISS_VALID_MASK 0x00000010
+#define MH_DEBUG_REG48_RDC_VALID_MASK  0x00000020
+#define MH_DEBUG_REG48_RDC_RID_MASK    0x000001c0
+#define MH_DEBUG_REG48_RDC_RLAST_MASK  0x00000200
+#define MH_DEBUG_REG48_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK 0x00001000
+#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK 0x00004000
+#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000
+#define MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK 0x00200000
+#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000
+#define MH_DEBUG_REG48_CNT_HOLD_q1_MASK 0x10000000
+#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000
+
+#define MH_DEBUG_REG48_MASK \
+     (MH_DEBUG_REG48_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG48_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG48_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG48_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG48_RDC_VALID_MASK | \
+      MH_DEBUG_REG48_RDC_RID_MASK | \
+      MH_DEBUG_REG48_RDC_RLAST_MASK | \
+      MH_DEBUG_REG48_RDC_RRESP_MASK | \
+      MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK | \
+      MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK | \
+      MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK | \
+      MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK | \
+      MH_DEBUG_REG48_CNT_HOLD_q1_MASK | \
+      MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG48(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \
+     ((mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) | \
+      (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) | \
+      (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) | \
+      (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) | \
+      (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG48_GET_MH_CP_grb_send(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CP_grb_send_MASK) >> MH_DEBUG_REG48_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_VGT_grb_send(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_TC_mcsend(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TC_mcsend_MASK) >> MH_DEBUG_REG48_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_TLBMISS_SEND(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG48_GET_TLBMISS_VALID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_VALID_MASK) >> MH_DEBUG_REG48_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_VALID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_VALID_MASK) >> MH_DEBUG_REG48_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_RID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RID_MASK) >> MH_DEBUG_REG48_RDC_RID_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_RLAST(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RLAST_MASK) >> MH_DEBUG_REG48_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG48_GET_RDC_RRESP(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RRESP_MASK) >> MH_DEBUG_REG48_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG48_GET_TLBMISS_CTRL_RTS(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG48_GET_CTRL_TLBMISS_RE_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG48_GET_MMU_ID_REQUEST_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG48_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_GET_MMU_ID_RESPONSE(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG48_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_GET_CNT_HOLD_q1(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG48_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG48_SET_MH_CP_grb_send(mh_debug_reg48_reg, mh_cp_grb_send) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_VGT_grb_send(mh_debug_reg48_reg, mh_vgt_grb_send) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_TC_mcsend(mh_debug_reg48_reg, mh_tc_mcsend) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_TLBMISS_SEND(mh_debug_reg48_reg, mh_tlbmiss_send) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG48_SET_TLBMISS_VALID(mh_debug_reg48_reg, tlbmiss_valid) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_VALID(mh_debug_reg48_reg, rdc_valid) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_RID(mh_debug_reg48_reg, rdc_rid) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_RLAST(mh_debug_reg48_reg, rdc_rlast) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG48_SET_RDC_RRESP(mh_debug_reg48_reg, rdc_rresp) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG48_SET_TLBMISS_CTRL_RTS(mh_debug_reg48_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG48_SET_CTRL_TLBMISS_RE_q(mh_debug_reg48_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG48_SET_MMU_ID_REQUEST_q(mh_debug_reg48_reg, mmu_id_request_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG48_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48_reg, outstanding_mmuid_cnt_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_SET_MMU_ID_RESPONSE(mh_debug_reg48_reg, mmu_id_response) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG48_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg48_reg, tlbmiss_return_cnt_q) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG48_SET_CNT_HOLD_q1(mh_debug_reg48_reg, cnt_hold_q1) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG48_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG48_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG48_MH_TC_mcsend_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG48_TLBMISS_VALID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG48_RDC_VALID_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG48_RDC_RID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG48_RDC_RLAST_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG48_RDC_RRESP_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+     } mh_debug_reg48_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG48_RDC_RRESP_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG48_RDC_RLAST_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG48_RDC_RID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG48_RDC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG48_TLBMISS_VALID_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG48_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG48_MH_CP_grb_send_SIZE;
+     } mh_debug_reg48_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg48_t f;
+} mh_debug_reg48_u;
+
+
+/*
+ * MH_DEBUG_REG49 struct
+ */
+
+#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE 32
+
+#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT 0
+
+#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG49_MASK \
+     (MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK)
+
+#define MH_DEBUG_REG49(rf_mmu_page_fault) \
+     ((rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_DEBUG_REG49_GET_RF_MMU_PAGE_FAULT(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_DEBUG_REG49_SET_RF_MMU_PAGE_FAULT(mh_debug_reg49_reg, rf_mmu_page_fault) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg49_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg49_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg49_t f;
+} mh_debug_reg49_u;
+
+
+/*
+ * MH_DEBUG_REG50 struct
+ */
+
+#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE 24
+#define MH_DEBUG_REG50_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG50_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG50_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG50_ARB_WE_SIZE     1
+#define MH_DEBUG_REG50_MMU_RTR_SIZE    1
+
+#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG50_ARB_ID_q_SHIFT  24
+#define MH_DEBUG_REG50_ARB_WRITE_q_SHIFT 27
+#define MH_DEBUG_REG50_client_behavior_q_SHIFT 28
+#define MH_DEBUG_REG50_ARB_WE_SHIFT    30
+#define MH_DEBUG_REG50_MMU_RTR_SHIFT   31
+
+#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK 0x00ffffff
+#define MH_DEBUG_REG50_ARB_ID_q_MASK   0x07000000
+#define MH_DEBUG_REG50_ARB_WRITE_q_MASK 0x08000000
+#define MH_DEBUG_REG50_client_behavior_q_MASK 0x30000000
+#define MH_DEBUG_REG50_ARB_WE_MASK     0x40000000
+#define MH_DEBUG_REG50_MMU_RTR_MASK    0x80000000
+
+#define MH_DEBUG_REG50_MASK \
+     (MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK | \
+      MH_DEBUG_REG50_ARB_ID_q_MASK | \
+      MH_DEBUG_REG50_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG50_client_behavior_q_MASK | \
+      MH_DEBUG_REG50_ARB_WE_MASK | \
+      MH_DEBUG_REG50_MMU_RTR_MASK)
+
+#define MH_DEBUG_REG50(rf_mmu_config_q, arb_id_q, arb_write_q, client_behavior_q, arb_we, mmu_rtr) \
+     ((rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT) | \
+      (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT))
+
+#define MH_DEBUG_REG50_GET_RF_MMU_CONFIG_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) >> MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG50_GET_ARB_ID_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_ID_q_MASK) >> MH_DEBUG_REG50_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG50_GET_ARB_WRITE_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WRITE_q_MASK) >> MH_DEBUG_REG50_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG50_GET_client_behavior_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_client_behavior_q_MASK) >> MH_DEBUG_REG50_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG50_GET_ARB_WE(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WE_MASK) >> MH_DEBUG_REG50_ARB_WE_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_RTR(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_RTR_MASK) >> MH_DEBUG_REG50_MMU_RTR_SHIFT)
+
+#define MH_DEBUG_REG50_SET_RF_MMU_CONFIG_q(mh_debug_reg50_reg, rf_mmu_config_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) | (rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG50_SET_ARB_ID_q(mh_debug_reg50_reg, arb_id_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG50_SET_ARB_WRITE_q(mh_debug_reg50_reg, arb_write_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG50_SET_client_behavior_q(mh_debug_reg50_reg, client_behavior_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG50_SET_ARB_WE(mh_debug_reg50_reg, arb_we) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_RTR(mh_debug_reg50_reg, mmu_rtr) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int rf_mmu_config_q                : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG50_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG50_ARB_WRITE_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG50_client_behavior_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG50_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG50_MMU_RTR_SIZE;
+     } mh_debug_reg50_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mmu_rtr                        : MH_DEBUG_REG50_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG50_ARB_WE_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG50_client_behavior_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG50_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG50_ARB_ID_q_SIZE;
+          unsigned int rf_mmu_config_q                : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE;
+     } mh_debug_reg50_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg50_t f;
+} mh_debug_reg50_u;
+
+
+/*
+ * MH_DEBUG_REG51 struct
+ */
+
+#define MH_DEBUG_REG51_stage1_valid_SIZE 1
+#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG51_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG51_tag_match_q_SIZE 1
+#define MH_DEBUG_REG51_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG51_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG51_MMU_MISS_SIZE   1
+#define MH_DEBUG_REG51_MMU_READ_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_HIT_SIZE    1
+#define MH_DEBUG_REG51_MMU_READ_HIT_SIZE 1
+#define MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1
+#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE 16
+
+#define MH_DEBUG_REG51_stage1_valid_SHIFT 0
+#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT 1
+#define MH_DEBUG_REG51_pa_in_mpu_range_SHIFT 2
+#define MH_DEBUG_REG51_tag_match_q_SHIFT 3
+#define MH_DEBUG_REG51_tag_miss_q_SHIFT 4
+#define MH_DEBUG_REG51_va_in_range_q_SHIFT 5
+#define MH_DEBUG_REG51_MMU_MISS_SHIFT  6
+#define MH_DEBUG_REG51_MMU_READ_MISS_SHIFT 7
+#define MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT 8
+#define MH_DEBUG_REG51_MMU_HIT_SHIFT   9
+#define MH_DEBUG_REG51_MMU_READ_HIT_SHIFT 10
+#define MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT 11
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT 12
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT 13
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15
+#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT 16
+
+#define MH_DEBUG_REG51_stage1_valid_MASK 0x00000001
+#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK 0x00000002
+#define MH_DEBUG_REG51_pa_in_mpu_range_MASK 0x00000004
+#define MH_DEBUG_REG51_tag_match_q_MASK 0x00000008
+#define MH_DEBUG_REG51_tag_miss_q_MASK 0x00000010
+#define MH_DEBUG_REG51_va_in_range_q_MASK 0x00000020
+#define MH_DEBUG_REG51_MMU_MISS_MASK   0x00000040
+#define MH_DEBUG_REG51_MMU_READ_MISS_MASK 0x00000080
+#define MH_DEBUG_REG51_MMU_WRITE_MISS_MASK 0x00000100
+#define MH_DEBUG_REG51_MMU_HIT_MASK    0x00000200
+#define MH_DEBUG_REG51_MMU_READ_HIT_MASK 0x00000400
+#define MH_DEBUG_REG51_MMU_WRITE_HIT_MASK 0x00000800
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000
+#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000
+#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG51_MASK \
+     (MH_DEBUG_REG51_stage1_valid_MASK | \
+      MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG51_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG51_tag_match_q_MASK | \
+      MH_DEBUG_REG51_tag_miss_q_MASK | \
+      MH_DEBUG_REG51_va_in_range_q_MASK | \
+      MH_DEBUG_REG51_MMU_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_READ_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_WRITE_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_READ_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_WRITE_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK | \
+      MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK | \
+      MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK)
+
+#define MH_DEBUG_REG51(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \
+     ((stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT) | \
+      (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT) | \
+      (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) | \
+      (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) | \
+      (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT) | \
+      (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) | \
+      (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) | \
+      (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \
+      (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \
+      (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \
+      (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \
+      (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT))
+
+#define MH_DEBUG_REG51_GET_stage1_valid(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_stage1_valid_MASK) >> MH_DEBUG_REG51_stage1_valid_SHIFT)
+#define MH_DEBUG_REG51_GET_IGNORE_TAG_MISS_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG51_GET_pa_in_mpu_range(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_pa_in_mpu_range_MASK) >> MH_DEBUG_REG51_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG51_GET_tag_match_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_tag_match_q_MASK) >> MH_DEBUG_REG51_tag_match_q_SHIFT)
+#define MH_DEBUG_REG51_GET_tag_miss_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_tag_miss_q_MASK) >> MH_DEBUG_REG51_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG51_GET_va_in_range_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_va_in_range_q_MASK) >> MH_DEBUG_REG51_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_MISS_MASK) >> MH_DEBUG_REG51_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_READ_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_MISS_MASK) >> MH_DEBUG_REG51_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_WRITE_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_HIT_MASK) >> MH_DEBUG_REG51_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_READ_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_HIT_MASK) >> MH_DEBUG_REG51_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_WRITE_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG51_GET_REQ_VA_OFFSET_q(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT)
+
+#define MH_DEBUG_REG51_SET_stage1_valid(mh_debug_reg51_reg, stage1_valid) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT)
+#define MH_DEBUG_REG51_SET_IGNORE_TAG_MISS_q(mh_debug_reg51_reg, ignore_tag_miss_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG51_SET_pa_in_mpu_range(mh_debug_reg51_reg, pa_in_mpu_range) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG51_SET_tag_match_q(mh_debug_reg51_reg, tag_match_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT)
+#define MH_DEBUG_REG51_SET_tag_miss_q(mh_debug_reg51_reg, tag_miss_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG51_SET_va_in_range_q(mh_debug_reg51_reg, va_in_range_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_MISS(mh_debug_reg51_reg, mmu_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_READ_MISS(mh_debug_reg51_reg, mmu_read_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_WRITE_MISS(mh_debug_reg51_reg, mmu_write_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_HIT(mh_debug_reg51_reg, mmu_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_READ_HIT(mh_debug_reg51_reg, mmu_read_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_WRITE_HIT(mh_debug_reg51_reg, mmu_write_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51_reg, mmu_split_mode_tc_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51_reg, mmu_split_mode_tc_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51_reg, mmu_split_mode_nontc_miss) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51_reg, mmu_split_mode_nontc_hit) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG51_SET_REQ_VA_OFFSET_q(mh_debug_reg51_reg, req_va_offset_q) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int stage1_valid                   : MH_DEBUG_REG51_stage1_valid_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG51_pa_in_mpu_range_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG51_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG51_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG51_va_in_range_q_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG51_MMU_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG51_MMU_READ_MISS_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG51_MMU_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG51_MMU_READ_HIT_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int req_va_offset_q                : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE;
+     } mh_debug_reg51_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int req_va_offset_q                : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG51_MMU_READ_HIT_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG51_MMU_HIT_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG51_MMU_READ_MISS_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG51_MMU_MISS_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG51_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG51_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG51_tag_match_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG51_pa_in_mpu_range_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG51_stage1_valid_SIZE;
+     } mh_debug_reg51_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg51_t f;
+} mh_debug_reg51_u;
+
+
+/*
+ * MH_DEBUG_REG52 struct
+ */
+
+#define MH_DEBUG_REG52_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG52_MMU_WE_SIZE     1
+#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1
+#define MH_DEBUG_REG52_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG52_stage1_valid_SIZE 1
+#define MH_DEBUG_REG52_stage2_valid_SIZE 1
+#define MH_DEBUG_REG52_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG52_tag_match_q_SIZE 1
+#define MH_DEBUG_REG52_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG52_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE 1
+#define MH_DEBUG_REG52_TAG_valid_q_SIZE 16
+
+#define MH_DEBUG_REG52_ARQ_RTR_SHIFT   0
+#define MH_DEBUG_REG52_MMU_WE_SHIFT    1
+#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT 2
+#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT 3
+#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT 4
+#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5
+#define MH_DEBUG_REG52_pa_in_mpu_range_SHIFT 6
+#define MH_DEBUG_REG52_stage1_valid_SHIFT 7
+#define MH_DEBUG_REG52_stage2_valid_SHIFT 8
+#define MH_DEBUG_REG52_client_behavior_q_SHIFT 9
+#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT 11
+#define MH_DEBUG_REG52_tag_match_q_SHIFT 12
+#define MH_DEBUG_REG52_tag_miss_q_SHIFT 13
+#define MH_DEBUG_REG52_va_in_range_q_SHIFT 14
+#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT 15
+#define MH_DEBUG_REG52_TAG_valid_q_SHIFT 16
+
+#define MH_DEBUG_REG52_ARQ_RTR_MASK    0x00000001
+#define MH_DEBUG_REG52_MMU_WE_MASK     0x00000002
+#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK 0x00000004
+#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK 0x00000008
+#define MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK 0x00000010
+#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020
+#define MH_DEBUG_REG52_pa_in_mpu_range_MASK 0x00000040
+#define MH_DEBUG_REG52_stage1_valid_MASK 0x00000080
+#define MH_DEBUG_REG52_stage2_valid_MASK 0x00000100
+#define MH_DEBUG_REG52_client_behavior_q_MASK 0x00000600
+#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK 0x00000800
+#define MH_DEBUG_REG52_tag_match_q_MASK 0x00001000
+#define MH_DEBUG_REG52_tag_miss_q_MASK 0x00002000
+#define MH_DEBUG_REG52_va_in_range_q_MASK 0x00004000
+#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK 0x00008000
+#define MH_DEBUG_REG52_TAG_valid_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG52_MASK \
+     (MH_DEBUG_REG52_ARQ_RTR_MASK | \
+      MH_DEBUG_REG52_MMU_WE_MASK | \
+      MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \
+      MH_DEBUG_REG52_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG52_stage1_valid_MASK | \
+      MH_DEBUG_REG52_stage2_valid_MASK | \
+      MH_DEBUG_REG52_client_behavior_q_MASK | \
+      MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG52_tag_match_q_MASK | \
+      MH_DEBUG_REG52_tag_miss_q_MASK | \
+      MH_DEBUG_REG52_va_in_range_q_MASK | \
+      MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK | \
+      MH_DEBUG_REG52_TAG_valid_q_MASK)
+
+#define MH_DEBUG_REG52(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \
+     ((arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) | \
+      (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) | \
+      (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT) | \
+      (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT) | \
+      (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) | \
+      (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT))
+
+#define MH_DEBUG_REG52_GET_ARQ_RTR(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARQ_RTR_MASK) >> MH_DEBUG_REG52_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_WE(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_WE_MASK) >> MH_DEBUG_REG52_MMU_WE_SHIFT)
+#define MH_DEBUG_REG52_GET_CTRL_TLBMISS_RE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_TLBMISS_CTRL_RTS(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG52_GET_MH_TLBMISS_SEND(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG52_GET_pa_in_mpu_range(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_pa_in_mpu_range_MASK) >> MH_DEBUG_REG52_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG52_GET_stage1_valid(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_stage1_valid_MASK) >> MH_DEBUG_REG52_stage1_valid_SHIFT)
+#define MH_DEBUG_REG52_GET_stage2_valid(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_stage2_valid_MASK) >> MH_DEBUG_REG52_stage2_valid_SHIFT)
+#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG52_GET_IGNORE_TAG_MISS_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG52_GET_tag_match_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_tag_match_q_MASK) >> MH_DEBUG_REG52_tag_match_q_SHIFT)
+#define MH_DEBUG_REG52_GET_tag_miss_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_tag_miss_q_MASK) >> MH_DEBUG_REG52_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG52_GET_va_in_range_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_va_in_range_q_MASK) >> MH_DEBUG_REG52_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG52_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_TAG_valid_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_TAG_valid_q_MASK) >> MH_DEBUG_REG52_TAG_valid_q_SHIFT)
+
+#define MH_DEBUG_REG52_SET_ARQ_RTR(mh_debug_reg52_reg, arq_rtr) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_WE(mh_debug_reg52_reg, mmu_we) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT)
+#define MH_DEBUG_REG52_SET_CTRL_TLBMISS_RE_q(mh_debug_reg52_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_TLBMISS_CTRL_RTS(mh_debug_reg52_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG52_SET_MH_TLBMISS_SEND(mh_debug_reg52_reg, mh_tlbmiss_send) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52_reg, mmu_stall_awaiting_tlb_miss_fetch) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG52_SET_pa_in_mpu_range(mh_debug_reg52_reg, pa_in_mpu_range) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG52_SET_stage1_valid(mh_debug_reg52_reg, stage1_valid) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT)
+#define MH_DEBUG_REG52_SET_stage2_valid(mh_debug_reg52_reg, stage2_valid) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT)
+#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG52_SET_IGNORE_TAG_MISS_q(mh_debug_reg52_reg, ignore_tag_miss_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG52_SET_tag_match_q(mh_debug_reg52_reg, tag_match_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT)
+#define MH_DEBUG_REG52_SET_tag_miss_q(mh_debug_reg52_reg, tag_miss_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG52_SET_va_in_range_q(mh_debug_reg52_reg, va_in_range_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG52_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg52_reg, pte_fetch_complete_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_TAG_valid_q(mh_debug_reg52_reg, tag_valid_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int arq_rtr                        : MH_DEBUG_REG52_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG52_MMU_WE_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG52_pa_in_mpu_range_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG52_stage1_valid_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG52_stage2_valid_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG52_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG52_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG52_va_in_range_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int tag_valid_q                    : MH_DEBUG_REG52_TAG_valid_q_SIZE;
+     } mh_debug_reg52_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int tag_valid_q                    : MH_DEBUG_REG52_TAG_valid_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG52_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG52_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG52_tag_match_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG52_stage2_valid_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG52_stage1_valid_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG52_pa_in_mpu_range_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG52_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG52_ARQ_RTR_SIZE;
+     } mh_debug_reg52_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg52_t f;
+} mh_debug_reg52_u;
+
+
+/*
+ * MH_DEBUG_REG53 struct
+ */
+
+#define MH_DEBUG_REG53_TAG0_VA_SIZE    13
+#define MH_DEBUG_REG53_TAG_valid_q_0_SIZE 1
+#define MH_DEBUG_REG53_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG53_TAG1_VA_SIZE    13
+#define MH_DEBUG_REG53_TAG_valid_q_1_SIZE 1
+
+#define MH_DEBUG_REG53_TAG0_VA_SHIFT   0
+#define MH_DEBUG_REG53_TAG_valid_q_0_SHIFT 13
+#define MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG53_TAG1_VA_SHIFT   16
+#define MH_DEBUG_REG53_TAG_valid_q_1_SHIFT 29
+
+#define MH_DEBUG_REG53_TAG0_VA_MASK    0x00001fff
+#define MH_DEBUG_REG53_TAG_valid_q_0_MASK 0x00002000
+#define MH_DEBUG_REG53_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG53_TAG1_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG53_TAG_valid_q_1_MASK 0x20000000
+
+#define MH_DEBUG_REG53_MASK \
+     (MH_DEBUG_REG53_TAG0_VA_MASK | \
+      MH_DEBUG_REG53_TAG_valid_q_0_MASK | \
+      MH_DEBUG_REG53_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG53_TAG1_VA_MASK | \
+      MH_DEBUG_REG53_TAG_valid_q_1_MASK)
+
+#define MH_DEBUG_REG53(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \
+     ((tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT) | \
+      (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) | \
+      (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) | \
+      (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT) | \
+      (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT))
+
+#define MH_DEBUG_REG53_GET_TAG0_VA(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG0_VA_MASK) >> MH_DEBUG_REG53_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG53_GET_TAG_valid_q_0(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_0_MASK) >> MH_DEBUG_REG53_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG53_GET_ALWAYS_ZERO(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG53_GET_TAG1_VA(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG1_VA_MASK) >> MH_DEBUG_REG53_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG53_GET_TAG_valid_q_1(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_1_MASK) >> MH_DEBUG_REG53_TAG_valid_q_1_SHIFT)
+
+#define MH_DEBUG_REG53_SET_TAG0_VA(mh_debug_reg53_reg, tag0_va) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG53_SET_TAG_valid_q_0(mh_debug_reg53_reg, tag_valid_q_0) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG53_SET_ALWAYS_ZERO(mh_debug_reg53_reg, always_zero) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG53_SET_TAG1_VA(mh_debug_reg53_reg, tag1_va) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG53_SET_TAG_valid_q_1(mh_debug_reg53_reg, tag_valid_q_1) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int tag0_va                        : MH_DEBUG_REG53_TAG0_VA_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG53_TAG_valid_q_0_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG53_TAG1_VA_SIZE;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG53_TAG_valid_q_1_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg53_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG53_TAG_valid_q_1_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG53_TAG1_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG53_TAG_valid_q_0_SIZE;
+          unsigned int tag0_va                        : MH_DEBUG_REG53_TAG0_VA_SIZE;
+     } mh_debug_reg53_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg53_t f;
+} mh_debug_reg53_u;
+
+
+/*
+ * MH_DEBUG_REG54 struct
+ */
+
+#define MH_DEBUG_REG54_TAG2_VA_SIZE    13
+#define MH_DEBUG_REG54_TAG_valid_q_2_SIZE 1
+#define MH_DEBUG_REG54_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG54_TAG3_VA_SIZE    13
+#define MH_DEBUG_REG54_TAG_valid_q_3_SIZE 1
+
+#define MH_DEBUG_REG54_TAG2_VA_SHIFT   0
+#define MH_DEBUG_REG54_TAG_valid_q_2_SHIFT 13
+#define MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG54_TAG3_VA_SHIFT   16
+#define MH_DEBUG_REG54_TAG_valid_q_3_SHIFT 29
+
+#define MH_DEBUG_REG54_TAG2_VA_MASK    0x00001fff
+#define MH_DEBUG_REG54_TAG_valid_q_2_MASK 0x00002000
+#define MH_DEBUG_REG54_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG54_TAG3_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG54_TAG_valid_q_3_MASK 0x20000000
+
+#define MH_DEBUG_REG54_MASK \
+     (MH_DEBUG_REG54_TAG2_VA_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_2_MASK | \
+      MH_DEBUG_REG54_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG54_TAG3_VA_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_3_MASK)
+
+#define MH_DEBUG_REG54(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \
+     ((tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT) | \
+      (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) | \
+      (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) | \
+      (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT) | \
+      (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT))
+
+#define MH_DEBUG_REG54_GET_TAG2_VA(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG2_VA_MASK) >> MH_DEBUG_REG54_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q_2(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_2_MASK) >> MH_DEBUG_REG54_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG54_GET_ALWAYS_ZERO(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG3_VA(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG3_VA_MASK) >> MH_DEBUG_REG54_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q_3(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_3_MASK) >> MH_DEBUG_REG54_TAG_valid_q_3_SHIFT)
+
+#define MH_DEBUG_REG54_SET_TAG2_VA(mh_debug_reg54_reg, tag2_va) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q_2(mh_debug_reg54_reg, tag_valid_q_2) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG54_SET_ALWAYS_ZERO(mh_debug_reg54_reg, always_zero) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG3_VA(mh_debug_reg54_reg, tag3_va) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q_3(mh_debug_reg54_reg, tag_valid_q_3) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int tag2_va                        : MH_DEBUG_REG54_TAG2_VA_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG54_TAG_valid_q_2_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG54_TAG3_VA_SIZE;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG54_TAG_valid_q_3_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg54_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG54_TAG_valid_q_3_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG54_TAG3_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG54_TAG_valid_q_2_SIZE;
+          unsigned int tag2_va                        : MH_DEBUG_REG54_TAG2_VA_SIZE;
+     } mh_debug_reg54_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg54_t f;
+} mh_debug_reg54_u;
+
+
+/*
+ * MH_DEBUG_REG55 struct
+ */
+
+#define MH_DEBUG_REG55_TAG4_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_4_SIZE 1
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG55_TAG5_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_5_SIZE 1
+
+#define MH_DEBUG_REG55_TAG4_VA_SHIFT   0
+#define MH_DEBUG_REG55_TAG_valid_q_4_SHIFT 13
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG55_TAG5_VA_SHIFT   16
+#define MH_DEBUG_REG55_TAG_valid_q_5_SHIFT 29
+
+#define MH_DEBUG_REG55_TAG4_VA_MASK    0x00001fff
+#define MH_DEBUG_REG55_TAG_valid_q_4_MASK 0x00002000
+#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG55_TAG5_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG55_TAG_valid_q_5_MASK 0x20000000
+
+#define MH_DEBUG_REG55_MASK \
+     (MH_DEBUG_REG55_TAG4_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_4_MASK | \
+      MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG55_TAG5_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_5_MASK)
+
+#define MH_DEBUG_REG55(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \
+     ((tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT) | \
+      (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) | \
+      (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \
+      (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT) | \
+      (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT))
+
+#define MH_DEBUG_REG55_GET_TAG4_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG4_VA_MASK) >> MH_DEBUG_REG55_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_4(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_4_MASK) >> MH_DEBUG_REG55_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG5_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG5_VA_MASK) >> MH_DEBUG_REG55_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_5(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_5_MASK) >> MH_DEBUG_REG55_TAG_valid_q_5_SHIFT)
+
+#define MH_DEBUG_REG55_SET_TAG4_VA(mh_debug_reg55_reg, tag4_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_4(mh_debug_reg55_reg, tag_valid_q_4) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG5_VA(mh_debug_reg55_reg, tag5_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_5(mh_debug_reg55_reg, tag_valid_q_5) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int tag4_va                        : MH_DEBUG_REG55_TAG4_VA_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG55_TAG_valid_q_4_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG55_TAG5_VA_SIZE;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG55_TAG_valid_q_5_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg55_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG55_TAG_valid_q_5_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG55_TAG5_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG55_TAG_valid_q_4_SIZE;
+          unsigned int tag4_va                        : MH_DEBUG_REG55_TAG4_VA_SIZE;
+     } mh_debug_reg55_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg55_t f;
+} mh_debug_reg55_u;
+
+
+/*
+ * MH_DEBUG_REG56 struct
+ */
+
+#define MH_DEBUG_REG56_TAG6_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_6_SIZE 1
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG56_TAG7_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_7_SIZE 1
+
+#define MH_DEBUG_REG56_TAG6_VA_SHIFT   0
+#define MH_DEBUG_REG56_TAG_valid_q_6_SHIFT 13
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG56_TAG7_VA_SHIFT   16
+#define MH_DEBUG_REG56_TAG_valid_q_7_SHIFT 29
+
+#define MH_DEBUG_REG56_TAG6_VA_MASK    0x00001fff
+#define MH_DEBUG_REG56_TAG_valid_q_6_MASK 0x00002000
+#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG56_TAG7_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG56_TAG_valid_q_7_MASK 0x20000000
+
+#define MH_DEBUG_REG56_MASK \
+     (MH_DEBUG_REG56_TAG6_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_6_MASK | \
+      MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG56_TAG7_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_7_MASK)
+
+#define MH_DEBUG_REG56(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \
+     ((tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT) | \
+      (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) | \
+      (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \
+      (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT) | \
+      (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT))
+
+#define MH_DEBUG_REG56_GET_TAG6_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG6_VA_MASK) >> MH_DEBUG_REG56_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_6(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_6_MASK) >> MH_DEBUG_REG56_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG7_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG7_VA_MASK) >> MH_DEBUG_REG56_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_7(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_7_MASK) >> MH_DEBUG_REG56_TAG_valid_q_7_SHIFT)
+
+#define MH_DEBUG_REG56_SET_TAG6_VA(mh_debug_reg56_reg, tag6_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_6(mh_debug_reg56_reg, tag_valid_q_6) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG7_VA(mh_debug_reg56_reg, tag7_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_7(mh_debug_reg56_reg, tag_valid_q_7) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int tag6_va                        : MH_DEBUG_REG56_TAG6_VA_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG56_TAG_valid_q_6_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG56_TAG7_VA_SIZE;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG56_TAG_valid_q_7_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg56_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG56_TAG_valid_q_7_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG56_TAG7_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG56_TAG_valid_q_6_SIZE;
+          unsigned int tag6_va                        : MH_DEBUG_REG56_TAG6_VA_SIZE;
+     } mh_debug_reg56_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg56_t f;
+} mh_debug_reg56_u;
+
+
+/*
+ * MH_DEBUG_REG57 struct
+ */
+
+#define MH_DEBUG_REG57_TAG8_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_8_SIZE 1
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG57_TAG9_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_9_SIZE 1
+
+#define MH_DEBUG_REG57_TAG8_VA_SHIFT   0
+#define MH_DEBUG_REG57_TAG_valid_q_8_SHIFT 13
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG57_TAG9_VA_SHIFT   16
+#define MH_DEBUG_REG57_TAG_valid_q_9_SHIFT 29
+
+#define MH_DEBUG_REG57_TAG8_VA_MASK    0x00001fff
+#define MH_DEBUG_REG57_TAG_valid_q_8_MASK 0x00002000
+#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG57_TAG9_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG57_TAG_valid_q_9_MASK 0x20000000
+
+#define MH_DEBUG_REG57_MASK \
+     (MH_DEBUG_REG57_TAG8_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_8_MASK | \
+      MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG57_TAG9_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_9_MASK)
+
+#define MH_DEBUG_REG57(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \
+     ((tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT) | \
+      (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) | \
+      (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \
+      (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT) | \
+      (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT))
+
+#define MH_DEBUG_REG57_GET_TAG8_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG8_VA_MASK) >> MH_DEBUG_REG57_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_8(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_8_MASK) >> MH_DEBUG_REG57_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG9_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG9_VA_MASK) >> MH_DEBUG_REG57_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_9(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_9_MASK) >> MH_DEBUG_REG57_TAG_valid_q_9_SHIFT)
+
+#define MH_DEBUG_REG57_SET_TAG8_VA(mh_debug_reg57_reg, tag8_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_8(mh_debug_reg57_reg, tag_valid_q_8) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG9_VA(mh_debug_reg57_reg, tag9_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_9(mh_debug_reg57_reg, tag_valid_q_9) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int tag8_va                        : MH_DEBUG_REG57_TAG8_VA_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG57_TAG_valid_q_8_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG57_TAG9_VA_SIZE;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG57_TAG_valid_q_9_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg57_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG57_TAG_valid_q_9_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG57_TAG9_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG57_TAG_valid_q_8_SIZE;
+          unsigned int tag8_va                        : MH_DEBUG_REG57_TAG8_VA_SIZE;
+     } mh_debug_reg57_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg57_t f;
+} mh_debug_reg57_u;
+
+
+/*
+ * MH_DEBUG_REG58 struct
+ */
+
+#define MH_DEBUG_REG58_TAG10_VA_SIZE   13
+#define MH_DEBUG_REG58_TAG_valid_q_10_SIZE 1
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG58_TAG11_VA_SIZE   13
+#define MH_DEBUG_REG58_TAG_valid_q_11_SIZE 1
+
+#define MH_DEBUG_REG58_TAG10_VA_SHIFT  0
+#define MH_DEBUG_REG58_TAG_valid_q_10_SHIFT 13
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG58_TAG11_VA_SHIFT  16
+#define MH_DEBUG_REG58_TAG_valid_q_11_SHIFT 29
+
+#define MH_DEBUG_REG58_TAG10_VA_MASK   0x00001fff
+#define MH_DEBUG_REG58_TAG_valid_q_10_MASK 0x00002000
+#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG58_TAG11_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG58_TAG_valid_q_11_MASK 0x20000000
+
+#define MH_DEBUG_REG58_MASK \
+     (MH_DEBUG_REG58_TAG10_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_10_MASK | \
+      MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG58_TAG11_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_11_MASK)
+
+#define MH_DEBUG_REG58(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \
+     ((tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT) | \
+      (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) | \
+      (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \
+      (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT) | \
+      (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT))
+
+#define MH_DEBUG_REG58_GET_TAG10_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG10_VA_MASK) >> MH_DEBUG_REG58_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_10(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_10_MASK) >> MH_DEBUG_REG58_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG11_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG11_VA_MASK) >> MH_DEBUG_REG58_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_11(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_11_MASK) >> MH_DEBUG_REG58_TAG_valid_q_11_SHIFT)
+
+#define MH_DEBUG_REG58_SET_TAG10_VA(mh_debug_reg58_reg, tag10_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_10(mh_debug_reg58_reg, tag_valid_q_10) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG11_VA(mh_debug_reg58_reg, tag11_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_11(mh_debug_reg58_reg, tag_valid_q_11) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int tag10_va                       : MH_DEBUG_REG58_TAG10_VA_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG58_TAG11_VA_SIZE;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg58_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG58_TAG11_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE;
+          unsigned int tag10_va                       : MH_DEBUG_REG58_TAG10_VA_SIZE;
+     } mh_debug_reg58_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg58_t f;
+} mh_debug_reg58_u;
+
+
+/*
+ * MH_DEBUG_REG59 struct
+ */
+
+#define MH_DEBUG_REG59_TAG12_VA_SIZE   13
+#define MH_DEBUG_REG59_TAG_valid_q_12_SIZE 1
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG59_TAG13_VA_SIZE   13
+#define MH_DEBUG_REG59_TAG_valid_q_13_SIZE 1
+
+#define MH_DEBUG_REG59_TAG12_VA_SHIFT  0
+#define MH_DEBUG_REG59_TAG_valid_q_12_SHIFT 13
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG59_TAG13_VA_SHIFT  16
+#define MH_DEBUG_REG59_TAG_valid_q_13_SHIFT 29
+
+#define MH_DEBUG_REG59_TAG12_VA_MASK   0x00001fff
+#define MH_DEBUG_REG59_TAG_valid_q_12_MASK 0x00002000
+#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG59_TAG13_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG59_TAG_valid_q_13_MASK 0x20000000
+
+#define MH_DEBUG_REG59_MASK \
+     (MH_DEBUG_REG59_TAG12_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_12_MASK | \
+      MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG59_TAG13_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_13_MASK)
+
+#define MH_DEBUG_REG59(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \
+     ((tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT) | \
+      (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) | \
+      (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \
+      (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT) | \
+      (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT))
+
+#define MH_DEBUG_REG59_GET_TAG12_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG12_VA_MASK) >> MH_DEBUG_REG59_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_12(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_12_MASK) >> MH_DEBUG_REG59_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG13_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG13_VA_MASK) >> MH_DEBUG_REG59_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_13(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_13_MASK) >> MH_DEBUG_REG59_TAG_valid_q_13_SHIFT)
+
+#define MH_DEBUG_REG59_SET_TAG12_VA(mh_debug_reg59_reg, tag12_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_12(mh_debug_reg59_reg, tag_valid_q_12) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG13_VA(mh_debug_reg59_reg, tag13_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_13(mh_debug_reg59_reg, tag_valid_q_13) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int tag12_va                       : MH_DEBUG_REG59_TAG12_VA_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG59_TAG13_VA_SIZE;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg59_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG59_TAG13_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE;
+          unsigned int tag12_va                       : MH_DEBUG_REG59_TAG12_VA_SIZE;
+     } mh_debug_reg59_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg59_t f;
+} mh_debug_reg59_u;
+
+
+/*
+ * MH_DEBUG_REG60 struct
+ */
+
+#define MH_DEBUG_REG60_TAG14_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_14_SIZE 1
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG60_TAG15_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_15_SIZE 1
+
+#define MH_DEBUG_REG60_TAG14_VA_SHIFT  0
+#define MH_DEBUG_REG60_TAG_valid_q_14_SHIFT 13
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG60_TAG15_VA_SHIFT  16
+#define MH_DEBUG_REG60_TAG_valid_q_15_SHIFT 29
+
+#define MH_DEBUG_REG60_TAG14_VA_MASK   0x00001fff
+#define MH_DEBUG_REG60_TAG_valid_q_14_MASK 0x00002000
+#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG60_TAG15_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG60_TAG_valid_q_15_MASK 0x20000000
+
+#define MH_DEBUG_REG60_MASK \
+     (MH_DEBUG_REG60_TAG14_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_14_MASK | \
+      MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG60_TAG15_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_15_MASK)
+
+#define MH_DEBUG_REG60(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \
+     ((tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT) | \
+      (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) | \
+      (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \
+      (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT) | \
+      (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT))
+
+#define MH_DEBUG_REG60_GET_TAG14_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG14_VA_MASK) >> MH_DEBUG_REG60_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_14(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_14_MASK) >> MH_DEBUG_REG60_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG15_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG15_VA_MASK) >> MH_DEBUG_REG60_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_15(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_15_MASK) >> MH_DEBUG_REG60_TAG_valid_q_15_SHIFT)
+
+#define MH_DEBUG_REG60_SET_TAG14_VA(mh_debug_reg60_reg, tag14_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_14(mh_debug_reg60_reg, tag_valid_q_14) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG15_VA(mh_debug_reg60_reg, tag15_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_15(mh_debug_reg60_reg, tag_valid_q_15) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int tag14_va                       : MH_DEBUG_REG60_TAG14_VA_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG60_TAG15_VA_SIZE;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg60_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG60_TAG15_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE;
+          unsigned int tag14_va                       : MH_DEBUG_REG60_TAG14_VA_SIZE;
+     } mh_debug_reg60_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg60_t f;
+} mh_debug_reg60_u;
+
+
+/*
+ * MH_DEBUG_REG61 struct
+ */
+
+#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG61_MASK \
+     (MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG61(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG61_GET_MH_DBG_DEFAULT(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG61_SET_MH_DBG_DEFAULT(mh_debug_reg61_reg, mh_dbg_default) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg61_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg61_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg61_t f;
+} mh_debug_reg61_u;
+
+
+/*
+ * MH_DEBUG_REG62 struct
+ */
+
+#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG62_MASK \
+     (MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG62(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG62_GET_MH_DBG_DEFAULT(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG62_SET_MH_DBG_DEFAULT(mh_debug_reg62_reg, mh_dbg_default) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg62_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg62_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg62_t f;
+} mh_debug_reg62_u;
+
+
+/*
+ * MH_DEBUG_REG63 struct
+ */
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG63_MASK \
+     (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG63(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \
+     ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \
+     mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg63_t f;
+} mh_debug_reg63_u;
+
+
+/*
+ * MH_MMU_CONFIG struct
+ */
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SIZE  1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1
+#define MH_MMU_CONFIG_RESERVED1_SIZE   2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1
+#define MH_MMU_CONFIG_RESERVED1_SHIFT  2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22
+
+#define MH_MMU_CONFIG_MMU_ENABLE_MASK  0x00000001
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002
+#define MH_MMU_CONFIG_RESERVED1_MASK   0x0000000c
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000
+
+#define MH_MMU_CONFIG_MASK \
+     (MH_MMU_CONFIG_MMU_ENABLE_MASK | \
+      MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \
+      MH_MMU_CONFIG_RESERVED1_MASK | \
+      MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK)
+
+#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior) \
+     ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \
+      (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \
+      (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \
+      (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT))
+
+#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+
+#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int                                : 8;
+     } mh_mmu_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int                                : 8;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+     } mh_mmu_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_config_t f;
+} mh_mmu_config_u;
+
+
+/*
+ * MH_MMU_VA_RANGE struct
+ */
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12
+#define MH_MMU_VA_RANGE_VA_BASE_SIZE   20
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0
+#define MH_MMU_VA_RANGE_VA_BASE_SHIFT  12
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff
+#define MH_MMU_VA_RANGE_VA_BASE_MASK   0xfffff000
+
+#define MH_MMU_VA_RANGE_MASK \
+     (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \
+      MH_MMU_VA_RANGE_VA_BASE_MASK)
+
+#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \
+     ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \
+      (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT))
+
+#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+     } mh_mmu_va_range_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+     } mh_mmu_va_range_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_va_range_t f;
+} mh_mmu_va_range_u;
+
+
+/*
+ * MH_MMU_PT_BASE struct
+ */
+
+#define MH_MMU_PT_BASE_PT_BASE_SIZE    20
+
+#define MH_MMU_PT_BASE_PT_BASE_SHIFT   12
+
+#define MH_MMU_PT_BASE_PT_BASE_MASK    0xfffff000
+
+#define MH_MMU_PT_BASE_MASK \
+     (MH_MMU_PT_BASE_PT_BASE_MASK)
+
+#define MH_MMU_PT_BASE(pt_base) \
+     ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT))
+
+#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \
+     ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \
+     mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int                                : 12;
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+     } mh_mmu_pt_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_pt_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_pt_base_t f;
+} mh_mmu_pt_base_u;
+
+
+/*
+ * MH_MMU_PAGE_FAULT struct
+ */
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE  3
+#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE  20
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4
+#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11
+#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001
+#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c
+#define MH_MMU_PAGE_FAULT_AXI_ID_MASK  0x00000070
+#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800
+#define MH_MMU_PAGE_FAULT_REQ_VA_MASK  0xfffff000
+
+#define MH_MMU_PAGE_FAULT_MASK \
+     (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \
+      MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \
+      MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_PAGE_FAULT_AXI_ID_MASK | \
+      MH_MMU_PAGE_FAULT_RESERVED1_MASK | \
+      MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_REQ_VA_MASK)
+
+#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \
+     ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \
+      (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \
+      (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \
+      (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \
+      (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \
+      (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \
+      (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \
+      (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT))
+
+#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+     } mh_mmu_page_fault_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+     } mh_mmu_page_fault_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_page_fault_t f;
+} mh_mmu_page_fault_u;
+
+
+/*
+ * MH_MMU_TRAN_ERROR struct
+ */
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0
+
+#define MH_MMU_TRAN_ERROR_MASK \
+     (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK)
+
+#define MH_MMU_TRAN_ERROR(tran_error) \
+     ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT))
+
+#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \
+     ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \
+     mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int                                : 5;
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+     } mh_mmu_tran_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+          unsigned int                                : 5;
+     } mh_mmu_tran_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_tran_error_t f;
+} mh_mmu_tran_error_u;
+
+
+/*
+ * MH_MMU_INVALIDATE struct
+ */
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002
+
+#define MH_MMU_INVALIDATE_MASK \
+     (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_MMU_INVALIDATE_INVALIDATE_TC_MASK)
+
+#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \
+     ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT))
+
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int                                : 30;
+     } mh_mmu_invalidate_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int                                : 30;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+     } mh_mmu_invalidate_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_invalidate_t f;
+} mh_mmu_invalidate_u;
+
+
+/*
+ * MH_MMU_MPU_BASE struct
+ */
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SIZE  20
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12
+
+#define MH_MMU_MPU_BASE_MPU_BASE_MASK  0xfffff000
+
+#define MH_MMU_MPU_BASE_MASK \
+     (MH_MMU_MPU_BASE_MPU_BASE_MASK)
+
+#define MH_MMU_MPU_BASE(mpu_base) \
+     ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT))
+
+#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \
+     ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \
+     mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int                                : 12;
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+     } mh_mmu_mpu_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_base_t f;
+} mh_mmu_mpu_base_u;
+
+
+/*
+ * MH_MMU_MPU_END struct
+ */
+
+#define MH_MMU_MPU_END_MPU_END_SIZE    20
+
+#define MH_MMU_MPU_END_MPU_END_SHIFT   12
+
+#define MH_MMU_MPU_END_MPU_END_MASK    0xfffff000
+
+#define MH_MMU_MPU_END_MASK \
+     (MH_MMU_MPU_END_MPU_END_MASK)
+
+#define MH_MMU_MPU_END(mpu_end) \
+     ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT))
+
+#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \
+     ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \
+     mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int                                : 12;
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+     } mh_mmu_mpu_end_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_end_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_end_t f;
+} mh_mmu_mpu_end_u;
+
+
+#endif
+
+
+#if !defined (_PA_FIDDLE_H)
+#define _PA_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * PA_CL_VPORT_XSCALE struct
+ */
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_XSCALE_MASK \
+     (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK)
+
+#define PA_CL_VPORT_XSCALE(vport_xscale) \
+     ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT))
+
+#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \
+     ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \
+     pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xscale_t f;
+} pa_cl_vport_xscale_u;
+
+
+/*
+ * PA_CL_VPORT_XOFFSET struct
+ */
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_XOFFSET_MASK \
+     (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK)
+
+#define PA_CL_VPORT_XOFFSET(vport_xoffset) \
+     ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT))
+
+#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \
+     ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \
+     pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xoffset_t f;
+} pa_cl_vport_xoffset_u;
+
+
+/*
+ * PA_CL_VPORT_YSCALE struct
+ */
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_YSCALE_MASK \
+     (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK)
+
+#define PA_CL_VPORT_YSCALE(vport_yscale) \
+     ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT))
+
+#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \
+     ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \
+     pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yscale_t f;
+} pa_cl_vport_yscale_u;
+
+
+/*
+ * PA_CL_VPORT_YOFFSET struct
+ */
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_YOFFSET_MASK \
+     (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK)
+
+#define PA_CL_VPORT_YOFFSET(vport_yoffset) \
+     ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT))
+
+#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \
+     ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \
+     pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yoffset_t f;
+} pa_cl_vport_yoffset_u;
+
+
+/*
+ * PA_CL_VPORT_ZSCALE struct
+ */
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZSCALE_MASK \
+     (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK)
+
+#define PA_CL_VPORT_ZSCALE(vport_zscale) \
+     ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT))
+
+#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \
+     ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \
+     pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zscale_t f;
+} pa_cl_vport_zscale_u;
+
+
+/*
+ * PA_CL_VPORT_ZOFFSET struct
+ */
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZOFFSET_MASK \
+     (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK)
+
+#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \
+     ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT))
+
+#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \
+     ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \
+     pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zoffset_t f;
+} pa_cl_vport_zoffset_u;
+
+
+/*
+ * PA_CL_VTE_CNTL struct
+ */
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE  1
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK  0x00000200
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800
+
+#define PA_CL_VTE_CNTL_MASK \
+     (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \
+      PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK)
+
+#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \
+     ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \
+      (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \
+      (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \
+      (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \
+      (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \
+      (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \
+      (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \
+      (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \
+      (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \
+      (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT))
+
+#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int                                : 2;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int                                : 20;
+     } pa_cl_vte_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int                                : 20;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int                                : 2;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+     } pa_cl_vte_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vte_cntl_t f;
+} pa_cl_vte_cntl_u;
+
+
+/*
+ * PA_CL_CLIP_CNTL struct
+ */
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000
+
+#define PA_CL_CLIP_CNTL_MASK \
+     (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \
+      PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \
+      PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \
+      PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \
+      PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \
+      PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK)
+
+#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \
+     ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \
+      (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \
+      (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \
+      (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \
+      (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \
+      (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \
+      (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \
+      (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT))
+
+#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 16;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int                                : 7;
+     } pa_cl_clip_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 7;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 16;
+     } pa_cl_clip_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_clip_cntl_t f;
+} pa_cl_clip_cntl_u;
+
+
+/*
+ * PA_CL_GB_VERT_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_CLIP_ADJ_MASK \
+     (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \
+     ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \
+     pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_clip_adj_t f;
+} pa_cl_gb_vert_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_VERT_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_DISC_ADJ_MASK \
+     (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \
+     ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \
+     pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_disc_adj_t f;
+} pa_cl_gb_vert_disc_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \
+     (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \
+     ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \
+     pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_clip_adj_t f;
+} pa_cl_gb_horz_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_DISC_ADJ_MASK \
+     (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \
+     ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \
+     pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_disc_adj_t f;
+} pa_cl_gb_horz_disc_adj_u;
+
+
+/*
+ * PA_CL_ENHANCE struct
+ */
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1
+#define PA_CL_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0
+#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001
+#define PA_CL_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_CL_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_CL_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_CL_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_CL_ENHANCE_MASK \
+     (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE3_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE2_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE1_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \
+      (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+          unsigned int                                : 27;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_cl_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 27;
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+     } pa_cl_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_enhance_t f;
+} pa_cl_enhance_u;
+
+
+/*
+ * PA_SC_ENHANCE struct
+ */
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_SC_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_SC_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_SC_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_SC_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_SC_ENHANCE_MASK \
+     (PA_SC_ENHANCE_ECO_SPARE3_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE2_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE1_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int                                : 28;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_sc_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 28;
+     } pa_sc_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_enhance_t f;
+} pa_sc_enhance_u;
+
+
+/*
+ * PA_SU_VTX_CNTL struct
+ */
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1
+#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2
+#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0
+#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1
+#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001
+#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006
+#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038
+
+#define PA_SU_VTX_CNTL_MASK \
+     (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \
+      PA_SU_VTX_CNTL_ROUND_MODE_MASK | \
+      PA_SU_VTX_CNTL_QUANT_MODE_MASK)
+
+#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \
+     ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \
+      (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \
+      (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT))
+
+#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int                                : 26;
+     } pa_su_vtx_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int                                : 26;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+     } pa_su_vtx_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_vtx_cntl_t f;
+} pa_su_vtx_cntl_u;
+
+
+/*
+ * PA_SU_POINT_SIZE struct
+ */
+
+#define PA_SU_POINT_SIZE_HEIGHT_SIZE   16
+#define PA_SU_POINT_SIZE_WIDTH_SIZE    16
+
+#define PA_SU_POINT_SIZE_HEIGHT_SHIFT  0
+#define PA_SU_POINT_SIZE_WIDTH_SHIFT   16
+
+#define PA_SU_POINT_SIZE_HEIGHT_MASK   0x0000ffff
+#define PA_SU_POINT_SIZE_WIDTH_MASK    0xffff0000
+
+#define PA_SU_POINT_SIZE_MASK \
+     (PA_SU_POINT_SIZE_HEIGHT_MASK | \
+      PA_SU_POINT_SIZE_WIDTH_MASK)
+
+#define PA_SU_POINT_SIZE(height, width) \
+     ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \
+      (width << PA_SU_POINT_SIZE_WIDTH_SHIFT))
+
+#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+     } pa_su_point_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+     } pa_su_point_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_size_t f;
+} pa_su_point_size_u;
+
+
+/*
+ * PA_SU_POINT_MINMAX struct
+ */
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff
+#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000
+
+#define PA_SU_POINT_MINMAX_MASK \
+     (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \
+      PA_SU_POINT_MINMAX_MAX_SIZE_MASK)
+
+#define PA_SU_POINT_MINMAX(min_size, max_size) \
+     ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \
+      (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT))
+
+#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_minmax_t f;
+} pa_su_point_minmax_u;
+
+
+/*
+ * PA_SU_LINE_CNTL struct
+ */
+
+#define PA_SU_LINE_CNTL_WIDTH_SIZE     16
+
+#define PA_SU_LINE_CNTL_WIDTH_SHIFT    0
+
+#define PA_SU_LINE_CNTL_WIDTH_MASK     0x0000ffff
+
+#define PA_SU_LINE_CNTL_MASK \
+     (PA_SU_LINE_CNTL_WIDTH_MASK)
+
+#define PA_SU_LINE_CNTL(width) \
+     ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT))
+
+#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \
+     ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \
+     pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+          unsigned int                                : 16;
+     } pa_su_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int                                : 16;
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+     } pa_su_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_line_cntl_t f;
+} pa_su_line_cntl_u;
+
+
+/*
+ * PA_SU_SC_MODE_CNTL struct
+ */
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_SIZE   1
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1
+#define PA_SU_SC_MODE_CNTL_FACE_SHIFT  2
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002
+#define PA_SU_SC_MODE_CNTL_FACE_MASK   0x00000004
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000
+
+#define PA_SU_SC_MODE_CNTL_MASK \
+     (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \
+      PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \
+      PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \
+      PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \
+      PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK)
+
+#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state) \
+     ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \
+      (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \
+      (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \
+      (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \
+      (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \
+      (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \
+      (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \
+      (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \
+      (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \
+      (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \
+      (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \
+      (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \
+      (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \
+      (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \
+      (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \
+      (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \
+      (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \
+      (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT))
+
+#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+
+#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int                                : 5;
+     } pa_su_sc_mode_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int                                : 5;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_sc_mode_cntl_t f;
+} pa_su_sc_mode_cntl_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \
+     ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \
+     pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_scale_t f;
+} pa_su_poly_offset_front_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \
+     ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \
+     pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_offset_t f;
+} pa_su_poly_offset_front_offset_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \
+     ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \
+     pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_scale_t f;
+} pa_su_poly_offset_back_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \
+     ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \
+     pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_offset_t f;
+} pa_su_poly_offset_back_offset_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER0_SELECT_MASK \
+     (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \
+     ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \
+     pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_select_t f;
+} pa_su_perfcounter0_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER1_SELECT_MASK \
+     (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \
+     ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \
+     pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_select_t f;
+} pa_su_perfcounter1_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER2_SELECT_MASK \
+     (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \
+     ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \
+     pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_select_t f;
+} pa_su_perfcounter2_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER3_SELECT_MASK \
+     (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \
+     ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \
+     pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_select_t f;
+} pa_su_perfcounter3_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER0_LOW_MASK \
+     (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \
+     ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \
+     pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_low_t f;
+} pa_su_perfcounter0_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER0_HI_MASK \
+     (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \
+     ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \
+     pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_hi_t f;
+} pa_su_perfcounter0_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER1_LOW_MASK \
+     (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \
+     ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \
+     pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_low_t f;
+} pa_su_perfcounter1_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER1_HI_MASK \
+     (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \
+     ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \
+     pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_hi_t f;
+} pa_su_perfcounter1_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER2_LOW_MASK \
+     (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \
+     ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \
+     pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_low_t f;
+} pa_su_perfcounter2_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER2_HI_MASK \
+     (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \
+     ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \
+     pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_hi_t f;
+} pa_su_perfcounter2_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER3_LOW_MASK \
+     (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \
+     ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \
+     pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_low_t f;
+} pa_su_perfcounter3_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER3_HI_MASK \
+     (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \
+     ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \
+     pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_hi_t f;
+} pa_su_perfcounter3_hi_u;
+
+
+/*
+ * PA_SC_WINDOW_OFFSET struct
+ */
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000
+
+#define PA_SC_WINDOW_OFFSET_MASK \
+     (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \
+      PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK)
+
+#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \
+     ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \
+      (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT))
+
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_window_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+     } pa_sc_window_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_offset_t f;
+} pa_sc_window_offset_u;
+
+
+/*
+ * PA_SC_AA_CONFIG struct
+ */
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000
+
+#define PA_SC_AA_CONFIG_MASK \
+     (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \
+      PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK)
+
+#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \
+     ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \
+      (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT))
+
+#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+          unsigned int                                : 10;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 15;
+     } pa_sc_aa_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int                                : 15;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 10;
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+     } pa_sc_aa_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_config_t f;
+} pa_sc_aa_config_u;
+
+
+/*
+ * PA_SC_AA_MASK struct
+ */
+
+#define PA_SC_AA_MASK_AA_MASK_SIZE     16
+
+#define PA_SC_AA_MASK_AA_MASK_SHIFT    0
+
+#define PA_SC_AA_MASK_AA_MASK_MASK     0x0000ffff
+
+#define PA_SC_AA_MASK_MASK \
+     (PA_SC_AA_MASK_AA_MASK_MASK)
+
+#define PA_SC_AA_MASK(aa_mask) \
+     ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT))
+
+#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \
+     ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \
+     pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_aa_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int                                : 16;
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+     } pa_sc_aa_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_mask_t f;
+} pa_sc_aa_mask_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000
+
+#define PA_SC_LINE_STIPPLE_MASK \
+     (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \
+      PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \
+      PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \
+      PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK)
+
+#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \
+     ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \
+      (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \
+      (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \
+      (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_line_stipple_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int                                : 1;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int                                : 4;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+     } pa_sc_line_stipple_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_t f;
+} pa_sc_line_stipple_u;
+
+
+/*
+ * PA_SC_LINE_CNTL struct
+ */
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200
+#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400
+
+#define PA_SC_LINE_CNTL_MASK \
+     (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \
+      PA_SC_LINE_CNTL_LAST_PIXEL_MASK)
+
+#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \
+     ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \
+      (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \
+      (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \
+      (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT))
+
+#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int                                : 21;
+     } pa_sc_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int                                : 21;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+     } pa_sc_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_cntl_t f;
+} pa_sc_line_cntl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_TL struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000
+
+#define PA_SC_WINDOW_SCISSOR_TL_MASK \
+     (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \
+     ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \
+      (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_tl_t f;
+} pa_sc_window_scissor_tl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_BR struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000
+
+#define PA_SC_WINDOW_SCISSOR_BR_MASK \
+     (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+     } pa_sc_window_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_window_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_br_t f;
+} pa_sc_window_scissor_br_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_TL struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_TL_MASK \
+     (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \
+     ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_screen_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_tl_t f;
+} pa_sc_screen_scissor_tl_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_BR struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_BR_MASK \
+     (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_screen_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_br_t f;
+} pa_sc_screen_scissor_br_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY struct
+ */
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080
+
+#define PA_SC_VIZ_QUERY_MASK \
+     (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \
+      PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \
+      PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK)
+
+#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \
+     ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \
+      (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \
+      (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT))
+
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int                                : 1;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_viz_query_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int                                : 24;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 1;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+     } pa_sc_viz_query_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_t f;
+} pa_sc_viz_query_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY_STATUS struct
+ */
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff
+
+#define PA_SC_VIZ_QUERY_STATUS_MASK \
+     (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK)
+
+#define PA_SC_VIZ_QUERY_STATUS(status_bits) \
+     ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT))
+
+#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \
+     ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \
+     pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_status_t f;
+} pa_sc_viz_query_status_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE_STATE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00
+
+#define PA_SC_LINE_STIPPLE_STATE_MASK \
+     (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \
+      PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK)
+
+#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \
+     ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \
+      (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_line_stipple_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int                                : 16;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+     } pa_sc_line_stipple_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_state_t f;
+} pa_sc_line_stipple_state_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SC_PERFCOUNTER0_SELECT_MASK \
+     (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \
+     ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \
+     pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_sc_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_select_t f;
+} pa_sc_perfcounter0_select_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SC_PERFCOUNTER0_LOW_MASK \
+     (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \
+     ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \
+     pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_low_t f;
+} pa_sc_perfcounter0_low_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SC_PERFCOUNTER0_HI_MASK \
+     (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \
+     ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \
+     pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_hi_t f;
+} pa_sc_perfcounter0_hi_u;
+
+
+/*
+ * PA_CL_CNTL_STATUS struct
+ */
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000
+
+#define PA_CL_CNTL_STATUS_MASK \
+     (PA_CL_CNTL_STATUS_CL_BUSY_MASK)
+
+#define PA_CL_CNTL_STATUS(cl_busy) \
+     ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT))
+
+#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \
+     ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \
+     pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+     } pa_cl_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_cl_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_cntl_status_t f;
+} pa_cl_cntl_status_u;
+
+
+/*
+ * PA_SU_CNTL_STATUS struct
+ */
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000
+
+#define PA_SU_CNTL_STATUS_MASK \
+     (PA_SU_CNTL_STATUS_SU_BUSY_MASK)
+
+#define PA_SU_CNTL_STATUS(su_busy) \
+     ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT))
+
+#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \
+     ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \
+     pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+     } pa_su_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_su_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_cntl_status_t f;
+} pa_su_cntl_status_u;
+
+
+/*
+ * PA_SC_CNTL_STATUS struct
+ */
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000
+
+#define PA_SC_CNTL_STATUS_MASK \
+     (PA_SC_CNTL_STATUS_SC_BUSY_MASK)
+
+#define PA_SC_CNTL_STATUS(sc_busy) \
+     ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT))
+
+#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \
+     ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \
+     pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+     } pa_sc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_sc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_cntl_status_t f;
+} pa_sc_cntl_status_u;
+
+
+/*
+ * PA_SU_DEBUG_CNTL struct
+ */
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SU_DEBUG_CNTL_MASK \
+     (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK)
+
+#define PA_SU_DEBUG_CNTL(su_debug_indx) \
+     ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT))
+
+#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \
+     ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \
+     pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_su_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+     } pa_su_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_cntl_t f;
+} pa_su_debug_cntl_u;
+
+
+/*
+ * PA_SU_DEBUG_DATA struct
+ */
+
+#define PA_SU_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SU_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SU_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SU_DEBUG_DATA_MASK \
+     (PA_SU_DEBUG_DATA_DATA_MASK)
+
+#define PA_SU_DEBUG_DATA(data) \
+     ((data << PA_SU_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \
+     ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \
+     pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_data_t f;
+} pa_su_debug_data_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG00 struct
+ */
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000
+
+#define CLIPPER_DEBUG_REG00_MASK \
+     (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \
+     ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \
+      (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \
+      (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \
+      (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \
+      (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \
+      (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \
+      (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \
+      (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \
+      (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \
+      (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \
+      (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \
+      (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \
+      (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \
+      (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \
+      (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \
+      (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \
+      (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \
+      (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \
+      (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \
+      (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+     } clipper_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg00_t f;
+} clipper_debug_reg00_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG01 struct
+ */
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000
+
+#define CLIPPER_DEBUG_REG01_MASK \
+     (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \
+      CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \
+     ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \
+      (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \
+      (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \
+      (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \
+      (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \
+      (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \
+      (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+     } clipper_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg01_t f;
+} clipper_debug_reg01_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG02 struct
+ */
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+
+#define CLIPPER_DEBUG_REG02_MASK \
+     (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \
+      CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK)
+
+#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \
+     ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \
+      (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT))
+
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+     } clipper_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+     } clipper_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg02_t f;
+} clipper_debug_reg02_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG03 struct
+ */
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG03_MASK \
+     (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \
+     ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+     } clipper_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg03_t f;
+} clipper_debug_reg03_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG04 struct
+ */
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00
+
+#define CLIPPER_DEBUG_REG04_MASK \
+     (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \
+     ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+     } clipper_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg04_t f;
+} clipper_debug_reg04_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG05 struct
+ */
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000
+
+#define CLIPPER_DEBUG_REG05_MASK \
+     (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \
+     ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \
+      (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+     } clipper_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg05_t f;
+} clipper_debug_reg05_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG09 struct
+ */
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000
+#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000
+
+#define CLIPPER_DEBUG_REG09_MASK \
+     (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \
+      CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK)
+
+#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \
+     ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \
+      (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \
+      (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \
+      (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \
+      (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \
+      (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \
+      (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \
+      (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \
+      (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT))
+
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+     } clipper_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+     } clipper_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg09_t f;
+} clipper_debug_reg09_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG10 struct
+ */
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG10_MASK \
+     (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK)
+
+#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \
+     ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \
+      (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \
+      (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \
+      (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \
+      (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT))
+
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+     } clipper_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+     } clipper_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg10_t f;
+} clipper_debug_reg10_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG11 struct
+ */
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0
+
+#define CLIPPER_DEBUG_REG11_MASK \
+     (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \
+      CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \
+     ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+     } clipper_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg11_t f;
+} clipper_debug_reg11_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG12 struct
+ */
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define CLIPPER_DEBUG_REG12_MASK \
+     (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \
+      CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \
+     ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \
+      (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \
+      (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \
+      (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \
+      (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \
+      (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+     } clipper_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg12_t f;
+} clipper_debug_reg12_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG13 struct
+ */
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000
+#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000
+
+#define CLIPPER_DEBUG_REG13_MASK \
+     (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \
+     ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \
+      (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \
+      (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \
+      (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+     } clipper_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg13_t f;
+} clipper_debug_reg13_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG0 struct
+ */
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4
+#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3
+#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0
+#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380
+#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000
+
+#define SXIFCCG_DEBUG_REG0_MASK \
+     (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \
+      SXIFCCG_DEBUG_REG0_position_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG0_point_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK)
+
+#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \
+     ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \
+      (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \
+      (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \
+      (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \
+      (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \
+      (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \
+      (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \
+      (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT))
+
+#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg0_t f;
+} sxifccg_debug_reg0_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG1 struct
+ */
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4
+#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c
+#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000
+#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000
+#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000
+
+#define SXIFCCG_DEBUG_REG1_MASK \
+     (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \
+      SXIFCCG_DEBUG_REG1_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \
+      SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG1_aux_sel_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \
+      SXIFCCG_DEBUG_REG1_param_cache_base_MASK)
+
+#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \
+     ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \
+      (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \
+      (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \
+      (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \
+      (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \
+      (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \
+      (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \
+      (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT))
+
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg1_t f;
+} sxifccg_debug_reg1_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG2 struct
+ */
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002
+#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8
+#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000
+
+#define SXIFCCG_DEBUG_REG2_MASK \
+     (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_aux_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK)
+
+#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \
+     ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \
+      (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \
+      (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \
+      (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \
+      (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \
+      (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \
+      (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \
+      (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \
+      (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \
+      (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT))
+
+#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg2_t f;
+} sxifccg_debug_reg2_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG3 struct
+ */
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4
+#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8
+#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010
+#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00
+#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define SXIFCCG_DEBUG_REG3_MASK \
+     (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG3_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG3_current_state_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK)
+
+#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \
+     ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \
+      (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \
+      (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \
+      (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \
+      (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \
+      (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \
+      (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \
+      (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT))
+
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg3_t f;
+} sxifccg_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG0 struct
+ */
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5
+#define SETUP_DEBUG_REG0_pmode_state_SIZE 6
+#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1
+#define SETUP_DEBUG_REG0_geom_enable_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1
+#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1
+#define SETUP_DEBUG_REG0_geom_busy_SIZE 1
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0
+#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5
+#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11
+#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13
+#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14
+#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15
+#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16
+#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17
+
+#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f
+#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0
+#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800
+#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000
+#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000
+#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000
+#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000
+#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000
+
+#define SETUP_DEBUG_REG0_MASK \
+     (SETUP_DEBUG_REG0_su_cntl_state_MASK | \
+      SETUP_DEBUG_REG0_pmode_state_MASK | \
+      SETUP_DEBUG_REG0_ge_stallb_MASK | \
+      SETUP_DEBUG_REG0_geom_enable_MASK | \
+      SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \
+      SETUP_DEBUG_REG0_su_clip_rtr_MASK | \
+      SETUP_DEBUG_REG0_pfifo_busy_MASK | \
+      SETUP_DEBUG_REG0_su_cntl_busy_MASK | \
+      SETUP_DEBUG_REG0_geom_busy_MASK)
+
+#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \
+     ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \
+      (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \
+      (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \
+      (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \
+      (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \
+      (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \
+      (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \
+      (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \
+      (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT))
+
+#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int                                : 14;
+     } setup_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int                                : 14;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+     } setup_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg0_t f;
+} setup_debug_reg0_u;
+
+
+/*
+ * SETUP_DEBUG_REG1 struct
+ */
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG1_MASK \
+     (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \
+      SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \
+     ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \
+      (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int                                : 4;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+     } setup_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg1_t f;
+} setup_debug_reg1_u;
+
+
+/*
+ * SETUP_DEBUG_REG2 struct
+ */
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG2_MASK \
+     (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \
+      SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \
+     ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \
+      (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int                                : 4;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+     } setup_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg2_t f;
+} setup_debug_reg2_u;
+
+
+/*
+ * SETUP_DEBUG_REG3 struct
+ */
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG3_MASK \
+     (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \
+      SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \
+     ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \
+      (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int                                : 4;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+     } setup_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg3_t f;
+} setup_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG4 struct
+ */
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11
+#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1
+#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3
+#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3
+#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2
+#define SETUP_DEBUG_REG4_type_gated_SIZE 3
+#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_event_gated_SIZE 1
+#define SETUP_DEBUG_REG4_eop_gated_SIZE 1
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0
+#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11
+#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12
+#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13
+#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17
+#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21
+#define SETUP_DEBUG_REG4_type_gated_SHIFT 23
+#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27
+#define SETUP_DEBUG_REG4_event_gated_SHIFT 28
+#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800
+#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000
+#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000
+#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000
+#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000
+#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000
+#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000
+#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000
+#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000
+#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000
+
+#define SETUP_DEBUG_REG4_MASK \
+     (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \
+      SETUP_DEBUG_REG4_null_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_backfacing_gated_MASK | \
+      SETUP_DEBUG_REG4_st_indx_gated_MASK | \
+      SETUP_DEBUG_REG4_clipped_gated_MASK | \
+      SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \
+      SETUP_DEBUG_REG4_xmajor_gated_MASK | \
+      SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \
+      SETUP_DEBUG_REG4_type_gated_MASK | \
+      SETUP_DEBUG_REG4_fpov_gated_MASK | \
+      SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_event_gated_MASK | \
+      SETUP_DEBUG_REG4_eop_gated_MASK)
+
+#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \
+     ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \
+      (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \
+      (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \
+      (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \
+      (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \
+      (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \
+      (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \
+      (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \
+      (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \
+      (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \
+      (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \
+      (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \
+      (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT))
+
+#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int                                : 2;
+     } setup_debug_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int                                : 2;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+     } setup_debug_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg4_t f;
+} setup_debug_reg4_u;
+
+
+/*
+ * SETUP_DEBUG_REG5 struct
+ */
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2
+#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22
+#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000
+#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000
+
+#define SETUP_DEBUG_REG5_MASK \
+     (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \
+      SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \
+      SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \
+      SETUP_DEBUG_REG5_event_id_gated_MASK)
+
+#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \
+     ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \
+      (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \
+      (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \
+      (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT))
+
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int                                : 3;
+     } setup_debug_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int                                : 3;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+     } setup_debug_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg5_t f;
+} setup_debug_reg5_u;
+
+
+/*
+ * PA_SC_DEBUG_CNTL struct
+ */
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SC_DEBUG_CNTL_MASK \
+     (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK)
+
+#define PA_SC_DEBUG_CNTL(sc_debug_indx) \
+     ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT))
+
+#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \
+     ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \
+     pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_sc_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+     } pa_sc_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_cntl_t f;
+} pa_sc_debug_cntl_u;
+
+
+/*
+ * PA_SC_DEBUG_DATA struct
+ */
+
+#define PA_SC_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SC_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SC_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SC_DEBUG_DATA_MASK \
+     (PA_SC_DEBUG_DATA_DATA_MASK)
+
+#define PA_SC_DEBUG_DATA(data) \
+     ((data << PA_SC_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \
+     ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \
+     pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_data_t f;
+} pa_sc_debug_data_u;
+
+
+/*
+ * SC_DEBUG_0 struct
+ */
+
+#define SC_DEBUG_0_pa_freeze_b1_SIZE   1
+#define SC_DEBUG_0_pa_sc_valid_SIZE    1
+#define SC_DEBUG_0_pa_sc_phase_SIZE    3
+#define SC_DEBUG_0_cntx_cnt_SIZE       7
+#define SC_DEBUG_0_decr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_incr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_trigger_SIZE        1
+
+#define SC_DEBUG_0_pa_freeze_b1_SHIFT  0
+#define SC_DEBUG_0_pa_sc_valid_SHIFT   1
+#define SC_DEBUG_0_pa_sc_phase_SHIFT   2
+#define SC_DEBUG_0_cntx_cnt_SHIFT      5
+#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12
+#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13
+#define SC_DEBUG_0_trigger_SHIFT       31
+
+#define SC_DEBUG_0_pa_freeze_b1_MASK   0x00000001
+#define SC_DEBUG_0_pa_sc_valid_MASK    0x00000002
+#define SC_DEBUG_0_pa_sc_phase_MASK    0x0000001c
+#define SC_DEBUG_0_cntx_cnt_MASK       0x00000fe0
+#define SC_DEBUG_0_decr_cntx_cnt_MASK  0x00001000
+#define SC_DEBUG_0_incr_cntx_cnt_MASK  0x00002000
+#define SC_DEBUG_0_trigger_MASK        0x80000000
+
+#define SC_DEBUG_0_MASK \
+     (SC_DEBUG_0_pa_freeze_b1_MASK | \
+      SC_DEBUG_0_pa_sc_valid_MASK | \
+      SC_DEBUG_0_pa_sc_phase_MASK | \
+      SC_DEBUG_0_cntx_cnt_MASK | \
+      SC_DEBUG_0_decr_cntx_cnt_MASK | \
+      SC_DEBUG_0_incr_cntx_cnt_MASK | \
+      SC_DEBUG_0_trigger_MASK)
+
+#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \
+     ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \
+      (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \
+      (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \
+      (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \
+      (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \
+      (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \
+      (trigger << SC_DEBUG_0_trigger_SHIFT))
+
+#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_trigger(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT)
+
+#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int                                : 17;
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+     } sc_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+          unsigned int                                : 17;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+     } sc_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_0_t f;
+} sc_debug_0_u;
+
+
+/*
+ * SC_DEBUG_1 struct
+ */
+
+#define SC_DEBUG_1_em_state_SIZE       3
+#define SC_DEBUG_1_em1_data_ready_SIZE 1
+#define SC_DEBUG_1_em2_data_ready_SIZE 1
+#define SC_DEBUG_1_move_em1_to_em2_SIZE 1
+#define SC_DEBUG_1_ef_data_ready_SIZE  1
+#define SC_DEBUG_1_ef_state_SIZE       2
+#define SC_DEBUG_1_pipe_valid_SIZE     1
+#define SC_DEBUG_1_trigger_SIZE        1
+
+#define SC_DEBUG_1_em_state_SHIFT      0
+#define SC_DEBUG_1_em1_data_ready_SHIFT 3
+#define SC_DEBUG_1_em2_data_ready_SHIFT 4
+#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5
+#define SC_DEBUG_1_ef_data_ready_SHIFT 6
+#define SC_DEBUG_1_ef_state_SHIFT      7
+#define SC_DEBUG_1_pipe_valid_SHIFT    9
+#define SC_DEBUG_1_trigger_SHIFT       31
+
+#define SC_DEBUG_1_em_state_MASK       0x00000007
+#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008
+#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010
+#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020
+#define SC_DEBUG_1_ef_data_ready_MASK  0x00000040
+#define SC_DEBUG_1_ef_state_MASK       0x00000180
+#define SC_DEBUG_1_pipe_valid_MASK     0x00000200
+#define SC_DEBUG_1_trigger_MASK        0x80000000
+
+#define SC_DEBUG_1_MASK \
+     (SC_DEBUG_1_em_state_MASK | \
+      SC_DEBUG_1_em1_data_ready_MASK | \
+      SC_DEBUG_1_em2_data_ready_MASK | \
+      SC_DEBUG_1_move_em1_to_em2_MASK | \
+      SC_DEBUG_1_ef_data_ready_MASK | \
+      SC_DEBUG_1_ef_state_MASK | \
+      SC_DEBUG_1_pipe_valid_MASK | \
+      SC_DEBUG_1_trigger_MASK)
+
+#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \
+     ((em_state << SC_DEBUG_1_em_state_SHIFT) | \
+      (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \
+      (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \
+      (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \
+      (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \
+      (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \
+      (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \
+      (trigger << SC_DEBUG_1_trigger_SHIFT))
+
+#define SC_DEBUG_1_GET_em_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_GET_trigger(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT)
+
+#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int                                : 21;
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+     } sc_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+          unsigned int                                : 21;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+     } sc_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_1_t f;
+} sc_debug_1_u;
+
+
+/*
+ * SC_DEBUG_2 struct
+ */
+
+#define SC_DEBUG_2_rc_rtr_dly_SIZE     1
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1
+#define SC_DEBUG_2_pipe_freeze_b_SIZE  1
+#define SC_DEBUG_2_prim_rts_SIZE       1
+#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1
+#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1
+#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1
+#define SC_DEBUG_2_stage0_rts_SIZE     1
+#define SC_DEBUG_2_phase_rts_dly_SIZE  1
+#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1
+#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1
+#define SC_DEBUG_2_event_id_s1_SIZE    5
+#define SC_DEBUG_2_event_s1_SIZE       1
+#define SC_DEBUG_2_trigger_SIZE        1
+
+#define SC_DEBUG_2_rc_rtr_dly_SHIFT    0
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1
+#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3
+#define SC_DEBUG_2_prim_rts_SHIFT      4
+#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5
+#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6
+#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7
+#define SC_DEBUG_2_stage0_rts_SHIFT    8
+#define SC_DEBUG_2_phase_rts_dly_SHIFT 9
+#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15
+#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16
+#define SC_DEBUG_2_event_id_s1_SHIFT   17
+#define SC_DEBUG_2_event_s1_SHIFT      22
+#define SC_DEBUG_2_trigger_SHIFT       31
+
+#define SC_DEBUG_2_rc_rtr_dly_MASK     0x00000001
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002
+#define SC_DEBUG_2_pipe_freeze_b_MASK  0x00000008
+#define SC_DEBUG_2_prim_rts_MASK       0x00000010
+#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020
+#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040
+#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080
+#define SC_DEBUG_2_stage0_rts_MASK     0x00000100
+#define SC_DEBUG_2_phase_rts_dly_MASK  0x00000200
+#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000
+#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000
+#define SC_DEBUG_2_event_id_s1_MASK    0x003e0000
+#define SC_DEBUG_2_event_s1_MASK       0x00400000
+#define SC_DEBUG_2_trigger_MASK        0x80000000
+
+#define SC_DEBUG_2_MASK \
+     (SC_DEBUG_2_rc_rtr_dly_MASK | \
+      SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \
+      SC_DEBUG_2_pipe_freeze_b_MASK | \
+      SC_DEBUG_2_prim_rts_MASK | \
+      SC_DEBUG_2_next_prim_rts_dly_MASK | \
+      SC_DEBUG_2_next_prim_rtr_dly_MASK | \
+      SC_DEBUG_2_pre_stage1_rts_d1_MASK | \
+      SC_DEBUG_2_stage0_rts_MASK | \
+      SC_DEBUG_2_phase_rts_dly_MASK | \
+      SC_DEBUG_2_end_of_prim_s1_dly_MASK | \
+      SC_DEBUG_2_pass_empty_prim_s1_MASK | \
+      SC_DEBUG_2_event_id_s1_MASK | \
+      SC_DEBUG_2_event_s1_MASK | \
+      SC_DEBUG_2_trigger_MASK)
+
+#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \
+     ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \
+      (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \
+      (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \
+      (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \
+      (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \
+      (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \
+      (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \
+      (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \
+      (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \
+      (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \
+      (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \
+      (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \
+      (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \
+      (trigger << SC_DEBUG_2_trigger_SHIFT))
+
+#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_GET_trigger(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT)
+
+#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int                                : 1;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int                                : 8;
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+     } sc_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+          unsigned int                                : 8;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int                                : 1;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+     } sc_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_2_t f;
+} sc_debug_2_u;
+
+
+/*
+ * SC_DEBUG_3 struct
+ */
+
+#define SC_DEBUG_3_x_curr_s1_SIZE      11
+#define SC_DEBUG_3_y_curr_s1_SIZE      11
+#define SC_DEBUG_3_trigger_SIZE        1
+
+#define SC_DEBUG_3_x_curr_s1_SHIFT     0
+#define SC_DEBUG_3_y_curr_s1_SHIFT     11
+#define SC_DEBUG_3_trigger_SHIFT       31
+
+#define SC_DEBUG_3_x_curr_s1_MASK      0x000007ff
+#define SC_DEBUG_3_y_curr_s1_MASK      0x003ff800
+#define SC_DEBUG_3_trigger_MASK        0x80000000
+
+#define SC_DEBUG_3_MASK \
+     (SC_DEBUG_3_x_curr_s1_MASK | \
+      SC_DEBUG_3_y_curr_s1_MASK | \
+      SC_DEBUG_3_trigger_MASK)
+
+#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \
+     ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \
+      (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \
+      (trigger << SC_DEBUG_3_trigger_SHIFT))
+
+#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_trigger(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT)
+
+#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int                                : 9;
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+     } sc_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+          unsigned int                                : 9;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+     } sc_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_3_t f;
+} sc_debug_3_u;
+
+
+/*
+ * SC_DEBUG_4 struct
+ */
+
+#define SC_DEBUG_4_y_end_s1_SIZE       14
+#define SC_DEBUG_4_y_start_s1_SIZE     14
+#define SC_DEBUG_4_y_dir_s1_SIZE       1
+#define SC_DEBUG_4_trigger_SIZE        1
+
+#define SC_DEBUG_4_y_end_s1_SHIFT      0
+#define SC_DEBUG_4_y_start_s1_SHIFT    14
+#define SC_DEBUG_4_y_dir_s1_SHIFT      28
+#define SC_DEBUG_4_trigger_SHIFT       31
+
+#define SC_DEBUG_4_y_end_s1_MASK       0x00003fff
+#define SC_DEBUG_4_y_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_4_y_dir_s1_MASK       0x10000000
+#define SC_DEBUG_4_trigger_MASK        0x80000000
+
+#define SC_DEBUG_4_MASK \
+     (SC_DEBUG_4_y_end_s1_MASK | \
+      SC_DEBUG_4_y_start_s1_MASK | \
+      SC_DEBUG_4_y_dir_s1_MASK | \
+      SC_DEBUG_4_trigger_MASK)
+
+#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \
+     ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \
+      (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \
+      (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_4_trigger_SHIFT))
+
+#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_GET_trigger(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT)
+
+#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+     } sc_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+     } sc_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_4_t f;
+} sc_debug_4_u;
+
+
+/*
+ * SC_DEBUG_5 struct
+ */
+
+#define SC_DEBUG_5_x_end_s1_SIZE       14
+#define SC_DEBUG_5_x_start_s1_SIZE     14
+#define SC_DEBUG_5_x_dir_s1_SIZE       1
+#define SC_DEBUG_5_trigger_SIZE        1
+
+#define SC_DEBUG_5_x_end_s1_SHIFT      0
+#define SC_DEBUG_5_x_start_s1_SHIFT    14
+#define SC_DEBUG_5_x_dir_s1_SHIFT      28
+#define SC_DEBUG_5_trigger_SHIFT       31
+
+#define SC_DEBUG_5_x_end_s1_MASK       0x00003fff
+#define SC_DEBUG_5_x_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_5_x_dir_s1_MASK       0x10000000
+#define SC_DEBUG_5_trigger_MASK        0x80000000
+
+#define SC_DEBUG_5_MASK \
+     (SC_DEBUG_5_x_end_s1_MASK | \
+      SC_DEBUG_5_x_start_s1_MASK | \
+      SC_DEBUG_5_x_dir_s1_MASK | \
+      SC_DEBUG_5_trigger_MASK)
+
+#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \
+     ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \
+      (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \
+      (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_5_trigger_SHIFT))
+
+#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_GET_trigger(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT)
+
+#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+     } sc_debug_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+     } sc_debug_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_5_t f;
+} sc_debug_5_u;
+
+
+/*
+ * SC_DEBUG_6 struct
+ */
+
+#define SC_DEBUG_6_z_ff_empty_SIZE     1
+#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1
+#define SC_DEBUG_6_xy_ff_empty_SIZE    1
+#define SC_DEBUG_6_event_flag_SIZE     1
+#define SC_DEBUG_6_z_mask_needed_SIZE  1
+#define SC_DEBUG_6_state_SIZE          3
+#define SC_DEBUG_6_state_delayed_SIZE  3
+#define SC_DEBUG_6_data_valid_SIZE     1
+#define SC_DEBUG_6_data_valid_d_SIZE   1
+#define SC_DEBUG_6_tilex_delayed_SIZE  9
+#define SC_DEBUG_6_tiley_delayed_SIZE  9
+#define SC_DEBUG_6_trigger_SIZE        1
+
+#define SC_DEBUG_6_z_ff_empty_SHIFT    0
+#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1
+#define SC_DEBUG_6_xy_ff_empty_SHIFT   2
+#define SC_DEBUG_6_event_flag_SHIFT    3
+#define SC_DEBUG_6_z_mask_needed_SHIFT 4
+#define SC_DEBUG_6_state_SHIFT         5
+#define SC_DEBUG_6_state_delayed_SHIFT 8
+#define SC_DEBUG_6_data_valid_SHIFT    11
+#define SC_DEBUG_6_data_valid_d_SHIFT  12
+#define SC_DEBUG_6_tilex_delayed_SHIFT 13
+#define SC_DEBUG_6_tiley_delayed_SHIFT 22
+#define SC_DEBUG_6_trigger_SHIFT       31
+
+#define SC_DEBUG_6_z_ff_empty_MASK     0x00000001
+#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002
+#define SC_DEBUG_6_xy_ff_empty_MASK    0x00000004
+#define SC_DEBUG_6_event_flag_MASK     0x00000008
+#define SC_DEBUG_6_z_mask_needed_MASK  0x00000010
+#define SC_DEBUG_6_state_MASK          0x000000e0
+#define SC_DEBUG_6_state_delayed_MASK  0x00000700
+#define SC_DEBUG_6_data_valid_MASK     0x00000800
+#define SC_DEBUG_6_data_valid_d_MASK   0x00001000
+#define SC_DEBUG_6_tilex_delayed_MASK  0x003fe000
+#define SC_DEBUG_6_tiley_delayed_MASK  0x7fc00000
+#define SC_DEBUG_6_trigger_MASK        0x80000000
+
+#define SC_DEBUG_6_MASK \
+     (SC_DEBUG_6_z_ff_empty_MASK | \
+      SC_DEBUG_6_qmcntl_ff_empty_MASK | \
+      SC_DEBUG_6_xy_ff_empty_MASK | \
+      SC_DEBUG_6_event_flag_MASK | \
+      SC_DEBUG_6_z_mask_needed_MASK | \
+      SC_DEBUG_6_state_MASK | \
+      SC_DEBUG_6_state_delayed_MASK | \
+      SC_DEBUG_6_data_valid_MASK | \
+      SC_DEBUG_6_data_valid_d_MASK | \
+      SC_DEBUG_6_tilex_delayed_MASK | \
+      SC_DEBUG_6_tiley_delayed_MASK | \
+      SC_DEBUG_6_trigger_MASK)
+
+#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \
+     ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \
+      (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \
+      (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \
+      (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \
+      (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \
+      (state << SC_DEBUG_6_state_SHIFT) | \
+      (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \
+      (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \
+      (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \
+      (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \
+      (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \
+      (trigger << SC_DEBUG_6_trigger_SHIFT))
+
+#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_GET_state(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_GET_trigger(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT)
+
+#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+     } sc_debug_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+     } sc_debug_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_6_t f;
+} sc_debug_6_u;
+
+
+/*
+ * SC_DEBUG_7 struct
+ */
+
+#define SC_DEBUG_7_event_flag_SIZE     1
+#define SC_DEBUG_7_deallocate_SIZE     3
+#define SC_DEBUG_7_fpos_SIZE           1
+#define SC_DEBUG_7_sr_prim_we_SIZE     1
+#define SC_DEBUG_7_last_tile_SIZE      1
+#define SC_DEBUG_7_tile_ff_we_SIZE     1
+#define SC_DEBUG_7_qs_data_valid_SIZE  1
+#define SC_DEBUG_7_qs_q0_y_SIZE        2
+#define SC_DEBUG_7_qs_q0_x_SIZE        2
+#define SC_DEBUG_7_qs_q0_valid_SIZE    1
+#define SC_DEBUG_7_prim_ff_we_SIZE     1
+#define SC_DEBUG_7_tile_ff_re_SIZE     1
+#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_7_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_7_new_prim_SIZE       1
+#define SC_DEBUG_7_load_new_tile_data_SIZE 1
+#define SC_DEBUG_7_state_SIZE          2
+#define SC_DEBUG_7_fifos_ready_SIZE    1
+#define SC_DEBUG_7_trigger_SIZE        1
+
+#define SC_DEBUG_7_event_flag_SHIFT    0
+#define SC_DEBUG_7_deallocate_SHIFT    1
+#define SC_DEBUG_7_fpos_SHIFT          4
+#define SC_DEBUG_7_sr_prim_we_SHIFT    5
+#define SC_DEBUG_7_last_tile_SHIFT     6
+#define SC_DEBUG_7_tile_ff_we_SHIFT    7
+#define SC_DEBUG_7_qs_data_valid_SHIFT 8
+#define SC_DEBUG_7_qs_q0_y_SHIFT       9
+#define SC_DEBUG_7_qs_q0_x_SHIFT       11
+#define SC_DEBUG_7_qs_q0_valid_SHIFT   13
+#define SC_DEBUG_7_prim_ff_we_SHIFT    14
+#define SC_DEBUG_7_tile_ff_re_SHIFT    15
+#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16
+#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17
+#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18
+#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19
+#define SC_DEBUG_7_new_prim_SHIFT      20
+#define SC_DEBUG_7_load_new_tile_data_SHIFT 21
+#define SC_DEBUG_7_state_SHIFT         22
+#define SC_DEBUG_7_fifos_ready_SHIFT   24
+#define SC_DEBUG_7_trigger_SHIFT       31
+
+#define SC_DEBUG_7_event_flag_MASK     0x00000001
+#define SC_DEBUG_7_deallocate_MASK     0x0000000e
+#define SC_DEBUG_7_fpos_MASK           0x00000010
+#define SC_DEBUG_7_sr_prim_we_MASK     0x00000020
+#define SC_DEBUG_7_last_tile_MASK      0x00000040
+#define SC_DEBUG_7_tile_ff_we_MASK     0x00000080
+#define SC_DEBUG_7_qs_data_valid_MASK  0x00000100
+#define SC_DEBUG_7_qs_q0_y_MASK        0x00000600
+#define SC_DEBUG_7_qs_q0_x_MASK        0x00001800
+#define SC_DEBUG_7_qs_q0_valid_MASK    0x00002000
+#define SC_DEBUG_7_prim_ff_we_MASK     0x00004000
+#define SC_DEBUG_7_tile_ff_re_MASK     0x00008000
+#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000
+#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000
+#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000
+#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000
+#define SC_DEBUG_7_new_prim_MASK       0x00100000
+#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000
+#define SC_DEBUG_7_state_MASK          0x00c00000
+#define SC_DEBUG_7_fifos_ready_MASK    0x01000000
+#define SC_DEBUG_7_trigger_MASK        0x80000000
+
+#define SC_DEBUG_7_MASK \
+     (SC_DEBUG_7_event_flag_MASK | \
+      SC_DEBUG_7_deallocate_MASK | \
+      SC_DEBUG_7_fpos_MASK | \
+      SC_DEBUG_7_sr_prim_we_MASK | \
+      SC_DEBUG_7_last_tile_MASK | \
+      SC_DEBUG_7_tile_ff_we_MASK | \
+      SC_DEBUG_7_qs_data_valid_MASK | \
+      SC_DEBUG_7_qs_q0_y_MASK | \
+      SC_DEBUG_7_qs_q0_x_MASK | \
+      SC_DEBUG_7_qs_q0_valid_MASK | \
+      SC_DEBUG_7_prim_ff_we_MASK | \
+      SC_DEBUG_7_tile_ff_re_MASK | \
+      SC_DEBUG_7_fw_prim_data_valid_MASK | \
+      SC_DEBUG_7_last_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_prim_MASK | \
+      SC_DEBUG_7_new_prim_MASK | \
+      SC_DEBUG_7_load_new_tile_data_MASK | \
+      SC_DEBUG_7_state_MASK | \
+      SC_DEBUG_7_fifos_ready_MASK | \
+      SC_DEBUG_7_trigger_MASK)
+
+#define SC_DEBUG_7(event_flag, deallocate, fpos, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \
+     ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \
+      (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \
+      (fpos << SC_DEBUG_7_fpos_SHIFT) | \
+      (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \
+      (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \
+      (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \
+      (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \
+      (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \
+      (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \
+      (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \
+      (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \
+      (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \
+      (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \
+      (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \
+      (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \
+      (state << SC_DEBUG_7_state_SHIFT) | \
+      (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \
+      (trigger << SC_DEBUG_7_trigger_SHIFT))
+
+#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_GET_fpos(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fpos_MASK) >> SC_DEBUG_7_fpos_SHIFT)
+#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_GET_state(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_GET_trigger(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT)
+
+#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_SET_fpos(sc_debug_7_reg, fpos) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fpos_MASK) | (fpos << SC_DEBUG_7_fpos_SHIFT)
+#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int fpos                           : SC_DEBUG_7_fpos_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int                                : 6;
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+     } sc_debug_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+          unsigned int                                : 6;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int fpos                           : SC_DEBUG_7_fpos_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+     } sc_debug_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_7_t f;
+} sc_debug_7_u;
+
+
+/*
+ * SC_DEBUG_8 struct
+ */
+
+#define SC_DEBUG_8_sample_last_SIZE    1
+#define SC_DEBUG_8_sample_mask_SIZE    4
+#define SC_DEBUG_8_sample_y_SIZE       2
+#define SC_DEBUG_8_sample_x_SIZE       2
+#define SC_DEBUG_8_sample_send_SIZE    1
+#define SC_DEBUG_8_next_cycle_SIZE     2
+#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1
+#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1
+#define SC_DEBUG_8_num_samples_SIZE    2
+#define SC_DEBUG_8_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_8_last_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_sample_we_SIZE      1
+#define SC_DEBUG_8_fpos_SIZE           1
+#define SC_DEBUG_8_event_id_SIZE       5
+#define SC_DEBUG_8_event_flag_SIZE     1
+#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_8_trigger_SIZE        1
+
+#define SC_DEBUG_8_sample_last_SHIFT   0
+#define SC_DEBUG_8_sample_mask_SHIFT   1
+#define SC_DEBUG_8_sample_y_SHIFT      5
+#define SC_DEBUG_8_sample_x_SHIFT      7
+#define SC_DEBUG_8_sample_send_SHIFT   9
+#define SC_DEBUG_8_next_cycle_SHIFT    10
+#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12
+#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13
+#define SC_DEBUG_8_num_samples_SHIFT   14
+#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16
+#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17
+#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18
+#define SC_DEBUG_8_sample_we_SHIFT     19
+#define SC_DEBUG_8_fpos_SHIFT          20
+#define SC_DEBUG_8_event_id_SHIFT      21
+#define SC_DEBUG_8_event_flag_SHIFT    26
+#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27
+#define SC_DEBUG_8_trigger_SHIFT       31
+
+#define SC_DEBUG_8_sample_last_MASK    0x00000001
+#define SC_DEBUG_8_sample_mask_MASK    0x0000001e
+#define SC_DEBUG_8_sample_y_MASK       0x00000060
+#define SC_DEBUG_8_sample_x_MASK       0x00000180
+#define SC_DEBUG_8_sample_send_MASK    0x00000200
+#define SC_DEBUG_8_next_cycle_MASK     0x00000c00
+#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000
+#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000
+#define SC_DEBUG_8_num_samples_MASK    0x0000c000
+#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000
+#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000
+#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000
+#define SC_DEBUG_8_sample_we_MASK      0x00080000
+#define SC_DEBUG_8_fpos_MASK           0x00100000
+#define SC_DEBUG_8_event_id_MASK       0x03e00000
+#define SC_DEBUG_8_event_flag_MASK     0x04000000
+#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000
+#define SC_DEBUG_8_trigger_MASK        0x80000000
+
+#define SC_DEBUG_8_MASK \
+     (SC_DEBUG_8_sample_last_MASK | \
+      SC_DEBUG_8_sample_mask_MASK | \
+      SC_DEBUG_8_sample_y_MASK | \
+      SC_DEBUG_8_sample_x_MASK | \
+      SC_DEBUG_8_sample_send_MASK | \
+      SC_DEBUG_8_next_cycle_MASK | \
+      SC_DEBUG_8_ez_sample_ff_full_MASK | \
+      SC_DEBUG_8_rb_sc_samp_rtr_MASK | \
+      SC_DEBUG_8_num_samples_MASK | \
+      SC_DEBUG_8_last_quad_of_tile_MASK | \
+      SC_DEBUG_8_last_quad_of_prim_MASK | \
+      SC_DEBUG_8_first_quad_of_prim_MASK | \
+      SC_DEBUG_8_sample_we_MASK | \
+      SC_DEBUG_8_fpos_MASK | \
+      SC_DEBUG_8_event_id_MASK | \
+      SC_DEBUG_8_event_flag_MASK | \
+      SC_DEBUG_8_fw_prim_data_valid_MASK | \
+      SC_DEBUG_8_trigger_MASK)
+
+#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fpos, event_id, event_flag, fw_prim_data_valid, trigger) \
+     ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \
+      (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \
+      (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \
+      (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \
+      (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \
+      (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \
+      (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \
+      (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \
+      (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \
+      (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \
+      (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \
+      (fpos << SC_DEBUG_8_fpos_SHIFT) | \
+      (event_id << SC_DEBUG_8_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \
+      (trigger << SC_DEBUG_8_trigger_SHIFT))
+
+#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_GET_fpos(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fpos_MASK) >> SC_DEBUG_8_fpos_SHIFT)
+#define SC_DEBUG_8_GET_event_id(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_GET_trigger(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT)
+
+#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_SET_fpos(sc_debug_8_reg, fpos) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fpos_MASK) | (fpos << SC_DEBUG_8_fpos_SHIFT)
+#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int fpos                           : SC_DEBUG_8_fpos_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int                                : 3;
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+     } sc_debug_8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int fpos                           : SC_DEBUG_8_fpos_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+     } sc_debug_8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_8_t f;
+} sc_debug_8_u;
+
+
+/*
+ * SC_DEBUG_9 struct
+ */
+
+#define SC_DEBUG_9_rb_sc_send_SIZE     1
+#define SC_DEBUG_9_rb_sc_ez_mask_SIZE  4
+#define SC_DEBUG_9_fifo_data_ready_SIZE 1
+#define SC_DEBUG_9_early_z_enable_SIZE 1
+#define SC_DEBUG_9_mask_state_SIZE     2
+#define SC_DEBUG_9_next_ez_mask_SIZE   16
+#define SC_DEBUG_9_mask_ready_SIZE     1
+#define SC_DEBUG_9_drop_sample_SIZE    1
+#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_9_trigger_SIZE        1
+
+#define SC_DEBUG_9_rb_sc_send_SHIFT    0
+#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1
+#define SC_DEBUG_9_fifo_data_ready_SHIFT 5
+#define SC_DEBUG_9_early_z_enable_SHIFT 6
+#define SC_DEBUG_9_mask_state_SHIFT    7
+#define SC_DEBUG_9_next_ez_mask_SHIFT  9
+#define SC_DEBUG_9_mask_ready_SHIFT    25
+#define SC_DEBUG_9_drop_sample_SHIFT   26
+#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30
+#define SC_DEBUG_9_trigger_SHIFT       31
+
+#define SC_DEBUG_9_rb_sc_send_MASK     0x00000001
+#define SC_DEBUG_9_rb_sc_ez_mask_MASK  0x0000001e
+#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020
+#define SC_DEBUG_9_early_z_enable_MASK 0x00000040
+#define SC_DEBUG_9_mask_state_MASK     0x00000180
+#define SC_DEBUG_9_next_ez_mask_MASK   0x01fffe00
+#define SC_DEBUG_9_mask_ready_MASK     0x02000000
+#define SC_DEBUG_9_drop_sample_MASK    0x04000000
+#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000
+#define SC_DEBUG_9_trigger_MASK        0x80000000
+
+#define SC_DEBUG_9_MASK \
+     (SC_DEBUG_9_rb_sc_send_MASK | \
+      SC_DEBUG_9_rb_sc_ez_mask_MASK | \
+      SC_DEBUG_9_fifo_data_ready_MASK | \
+      SC_DEBUG_9_early_z_enable_MASK | \
+      SC_DEBUG_9_mask_state_MASK | \
+      SC_DEBUG_9_next_ez_mask_MASK | \
+      SC_DEBUG_9_mask_ready_MASK | \
+      SC_DEBUG_9_drop_sample_MASK | \
+      SC_DEBUG_9_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_9_trigger_MASK)
+
+#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \
+     ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \
+      (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \
+      (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \
+      (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \
+      (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \
+      (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \
+      (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \
+      (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \
+      (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \
+      (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \
+      (trigger << SC_DEBUG_9_trigger_SHIFT))
+
+#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_GET_trigger(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT)
+
+#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+     } sc_debug_9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+     } sc_debug_9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_9_t f;
+} sc_debug_9_u;
+
+
+/*
+ * SC_DEBUG_10 struct
+ */
+
+#define SC_DEBUG_10_combined_sample_mask_SIZE 16
+#define SC_DEBUG_10_trigger_SIZE       1
+
+#define SC_DEBUG_10_combined_sample_mask_SHIFT 0
+#define SC_DEBUG_10_trigger_SHIFT      31
+
+#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff
+#define SC_DEBUG_10_trigger_MASK       0x80000000
+
+#define SC_DEBUG_10_MASK \
+     (SC_DEBUG_10_combined_sample_mask_MASK | \
+      SC_DEBUG_10_trigger_MASK)
+
+#define SC_DEBUG_10(combined_sample_mask, trigger) \
+     ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \
+      (trigger << SC_DEBUG_10_trigger_SHIFT))
+
+#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_GET_trigger(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT)
+
+#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+          unsigned int                                : 15;
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+     } sc_debug_10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+          unsigned int                                : 15;
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+     } sc_debug_10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_10_t f;
+} sc_debug_10_u;
+
+
+/*
+ * SC_DEBUG_11 struct
+ */
+
+#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_11_iterator_input_fz_SIZE 1
+#define SC_DEBUG_11_packer_send_quads_SIZE 1
+#define SC_DEBUG_11_packer_send_cmd_SIZE 1
+#define SC_DEBUG_11_packer_send_event_SIZE 1
+#define SC_DEBUG_11_next_state_SIZE    3
+#define SC_DEBUG_11_state_SIZE         3
+#define SC_DEBUG_11_stall_SIZE         1
+#define SC_DEBUG_11_trigger_SIZE       1
+
+#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1
+#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3
+#define SC_DEBUG_11_iterator_input_fz_SHIFT 4
+#define SC_DEBUG_11_packer_send_quads_SHIFT 5
+#define SC_DEBUG_11_packer_send_cmd_SHIFT 6
+#define SC_DEBUG_11_packer_send_event_SHIFT 7
+#define SC_DEBUG_11_next_state_SHIFT   8
+#define SC_DEBUG_11_state_SHIFT        11
+#define SC_DEBUG_11_stall_SHIFT        14
+#define SC_DEBUG_11_trigger_SHIFT      31
+
+#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002
+#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008
+#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010
+#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020
+#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040
+#define SC_DEBUG_11_packer_send_event_MASK 0x00000080
+#define SC_DEBUG_11_next_state_MASK    0x00000700
+#define SC_DEBUG_11_state_MASK         0x00003800
+#define SC_DEBUG_11_stall_MASK         0x00004000
+#define SC_DEBUG_11_trigger_MASK       0x80000000
+
+#define SC_DEBUG_11_MASK \
+     (SC_DEBUG_11_ez_sample_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_11_ez_prim_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_11_iterator_input_fz_MASK | \
+      SC_DEBUG_11_packer_send_quads_MASK | \
+      SC_DEBUG_11_packer_send_cmd_MASK | \
+      SC_DEBUG_11_packer_send_event_MASK | \
+      SC_DEBUG_11_next_state_MASK | \
+      SC_DEBUG_11_state_MASK | \
+      SC_DEBUG_11_stall_MASK | \
+      SC_DEBUG_11_trigger_MASK)
+
+#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \
+     ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \
+      (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \
+      (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \
+      (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \
+      (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \
+      (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \
+      (next_state << SC_DEBUG_11_next_state_SHIFT) | \
+      (state << SC_DEBUG_11_state_SHIFT) | \
+      (stall << SC_DEBUG_11_stall_SHIFT) | \
+      (trigger << SC_DEBUG_11_trigger_SHIFT))
+
+#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_GET_next_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_GET_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_GET_stall(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_GET_trigger(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT)
+
+#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int                                : 16;
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+     } sc_debug_11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+          unsigned int                                : 16;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+     } sc_debug_11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_11_t f;
+} sc_debug_11_u;
+
+
+/*
+ * SC_DEBUG_12 struct
+ */
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1
+#define SC_DEBUG_12_event_id_SIZE      5
+#define SC_DEBUG_12_event_flag_SIZE    1
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_full_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1
+#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1
+#define SC_DEBUG_12_iter_qdhit0_SIZE   1
+#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1
+#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1
+#define SC_DEBUG_12_iter_phase_out_SIZE 2
+#define SC_DEBUG_12_iter_phase_reg_SIZE 2
+#define SC_DEBUG_12_iterator_SP_valid_SIZE 1
+#define SC_DEBUG_12_eopv_reg_SIZE      1
+#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1
+#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1
+#define SC_DEBUG_12_trigger_SIZE       1
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0
+#define SC_DEBUG_12_event_id_SHIFT     1
+#define SC_DEBUG_12_event_flag_SHIFT   6
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7
+#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8
+#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9
+#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11
+#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12
+#define SC_DEBUG_12_iter_qdhit0_SHIFT  13
+#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14
+#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15
+#define SC_DEBUG_12_iter_phase_out_SHIFT 16
+#define SC_DEBUG_12_iter_phase_reg_SHIFT 18
+#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20
+#define SC_DEBUG_12_eopv_reg_SHIFT     21
+#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22
+#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23
+#define SC_DEBUG_12_trigger_SHIFT      31
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001
+#define SC_DEBUG_12_event_id_MASK      0x0000003e
+#define SC_DEBUG_12_event_flag_MASK    0x00000040
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080
+#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100
+#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200
+#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400
+#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800
+#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000
+#define SC_DEBUG_12_iter_qdhit0_MASK   0x00002000
+#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000
+#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000
+#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000
+#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000
+#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000
+#define SC_DEBUG_12_eopv_reg_MASK      0x00200000
+#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000
+#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000
+#define SC_DEBUG_12_trigger_MASK       0x80000000
+
+#define SC_DEBUG_12_MASK \
+     (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \
+      SC_DEBUG_12_event_id_MASK | \
+      SC_DEBUG_12_event_flag_MASK | \
+      SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \
+      SC_DEBUG_12_itercmdfifo_full_MASK | \
+      SC_DEBUG_12_itercmdfifo_empty_MASK | \
+      SC_DEBUG_12_iter_ds_one_clk_command_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_vector_MASK | \
+      SC_DEBUG_12_iter_qdhit0_MASK | \
+      SC_DEBUG_12_bc_use_centers_reg_MASK | \
+      SC_DEBUG_12_bc_output_xy_reg_MASK | \
+      SC_DEBUG_12_iter_phase_out_MASK | \
+      SC_DEBUG_12_iter_phase_reg_MASK | \
+      SC_DEBUG_12_iterator_SP_valid_MASK | \
+      SC_DEBUG_12_eopv_reg_MASK | \
+      SC_DEBUG_12_one_clk_cmd_reg_MASK | \
+      SC_DEBUG_12_iter_dx_end_of_prim_MASK | \
+      SC_DEBUG_12_trigger_MASK)
+
+#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \
+     ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \
+      (event_id << SC_DEBUG_12_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \
+      (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \
+      (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \
+      (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \
+      (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \
+      (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \
+      (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \
+      (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \
+      (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \
+      (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \
+      (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \
+      (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \
+      (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \
+      (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \
+      (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \
+      (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \
+      (trigger << SC_DEBUG_12_trigger_SHIFT))
+
+#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_GET_event_id(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_GET_trigger(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT)
+
+#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int                                : 7;
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+     } sc_debug_12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+          unsigned int                                : 7;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+     } sc_debug_12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_12_t f;
+} sc_debug_12_u;
+
+
+#endif
+
+
+#if !defined (_VGT_FIDDLE_H)
+#define _VGT_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+#define VGT_OUT_POINT                  0x00000000
+#define VGT_OUT_LINE                   0x00000001
+#define VGT_OUT_TRI                    0x00000002
+#define VGT_OUT_RECT_V0                0x00000003
+#define VGT_OUT_RECT_V1                0x00000004
+#define VGT_OUT_RECT_V2                0x00000005
+#define VGT_OUT_RECT_V3                0x00000006
+#define VGT_OUT_RESERVED               0x00000007
+#define VGT_TE_QUAD                    0x00000008
+#define VGT_TE_PRIM_INDEX_LINE         0x00000009
+#define VGT_TE_PRIM_INDEX_TRI          0x0000000a
+#define VGT_TE_PRIM_INDEX_QUAD         0x0000000b
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * GFX_COPY_STATE struct
+ */
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0
+
+#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+
+#define GFX_COPY_STATE_MASK \
+     (GFX_COPY_STATE_SRC_STATE_ID_MASK)
+
+#define GFX_COPY_STATE(src_state_id) \
+     ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT))
+
+#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \
+     ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \
+     gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 31;
+     } gfx_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int                                : 31;
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+     } gfx_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gfx_copy_state_t f;
+} gfx_copy_state_u;
+
+
+/*
+ * VGT_DRAW_INITIATOR struct
+ */
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1
+#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11
+#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800
+#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000
+#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000
+
+#define VGT_DRAW_INITIATOR_MASK \
+     (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \
+      VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \
+      VGT_DRAW_INITIATOR_NOT_EOP_MASK | \
+      VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \
+      VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_NUM_INDICES_MASK)
+
+#define VGT_DRAW_INITIATOR(prim_type, source_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \
+     ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \
+      (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \
+      (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \
+      (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \
+      (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \
+      (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \
+      (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \
+      (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT))
+
+#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int                                : 3;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+     } vgt_draw_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+     } vgt_draw_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_draw_initiator_t f;
+} vgt_draw_initiator_u;
+
+
+/*
+ * VGT_EVENT_INITIATOR struct
+ */
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f
+
+#define VGT_EVENT_INITIATOR_MASK \
+     (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK)
+
+#define VGT_EVENT_INITIATOR(event_type) \
+     ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT))
+
+#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \
+     ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \
+     vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+          unsigned int                                : 26;
+     } vgt_event_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int                                : 26;
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+     } vgt_event_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_event_initiator_t f;
+} vgt_event_initiator_u;
+
+
+/*
+ * VGT_DMA_BASE struct
+ */
+
+#define VGT_DMA_BASE_BASE_ADDR_SIZE    32
+
+#define VGT_DMA_BASE_BASE_ADDR_SHIFT   0
+
+#define VGT_DMA_BASE_BASE_ADDR_MASK    0xffffffff
+
+#define VGT_DMA_BASE_MASK \
+     (VGT_DMA_BASE_BASE_ADDR_MASK)
+
+#define VGT_DMA_BASE(base_addr) \
+     ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT))
+
+#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \
+     ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \
+     vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_base_t f;
+} vgt_dma_base_u;
+
+
+/*
+ * VGT_DMA_SIZE struct
+ */
+
+#define VGT_DMA_SIZE_NUM_WORDS_SIZE    24
+#define VGT_DMA_SIZE_SWAP_MODE_SIZE    2
+
+#define VGT_DMA_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_DMA_SIZE_SWAP_MODE_SHIFT   30
+
+#define VGT_DMA_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_DMA_SIZE_SWAP_MODE_MASK    0xc0000000
+
+#define VGT_DMA_SIZE_MASK \
+     (VGT_DMA_SIZE_NUM_WORDS_MASK | \
+      VGT_DMA_SIZE_SWAP_MODE_MASK)
+
+#define VGT_DMA_SIZE(num_words, swap_mode) \
+     ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \
+      (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT))
+
+#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+     } vgt_dma_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+     } vgt_dma_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_size_t f;
+} vgt_dma_size_u;
+
+
+/*
+ * VGT_BIN_BASE struct
+ */
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff
+
+#define VGT_BIN_BASE_MASK \
+     (VGT_BIN_BASE_BIN_BASE_ADDR_MASK)
+
+#define VGT_BIN_BASE(bin_base_addr) \
+     ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT))
+
+#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \
+     ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \
+     vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_base_t f;
+} vgt_bin_base_u;
+
+
+/*
+ * VGT_BIN_SIZE struct
+ */
+
+#define VGT_BIN_SIZE_NUM_WORDS_SIZE    24
+
+#define VGT_BIN_SIZE_NUM_WORDS_SHIFT   0
+
+#define VGT_BIN_SIZE_NUM_WORDS_MASK    0x00ffffff
+
+#define VGT_BIN_SIZE_MASK \
+     (VGT_BIN_SIZE_NUM_WORDS_MASK)
+
+#define VGT_BIN_SIZE(num_words) \
+     ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT))
+
+#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+
+#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 8;
+     } vgt_bin_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int                                : 8;
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+     } vgt_bin_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_size_t f;
+} vgt_bin_size_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MIN struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MIN_MASK \
+     (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_min_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+     } vgt_current_bin_id_min_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_min_t f;
+} vgt_current_bin_id_min_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MAX struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MAX_MASK \
+     (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_max_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+     } vgt_current_bin_id_max_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_max_t f;
+} vgt_current_bin_id_max_u;
+
+
+/*
+ * VGT_IMMED_DATA struct
+ */
+
+#define VGT_IMMED_DATA_DATA_SIZE       32
+
+#define VGT_IMMED_DATA_DATA_SHIFT      0
+
+#define VGT_IMMED_DATA_DATA_MASK       0xffffffff
+
+#define VGT_IMMED_DATA_MASK \
+     (VGT_IMMED_DATA_DATA_MASK)
+
+#define VGT_IMMED_DATA(data) \
+     ((data << VGT_IMMED_DATA_DATA_SHIFT))
+
+#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \
+     ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT)
+
+#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \
+     vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_immed_data_t f;
+} vgt_immed_data_u;
+
+
+/*
+ * VGT_MAX_VTX_INDX struct
+ */
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff
+
+#define VGT_MAX_VTX_INDX_MASK \
+     (VGT_MAX_VTX_INDX_MAX_INDX_MASK)
+
+#define VGT_MAX_VTX_INDX(max_indx) \
+     ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT))
+
+#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \
+     ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \
+     vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_max_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+     } vgt_max_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_max_vtx_indx_t f;
+} vgt_max_vtx_indx_u;
+
+
+/*
+ * VGT_MIN_VTX_INDX struct
+ */
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff
+
+#define VGT_MIN_VTX_INDX_MASK \
+     (VGT_MIN_VTX_INDX_MIN_INDX_MASK)
+
+#define VGT_MIN_VTX_INDX(min_indx) \
+     ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT))
+
+#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \
+     ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \
+     vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_min_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+     } vgt_min_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_min_vtx_indx_t f;
+} vgt_min_vtx_indx_u;
+
+
+/*
+ * VGT_INDX_OFFSET struct
+ */
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff
+
+#define VGT_INDX_OFFSET_MASK \
+     (VGT_INDX_OFFSET_INDX_OFFSET_MASK)
+
+#define VGT_INDX_OFFSET(indx_offset) \
+     ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT))
+
+#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \
+     ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \
+     vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+          unsigned int                                : 8;
+     } vgt_indx_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int                                : 8;
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+     } vgt_indx_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_indx_offset_t f;
+} vgt_indx_offset_u;
+
+
+/*
+ * VGT_VERTEX_REUSE_BLOCK_CNTL struct
+ */
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \
+     (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \
+     ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT))
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \
+     ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \
+     vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+          unsigned int                                : 29;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int                                : 29;
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vertex_reuse_block_cntl_t f;
+} vgt_vertex_reuse_block_cntl_u;
+
+
+/*
+ * VGT_OUT_DEALLOC_CNTL struct
+ */
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003
+
+#define VGT_OUT_DEALLOC_CNTL_MASK \
+     (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK)
+
+#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \
+     ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT))
+
+#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \
+     ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \
+     vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+          unsigned int                                : 30;
+     } vgt_out_dealloc_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int                                : 30;
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+     } vgt_out_dealloc_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_out_dealloc_cntl_t f;
+} vgt_out_dealloc_cntl_u;
+
+
+/*
+ * VGT_MULTI_PRIM_IB_RESET_INDX struct
+ */
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \
+     (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \
+     ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT))
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \
+     ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \
+     vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int                                : 8;
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_multi_prim_ib_reset_indx_t f;
+} vgt_multi_prim_ib_reset_indx_u;
+
+
+/*
+ * VGT_ENHANCE struct
+ */
+
+#define VGT_ENHANCE_MISC_SIZE          16
+
+#define VGT_ENHANCE_MISC_SHIFT         0
+
+#define VGT_ENHANCE_MISC_MASK          0x0000ffff
+
+#define VGT_ENHANCE_MASK \
+     (VGT_ENHANCE_MISC_MASK)
+
+#define VGT_ENHANCE(misc) \
+     ((misc << VGT_ENHANCE_MISC_SHIFT))
+
+#define VGT_ENHANCE_GET_MISC(vgt_enhance) \
+     ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT)
+
+#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \
+     vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+          unsigned int                                : 16;
+     } vgt_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int                                : 16;
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+     } vgt_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_enhance_t f;
+} vgt_enhance_u;
+
+
+/*
+ * VGT_VTX_VECT_EJECT_REG struct
+ */
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f
+
+#define VGT_VTX_VECT_EJECT_REG_MASK \
+     (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK)
+
+#define VGT_VTX_VECT_EJECT_REG(prim_count) \
+     ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT))
+
+#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \
+     ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \
+     vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+          unsigned int                                : 27;
+     } vgt_vtx_vect_eject_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int                                : 27;
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+     } vgt_vtx_vect_eject_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vtx_vect_eject_reg_t f;
+} vgt_vtx_vect_eject_reg_u;
+
+
+/*
+ * VGT_LAST_COPY_STATE struct
+ */
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000
+
+#define VGT_LAST_COPY_STATE_MASK \
+     (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \
+      VGT_LAST_COPY_STATE_DST_STATE_ID_MASK)
+
+#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \
+     ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \
+      (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT))
+
+#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+     } vgt_last_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+     } vgt_last_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_last_copy_state_t f;
+} vgt_last_copy_state_u;
+
+
+/*
+ * VGT_DEBUG_CNTL struct
+ */
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f
+
+#define VGT_DEBUG_CNTL_MASK \
+     (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK)
+
+#define VGT_DEBUG_CNTL(vgt_debug_indx) \
+     ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT))
+
+#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \
+     ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \
+     vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } vgt_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+     } vgt_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_cntl_t f;
+} vgt_debug_cntl_u;
+
+
+/*
+ * VGT_DEBUG_DATA struct
+ */
+
+#define VGT_DEBUG_DATA_DATA_SIZE       32
+
+#define VGT_DEBUG_DATA_DATA_SHIFT      0
+
+#define VGT_DEBUG_DATA_DATA_MASK       0xffffffff
+
+#define VGT_DEBUG_DATA_MASK \
+     (VGT_DEBUG_DATA_DATA_MASK)
+
+#define VGT_DEBUG_DATA(data) \
+     ((data << VGT_DEBUG_DATA_DATA_SHIFT))
+
+#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \
+     ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT)
+
+#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \
+     vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_data_t f;
+} vgt_debug_data_u;
+
+
+/*
+ * VGT_CNTL_STATUS struct
+ */
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SIZE  1
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8
+
+#define VGT_CNTL_STATUS_VGT_BUSY_MASK  0x00000001
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100
+
+#define VGT_CNTL_STATUS_MASK \
+     (VGT_CNTL_STATUS_VGT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK)
+
+#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \
+     ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \
+      (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \
+      (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \
+      (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \
+      (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \
+      (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \
+      (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \
+      (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \
+      (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT))
+
+#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int                                : 23;
+     } vgt_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int                                : 23;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+     } vgt_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_cntl_status_t f;
+} vgt_cntl_status_u;
+
+
+/*
+ * VGT_DEBUG_REG0 struct
+ */
+
+#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_out_busy_SIZE   1
+#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1
+#define VGT_DEBUG_REG0_grp_busy_SIZE   1
+#define VGT_DEBUG_REG0_dma_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_rbiu_busy_SIZE  1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1
+
+#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0
+#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2
+#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3
+#define VGT_DEBUG_REG0_out_busy_SHIFT  4
+#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5
+#define VGT_DEBUG_REG0_grp_busy_SHIFT  6
+#define VGT_DEBUG_REG0_dma_busy_SHIFT  7
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8
+#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11
+#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12
+#define VGT_DEBUG_REG0_vgt_busy_SHIFT  13
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16
+
+#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001
+#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002
+#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004
+#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008
+#define VGT_DEBUG_REG0_out_busy_MASK   0x00000010
+#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020
+#define VGT_DEBUG_REG0_grp_busy_MASK   0x00000040
+#define VGT_DEBUG_REG0_dma_busy_MASK   0x00000080
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100
+#define VGT_DEBUG_REG0_rbiu_busy_MASK  0x00000200
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800
+#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000
+#define VGT_DEBUG_REG0_vgt_busy_MASK   0x00002000
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000
+
+#define VGT_DEBUG_REG0_MASK \
+     (VGT_DEBUG_REG0_te_grp_busy_MASK | \
+      VGT_DEBUG_REG0_pt_grp_busy_MASK | \
+      VGT_DEBUG_REG0_vr_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_out_busy_MASK | \
+      VGT_DEBUG_REG0_grp_backend_busy_MASK | \
+      VGT_DEBUG_REG0_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_MASK | \
+      VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_busy_MASK)
+
+#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \
+     ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \
+      (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \
+      (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \
+      (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \
+      (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \
+      (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \
+      (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \
+      (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \
+      (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \
+      (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \
+      (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \
+      (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \
+      (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \
+      (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \
+      (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \
+      (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \
+      (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT))
+
+#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int                                : 15;
+     } vgt_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int                                : 15;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+     } vgt_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg0_t f;
+} vgt_debug_reg0_u;
+
+
+/*
+ * VGT_DEBUG_REG1 struct
+ */
+
+#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1
+#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_te_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1
+#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1
+#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1
+#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1
+
+#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0
+#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3
+#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5
+#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7
+#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9
+#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10
+#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11
+#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12
+#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13
+#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14
+#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15
+#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16
+#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20
+#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28
+#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30
+
+#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001
+#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002
+#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004
+#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008
+#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010
+#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020
+#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040
+#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080
+#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100
+#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200
+#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400
+#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800
+#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000
+#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000
+#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000
+#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000
+#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000
+#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000
+#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000
+#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000
+
+#define VGT_DEBUG_REG1_MASK \
+     (VGT_DEBUG_REG1_out_te_data_read_MASK | \
+      VGT_DEBUG_REG1_te_out_data_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_prim_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_data_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_prim_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_indx_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_te_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_te_valid_MASK | \
+      VGT_DEBUG_REG1_pt_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_pt_valid_MASK | \
+      VGT_DEBUG_REG1_vr_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_vr_valid_MASK | \
+      VGT_DEBUG_REG1_grp_dma_read_MASK | \
+      VGT_DEBUG_REG1_dma_grp_valid_MASK | \
+      VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \
+      VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \
+      VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_MH_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \
+      VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_SQ_send_MASK | \
+      VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK)
+
+#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \
+     ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \
+      (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \
+      (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \
+      (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \
+      (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \
+      (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \
+      (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \
+      (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \
+      (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \
+      (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \
+      (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \
+      (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \
+      (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \
+      (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \
+      (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \
+      (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \
+      (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \
+      (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \
+      (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \
+      (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \
+      (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \
+      (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \
+      (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \
+      (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \
+      (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \
+      (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \
+      (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \
+      (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \
+      (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \
+      (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \
+      (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT))
+
+#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int                                : 1;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+     } vgt_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg1_t f;
+} vgt_debug_reg1_u;
+
+
+/*
+ * VGT_DEBUG_REG3 struct
+ */
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002
+
+#define VGT_DEBUG_REG3_MASK \
+     (VGT_DEBUG_REG3_vgt_clk_en_MASK | \
+      VGT_DEBUG_REG3_reg_fifos_clk_en_MASK)
+
+#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \
+     ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \
+      (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT))
+
+#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int                                : 30;
+     } vgt_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int                                : 30;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+     } vgt_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg3_t f;
+} vgt_debug_reg3_u;
+
+
+/*
+ * VGT_DEBUG_REG6 struct
+ */
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG6_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_extract_vector_SIZE 1
+#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG6_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG6_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG6_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG6_MASK \
+     (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG6_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG6_input_data_valid_MASK | \
+      VGT_DEBUG_REG6_input_data_xfer_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG6_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG6_shifter_first_load_MASK | \
+      VGT_DEBUG_REG6_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG6_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG6_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG6_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG6_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG6_extract_vector_MASK | \
+      VGT_DEBUG_REG6_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG6_destination_rtr_MASK | \
+      VGT_DEBUG_REG6_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int                                : 3;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg6_t f;
+} vgt_debug_reg6_u;
+
+
+/*
+ * VGT_DEBUG_REG7 struct
+ */
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG7_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG7_MASK \
+     (VGT_DEBUG_REG7_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG7_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG7_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG7_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+     } vgt_debug_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+     } vgt_debug_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg7_t f;
+} vgt_debug_reg7_u;
+
+
+/*
+ * VGT_DEBUG_REG8 struct
+ */
+
+#define VGT_DEBUG_REG8_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG8_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG8_MASK \
+     (VGT_DEBUG_REG8_current_source_sel_MASK | \
+      VGT_DEBUG_REG8_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG8_input_data_cnt_MASK | \
+      VGT_DEBUG_REG8_input_data_lsw_MASK | \
+      VGT_DEBUG_REG8_input_data_msw_MASK | \
+      VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+     } vgt_debug_reg8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg8_t f;
+} vgt_debug_reg8_u;
+
+
+/*
+ * VGT_DEBUG_REG9 struct
+ */
+
+#define VGT_DEBUG_REG9_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG9_MASK \
+     (VGT_DEBUG_REG9_next_stride_q_MASK | \
+      VGT_DEBUG_REG9_next_stride_d_MASK | \
+      VGT_DEBUG_REG9_current_shift_q_MASK | \
+      VGT_DEBUG_REG9_current_shift_d_MASK | \
+      VGT_DEBUG_REG9_current_stride_q_MASK | \
+      VGT_DEBUG_REG9_current_stride_d_MASK | \
+      VGT_DEBUG_REG9_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int                                : 1;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+     } vgt_debug_reg9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg9_t f;
+} vgt_debug_reg9_u;
+
+
+/*
+ * VGT_DEBUG_REG10 struct
+ */
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG10_bin_valid_SIZE 1
+#define VGT_DEBUG_REG10_read_block_SIZE 1
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1
+#define VGT_DEBUG_REG10_selected_data_SIZE 8
+#define VGT_DEBUG_REG10_mask_input_data_SIZE 8
+#define VGT_DEBUG_REG10_gap_q_SIZE     1
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1
+#define VGT_DEBUG_REG10_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3
+#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4
+#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5
+#define VGT_DEBUG_REG10_bin_valid_SHIFT 6
+#define VGT_DEBUG_REG10_read_block_SHIFT 7
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8
+#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10
+#define VGT_DEBUG_REG10_selected_data_SHIFT 11
+#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19
+#define VGT_DEBUG_REG10_gap_q_SHIFT    27
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30
+#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008
+#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010
+#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020
+#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040
+#define VGT_DEBUG_REG10_read_block_MASK 0x00000080
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100
+#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200
+#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400
+#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800
+#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000
+#define VGT_DEBUG_REG10_gap_q_MASK     0x08000000
+#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000
+#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000
+#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000
+#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG10_MASK \
+     (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG10_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG10_bin_valid_MASK | \
+      VGT_DEBUG_REG10_read_block_MASK | \
+      VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \
+      VGT_DEBUG_REG10_last_bit_enable_q_MASK | \
+      VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \
+      VGT_DEBUG_REG10_selected_data_MASK | \
+      VGT_DEBUG_REG10_mask_input_data_MASK | \
+      VGT_DEBUG_REG10_gap_q_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \
+      VGT_DEBUG_REG10_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \
+     ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \
+      (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \
+      (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \
+      (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \
+      (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \
+      (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \
+      (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \
+      (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \
+      (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \
+      (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \
+      (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \
+      (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \
+      (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \
+      (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \
+      (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+     } vgt_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+     } vgt_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg10_t f;
+} vgt_debug_reg10_u;
+
+
+/*
+ * VGT_DEBUG_REG12 struct
+ */
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG12_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_extract_vector_SIZE 1
+#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG12_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG12_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG12_MASK \
+     (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG12_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG12_input_data_valid_MASK | \
+      VGT_DEBUG_REG12_input_data_xfer_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG12_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG12_shifter_first_load_MASK | \
+      VGT_DEBUG_REG12_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG12_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG12_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG12_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG12_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG12_extract_vector_MASK | \
+      VGT_DEBUG_REG12_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG12_destination_rtr_MASK | \
+      VGT_DEBUG_REG12_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int                                : 3;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg12_t f;
+} vgt_debug_reg12_u;
+
+
+/*
+ * VGT_DEBUG_REG13 struct
+ */
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG13_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG13_MASK \
+     (VGT_DEBUG_REG13_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG13_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG13_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG13_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+     } vgt_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+     } vgt_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg13_t f;
+} vgt_debug_reg13_u;
+
+
+/*
+ * VGT_DEBUG_REG14 struct
+ */
+
+#define VGT_DEBUG_REG14_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG14_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG14_MASK \
+     (VGT_DEBUG_REG14_current_source_sel_MASK | \
+      VGT_DEBUG_REG14_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG14_input_data_cnt_MASK | \
+      VGT_DEBUG_REG14_input_data_lsw_MASK | \
+      VGT_DEBUG_REG14_input_data_msw_MASK | \
+      VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+     } vgt_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg14_t f;
+} vgt_debug_reg14_u;
+
+
+/*
+ * VGT_DEBUG_REG15 struct
+ */
+
+#define VGT_DEBUG_REG15_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG15_MASK \
+     (VGT_DEBUG_REG15_next_stride_q_MASK | \
+      VGT_DEBUG_REG15_next_stride_d_MASK | \
+      VGT_DEBUG_REG15_current_shift_q_MASK | \
+      VGT_DEBUG_REG15_current_shift_d_MASK | \
+      VGT_DEBUG_REG15_current_stride_q_MASK | \
+      VGT_DEBUG_REG15_current_stride_d_MASK | \
+      VGT_DEBUG_REG15_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int                                : 1;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+     } vgt_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg15_t f;
+} vgt_debug_reg15_u;
+
+
+/*
+ * VGT_DEBUG_REG16 struct
+ */
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1
+#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1
+#define VGT_DEBUG_REG16_current_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_en_SIZE 1
+#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1
+#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9
+#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10
+#define VGT_DEBUG_REG16_current_state_q_SHIFT 11
+#define VGT_DEBUG_REG16_old_state_q_SHIFT 12
+#define VGT_DEBUG_REG16_old_state_en_SHIFT 13
+#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15
+#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17
+#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30
+#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200
+#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400
+#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800
+#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000
+#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000
+#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000
+#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000
+#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000
+#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000
+#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000
+#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG16_MASK \
+     (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \
+      VGT_DEBUG_REG16_rst_last_bit_MASK | \
+      VGT_DEBUG_REG16_current_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_en_MASK | \
+      VGT_DEBUG_REG16_prev_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_last_bit_block_q_MASK | \
+      VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \
+      VGT_DEBUG_REG16_load_empty_reg_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \
+      VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \
+     ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \
+      (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \
+      (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \
+      (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \
+      (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \
+      (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \
+      (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \
+      (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \
+      (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \
+      (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \
+      (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \
+      (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \
+      (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \
+      (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \
+      (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \
+      (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \
+      (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \
+      (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \
+      (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \
+      (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \
+      (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+     } vgt_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+     } vgt_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg16_t f;
+} vgt_debug_reg16_u;
+
+
+/*
+ * VGT_DEBUG_REG17 struct
+ */
+
+#define VGT_DEBUG_REG17_save_read_q_SIZE 1
+#define VGT_DEBUG_REG17_extend_read_q_SIZE 1
+#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2
+#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1
+#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1
+#define VGT_DEBUG_REG17_check_second_reg_SIZE 1
+#define VGT_DEBUG_REG17_check_first_reg_SIZE 1
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1
+#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG17_save_read_q_SHIFT 0
+#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1
+#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2
+#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4
+#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5
+#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6
+#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7
+#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8
+#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14
+#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15
+#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24
+#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001
+#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002
+#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c
+#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010
+#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020
+#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040
+#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080
+#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100
+#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000
+#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000
+#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000
+#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000
+#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000
+#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG17_MASK \
+     (VGT_DEBUG_REG17_save_read_q_MASK | \
+      VGT_DEBUG_REG17_extend_read_q_MASK | \
+      VGT_DEBUG_REG17_grp_indx_size_MASK | \
+      VGT_DEBUG_REG17_cull_prim_true_MASK | \
+      VGT_DEBUG_REG17_reset_bit2_q_MASK | \
+      VGT_DEBUG_REG17_reset_bit1_q_MASK | \
+      VGT_DEBUG_REG17_first_reg_first_q_MASK | \
+      VGT_DEBUG_REG17_check_second_reg_MASK | \
+      VGT_DEBUG_REG17_check_first_reg_MASK | \
+      VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \
+      VGT_DEBUG_REG17_to_second_reg_q_MASK | \
+      VGT_DEBUG_REG17_roll_over_msk_q_MASK | \
+      VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \
+     ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \
+      (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \
+      (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \
+      (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \
+      (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \
+      (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \
+      (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \
+      (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \
+      (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \
+      (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \
+      (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \
+      (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \
+      (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \
+      (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \
+      (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \
+      (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \
+      (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \
+      (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+     } vgt_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+     } vgt_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg17_t f;
+} vgt_debug_reg17_u;
+
+
+/*
+ * VGT_DEBUG_REG18 struct
+ */
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_start_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1
+#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13
+#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15
+#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16
+#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17
+#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20
+#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21
+#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22
+#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23
+#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24
+#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26
+#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27
+#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28
+#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000
+#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000
+#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000
+#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000
+#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000
+#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000
+#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000
+#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000
+#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000
+#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000
+#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000
+#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000
+#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000
+#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000
+
+#define VGT_DEBUG_REG18_MASK \
+     (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG18_dma_mem_full_MASK | \
+      VGT_DEBUG_REG18_dma_ram_re_MASK | \
+      VGT_DEBUG_REG18_dma_ram_we_MASK | \
+      VGT_DEBUG_REG18_dma_mem_empty_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \
+      VGT_DEBUG_REG18_bin_mem_full_MASK | \
+      VGT_DEBUG_REG18_bin_ram_we_MASK | \
+      VGT_DEBUG_REG18_bin_ram_re_MASK | \
+      VGT_DEBUG_REG18_bin_mem_empty_MASK | \
+      VGT_DEBUG_REG18_start_bin_req_MASK | \
+      VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \
+      VGT_DEBUG_REG18_dma_req_xfer_MASK | \
+      VGT_DEBUG_REG18_have_valid_bin_req_MASK | \
+      VGT_DEBUG_REG18_have_valid_dma_req_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK)
+
+#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \
+     ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \
+      (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \
+      (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \
+      (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \
+      (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \
+      (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \
+      (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \
+      (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \
+      (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \
+      (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \
+      (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \
+      (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \
+      (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \
+      (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \
+      (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \
+      (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \
+      (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \
+      (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \
+      (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT))
+
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+     } vgt_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+     } vgt_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg18_t f;
+} vgt_debug_reg18_u;
+
+
+/*
+ * VGT_DEBUG_REG20 struct
+ */
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_sent_cnt_SIZE  4
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5
+#define VGT_DEBUG_REG20_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5
+#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6
+#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7
+#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8
+#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9
+#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10
+#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11
+#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12
+#define VGT_DEBUG_REG20_hold_prim_SHIFT 13
+#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21
+#define VGT_DEBUG_REG20_out_trigger_SHIFT 26
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004
+#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020
+#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040
+#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080
+#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100
+#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200
+#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400
+#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800
+#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000
+#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000
+#define VGT_DEBUG_REG20_sent_cnt_MASK  0x0003c000
+#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000
+#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000
+#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000
+
+#define VGT_DEBUG_REG20_MASK \
+     (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_re_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_we_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_full_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_re_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_we_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_full_MASK | \
+      VGT_DEBUG_REG20_hold_prim_MASK | \
+      VGT_DEBUG_REG20_sent_cnt_MASK | \
+      VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \
+      VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \
+      VGT_DEBUG_REG20_out_trigger_MASK)
+
+#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \
+     ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \
+      (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \
+      (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \
+      (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \
+      (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \
+      (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \
+      (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \
+      (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \
+      (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \
+      (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \
+      (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \
+      (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \
+      (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \
+      (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \
+      (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \
+      (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \
+      (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \
+      (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \
+      (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int                                : 5;
+     } vgt_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int                                : 5;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+     } vgt_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg20_t f;
+} vgt_debug_reg20_u;
+
+
+/*
+ * VGT_DEBUG_REG21 struct
+ */
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3
+#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4
+#define VGT_DEBUG_REG21_new_packet_q_SIZE 1
+#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1
+#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1
+#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1
+#define VGT_DEBUG_REG21_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1
+#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14
+#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18
+#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22
+#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25
+#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26
+#define VGT_DEBUG_REG21_out_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e
+#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380
+#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000
+#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000
+#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000
+#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000
+#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000
+#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000
+#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG21_MASK \
+     (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \
+      VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \
+      VGT_DEBUG_REG21_alloc_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \
+      VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \
+      VGT_DEBUG_REG21_new_packet_q_MASK | \
+      VGT_DEBUG_REG21_new_allocate_q_MASK | \
+      VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \
+      VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \
+      VGT_DEBUG_REG21_insert_null_prim_MASK | \
+      VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \
+      VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \
+      VGT_DEBUG_REG21_buffered_thread_size_MASK | \
+      VGT_DEBUG_REG21_out_trigger_MASK)
+
+#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \
+     ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \
+      (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \
+      (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \
+      (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \
+      (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \
+      (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \
+      (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \
+      (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \
+      (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \
+      (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \
+      (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \
+      (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \
+      (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \
+      (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int                                : 4;
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+     } vgt_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+          unsigned int                                : 4;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+     } vgt_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg21_t f;
+} vgt_debug_reg21_u;
+
+
+/*
+ * VGT_CRC_SQ_DATA struct
+ */
+
+#define VGT_CRC_SQ_DATA_CRC_SIZE       32
+
+#define VGT_CRC_SQ_DATA_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_DATA_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_DATA_MASK \
+     (VGT_CRC_SQ_DATA_CRC_MASK)
+
+#define VGT_CRC_SQ_DATA(crc) \
+     ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT))
+
+#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \
+     ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \
+     vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_data_t f;
+} vgt_crc_sq_data_u;
+
+
+/*
+ * VGT_CRC_SQ_CTRL struct
+ */
+
+#define VGT_CRC_SQ_CTRL_CRC_SIZE       32
+
+#define VGT_CRC_SQ_CTRL_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_CTRL_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_CTRL_MASK \
+     (VGT_CRC_SQ_CTRL_CRC_MASK)
+
+#define VGT_CRC_SQ_CTRL(crc) \
+     ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT))
+
+#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \
+     ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \
+     vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_ctrl_t f;
+} vgt_crc_sq_ctrl_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER0_SELECT_MASK \
+     (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \
+     ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \
+     vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_select_t f;
+} vgt_perfcounter0_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER1_SELECT_MASK \
+     (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \
+     ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \
+     vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_select_t f;
+} vgt_perfcounter1_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER2_SELECT_MASK \
+     (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \
+     ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \
+     vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_select_t f;
+} vgt_perfcounter2_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER3_SELECT_MASK \
+     (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \
+     ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \
+     vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_select_t f;
+} vgt_perfcounter3_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_LOW struct
+ */
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER0_LOW_MASK \
+     (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \
+     ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \
+     vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_low_t f;
+} vgt_perfcounter0_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_LOW struct
+ */
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER1_LOW_MASK \
+     (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \
+     ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \
+     vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_low_t f;
+} vgt_perfcounter1_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_LOW struct
+ */
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER2_LOW_MASK \
+     (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \
+     ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \
+     vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_low_t f;
+} vgt_perfcounter2_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_LOW struct
+ */
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER3_LOW_MASK \
+     (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \
+     ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \
+     vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_low_t f;
+} vgt_perfcounter3_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_HI struct
+ */
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER0_HI_MASK \
+     (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \
+     ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \
+     vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_hi_t f;
+} vgt_perfcounter0_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_HI struct
+ */
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER1_HI_MASK \
+     (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \
+     ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \
+     vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_hi_t f;
+} vgt_perfcounter1_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_HI struct
+ */
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER2_HI_MASK \
+     (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \
+     ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \
+     vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_hi_t f;
+} vgt_perfcounter2_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_HI struct
+ */
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER3_HI_MASK \
+     (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \
+     ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \
+     vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_hi_t f;
+} vgt_perfcounter3_hi_u;
+
+
+#endif
+
+
+#if !defined (_SQ_FIDDLE_H)
+#define _SQ_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * SQ_GPR_MANAGEMENT struct
+ */
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000
+
+#define SQ_GPR_MANAGEMENT_MASK \
+     (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK)
+
+#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \
+     ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \
+      (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \
+      (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT))
+
+#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 13;
+     } sq_gpr_management_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int                                : 13;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+     } sq_gpr_management_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_gpr_management_t f;
+} sq_gpr_management_u;
+
+
+/*
+ * SQ_FLOW_CONTROL struct
+ */
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1
+#define SQ_FLOW_CONTROL_ONE_ALU_SIZE   1
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4
+#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE  1
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0
+#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4
+#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT  8
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12
+#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003
+#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010
+#define SQ_FLOW_CONTROL_ONE_ALU_MASK   0x00000100
+#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000
+#define SQ_FLOW_CONTROL_NO_PV_PS_MASK  0x00010000
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000
+
+#define SQ_FLOW_CONTROL_MASK \
+     (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ONE_THREAD_MASK | \
+      SQ_FLOW_CONTROL_ONE_ALU_MASK | \
+      SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \
+      SQ_FLOW_CONTROL_NO_PV_PS_MASK | \
+      SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \
+      SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \
+      SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \
+      SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \
+      SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \
+      SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \
+      SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK)
+
+#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \
+     ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \
+      (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \
+      (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \
+      (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \
+      (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \
+      (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \
+      (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \
+      (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \
+      (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \
+      (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \
+      (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \
+      (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \
+      (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \
+      (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \
+      (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT))
+
+#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+          unsigned int                                : 2;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int                                : 4;
+     } sq_flow_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int                                : 4;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 2;
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+     } sq_flow_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_flow_control_t f;
+} sq_flow_control_u;
+
+
+/*
+ * SQ_INST_STORE_MANAGMENT struct
+ */
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000
+
+#define SQ_INST_STORE_MANAGMENT_MASK \
+     (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \
+      SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK)
+
+#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \
+     ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \
+      (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT))
+
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+     } sq_inst_store_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+     } sq_inst_store_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_inst_store_managment_t f;
+} sq_inst_store_managment_u;
+
+
+/*
+ * SQ_RESOURCE_MANAGMENT struct
+ */
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000
+
+#define SQ_RESOURCE_MANAGMENT_MASK \
+     (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK)
+
+#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \
+     ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT))
+
+#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int                                : 7;
+     } sq_resource_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int                                : 7;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+     } sq_resource_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_resource_managment_t f;
+} sq_resource_managment_u;
+
+
+/*
+ * SQ_EO_RT struct
+ */
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE  8
+#define SQ_EO_RT_EO_TSTATE_RT_SIZE     8
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0
+#define SQ_EO_RT_EO_TSTATE_RT_SHIFT    16
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_MASK  0x000000ff
+#define SQ_EO_RT_EO_TSTATE_RT_MASK     0x00ff0000
+
+#define SQ_EO_RT_MASK \
+     (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \
+      SQ_EO_RT_EO_TSTATE_RT_MASK)
+
+#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \
+     ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \
+      (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT))
+
+#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+     } sq_eo_rt_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+     } sq_eo_rt_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_eo_rt_t f;
+} sq_eo_rt_u;
+
+
+/*
+ * SQ_DEBUG_MISC struct
+ */
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8
+#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1
+#define SQ_DEBUG_MISC_RESERVED_SIZE    2
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12
+#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20
+#define SQ_DEBUG_MISC_RESERVED_SHIFT   21
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000
+#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000
+#define SQ_DEBUG_MISC_RESERVED_MASK    0x00600000
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000
+
+#define SQ_DEBUG_MISC_MASK \
+     (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_READ_CTX_MASK | \
+      SQ_DEBUG_MISC_RESERVED_MASK | \
+      SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK)
+
+#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \
+     ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \
+      (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \
+      (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \
+      (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \
+      (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \
+      (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \
+      (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \
+      (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \
+      (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT))
+
+#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int                                : 3;
+     } sq_debug_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int                                : 3;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+     } sq_debug_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_t f;
+} sq_debug_misc_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_CNTL struct
+ */
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000
+#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000
+
+#define SQ_ACTIVITY_METER_CNTL_MASK \
+     (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \
+      SQ_ACTIVITY_METER_CNTL_SPARE_MASK)
+
+#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \
+     ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \
+      (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \
+      (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \
+      (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT))
+
+#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_cntl_t f;
+} sq_activity_meter_cntl_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_STATUS struct
+ */
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff
+
+#define SQ_ACTIVITY_METER_STATUS_MASK \
+     (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK)
+
+#define SQ_ACTIVITY_METER_STATUS(percent_busy) \
+     ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT))
+
+#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \
+     ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \
+     sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+          unsigned int                                : 24;
+     } sq_activity_meter_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int                                : 24;
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+     } sq_activity_meter_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_status_t f;
+} sq_activity_meter_status_u;
+
+
+/*
+ * SQ_INPUT_ARB_PRIORITY struct
+ */
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+
+#define SQ_INPUT_ARB_PRIORITY_MASK \
+     (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK)
+
+#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \
+     ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT))
+
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int                                : 14;
+     } sq_input_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int                                : 14;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_input_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_input_arb_priority_t f;
+} sq_input_arb_priority_u;
+
+
+/*
+ * SQ_THREAD_ARB_PRIORITY struct
+ */
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000
+
+#define SQ_THREAD_ARB_PRIORITY_MASK \
+     (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \
+      SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \
+      SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK)
+
+#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \
+     ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \
+      (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \
+      (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \
+      (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \
+      (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT))
+
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int                                : 9;
+     } sq_thread_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int                                : 9;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_thread_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_thread_arb_priority_t f;
+} sq_thread_arb_priority_u;
+
+
+/*
+ * SQ_DEBUG_INPUT_FSM struct
+ */
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE  3
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007
+#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK  0x00007000
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000
+
+#define SQ_DEBUG_INPUT_FSM_MASK \
+     (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \
+      SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK)
+
+#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \
+     ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \
+      (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \
+      (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \
+      (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \
+      (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \
+      (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \
+      (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \
+      (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT))
+
+#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_input_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int                                : 4;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+     } sq_debug_input_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_input_fsm_t f;
+} sq_debug_input_fsm_u;
+
+
+/*
+ * SQ_DEBUG_CONST_MGR_FSM struct
+ */
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000
+
+#define SQ_DEBUG_CONST_MGR_FSM_MASK \
+     (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK)
+
+#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \
+     ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \
+      (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \
+      (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \
+      (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \
+      (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \
+      (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \
+      (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \
+      (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \
+      (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \
+      (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT))
+
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int                                : 8;
+     } sq_debug_const_mgr_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int                                : 8;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+     } sq_debug_const_mgr_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_const_mgr_fsm_t f;
+} sq_debug_const_mgr_fsm_u;
+
+
+/*
+ * SQ_DEBUG_TP_FSM struct
+ */
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1
+#define SQ_DEBUG_TP_FSM_CF_TP_SIZE     4
+#define SQ_DEBUG_TP_FSM_IF_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2
+#define SQ_DEBUG_TP_FSM_GS_TP_SIZE     2
+#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT    0
+#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3
+#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT    4
+#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT    8
+#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT   12
+#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14
+#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT    16
+#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18
+#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT   20
+#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22
+#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT   24
+#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28
+
+#define SQ_DEBUG_TP_FSM_EX_TP_MASK     0x00000007
+#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_TP_FSM_CF_TP_MASK     0x000000f0
+#define SQ_DEBUG_TP_FSM_IF_TP_MASK     0x00000700
+#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_TP_FSM_TIS_TP_MASK    0x00003000
+#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000
+#define SQ_DEBUG_TP_FSM_GS_TP_MASK     0x00030000
+#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000
+#define SQ_DEBUG_TP_FSM_FCR_TP_MASK    0x00300000
+#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000
+#define SQ_DEBUG_TP_FSM_FCS_TP_MASK    0x03000000
+#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000
+
+#define SQ_DEBUG_TP_FSM_MASK \
+     (SQ_DEBUG_TP_FSM_EX_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED0_MASK | \
+      SQ_DEBUG_TP_FSM_CF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_IF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_TP_FSM_TIS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_TP_FSM_GS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED3_MASK | \
+      SQ_DEBUG_TP_FSM_FCR_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED4_MASK | \
+      SQ_DEBUG_TP_FSM_FCS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED5_MASK | \
+      SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK)
+
+#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \
+     ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \
+      (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \
+      (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \
+      (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \
+      (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \
+      (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \
+      (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \
+      (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \
+      (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \
+      (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \
+      (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \
+      (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \
+      (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \
+      (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT))
+
+#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_tp_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+     } sq_debug_tp_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tp_fsm_t f;
+} sq_debug_tp_fsm_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_0 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_0_MASK \
+     (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_0_t f;
+} sq_debug_fsm_alu_0_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_1 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_1_MASK \
+     (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_1_t f;
+} sq_debug_fsm_alu_1_u;
+
+
+/*
+ * SQ_DEBUG_EXP_ALLOC struct
+ */
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000
+
+#define SQ_DEBUG_EXP_ALLOC_MASK \
+     (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \
+      SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK)
+
+#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \
+     ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \
+      (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \
+      (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \
+      (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \
+      (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT))
+
+#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_exp_alloc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int                                : 10;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+     } sq_debug_exp_alloc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_exp_alloc_t f;
+} sq_debug_exp_alloc_u;
+
+
+/*
+ * SQ_DEBUG_PTR_BUFF struct
+ */
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000
+
+#define SQ_DEBUG_PTR_BUFF_MASK \
+     (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \
+      SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \
+      SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \
+      SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \
+      SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \
+      SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK)
+
+#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \
+     ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \
+      (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \
+      (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \
+      (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \
+      (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \
+      (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \
+      (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \
+      (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \
+      (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT))
+
+#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_ptr_buff_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int                                : 4;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+     } sq_debug_ptr_buff_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_ptr_buff_t f;
+} sq_debug_ptr_buff_u;
+
+
+/*
+ * SQ_DEBUG_GPR_VTX struct
+ */
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_VTX_MASK \
+     (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \
+     ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \
+      (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \
+      (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \
+      (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_vtx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int                                : 1;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_vtx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_vtx_t f;
+} sq_debug_gpr_vtx_u;
+
+
+/*
+ * SQ_DEBUG_GPR_PIX struct
+ */
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_PIX_MASK \
+     (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \
+     ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \
+      (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \
+      (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \
+      (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_pix_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int                                : 1;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_pix_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_pix_t f;
+} sq_debug_gpr_pix_u;
+
+
+/*
+ * SQ_DEBUG_TB_STATUS_SEL struct
+ */
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000
+
+#define SQ_DEBUG_TB_STATUS_SEL_MASK \
+     (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK)
+
+#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \
+     ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \
+      (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \
+      (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \
+      (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \
+      (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT))
+
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tb_status_sel_t f;
+} sq_debug_tb_status_sel_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_0 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE  1
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK  0x00200000
+
+#define SQ_DEBUG_VTX_TB_0_MASK \
+     (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \
+      SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK)
+
+#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \
+     ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \
+      (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \
+      (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \
+      (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \
+      (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \
+      (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \
+      (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_vtx_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int                                : 10;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+     } sq_debug_vtx_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_0_t f;
+} sq_debug_vtx_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_1 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff
+
+#define SQ_DEBUG_VTX_TB_1_MASK \
+     (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK)
+
+#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \
+     ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \
+     ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \
+     sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+          unsigned int                                : 16;
+     } sq_debug_vtx_tb_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int                                : 16;
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+     } sq_debug_vtx_tb_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_1_t f;
+} sq_debug_vtx_tb_1_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATUS_REG struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \
+     (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \
+     ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \
+     ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \
+     sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_status_reg_t f;
+} sq_debug_vtx_tb_status_reg_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \
+     ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \
+     ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \
+     sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_state_mem_t f;
+} sq_debug_vtx_tb_state_mem_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE    1
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25
+#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT   31
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000
+#define SQ_DEBUG_PIX_TB_0_BUSY_MASK    0x80000000
+
+#define SQ_DEBUG_PIX_TB_0_MASK \
+     (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_BUSY_MASK)
+
+#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \
+     ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \
+      (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \
+      (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \
+      (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \
+      (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \
+      (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_0_t f;
+} sq_debug_pix_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \
+     ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \
+     ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \
+     sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_0_t f;
+} sq_debug_pix_tb_status_reg_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \
+     ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \
+     ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \
+     sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_1_t f;
+} sq_debug_pix_tb_status_reg_1_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \
+     ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \
+     ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \
+     sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_2_t f;
+} sq_debug_pix_tb_status_reg_2_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \
+     ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \
+     ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \
+     sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_3_t f;
+} sq_debug_pix_tb_status_reg_3_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \
+     ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \
+     ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \
+     sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_state_mem_t f;
+} sq_debug_pix_tb_state_mem_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER0_SELECT_MASK \
+     (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \
+     ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \
+     sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_select_t f;
+} sq_perfcounter0_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER1_SELECT_MASK \
+     (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \
+     ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \
+     sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_select_t f;
+} sq_perfcounter1_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER2_SELECT_MASK \
+     (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \
+     ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \
+     sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_select_t f;
+} sq_perfcounter2_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER3_SELECT_MASK \
+     (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \
+     ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \
+     sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_select_t f;
+} sq_perfcounter3_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_LOW struct
+ */
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER0_LOW_MASK \
+     (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \
+     ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \
+     sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_low_t f;
+} sq_perfcounter0_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_HI struct
+ */
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER0_HI_MASK \
+     (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \
+     ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \
+     sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_hi_t f;
+} sq_perfcounter0_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_LOW struct
+ */
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER1_LOW_MASK \
+     (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \
+     ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \
+     sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_low_t f;
+} sq_perfcounter1_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_HI struct
+ */
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER1_HI_MASK \
+     (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \
+     ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \
+     sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_hi_t f;
+} sq_perfcounter1_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_LOW struct
+ */
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER2_LOW_MASK \
+     (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \
+     ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \
+     sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_low_t f;
+} sq_perfcounter2_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_HI struct
+ */
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER2_HI_MASK \
+     (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \
+     ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \
+     sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_hi_t f;
+} sq_perfcounter2_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_LOW struct
+ */
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER3_LOW_MASK \
+     (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \
+     ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \
+     sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_low_t f;
+} sq_perfcounter3_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_HI struct
+ */
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER3_HI_MASK \
+     (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \
+     ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \
+     sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_hi_t f;
+} sq_perfcounter3_hi_u;
+
+
+/*
+ * SX_PERFCOUNTER0_SELECT struct
+ */
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SX_PERFCOUNTER0_SELECT_MASK \
+     (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SX_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \
+     ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \
+     sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sx_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sx_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_select_t f;
+} sx_perfcounter0_select_u;
+
+
+/*
+ * SX_PERFCOUNTER0_LOW struct
+ */
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SX_PERFCOUNTER0_LOW_MASK \
+     (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \
+     ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \
+     sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_low_t f;
+} sx_perfcounter0_low_u;
+
+
+/*
+ * SX_PERFCOUNTER0_HI struct
+ */
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SX_PERFCOUNTER0_HI_MASK \
+     (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \
+     ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \
+     sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sx_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sx_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_hi_t f;
+} sx_perfcounter0_hi_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_0 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0
+#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT 6
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8
+#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT 14
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_ALU_0_MASK \
+     (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_ALU_0(vector_result, cst_0_abs_mod, low_precision_16b_fp, scalar_result, sst_0_abs_mod, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \
+     ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \
+      (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) | \
+      (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \
+      (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \
+      (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) | \
+      (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \
+      (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \
+      (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \
+      (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \
+      (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \
+      (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_CST_0_ABS_MOD(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SST_0_ABS_MOD(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_CST_0_ABS_MOD(sq_instruction_alu_0_reg, cst_0_abs_mod) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) | (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SST_0_ABS_MOD(sq_instruction_alu_0_reg, sst_0_abs_mod) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) | (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+          unsigned int cst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int sst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+     } sq_instruction_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int sst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int cst_0_abs_mod                  : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE;
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+     } sq_instruction_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_0_t f;
+} sq_instruction_alu_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_1 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_1_MASK \
+     (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \
+      SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK)
+
+#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \
+     ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \
+      (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \
+      (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \
+      (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \
+      (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \
+      (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \
+      (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \
+      (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \
+      (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \
+      (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \
+      (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \
+      (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \
+      (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \
+      (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \
+      (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \
+      (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \
+      (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \
+      (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+     } sq_instruction_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+     } sq_instruction_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_1_t f;
+} sq_instruction_alu_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_2 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_2_MASK \
+     (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK)
+
+#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \
+     ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \
+      (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \
+      (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \
+      (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \
+      (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \
+      (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \
+      (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \
+      (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \
+      (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \
+      (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \
+      (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \
+      (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \
+      (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+     } sq_instruction_alu_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+     } sq_instruction_alu_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_2_t f;
+} sq_instruction_alu_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_0_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \
+     ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \
+      (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_0_t f;
+} sq_instruction_cf_exec_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_1_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \
+     ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_1_t f;
+} sq_instruction_cf_exec_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_EXEC_2_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \
+     ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \
+      (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_2_t f;
+} sq_instruction_cf_exec_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000
+
+#define SQ_INSTRUCTION_CF_LOOP_0_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \
+      (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_0_t f;
+} sq_instruction_cf_loop_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_CF_LOOP_1_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_1_t f;
+} sq_instruction_cf_loop_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_LOOP_2_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \
+     ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_2_t f;
+} sq_instruction_cf_loop_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \
+      (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_0_t f;
+} sq_instruction_cf_jmp_call_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \
+      (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_1_t f;
+} sq_instruction_cf_jmp_call_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_2_t f;
+} sq_instruction_cf_jmp_call_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \
+     ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_0_t f;
+} sq_instruction_cf_alloc_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \
+      (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_1_t f;
+} sq_instruction_cf_alloc_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_2_t f;
+} sq_instruction_cf_alloc_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_TFETCH_0_MASK \
+     (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \
+     ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \
+      (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \
+      (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \
+      (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \
+      (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \
+      (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_0_t f;
+} sq_instruction_tfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_1_MASK \
+     (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \
+      (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \
+      (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \
+      (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \
+      (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \
+      (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \
+      (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \
+      (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \
+      (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \
+      (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_1_t f;
+} sq_instruction_tfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_2_MASK \
+     (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \
+     ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \
+      (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \
+      (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \
+      (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \
+      (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \
+      (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \
+      (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_2_t f;
+} sq_instruction_tfetch_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_VFETCH_0_MASK \
+     (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \
+     ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \
+      (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \
+      (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \
+      (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_0_t f;
+} sq_instruction_vfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_1_MASK \
+     (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \
+      (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \
+      (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \
+      (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \
+      (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \
+      (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_1_t f;
+} sq_instruction_vfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_2_MASK \
+     (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \
+     ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \
+      (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+          unsigned int                                : 8;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 7;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int                                : 7;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 8;
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_2_t f;
+} sq_instruction_vfetch_2_u;
+
+
+/*
+ * SQ_CONSTANT_0 struct
+ */
+
+#define SQ_CONSTANT_0_RED_SIZE         32
+
+#define SQ_CONSTANT_0_RED_SHIFT        0
+
+#define SQ_CONSTANT_0_RED_MASK         0xffffffff
+
+#define SQ_CONSTANT_0_MASK \
+     (SQ_CONSTANT_0_RED_MASK)
+
+#define SQ_CONSTANT_0(red) \
+     ((red << SQ_CONSTANT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \
+     ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \
+     sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_0_t f;
+} sq_constant_0_u;
+
+
+/*
+ * SQ_CONSTANT_1 struct
+ */
+
+#define SQ_CONSTANT_1_GREEN_SIZE       32
+
+#define SQ_CONSTANT_1_GREEN_SHIFT      0
+
+#define SQ_CONSTANT_1_GREEN_MASK       0xffffffff
+
+#define SQ_CONSTANT_1_MASK \
+     (SQ_CONSTANT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_1(green) \
+     ((green << SQ_CONSTANT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \
+     ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \
+     sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_1_t f;
+} sq_constant_1_u;
+
+
+/*
+ * SQ_CONSTANT_2 struct
+ */
+
+#define SQ_CONSTANT_2_BLUE_SIZE        32
+
+#define SQ_CONSTANT_2_BLUE_SHIFT       0
+
+#define SQ_CONSTANT_2_BLUE_MASK        0xffffffff
+
+#define SQ_CONSTANT_2_MASK \
+     (SQ_CONSTANT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_2(blue) \
+     ((blue << SQ_CONSTANT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \
+     ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \
+     sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_2_t f;
+} sq_constant_2_u;
+
+
+/*
+ * SQ_CONSTANT_3 struct
+ */
+
+#define SQ_CONSTANT_3_ALPHA_SIZE       32
+
+#define SQ_CONSTANT_3_ALPHA_SHIFT      0
+
+#define SQ_CONSTANT_3_ALPHA_MASK       0xffffffff
+
+#define SQ_CONSTANT_3_MASK \
+     (SQ_CONSTANT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_3(alpha) \
+     ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \
+     ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \
+     sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_3_t f;
+} sq_constant_3_u;
+
+
+/*
+ * SQ_FETCH_0 struct
+ */
+
+#define SQ_FETCH_0_VALUE_SIZE          32
+
+#define SQ_FETCH_0_VALUE_SHIFT         0
+
+#define SQ_FETCH_0_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_0_MASK \
+     (SQ_FETCH_0_VALUE_MASK)
+
+#define SQ_FETCH_0(value) \
+     ((value << SQ_FETCH_0_VALUE_SHIFT))
+
+#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \
+     ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT)
+
+#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \
+     sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_0_t f;
+} sq_fetch_0_u;
+
+
+/*
+ * SQ_FETCH_1 struct
+ */
+
+#define SQ_FETCH_1_VALUE_SIZE          32
+
+#define SQ_FETCH_1_VALUE_SHIFT         0
+
+#define SQ_FETCH_1_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_1_MASK \
+     (SQ_FETCH_1_VALUE_MASK)
+
+#define SQ_FETCH_1(value) \
+     ((value << SQ_FETCH_1_VALUE_SHIFT))
+
+#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \
+     ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT)
+
+#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \
+     sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_1_t f;
+} sq_fetch_1_u;
+
+
+/*
+ * SQ_FETCH_2 struct
+ */
+
+#define SQ_FETCH_2_VALUE_SIZE          32
+
+#define SQ_FETCH_2_VALUE_SHIFT         0
+
+#define SQ_FETCH_2_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_2_MASK \
+     (SQ_FETCH_2_VALUE_MASK)
+
+#define SQ_FETCH_2(value) \
+     ((value << SQ_FETCH_2_VALUE_SHIFT))
+
+#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \
+     ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT)
+
+#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \
+     sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_2_t f;
+} sq_fetch_2_u;
+
+
+/*
+ * SQ_FETCH_3 struct
+ */
+
+#define SQ_FETCH_3_VALUE_SIZE          32
+
+#define SQ_FETCH_3_VALUE_SHIFT         0
+
+#define SQ_FETCH_3_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_3_MASK \
+     (SQ_FETCH_3_VALUE_MASK)
+
+#define SQ_FETCH_3(value) \
+     ((value << SQ_FETCH_3_VALUE_SHIFT))
+
+#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \
+     ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT)
+
+#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \
+     sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_3_t f;
+} sq_fetch_3_u;
+
+
+/*
+ * SQ_FETCH_4 struct
+ */
+
+#define SQ_FETCH_4_VALUE_SIZE          32
+
+#define SQ_FETCH_4_VALUE_SHIFT         0
+
+#define SQ_FETCH_4_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_4_MASK \
+     (SQ_FETCH_4_VALUE_MASK)
+
+#define SQ_FETCH_4(value) \
+     ((value << SQ_FETCH_4_VALUE_SHIFT))
+
+#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \
+     ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT)
+
+#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \
+     sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_4_t f;
+} sq_fetch_4_u;
+
+
+/*
+ * SQ_FETCH_5 struct
+ */
+
+#define SQ_FETCH_5_VALUE_SIZE          32
+
+#define SQ_FETCH_5_VALUE_SHIFT         0
+
+#define SQ_FETCH_5_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_5_MASK \
+     (SQ_FETCH_5_VALUE_MASK)
+
+#define SQ_FETCH_5(value) \
+     ((value << SQ_FETCH_5_VALUE_SHIFT))
+
+#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \
+     ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT)
+
+#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \
+     sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_5_t f;
+} sq_fetch_5_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_0 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0
+#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001
+#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_0_MASK \
+     (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \
+      SQ_CONSTANT_VFETCH_0_STATE_MASK | \
+      SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \
+     ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \
+      (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \
+      (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_0_t f;
+} sq_constant_vfetch_0_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_1 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_1_MASK \
+     (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \
+      SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \
+     ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \
+      (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_1_t f;
+} sq_constant_vfetch_1_u;
+
+
+/*
+ * SQ_CONSTANT_T2 struct
+ */
+
+#define SQ_CONSTANT_T2_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T2_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T2_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T2_MASK \
+     (SQ_CONSTANT_T2_VALUE_MASK)
+
+#define SQ_CONSTANT_T2(value) \
+     ((value << SQ_CONSTANT_T2_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \
+     ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \
+     sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t2_t f;
+} sq_constant_t2_u;
+
+
+/*
+ * SQ_CONSTANT_T3 struct
+ */
+
+#define SQ_CONSTANT_T3_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T3_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T3_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T3_MASK \
+     (SQ_CONSTANT_T3_VALUE_MASK)
+
+#define SQ_CONSTANT_T3(value) \
+     ((value << SQ_CONSTANT_T3_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \
+     ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \
+     sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t3_t f;
+} sq_constant_t3_u;
+
+
+/*
+ * SQ_CF_BOOLEANS struct
+ */
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_BOOLEANS_MASK \
+     (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_booleans_t f;
+} sq_cf_booleans_u;
+
+
+/*
+ * SQ_CF_LOOP struct
+ */
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_START_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE   8
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT  16
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK  0x000000ff
+#define SQ_CF_LOOP_CF_LOOP_START_MASK  0x0000ff00
+#define SQ_CF_LOOP_CF_LOOP_STEP_MASK   0x00ff0000
+
+#define SQ_CF_LOOP_MASK \
+     (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_loop_t f;
+} sq_cf_loop_u;
+
+
+/*
+ * SQ_CONSTANT_RT_0 struct
+ */
+
+#define SQ_CONSTANT_RT_0_RED_SIZE      32
+
+#define SQ_CONSTANT_RT_0_RED_SHIFT     0
+
+#define SQ_CONSTANT_RT_0_RED_MASK      0xffffffff
+
+#define SQ_CONSTANT_RT_0_MASK \
+     (SQ_CONSTANT_RT_0_RED_MASK)
+
+#define SQ_CONSTANT_RT_0(red) \
+     ((red << SQ_CONSTANT_RT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \
+     ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \
+     sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_0_t f;
+} sq_constant_rt_0_u;
+
+
+/*
+ * SQ_CONSTANT_RT_1 struct
+ */
+
+#define SQ_CONSTANT_RT_1_GREEN_SIZE    32
+
+#define SQ_CONSTANT_RT_1_GREEN_SHIFT   0
+
+#define SQ_CONSTANT_RT_1_GREEN_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_1_MASK \
+     (SQ_CONSTANT_RT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_RT_1(green) \
+     ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \
+     ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \
+     sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_1_t f;
+} sq_constant_rt_1_u;
+
+
+/*
+ * SQ_CONSTANT_RT_2 struct
+ */
+
+#define SQ_CONSTANT_RT_2_BLUE_SIZE     32
+
+#define SQ_CONSTANT_RT_2_BLUE_SHIFT    0
+
+#define SQ_CONSTANT_RT_2_BLUE_MASK     0xffffffff
+
+#define SQ_CONSTANT_RT_2_MASK \
+     (SQ_CONSTANT_RT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_RT_2(blue) \
+     ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \
+     ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \
+     sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_2_t f;
+} sq_constant_rt_2_u;
+
+
+/*
+ * SQ_CONSTANT_RT_3 struct
+ */
+
+#define SQ_CONSTANT_RT_3_ALPHA_SIZE    32
+
+#define SQ_CONSTANT_RT_3_ALPHA_SHIFT   0
+
+#define SQ_CONSTANT_RT_3_ALPHA_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_3_MASK \
+     (SQ_CONSTANT_RT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_RT_3(alpha) \
+     ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \
+     ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \
+     sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_3_t f;
+} sq_constant_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_0 struct
+ */
+
+#define SQ_FETCH_RT_0_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_0_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_0_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_0_MASK \
+     (SQ_FETCH_RT_0_VALUE_MASK)
+
+#define SQ_FETCH_RT_0(value) \
+     ((value << SQ_FETCH_RT_0_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \
+     ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \
+     sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_0_t f;
+} sq_fetch_rt_0_u;
+
+
+/*
+ * SQ_FETCH_RT_1 struct
+ */
+
+#define SQ_FETCH_RT_1_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_1_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_1_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_1_MASK \
+     (SQ_FETCH_RT_1_VALUE_MASK)
+
+#define SQ_FETCH_RT_1(value) \
+     ((value << SQ_FETCH_RT_1_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \
+     ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \
+     sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_1_t f;
+} sq_fetch_rt_1_u;
+
+
+/*
+ * SQ_FETCH_RT_2 struct
+ */
+
+#define SQ_FETCH_RT_2_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_2_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_2_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_2_MASK \
+     (SQ_FETCH_RT_2_VALUE_MASK)
+
+#define SQ_FETCH_RT_2(value) \
+     ((value << SQ_FETCH_RT_2_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \
+     ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \
+     sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_2_t f;
+} sq_fetch_rt_2_u;
+
+
+/*
+ * SQ_FETCH_RT_3 struct
+ */
+
+#define SQ_FETCH_RT_3_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_3_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_3_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_3_MASK \
+     (SQ_FETCH_RT_3_VALUE_MASK)
+
+#define SQ_FETCH_RT_3(value) \
+     ((value << SQ_FETCH_RT_3_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \
+     ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \
+     sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_3_t f;
+} sq_fetch_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_4 struct
+ */
+
+#define SQ_FETCH_RT_4_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_4_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_4_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_4_MASK \
+     (SQ_FETCH_RT_4_VALUE_MASK)
+
+#define SQ_FETCH_RT_4(value) \
+     ((value << SQ_FETCH_RT_4_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \
+     ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \
+     sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_4_t f;
+} sq_fetch_rt_4_u;
+
+
+/*
+ * SQ_FETCH_RT_5 struct
+ */
+
+#define SQ_FETCH_RT_5_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_5_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_5_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_5_MASK \
+     (SQ_FETCH_RT_5_VALUE_MASK)
+
+#define SQ_FETCH_RT_5(value) \
+     ((value << SQ_FETCH_RT_5_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \
+     ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \
+     sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_5_t f;
+} sq_fetch_rt_5_u;
+
+
+/*
+ * SQ_CF_RT_BOOLEANS struct
+ */
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_RT_BOOLEANS_MASK \
+     (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_booleans_t f;
+} sq_cf_rt_booleans_u;
+
+
+/*
+ * SQ_CF_RT_LOOP struct
+ */
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff
+#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000
+
+#define SQ_CF_RT_LOOP_MASK \
+     (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_rt_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_rt_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_loop_t f;
+} sq_cf_rt_loop_u;
+
+
+/*
+ * SQ_VS_PROGRAM struct
+ */
+
+#define SQ_VS_PROGRAM_BASE_SIZE        12
+#define SQ_VS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_VS_PROGRAM_BASE_SHIFT       0
+#define SQ_VS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_VS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_VS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_VS_PROGRAM_MASK \
+     (SQ_VS_PROGRAM_BASE_MASK | \
+      SQ_VS_PROGRAM_SIZE_MASK)
+
+#define SQ_VS_PROGRAM(base, size) \
+     ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_VS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_vs_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+     } sq_vs_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_program_t f;
+} sq_vs_program_u;
+
+
+/*
+ * SQ_PS_PROGRAM struct
+ */
+
+#define SQ_PS_PROGRAM_BASE_SIZE        12
+#define SQ_PS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_PS_PROGRAM_BASE_SHIFT       0
+#define SQ_PS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_PS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_PS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_PS_PROGRAM_MASK \
+     (SQ_PS_PROGRAM_BASE_MASK | \
+      SQ_PS_PROGRAM_SIZE_MASK)
+
+#define SQ_PS_PROGRAM(base, size) \
+     ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_PS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_ps_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+     } sq_ps_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_program_t f;
+} sq_ps_program_u;
+
+
+/*
+ * SQ_CF_PROGRAM_SIZE struct
+ */
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000
+
+#define SQ_CF_PROGRAM_SIZE_MASK \
+     (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \
+      SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK)
+
+#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \
+     ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \
+      (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT))
+
+#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 9;
+     } sq_cf_program_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int                                : 9;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+     } sq_cf_program_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_program_size_t f;
+} sq_cf_program_size_u;
+
+
+/*
+ * SQ_INTERPOLATOR_CNTL struct
+ */
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000
+
+#define SQ_INTERPOLATOR_CNTL_MASK \
+     (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \
+      SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK)
+
+#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \
+     ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \
+      (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT))
+
+#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+     } sq_interpolator_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+     } sq_interpolator_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_interpolator_cntl_t f;
+} sq_interpolator_cntl_u;
+
+
+/*
+ * SQ_PROGRAM_CNTL struct
+ */
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000
+#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000
+
+#define SQ_PROGRAM_CNTL_MASK \
+     (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK)
+
+#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \
+     ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \
+      (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \
+      (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \
+      (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \
+      (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \
+      (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \
+      (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \
+      (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \
+      (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \
+      (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT))
+
+#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+     } sq_program_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+     } sq_program_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_program_cntl_t f;
+} sq_program_cntl_u;
+
+
+/*
+ * SQ_WRAPPING_0 struct
+ */
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f
+#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0
+#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00
+#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000
+#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000
+#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000
+#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000
+#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000
+
+#define SQ_WRAPPING_0_MASK \
+     (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_7_MASK)
+
+#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \
+     ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \
+      (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \
+      (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \
+      (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \
+      (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \
+      (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \
+      (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \
+      (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT))
+
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+     } sq_wrapping_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+     } sq_wrapping_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_0_t f;
+} sq_wrapping_0_u;
+
+
+/*
+ * SQ_WRAPPING_1 struct
+ */
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f
+#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0
+#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00
+#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000
+#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000
+#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000
+#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000
+#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000
+
+#define SQ_WRAPPING_1_MASK \
+     (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_15_MASK)
+
+#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \
+     ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \
+      (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \
+      (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \
+      (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \
+      (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \
+      (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \
+      (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \
+      (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT))
+
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+     } sq_wrapping_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+     } sq_wrapping_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_1_t f;
+} sq_wrapping_1_u;
+
+
+/*
+ * SQ_VS_CONST struct
+ */
+
+#define SQ_VS_CONST_BASE_SIZE          9
+#define SQ_VS_CONST_SIZE_SIZE          9
+
+#define SQ_VS_CONST_BASE_SHIFT         0
+#define SQ_VS_CONST_SIZE_SHIFT         12
+
+#define SQ_VS_CONST_BASE_MASK          0x000001ff
+#define SQ_VS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_VS_CONST_MASK \
+     (SQ_VS_CONST_BASE_MASK | \
+      SQ_VS_CONST_SIZE_MASK)
+
+#define SQ_VS_CONST(base, size) \
+     ((base << SQ_VS_CONST_BASE_SHIFT) | \
+      (size << SQ_VS_CONST_SIZE_SHIFT))
+
+#define SQ_VS_CONST_GET_BASE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT)
+
+#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_vs_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+     } sq_vs_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_const_t f;
+} sq_vs_const_u;
+
+
+/*
+ * SQ_PS_CONST struct
+ */
+
+#define SQ_PS_CONST_BASE_SIZE          9
+#define SQ_PS_CONST_SIZE_SIZE          9
+
+#define SQ_PS_CONST_BASE_SHIFT         0
+#define SQ_PS_CONST_SIZE_SHIFT         12
+
+#define SQ_PS_CONST_BASE_MASK          0x000001ff
+#define SQ_PS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_PS_CONST_MASK \
+     (SQ_PS_CONST_BASE_MASK | \
+      SQ_PS_CONST_SIZE_MASK)
+
+#define SQ_PS_CONST(base, size) \
+     ((base << SQ_PS_CONST_BASE_SHIFT) | \
+      (size << SQ_PS_CONST_SIZE_SHIFT))
+
+#define SQ_PS_CONST_GET_BASE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT)
+
+#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_ps_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+     } sq_ps_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_const_t f;
+} sq_ps_const_u;
+
+
+/*
+ * SQ_CONTEXT_MISC struct
+ */
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000
+
+#define SQ_CONTEXT_MISC_MASK \
+     (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \
+      SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \
+      SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \
+      SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \
+      SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK)
+
+#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \
+     ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \
+      (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \
+      (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \
+      (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \
+      (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \
+      (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \
+      (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT))
+
+#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int                                : 4;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int                                : 13;
+     } sq_context_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int                                : 13;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int                                : 4;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+     } sq_context_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_context_misc_t f;
+} sq_context_misc_u;
+
+
+/*
+ * SQ_CF_RD_BASE struct
+ */
+
+#define SQ_CF_RD_BASE_RD_BASE_SIZE     3
+
+#define SQ_CF_RD_BASE_RD_BASE_SHIFT    0
+
+#define SQ_CF_RD_BASE_RD_BASE_MASK     0x00000007
+
+#define SQ_CF_RD_BASE_MASK \
+     (SQ_CF_RD_BASE_RD_BASE_MASK)
+
+#define SQ_CF_RD_BASE(rd_base) \
+     ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT))
+
+#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \
+     ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \
+     sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+          unsigned int                                : 29;
+     } sq_cf_rd_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int                                : 29;
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+     } sq_cf_rd_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rd_base_t f;
+} sq_cf_rd_base_u;
+
+
+/*
+ * SQ_DEBUG_MISC_0 struct
+ */
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000
+
+#define SQ_DEBUG_MISC_0_MASK \
+     (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK)
+
+#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \
+     ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \
+      (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \
+      (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \
+      (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT))
+
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+     } sq_debug_misc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+     } sq_debug_misc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_0_t f;
+} sq_debug_misc_0_u;
+
+
+/*
+ * SQ_DEBUG_MISC_1 struct
+ */
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000
+
+#define SQ_DEBUG_MISC_1_MASK \
+     (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \
+      SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \
+      SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \
+      SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK)
+
+#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \
+     ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \
+      (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \
+      (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \
+      (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT))
+
+#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int                                : 5;
+     } sq_debug_misc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int                                : 5;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+     } sq_debug_misc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_1_t f;
+} sq_debug_misc_1_u;
+
+
+#endif
+
+
+#if !defined (_SX_FIDDLE_H)
+#define _SX_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_TP_FIDDLE_H)
+#define _TP_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * TC_CNTL_STATUS struct
+ */
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2
+#define TC_CNTL_STATUS_TC_BUSY_SIZE    1
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18
+#define TC_CNTL_STATUS_TC_BUSY_SHIFT   31
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000
+#define TC_CNTL_STATUS_TC_BUSY_MASK    0x80000000
+
+#define TC_CNTL_STATUS_MASK \
+     (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \
+      TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \
+      TC_CNTL_STATUS_TC_BUSY_MASK)
+
+#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \
+     ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \
+      (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \
+      (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT))
+
+#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+          unsigned int                                : 17;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+     } tc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 17;
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+     } tc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tc_cntl_status_t f;
+} tc_cntl_status_u;
+
+
+/*
+ * TCR_CHICKEN struct
+ */
+
+#define TCR_CHICKEN_SPARE_SIZE         32
+
+#define TCR_CHICKEN_SPARE_SHIFT        0
+
+#define TCR_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCR_CHICKEN_MASK \
+     (TCR_CHICKEN_SPARE_MASK)
+
+#define TCR_CHICKEN(spare) \
+     ((spare << TCR_CHICKEN_SPARE_SHIFT))
+
+#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \
+     ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT)
+
+#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \
+     tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_chicken_t f;
+} tcr_chicken_u;
+
+
+/*
+ * TCF_CHICKEN struct
+ */
+
+#define TCF_CHICKEN_SPARE_SIZE         32
+
+#define TCF_CHICKEN_SPARE_SHIFT        0
+
+#define TCF_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCF_CHICKEN_MASK \
+     (TCF_CHICKEN_SPARE_MASK)
+
+#define TCF_CHICKEN(spare) \
+     ((spare << TCF_CHICKEN_SPARE_SHIFT))
+
+#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \
+     ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT)
+
+#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \
+     tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_chicken_t f;
+} tcf_chicken_u;
+
+
+/*
+ * TCM_CHICKEN struct
+ */
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1
+#define TCM_CHICKEN_SPARE_SIZE         23
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8
+#define TCM_CHICKEN_SPARE_SHIFT        9
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100
+#define TCM_CHICKEN_SPARE_MASK         0xfffffe00
+
+#define TCM_CHICKEN_MASK \
+     (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \
+      TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \
+      TCM_CHICKEN_SPARE_MASK)
+
+#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \
+     ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \
+      (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \
+      (spare << TCM_CHICKEN_SPARE_SHIFT))
+
+#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT)
+
+#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+     } tcm_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+     } tcm_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_chicken_t f;
+} tcm_chicken_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER0_SELECT_MASK \
+     (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \
+     ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \
+     tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_select_t f;
+} tcr_perfcounter0_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER1_SELECT_MASK \
+     (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \
+     ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \
+     tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_select_t f;
+} tcr_perfcounter1_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_HI struct
+ */
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER0_HI_MASK \
+     (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \
+     ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \
+     tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_hi_t f;
+} tcr_perfcounter0_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_HI struct
+ */
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER1_HI_MASK \
+     (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \
+     ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \
+     tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_hi_t f;
+} tcr_perfcounter1_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_LOW struct
+ */
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER0_LOW_MASK \
+     (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \
+     ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \
+     tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_low_t f;
+} tcr_perfcounter0_low_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_LOW struct
+ */
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER1_LOW_MASK \
+     (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \
+     ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \
+     tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_low_t f;
+} tcr_perfcounter1_low_u;
+
+
+/*
+ * TP_TC_CLKGATE_CNTL struct
+ */
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038
+
+#define TP_TC_CLKGATE_CNTL_MASK \
+     (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \
+      TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK)
+
+#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \
+     ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \
+      (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT))
+
+#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int                                : 26;
+     } tp_tc_clkgate_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int                                : 26;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+     } tp_tc_clkgate_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp_tc_clkgate_cntl_t f;
+} tp_tc_clkgate_cntl_u;
+
+
+/*
+ * TPC_CNTL_STATUS struct
+ */
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BUSY_SIZE  1
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15
+#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17
+#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19
+#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22
+#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23
+#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25
+#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27
+#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30
+#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000
+#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000
+#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000
+#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000
+#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000
+#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000
+#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000
+#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000
+#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000
+#define TPC_CNTL_STATUS_TPC_BUSY_MASK  0x80000000
+
+#define TPC_CNTL_STATUS_MASK \
+     (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTR_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TF_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \
+      TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \
+      TPC_CNTL_STATUS_TPC_BUSY_MASK)
+
+#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \
+     ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \
+      (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \
+      (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \
+      (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \
+      (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \
+      (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \
+      (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \
+      (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \
+      (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \
+      (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \
+      (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \
+      (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \
+      (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \
+      (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \
+      (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \
+      (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \
+      (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \
+      (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \
+      (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \
+      (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \
+      (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \
+      (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \
+      (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT))
+
+#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_cntl_status_t f;
+} tpc_cntl_status_u;
+
+
+/*
+ * TPC_DEBUG0 struct
+ */
+
+#define TPC_DEBUG0_LOD_CNTL_SIZE       2
+#define TPC_DEBUG0_IC_CTR_SIZE         2
+#define TPC_DEBUG0_WALKER_CNTL_SIZE    4
+#define TPC_DEBUG0_ALIGNER_CNTL_SIZE   3
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1
+#define TPC_DEBUG0_WALKER_STATE_SIZE   10
+#define TPC_DEBUG0_ALIGNER_STATE_SIZE  2
+#define TPC_DEBUG0_REG_CLK_EN_SIZE     1
+#define TPC_DEBUG0_TPC_CLK_EN_SIZE     1
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE   1
+
+#define TPC_DEBUG0_LOD_CNTL_SHIFT      0
+#define TPC_DEBUG0_IC_CTR_SHIFT        2
+#define TPC_DEBUG0_WALKER_CNTL_SHIFT   4
+#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT  8
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12
+#define TPC_DEBUG0_WALKER_STATE_SHIFT  16
+#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26
+#define TPC_DEBUG0_REG_CLK_EN_SHIFT    29
+#define TPC_DEBUG0_TPC_CLK_EN_SHIFT    30
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT  31
+
+#define TPC_DEBUG0_LOD_CNTL_MASK       0x00000003
+#define TPC_DEBUG0_IC_CTR_MASK         0x0000000c
+#define TPC_DEBUG0_WALKER_CNTL_MASK    0x000000f0
+#define TPC_DEBUG0_ALIGNER_CNTL_MASK   0x00000700
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000
+#define TPC_DEBUG0_WALKER_STATE_MASK   0x03ff0000
+#define TPC_DEBUG0_ALIGNER_STATE_MASK  0x0c000000
+#define TPC_DEBUG0_REG_CLK_EN_MASK     0x20000000
+#define TPC_DEBUG0_TPC_CLK_EN_MASK     0x40000000
+#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK   0x80000000
+
+#define TPC_DEBUG0_MASK \
+     (TPC_DEBUG0_LOD_CNTL_MASK | \
+      TPC_DEBUG0_IC_CTR_MASK | \
+      TPC_DEBUG0_WALKER_CNTL_MASK | \
+      TPC_DEBUG0_ALIGNER_CNTL_MASK | \
+      TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \
+      TPC_DEBUG0_WALKER_STATE_MASK | \
+      TPC_DEBUG0_ALIGNER_STATE_MASK | \
+      TPC_DEBUG0_REG_CLK_EN_MASK | \
+      TPC_DEBUG0_TPC_CLK_EN_MASK | \
+      TPC_DEBUG0_SQ_TP_WAKEUP_MASK)
+
+#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \
+     ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \
+      (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \
+      (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \
+      (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \
+      (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \
+      (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \
+      (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \
+      (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \
+      (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \
+      (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT))
+
+#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 3;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+     } tpc_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+     } tpc_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug0_t f;
+} tpc_debug0_u;
+
+
+/*
+ * TPC_DEBUG1 struct
+ */
+
+#define TPC_DEBUG1_UNUSED_SIZE         1
+
+#define TPC_DEBUG1_UNUSED_SHIFT        0
+
+#define TPC_DEBUG1_UNUSED_MASK         0x00000001
+
+#define TPC_DEBUG1_MASK \
+     (TPC_DEBUG1_UNUSED_MASK)
+
+#define TPC_DEBUG1(unused) \
+     ((unused << TPC_DEBUG1_UNUSED_SHIFT))
+
+#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \
+     ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT)
+
+#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \
+     tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+          unsigned int                                : 31;
+     } tpc_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int                                : 31;
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+     } tpc_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug1_t f;
+} tpc_debug1_u;
+
+
+/*
+ * TPC_CHICKEN struct
+ */
+
+#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1
+#define TPC_CHICKEN_SPARE_SIZE         31
+
+#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0
+#define TPC_CHICKEN_SPARE_SHIFT        1
+
+#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001
+#define TPC_CHICKEN_SPARE_MASK         0xfffffffe
+
+#define TPC_CHICKEN_MASK \
+     (TPC_CHICKEN_BLEND_PRECISION_MASK | \
+      TPC_CHICKEN_SPARE_MASK)
+
+#define TPC_CHICKEN(blend_precision, spare) \
+     ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \
+      (spare << TPC_CHICKEN_SPARE_SHIFT))
+
+#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT)
+
+#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+     } tpc_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+     } tpc_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_chicken_t f;
+} tpc_chicken_u;
+
+
+/*
+ * TP0_CNTL_STATUS struct
+ */
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1
+#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TP_BUSY_SIZE   1
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14
+#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16
+#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17
+#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18
+#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19
+#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21
+#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23
+#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25
+#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27
+#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29
+#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30
+#define TP0_CNTL_STATUS_TP_BUSY_SHIFT  31
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200
+#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000
+#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000
+#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000
+#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000
+#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000
+#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000
+#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000
+#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000
+#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000
+#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000
+#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000
+#define TP0_CNTL_STATUS_TP_BUSY_MASK   0x80000000
+
+#define TP0_CNTL_STATUS_MASK \
+     (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_IN_LC_RTS_MASK | \
+      TP0_CNTL_STATUS_LC_LA_RTS_MASK | \
+      TP0_CNTL_STATUS_LA_FL_RTS_MASK | \
+      TP0_CNTL_STATUS_FL_TA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \
+      TP0_CNTL_STATUS_TB_TO_RTS_MASK | \
+      TP0_CNTL_STATUS_TP_BUSY_MASK)
+
+#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \
+     ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \
+      (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \
+      (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \
+      (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \
+      (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \
+      (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \
+      (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \
+      (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \
+      (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \
+      (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \
+      (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \
+      (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \
+      (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \
+      (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \
+      (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \
+      (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \
+      (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \
+      (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \
+      (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \
+      (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \
+      (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \
+      (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \
+      (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \
+      (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \
+      (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \
+      (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \
+      (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \
+      (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \
+      (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \
+      (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT))
+
+#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_cntl_status_t f;
+} tp0_cntl_status_u;
+
+
+/*
+ * TP0_DEBUG struct
+ */
+
+#define TP0_DEBUG_Q_LOD_CNTL_SIZE      2
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE  1
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17
+#define TP0_DEBUG_REG_CLK_EN_SIZE      1
+#define TP0_DEBUG_PERF_CLK_EN_SIZE     1
+#define TP0_DEBUG_TP_CLK_EN_SIZE       1
+#define TP0_DEBUG_Q_WALKER_CNTL_SIZE   4
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE  3
+
+#define TP0_DEBUG_Q_LOD_CNTL_SHIFT     0
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4
+#define TP0_DEBUG_REG_CLK_EN_SHIFT     21
+#define TP0_DEBUG_PERF_CLK_EN_SHIFT    22
+#define TP0_DEBUG_TP_CLK_EN_SHIFT      23
+#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT  24
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28
+
+#define TP0_DEBUG_Q_LOD_CNTL_MASK      0x00000003
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK  0x00000008
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0
+#define TP0_DEBUG_REG_CLK_EN_MASK      0x00200000
+#define TP0_DEBUG_PERF_CLK_EN_MASK     0x00400000
+#define TP0_DEBUG_TP_CLK_EN_MASK       0x00800000
+#define TP0_DEBUG_Q_WALKER_CNTL_MASK   0x0f000000
+#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK  0x70000000
+
+#define TP0_DEBUG_MASK \
+     (TP0_DEBUG_Q_LOD_CNTL_MASK | \
+      TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \
+      TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \
+      TP0_DEBUG_REG_CLK_EN_MASK | \
+      TP0_DEBUG_PERF_CLK_EN_MASK | \
+      TP0_DEBUG_TP_CLK_EN_MASK | \
+      TP0_DEBUG_Q_WALKER_CNTL_MASK | \
+      TP0_DEBUG_Q_ALIGNER_CNTL_MASK)
+
+#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \
+     ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \
+      (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \
+      (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \
+      (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \
+      (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \
+      (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \
+      (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \
+      (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT))
+
+#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+     } tp0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int                                : 1;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+     } tp0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_debug_t f;
+} tp0_debug_u;
+
+
+/*
+ * TP0_CHICKEN struct
+ */
+
+#define TP0_CHICKEN_TT_MODE_SIZE       1
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1
+#define TP0_CHICKEN_SPARE_SIZE         30
+
+#define TP0_CHICKEN_TT_MODE_SHIFT      0
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1
+#define TP0_CHICKEN_SPARE_SHIFT        2
+
+#define TP0_CHICKEN_TT_MODE_MASK       0x00000001
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002
+#define TP0_CHICKEN_SPARE_MASK         0xfffffffc
+
+#define TP0_CHICKEN_MASK \
+     (TP0_CHICKEN_TT_MODE_MASK | \
+      TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \
+      TP0_CHICKEN_SPARE_MASK)
+
+#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \
+     ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \
+      (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \
+      (spare << TP0_CHICKEN_SPARE_SHIFT))
+
+#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT)
+
+#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+     } tp0_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+     } tp0_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_chicken_t f;
+} tp0_chicken_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER0_SELECT_MASK \
+     (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \
+     ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \
+     tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_select_t f;
+} tp0_perfcounter0_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_HI struct
+ */
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER0_HI_MASK \
+     (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \
+     ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \
+     tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_hi_t f;
+} tp0_perfcounter0_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_LOW struct
+ */
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER0_LOW_MASK \
+     (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \
+     ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \
+     tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_low_t f;
+} tp0_perfcounter0_low_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER1_SELECT_MASK \
+     (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \
+     ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \
+     tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_select_t f;
+} tp0_perfcounter1_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_HI struct
+ */
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER1_HI_MASK \
+     (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \
+     ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \
+     tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_hi_t f;
+} tp0_perfcounter1_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_LOW struct
+ */
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER1_LOW_MASK \
+     (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \
+     ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \
+     tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_low_t f;
+} tp0_perfcounter1_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER0_SELECT_MASK \
+     (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \
+     ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \
+     tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_select_t f;
+} tcm_perfcounter0_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER1_SELECT_MASK \
+     (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \
+     ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \
+     tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_select_t f;
+} tcm_perfcounter1_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_HI struct
+ */
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER0_HI_MASK \
+     (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \
+     ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \
+     tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_hi_t f;
+} tcm_perfcounter0_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_HI struct
+ */
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER1_HI_MASK \
+     (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \
+     ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \
+     tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_hi_t f;
+} tcm_perfcounter1_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_LOW struct
+ */
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER0_LOW_MASK \
+     (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \
+     ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \
+     tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_low_t f;
+} tcm_perfcounter0_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_LOW struct
+ */
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER1_LOW_MASK \
+     (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \
+     ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \
+     tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_low_t f;
+} tcm_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER0_SELECT_MASK \
+     (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \
+     ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \
+     tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_select_t f;
+} tcf_perfcounter0_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER1_SELECT_MASK \
+     (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \
+     ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \
+     tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_select_t f;
+} tcf_perfcounter1_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER2_SELECT_MASK \
+     (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \
+     ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \
+     tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_select_t f;
+} tcf_perfcounter2_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER3_SELECT_MASK \
+     (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \
+     ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \
+     tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_select_t f;
+} tcf_perfcounter3_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER4_SELECT_MASK \
+     (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \
+     ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \
+     tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter4_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter4_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_select_t f;
+} tcf_perfcounter4_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER5_SELECT_MASK \
+     (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \
+     ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \
+     tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter5_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter5_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_select_t f;
+} tcf_perfcounter5_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER6_SELECT_MASK \
+     (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \
+     ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \
+     tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter6_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter6_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_select_t f;
+} tcf_perfcounter6_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER7_SELECT_MASK \
+     (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \
+     ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \
+     tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter7_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter7_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_select_t f;
+} tcf_perfcounter7_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER8_SELECT_MASK \
+     (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \
+     ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \
+     tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter8_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter8_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_select_t f;
+} tcf_perfcounter8_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER9_SELECT_MASK \
+     (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \
+     ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \
+     tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter9_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter9_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_select_t f;
+} tcf_perfcounter9_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER10_SELECT_MASK \
+     (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \
+     ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \
+     tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter10_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter10_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_select_t f;
+} tcf_perfcounter10_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER11_SELECT_MASK \
+     (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \
+     ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \
+     tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter11_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter11_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_select_t f;
+} tcf_perfcounter11_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_HI struct
+ */
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER0_HI_MASK \
+     (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \
+     ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \
+     tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_hi_t f;
+} tcf_perfcounter0_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_HI struct
+ */
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER1_HI_MASK \
+     (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \
+     ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \
+     tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_hi_t f;
+} tcf_perfcounter1_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_HI struct
+ */
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER2_HI_MASK \
+     (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \
+     ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \
+     tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_hi_t f;
+} tcf_perfcounter2_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_HI struct
+ */
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER3_HI_MASK \
+     (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \
+     ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \
+     tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_hi_t f;
+} tcf_perfcounter3_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_HI struct
+ */
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER4_HI_MASK \
+     (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \
+     ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \
+     tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter4_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter4_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_hi_t f;
+} tcf_perfcounter4_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_HI struct
+ */
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER5_HI_MASK \
+     (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \
+     ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \
+     tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter5_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter5_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_hi_t f;
+} tcf_perfcounter5_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_HI struct
+ */
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER6_HI_MASK \
+     (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \
+     ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \
+     tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter6_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter6_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_hi_t f;
+} tcf_perfcounter6_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_HI struct
+ */
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER7_HI_MASK \
+     (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \
+     ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \
+     tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter7_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter7_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_hi_t f;
+} tcf_perfcounter7_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_HI struct
+ */
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER8_HI_MASK \
+     (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \
+     ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \
+     tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter8_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter8_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_hi_t f;
+} tcf_perfcounter8_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_HI struct
+ */
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER9_HI_MASK \
+     (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \
+     ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \
+     tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter9_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter9_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_hi_t f;
+} tcf_perfcounter9_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_HI struct
+ */
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER10_HI_MASK \
+     (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \
+     ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \
+     tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter10_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter10_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_hi_t f;
+} tcf_perfcounter10_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_HI struct
+ */
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER11_HI_MASK \
+     (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \
+     ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \
+     tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter11_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter11_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_hi_t f;
+} tcf_perfcounter11_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_LOW struct
+ */
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER0_LOW_MASK \
+     (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \
+     ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \
+     tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_low_t f;
+} tcf_perfcounter0_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_LOW struct
+ */
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER1_LOW_MASK \
+     (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \
+     ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \
+     tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_low_t f;
+} tcf_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_LOW struct
+ */
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER2_LOW_MASK \
+     (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \
+     ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \
+     tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_low_t f;
+} tcf_perfcounter2_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_LOW struct
+ */
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER3_LOW_MASK \
+     (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \
+     ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \
+     tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_low_t f;
+} tcf_perfcounter3_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_LOW struct
+ */
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER4_LOW_MASK \
+     (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \
+     ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \
+     tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_low_t f;
+} tcf_perfcounter4_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_LOW struct
+ */
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER5_LOW_MASK \
+     (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \
+     ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \
+     tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_low_t f;
+} tcf_perfcounter5_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_LOW struct
+ */
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER6_LOW_MASK \
+     (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \
+     ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \
+     tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_low_t f;
+} tcf_perfcounter6_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_LOW struct
+ */
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER7_LOW_MASK \
+     (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \
+     ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \
+     tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_low_t f;
+} tcf_perfcounter7_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_LOW struct
+ */
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER8_LOW_MASK \
+     (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \
+     ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \
+     tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_low_t f;
+} tcf_perfcounter8_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_LOW struct
+ */
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER9_LOW_MASK \
+     (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \
+     ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \
+     tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_low_t f;
+} tcf_perfcounter9_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_LOW struct
+ */
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER10_LOW_MASK \
+     (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \
+     ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \
+     tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_low_t f;
+} tcf_perfcounter10_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_LOW struct
+ */
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER11_LOW_MASK \
+     (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \
+     ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \
+     tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_low_t f;
+} tcf_perfcounter11_low_u;
+
+
+/*
+ * TCF_DEBUG struct
+ */
+
+#define TCF_DEBUG_not_MH_TC_rtr_SIZE   1
+#define TCF_DEBUG_TC_MH_send_SIZE      1
+#define TCF_DEBUG_not_FG0_rtr_SIZE     1
+#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1
+#define TCF_DEBUG_TCB_ff_stall_SIZE    1
+#define TCF_DEBUG_TCB_miss_stall_SIZE  1
+#define TCF_DEBUG_TCA_TCB_stall_SIZE   1
+#define TCF_DEBUG_PF0_stall_SIZE       1
+#define TCF_DEBUG_TP0_full_SIZE        1
+#define TCF_DEBUG_TPC_full_SIZE        1
+#define TCF_DEBUG_not_TPC_rtr_SIZE     1
+#define TCF_DEBUG_tca_state_rts_SIZE   1
+#define TCF_DEBUG_tca_rts_SIZE         1
+
+#define TCF_DEBUG_not_MH_TC_rtr_SHIFT  6
+#define TCF_DEBUG_TC_MH_send_SHIFT     7
+#define TCF_DEBUG_not_FG0_rtr_SHIFT    8
+#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12
+#define TCF_DEBUG_TCB_ff_stall_SHIFT   13
+#define TCF_DEBUG_TCB_miss_stall_SHIFT 14
+#define TCF_DEBUG_TCA_TCB_stall_SHIFT  15
+#define TCF_DEBUG_PF0_stall_SHIFT      16
+#define TCF_DEBUG_TP0_full_SHIFT       20
+#define TCF_DEBUG_TPC_full_SHIFT       24
+#define TCF_DEBUG_not_TPC_rtr_SHIFT    25
+#define TCF_DEBUG_tca_state_rts_SHIFT  26
+#define TCF_DEBUG_tca_rts_SHIFT        27
+
+#define TCF_DEBUG_not_MH_TC_rtr_MASK   0x00000040
+#define TCF_DEBUG_TC_MH_send_MASK      0x00000080
+#define TCF_DEBUG_not_FG0_rtr_MASK     0x00000100
+#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000
+#define TCF_DEBUG_TCB_ff_stall_MASK    0x00002000
+#define TCF_DEBUG_TCB_miss_stall_MASK  0x00004000
+#define TCF_DEBUG_TCA_TCB_stall_MASK   0x00008000
+#define TCF_DEBUG_PF0_stall_MASK       0x00010000
+#define TCF_DEBUG_TP0_full_MASK        0x00100000
+#define TCF_DEBUG_TPC_full_MASK        0x01000000
+#define TCF_DEBUG_not_TPC_rtr_MASK     0x02000000
+#define TCF_DEBUG_tca_state_rts_MASK   0x04000000
+#define TCF_DEBUG_tca_rts_MASK         0x08000000
+
+#define TCF_DEBUG_MASK \
+     (TCF_DEBUG_not_MH_TC_rtr_MASK | \
+      TCF_DEBUG_TC_MH_send_MASK | \
+      TCF_DEBUG_not_FG0_rtr_MASK | \
+      TCF_DEBUG_not_TCB_TCO_rtr_MASK | \
+      TCF_DEBUG_TCB_ff_stall_MASK | \
+      TCF_DEBUG_TCB_miss_stall_MASK | \
+      TCF_DEBUG_TCA_TCB_stall_MASK | \
+      TCF_DEBUG_PF0_stall_MASK | \
+      TCF_DEBUG_TP0_full_MASK | \
+      TCF_DEBUG_TPC_full_MASK | \
+      TCF_DEBUG_not_TPC_rtr_MASK | \
+      TCF_DEBUG_tca_state_rts_MASK | \
+      TCF_DEBUG_tca_rts_MASK)
+
+#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \
+     ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \
+      (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \
+      (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \
+      (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \
+      (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \
+      (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \
+      (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \
+      (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \
+      (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \
+      (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \
+      (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \
+      (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \
+      (tca_rts << TCF_DEBUG_tca_rts_SHIFT))
+
+#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_GET_TP0_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_GET_TPC_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_GET_tca_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT)
+
+#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 6;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int                                : 4;
+     } tcf_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 4;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int                                : 6;
+     } tcf_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_debug_t f;
+} tcf_debug_u;
+
+
+/*
+ * TCA_FIFO_DEBUG struct
+ */
+
+#define TCA_FIFO_DEBUG_tp0_full_SIZE   1
+#define TCA_FIFO_DEBUG_tpc_full_SIZE   1
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1
+#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1
+#define TCA_FIFO_DEBUG_FW_full_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1
+#define TCA_FIFO_DEBUG_FW_rts0_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1
+
+#define TCA_FIFO_DEBUG_tp0_full_SHIFT  0
+#define TCA_FIFO_DEBUG_tpc_full_SHIFT  4
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5
+#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6
+#define TCA_FIFO_DEBUG_FW_full_SHIFT   7
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8
+#define TCA_FIFO_DEBUG_FW_rts0_SHIFT   12
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17
+
+#define TCA_FIFO_DEBUG_tp0_full_MASK   0x00000001
+#define TCA_FIFO_DEBUG_tpc_full_MASK   0x00000010
+#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020
+#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040
+#define TCA_FIFO_DEBUG_FW_full_MASK    0x00000080
+#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100
+#define TCA_FIFO_DEBUG_FW_rts0_MASK    0x00001000
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000
+#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000
+
+#define TCA_FIFO_DEBUG_MASK \
+     (TCA_FIFO_DEBUG_tp0_full_MASK | \
+      TCA_FIFO_DEBUG_tpc_full_MASK | \
+      TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \
+      TCA_FIFO_DEBUG_load_tp_fifos_MASK | \
+      TCA_FIFO_DEBUG_FW_full_MASK | \
+      TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \
+      TCA_FIFO_DEBUG_FW_rts0_MASK | \
+      TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \
+      TCA_FIFO_DEBUG_FW_tpc_rts_MASK)
+
+#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \
+     ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \
+      (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \
+      (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \
+      (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \
+      (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \
+      (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \
+      (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \
+      (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \
+      (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT))
+
+#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int                                : 14;
+     } tca_fifo_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int                                : 14;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+     } tca_fifo_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_fifo_debug_t f;
+} tca_fifo_debug_u;
+
+
+/*
+ * TCA_PROBE_DEBUG struct
+ */
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001
+
+#define TCA_PROBE_DEBUG_MASK \
+     (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK)
+
+#define TCA_PROBE_DEBUG(probefilter_stall) \
+     ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT))
+
+#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \
+     ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \
+     tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+          unsigned int                                : 31;
+     } tca_probe_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int                                : 31;
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+     } tca_probe_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_probe_debug_t f;
+} tca_probe_debug_u;
+
+
+/*
+ * TCA_TPC_DEBUG struct
+ */
+
+#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1
+#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1
+
+#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12
+#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13
+
+#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000
+#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000
+
+#define TCA_TPC_DEBUG_MASK \
+     (TCA_TPC_DEBUG_captue_state_rts_MASK | \
+      TCA_TPC_DEBUG_capture_tca_rts_MASK)
+
+#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \
+     ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \
+      (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT))
+
+#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 12;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int                                : 18;
+     } tca_tpc_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 18;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int                                : 12;
+     } tca_tpc_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_tpc_debug_t f;
+} tca_tpc_debug_u;
+
+
+/*
+ * TCB_CORE_DEBUG struct
+ */
+
+#define TCB_CORE_DEBUG_access512_SIZE  1
+#define TCB_CORE_DEBUG_tiled_SIZE      1
+#define TCB_CORE_DEBUG_opcode_SIZE     3
+#define TCB_CORE_DEBUG_format_SIZE     6
+#define TCB_CORE_DEBUG_sector_format_SIZE 5
+#define TCB_CORE_DEBUG_sector_format512_SIZE 3
+
+#define TCB_CORE_DEBUG_access512_SHIFT 0
+#define TCB_CORE_DEBUG_tiled_SHIFT     1
+#define TCB_CORE_DEBUG_opcode_SHIFT    4
+#define TCB_CORE_DEBUG_format_SHIFT    8
+#define TCB_CORE_DEBUG_sector_format_SHIFT 16
+#define TCB_CORE_DEBUG_sector_format512_SHIFT 24
+
+#define TCB_CORE_DEBUG_access512_MASK  0x00000001
+#define TCB_CORE_DEBUG_tiled_MASK      0x00000002
+#define TCB_CORE_DEBUG_opcode_MASK     0x00000070
+#define TCB_CORE_DEBUG_format_MASK     0x00003f00
+#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000
+#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000
+
+#define TCB_CORE_DEBUG_MASK \
+     (TCB_CORE_DEBUG_access512_MASK | \
+      TCB_CORE_DEBUG_tiled_MASK | \
+      TCB_CORE_DEBUG_opcode_MASK | \
+      TCB_CORE_DEBUG_format_MASK | \
+      TCB_CORE_DEBUG_sector_format_MASK | \
+      TCB_CORE_DEBUG_sector_format512_MASK)
+
+#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \
+     ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \
+      (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \
+      (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \
+      (format << TCB_CORE_DEBUG_format_SHIFT) | \
+      (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \
+      (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT))
+
+#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int                                : 2;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 1;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 5;
+     } tcb_core_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int                                : 5;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 2;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+     } tcb_core_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_core_debug_t f;
+} tcb_core_debug_u;
+
+
+/*
+ * TCB_TAG0_DEBUG struct
+ */
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG0_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG0_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG0_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG0_DEBUG_MASK \
+     (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG0_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG0_DEBUG_miss_stall_MASK | \
+      TCB_TAG0_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG0_DEBUG_max_misses_MASK)
+
+#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+     } tcb_tag0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag0_debug_t f;
+} tcb_tag0_debug_u;
+
+
+/*
+ * TCB_TAG1_DEBUG struct
+ */
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG1_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG1_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG1_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG1_DEBUG_MASK \
+     (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG1_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG1_DEBUG_miss_stall_MASK | \
+      TCB_TAG1_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG1_DEBUG_max_misses_MASK)
+
+#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+     } tcb_tag1_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag1_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag1_debug_t f;
+} tcb_tag1_debug_u;
+
+
+/*
+ * TCB_TAG2_DEBUG struct
+ */
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG2_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG2_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG2_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG2_DEBUG_MASK \
+     (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG2_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG2_DEBUG_miss_stall_MASK | \
+      TCB_TAG2_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG2_DEBUG_max_misses_MASK)
+
+#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+     } tcb_tag2_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag2_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag2_debug_t f;
+} tcb_tag2_debug_u;
+
+
+/*
+ * TCB_TAG3_DEBUG struct
+ */
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG3_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG3_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG3_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG3_DEBUG_MASK \
+     (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG3_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG3_DEBUG_miss_stall_MASK | \
+      TCB_TAG3_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG3_DEBUG_max_misses_MASK)
+
+#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+     } tcb_tag3_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag3_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag3_debug_t f;
+} tcb_tag3_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \
+     (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \
+     ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \
+      (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \
+      (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \
+      (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \
+      (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \
+      (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \
+      (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \
+      (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT))
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int                                : 3;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int                                : 3;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_sector_walker0_debug_t f;
+} tcb_fetch_gen_sector_walker0_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_WALKER_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \
+     (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \
+     ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \
+      (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \
+      (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \
+      (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \
+      (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \
+      (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT))
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 4;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int                                : 12;
+     } tcb_fetch_gen_walker_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 12;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int                                : 4;
+     } tcb_fetch_gen_walker_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_walker_debug_t f;
+} tcb_fetch_gen_walker_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_PIPE0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \
+     (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \
+     ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \
+      (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \
+      (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \
+      (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \
+      (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \
+      (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \
+      (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \
+      (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \
+      (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \
+      (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \
+      (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT))
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_pipe0_debug_t f;
+} tcb_fetch_gen_pipe0_debug_u;
+
+
+/*
+ * TCD_INPUT0_DEBUG struct
+ */
+
+#define TCD_INPUT0_DEBUG_empty_SIZE    1
+#define TCD_INPUT0_DEBUG_full_SIZE     1
+#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_cnt_q1_SIZE   2
+#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_ip_send_SIZE  1
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1
+
+#define TCD_INPUT0_DEBUG_empty_SHIFT   16
+#define TCD_INPUT0_DEBUG_full_SHIFT    17
+#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20
+#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT  21
+#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23
+#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26
+
+#define TCD_INPUT0_DEBUG_empty_MASK    0x00010000
+#define TCD_INPUT0_DEBUG_full_MASK     0x00020000
+#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000
+#define TCD_INPUT0_DEBUG_cnt_q1_MASK   0x00600000
+#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000
+#define TCD_INPUT0_DEBUG_ip_send_MASK  0x01000000
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000
+#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000
+
+#define TCD_INPUT0_DEBUG_MASK \
+     (TCD_INPUT0_DEBUG_empty_MASK | \
+      TCD_INPUT0_DEBUG_full_MASK | \
+      TCD_INPUT0_DEBUG_valid_q1_MASK | \
+      TCD_INPUT0_DEBUG_cnt_q1_MASK | \
+      TCD_INPUT0_DEBUG_last_send_q1_MASK | \
+      TCD_INPUT0_DEBUG_ip_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_busy_MASK)
+
+#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \
+     ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \
+      (full << TCD_INPUT0_DEBUG_full_SHIFT) | \
+      (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \
+      (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \
+      (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \
+      (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \
+      (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \
+      (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT))
+
+#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 16;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int                                : 2;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int                                : 5;
+     } tcd_input0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 5;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int                                : 2;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int                                : 16;
+     } tcd_input0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_input0_debug_t f;
+} tcd_input0_debug_u;
+
+
+/*
+ * TCD_DEGAMMA_DEBUG struct
+ */
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040
+
+#define TCD_DEGAMMA_DEBUG_MASK \
+     (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK)
+
+#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \
+     ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \
+      (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \
+      (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \
+      (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \
+      (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \
+      (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT))
+
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int                                : 25;
+     } tcd_degamma_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int                                : 25;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+     } tcd_degamma_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_degamma_debug_t f;
+} tcd_degamma_debug_u;
+
+
+/*
+ * TCD_DXTMUX_SCTARB_DEBUG struct
+ */
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000
+
+#define TCD_DXTMUX_SCTARB_DEBUG_MASK \
+     (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK)
+
+#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \
+     ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \
+      (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \
+      (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \
+      (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \
+      (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \
+      (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \
+      (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \
+      (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \
+      (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT))
+
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 9;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int                                : 2;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 2;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int                                : 9;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtmux_sctarb_debug_t f;
+} tcd_dxtmux_sctarb_debug_u;
+
+
+/*
+ * TCD_DXTC_ARB_DEBUG struct
+ */
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4
+#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010
+#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000
+
+#define TCD_DXTC_ARB_DEBUG_MASK \
+     (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \
+      TCD_DXTC_ARB_DEBUG_pstate_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK)
+
+#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \
+     ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \
+      (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \
+      (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \
+      (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \
+      (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \
+      (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \
+      (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \
+      (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \
+      (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT))
+
+#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int                                : 4;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+     } tcd_dxtc_arb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int                                : 4;
+     } tcd_dxtc_arb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtc_arb_debug_t f;
+} tcd_dxtc_arb_debug_u;
+
+
+/*
+ * TCD_STALLS_DEBUG struct
+ */
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000
+#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000
+
+#define TCD_STALLS_DEBUG_MASK \
+     (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_incoming_rtr_MASK)
+
+#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \
+     ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \
+      (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \
+      (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \
+      (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \
+      (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \
+      (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT))
+
+#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int                                : 10;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+     } tcd_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int                                : 10;
+     } tcd_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_stalls_debug_t f;
+} tcd_stalls_debug_u;
+
+
+/*
+ * TCO_STALLS_DEBUG struct
+ */
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080
+
+#define TCO_STALLS_DEBUG_MASK \
+     (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK)
+
+#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \
+     ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \
+      (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \
+      (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT))
+
+#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 5;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int                                : 24;
+     } tco_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 24;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int                                : 5;
+     } tco_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_stalls_debug_t f;
+} tco_stalls_debug_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG0 struct
+ */
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1
+#define TCO_QUAD0_DEBUG0_busy_SIZE     1
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16
+#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29
+#define TCO_QUAD0_DEBUG0_busy_SHIFT    30
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000
+#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000
+#define TCO_QUAD0_DEBUG0_busy_MASK     0x40000000
+
+#define TCO_QUAD0_DEBUG0_MASK \
+     (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \
+      TCO_QUAD0_DEBUG0_read_cache_q_MASK | \
+      TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \
+      TCO_QUAD0_DEBUG0_busy_MASK)
+
+#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \
+     ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \
+      (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \
+      (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \
+      (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \
+      (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \
+      (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \
+      (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \
+      (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \
+      (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \
+      (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \
+      (busy << TCO_QUAD0_DEBUG0_busy_SHIFT))
+
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int                                : 2;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int                                : 1;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 2;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+     } tco_quad0_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug0_t f;
+} tco_quad0_debug0_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG1 struct
+ */
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_empty_SIZE    1
+#define TCO_QUAD0_DEBUG1_full_SIZE     1
+#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0
+#define TCO_QUAD0_DEBUG1_empty_SHIFT   1
+#define TCO_QUAD0_DEBUG1_full_SHIFT    2
+#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001
+#define TCO_QUAD0_DEBUG1_empty_MASK    0x00000002
+#define TCO_QUAD0_DEBUG1_full_MASK     0x00000004
+#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800
+#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000
+#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000
+
+#define TCO_QUAD0_DEBUG1_MASK \
+     (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_empty_MASK | \
+      TCO_QUAD0_DEBUG1_full_MASK | \
+      TCO_QUAD0_DEBUG1_write_enable_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \
+      TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \
+      TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK)
+
+#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \
+     ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \
+      (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \
+      (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \
+      (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \
+      (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \
+      (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \
+      (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \
+      (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \
+      (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \
+      (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \
+      (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \
+      (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \
+      (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT))
+
+#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int                                : 2;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int                                : 1;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int                                : 2;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+     } tco_quad0_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug1_t f;
+} tco_quad0_debug1_u;
+
+
+#endif
+
+
+#if !defined (_TC_FIDDLE_H)
+#define _TC_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_SC_FIDDLE_H)
+#define _SC_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_BC_FIDDLE_H)
+#define _BC_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * RB_SURFACE_INFO struct
+ */
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff
+#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000
+
+#define RB_SURFACE_INFO_MASK \
+     (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \
+      RB_SURFACE_INFO_MSAA_SAMPLES_MASK)
+
+#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \
+     ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \
+      (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT))
+
+#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int                                : 16;
+     } rb_surface_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int                                : 16;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+     } rb_surface_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_surface_info_t f;
+} rb_surface_info_u;
+
+
+/*
+ * RB_COLOR_INFO struct
+ */
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2
+#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1
+#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2
+#define RB_COLOR_INFO_COLOR_SWAP_SIZE  2
+#define RB_COLOR_INFO_COLOR_BASE_SIZE  20
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4
+#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6
+#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7
+#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9
+#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12
+
+#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030
+#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040
+#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180
+#define RB_COLOR_INFO_COLOR_SWAP_MASK  0x00000600
+#define RB_COLOR_INFO_COLOR_BASE_MASK  0xfffff000
+
+#define RB_COLOR_INFO_MASK \
+     (RB_COLOR_INFO_COLOR_FORMAT_MASK | \
+      RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \
+      RB_COLOR_INFO_COLOR_LINEAR_MASK | \
+      RB_COLOR_INFO_COLOR_ENDIAN_MASK | \
+      RB_COLOR_INFO_COLOR_SWAP_MASK | \
+      RB_COLOR_INFO_COLOR_BASE_MASK)
+
+#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \
+     ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \
+      (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \
+      (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \
+      (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \
+      (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \
+      (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT))
+
+#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+     } rb_color_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+     } rb_color_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_info_t f;
+} rb_color_info_u;
+
+
+/*
+ * RB_DEPTH_INFO struct
+ */
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1
+#define RB_DEPTH_INFO_DEPTH_BASE_SIZE  20
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0
+#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001
+#define RB_DEPTH_INFO_DEPTH_BASE_MASK  0xfffff000
+
+#define RB_DEPTH_INFO_MASK \
+     (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \
+      RB_DEPTH_INFO_DEPTH_BASE_MASK)
+
+#define RB_DEPTH_INFO(depth_format, depth_base) \
+     ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \
+      (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT))
+
+#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+     } rb_depth_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+     } rb_depth_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_info_t f;
+} rb_depth_info_u;
+
+
+/*
+ * RB_STENCILREFMASK struct
+ */
+
+#define RB_STENCILREFMASK_STENCILREF_SIZE 8
+#define RB_STENCILREFMASK_STENCILMASK_SIZE 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8
+
+#define RB_STENCILREFMASK_STENCILREF_SHIFT 0
+#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
+
+#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
+#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
+#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000
+
+#define RB_STENCILREFMASK_MASK \
+     (RB_STENCILREFMASK_STENCILREF_MASK | \
+      RB_STENCILREFMASK_STENCILMASK_MASK | \
+      RB_STENCILREFMASK_STENCILWRITEMASK_MASK)
+
+#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask) \
+     ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \
+      (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \
+      (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT))
+
+#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+
+#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int                                : 8;
+     } rb_stencilrefmask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int                                : 8;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+     } rb_stencilrefmask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_t f;
+} rb_stencilrefmask_u;
+
+
+/*
+ * RB_ALPHA_REF struct
+ */
+
+#define RB_ALPHA_REF_ALPHA_REF_SIZE    32
+
+#define RB_ALPHA_REF_ALPHA_REF_SHIFT   0
+
+#define RB_ALPHA_REF_ALPHA_REF_MASK    0xffffffff
+
+#define RB_ALPHA_REF_MASK \
+     (RB_ALPHA_REF_ALPHA_REF_MASK)
+
+#define RB_ALPHA_REF(alpha_ref) \
+     ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT))
+
+#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \
+     ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \
+     rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_alpha_ref_t f;
+} rb_alpha_ref_u;
+
+
+/*
+ * RB_COLOR_MASK struct
+ */
+
+#define RB_COLOR_MASK_WRITE_RED_SIZE   1
+#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1
+#define RB_COLOR_MASK_WRITE_BLUE_SIZE  1
+#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COLOR_MASK_WRITE_RED_SHIFT  0
+#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1
+#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2
+#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3
+
+#define RB_COLOR_MASK_WRITE_RED_MASK   0x00000001
+#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002
+#define RB_COLOR_MASK_WRITE_BLUE_MASK  0x00000004
+#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008
+
+#define RB_COLOR_MASK_MASK \
+     (RB_COLOR_MASK_WRITE_RED_MASK | \
+      RB_COLOR_MASK_WRITE_GREEN_MASK | \
+      RB_COLOR_MASK_WRITE_BLUE_MASK | \
+      RB_COLOR_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha) \
+     ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \
+      (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \
+      (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \
+      (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 28;
+     } rb_color_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int                                : 28;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+     } rb_color_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_mask_t f;
+} rb_color_mask_u;
+
+
+/*
+ * RB_BLEND_RED struct
+ */
+
+#define RB_BLEND_RED_BLEND_RED_SIZE    8
+
+#define RB_BLEND_RED_BLEND_RED_SHIFT   0
+
+#define RB_BLEND_RED_BLEND_RED_MASK    0x000000ff
+
+#define RB_BLEND_RED_MASK \
+     (RB_BLEND_RED_BLEND_RED_MASK)
+
+#define RB_BLEND_RED(blend_red) \
+     ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT))
+
+#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \
+     ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \
+     rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_red_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int                                : 24;
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+     } rb_blend_red_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_red_t f;
+} rb_blend_red_u;
+
+
+/*
+ * RB_BLEND_GREEN struct
+ */
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0
+
+#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff
+
+#define RB_BLEND_GREEN_MASK \
+     (RB_BLEND_GREEN_BLEND_GREEN_MASK)
+
+#define RB_BLEND_GREEN(blend_green) \
+     ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT))
+
+#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \
+     ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \
+     rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_green_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int                                : 24;
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+     } rb_blend_green_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_green_t f;
+} rb_blend_green_u;
+
+
+/*
+ * RB_BLEND_BLUE struct
+ */
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SIZE  8
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0
+
+#define RB_BLEND_BLUE_BLEND_BLUE_MASK  0x000000ff
+
+#define RB_BLEND_BLUE_MASK \
+     (RB_BLEND_BLUE_BLEND_BLUE_MASK)
+
+#define RB_BLEND_BLUE(blend_blue) \
+     ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT))
+
+#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \
+     ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \
+     rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_blue_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int                                : 24;
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+     } rb_blend_blue_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_blue_t f;
+} rb_blend_blue_u;
+
+
+/*
+ * RB_BLEND_ALPHA struct
+ */
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff
+
+#define RB_BLEND_ALPHA_MASK \
+     (RB_BLEND_ALPHA_BLEND_ALPHA_MASK)
+
+#define RB_BLEND_ALPHA(blend_alpha) \
+     ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT))
+
+#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \
+     ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \
+     rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_alpha_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int                                : 24;
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+     } rb_blend_alpha_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_alpha_t f;
+} rb_blend_alpha_u;
+
+
+/*
+ * RB_FOG_COLOR struct
+ */
+
+#define RB_FOG_COLOR_FOG_RED_SIZE      8
+#define RB_FOG_COLOR_FOG_GREEN_SIZE    8
+#define RB_FOG_COLOR_FOG_BLUE_SIZE     8
+
+#define RB_FOG_COLOR_FOG_RED_SHIFT     0
+#define RB_FOG_COLOR_FOG_GREEN_SHIFT   8
+#define RB_FOG_COLOR_FOG_BLUE_SHIFT    16
+
+#define RB_FOG_COLOR_FOG_RED_MASK      0x000000ff
+#define RB_FOG_COLOR_FOG_GREEN_MASK    0x0000ff00
+#define RB_FOG_COLOR_FOG_BLUE_MASK     0x00ff0000
+
+#define RB_FOG_COLOR_MASK \
+     (RB_FOG_COLOR_FOG_RED_MASK | \
+      RB_FOG_COLOR_FOG_GREEN_MASK | \
+      RB_FOG_COLOR_FOG_BLUE_MASK)
+
+#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \
+     ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \
+      (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \
+      (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT))
+
+#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int                                : 8;
+     } rb_fog_color_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int                                : 8;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+     } rb_fog_color_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_fog_color_t f;
+} rb_fog_color_u;
+
+
+/*
+ * RB_STENCILREFMASK_BF struct
+ */
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000
+
+#define RB_STENCILREFMASK_BF_MASK \
+     (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK)
+
+#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf) \
+     ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \
+      (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \
+      (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT))
+
+#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+
+#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int                                : 8;
+     } rb_stencilrefmask_bf_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int                                : 8;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+     } rb_stencilrefmask_bf_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_bf_t f;
+} rb_stencilrefmask_bf_u;
+
+
+/*
+ * RB_DEPTHCONTROL struct
+ */
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_Z_ENABLE_SIZE  1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_ZFUNC_SIZE     3
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0
+#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3
+#define RB_DEPTHCONTROL_ZFUNC_SHIFT    4
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7
+#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8
+#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11
+#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14
+#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001
+#define RB_DEPTHCONTROL_Z_ENABLE_MASK  0x00000002
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008
+#define RB_DEPTHCONTROL_ZFUNC_MASK     0x00000070
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080
+#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700
+#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800
+#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000
+#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000
+
+#define RB_DEPTHCONTROL_MASK \
+     (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_ZFUNC_MASK | \
+      RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK)
+
+#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \
+     ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \
+      (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \
+      (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \
+      (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \
+      (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \
+      (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \
+      (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \
+      (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \
+      (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \
+      (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \
+      (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \
+      (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \
+      (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \
+      (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT))
+
+#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+     } rb_depthcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+     } rb_depthcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depthcontrol_t f;
+} rb_depthcontrol_u;
+
+
+/*
+ * RB_BLENDCONTROL struct
+ */
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1
+#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29
+#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000
+#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000
+
+#define RB_BLENDCONTROL_MASK \
+     (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_MASK)
+
+#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \
+     ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \
+      (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \
+      (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \
+      (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \
+      (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \
+      (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \
+      (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \
+      (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT))
+
+#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int                                : 1;
+     } rb_blendcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int                                : 1;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+     } rb_blendcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blendcontrol_t f;
+} rb_blendcontrol_u;
+
+
+/*
+ * RB_COLORCONTROL struct
+ */
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1
+#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1
+#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1
+#define RB_COLORCONTROL_ROP_CODE_SIZE  4
+#define RB_COLORCONTROL_DITHER_MODE_SIZE 2
+#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2
+#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4
+#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5
+#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7
+#define RB_COLORCONTROL_ROP_CODE_SHIFT 8
+#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12
+#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14
+#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30
+
+#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010
+#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020
+#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080
+#define RB_COLORCONTROL_ROP_CODE_MASK  0x00000f00
+#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000
+#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000
+#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000
+
+#define RB_COLORCONTROL_MASK \
+     (RB_COLORCONTROL_ALPHA_FUNC_MASK | \
+      RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \
+      RB_COLORCONTROL_BLEND_DISABLE_MASK | \
+      RB_COLORCONTROL_FOG_ENABLE_MASK | \
+      RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \
+      RB_COLORCONTROL_ROP_CODE_MASK | \
+      RB_COLORCONTROL_DITHER_MODE_MASK | \
+      RB_COLORCONTROL_DITHER_TYPE_MASK | \
+      RB_COLORCONTROL_PIXEL_FOG_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK)
+
+#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \
+     ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \
+      (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \
+      (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \
+      (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \
+      (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \
+      (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \
+      (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \
+      (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \
+      (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \
+      (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \
+      (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \
+      (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \
+      (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \
+      (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT))
+
+#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int                                : 7;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+     } rb_colorcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int                                : 7;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+     } rb_colorcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_colorcontrol_t f;
+} rb_colorcontrol_u;
+
+
+/*
+ * RB_MODECONTROL struct
+ */
+
+#define RB_MODECONTROL_EDRAM_MODE_SIZE 3
+
+#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0
+
+#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007
+
+#define RB_MODECONTROL_MASK \
+     (RB_MODECONTROL_EDRAM_MODE_MASK)
+
+#define RB_MODECONTROL(edram_mode) \
+     ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT))
+
+#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \
+     ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \
+     rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+          unsigned int                                : 29;
+     } rb_modecontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int                                : 29;
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+     } rb_modecontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_modecontrol_t f;
+} rb_modecontrol_u;
+
+
+/*
+ * RB_COLOR_DEST_MASK struct
+ */
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff
+
+#define RB_COLOR_DEST_MASK_MASK \
+     (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK)
+
+#define RB_COLOR_DEST_MASK(color_dest_mask) \
+     ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT))
+
+#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \
+     ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \
+     rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_dest_mask_t f;
+} rb_color_dest_mask_u;
+
+
+/*
+ * RB_COPY_CONTROL struct
+ */
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1
+#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3
+#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008
+#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0
+
+#define RB_COPY_CONTROL_MASK \
+     (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \
+      RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \
+      RB_COPY_CONTROL_CLEAR_MASK_MASK)
+
+#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \
+     ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \
+      (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \
+      (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT))
+
+#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int                                : 24;
+     } rb_copy_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int                                : 24;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+     } rb_copy_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_control_t f;
+} rb_copy_control_u;
+
+
+/*
+ * RB_COPY_DEST_BASE struct
+ */
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000
+
+#define RB_COPY_DEST_BASE_MASK \
+     (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK)
+
+#define RB_COPY_DEST_BASE(copy_dest_base) \
+     ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT))
+
+#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \
+     ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \
+     rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int                                : 12;
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+     } rb_copy_dest_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+          unsigned int                                : 12;
+     } rb_copy_dest_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_base_t f;
+} rb_copy_dest_base_u;
+
+
+/*
+ * RB_COPY_DEST_PITCH struct
+ */
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff
+
+#define RB_COPY_DEST_PITCH_MASK \
+     (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK)
+
+#define RB_COPY_DEST_PITCH(copy_dest_pitch) \
+     ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT))
+
+#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \
+     ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \
+     rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+          unsigned int                                : 23;
+     } rb_copy_dest_pitch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int                                : 23;
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+     } rb_copy_dest_pitch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pitch_t f;
+} rb_copy_dest_pitch_u;
+
+
+/*
+ * RB_COPY_DEST_INFO struct
+ */
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000
+
+#define RB_COPY_DEST_INFO_MASK \
+     (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \
+     ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \
+      (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \
+      (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \
+      (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \
+      (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \
+      (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \
+      (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \
+      (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \
+      (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \
+      (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 14;
+     } rb_copy_dest_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int                                : 14;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+     } rb_copy_dest_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_info_t f;
+} rb_copy_dest_info_u;
+
+
+/*
+ * RB_COPY_DEST_PIXEL_OFFSET struct
+ */
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000
+
+#define RB_COPY_DEST_PIXEL_OFFSET_MASK \
+     (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \
+      RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK)
+
+#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \
+     ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \
+      (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT))
+
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int                                : 6;
+     } rb_copy_dest_pixel_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int                                : 6;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+     } rb_copy_dest_pixel_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pixel_offset_t f;
+} rb_copy_dest_pixel_offset_u;
+
+
+/*
+ * RB_DEPTH_CLEAR struct
+ */
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff
+
+#define RB_DEPTH_CLEAR_MASK \
+     (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK)
+
+#define RB_DEPTH_CLEAR(depth_clear) \
+     ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT))
+
+#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \
+     ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \
+     rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_clear_t f;
+} rb_depth_clear_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_CTL struct
+ */
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002
+
+#define RB_SAMPLE_COUNT_CTL_MASK \
+     (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \
+      RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK)
+
+#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \
+     ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \
+      (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT))
+
+#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int                                : 30;
+     } rb_sample_count_ctl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int                                : 30;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+     } rb_sample_count_ctl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_ctl_t f;
+} rb_sample_count_ctl_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_ADDR struct
+ */
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff
+
+#define RB_SAMPLE_COUNT_ADDR_MASK \
+     (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK)
+
+#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \
+     ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT))
+
+#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \
+     ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \
+     rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_addr_t f;
+} rb_sample_count_addr_u;
+
+
+/*
+ * RB_BC_CONTROL struct
+ */
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1
+#define RB_BC_CONTROL_CRC_MODE_SIZE    1
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1
+#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_RESERVED9_SIZE   1
+#define RB_BC_CONTROL_RESERVED10_SIZE  1
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14
+#define RB_BC_CONTROL_CRC_MODE_SHIFT   15
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16
+#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29
+#define RB_BC_CONTROL_RESERVED9_SHIFT  30
+#define RB_BC_CONTROL_RESERVED10_SHIFT 31
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000
+#define RB_BC_CONTROL_CRC_MODE_MASK    0x00008000
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000
+#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000
+#define RB_BC_CONTROL_RESERVED9_MASK   0x40000000
+#define RB_BC_CONTROL_RESERVED10_MASK  0x80000000
+
+#define RB_BC_CONTROL_MASK \
+     (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \
+      RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \
+      RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \
+      RB_BC_CONTROL_CRC_MODE_MASK | \
+      RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \
+      RB_BC_CONTROL_DISABLE_ACCUM_MASK | \
+      RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \
+      RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_RESERVED9_MASK | \
+      RB_BC_CONTROL_RESERVED10_MASK)
+
+#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, reserved9, reserved10) \
+     ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \
+      (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \
+      (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \
+      (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \
+      (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \
+      (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \
+      (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \
+      (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \
+      (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \
+      (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \
+      (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \
+      (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \
+      (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \
+      (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \
+      (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \
+      (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \
+      (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \
+      (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT) | \
+      (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT))
+
+#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED9(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED9_MASK) >> RB_BC_CONTROL_RESERVED9_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED10(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED10_MASK) >> RB_BC_CONTROL_RESERVED10_SHIFT)
+
+#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED9(rb_bc_control_reg, reserved9) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED9_MASK) | (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED10(rb_bc_control_reg, reserved10) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED10_MASK) | (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int                                : 1;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int reserved9                      : RB_BC_CONTROL_RESERVED9_SIZE;
+          unsigned int reserved10                     : RB_BC_CONTROL_RESERVED10_SIZE;
+     } rb_bc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int reserved10                     : RB_BC_CONTROL_RESERVED10_SIZE;
+          unsigned int reserved9                      : RB_BC_CONTROL_RESERVED9_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+     } rb_bc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_control_t f;
+} rb_bc_control_u;
+
+
+/*
+ * RB_EDRAM_INFO struct
+ */
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE  4
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
+#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4
+#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_MASK  0x0000000f
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030
+#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000
+
+#define RB_EDRAM_INFO_MASK \
+     (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \
+      RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \
+      RB_EDRAM_INFO_EDRAM_RANGE_MASK)
+
+#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \
+     ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \
+      (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \
+      (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT))
+
+#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+     } rb_edram_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+     } rb_edram_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_edram_info_t f;
+} rb_edram_info_u;
+
+
+/*
+ * RB_CRC_RD_PORT struct
+ */
+
+#define RB_CRC_RD_PORT_CRC_DATA_SIZE   32
+
+#define RB_CRC_RD_PORT_CRC_DATA_SHIFT  0
+
+#define RB_CRC_RD_PORT_CRC_DATA_MASK   0xffffffff
+
+#define RB_CRC_RD_PORT_MASK \
+     (RB_CRC_RD_PORT_CRC_DATA_MASK)
+
+#define RB_CRC_RD_PORT(crc_data) \
+     ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT))
+
+#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \
+     ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \
+     rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_rd_port_t f;
+} rb_crc_rd_port_u;
+
+
+/*
+ * RB_CRC_CONTROL struct
+ */
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001
+
+#define RB_CRC_CONTROL_MASK \
+     (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK)
+
+#define RB_CRC_CONTROL(crc_rd_advance) \
+     ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT))
+
+#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \
+     ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \
+     rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+          unsigned int                                : 31;
+     } rb_crc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int                                : 31;
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+     } rb_crc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_control_t f;
+} rb_crc_control_u;
+
+
+/*
+ * RB_CRC_MASK struct
+ */
+
+#define RB_CRC_MASK_CRC_MASK_SIZE      32
+
+#define RB_CRC_MASK_CRC_MASK_SHIFT     0
+
+#define RB_CRC_MASK_CRC_MASK_MASK      0xffffffff
+
+#define RB_CRC_MASK_MASK \
+     (RB_CRC_MASK_CRC_MASK_MASK)
+
+#define RB_CRC_MASK(crc_mask) \
+     ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT))
+
+#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \
+     ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \
+     rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_mask_t f;
+} rb_crc_mask_u;
+
+
+/*
+ * RB_PERFCOUNTER0_SELECT struct
+ */
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define RB_PERFCOUNTER0_SELECT_MASK \
+     (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define RB_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \
+     ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \
+     rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } rb_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } rb_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_select_t f;
+} rb_perfcounter0_select_u;
+
+
+/*
+ * RB_PERFCOUNTER0_LOW struct
+ */
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define RB_PERFCOUNTER0_LOW_MASK \
+     (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \
+     ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \
+     rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_low_t f;
+} rb_perfcounter0_low_u;
+
+
+/*
+ * RB_PERFCOUNTER0_HI struct
+ */
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define RB_PERFCOUNTER0_HI_MASK \
+     (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \
+     ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \
+     rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } rb_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } rb_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_hi_t f;
+} rb_perfcounter0_hi_u;
+
+
+/*
+ * RB_TOTAL_SAMPLES struct
+ */
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff
+
+#define RB_TOTAL_SAMPLES_MASK \
+     (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK)
+
+#define RB_TOTAL_SAMPLES(total_samples) \
+     ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT))
+
+#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \
+     ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \
+     rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_total_samples_t f;
+} rb_total_samples_u;
+
+
+/*
+ * RB_ZPASS_SAMPLES struct
+ */
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff
+
+#define RB_ZPASS_SAMPLES_MASK \
+     (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK)
+
+#define RB_ZPASS_SAMPLES(zpass_samples) \
+     ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT))
+
+#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \
+     ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \
+     rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zpass_samples_t f;
+} rb_zpass_samples_u;
+
+
+/*
+ * RB_ZFAIL_SAMPLES struct
+ */
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_ZFAIL_SAMPLES_MASK \
+     (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK)
+
+#define RB_ZFAIL_SAMPLES(zfail_samples) \
+     ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT))
+
+#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \
+     ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \
+     rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zfail_samples_t f;
+} rb_zfail_samples_u;
+
+
+/*
+ * RB_SFAIL_SAMPLES struct
+ */
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_SFAIL_SAMPLES_MASK \
+     (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK)
+
+#define RB_SFAIL_SAMPLES(sfail_samples) \
+     ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT))
+
+#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \
+     ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \
+     rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sfail_samples_t f;
+} rb_sfail_samples_u;
+
+
+/*
+ * RB_DEBUG_0 struct
+ */
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE  1
+#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE  1
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1
+#define RB_DEBUG_0_C_REQ_FULL_SIZE     1
+#define RB_DEBUG_0_C_MASK_FULL_SIZE    1
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7
+#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8
+#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17
+#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18
+#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25
+#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26
+#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28
+#define RB_DEBUG_0_C_REQ_FULL_SHIFT    29
+#define RB_DEBUG_0_C_MASK_FULL_SHIFT   30
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020
+#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK  0x00000040
+#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK  0x00000080
+#define RB_DEBUG_0_RDREQ_C1_FULL_MASK  0x00000100
+#define RB_DEBUG_0_RDREQ_C0_FULL_MASK  0x00000200
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000
+#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK  0x00010000
+#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK  0x00020000
+#define RB_DEBUG_0_WRREQ_C1_FULL_MASK  0x00040000
+#define RB_DEBUG_0_WRREQ_C0_FULL_MASK  0x00080000
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000
+#define RB_DEBUG_0_C_SX_LAT_FULL_MASK  0x04000000
+#define RB_DEBUG_0_C_SX_CMD_FULL_MASK  0x08000000
+#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000
+#define RB_DEBUG_0_C_REQ_FULL_MASK     0x20000000
+#define RB_DEBUG_0_C_MASK_FULL_MASK    0x40000000
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000
+
+#define RB_DEBUG_0_MASK \
+     (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_C_SX_LAT_FULL_MASK | \
+      RB_DEBUG_0_C_SX_CMD_FULL_MASK | \
+      RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \
+      RB_DEBUG_0_C_REQ_FULL_MASK | \
+      RB_DEBUG_0_C_MASK_FULL_MASK | \
+      RB_DEBUG_0_EZ_INFSAMP_FULL_MASK)
+
+#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \
+     ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \
+      (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \
+      (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \
+      (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \
+      (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \
+      (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \
+      (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \
+      (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \
+      (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \
+      (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \
+      (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \
+      (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \
+      (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \
+      (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \
+      (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \
+      (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \
+      (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \
+      (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \
+      (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \
+      (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \
+      (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT))
+
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+     } rb_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+     } rb_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_0_t f;
+} rb_debug_0_u;
+
+
+/*
+ * RB_DEBUG_1 struct
+ */
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_REQ_EMPTY_SIZE    1
+#define RB_DEBUG_1_C_MASK_EMPTY_SIZE   1
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28
+#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT   29
+#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT  30
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000
+#define RB_DEBUG_1_C_REQ_EMPTY_MASK    0x20000000
+#define RB_DEBUG_1_C_MASK_EMPTY_MASK   0x40000000
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000
+
+#define RB_DEBUG_1_MASK \
+     (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \
+      RB_DEBUG_1_C_REQ_EMPTY_MASK | \
+      RB_DEBUG_1_C_MASK_EMPTY_MASK | \
+      RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK)
+
+#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \
+     ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \
+      (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \
+      (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \
+      (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \
+      (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \
+      (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \
+      (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \
+      (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \
+      (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \
+      (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \
+      (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \
+      (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \
+      (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \
+      (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \
+      (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \
+      (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \
+      (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \
+      (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \
+      (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \
+      (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \
+      (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT))
+
+#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_1_t f;
+} rb_debug_1_u;
+
+
+/*
+ * RB_DEBUG_2 struct
+ */
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z1_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z0_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z1_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z_SAMP_FULL_SIZE    1
+#define RB_DEBUG_2_Z_TILE_FULL_SIZE    1
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE   1
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16
+#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT  17
+#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT  18
+#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT   19
+#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT   20
+#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT   21
+#define RB_DEBUG_2_Z_TILE_FULL_SHIFT   22
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT  28
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT  29
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT  30
+#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT  31
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000
+#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000
+#define RB_DEBUG_2_Z0_MASK_FULL_MASK   0x00020000
+#define RB_DEBUG_2_Z1_MASK_FULL_MASK   0x00040000
+#define RB_DEBUG_2_Z0_REQ_FULL_MASK    0x00080000
+#define RB_DEBUG_2_Z1_REQ_FULL_MASK    0x00100000
+#define RB_DEBUG_2_Z_SAMP_FULL_MASK    0x00200000
+#define RB_DEBUG_2_Z_TILE_FULL_MASK    0x00400000
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK  0x04000000
+#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK  0x08000000
+#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK   0x10000000
+#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK   0x20000000
+#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK   0x40000000
+#define RB_DEBUG_2_Z_TILE_EMPTY_MASK   0x80000000
+
+#define RB_DEBUG_2_MASK \
+     (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \
+      RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \
+      RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \
+      RB_DEBUG_2_Z0_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z1_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z0_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z1_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z_SAMP_FULL_MASK | \
+      RB_DEBUG_2_Z_TILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \
+      RB_DEBUG_2_Z_TILE_EMPTY_MASK)
+
+#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \
+     ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \
+      (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \
+      (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \
+      (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \
+      (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \
+      (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \
+      (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \
+      (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \
+      (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \
+      (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \
+      (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \
+      (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \
+      (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \
+      (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \
+      (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \
+      (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \
+      (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \
+      (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \
+      (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \
+      (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \
+      (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \
+      (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \
+      (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT))
+
+#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+     } rb_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+     } rb_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_2_t f;
+} rb_debug_2_u;
+
+
+/*
+ * RB_DEBUG_3 struct
+ */
+
+#define RB_DEBUG_3_ACCUM_VALID_SIZE    4
+#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4
+#define RB_DEBUG_3_SHD_FULL_SIZE       1
+#define RB_DEBUG_3_SHD_EMPTY_SIZE      1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1
+
+#define RB_DEBUG_3_ACCUM_VALID_SHIFT   0
+#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15
+#define RB_DEBUG_3_SHD_FULL_SHIFT      19
+#define RB_DEBUG_3_SHD_EMPTY_SHIFT     20
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28
+
+#define RB_DEBUG_3_ACCUM_VALID_MASK    0x0000000f
+#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000
+#define RB_DEBUG_3_SHD_FULL_MASK       0x00080000
+#define RB_DEBUG_3_SHD_EMPTY_MASK      0x00100000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000
+
+#define RB_DEBUG_3_MASK \
+     (RB_DEBUG_3_ACCUM_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_FLUSHING_MASK | \
+      RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \
+      RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \
+      RB_DEBUG_3_SHD_FULL_MASK | \
+      RB_DEBUG_3_SHD_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_FULL_MASK)
+
+#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \
+     ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \
+      (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \
+      (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \
+      (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \
+      (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \
+      (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \
+      (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \
+      (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \
+      (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \
+      (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \
+      (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \
+      (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \
+      (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \
+      (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \
+      (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT))
+
+#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int                                : 3;
+     } rb_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int                                : 3;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+     } rb_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_3_t f;
+} rb_debug_3_u;
+
+
+/*
+ * RB_DEBUG_4 struct
+ */
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00
+
+#define RB_DEBUG_4_MASK \
+     (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \
+      RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \
+      RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK)
+
+#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \
+     ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \
+      (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \
+      (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \
+      (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \
+      (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \
+      (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT))
+
+#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int                                : 19;
+     } rb_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int                                : 19;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+     } rb_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_4_t f;
+} rb_debug_4_u;
+
+
+/*
+ * RB_FLAG_CONTROL struct
+ */
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001
+
+#define RB_FLAG_CONTROL_MASK \
+     (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK)
+
+#define RB_FLAG_CONTROL(debug_flag_clear) \
+     ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT))
+
+#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \
+     ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \
+     rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+          unsigned int                                : 31;
+     } rb_flag_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int                                : 31;
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+     } rb_flag_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_flag_control_t f;
+} rb_flag_control_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_ENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000
+
+#define BC_DUMMY_CRAYRB_ENUMS_MASK \
+     (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK)
+
+#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \
+     ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \
+      (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \
+      (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \
+      (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \
+      (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \
+      (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \
+      (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT))
+
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_enums_t f;
+} bc_dummy_crayrb_enums_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_MOREENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \
+     (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \
+     ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT))
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \
+     ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \
+     bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+          unsigned int                                : 30;
+     } bc_dummy_crayrb_moreenums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int                                : 30;
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+     } bc_dummy_crayrb_moreenums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_moreenums_t f;
+} bc_dummy_crayrb_moreenums_u;
+
+
+#endif
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h
new file mode 100644
index 00000000000..1feebebda05
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h
@@ -0,0 +1,540 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_TYPEDEF_HEADER)
+#define _yamato_TYPEDEF_HEADER
+
+#include "yamato_registers.h"
+
+typedef union PA_CL_VPORT_XSCALE                regPA_CL_VPORT_XSCALE;
+typedef union PA_CL_VPORT_XOFFSET               regPA_CL_VPORT_XOFFSET;
+typedef union PA_CL_VPORT_YSCALE                regPA_CL_VPORT_YSCALE;
+typedef union PA_CL_VPORT_YOFFSET               regPA_CL_VPORT_YOFFSET;
+typedef union PA_CL_VPORT_ZSCALE                regPA_CL_VPORT_ZSCALE;
+typedef union PA_CL_VPORT_ZOFFSET               regPA_CL_VPORT_ZOFFSET;
+typedef union PA_CL_VTE_CNTL                    regPA_CL_VTE_CNTL;
+typedef union PA_CL_CLIP_CNTL                   regPA_CL_CLIP_CNTL;
+typedef union PA_CL_GB_VERT_CLIP_ADJ            regPA_CL_GB_VERT_CLIP_ADJ;
+typedef union PA_CL_GB_VERT_DISC_ADJ            regPA_CL_GB_VERT_DISC_ADJ;
+typedef union PA_CL_GB_HORZ_CLIP_ADJ            regPA_CL_GB_HORZ_CLIP_ADJ;
+typedef union PA_CL_GB_HORZ_DISC_ADJ            regPA_CL_GB_HORZ_DISC_ADJ;
+typedef union PA_CL_ENHANCE                     regPA_CL_ENHANCE;
+typedef union PA_SC_ENHANCE                     regPA_SC_ENHANCE;
+typedef union PA_SU_VTX_CNTL                    regPA_SU_VTX_CNTL;
+typedef union PA_SU_POINT_SIZE                  regPA_SU_POINT_SIZE;
+typedef union PA_SU_POINT_MINMAX                regPA_SU_POINT_MINMAX;
+typedef union PA_SU_LINE_CNTL                   regPA_SU_LINE_CNTL;
+typedef union PA_SU_SC_MODE_CNTL                regPA_SU_SC_MODE_CNTL;
+typedef union PA_SU_POLY_OFFSET_FRONT_SCALE     regPA_SU_POLY_OFFSET_FRONT_SCALE;
+typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET    regPA_SU_POLY_OFFSET_FRONT_OFFSET;
+typedef union PA_SU_POLY_OFFSET_BACK_SCALE      regPA_SU_POLY_OFFSET_BACK_SCALE;
+typedef union PA_SU_POLY_OFFSET_BACK_OFFSET     regPA_SU_POLY_OFFSET_BACK_OFFSET;
+typedef union PA_SU_PERFCOUNTER0_SELECT         regPA_SU_PERFCOUNTER0_SELECT;
+typedef union PA_SU_PERFCOUNTER1_SELECT         regPA_SU_PERFCOUNTER1_SELECT;
+typedef union PA_SU_PERFCOUNTER2_SELECT         regPA_SU_PERFCOUNTER2_SELECT;
+typedef union PA_SU_PERFCOUNTER3_SELECT         regPA_SU_PERFCOUNTER3_SELECT;
+typedef union PA_SU_PERFCOUNTER0_LOW            regPA_SU_PERFCOUNTER0_LOW;
+typedef union PA_SU_PERFCOUNTER0_HI             regPA_SU_PERFCOUNTER0_HI;
+typedef union PA_SU_PERFCOUNTER1_LOW            regPA_SU_PERFCOUNTER1_LOW;
+typedef union PA_SU_PERFCOUNTER1_HI             regPA_SU_PERFCOUNTER1_HI;
+typedef union PA_SU_PERFCOUNTER2_LOW            regPA_SU_PERFCOUNTER2_LOW;
+typedef union PA_SU_PERFCOUNTER2_HI             regPA_SU_PERFCOUNTER2_HI;
+typedef union PA_SU_PERFCOUNTER3_LOW            regPA_SU_PERFCOUNTER3_LOW;
+typedef union PA_SU_PERFCOUNTER3_HI             regPA_SU_PERFCOUNTER3_HI;
+typedef union PA_SC_WINDOW_OFFSET               regPA_SC_WINDOW_OFFSET;
+typedef union PA_SC_AA_CONFIG                   regPA_SC_AA_CONFIG;
+typedef union PA_SC_AA_MASK                     regPA_SC_AA_MASK;
+typedef union PA_SC_LINE_STIPPLE                regPA_SC_LINE_STIPPLE;
+typedef union PA_SC_LINE_CNTL                   regPA_SC_LINE_CNTL;
+typedef union PA_SC_WINDOW_SCISSOR_TL           regPA_SC_WINDOW_SCISSOR_TL;
+typedef union PA_SC_WINDOW_SCISSOR_BR           regPA_SC_WINDOW_SCISSOR_BR;
+typedef union PA_SC_SCREEN_SCISSOR_TL           regPA_SC_SCREEN_SCISSOR_TL;
+typedef union PA_SC_SCREEN_SCISSOR_BR           regPA_SC_SCREEN_SCISSOR_BR;
+typedef union PA_SC_VIZ_QUERY                   regPA_SC_VIZ_QUERY;
+typedef union PA_SC_VIZ_QUERY_STATUS            regPA_SC_VIZ_QUERY_STATUS;
+typedef union PA_SC_LINE_STIPPLE_STATE          regPA_SC_LINE_STIPPLE_STATE;
+typedef union PA_SC_PERFCOUNTER0_SELECT         regPA_SC_PERFCOUNTER0_SELECT;
+typedef union PA_SC_PERFCOUNTER0_LOW            regPA_SC_PERFCOUNTER0_LOW;
+typedef union PA_SC_PERFCOUNTER0_HI             regPA_SC_PERFCOUNTER0_HI;
+typedef union PA_CL_CNTL_STATUS                 regPA_CL_CNTL_STATUS;
+typedef union PA_SU_CNTL_STATUS                 regPA_SU_CNTL_STATUS;
+typedef union PA_SC_CNTL_STATUS                 regPA_SC_CNTL_STATUS;
+typedef union PA_SU_DEBUG_CNTL                  regPA_SU_DEBUG_CNTL;
+typedef union PA_SU_DEBUG_DATA                  regPA_SU_DEBUG_DATA;
+typedef union PA_SC_DEBUG_CNTL                  regPA_SC_DEBUG_CNTL;
+typedef union PA_SC_DEBUG_DATA                  regPA_SC_DEBUG_DATA;
+typedef union GFX_COPY_STATE                    regGFX_COPY_STATE;
+typedef union VGT_DRAW_INITIATOR                regVGT_DRAW_INITIATOR;
+typedef union VGT_EVENT_INITIATOR               regVGT_EVENT_INITIATOR;
+typedef union VGT_DMA_BASE                      regVGT_DMA_BASE;
+typedef union VGT_DMA_SIZE                      regVGT_DMA_SIZE;
+typedef union VGT_BIN_BASE                      regVGT_BIN_BASE;
+typedef union VGT_BIN_SIZE                      regVGT_BIN_SIZE;
+typedef union VGT_CURRENT_BIN_ID_MIN            regVGT_CURRENT_BIN_ID_MIN;
+typedef union VGT_CURRENT_BIN_ID_MAX            regVGT_CURRENT_BIN_ID_MAX;
+typedef union VGT_IMMED_DATA                    regVGT_IMMED_DATA;
+typedef union VGT_MAX_VTX_INDX                  regVGT_MAX_VTX_INDX;
+typedef union VGT_MIN_VTX_INDX                  regVGT_MIN_VTX_INDX;
+typedef union VGT_INDX_OFFSET                   regVGT_INDX_OFFSET;
+typedef union VGT_VERTEX_REUSE_BLOCK_CNTL       regVGT_VERTEX_REUSE_BLOCK_CNTL;
+typedef union VGT_OUT_DEALLOC_CNTL              regVGT_OUT_DEALLOC_CNTL;
+typedef union VGT_MULTI_PRIM_IB_RESET_INDX      regVGT_MULTI_PRIM_IB_RESET_INDX;
+typedef union VGT_ENHANCE                       regVGT_ENHANCE;
+typedef union VGT_VTX_VECT_EJECT_REG            regVGT_VTX_VECT_EJECT_REG;
+typedef union VGT_LAST_COPY_STATE               regVGT_LAST_COPY_STATE;
+typedef union VGT_DEBUG_CNTL                    regVGT_DEBUG_CNTL;
+typedef union VGT_DEBUG_DATA                    regVGT_DEBUG_DATA;
+typedef union VGT_CNTL_STATUS                   regVGT_CNTL_STATUS;
+typedef union VGT_CRC_SQ_DATA                   regVGT_CRC_SQ_DATA;
+typedef union VGT_CRC_SQ_CTRL                   regVGT_CRC_SQ_CTRL;
+typedef union VGT_PERFCOUNTER0_SELECT           regVGT_PERFCOUNTER0_SELECT;
+typedef union VGT_PERFCOUNTER1_SELECT           regVGT_PERFCOUNTER1_SELECT;
+typedef union VGT_PERFCOUNTER2_SELECT           regVGT_PERFCOUNTER2_SELECT;
+typedef union VGT_PERFCOUNTER3_SELECT           regVGT_PERFCOUNTER3_SELECT;
+typedef union VGT_PERFCOUNTER0_LOW              regVGT_PERFCOUNTER0_LOW;
+typedef union VGT_PERFCOUNTER1_LOW              regVGT_PERFCOUNTER1_LOW;
+typedef union VGT_PERFCOUNTER2_LOW              regVGT_PERFCOUNTER2_LOW;
+typedef union VGT_PERFCOUNTER3_LOW              regVGT_PERFCOUNTER3_LOW;
+typedef union VGT_PERFCOUNTER0_HI               regVGT_PERFCOUNTER0_HI;
+typedef union VGT_PERFCOUNTER1_HI               regVGT_PERFCOUNTER1_HI;
+typedef union VGT_PERFCOUNTER2_HI               regVGT_PERFCOUNTER2_HI;
+typedef union VGT_PERFCOUNTER3_HI               regVGT_PERFCOUNTER3_HI;
+typedef union TC_CNTL_STATUS                    regTC_CNTL_STATUS;
+typedef union TCR_CHICKEN                       regTCR_CHICKEN;
+typedef union TCF_CHICKEN                       regTCF_CHICKEN;
+typedef union TCM_CHICKEN                       regTCM_CHICKEN;
+typedef union TCR_PERFCOUNTER0_SELECT           regTCR_PERFCOUNTER0_SELECT;
+typedef union TCR_PERFCOUNTER1_SELECT           regTCR_PERFCOUNTER1_SELECT;
+typedef union TCR_PERFCOUNTER0_HI               regTCR_PERFCOUNTER0_HI;
+typedef union TCR_PERFCOUNTER1_HI               regTCR_PERFCOUNTER1_HI;
+typedef union TCR_PERFCOUNTER0_LOW              regTCR_PERFCOUNTER0_LOW;
+typedef union TCR_PERFCOUNTER1_LOW              regTCR_PERFCOUNTER1_LOW;
+typedef union TP_TC_CLKGATE_CNTL                regTP_TC_CLKGATE_CNTL;
+typedef union TPC_CNTL_STATUS                   regTPC_CNTL_STATUS;
+typedef union TPC_DEBUG0                        regTPC_DEBUG0;
+typedef union TPC_DEBUG1                        regTPC_DEBUG1;
+typedef union TPC_CHICKEN                       regTPC_CHICKEN;
+typedef union TP0_CNTL_STATUS                   regTP0_CNTL_STATUS;
+typedef union TP0_DEBUG                         regTP0_DEBUG;
+typedef union TP0_CHICKEN                       regTP0_CHICKEN;
+typedef union TP0_PERFCOUNTER0_SELECT           regTP0_PERFCOUNTER0_SELECT;
+typedef union TP0_PERFCOUNTER0_HI               regTP0_PERFCOUNTER0_HI;
+typedef union TP0_PERFCOUNTER0_LOW              regTP0_PERFCOUNTER0_LOW;
+typedef union TP0_PERFCOUNTER1_SELECT           regTP0_PERFCOUNTER1_SELECT;
+typedef union TP0_PERFCOUNTER1_HI               regTP0_PERFCOUNTER1_HI;
+typedef union TP0_PERFCOUNTER1_LOW              regTP0_PERFCOUNTER1_LOW;
+typedef union TCM_PERFCOUNTER0_SELECT           regTCM_PERFCOUNTER0_SELECT;
+typedef union TCM_PERFCOUNTER1_SELECT           regTCM_PERFCOUNTER1_SELECT;
+typedef union TCM_PERFCOUNTER0_HI               regTCM_PERFCOUNTER0_HI;
+typedef union TCM_PERFCOUNTER1_HI               regTCM_PERFCOUNTER1_HI;
+typedef union TCM_PERFCOUNTER0_LOW              regTCM_PERFCOUNTER0_LOW;
+typedef union TCM_PERFCOUNTER1_LOW              regTCM_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER0_SELECT           regTCF_PERFCOUNTER0_SELECT;
+typedef union TCF_PERFCOUNTER1_SELECT           regTCF_PERFCOUNTER1_SELECT;
+typedef union TCF_PERFCOUNTER2_SELECT           regTCF_PERFCOUNTER2_SELECT;
+typedef union TCF_PERFCOUNTER3_SELECT           regTCF_PERFCOUNTER3_SELECT;
+typedef union TCF_PERFCOUNTER4_SELECT           regTCF_PERFCOUNTER4_SELECT;
+typedef union TCF_PERFCOUNTER5_SELECT           regTCF_PERFCOUNTER5_SELECT;
+typedef union TCF_PERFCOUNTER6_SELECT           regTCF_PERFCOUNTER6_SELECT;
+typedef union TCF_PERFCOUNTER7_SELECT           regTCF_PERFCOUNTER7_SELECT;
+typedef union TCF_PERFCOUNTER8_SELECT           regTCF_PERFCOUNTER8_SELECT;
+typedef union TCF_PERFCOUNTER9_SELECT           regTCF_PERFCOUNTER9_SELECT;
+typedef union TCF_PERFCOUNTER10_SELECT          regTCF_PERFCOUNTER10_SELECT;
+typedef union TCF_PERFCOUNTER11_SELECT          regTCF_PERFCOUNTER11_SELECT;
+typedef union TCF_PERFCOUNTER0_HI               regTCF_PERFCOUNTER0_HI;
+typedef union TCF_PERFCOUNTER1_HI               regTCF_PERFCOUNTER1_HI;
+typedef union TCF_PERFCOUNTER2_HI               regTCF_PERFCOUNTER2_HI;
+typedef union TCF_PERFCOUNTER3_HI               regTCF_PERFCOUNTER3_HI;
+typedef union TCF_PERFCOUNTER4_HI               regTCF_PERFCOUNTER4_HI;
+typedef union TCF_PERFCOUNTER5_HI               regTCF_PERFCOUNTER5_HI;
+typedef union TCF_PERFCOUNTER6_HI               regTCF_PERFCOUNTER6_HI;
+typedef union TCF_PERFCOUNTER7_HI               regTCF_PERFCOUNTER7_HI;
+typedef union TCF_PERFCOUNTER8_HI               regTCF_PERFCOUNTER8_HI;
+typedef union TCF_PERFCOUNTER9_HI               regTCF_PERFCOUNTER9_HI;
+typedef union TCF_PERFCOUNTER10_HI              regTCF_PERFCOUNTER10_HI;
+typedef union TCF_PERFCOUNTER11_HI              regTCF_PERFCOUNTER11_HI;
+typedef union TCF_PERFCOUNTER0_LOW              regTCF_PERFCOUNTER0_LOW;
+typedef union TCF_PERFCOUNTER1_LOW              regTCF_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER2_LOW              regTCF_PERFCOUNTER2_LOW;
+typedef union TCF_PERFCOUNTER3_LOW              regTCF_PERFCOUNTER3_LOW;
+typedef union TCF_PERFCOUNTER4_LOW              regTCF_PERFCOUNTER4_LOW;
+typedef union TCF_PERFCOUNTER5_LOW              regTCF_PERFCOUNTER5_LOW;
+typedef union TCF_PERFCOUNTER6_LOW              regTCF_PERFCOUNTER6_LOW;
+typedef union TCF_PERFCOUNTER7_LOW              regTCF_PERFCOUNTER7_LOW;
+typedef union TCF_PERFCOUNTER8_LOW              regTCF_PERFCOUNTER8_LOW;
+typedef union TCF_PERFCOUNTER9_LOW              regTCF_PERFCOUNTER9_LOW;
+typedef union TCF_PERFCOUNTER10_LOW             regTCF_PERFCOUNTER10_LOW;
+typedef union TCF_PERFCOUNTER11_LOW             regTCF_PERFCOUNTER11_LOW;
+typedef union TCF_DEBUG                         regTCF_DEBUG;
+typedef union TCA_FIFO_DEBUG                    regTCA_FIFO_DEBUG;
+typedef union TCA_PROBE_DEBUG                   regTCA_PROBE_DEBUG;
+typedef union TCA_TPC_DEBUG                     regTCA_TPC_DEBUG;
+typedef union TCB_CORE_DEBUG                    regTCB_CORE_DEBUG;
+typedef union TCB_TAG0_DEBUG                    regTCB_TAG0_DEBUG;
+typedef union TCB_TAG1_DEBUG                    regTCB_TAG1_DEBUG;
+typedef union TCB_TAG2_DEBUG                    regTCB_TAG2_DEBUG;
+typedef union TCB_TAG3_DEBUG                    regTCB_TAG3_DEBUG;
+typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG;
+typedef union TCB_FETCH_GEN_WALKER_DEBUG        regTCB_FETCH_GEN_WALKER_DEBUG;
+typedef union TCB_FETCH_GEN_PIPE0_DEBUG         regTCB_FETCH_GEN_PIPE0_DEBUG;
+typedef union TCD_INPUT0_DEBUG                  regTCD_INPUT0_DEBUG;
+typedef union TCD_DEGAMMA_DEBUG                 regTCD_DEGAMMA_DEBUG;
+typedef union TCD_DXTMUX_SCTARB_DEBUG           regTCD_DXTMUX_SCTARB_DEBUG;
+typedef union TCD_DXTC_ARB_DEBUG                regTCD_DXTC_ARB_DEBUG;
+typedef union TCD_STALLS_DEBUG                  regTCD_STALLS_DEBUG;
+typedef union TCO_STALLS_DEBUG                  regTCO_STALLS_DEBUG;
+typedef union TCO_QUAD0_DEBUG0                  regTCO_QUAD0_DEBUG0;
+typedef union TCO_QUAD0_DEBUG1                  regTCO_QUAD0_DEBUG1;
+typedef union SQ_GPR_MANAGEMENT                 regSQ_GPR_MANAGEMENT;
+typedef union SQ_FLOW_CONTROL                   regSQ_FLOW_CONTROL;
+typedef union SQ_INST_STORE_MANAGMENT           regSQ_INST_STORE_MANAGMENT;
+typedef union SQ_RESOURCE_MANAGMENT             regSQ_RESOURCE_MANAGMENT;
+typedef union SQ_EO_RT                          regSQ_EO_RT;
+typedef union SQ_DEBUG_MISC                     regSQ_DEBUG_MISC;
+typedef union SQ_ACTIVITY_METER_CNTL            regSQ_ACTIVITY_METER_CNTL;
+typedef union SQ_ACTIVITY_METER_STATUS          regSQ_ACTIVITY_METER_STATUS;
+typedef union SQ_INPUT_ARB_PRIORITY             regSQ_INPUT_ARB_PRIORITY;
+typedef union SQ_THREAD_ARB_PRIORITY            regSQ_THREAD_ARB_PRIORITY;
+typedef union SQ_DEBUG_INPUT_FSM                regSQ_DEBUG_INPUT_FSM;
+typedef union SQ_DEBUG_CONST_MGR_FSM            regSQ_DEBUG_CONST_MGR_FSM;
+typedef union SQ_DEBUG_TP_FSM                   regSQ_DEBUG_TP_FSM;
+typedef union SQ_DEBUG_FSM_ALU_0                regSQ_DEBUG_FSM_ALU_0;
+typedef union SQ_DEBUG_FSM_ALU_1                regSQ_DEBUG_FSM_ALU_1;
+typedef union SQ_DEBUG_EXP_ALLOC                regSQ_DEBUG_EXP_ALLOC;
+typedef union SQ_DEBUG_PTR_BUFF                 regSQ_DEBUG_PTR_BUFF;
+typedef union SQ_DEBUG_GPR_VTX                  regSQ_DEBUG_GPR_VTX;
+typedef union SQ_DEBUG_GPR_PIX                  regSQ_DEBUG_GPR_PIX;
+typedef union SQ_DEBUG_TB_STATUS_SEL            regSQ_DEBUG_TB_STATUS_SEL;
+typedef union SQ_DEBUG_VTX_TB_0                 regSQ_DEBUG_VTX_TB_0;
+typedef union SQ_DEBUG_VTX_TB_1                 regSQ_DEBUG_VTX_TB_1;
+typedef union SQ_DEBUG_VTX_TB_STATUS_REG        regSQ_DEBUG_VTX_TB_STATUS_REG;
+typedef union SQ_DEBUG_VTX_TB_STATE_MEM         regSQ_DEBUG_VTX_TB_STATE_MEM;
+typedef union SQ_DEBUG_PIX_TB_0                 regSQ_DEBUG_PIX_TB_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0      regSQ_DEBUG_PIX_TB_STATUS_REG_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1      regSQ_DEBUG_PIX_TB_STATUS_REG_1;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2      regSQ_DEBUG_PIX_TB_STATUS_REG_2;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3      regSQ_DEBUG_PIX_TB_STATUS_REG_3;
+typedef union SQ_DEBUG_PIX_TB_STATE_MEM         regSQ_DEBUG_PIX_TB_STATE_MEM;
+typedef union SQ_PERFCOUNTER0_SELECT            regSQ_PERFCOUNTER0_SELECT;
+typedef union SQ_PERFCOUNTER1_SELECT            regSQ_PERFCOUNTER1_SELECT;
+typedef union SQ_PERFCOUNTER2_SELECT            regSQ_PERFCOUNTER2_SELECT;
+typedef union SQ_PERFCOUNTER3_SELECT            regSQ_PERFCOUNTER3_SELECT;
+typedef union SQ_PERFCOUNTER0_LOW               regSQ_PERFCOUNTER0_LOW;
+typedef union SQ_PERFCOUNTER0_HI                regSQ_PERFCOUNTER0_HI;
+typedef union SQ_PERFCOUNTER1_LOW               regSQ_PERFCOUNTER1_LOW;
+typedef union SQ_PERFCOUNTER1_HI                regSQ_PERFCOUNTER1_HI;
+typedef union SQ_PERFCOUNTER2_LOW               regSQ_PERFCOUNTER2_LOW;
+typedef union SQ_PERFCOUNTER2_HI                regSQ_PERFCOUNTER2_HI;
+typedef union SQ_PERFCOUNTER3_LOW               regSQ_PERFCOUNTER3_LOW;
+typedef union SQ_PERFCOUNTER3_HI                regSQ_PERFCOUNTER3_HI;
+typedef union SX_PERFCOUNTER0_SELECT            regSX_PERFCOUNTER0_SELECT;
+typedef union SX_PERFCOUNTER0_LOW               regSX_PERFCOUNTER0_LOW;
+typedef union SX_PERFCOUNTER0_HI                regSX_PERFCOUNTER0_HI;
+typedef union SQ_INSTRUCTION_ALU_0              regSQ_INSTRUCTION_ALU_0;
+typedef union SQ_INSTRUCTION_ALU_1              regSQ_INSTRUCTION_ALU_1;
+typedef union SQ_INSTRUCTION_ALU_2              regSQ_INSTRUCTION_ALU_2;
+typedef union SQ_INSTRUCTION_CF_EXEC_0          regSQ_INSTRUCTION_CF_EXEC_0;
+typedef union SQ_INSTRUCTION_CF_EXEC_1          regSQ_INSTRUCTION_CF_EXEC_1;
+typedef union SQ_INSTRUCTION_CF_EXEC_2          regSQ_INSTRUCTION_CF_EXEC_2;
+typedef union SQ_INSTRUCTION_CF_LOOP_0          regSQ_INSTRUCTION_CF_LOOP_0;
+typedef union SQ_INSTRUCTION_CF_LOOP_1          regSQ_INSTRUCTION_CF_LOOP_1;
+typedef union SQ_INSTRUCTION_CF_LOOP_2          regSQ_INSTRUCTION_CF_LOOP_2;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_0      regSQ_INSTRUCTION_CF_JMP_CALL_0;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_1      regSQ_INSTRUCTION_CF_JMP_CALL_1;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_2      regSQ_INSTRUCTION_CF_JMP_CALL_2;
+typedef union SQ_INSTRUCTION_CF_ALLOC_0         regSQ_INSTRUCTION_CF_ALLOC_0;
+typedef union SQ_INSTRUCTION_CF_ALLOC_1         regSQ_INSTRUCTION_CF_ALLOC_1;
+typedef union SQ_INSTRUCTION_CF_ALLOC_2         regSQ_INSTRUCTION_CF_ALLOC_2;
+typedef union SQ_INSTRUCTION_TFETCH_0           regSQ_INSTRUCTION_TFETCH_0;
+typedef union SQ_INSTRUCTION_TFETCH_1           regSQ_INSTRUCTION_TFETCH_1;
+typedef union SQ_INSTRUCTION_TFETCH_2           regSQ_INSTRUCTION_TFETCH_2;
+typedef union SQ_INSTRUCTION_VFETCH_0           regSQ_INSTRUCTION_VFETCH_0;
+typedef union SQ_INSTRUCTION_VFETCH_1           regSQ_INSTRUCTION_VFETCH_1;
+typedef union SQ_INSTRUCTION_VFETCH_2           regSQ_INSTRUCTION_VFETCH_2;
+typedef union SQ_CONSTANT_0                     regSQ_CONSTANT_0;
+typedef union SQ_CONSTANT_1                     regSQ_CONSTANT_1;
+typedef union SQ_CONSTANT_2                     regSQ_CONSTANT_2;
+typedef union SQ_CONSTANT_3                     regSQ_CONSTANT_3;
+typedef union SQ_FETCH_0                        regSQ_FETCH_0;
+typedef union SQ_FETCH_1                        regSQ_FETCH_1;
+typedef union SQ_FETCH_2                        regSQ_FETCH_2;
+typedef union SQ_FETCH_3                        regSQ_FETCH_3;
+typedef union SQ_FETCH_4                        regSQ_FETCH_4;
+typedef union SQ_FETCH_5                        regSQ_FETCH_5;
+typedef union SQ_CONSTANT_VFETCH_0              regSQ_CONSTANT_VFETCH_0;
+typedef union SQ_CONSTANT_VFETCH_1              regSQ_CONSTANT_VFETCH_1;
+typedef union SQ_CONSTANT_T2                    regSQ_CONSTANT_T2;
+typedef union SQ_CONSTANT_T3                    regSQ_CONSTANT_T3;
+typedef union SQ_CF_BOOLEANS                    regSQ_CF_BOOLEANS;
+typedef union SQ_CF_LOOP                        regSQ_CF_LOOP;
+typedef union SQ_CONSTANT_RT_0                  regSQ_CONSTANT_RT_0;
+typedef union SQ_CONSTANT_RT_1                  regSQ_CONSTANT_RT_1;
+typedef union SQ_CONSTANT_RT_2                  regSQ_CONSTANT_RT_2;
+typedef union SQ_CONSTANT_RT_3                  regSQ_CONSTANT_RT_3;
+typedef union SQ_FETCH_RT_0                     regSQ_FETCH_RT_0;
+typedef union SQ_FETCH_RT_1                     regSQ_FETCH_RT_1;
+typedef union SQ_FETCH_RT_2                     regSQ_FETCH_RT_2;
+typedef union SQ_FETCH_RT_3                     regSQ_FETCH_RT_3;
+typedef union SQ_FETCH_RT_4                     regSQ_FETCH_RT_4;
+typedef union SQ_FETCH_RT_5                     regSQ_FETCH_RT_5;
+typedef union SQ_CF_RT_BOOLEANS                 regSQ_CF_RT_BOOLEANS;
+typedef union SQ_CF_RT_LOOP                     regSQ_CF_RT_LOOP;
+typedef union SQ_VS_PROGRAM                     regSQ_VS_PROGRAM;
+typedef union SQ_PS_PROGRAM                     regSQ_PS_PROGRAM;
+typedef union SQ_CF_PROGRAM_SIZE                regSQ_CF_PROGRAM_SIZE;
+typedef union SQ_INTERPOLATOR_CNTL              regSQ_INTERPOLATOR_CNTL;
+typedef union SQ_PROGRAM_CNTL                   regSQ_PROGRAM_CNTL;
+typedef union SQ_WRAPPING_0                     regSQ_WRAPPING_0;
+typedef union SQ_WRAPPING_1                     regSQ_WRAPPING_1;
+typedef union SQ_VS_CONST                       regSQ_VS_CONST;
+typedef union SQ_PS_CONST                       regSQ_PS_CONST;
+typedef union SQ_CONTEXT_MISC                   regSQ_CONTEXT_MISC;
+typedef union SQ_CF_RD_BASE                     regSQ_CF_RD_BASE;
+typedef union SQ_DEBUG_MISC_0                   regSQ_DEBUG_MISC_0;
+typedef union SQ_DEBUG_MISC_1                   regSQ_DEBUG_MISC_1;
+typedef union MH_ARBITER_CONFIG                 regMH_ARBITER_CONFIG;
+typedef union MH_CLNT_AXI_ID_REUSE              regMH_CLNT_AXI_ID_REUSE;
+typedef union MH_INTERRUPT_MASK                 regMH_INTERRUPT_MASK;
+typedef union MH_INTERRUPT_STATUS               regMH_INTERRUPT_STATUS;
+typedef union MH_INTERRUPT_CLEAR                regMH_INTERRUPT_CLEAR;
+typedef union MH_AXI_ERROR                      regMH_AXI_ERROR;
+typedef union MH_PERFCOUNTER0_SELECT            regMH_PERFCOUNTER0_SELECT;
+typedef union MH_PERFCOUNTER1_SELECT            regMH_PERFCOUNTER1_SELECT;
+typedef union MH_PERFCOUNTER0_CONFIG            regMH_PERFCOUNTER0_CONFIG;
+typedef union MH_PERFCOUNTER1_CONFIG            regMH_PERFCOUNTER1_CONFIG;
+typedef union MH_PERFCOUNTER0_LOW               regMH_PERFCOUNTER0_LOW;
+typedef union MH_PERFCOUNTER1_LOW               regMH_PERFCOUNTER1_LOW;
+typedef union MH_PERFCOUNTER0_HI                regMH_PERFCOUNTER0_HI;
+typedef union MH_PERFCOUNTER1_HI                regMH_PERFCOUNTER1_HI;
+typedef union MH_DEBUG_CTRL                     regMH_DEBUG_CTRL;
+typedef union MH_DEBUG_DATA                     regMH_DEBUG_DATA;
+typedef union MH_MMU_CONFIG                     regMH_MMU_CONFIG;
+typedef union MH_MMU_VA_RANGE                   regMH_MMU_VA_RANGE;
+typedef union MH_MMU_PT_BASE                    regMH_MMU_PT_BASE;
+typedef union MH_MMU_PAGE_FAULT                 regMH_MMU_PAGE_FAULT;
+typedef union MH_MMU_TRAN_ERROR                 regMH_MMU_TRAN_ERROR;
+typedef union MH_MMU_INVALIDATE                 regMH_MMU_INVALIDATE;
+typedef union MH_MMU_MPU_BASE                   regMH_MMU_MPU_BASE;
+typedef union MH_MMU_MPU_END                    regMH_MMU_MPU_END;
+typedef union WAIT_UNTIL                        regWAIT_UNTIL;
+typedef union RBBM_ISYNC_CNTL                   regRBBM_ISYNC_CNTL;
+typedef union RBBM_STATUS                       regRBBM_STATUS;
+typedef union RBBM_DSPLY                        regRBBM_DSPLY;
+typedef union RBBM_RENDER_LATEST                regRBBM_RENDER_LATEST;
+typedef union RBBM_RTL_RELEASE                  regRBBM_RTL_RELEASE;
+typedef union RBBM_PATCH_RELEASE                regRBBM_PATCH_RELEASE;
+typedef union RBBM_AUXILIARY_CONFIG             regRBBM_AUXILIARY_CONFIG;
+typedef union RBBM_PERIPHID0                    regRBBM_PERIPHID0;
+typedef union RBBM_PERIPHID1                    regRBBM_PERIPHID1;
+typedef union RBBM_PERIPHID2                    regRBBM_PERIPHID2;
+typedef union RBBM_PERIPHID3                    regRBBM_PERIPHID3;
+typedef union RBBM_CNTL                         regRBBM_CNTL;
+typedef union RBBM_SKEW_CNTL                    regRBBM_SKEW_CNTL;
+typedef union RBBM_SOFT_RESET                   regRBBM_SOFT_RESET;
+typedef union RBBM_PM_OVERRIDE1                 regRBBM_PM_OVERRIDE1;
+typedef union RBBM_PM_OVERRIDE2                 regRBBM_PM_OVERRIDE2;
+typedef union GC_SYS_IDLE                       regGC_SYS_IDLE;
+typedef union NQWAIT_UNTIL                      regNQWAIT_UNTIL;
+typedef union RBBM_DEBUG                        regRBBM_DEBUG;
+typedef union RBBM_READ_ERROR                   regRBBM_READ_ERROR;
+typedef union RBBM_WAIT_IDLE_CLOCKS             regRBBM_WAIT_IDLE_CLOCKS;
+typedef union RBBM_INT_CNTL                     regRBBM_INT_CNTL;
+typedef union RBBM_INT_STATUS                   regRBBM_INT_STATUS;
+typedef union RBBM_INT_ACK                      regRBBM_INT_ACK;
+typedef union MASTER_INT_SIGNAL                 regMASTER_INT_SIGNAL;
+typedef union RBBM_PERFCOUNTER1_SELECT          regRBBM_PERFCOUNTER1_SELECT;
+typedef union RBBM_PERFCOUNTER1_LO              regRBBM_PERFCOUNTER1_LO;
+typedef union RBBM_PERFCOUNTER1_HI              regRBBM_PERFCOUNTER1_HI;
+typedef union CP_RB_BASE                        regCP_RB_BASE;
+typedef union CP_RB_CNTL                        regCP_RB_CNTL;
+typedef union CP_RB_RPTR_ADDR                   regCP_RB_RPTR_ADDR;
+typedef union CP_RB_RPTR                        regCP_RB_RPTR;
+typedef union CP_RB_RPTR_WR                     regCP_RB_RPTR_WR;
+typedef union CP_RB_WPTR                        regCP_RB_WPTR;
+typedef union CP_RB_WPTR_DELAY                  regCP_RB_WPTR_DELAY;
+typedef union CP_RB_WPTR_BASE                   regCP_RB_WPTR_BASE;
+typedef union CP_IB1_BASE                       regCP_IB1_BASE;
+typedef union CP_IB1_BUFSZ                      regCP_IB1_BUFSZ;
+typedef union CP_IB2_BASE                       regCP_IB2_BASE;
+typedef union CP_IB2_BUFSZ                      regCP_IB2_BUFSZ;
+typedef union CP_ST_BASE                        regCP_ST_BASE;
+typedef union CP_ST_BUFSZ                       regCP_ST_BUFSZ;
+typedef union CP_QUEUE_THRESHOLDS               regCP_QUEUE_THRESHOLDS;
+typedef union CP_MEQ_THRESHOLDS                 regCP_MEQ_THRESHOLDS;
+typedef union CP_CSQ_AVAIL                      regCP_CSQ_AVAIL;
+typedef union CP_STQ_AVAIL                      regCP_STQ_AVAIL;
+typedef union CP_MEQ_AVAIL                      regCP_MEQ_AVAIL;
+typedef union CP_CSQ_RB_STAT                    regCP_CSQ_RB_STAT;
+typedef union CP_CSQ_IB1_STAT                   regCP_CSQ_IB1_STAT;
+typedef union CP_CSQ_IB2_STAT                   regCP_CSQ_IB2_STAT;
+typedef union CP_NON_PREFETCH_CNTRS             regCP_NON_PREFETCH_CNTRS;
+typedef union CP_STQ_ST_STAT                    regCP_STQ_ST_STAT;
+typedef union CP_MEQ_STAT                       regCP_MEQ_STAT;
+typedef union CP_MIU_TAG_STAT                   regCP_MIU_TAG_STAT;
+typedef union CP_CMD_INDEX                      regCP_CMD_INDEX;
+typedef union CP_CMD_DATA                       regCP_CMD_DATA;
+typedef union CP_ME_CNTL                        regCP_ME_CNTL;
+typedef union CP_ME_STATUS                      regCP_ME_STATUS;
+typedef union CP_ME_RAM_WADDR                   regCP_ME_RAM_WADDR;
+typedef union CP_ME_RAM_RADDR                   regCP_ME_RAM_RADDR;
+typedef union CP_ME_RAM_DATA                    regCP_ME_RAM_DATA;
+typedef union CP_ME_RDADDR                      regCP_ME_RDADDR;
+typedef union CP_DEBUG                          regCP_DEBUG;
+typedef union SCRATCH_REG0                      regSCRATCH_REG0;
+typedef union GUI_SCRATCH_REG0                  regGUI_SCRATCH_REG0;
+typedef union SCRATCH_REG1                      regSCRATCH_REG1;
+typedef union GUI_SCRATCH_REG1                  regGUI_SCRATCH_REG1;
+typedef union SCRATCH_REG2                      regSCRATCH_REG2;
+typedef union GUI_SCRATCH_REG2                  regGUI_SCRATCH_REG2;
+typedef union SCRATCH_REG3                      regSCRATCH_REG3;
+typedef union GUI_SCRATCH_REG3                  regGUI_SCRATCH_REG3;
+typedef union SCRATCH_REG4                      regSCRATCH_REG4;
+typedef union GUI_SCRATCH_REG4                  regGUI_SCRATCH_REG4;
+typedef union SCRATCH_REG5                      regSCRATCH_REG5;
+typedef union GUI_SCRATCH_REG5                  regGUI_SCRATCH_REG5;
+typedef union SCRATCH_REG6                      regSCRATCH_REG6;
+typedef union GUI_SCRATCH_REG6                  regGUI_SCRATCH_REG6;
+typedef union SCRATCH_REG7                      regSCRATCH_REG7;
+typedef union GUI_SCRATCH_REG7                  regGUI_SCRATCH_REG7;
+typedef union SCRATCH_UMSK                      regSCRATCH_UMSK;
+typedef union SCRATCH_ADDR                      regSCRATCH_ADDR;
+typedef union CP_ME_VS_EVENT_SRC                regCP_ME_VS_EVENT_SRC;
+typedef union CP_ME_VS_EVENT_ADDR               regCP_ME_VS_EVENT_ADDR;
+typedef union CP_ME_VS_EVENT_DATA               regCP_ME_VS_EVENT_DATA;
+typedef union CP_ME_VS_EVENT_ADDR_SWM           regCP_ME_VS_EVENT_ADDR_SWM;
+typedef union CP_ME_VS_EVENT_DATA_SWM           regCP_ME_VS_EVENT_DATA_SWM;
+typedef union CP_ME_PS_EVENT_SRC                regCP_ME_PS_EVENT_SRC;
+typedef union CP_ME_PS_EVENT_ADDR               regCP_ME_PS_EVENT_ADDR;
+typedef union CP_ME_PS_EVENT_DATA               regCP_ME_PS_EVENT_DATA;
+typedef union CP_ME_PS_EVENT_ADDR_SWM           regCP_ME_PS_EVENT_ADDR_SWM;
+typedef union CP_ME_PS_EVENT_DATA_SWM           regCP_ME_PS_EVENT_DATA_SWM;
+typedef union CP_ME_CF_EVENT_SRC                regCP_ME_CF_EVENT_SRC;
+typedef union CP_ME_CF_EVENT_ADDR               regCP_ME_CF_EVENT_ADDR;
+typedef union CP_ME_CF_EVENT_DATA               regCP_ME_CF_EVENT_DATA;
+typedef union CP_ME_NRT_ADDR                    regCP_ME_NRT_ADDR;
+typedef union CP_ME_NRT_DATA                    regCP_ME_NRT_DATA;
+typedef union CP_ME_VS_FETCH_DONE_SRC           regCP_ME_VS_FETCH_DONE_SRC;
+typedef union CP_ME_VS_FETCH_DONE_ADDR          regCP_ME_VS_FETCH_DONE_ADDR;
+typedef union CP_ME_VS_FETCH_DONE_DATA          regCP_ME_VS_FETCH_DONE_DATA;
+typedef union CP_INT_CNTL                       regCP_INT_CNTL;
+typedef union CP_INT_STATUS                     regCP_INT_STATUS;
+typedef union CP_INT_ACK                        regCP_INT_ACK;
+typedef union CP_PFP_UCODE_ADDR                 regCP_PFP_UCODE_ADDR;
+typedef union CP_PFP_UCODE_DATA                 regCP_PFP_UCODE_DATA;
+typedef union CP_PERFMON_CNTL                   regCP_PERFMON_CNTL;
+typedef union CP_PERFCOUNTER_SELECT             regCP_PERFCOUNTER_SELECT;
+typedef union CP_PERFCOUNTER_LO                 regCP_PERFCOUNTER_LO;
+typedef union CP_PERFCOUNTER_HI                 regCP_PERFCOUNTER_HI;
+typedef union CP_BIN_MASK_LO                    regCP_BIN_MASK_LO;
+typedef union CP_BIN_MASK_HI                    regCP_BIN_MASK_HI;
+typedef union CP_BIN_SELECT_LO                  regCP_BIN_SELECT_LO;
+typedef union CP_BIN_SELECT_HI                  regCP_BIN_SELECT_HI;
+typedef union CP_NV_FLAGS_0                     regCP_NV_FLAGS_0;
+typedef union CP_NV_FLAGS_1                     regCP_NV_FLAGS_1;
+typedef union CP_NV_FLAGS_2                     regCP_NV_FLAGS_2;
+typedef union CP_NV_FLAGS_3                     regCP_NV_FLAGS_3;
+typedef union CP_STATE_DEBUG_INDEX              regCP_STATE_DEBUG_INDEX;
+typedef union CP_STATE_DEBUG_DATA               regCP_STATE_DEBUG_DATA;
+typedef union CP_PROG_COUNTER                   regCP_PROG_COUNTER;
+typedef union CP_STAT                           regCP_STAT;
+typedef union BIOS_0_SCRATCH                    regBIOS_0_SCRATCH;
+typedef union BIOS_1_SCRATCH                    regBIOS_1_SCRATCH;
+typedef union BIOS_2_SCRATCH                    regBIOS_2_SCRATCH;
+typedef union BIOS_3_SCRATCH                    regBIOS_3_SCRATCH;
+typedef union BIOS_4_SCRATCH                    regBIOS_4_SCRATCH;
+typedef union BIOS_5_SCRATCH                    regBIOS_5_SCRATCH;
+typedef union BIOS_6_SCRATCH                    regBIOS_6_SCRATCH;
+typedef union BIOS_7_SCRATCH                    regBIOS_7_SCRATCH;
+typedef union BIOS_8_SCRATCH                    regBIOS_8_SCRATCH;
+typedef union BIOS_9_SCRATCH                    regBIOS_9_SCRATCH;
+typedef union BIOS_10_SCRATCH                   regBIOS_10_SCRATCH;
+typedef union BIOS_11_SCRATCH                   regBIOS_11_SCRATCH;
+typedef union BIOS_12_SCRATCH                   regBIOS_12_SCRATCH;
+typedef union BIOS_13_SCRATCH                   regBIOS_13_SCRATCH;
+typedef union BIOS_14_SCRATCH                   regBIOS_14_SCRATCH;
+typedef union BIOS_15_SCRATCH                   regBIOS_15_SCRATCH;
+typedef union COHER_SIZE_PM4                    regCOHER_SIZE_PM4;
+typedef union COHER_BASE_PM4                    regCOHER_BASE_PM4;
+typedef union COHER_STATUS_PM4                  regCOHER_STATUS_PM4;
+typedef union COHER_SIZE_HOST                   regCOHER_SIZE_HOST;
+typedef union COHER_BASE_HOST                   regCOHER_BASE_HOST;
+typedef union COHER_STATUS_HOST                 regCOHER_STATUS_HOST;
+typedef union COHER_DEST_BASE_0                 regCOHER_DEST_BASE_0;
+typedef union COHER_DEST_BASE_1                 regCOHER_DEST_BASE_1;
+typedef union COHER_DEST_BASE_2                 regCOHER_DEST_BASE_2;
+typedef union COHER_DEST_BASE_3                 regCOHER_DEST_BASE_3;
+typedef union COHER_DEST_BASE_4                 regCOHER_DEST_BASE_4;
+typedef union COHER_DEST_BASE_5                 regCOHER_DEST_BASE_5;
+typedef union COHER_DEST_BASE_6                 regCOHER_DEST_BASE_6;
+typedef union COHER_DEST_BASE_7                 regCOHER_DEST_BASE_7;
+typedef union RB_SURFACE_INFO                   regRB_SURFACE_INFO;
+typedef union RB_COLOR_INFO                     regRB_COLOR_INFO;
+typedef union RB_DEPTH_INFO                     regRB_DEPTH_INFO;
+typedef union RB_STENCILREFMASK                 regRB_STENCILREFMASK;
+typedef union RB_ALPHA_REF                      regRB_ALPHA_REF;
+typedef union RB_COLOR_MASK                     regRB_COLOR_MASK;
+typedef union RB_BLEND_RED                      regRB_BLEND_RED;
+typedef union RB_BLEND_GREEN                    regRB_BLEND_GREEN;
+typedef union RB_BLEND_BLUE                     regRB_BLEND_BLUE;
+typedef union RB_BLEND_ALPHA                    regRB_BLEND_ALPHA;
+typedef union RB_FOG_COLOR                      regRB_FOG_COLOR;
+typedef union RB_STENCILREFMASK_BF              regRB_STENCILREFMASK_BF;
+typedef union RB_DEPTHCONTROL                   regRB_DEPTHCONTROL;
+typedef union RB_BLENDCONTROL                   regRB_BLENDCONTROL;
+typedef union RB_COLORCONTROL                   regRB_COLORCONTROL;
+typedef union RB_MODECONTROL                    regRB_MODECONTROL;
+typedef union RB_COLOR_DEST_MASK                regRB_COLOR_DEST_MASK;
+typedef union RB_COPY_CONTROL                   regRB_COPY_CONTROL;
+typedef union RB_COPY_DEST_BASE                 regRB_COPY_DEST_BASE;
+typedef union RB_COPY_DEST_PITCH                regRB_COPY_DEST_PITCH;
+typedef union RB_COPY_DEST_INFO                 regRB_COPY_DEST_INFO;
+typedef union RB_COPY_DEST_PIXEL_OFFSET         regRB_COPY_DEST_PIXEL_OFFSET;
+typedef union RB_DEPTH_CLEAR                    regRB_DEPTH_CLEAR;
+typedef union RB_SAMPLE_COUNT_CTL               regRB_SAMPLE_COUNT_CTL;
+typedef union RB_SAMPLE_COUNT_ADDR              regRB_SAMPLE_COUNT_ADDR;
+typedef union RB_BC_CONTROL                     regRB_BC_CONTROL;
+typedef union RB_EDRAM_INFO                     regRB_EDRAM_INFO;
+typedef union RB_CRC_RD_PORT                    regRB_CRC_RD_PORT;
+typedef union RB_CRC_CONTROL                    regRB_CRC_CONTROL;
+typedef union RB_CRC_MASK                       regRB_CRC_MASK;
+typedef union RB_PERFCOUNTER0_SELECT            regRB_PERFCOUNTER0_SELECT;
+typedef union RB_PERFCOUNTER0_LOW               regRB_PERFCOUNTER0_LOW;
+typedef union RB_PERFCOUNTER0_HI                regRB_PERFCOUNTER0_HI;
+typedef union RB_TOTAL_SAMPLES                  regRB_TOTAL_SAMPLES;
+typedef union RB_ZPASS_SAMPLES                  regRB_ZPASS_SAMPLES;
+typedef union RB_ZFAIL_SAMPLES                  regRB_ZFAIL_SAMPLES;
+typedef union RB_SFAIL_SAMPLES                  regRB_SFAIL_SAMPLES;
+typedef union RB_DEBUG_0                        regRB_DEBUG_0;
+typedef union RB_DEBUG_1                        regRB_DEBUG_1;
+typedef union RB_DEBUG_2                        regRB_DEBUG_2;
+typedef union RB_DEBUG_3                        regRB_DEBUG_3;
+typedef union RB_DEBUG_4                        regRB_DEBUG_4;
+typedef union RB_FLAG_CONTROL                   regRB_FLAG_CONTROL;
+typedef union BC_DUMMY_CRAYRB_ENUMS             regBC_DUMMY_CRAYRB_ENUMS;
+typedef union BC_DUMMY_CRAYRB_MOREENUMS         regBC_DUMMY_CRAYRB_MOREENUMS;
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h
new file mode 100644
index 00000000000..15cfbebf290
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h
@@ -0,0 +1,1897 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_ENUM_HEADER)
+#define _yamato_ENUM_HEADER
+
+
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+#ifndef ENUMS_SU_PERFCNT_SELECT_H
+#define ENUMS_SU_PERFCNT_SELECT_H
+typedef enum SU_PERFCNT_SELECT {
+ PERF_PAPC_PASX_REQ = 0,
+ UNUSED1 = 1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 3,
+ PERF_PAPC_PASX_FIRST_DEAD = 4,
+ PERF_PAPC_PASX_SECOND_DEAD = 5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+ PERF_PAPC_PA_INPUT_PRIM = 8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+ PERF_PAPC_CLPR_CULL_PRIM = 13,
+ UNUSED2 = 14,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+ UNUSED3 = 16,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+ UNUSED4 = 20,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+ UNUSED5 = 22,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+ PERF_PAPC_CLSM_NULL_PRIM = 36,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+ PERF_PAPC_CLSM_CLIP_PRIM = 38,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+ PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+ PERF_PAPC_SU_INPUT_PRIM = 47,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+ PERF_PAPC_SU_OUTPUT_PRIM = 57,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+ PERF_PAPC_PASX_REQ_IDLE = 69,
+ PERF_PAPC_PASX_REQ_BUSY = 70,
+ PERF_PAPC_PASX_REQ_STALLED = 71,
+ PERF_PAPC_PASX_REC_IDLE = 72,
+ PERF_PAPC_PASX_REC_BUSY = 73,
+ PERF_PAPC_PASX_REC_STARVED_SX = 74,
+ PERF_PAPC_PASX_REC_STALLED = 75,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+ PERF_PAPC_CCGSM_IDLE = 78,
+ PERF_PAPC_CCGSM_BUSY = 79,
+ PERF_PAPC_CCGSM_STALLED = 80,
+ PERF_PAPC_CLPRIM_IDLE = 81,
+ PERF_PAPC_CLPRIM_BUSY = 82,
+ PERF_PAPC_CLPRIM_STALLED = 83,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+ PERF_PAPC_CLIPSM_IDLE = 85,
+ PERF_PAPC_CLIPSM_BUSY = 86,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+ PERF_PAPC_CLIPGA_IDLE = 92,
+ PERF_PAPC_CLIPGA_BUSY = 93,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+ PERF_PAPC_CLIPGA_STALLED = 95,
+ PERF_PAPC_CLIP_IDLE = 96,
+ PERF_PAPC_CLIP_BUSY = 97,
+ PERF_PAPC_SU_IDLE = 98,
+ PERF_PAPC_SU_BUSY = 99,
+ PERF_PAPC_SU_STARVED_CLIP = 100,
+ PERF_PAPC_SU_STALLED_SC = 101,
+ PERF_PAPC_SU_FACENESS_CULL = 102,
+} SU_PERFCNT_SELECT;
+#endif /*ENUMS_SU_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SC_PERFCNT_SELECT_H
+#define ENUMS_SC_PERFCNT_SELECT_H
+typedef enum SC_PERFCNT_SELECT {
+ SC_SR_WINDOW_VALID = 0,
+ SC_CW_WINDOW_VALID = 1,
+ SC_QM_WINDOW_VALID = 2,
+ SC_FW_WINDOW_VALID = 3,
+ SC_EZ_WINDOW_VALID = 4,
+ SC_IT_WINDOW_VALID = 5,
+ SC_STARVED_BY_PA = 6,
+ SC_STALLED_BY_RB_TILE = 7,
+ SC_STALLED_BY_RB_SAMP = 8,
+ SC_STARVED_BY_RB_EZ = 9,
+ SC_STALLED_BY_SAMPLE_FF = 10,
+ SC_STALLED_BY_SQ = 11,
+ SC_STALLED_BY_SP = 12,
+ SC_TOTAL_NO_PRIMS = 13,
+ SC_NON_EMPTY_PRIMS = 14,
+ SC_NO_TILES_PASSING_QM = 15,
+ SC_NO_PIXELS_PRE_EZ = 16,
+ SC_NO_PIXELS_POST_EZ = 17,
+} SC_PERFCNT_SELECT;
+#endif /*ENUMS_SC_PERFCNT_SELECT_H*/
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+#ifndef ENUMS_VGT_DI_PRIM_TYPE_H
+#define ENUMS_VGT_DI_PRIM_TYPE_H
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0,
+ DI_PT_POINTLIST = 1,
+ DI_PT_LINELIST = 2,
+ DI_PT_LINESTRIP = 3,
+ DI_PT_TRILIST = 4,
+ DI_PT_TRIFAN = 5,
+ DI_PT_TRISTRIP = 6,
+ DI_PT_UNUSED_1 = 7,
+ DI_PT_RECTLIST = 8,
+ DI_PT_UNUSED_2 = 9,
+ DI_PT_UNUSED_3 = 10,
+ DI_PT_UNUSED_4 = 11,
+ DI_PT_UNUSED_5 = 12,
+ DI_PT_QUADLIST = 13,
+ DI_PT_QUADSTRIP = 14,
+ DI_PT_POLYGON = 15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+ DI_PT_2D_FILL_RECT_LIST = 20,
+ DI_PT_2D_LINE_STRIP = 21,
+ DI_PT_2D_TRI_STRIP = 22,
+} VGT_DI_PRIM_TYPE;
+#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/
+
+#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H
+#define ENUMS_VGT_DI_SOURCE_SELECT_H
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0,
+ DI_SRC_SEL_IMMEDIATE = 1,
+ DI_SRC_SEL_AUTO_INDEX = 2,
+ DI_SRC_SEL_RESERVED = 3
+} VGT_DI_SOURCE_SELECT;
+#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H
+typedef enum VGT_DI_FACENESS_CULL_SELECT {
+ DI_FACE_CULL_NONE = 0,
+ DI_FACE_CULL_FETCH = 1,
+ DI_FACE_BACKFACE_CULL = 2,
+ DI_FACE_FRONTFACE_CULL = 3
+} VGT_DI_FACENESS_CULL_SELECT;
+#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/
+
+#ifndef ENUMS_VGT_DI_INDEX_SIZE_H
+#define ENUMS_VGT_DI_INDEX_SIZE_H
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0,
+ DI_INDEX_SIZE_32_BIT = 1
+} VGT_DI_INDEX_SIZE;
+#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/
+
+#ifndef ENUMS_VGT_DI_SMALL_INDEX_H
+#define ENUMS_VGT_DI_SMALL_INDEX_H
+typedef enum VGT_DI_SMALL_INDEX {
+ DI_USE_INDEX_SIZE = 0,
+ DI_INDEX_SIZE_8_BIT = 1
+} VGT_DI_SMALL_INDEX;
+#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/
+
+#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H
+typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE {
+ DISABLE_PRE_FETCH_CULL_ENABLE = 0,
+ PRE_FETCH_CULL_ENABLE = 1
+} VGT_DI_PRE_FETCH_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H
+typedef enum VGT_DI_GRP_CULL_ENABLE {
+ DISABLE_GRP_CULL_ENABLE = 0,
+ GRP_CULL_ENABLE = 1
+} VGT_DI_GRP_CULL_ENABLE;
+#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/
+
+#ifndef ENUMS_VGT_EVENT_TYPE_H
+#define ENUMS_VGT_EVENT_TYPE_H
+typedef enum VGT_EVENT_TYPE {
+ VS_DEALLOC = 0,
+ PS_DEALLOC = 1,
+ VS_DONE_TS = 2,
+ PS_DONE_TS = 3,
+ CACHE_FLUSH_TS = 4,
+ CONTEXT_DONE = 5,
+ CACHE_FLUSH = 6,
+ VIZQUERY_START = 7,
+ VIZQUERY_END = 8,
+ SC_WAIT_WC = 9,
+ RST_PIX_CNT = 13,
+ RST_VTX_CNT = 14,
+ TILE_FLUSH = 15,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+ ZPASS_DONE = 21,
+ CACHE_FLUSH_AND_INV_EVENT = 22,
+ PERFCOUNTER_START = 23,
+ PERFCOUNTER_STOP = 24,
+ VS_FETCH_DONE = 27,
+ FACENESS_FLUSH = 28,
+} VGT_EVENT_TYPE;
+#endif /*ENUMS_VGT_EVENT_TYPE_H*/
+
+#ifndef ENUMS_VGT_DMA_SWAP_MODE_H
+#define ENUMS_VGT_DMA_SWAP_MODE_H
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0,
+ VGT_DMA_SWAP_16_BIT = 1,
+ VGT_DMA_SWAP_32_BIT = 2,
+ VGT_DMA_SWAP_WORD = 3
+} VGT_DMA_SWAP_MODE;
+#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/
+
+#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H
+#define ENUMS_VGT_PERFCOUNT_SELECT_H
+typedef enum VGT_PERFCOUNT_SELECT {
+ VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+ VGT_SQ_SEND = 1,
+ VGT_SQ_STALLED = 2,
+ VGT_SQ_STARVED_BUSY = 3,
+ VGT_SQ_STARVED_IDLE = 4,
+ VGT_SQ_STATIC = 5,
+ VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+ VGT_PA_CLIP_V_SEND = 7,
+ VGT_PA_CLIP_V_STALLED = 8,
+ VGT_PA_CLIP_V_STARVED_BUSY = 9,
+ VGT_PA_CLIP_V_STARVED_IDLE = 10,
+ VGT_PA_CLIP_V_STATIC = 11,
+ VGT_PA_CLIP_P_SEND = 12,
+ VGT_PA_CLIP_P_STALLED = 13,
+ VGT_PA_CLIP_P_STARVED_BUSY = 14,
+ VGT_PA_CLIP_P_STARVED_IDLE = 15,
+ VGT_PA_CLIP_P_STATIC = 16,
+ VGT_PA_CLIP_S_SEND = 17,
+ VGT_PA_CLIP_S_STALLED = 18,
+ VGT_PA_CLIP_S_STARVED_BUSY = 19,
+ VGT_PA_CLIP_S_STARVED_IDLE = 20,
+ VGT_PA_CLIP_S_STATIC = 21,
+ RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+ RBIU_IMMED_DATA_FIFO_STARVED = 23,
+ RBIU_IMMED_DATA_FIFO_STALLED = 24,
+ RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+ RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+ RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+ RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+ BIN_PRIM_NEAR_CULL = 29,
+ BIN_PRIM_ZERO_CULL = 30,
+ BIN_PRIM_FAR_CULL = 31,
+ BIN_PRIM_BIN_CULL = 32,
+ BIN_PRIM_FACE_CULL = 33,
+ SPARE34 = 34,
+ SPARE35 = 35,
+ SPARE36 = 36,
+ SPARE37 = 37,
+ SPARE38 = 38,
+ SPARE39 = 39,
+ TE_SU_IN_VALID = 40,
+ TE_SU_IN_READ = 41,
+ TE_SU_IN_PRIM = 42,
+ TE_SU_IN_EOP = 43,
+ TE_SU_IN_NULL_PRIM = 44,
+ TE_WK_IN_VALID = 45,
+ TE_WK_IN_READ = 46,
+ TE_OUT_PRIM_VALID = 47,
+ TE_OUT_PRIM_READ = 48,
+} VGT_PERFCOUNT_SELECT;
+#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H
+#define ENUMS_TCR_PERFCOUNT_SELECT_H
+typedef enum TCR_PERFCOUNT_SELECT {
+ DGMMPD_IPMUX0_STALL = 0,
+ reserved_46 = 1,
+ reserved_47 = 2,
+ reserved_48 = 3,
+ DGMMPD_IPMUX_ALL_STALL = 4,
+ OPMUX0_L2_WRITES = 5,
+ reserved_49 = 6,
+ reserved_50 = 7,
+ reserved_51 = 8,
+} TCR_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TP_PERFCOUNT_SELECT_H
+#define ENUMS_TP_PERFCOUNT_SELECT_H
+typedef enum TP_PERFCOUNT_SELECT {
+ POINT_QUADS = 0,
+ BILIN_QUADS = 1,
+ ANISO_QUADS = 2,
+ MIP_QUADS = 3,
+ VOL_QUADS = 4,
+ MIP_VOL_QUADS = 5,
+ MIP_ANISO_QUADS = 6,
+ VOL_ANISO_QUADS = 7,
+ ANISO_2_1_QUADS = 8,
+ ANISO_4_1_QUADS = 9,
+ ANISO_6_1_QUADS = 10,
+ ANISO_8_1_QUADS = 11,
+ ANISO_10_1_QUADS = 12,
+ ANISO_12_1_QUADS = 13,
+ ANISO_14_1_QUADS = 14,
+ ANISO_16_1_QUADS = 15,
+ MIP_VOL_ANISO_QUADS = 16,
+ ALIGN_2_QUADS = 17,
+ ALIGN_4_QUADS = 18,
+ PIX_0_QUAD = 19,
+ PIX_1_QUAD = 20,
+ PIX_2_QUAD = 21,
+ PIX_3_QUAD = 22,
+ PIX_4_QUAD = 23,
+ TP_MIPMAP_LOD0 = 24,
+ TP_MIPMAP_LOD1 = 25,
+ TP_MIPMAP_LOD2 = 26,
+ TP_MIPMAP_LOD3 = 27,
+ TP_MIPMAP_LOD4 = 28,
+ TP_MIPMAP_LOD5 = 29,
+ TP_MIPMAP_LOD6 = 30,
+ TP_MIPMAP_LOD7 = 31,
+ TP_MIPMAP_LOD8 = 32,
+ TP_MIPMAP_LOD9 = 33,
+ TP_MIPMAP_LOD10 = 34,
+ TP_MIPMAP_LOD11 = 35,
+ TP_MIPMAP_LOD12 = 36,
+ TP_MIPMAP_LOD13 = 37,
+ TP_MIPMAP_LOD14 = 38,
+} TP_PERFCOUNT_SELECT;
+#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H
+#define ENUMS_TCM_PERFCOUNT_SELECT_H
+typedef enum TCM_PERFCOUNT_SELECT {
+ QUAD0_RD_LAT_FIFO_EMPTY = 0,
+ reserved_01 = 1,
+ reserved_02 = 2,
+ QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+ QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+ QUAD0_RD_LAT_FIFO_FULL = 5,
+ QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+ reserved_07 = 7,
+ reserved_08 = 8,
+ reserved_09 = 9,
+ reserved_10 = 10,
+ reserved_11 = 11,
+ reserved_12 = 12,
+ reserved_13 = 13,
+ reserved_14 = 14,
+ reserved_15 = 15,
+ reserved_16 = 16,
+ reserved_17 = 17,
+ reserved_18 = 18,
+ reserved_19 = 19,
+ reserved_20 = 20,
+ reserved_21 = 21,
+ reserved_22 = 22,
+ reserved_23 = 23,
+ reserved_24 = 24,
+ reserved_25 = 25,
+ reserved_26 = 26,
+ reserved_27 = 27,
+ READ_STARVED_QUAD0 = 28,
+ reserved_29 = 29,
+ reserved_30 = 30,
+ reserved_31 = 31,
+ READ_STARVED = 32,
+ READ_STALLED_QUAD0 = 33,
+ reserved_34 = 34,
+ reserved_35 = 35,
+ reserved_36 = 36,
+ READ_STALLED = 37,
+ VALID_READ_QUAD0 = 38,
+ reserved_39 = 39,
+ reserved_40 = 40,
+ reserved_41 = 41,
+ TC_TP_STARVED_QUAD0 = 42,
+ reserved_43 = 43,
+ reserved_44 = 44,
+ reserved_45 = 45,
+ TC_TP_STARVED = 46,
+} TCM_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/
+
+#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H
+#define ENUMS_TCF_PERFCOUNT_SELECT_H
+typedef enum TCF_PERFCOUNT_SELECT {
+ VALID_CYCLES = 0,
+ SINGLE_PHASES = 1,
+ ANISO_PHASES = 2,
+ MIP_PHASES = 3,
+ VOL_PHASES = 4,
+ MIP_VOL_PHASES = 5,
+ MIP_ANISO_PHASES = 6,
+ VOL_ANISO_PHASES = 7,
+ ANISO_2_1_PHASES = 8,
+ ANISO_4_1_PHASES = 9,
+ ANISO_6_1_PHASES = 10,
+ ANISO_8_1_PHASES = 11,
+ ANISO_10_1_PHASES = 12,
+ ANISO_12_1_PHASES = 13,
+ ANISO_14_1_PHASES = 14,
+ ANISO_16_1_PHASES = 15,
+ MIP_VOL_ANISO_PHASES = 16,
+ ALIGN_2_PHASES = 17,
+ ALIGN_4_PHASES = 18,
+ TPC_BUSY = 19,
+ TPC_STALLED = 20,
+ TPC_STARVED = 21,
+ TPC_WORKING = 22,
+ TPC_WALKER_BUSY = 23,
+ TPC_WALKER_STALLED = 24,
+ TPC_WALKER_WORKING = 25,
+ TPC_ALIGNER_BUSY = 26,
+ TPC_ALIGNER_STALLED = 27,
+ TPC_ALIGNER_STALLED_BY_BLEND = 28,
+ TPC_ALIGNER_STALLED_BY_CACHE = 29,
+ TPC_ALIGNER_WORKING = 30,
+ TPC_BLEND_BUSY = 31,
+ TPC_BLEND_SYNC = 32,
+ TPC_BLEND_STARVED = 33,
+ TPC_BLEND_WORKING = 34,
+ OPCODE_0x00 = 35,
+ OPCODE_0x01 = 36,
+ OPCODE_0x04 = 37,
+ OPCODE_0x10 = 38,
+ OPCODE_0x11 = 39,
+ OPCODE_0x12 = 40,
+ OPCODE_0x13 = 41,
+ OPCODE_0x18 = 42,
+ OPCODE_0x19 = 43,
+ OPCODE_0x1A = 44,
+ OPCODE_OTHER = 45,
+ IN_FIFO_0_EMPTY = 56,
+ IN_FIFO_0_LT_HALF_FULL = 57,
+ IN_FIFO_0_HALF_FULL = 58,
+ IN_FIFO_0_FULL = 59,
+ IN_FIFO_TPC_EMPTY = 72,
+ IN_FIFO_TPC_LT_HALF_FULL = 73,
+ IN_FIFO_TPC_HALF_FULL = 74,
+ IN_FIFO_TPC_FULL = 75,
+ TPC_TC_XFC = 76,
+ TPC_TC_STATE = 77,
+ TC_STALL = 78,
+ QUAD0_TAPS = 79,
+ QUADS = 83,
+ TCA_SYNC_STALL = 84,
+ TAG_STALL = 85,
+ TCB_SYNC_STALL = 88,
+ TCA_VALID = 89,
+ PROBES_VALID = 90,
+ MISS_STALL = 91,
+ FETCH_FIFO_STALL = 92,
+ TCO_STALL = 93,
+ ANY_STALL = 94,
+ TAG_MISSES = 95,
+ TAG_HITS = 96,
+ SUB_TAG_MISSES = 97,
+ SET0_INVALIDATES = 98,
+ SET1_INVALIDATES = 99,
+ SET2_INVALIDATES = 100,
+ SET3_INVALIDATES = 101,
+ SET0_TAG_MISSES = 102,
+ SET1_TAG_MISSES = 103,
+ SET2_TAG_MISSES = 104,
+ SET3_TAG_MISSES = 105,
+ SET0_TAG_HITS = 106,
+ SET1_TAG_HITS = 107,
+ SET2_TAG_HITS = 108,
+ SET3_TAG_HITS = 109,
+ SET0_SUB_TAG_MISSES = 110,
+ SET1_SUB_TAG_MISSES = 111,
+ SET2_SUB_TAG_MISSES = 112,
+ SET3_SUB_TAG_MISSES = 113,
+ SET0_EVICT1 = 114,
+ SET0_EVICT2 = 115,
+ SET0_EVICT3 = 116,
+ SET0_EVICT4 = 117,
+ SET0_EVICT5 = 118,
+ SET0_EVICT6 = 119,
+ SET0_EVICT7 = 120,
+ SET0_EVICT8 = 121,
+ SET1_EVICT1 = 130,
+ SET1_EVICT2 = 131,
+ SET1_EVICT3 = 132,
+ SET1_EVICT4 = 133,
+ SET1_EVICT5 = 134,
+ SET1_EVICT6 = 135,
+ SET1_EVICT7 = 136,
+ SET1_EVICT8 = 137,
+ SET2_EVICT1 = 146,
+ SET2_EVICT2 = 147,
+ SET2_EVICT3 = 148,
+ SET2_EVICT4 = 149,
+ SET2_EVICT5 = 150,
+ SET2_EVICT6 = 151,
+ SET2_EVICT7 = 152,
+ SET2_EVICT8 = 153,
+ SET3_EVICT1 = 162,
+ SET3_EVICT2 = 163,
+ SET3_EVICT3 = 164,
+ SET3_EVICT4 = 165,
+ SET3_EVICT5 = 166,
+ SET3_EVICT6 = 167,
+ SET3_EVICT7 = 168,
+ SET3_EVICT8 = 169,
+ FF_EMPTY = 178,
+ FF_LT_HALF_FULL = 179,
+ FF_HALF_FULL = 180,
+ FF_FULL = 181,
+ FF_XFC = 182,
+ FF_STALLED = 183,
+ FG_MASKS = 184,
+ FG_LEFT_MASKS = 185,
+ FG_LEFT_MASK_STALLED = 186,
+ FG_LEFT_NOT_DONE_STALL = 187,
+ FG_LEFT_FG_STALL = 188,
+ FG_LEFT_SECTORS = 189,
+ FG0_REQUESTS = 195,
+ FG0_STALLED = 196,
+ MEM_REQ512 = 199,
+ MEM_REQ_SENT = 200,
+ MEM_LOCAL_READ_REQ = 202,
+ TC0_MH_STALLED = 203,
+} TCF_PERFCOUNT_SELECT;
+#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+#ifndef ENUMS_SQ_PERFCNT_SELECT_H
+#define ENUMS_SQ_PERFCNT_SELECT_H
+typedef enum SQ_PERFCNT_SELECT {
+ SQ_PIXEL_VECTORS_SUB = 0,
+ SQ_VERTEX_VECTORS_SUB = 1,
+ SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+ SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+ SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+ SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+ SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+ SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+ SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+ SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+ SQ_EXPORT_CYCLES = 10,
+ SQ_ALU_CST_WRITTEN = 11,
+ SQ_TEX_CST_WRITTEN = 12,
+ SQ_ALU_CST_STALL = 13,
+ SQ_ALU_TEX_STALL = 14,
+ SQ_INST_WRITTEN = 15,
+ SQ_BOOLEAN_WRITTEN = 16,
+ SQ_LOOPS_WRITTEN = 17,
+ SQ_PIXEL_SWAP_IN = 18,
+ SQ_PIXEL_SWAP_OUT = 19,
+ SQ_VERTEX_SWAP_IN = 20,
+ SQ_VERTEX_SWAP_OUT = 21,
+ SQ_ALU_VTX_INST_ISSUED = 22,
+ SQ_TEX_VTX_INST_ISSUED = 23,
+ SQ_VC_VTX_INST_ISSUED = 24,
+ SQ_CF_VTX_INST_ISSUED = 25,
+ SQ_ALU_PIX_INST_ISSUED = 26,
+ SQ_TEX_PIX_INST_ISSUED = 27,
+ SQ_VC_PIX_INST_ISSUED = 28,
+ SQ_CF_PIX_INST_ISSUED = 29,
+ SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+ SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+ SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+ SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+ SQ_ALU_NOPS = 34,
+ SQ_PRED_SKIP = 35,
+ SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+ SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+ SQ_SYNC_TEX_STALL_VTX = 38,
+ SQ_SYNC_VC_STALL_VTX = 39,
+ SQ_CONSTANTS_USED_SIMD0 = 40,
+ SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+ SQ_GPR_STALL_VTX = 42,
+ SQ_GPR_STALL_PIX = 43,
+ SQ_VTX_RS_STALL = 44,
+ SQ_PIX_RS_STALL = 45,
+ SQ_SX_PC_FULL   = 46,
+ SQ_SX_EXP_BUFF_FULL = 47,
+ SQ_SX_POS_BUFF_FULL = 48,
+ SQ_INTERP_QUADS = 49,
+ SQ_INTERP_ACTIVE = 50,
+ SQ_IN_PIXEL_STALL = 51,
+ SQ_IN_VTX_STALL = 52,
+ SQ_VTX_CNT = 53,
+ SQ_VTX_VECTOR2 = 54,
+ SQ_VTX_VECTOR3 = 55,
+ SQ_VTX_VECTOR4 = 56,
+ SQ_PIXEL_VECTOR1 = 57,
+ SQ_PIXEL_VECTOR23 = 58,
+ SQ_PIXEL_VECTOR4 = 59,
+ SQ_CONSTANTS_USED_SIMD1 = 60,
+ SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+ SQ_SX_MEM_EXP_FULL = 62,
+ SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+ SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+ SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+ SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+ SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+ SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
+ SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+ SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
+ SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+ SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+ SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+ SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+ SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+ SQ_PERFCOUNT_VTX_POP_THREAD = 76,
+ SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+ SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+ SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+ SQ_PERFCOUNT_PIX_POP_THREAD = 80,
+ SQ_SYNC_TEX_STALL_PIX = 81,
+ SQ_SYNC_VC_STALL_PIX = 82,
+ SQ_CONSTANTS_USED_SIMD2 = 83,
+ SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+ SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
+ SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
+ SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+ SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+ SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+ SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+ SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+ SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+ SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+ SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+ VC_PERF_STATIC = 95,
+ VC_PERF_STALLED = 96,
+ VC_PERF_STARVED = 97,
+ VC_PERF_SEND = 98,
+ VC_PERF_ACTUAL_STARVED = 99,
+ PIXEL_THREAD_0_ACTIVE   = 100,
+ VERTEX_THREAD_0_ACTIVE  = 101,
+ PIXEL_THREAD_0_NUMBER   = 102,
+ VERTEX_THREAD_0_NUMBER  = 103,
+ VERTEX_EVENT_NUMBER     = 104,
+ PIXEL_EVENT_NUMBER  = 105,
+ PTRBUFF_EF_PUSH = 106,
+ PTRBUFF_EF_POP_EVENT = 107,
+ PTRBUFF_EF_POP_NEW_VTX = 108,
+ PTRBUFF_EF_POP_DEALLOC = 109,
+ PTRBUFF_EF_POP_PVECTOR = 110,
+ PTRBUFF_EF_POP_PVECTOR_X = 111,
+ PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+ PTRBUFF_PB_DEALLOC = 113,
+ PTRBUFF_PI_STATE_PPB_POP = 114,
+ PTRBUFF_PI_RTR = 115,
+ PTRBUFF_PI_READ_EN = 116,
+ PTRBUFF_PI_BUFF_SWAP = 117,
+ PTRBUFF_SQ_FREE_BUFF = 118,
+ PTRBUFF_SQ_DEC = 119,
+ PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+ PTRBUFF_SC_VALID_IJ_XFER = 121,
+ PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+ PTRBUFF_QUAL_NEW_VECTOR = 123,
+ PTRBUFF_QUAL_EVENT = 124,
+ PTRBUFF_END_BUFFER = 125,
+ PTRBUFF_FILL_QUAD = 126,
+ VERTS_WRITTEN_SPI = 127,
+ TP_FETCH_INSTR_EXEC = 128,
+ TP_FETCH_INSTR_REQ = 129,
+ TP_DATA_RETURN = 130,
+ SPI_WRITE_CYCLES_SP = 131,
+ SPI_WRITES_SP = 132,
+ SP_ALU_INSTR_EXEC = 133,
+ SP_CONST_ADDR_TO_SQ = 134,
+ SP_PRED_KILLS_TO_SQ = 135,
+ SP_EXPORT_CYCLES_TO_SX = 136,
+ SP_EXPORTS_TO_SX = 137,
+ SQ_CYCLES_ELAPSED = 138,
+ SQ_TCFS_OPT_ALLOC_EXEC = 139,
+ SQ_TCFS_NO_OPT_ALLOC = 140,
+ SQ_ALU0_NO_OPT_ALLOC = 141,
+ SQ_ALU1_NO_OPT_ALLOC = 142,
+ SQ_TCFS_ARB_XFC_CNT = 143,
+ SQ_ALU0_ARB_XFC_CNT = 144,
+ SQ_ALU1_ARB_XFC_CNT = 145,
+ SQ_TCFS_CFS_UPDATE_CNT = 146,
+ SQ_ALU0_CFS_UPDATE_CNT = 147,
+ SQ_ALU1_CFS_UPDATE_CNT = 148,
+ SQ_VTX_PUSH_THREAD_CNT = 149,
+ SQ_VTX_POP_THREAD_CNT = 150,
+ SQ_PIX_PUSH_THREAD_CNT = 151,
+ SQ_PIX_POP_THREAD_CNT = 152,
+ SQ_PIX_TOTAL = 153,
+ SQ_PIX_KILLED = 154,
+} SQ_PERFCNT_SELECT;
+#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_SX_PERFCNT_SELECT_H
+#define ENUMS_SX_PERFCNT_SELECT_H
+typedef enum SX_PERFCNT_SELECT {
+ SX_EXPORT_VECTORS = 0,
+ SX_DUMMY_QUADS  = 1,
+ SX_ALPHA_FAIL = 2,
+ SX_RB_QUAD_BUSY = 3,
+ SX_RB_COLOR_BUSY = 4,
+ SX_RB_QUAD_STALL = 5,
+ SX_RB_COLOR_STALL = 6,
+} SX_PERFCNT_SELECT;
+#endif /*ENUMS_SX_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_Abs_modifier_H
+#define ENUMS_Abs_modifier_H
+typedef enum Abs_modifier {
+ NO_ABS_MOD = 0,
+ ABS_MOD = 1
+} Abs_modifier;
+#endif /*ENUMS_Abs_modifier_H*/
+
+#ifndef ENUMS_Exporting_H
+#define ENUMS_Exporting_H
+typedef enum Exporting {
+ NOT_EXPORTING = 0,
+ EXPORTING = 1
+} Exporting;
+#endif /*ENUMS_Exporting_H*/
+
+#ifndef ENUMS_ScalarOpcode_H
+#define ENUMS_ScalarOpcode_H
+typedef enum ScalarOpcode {
+ ADDs = 0,
+ ADD_PREVs = 1,
+ MULs = 2,
+ MUL_PREVs = 3,
+ MUL_PREV2s = 4,
+ MAXs = 5,
+ MINs = 6,
+ SETEs = 7,
+ SETGTs = 8,
+ SETGTEs = 9,
+ SETNEs = 10,
+ FRACs = 11,
+ TRUNCs = 12,
+ FLOORs = 13,
+ EXP_IEEE = 14,
+ LOG_CLAMP = 15,
+ LOG_IEEE = 16,
+ RECIP_CLAMP = 17,
+ RECIP_FF = 18,
+ RECIP_IEEE = 19,
+ RECIPSQ_CLAMP = 20,
+ RECIPSQ_FF = 21,
+ RECIPSQ_IEEE = 22,
+ MOVAs = 23,
+ MOVA_FLOORs = 24,
+ SUBs = 25,
+ SUB_PREVs = 26,
+ PRED_SETEs = 27,
+ PRED_SETNEs = 28,
+ PRED_SETGTs = 29,
+ PRED_SETGTEs = 30,
+ PRED_SET_INVs = 31,
+ PRED_SET_POPs = 32,
+ PRED_SET_CLRs = 33,
+ PRED_SET_RESTOREs = 34,
+ KILLEs = 35,
+ KILLGTs = 36,
+ KILLGTEs = 37,
+ KILLNEs = 38,
+ KILLONEs = 39,
+ SQRT_IEEE = 40,
+ MUL_CONST_0 = 42,
+ MUL_CONST_1 = 43,
+ ADD_CONST_0 = 44,
+ ADD_CONST_1 = 45,
+ SUB_CONST_0 = 46,
+ SUB_CONST_1 = 47,
+ SIN = 48,
+ COS = 49,
+ RETAIN_PREV = 50,
+} ScalarOpcode;
+#endif /*ENUMS_ScalarOpcode_H*/
+
+#ifndef ENUMS_SwizzleType_H
+#define ENUMS_SwizzleType_H
+typedef enum SwizzleType {
+ NO_SWIZZLE = 0,
+ SHIFT_RIGHT_1 = 1,
+ SHIFT_RIGHT_2 = 2,
+ SHIFT_RIGHT_3 = 3
+} SwizzleType;
+#endif /*ENUMS_SwizzleType_H*/
+
+#ifndef ENUMS_InputModifier_H
+#define ENUMS_InputModifier_H
+typedef enum InputModifier {
+ NIL = 0,
+ NEGATE = 1
+} InputModifier;
+#endif /*ENUMS_InputModifier_H*/
+
+#ifndef ENUMS_PredicateSelect_H
+#define ENUMS_PredicateSelect_H
+typedef enum PredicateSelect {
+ NO_PREDICATION = 0,
+ PREDICATE_QUAD = 1,
+ PREDICATED_2 = 2,
+ PREDICATED_3 = 3
+} PredicateSelect;
+#endif /*ENUMS_PredicateSelect_H*/
+
+#ifndef ENUMS_OperandSelect1_H
+#define ENUMS_OperandSelect1_H
+typedef enum OperandSelect1 {
+ ABSOLUTE_REG = 0,
+ RELATIVE_REG = 1
+} OperandSelect1;
+#endif /*ENUMS_OperandSelect1_H*/
+
+#ifndef ENUMS_VectorOpcode_H
+#define ENUMS_VectorOpcode_H
+typedef enum VectorOpcode {
+ ADDv = 0,
+ MULv = 1,
+ MAXv = 2,
+ MINv = 3,
+ SETEv = 4,
+ SETGTv = 5,
+ SETGTEv = 6,
+ SETNEv = 7,
+ FRACv = 8,
+ TRUNCv = 9,
+ FLOORv = 10,
+ MULADDv = 11,
+ CNDEv = 12,
+ CNDGTEv = 13,
+ CNDGTv = 14,
+ DOT4v = 15,
+ DOT3v = 16,
+ DOT2ADDv = 17,
+ CUBEv = 18,
+ MAX4v = 19,
+ PRED_SETE_PUSHv = 20,
+ PRED_SETNE_PUSHv = 21,
+ PRED_SETGT_PUSHv = 22,
+ PRED_SETGTE_PUSHv = 23,
+ KILLEv = 24,
+ KILLGTv = 25,
+ KILLGTEv = 26,
+ KILLNEv = 27,
+ DSTv = 28,
+ MOVAv = 29,
+} VectorOpcode;
+#endif /*ENUMS_VectorOpcode_H*/
+
+#ifndef ENUMS_OperandSelect0_H
+#define ENUMS_OperandSelect0_H
+typedef enum OperandSelect0 {
+ CONSTANT = 0,
+ NON_CONSTANT = 1
+} OperandSelect0;
+#endif /*ENUMS_OperandSelect0_H*/
+
+#ifndef ENUMS_Ressource_type_H
+#define ENUMS_Ressource_type_H
+typedef enum Ressource_type {
+ ALU = 0,
+ TEXTURE = 1
+} Ressource_type;
+#endif /*ENUMS_Ressource_type_H*/
+
+#ifndef ENUMS_Instruction_serial_H
+#define ENUMS_Instruction_serial_H
+typedef enum Instruction_serial {
+ NOT_SERIAL = 0,
+ SERIAL = 1
+} Instruction_serial;
+#endif /*ENUMS_Instruction_serial_H*/
+
+#ifndef ENUMS_VC_type_H
+#define ENUMS_VC_type_H
+typedef enum VC_type {
+ ALU_TP_REQUEST = 0,
+ VC_REQUEST = 1
+} VC_type;
+#endif /*ENUMS_VC_type_H*/
+
+#ifndef ENUMS_Addressing_H
+#define ENUMS_Addressing_H
+typedef enum Addressing {
+ RELATIVE_ADDR = 0,
+ ABSOLUTE_ADDR = 1
+} Addressing;
+#endif /*ENUMS_Addressing_H*/
+
+#ifndef ENUMS_CFOpcode_H
+#define ENUMS_CFOpcode_H
+typedef enum CFOpcode {
+ NOP = 0,
+ EXECUTE = 1,
+ EXECUTE_END = 2,
+ COND_EXECUTE = 3,
+ COND_EXECUTE_END = 4,
+ COND_PRED_EXECUTE = 5,
+ COND_PRED_EXECUTE_END = 6,
+ LOOP_START = 7,
+ LOOP_END = 8,
+ COND_CALL = 9,
+ RETURN = 10,
+ COND_JMP = 11,
+ ALLOCATE = 12,
+ COND_EXECUTE_PRED_CLEAN = 13,
+ COND_EXECUTE_PRED_CLEAN_END = 14,
+ MARK_VS_FETCH_DONE = 15
+} CFOpcode;
+#endif /*ENUMS_CFOpcode_H*/
+
+#ifndef ENUMS_Allocation_type_H
+#define ENUMS_Allocation_type_H
+typedef enum Allocation_type {
+ SQ_NO_ALLOC = 0,
+ SQ_POSITION = 1,
+ SQ_PARAMETER_PIXEL = 2,
+ SQ_MEMORY = 3
+} Allocation_type;
+#endif /*ENUMS_Allocation_type_H*/
+
+#ifndef ENUMS_TexInstOpcode_H
+#define ENUMS_TexInstOpcode_H
+typedef enum TexInstOpcode {
+ TEX_INST_FETCH = 1,
+ TEX_INST_RESERVED_1 = 2,
+ TEX_INST_RESERVED_2 = 3,
+ TEX_INST_RESERVED_3 = 4,
+ TEX_INST_GET_BORDER_COLOR_FRAC = 16,
+ TEX_INST_GET_COMP_TEX_LOD = 17,
+ TEX_INST_GET_GRADIENTS = 18,
+ TEX_INST_GET_WEIGHTS = 19,
+ TEX_INST_SET_TEX_LOD = 24,
+ TEX_INST_SET_GRADIENTS_H = 25,
+ TEX_INST_SET_GRADIENTS_V = 26,
+ TEX_INST_RESERVED_4 = 27,
+} TexInstOpcode;
+#endif /*ENUMS_TexInstOpcode_H*/
+
+#ifndef ENUMS_Addressmode_H
+#define ENUMS_Addressmode_H
+typedef enum Addressmode {
+ LOGICAL = 0,
+ LOOP_RELATIVE = 1
+} Addressmode;
+#endif /*ENUMS_Addressmode_H*/
+
+#ifndef ENUMS_TexCoordDenorm_H
+#define ENUMS_TexCoordDenorm_H
+typedef enum TexCoordDenorm {
+ TEX_COORD_NORMALIZED = 0,
+ TEX_COORD_UNNORMALIZED = 1
+} TexCoordDenorm;
+#endif /*ENUMS_TexCoordDenorm_H*/
+
+#ifndef ENUMS_SrcSel_H
+#define ENUMS_SrcSel_H
+typedef enum SrcSel {
+ SRC_SEL_X = 0,
+ SRC_SEL_Y = 1,
+ SRC_SEL_Z = 2,
+ SRC_SEL_W = 3
+} SrcSel;
+#endif /*ENUMS_SrcSel_H*/
+
+#ifndef ENUMS_DstSel_H
+#define ENUMS_DstSel_H
+typedef enum DstSel {
+ DST_SEL_X = 0,
+ DST_SEL_Y = 1,
+ DST_SEL_Z = 2,
+ DST_SEL_W = 3,
+ DST_SEL_0 = 4,
+ DST_SEL_1 = 5,
+ DST_SEL_RSVD = 6,
+ DST_SEL_MASK = 7
+} DstSel;
+#endif /*ENUMS_DstSel_H*/
+
+#ifndef ENUMS_MagFilter_H
+#define ENUMS_MagFilter_H
+typedef enum MagFilter {
+ MAG_FILTER_POINT = 0,
+ MAG_FILTER_LINEAR = 1,
+ MAG_FILTER_RESERVED_0 = 2,
+ MAG_FILTER_USE_FETCH_CONST = 3
+} MagFilter;
+#endif /*ENUMS_MagFilter_H*/
+
+#ifndef ENUMS_MinFilter_H
+#define ENUMS_MinFilter_H
+typedef enum MinFilter {
+ MIN_FILTER_POINT = 0,
+ MIN_FILTER_LINEAR = 1,
+ MIN_FILTER_RESERVED_0 = 2,
+ MIN_FILTER_USE_FETCH_CONST = 3
+} MinFilter;
+#endif /*ENUMS_MinFilter_H*/
+
+#ifndef ENUMS_MipFilter_H
+#define ENUMS_MipFilter_H
+typedef enum MipFilter {
+ MIP_FILTER_POINT = 0,
+ MIP_FILTER_LINEAR = 1,
+ MIP_FILTER_BASEMAP = 2,
+ MIP_FILTER_USE_FETCH_CONST = 3
+} MipFilter;
+#endif /*ENUMS_MipFilter_H*/
+
+#ifndef ENUMS_AnisoFilter_H
+#define ENUMS_AnisoFilter_H
+typedef enum AnisoFilter {
+ ANISO_FILTER_DISABLED = 0,
+ ANISO_FILTER_MAX_1_1 = 1,
+ ANISO_FILTER_MAX_2_1 = 2,
+ ANISO_FILTER_MAX_4_1 = 3,
+ ANISO_FILTER_MAX_8_1 = 4,
+ ANISO_FILTER_MAX_16_1 = 5,
+ ANISO_FILTER_USE_FETCH_CONST = 7
+} AnisoFilter;
+#endif /*ENUMS_AnisoFilter_H*/
+
+#ifndef ENUMS_ArbitraryFilter_H
+#define ENUMS_ArbitraryFilter_H
+typedef enum ArbitraryFilter {
+ ARBITRARY_FILTER_2X4_SYM = 0,
+ ARBITRARY_FILTER_2X4_ASYM = 1,
+ ARBITRARY_FILTER_4X2_SYM = 2,
+ ARBITRARY_FILTER_4X2_ASYM = 3,
+ ARBITRARY_FILTER_4X4_SYM = 4,
+ ARBITRARY_FILTER_4X4_ASYM = 5,
+ ARBITRARY_FILTER_USE_FETCH_CONST = 7
+} ArbitraryFilter;
+#endif /*ENUMS_ArbitraryFilter_H*/
+
+#ifndef ENUMS_VolMagFilter_H
+#define ENUMS_VolMagFilter_H
+typedef enum VolMagFilter {
+ VOL_MAG_FILTER_POINT = 0,
+ VOL_MAG_FILTER_LINEAR = 1,
+ VOL_MAG_FILTER_USE_FETCH_CONST = 3
+} VolMagFilter;
+#endif /*ENUMS_VolMagFilter_H*/
+
+#ifndef ENUMS_VolMinFilter_H
+#define ENUMS_VolMinFilter_H
+typedef enum VolMinFilter {
+ VOL_MIN_FILTER_POINT = 0,
+ VOL_MIN_FILTER_LINEAR = 1,
+ VOL_MIN_FILTER_USE_FETCH_CONST = 3
+} VolMinFilter;
+#endif /*ENUMS_VolMinFilter_H*/
+
+#ifndef ENUMS_PredSelect_H
+#define ENUMS_PredSelect_H
+typedef enum PredSelect {
+ NOT_PREDICATED = 0,
+ PREDICATED = 1
+} PredSelect;
+#endif /*ENUMS_PredSelect_H*/
+
+#ifndef ENUMS_SampleLocation_H
+#define ENUMS_SampleLocation_H
+typedef enum SampleLocation {
+ SAMPLE_CENTROID = 0,
+ SAMPLE_CENTER = 1
+} SampleLocation;
+#endif /*ENUMS_SampleLocation_H*/
+
+#ifndef ENUMS_VertexMode_H
+#define ENUMS_VertexMode_H
+typedef enum VertexMode {
+ POSITION_1_VECTOR = 0,
+ POSITION_2_VECTORS_UNUSED = 1,
+ POSITION_2_VECTORS_SPRITE = 2,
+ POSITION_2_VECTORS_EDGE = 3,
+ POSITION_2_VECTORS_KILL = 4,
+ POSITION_2_VECTORS_SPRITE_KILL = 5,
+ POSITION_2_VECTORS_EDGE_KILL = 6,
+ MULTIPASS = 7
+} VertexMode;
+#endif /*ENUMS_VertexMode_H*/
+
+#ifndef ENUMS_Sample_Cntl_H
+#define ENUMS_Sample_Cntl_H
+typedef enum Sample_Cntl {
+ CENTROIDS_ONLY = 0,
+ CENTERS_ONLY = 1,
+ CENTROIDS_AND_CENTERS = 2,
+ UNDEF = 3
+} Sample_Cntl;
+#endif /*ENUMS_Sample_Cntl_H*/
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+#ifndef ENUMS_MhPerfEncode_H
+#define ENUMS_MhPerfEncode_H
+typedef enum MhPerfEncode {
+ CP_R0_REQUESTS = 0,
+ CP_R1_REQUESTS = 1,
+ CP_R2_REQUESTS = 2,
+ CP_R3_REQUESTS = 3,
+ CP_R4_REQUESTS = 4,
+ CP_TOTAL_READ_REQUESTS = 5,
+ CP_TOTAL_WRITE_REQUESTS = 6,
+ CP_TOTAL_REQUESTS = 7,
+ CP_DATA_BYTES_WRITTEN = 8,
+ CP_WRITE_CLEAN_RESPONSES = 9,
+ CP_R0_READ_BURSTS_RECEIVED = 10,
+ CP_R1_READ_BURSTS_RECEIVED = 11,
+ CP_R2_READ_BURSTS_RECEIVED = 12,
+ CP_R3_READ_BURSTS_RECEIVED = 13,
+ CP_R4_READ_BURSTS_RECEIVED = 14,
+ CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+ CP_R0_DATA_BEATS_READ = 16,
+ CP_R1_DATA_BEATS_READ = 17,
+ CP_R2_DATA_BEATS_READ = 18,
+ CP_R3_DATA_BEATS_READ = 19,
+ CP_R4_DATA_BEATS_READ = 20,
+ CP_TOTAL_DATA_BEATS_READ = 21,
+ VGT_R0_REQUESTS = 22,
+ VGT_R1_REQUESTS = 23,
+ VGT_TOTAL_REQUESTS = 24,
+ VGT_R0_READ_BURSTS_RECEIVED = 25,
+ VGT_R1_READ_BURSTS_RECEIVED = 26,
+ VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+ VGT_R0_DATA_BEATS_READ = 28,
+ VGT_R1_DATA_BEATS_READ = 29,
+ VGT_TOTAL_DATA_BEATS_READ = 30,
+ TC_TOTAL_REQUESTS = 31,
+ TC_ROQ_REQUESTS = 32,
+ TC_INFO_SENT = 33,
+ TC_READ_BURSTS_RECEIVED = 34,
+ TC_DATA_BEATS_READ = 35,
+ TCD_BURSTS_READ = 36,
+ RB_REQUESTS = 37,
+ RB_DATA_BYTES_WRITTEN = 38,
+ RB_WRITE_CLEAN_RESPONSES = 39,
+ AXI_READ_REQUESTS_ID_0 = 40,
+ AXI_READ_REQUESTS_ID_1 = 41,
+ AXI_READ_REQUESTS_ID_2 = 42,
+ AXI_READ_REQUESTS_ID_3 = 43,
+ AXI_READ_REQUESTS_ID_4 = 44,
+ AXI_READ_REQUESTS_ID_5 = 45,
+ AXI_READ_REQUESTS_ID_6 = 46,
+ AXI_READ_REQUESTS_ID_7 = 47,
+ AXI_TOTAL_READ_REQUESTS = 48,
+ AXI_WRITE_REQUESTS_ID_0 = 49,
+ AXI_WRITE_REQUESTS_ID_1 = 50,
+ AXI_WRITE_REQUESTS_ID_2 = 51,
+ AXI_WRITE_REQUESTS_ID_3 = 52,
+ AXI_WRITE_REQUESTS_ID_4 = 53,
+ AXI_WRITE_REQUESTS_ID_5 = 54,
+ AXI_WRITE_REQUESTS_ID_6 = 55,
+ AXI_WRITE_REQUESTS_ID_7 = 56,
+ AXI_TOTAL_WRITE_REQUESTS = 57,
+ AXI_TOTAL_REQUESTS_ID_0 = 58,
+ AXI_TOTAL_REQUESTS_ID_1 = 59,
+ AXI_TOTAL_REQUESTS_ID_2 = 60,
+ AXI_TOTAL_REQUESTS_ID_3 = 61,
+ AXI_TOTAL_REQUESTS_ID_4 = 62,
+ AXI_TOTAL_REQUESTS_ID_5 = 63,
+ AXI_TOTAL_REQUESTS_ID_6 = 64,
+ AXI_TOTAL_REQUESTS_ID_7 = 65,
+ AXI_TOTAL_REQUESTS = 66,
+ AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+ AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+ AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+ AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+ AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+ AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+ AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+ AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+ AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+ AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+ AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+ AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+ AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+ AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+ AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+ AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+ AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+ AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+ AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+ AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+ AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+ AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+ AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+ AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+ TOTAL_MMU_MISSES = 112,
+ MMU_READ_MISSES = 113,
+ MMU_WRITE_MISSES = 114,
+ TOTAL_MMU_HITS = 115,
+ MMU_READ_HITS = 116,
+ MMU_WRITE_HITS = 117,
+ SPLIT_MODE_TC_HITS = 118,
+ SPLIT_MODE_TC_MISSES = 119,
+ SPLIT_MODE_NON_TC_HITS = 120,
+ SPLIT_MODE_NON_TC_MISSES = 121,
+ STALL_AWAITING_TLB_MISS_FETCH = 122,
+ MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+ MMU_TLB_MISS_DATA_BEATS_READ = 124,
+ CP_CYCLES_HELD_OFF = 125,
+ VGT_CYCLES_HELD_OFF = 126,
+ TC_CYCLES_HELD_OFF = 127,
+ TC_ROQ_CYCLES_HELD_OFF = 128,
+ TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+ RB_CYCLES_HELD_OFF = 130,
+ TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+ TLB_MISS_CYCLES_HELD_OFF = 132,
+ AXI_READ_REQUEST_HELD_OFF = 133,
+ AXI_WRITE_REQUEST_HELD_OFF = 134,
+ AXI_REQUEST_HELD_OFF = 135,
+ AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+ AXI_WRITE_DATA_HELD_OFF = 137,
+ CP_SAME_PAGE_BANK_REQUESTS = 138,
+ VGT_SAME_PAGE_BANK_REQUESTS = 139,
+ TC_SAME_PAGE_BANK_REQUESTS = 140,
+ TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+ RB_SAME_PAGE_BANK_REQUESTS = 142,
+ TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+ CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+ VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+ TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+ RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+ TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+ TOTAL_MH_READ_REQUESTS = 149,
+ TOTAL_MH_WRITE_REQUESTS = 150,
+ TOTAL_MH_REQUESTS = 151,
+ MH_BUSY = 152,
+ CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+ VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+ TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+ RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+ TC_ROQ_N_VALID_ENTRIES = 157,
+ ARQ_N_ENTRIES = 158,
+ WDB_N_ENTRIES = 159,
+ MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+ MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+ MC_TOTAL_READ_REQUESTS = 162,
+ ELAPSED_CYCLES_MH_GATED_CLK = 163,
+ ELAPSED_CLK_CYCLES = 164,
+ CP_W_16B_REQUESTS = 165,
+ CP_W_32B_REQUESTS = 166,
+ TC_16B_REQUESTS = 167,
+ TC_32B_REQUESTS = 168,
+ PA_REQUESTS = 169,
+ PA_DATA_BYTES_WRITTEN = 170,
+ PA_WRITE_CLEAN_RESPONSES = 171,
+ PA_CYCLES_HELD_OFF = 172,
+ AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
+ AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
+ AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
+ AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
+ AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
+ AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
+ AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
+ AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
+ AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
+} MhPerfEncode;
+#endif /*ENUMS_MhPerfEncode_H*/
+
+#ifndef ENUMS_MmuClntBeh_H
+#define ENUMS_MmuClntBeh_H
+typedef enum MmuClntBeh {
+ BEH_NEVR = 0,
+ BEH_TRAN_RNG = 1,
+ BEH_TRAN_FLT = 2,
+} MmuClntBeh;
+#endif /*ENUMS_MmuClntBeh_H*/
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H
+#define ENUMS_RBBM_PERFCOUNT1_SEL_H
+typedef enum RBBM_PERFCOUNT1_SEL {
+ RBBM1_COUNT = 0,
+ RBBM1_NRT_BUSY = 1,
+ RBBM1_RB_BUSY = 2,
+ RBBM1_SQ_CNTX0_BUSY = 3,
+ RBBM1_SQ_CNTX17_BUSY = 4,
+ RBBM1_VGT_BUSY = 5,
+ RBBM1_VGT_NODMA_BUSY = 6,
+ RBBM1_PA_BUSY = 7,
+ RBBM1_SC_CNTX_BUSY = 8,
+ RBBM1_TPC_BUSY = 9,
+ RBBM1_TC_BUSY = 10,
+ RBBM1_SX_BUSY = 11,
+ RBBM1_CP_COHER_BUSY = 12,
+ RBBM1_CP_NRT_BUSY = 13,
+ RBBM1_GFX_IDLE_STALL = 14,
+ RBBM1_INTERRUPT = 15,
+} RBBM_PERFCOUNT1_SEL;
+#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+#ifndef ENUMS_CP_PERFCOUNT_SEL_H
+#define ENUMS_CP_PERFCOUNT_SEL_H
+typedef enum CP_PERFCOUNT_SEL {
+ ALWAYS_COUNT = 0,
+ TRANS_FIFO_FULL = 1,
+ TRANS_FIFO_AF = 2,
+ RCIU_PFPTRANS_WAIT = 3,
+ Reserved_04 = 4,
+ Reserved_05 = 5,
+ RCIU_NRTTRANS_WAIT = 6,
+ Reserved_07 = 7,
+ CSF_NRT_READ_WAIT = 8,
+ CSF_I1_FIFO_FULL = 9,
+ CSF_I2_FIFO_FULL = 10,
+ CSF_ST_FIFO_FULL = 11,
+ Reserved_12 = 12,
+ CSF_RING_ROQ_FULL = 13,
+ CSF_I1_ROQ_FULL = 14,
+ CSF_I2_ROQ_FULL = 15,
+ CSF_ST_ROQ_FULL = 16,
+ Reserved_17 = 17,
+ MIU_TAG_MEM_FULL = 18,
+ MIU_WRITECLEAN = 19,
+ Reserved_20 = 20,
+ Reserved_21 = 21,
+ MIU_NRT_WRITE_STALLED = 22,
+ MIU_NRT_READ_STALLED = 23,
+ ME_WRITE_CONFIRM_FIFO_FULL = 24,
+ ME_VS_DEALLOC_FIFO_FULL = 25,
+ ME_PS_DEALLOC_FIFO_FULL = 26,
+ ME_REGS_VS_EVENT_FIFO_FULL = 27,
+ ME_REGS_PS_EVENT_FIFO_FULL = 28,
+ ME_REGS_CF_EVENT_FIFO_FULL = 29,
+ ME_MICRO_RB_STARVED = 30,
+ ME_MICRO_I1_STARVED = 31,
+ ME_MICRO_I2_STARVED = 32,
+ ME_MICRO_ST_STARVED = 33,
+ Reserved_34 = 34,
+ Reserved_35 = 35,
+ Reserved_36 = 36,
+ Reserved_37 = 37,
+ Reserved_38 = 38,
+ Reserved_39 = 39,
+ RCIU_RBBM_DWORD_SENT = 40,
+ ME_BUSY_CLOCKS = 41,
+ ME_WAIT_CONTEXT_AVAIL = 42,
+ PFP_TYPE0_PACKET = 43,
+ PFP_TYPE3_PACKET = 44,
+ CSF_RB_WPTR_NEQ_RPTR = 45,
+ CSF_I1_SIZE_NEQ_ZERO = 46,
+ CSF_I2_SIZE_NEQ_ZERO = 47,
+ CSF_RBI1I2_FETCHING = 48,
+ Reserved_49 = 49,
+ Reserved_50 = 50,
+ Reserved_51 = 51,
+ Reserved_52 = 52,
+ Reserved_53 = 53,
+ Reserved_54 = 54,
+ Reserved_55 = 55,
+ Reserved_56 = 56,
+ Reserved_57 = 57,
+ Reserved_58 = 58,
+ Reserved_59 = 59,
+ Reserved_60 = 60,
+ Reserved_61 = 61,
+ Reserved_62 = 62,
+ Reserved_63 = 63
+} CP_PERFCOUNT_SEL;
+#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+#ifndef ENUMS_ColorformatX_H
+#define ENUMS_ColorformatX_H
+typedef enum ColorformatX {
+ COLORX_4_4_4_4 = 0,
+ COLORX_1_5_5_5 = 1,
+ COLORX_5_6_5 = 2,
+ COLORX_8 = 3,
+ COLORX_8_8 = 4,
+ COLORX_8_8_8_8 = 5,
+ COLORX_S8_8_8_8 = 6,
+ COLORX_16_FLOAT = 7,
+ COLORX_16_16_FLOAT = 8,
+ COLORX_16_16_16_16_FLOAT = 9,
+ COLORX_32_FLOAT = 10,
+ COLORX_32_32_FLOAT = 11,
+ COLORX_32_32_32_32_FLOAT = 12,
+ COLORX_2_3_3 = 13,
+ COLORX_8_8_8 = 14,
+} ColorformatX;
+#endif /*ENUMS_ColorformatX_H*/
+
+#ifndef ENUMS_DepthformatX_H
+#define ENUMS_DepthformatX_H
+typedef enum DepthformatX {
+ DEPTHX_16 = 0,
+ DEPTHX_24_8 = 1
+} DepthformatX;
+#endif /*ENUMS_DepthformatX_H*/
+
+#ifndef ENUMS_CompareFrag_H
+#define ENUMS_CompareFrag_H
+typedef enum CompareFrag {
+ FRAG_NEVER = 0,
+ FRAG_LESS = 1,
+ FRAG_EQUAL = 2,
+ FRAG_LEQUAL = 3,
+ FRAG_GREATER = 4,
+ FRAG_NOTEQUAL = 5,
+ FRAG_GEQUAL = 6,
+ FRAG_ALWAYS = 7
+} CompareFrag;
+#endif /*ENUMS_CompareFrag_H*/
+
+#ifndef ENUMS_CompareRef_H
+#define ENUMS_CompareRef_H
+typedef enum CompareRef {
+ REF_NEVER = 0,
+ REF_LESS = 1,
+ REF_EQUAL = 2,
+ REF_LEQUAL = 3,
+ REF_GREATER = 4,
+ REF_NOTEQUAL = 5,
+ REF_GEQUAL = 6,
+ REF_ALWAYS = 7
+} CompareRef;
+#endif /*ENUMS_CompareRef_H*/
+
+#ifndef ENUMS_StencilOp_H
+#define ENUMS_StencilOp_H
+typedef enum StencilOp {
+ STENCIL_KEEP = 0,
+ STENCIL_ZERO = 1,
+ STENCIL_REPLACE = 2,
+ STENCIL_INCR_CLAMP = 3,
+ STENCIL_DECR_CLAMP = 4,
+ STENCIL_INVERT = 5,
+ STENCIL_INCR_WRAP = 6,
+ STENCIL_DECR_WRAP = 7
+} StencilOp;
+#endif /*ENUMS_StencilOp_H*/
+
+#ifndef ENUMS_BlendOpX_H
+#define ENUMS_BlendOpX_H
+typedef enum BlendOpX {
+ BLENDX_ZERO = 0,
+ BLENDX_ONE = 1,
+ BLENDX_SRC_COLOR = 4,
+ BLENDX_ONE_MINUS_SRC_COLOR = 5,
+ BLENDX_SRC_ALPHA = 6,
+ BLENDX_ONE_MINUS_SRC_ALPHA = 7,
+ BLENDX_DST_COLOR = 8,
+ BLENDX_ONE_MINUS_DST_COLOR = 9,
+ BLENDX_DST_ALPHA = 10,
+ BLENDX_ONE_MINUS_DST_ALPHA = 11,
+ BLENDX_CONSTANT_COLOR = 12,
+ BLENDX_ONE_MINUS_CONSTANT_COLOR = 13,
+ BLENDX_CONSTANT_ALPHA = 14,
+ BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15,
+ BLENDX_SRC_ALPHA_SATURATE = 16,
+} BlendOpX;
+#endif /*ENUMS_BlendOpX_H*/
+
+#ifndef ENUMS_CombFuncX_H
+#define ENUMS_CombFuncX_H
+typedef enum CombFuncX {
+ COMB_DST_PLUS_SRC = 0,
+ COMB_SRC_MINUS_DST = 1,
+ COMB_MIN_DST_SRC = 2,
+ COMB_MAX_DST_SRC = 3,
+ COMB_DST_MINUS_SRC = 4,
+ COMB_DST_PLUS_SRC_BIAS = 5,
+} CombFuncX;
+#endif /*ENUMS_CombFuncX_H*/
+
+#ifndef ENUMS_DitherModeX_H
+#define ENUMS_DitherModeX_H
+typedef enum DitherModeX {
+ DITHER_DISABLE = 0,
+ DITHER_ALWAYS = 1,
+ DITHER_IF_ALPHA_OFF = 2,
+} DitherModeX;
+#endif /*ENUMS_DitherModeX_H*/
+
+#ifndef ENUMS_DitherTypeX_H
+#define ENUMS_DitherTypeX_H
+typedef enum DitherTypeX {
+ DITHER_PIXEL = 0,
+ DITHER_SUBPIXEL = 1,
+} DitherTypeX;
+#endif /*ENUMS_DitherTypeX_H*/
+
+#ifndef ENUMS_EdramMode_H
+#define ENUMS_EdramMode_H
+typedef enum EdramMode {
+ EDRAM_NOP = 0,
+ COLOR_DEPTH = 4,
+ DEPTH_ONLY = 5,
+ EDRAM_COPY = 6,
+} EdramMode;
+#endif /*ENUMS_EdramMode_H*/
+
+#ifndef ENUMS_SurfaceEndian_H
+#define ENUMS_SurfaceEndian_H
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0,
+ ENDIAN_8IN16 = 1,
+ ENDIAN_8IN32 = 2,
+ ENDIAN_16IN32 = 3,
+ ENDIAN_8IN64 = 4,
+ ENDIAN_8IN128 = 5,
+} SurfaceEndian;
+#endif /*ENUMS_SurfaceEndian_H*/
+
+#ifndef ENUMS_EdramSizeX_H
+#define ENUMS_EdramSizeX_H
+typedef enum EdramSizeX {
+ EDRAMSIZE_16KB = 0,
+ EDRAMSIZE_32KB = 1,
+ EDRAMSIZE_64KB = 2,
+ EDRAMSIZE_128KB = 3,
+ EDRAMSIZE_256KB = 4,
+ EDRAMSIZE_512KB = 5,
+ EDRAMSIZE_1MB = 6,
+ EDRAMSIZE_2MB = 7,
+ EDRAMSIZE_4MB = 8,
+ EDRAMSIZE_8MB = 9,
+ EDRAMSIZE_16MB = 10,
+} EdramSizeX;
+#endif /*ENUMS_EdramSizeX_H*/
+
+#ifndef ENUMS_RB_PERFCNT_SELECT_H
+#define ENUMS_RB_PERFCNT_SELECT_H
+typedef enum RB_PERFCNT_SELECT {
+ RBPERF_CNTX_BUSY = 0,
+ RBPERF_CNTX_BUSY_MAX = 1,
+ RBPERF_SX_QUAD_STARVED = 2,
+ RBPERF_SX_QUAD_STARVED_MAX = 3,
+ RBPERF_GA_GC_CH0_SYS_REQ = 4,
+ RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+ RBPERF_GA_GC_CH1_SYS_REQ = 6,
+ RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+ RBPERF_MH_STARVED = 8,
+ RBPERF_MH_STARVED_MAX = 9,
+ RBPERF_AZ_BC_COLOR_BUSY = 10,
+ RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+ RBPERF_AZ_BC_Z_BUSY = 12,
+ RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+ RBPERF_RB_SC_TILE_RTR_N = 14,
+ RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+ RBPERF_RB_SC_SAMP_RTR_N = 16,
+ RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+ RBPERF_RB_SX_QUAD_RTR_N = 18,
+ RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+ RBPERF_RB_SX_COLOR_RTR_N = 20,
+ RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+ RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+ RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+ RBPERF_ZXP_STALL = 24,
+ RBPERF_ZXP_STALL_MAX = 25,
+ RBPERF_EVENT_PENDING = 26,
+ RBPERF_EVENT_PENDING_MAX = 27,
+ RBPERF_RB_MH_VALID = 28,
+ RBPERF_RB_MH_VALID_MAX = 29,
+ RBPERF_SX_RB_QUAD_SEND = 30,
+ RBPERF_SX_RB_COLOR_SEND = 31,
+ RBPERF_SC_RB_TILE_SEND = 32,
+ RBPERF_SC_RB_SAMPLE_SEND = 33,
+ RBPERF_SX_RB_MEM_EXPORT = 34,
+ RBPERF_SX_RB_QUAD_EVENT = 35,
+ RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+ RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+ RBPERF_RB_SC_EZ_SEND = 38,
+ RBPERF_RB_SX_INDEX_SEND = 39,
+ RBPERF_GMEM_INTFO_RD = 40,
+ RBPERF_GMEM_INTF1_RD = 41,
+ RBPERF_GMEM_INTFO_WR = 42,
+ RBPERF_GMEM_INTF1_WR = 43,
+ RBPERF_RB_CP_CONTEXT_DONE = 44,
+ RBPERF_RB_CP_CACHE_FLUSH = 45,
+ RBPERF_ZPASS_DONE = 46,
+ RBPERF_ZCMD_VALID = 47,
+ RBPERF_CCMD_VALID = 48,
+ RBPERF_ACCUM_GRANT = 49,
+ RBPERF_ACCUM_C0_GRANT = 50,
+ RBPERF_ACCUM_C1_GRANT = 51,
+ RBPERF_ACCUM_FULL_BE_WR = 52,
+ RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+ RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+ RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+ RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+} RB_PERFCNT_SELECT;
+#endif /*ENUMS_RB_PERFCNT_SELECT_H*/
+
+#ifndef ENUMS_DepthFormat_H
+#define ENUMS_DepthFormat_H
+typedef enum DepthFormat {
+ DEPTH_24_8 = 22,
+ DEPTH_24_8_FLOAT = 23,
+ DEPTH_16 = 24,
+} DepthFormat;
+#endif /*ENUMS_DepthFormat_H*/
+
+#ifndef ENUMS_SurfaceSwap_H
+#define ENUMS_SurfaceSwap_H
+typedef enum SurfaceSwap {
+ SWAP_LOWRED = 0,
+ SWAP_LOWBLUE = 1
+} SurfaceSwap;
+#endif /*ENUMS_SurfaceSwap_H*/
+
+#ifndef ENUMS_DepthArray_H
+#define ENUMS_DepthArray_H
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0,
+ ARRAY_2D_DEPTH = 1,
+} DepthArray;
+#endif /*ENUMS_DepthArray_H*/
+
+#ifndef ENUMS_ColorArray_H
+#define ENUMS_ColorArray_H
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0,
+ ARRAY_2D_COLOR = 1,
+ ARRAY_3D_SLICE_COLOR = 3
+} ColorArray;
+#endif /*ENUMS_ColorArray_H*/
+
+#ifndef ENUMS_ColorFormat_H
+#define ENUMS_ColorFormat_H
+typedef enum ColorFormat {
+ COLOR_8 = 2,
+ COLOR_1_5_5_5 = 3,
+ COLOR_5_6_5 = 4,
+ COLOR_6_5_5 = 5,
+ COLOR_8_8_8_8 = 6,
+ COLOR_2_10_10_10 = 7,
+ COLOR_8_A = 8,
+ COLOR_8_B = 9,
+ COLOR_8_8 = 10,
+ COLOR_8_8_8 = 11,
+ COLOR_8_8_8_8_A = 14,
+ COLOR_4_4_4_4 = 15,
+ COLOR_10_11_11 = 16,
+ COLOR_11_11_10 = 17,
+ COLOR_16 = 24,
+ COLOR_16_16 = 25,
+ COLOR_16_16_16_16 = 26,
+ COLOR_16_FLOAT = 30,
+ COLOR_16_16_FLOAT = 31,
+ COLOR_16_16_16_16_FLOAT = 32,
+ COLOR_32_FLOAT = 36,
+ COLOR_32_32_FLOAT = 37,
+ COLOR_32_32_32_32_FLOAT = 38,
+ COLOR_2_3_3 = 39,
+} ColorFormat;
+#endif /*ENUMS_ColorFormat_H*/
+
+#ifndef ENUMS_SurfaceNumber_H
+#define ENUMS_SurfaceNumber_H
+typedef enum SurfaceNumber {
+ NUMBER_UREPEAT = 0,
+ NUMBER_SREPEAT = 1,
+ NUMBER_UINTEGER = 2,
+ NUMBER_SINTEGER = 3,
+ NUMBER_GAMMA = 4,
+ NUMBER_FIXED = 5,
+ NUMBER_FLOAT = 7
+} SurfaceNumber;
+#endif /*ENUMS_SurfaceNumber_H*/
+
+#ifndef ENUMS_SurfaceFormat_H
+#define ENUMS_SurfaceFormat_H
+typedef enum SurfaceFormat {
+ FMT_1_REVERSE = 0,
+ FMT_1 = 1,
+ FMT_8 = 2,
+ FMT_1_5_5_5 = 3,
+ FMT_5_6_5 = 4,
+ FMT_6_5_5 = 5,
+ FMT_8_8_8_8 = 6,
+ FMT_2_10_10_10 = 7,
+ FMT_8_A = 8,
+ FMT_8_B = 9,
+ FMT_8_8 = 10,
+ FMT_Cr_Y1_Cb_Y0 = 11,
+ FMT_Y1_Cr_Y0_Cb = 12,
+ FMT_5_5_5_1 = 13,
+ FMT_8_8_8_8_A = 14,
+ FMT_4_4_4_4 = 15,
+ FMT_8_8_8 = 16,
+ FMT_DXT1 = 18,
+ FMT_DXT2_3 = 19,
+ FMT_DXT4_5 = 20,
+ FMT_10_10_10_2 = 21,
+ FMT_24_8 = 22,
+ FMT_16 = 24,
+ FMT_16_16 = 25,
+ FMT_16_16_16_16 = 26,
+ FMT_16_EXPAND = 27,
+ FMT_16_16_EXPAND = 28,
+ FMT_16_16_16_16_EXPAND = 29,
+ FMT_16_FLOAT = 30,
+ FMT_16_16_FLOAT = 31,
+ FMT_16_16_16_16_FLOAT = 32,
+ FMT_32 = 33,
+ FMT_32_32 = 34,
+ FMT_32_32_32_32 = 35,
+ FMT_32_FLOAT = 36,
+ FMT_32_32_FLOAT = 37,
+ FMT_32_32_32_32_FLOAT = 38,
+ FMT_ATI_TC_RGB = 39,
+ FMT_ATI_TC_RGBA = 40,
+ FMT_ATI_TC_555_565_RGB = 41,
+ FMT_ATI_TC_555_565_RGBA = 42,
+ FMT_ATI_TC_RGBA_INTERP = 43,
+ FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+ FMT_ETC1_RGBA_INTERP = 46,
+ FMT_ETC1_RGB = 47,
+ FMT_ETC1_RGBA = 48,
+ FMT_DXN = 49,
+ FMT_2_3_3 = 51,
+ FMT_2_10_10_10_AS_16_16_16_16 = 54,
+ FMT_10_10_10_2_AS_16_16_16_16 = 55,
+ FMT_32_32_32_FLOAT = 57,
+ FMT_DXT3A = 58,
+ FMT_DXT5A = 59,
+ FMT_CTX1 = 60,
+} SurfaceFormat;
+#endif /*ENUMS_SurfaceFormat_H*/
+
+#ifndef ENUMS_SurfaceTiling_H
+#define ENUMS_SurfaceTiling_H
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0,
+ ARRAY_TILED = 1
+} SurfaceTiling;
+#endif /*ENUMS_SurfaceTiling_H*/
+
+#ifndef ENUMS_SurfaceArray_H
+#define ENUMS_SurfaceArray_H
+typedef enum SurfaceArray {
+ ARRAY_1D = 0,
+ ARRAY_2D = 1,
+ ARRAY_3D = 2,
+ ARRAY_3D_SLICE = 3
+} SurfaceArray;
+#endif /*ENUMS_SurfaceArray_H*/
+
+#ifndef ENUMS_SurfaceNumberX_H
+#define ENUMS_SurfaceNumberX_H
+typedef enum SurfaceNumberX {
+ NUMBERX_UREPEAT = 0,
+ NUMBERX_SREPEAT = 1,
+ NUMBERX_UINTEGER = 2,
+ NUMBERX_SINTEGER = 3,
+ NUMBERX_FLOAT = 7
+} SurfaceNumberX;
+#endif /*ENUMS_SurfaceNumberX_H*/
+
+#ifndef ENUMS_ColorArrayX_H
+#define ENUMS_ColorArrayX_H
+typedef enum ColorArrayX {
+ ARRAYX_2D_COLOR = 0,
+ ARRAYX_3D_SLICE_COLOR = 1,
+} ColorArrayX;
+#endif /*ENUMS_ColorArrayX_H*/
+
+#endif /*_yamato_ENUM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h
new file mode 100644
index 00000000000..87a454a1e38
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h
@@ -0,0 +1,1703 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_ENUMTYPE(SU_PERFCNT_SELECT)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0)
+    GENERATE_ENUM(UNUSED1, 1)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3)
+    GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4)
+    GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6)
+    GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11)
+    GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13)
+    GENERATE_ENUM(UNUSED2, 14)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15)
+    GENERATE_ENUM(UNUSED3, 16)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19)
+    GENERATE_ENUM(UNUSED4, 20)
+    GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21)
+    GENERATE_ENUM(UNUSED5, 22)
+    GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34)
+    GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36)
+    GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38)
+    GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44)
+    GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45)
+    GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48)
+    GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49)
+    GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50)
+    GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51)
+    GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55)
+    GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64)
+    GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67)
+    GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70)
+    GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76)
+    GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79)
+    GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83)
+    GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90)
+    GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94)
+    GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95)
+    GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96)
+    GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97)
+    GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98)
+    GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99)
+    GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100)
+    GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101)
+    GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102)
+END_ENUMTYPE(SU_PERFCNT_SELECT)
+
+START_ENUMTYPE(SC_PERFCNT_SELECT)
+    GENERATE_ENUM(SC_SR_WINDOW_VALID, 0)
+    GENERATE_ENUM(SC_CW_WINDOW_VALID, 1)
+    GENERATE_ENUM(SC_QM_WINDOW_VALID, 2)
+    GENERATE_ENUM(SC_FW_WINDOW_VALID, 3)
+    GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4)
+    GENERATE_ENUM(SC_IT_WINDOW_VALID, 5)
+    GENERATE_ENUM(SC_STARVED_BY_PA, 6)
+    GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7)
+    GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8)
+    GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9)
+    GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10)
+    GENERATE_ENUM(SC_STALLED_BY_SQ, 11)
+    GENERATE_ENUM(SC_STALLED_BY_SP, 12)
+    GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13)
+    GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14)
+    GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15)
+    GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16)
+    GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17)
+END_ENUMTYPE(SC_PERFCNT_SELECT)
+
+START_ENUMTYPE(VGT_DI_PRIM_TYPE)
+    GENERATE_ENUM(DI_PT_NONE, 0)
+    GENERATE_ENUM(DI_PT_POINTLIST, 1)
+    GENERATE_ENUM(DI_PT_LINELIST, 2)
+    GENERATE_ENUM(DI_PT_LINESTRIP, 3)
+    GENERATE_ENUM(DI_PT_TRILIST, 4)
+    GENERATE_ENUM(DI_PT_TRIFAN, 5)
+    GENERATE_ENUM(DI_PT_TRISTRIP, 6)
+    GENERATE_ENUM(DI_PT_UNUSED_1, 7)
+    GENERATE_ENUM(DI_PT_RECTLIST, 8)
+    GENERATE_ENUM(DI_PT_UNUSED_2, 9)
+    GENERATE_ENUM(DI_PT_UNUSED_3, 10)
+    GENERATE_ENUM(DI_PT_UNUSED_4, 11)
+    GENERATE_ENUM(DI_PT_UNUSED_5, 12)
+    GENERATE_ENUM(DI_PT_QUADLIST, 13)
+    GENERATE_ENUM(DI_PT_QUADSTRIP, 14)
+    GENERATE_ENUM(DI_PT_POLYGON, 15)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18)
+    GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19)
+    GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20)
+    GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21)
+    GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22)
+END_ENUMTYPE(VGT_DI_PRIM_TYPE)
+
+START_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+    GENERATE_ENUM(DI_SRC_SEL_DMA, 0)
+    GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1)
+    GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2)
+    GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3)
+END_ENUMTYPE(VGT_DI_SOURCE_SELECT)
+
+START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_ENUM(DI_FACE_CULL_NONE, 0)
+    GENERATE_ENUM(DI_FACE_CULL_FETCH, 1)
+    GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2)
+    GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3)
+END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT)
+
+START_ENUMTYPE(VGT_DI_INDEX_SIZE)
+    GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1)
+END_ENUMTYPE(VGT_DI_INDEX_SIZE)
+
+START_ENUMTYPE(VGT_DI_SMALL_INDEX)
+    GENERATE_ENUM(DI_USE_INDEX_SIZE, 0)
+    GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1)
+END_ENUMTYPE(VGT_DI_SMALL_INDEX)
+
+START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0)
+    GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0)
+    GENERATE_ENUM(GRP_CULL_ENABLE, 1)
+END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE)
+
+START_ENUMTYPE(VGT_EVENT_TYPE)
+    GENERATE_ENUM(VS_DEALLOC, 0)
+    GENERATE_ENUM(PS_DEALLOC, 1)
+    GENERATE_ENUM(VS_DONE_TS, 2)
+    GENERATE_ENUM(PS_DONE_TS, 3)
+    GENERATE_ENUM(CACHE_FLUSH_TS, 4)
+    GENERATE_ENUM(CONTEXT_DONE, 5)
+    GENERATE_ENUM(CACHE_FLUSH, 6)
+    GENERATE_ENUM(VIZQUERY_START, 7)
+    GENERATE_ENUM(VIZQUERY_END, 8)
+    GENERATE_ENUM(SC_WAIT_WC, 9)
+    GENERATE_ENUM(RST_PIX_CNT, 13)
+    GENERATE_ENUM(RST_VTX_CNT, 14)
+    GENERATE_ENUM(TILE_FLUSH, 15)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20)
+    GENERATE_ENUM(ZPASS_DONE, 21)
+    GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22)
+    GENERATE_ENUM(PERFCOUNTER_START, 23)
+    GENERATE_ENUM(PERFCOUNTER_STOP, 24)
+    GENERATE_ENUM(VS_FETCH_DONE, 27)
+    GENERATE_ENUM(FACENESS_FLUSH, 28)
+END_ENUMTYPE(VGT_EVENT_TYPE)
+
+START_ENUMTYPE(VGT_DMA_SWAP_MODE)
+    GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0)
+    GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1)
+    GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2)
+    GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3)
+END_ENUMTYPE(VGT_DMA_SWAP_MODE)
+
+START_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0)
+    GENERATE_ENUM(VGT_SQ_SEND, 1)
+    GENERATE_ENUM(VGT_SQ_STALLED, 2)
+    GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3)
+    GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4)
+    GENERATE_ENUM(VGT_SQ_STATIC, 5)
+    GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6)
+    GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10)
+    GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11)
+    GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15)
+    GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16)
+    GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20)
+    GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21)
+    GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23)
+    GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25)
+    GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27)
+    GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28)
+    GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29)
+    GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30)
+    GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31)
+    GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32)
+    GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33)
+    GENERATE_ENUM(SPARE34, 34)
+    GENERATE_ENUM(SPARE35, 35)
+    GENERATE_ENUM(SPARE36, 36)
+    GENERATE_ENUM(SPARE37, 37)
+    GENERATE_ENUM(SPARE38, 38)
+    GENERATE_ENUM(SPARE39, 39)
+    GENERATE_ENUM(TE_SU_IN_VALID, 40)
+    GENERATE_ENUM(TE_SU_IN_READ, 41)
+    GENERATE_ENUM(TE_SU_IN_PRIM, 42)
+    GENERATE_ENUM(TE_SU_IN_EOP, 43)
+    GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44)
+    GENERATE_ENUM(TE_WK_IN_VALID, 45)
+    GENERATE_ENUM(TE_WK_IN_READ, 46)
+    GENERATE_ENUM(TE_OUT_PRIM_VALID, 47)
+    GENERATE_ENUM(TE_OUT_PRIM_READ, 48)
+END_ENUMTYPE(VGT_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+    GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0)
+    GENERATE_ENUM(reserved_46, 1)
+    GENERATE_ENUM(reserved_47, 2)
+    GENERATE_ENUM(reserved_48, 3)
+    GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4)
+    GENERATE_ENUM(OPMUX0_L2_WRITES, 5)
+    GENERATE_ENUM(reserved_49, 6)
+    GENERATE_ENUM(reserved_50, 7)
+    GENERATE_ENUM(reserved_51, 8)
+END_ENUMTYPE(TCR_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TP_PERFCOUNT_SELECT)
+    GENERATE_ENUM(POINT_QUADS, 0)
+    GENERATE_ENUM(BILIN_QUADS, 1)
+    GENERATE_ENUM(ANISO_QUADS, 2)
+    GENERATE_ENUM(MIP_QUADS, 3)
+    GENERATE_ENUM(VOL_QUADS, 4)
+    GENERATE_ENUM(MIP_VOL_QUADS, 5)
+    GENERATE_ENUM(MIP_ANISO_QUADS, 6)
+    GENERATE_ENUM(VOL_ANISO_QUADS, 7)
+    GENERATE_ENUM(ANISO_2_1_QUADS, 8)
+    GENERATE_ENUM(ANISO_4_1_QUADS, 9)
+    GENERATE_ENUM(ANISO_6_1_QUADS, 10)
+    GENERATE_ENUM(ANISO_8_1_QUADS, 11)
+    GENERATE_ENUM(ANISO_10_1_QUADS, 12)
+    GENERATE_ENUM(ANISO_12_1_QUADS, 13)
+    GENERATE_ENUM(ANISO_14_1_QUADS, 14)
+    GENERATE_ENUM(ANISO_16_1_QUADS, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16)
+    GENERATE_ENUM(ALIGN_2_QUADS, 17)
+    GENERATE_ENUM(ALIGN_4_QUADS, 18)
+    GENERATE_ENUM(PIX_0_QUAD, 19)
+    GENERATE_ENUM(PIX_1_QUAD, 20)
+    GENERATE_ENUM(PIX_2_QUAD, 21)
+    GENERATE_ENUM(PIX_3_QUAD, 22)
+    GENERATE_ENUM(PIX_4_QUAD, 23)
+    GENERATE_ENUM(TP_MIPMAP_LOD0, 24)
+    GENERATE_ENUM(TP_MIPMAP_LOD1, 25)
+    GENERATE_ENUM(TP_MIPMAP_LOD2, 26)
+    GENERATE_ENUM(TP_MIPMAP_LOD3, 27)
+    GENERATE_ENUM(TP_MIPMAP_LOD4, 28)
+    GENERATE_ENUM(TP_MIPMAP_LOD5, 29)
+    GENERATE_ENUM(TP_MIPMAP_LOD6, 30)
+    GENERATE_ENUM(TP_MIPMAP_LOD7, 31)
+    GENERATE_ENUM(TP_MIPMAP_LOD8, 32)
+    GENERATE_ENUM(TP_MIPMAP_LOD9, 33)
+    GENERATE_ENUM(TP_MIPMAP_LOD10, 34)
+    GENERATE_ENUM(TP_MIPMAP_LOD11, 35)
+    GENERATE_ENUM(TP_MIPMAP_LOD12, 36)
+    GENERATE_ENUM(TP_MIPMAP_LOD13, 37)
+    GENERATE_ENUM(TP_MIPMAP_LOD14, 38)
+END_ENUMTYPE(TP_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0)
+    GENERATE_ENUM(reserved_01, 1)
+    GENERATE_ENUM(reserved_02, 2)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5)
+    GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6)
+    GENERATE_ENUM(reserved_07, 7)
+    GENERATE_ENUM(reserved_08, 8)
+    GENERATE_ENUM(reserved_09, 9)
+    GENERATE_ENUM(reserved_10, 10)
+    GENERATE_ENUM(reserved_11, 11)
+    GENERATE_ENUM(reserved_12, 12)
+    GENERATE_ENUM(reserved_13, 13)
+    GENERATE_ENUM(reserved_14, 14)
+    GENERATE_ENUM(reserved_15, 15)
+    GENERATE_ENUM(reserved_16, 16)
+    GENERATE_ENUM(reserved_17, 17)
+    GENERATE_ENUM(reserved_18, 18)
+    GENERATE_ENUM(reserved_19, 19)
+    GENERATE_ENUM(reserved_20, 20)
+    GENERATE_ENUM(reserved_21, 21)
+    GENERATE_ENUM(reserved_22, 22)
+    GENERATE_ENUM(reserved_23, 23)
+    GENERATE_ENUM(reserved_24, 24)
+    GENERATE_ENUM(reserved_25, 25)
+    GENERATE_ENUM(reserved_26, 26)
+    GENERATE_ENUM(reserved_27, 27)
+    GENERATE_ENUM(READ_STARVED_QUAD0, 28)
+    GENERATE_ENUM(reserved_29, 29)
+    GENERATE_ENUM(reserved_30, 30)
+    GENERATE_ENUM(reserved_31, 31)
+    GENERATE_ENUM(READ_STARVED, 32)
+    GENERATE_ENUM(READ_STALLED_QUAD0, 33)
+    GENERATE_ENUM(reserved_34, 34)
+    GENERATE_ENUM(reserved_35, 35)
+    GENERATE_ENUM(reserved_36, 36)
+    GENERATE_ENUM(READ_STALLED, 37)
+    GENERATE_ENUM(VALID_READ_QUAD0, 38)
+    GENERATE_ENUM(reserved_39, 39)
+    GENERATE_ENUM(reserved_40, 40)
+    GENERATE_ENUM(reserved_41, 41)
+    GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42)
+    GENERATE_ENUM(reserved_43, 43)
+    GENERATE_ENUM(reserved_44, 44)
+    GENERATE_ENUM(reserved_45, 45)
+    GENERATE_ENUM(TC_TP_STARVED, 46)
+END_ENUMTYPE(TCM_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+    GENERATE_ENUM(VALID_CYCLES, 0)
+    GENERATE_ENUM(SINGLE_PHASES, 1)
+    GENERATE_ENUM(ANISO_PHASES, 2)
+    GENERATE_ENUM(MIP_PHASES, 3)
+    GENERATE_ENUM(VOL_PHASES, 4)
+    GENERATE_ENUM(MIP_VOL_PHASES, 5)
+    GENERATE_ENUM(MIP_ANISO_PHASES, 6)
+    GENERATE_ENUM(VOL_ANISO_PHASES, 7)
+    GENERATE_ENUM(ANISO_2_1_PHASES, 8)
+    GENERATE_ENUM(ANISO_4_1_PHASES, 9)
+    GENERATE_ENUM(ANISO_6_1_PHASES, 10)
+    GENERATE_ENUM(ANISO_8_1_PHASES, 11)
+    GENERATE_ENUM(ANISO_10_1_PHASES, 12)
+    GENERATE_ENUM(ANISO_12_1_PHASES, 13)
+    GENERATE_ENUM(ANISO_14_1_PHASES, 14)
+    GENERATE_ENUM(ANISO_16_1_PHASES, 15)
+    GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16)
+    GENERATE_ENUM(ALIGN_2_PHASES, 17)
+    GENERATE_ENUM(ALIGN_4_PHASES, 18)
+    GENERATE_ENUM(TPC_BUSY, 19)
+    GENERATE_ENUM(TPC_STALLED, 20)
+    GENERATE_ENUM(TPC_STARVED, 21)
+    GENERATE_ENUM(TPC_WORKING, 22)
+    GENERATE_ENUM(TPC_WALKER_BUSY, 23)
+    GENERATE_ENUM(TPC_WALKER_STALLED, 24)
+    GENERATE_ENUM(TPC_WALKER_WORKING, 25)
+    GENERATE_ENUM(TPC_ALIGNER_BUSY, 26)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED, 27)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28)
+    GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29)
+    GENERATE_ENUM(TPC_ALIGNER_WORKING, 30)
+    GENERATE_ENUM(TPC_BLEND_BUSY, 31)
+    GENERATE_ENUM(TPC_BLEND_SYNC, 32)
+    GENERATE_ENUM(TPC_BLEND_STARVED, 33)
+    GENERATE_ENUM(TPC_BLEND_WORKING, 34)
+    GENERATE_ENUM(OPCODE_0x00, 35)
+    GENERATE_ENUM(OPCODE_0x01, 36)
+    GENERATE_ENUM(OPCODE_0x04, 37)
+    GENERATE_ENUM(OPCODE_0x10, 38)
+    GENERATE_ENUM(OPCODE_0x11, 39)
+    GENERATE_ENUM(OPCODE_0x12, 40)
+    GENERATE_ENUM(OPCODE_0x13, 41)
+    GENERATE_ENUM(OPCODE_0x18, 42)
+    GENERATE_ENUM(OPCODE_0x19, 43)
+    GENERATE_ENUM(OPCODE_0x1A, 44)
+    GENERATE_ENUM(OPCODE_OTHER, 45)
+    GENERATE_ENUM(IN_FIFO_0_EMPTY, 56)
+    GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57)
+    GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58)
+    GENERATE_ENUM(IN_FIFO_0_FULL, 59)
+    GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72)
+    GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73)
+    GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74)
+    GENERATE_ENUM(IN_FIFO_TPC_FULL, 75)
+    GENERATE_ENUM(TPC_TC_XFC, 76)
+    GENERATE_ENUM(TPC_TC_STATE, 77)
+    GENERATE_ENUM(TC_STALL, 78)
+    GENERATE_ENUM(QUAD0_TAPS, 79)
+    GENERATE_ENUM(QUADS, 83)
+    GENERATE_ENUM(TCA_SYNC_STALL, 84)
+    GENERATE_ENUM(TAG_STALL, 85)
+    GENERATE_ENUM(TCB_SYNC_STALL, 88)
+    GENERATE_ENUM(TCA_VALID, 89)
+    GENERATE_ENUM(PROBES_VALID, 90)
+    GENERATE_ENUM(MISS_STALL, 91)
+    GENERATE_ENUM(FETCH_FIFO_STALL, 92)
+    GENERATE_ENUM(TCO_STALL, 93)
+    GENERATE_ENUM(ANY_STALL, 94)
+    GENERATE_ENUM(TAG_MISSES, 95)
+    GENERATE_ENUM(TAG_HITS, 96)
+    GENERATE_ENUM(SUB_TAG_MISSES, 97)
+    GENERATE_ENUM(SET0_INVALIDATES, 98)
+    GENERATE_ENUM(SET1_INVALIDATES, 99)
+    GENERATE_ENUM(SET2_INVALIDATES, 100)
+    GENERATE_ENUM(SET3_INVALIDATES, 101)
+    GENERATE_ENUM(SET0_TAG_MISSES, 102)
+    GENERATE_ENUM(SET1_TAG_MISSES, 103)
+    GENERATE_ENUM(SET2_TAG_MISSES, 104)
+    GENERATE_ENUM(SET3_TAG_MISSES, 105)
+    GENERATE_ENUM(SET0_TAG_HITS, 106)
+    GENERATE_ENUM(SET1_TAG_HITS, 107)
+    GENERATE_ENUM(SET2_TAG_HITS, 108)
+    GENERATE_ENUM(SET3_TAG_HITS, 109)
+    GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110)
+    GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111)
+    GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112)
+    GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113)
+    GENERATE_ENUM(SET0_EVICT1, 114)
+    GENERATE_ENUM(SET0_EVICT2, 115)
+    GENERATE_ENUM(SET0_EVICT3, 116)
+    GENERATE_ENUM(SET0_EVICT4, 117)
+    GENERATE_ENUM(SET0_EVICT5, 118)
+    GENERATE_ENUM(SET0_EVICT6, 119)
+    GENERATE_ENUM(SET0_EVICT7, 120)
+    GENERATE_ENUM(SET0_EVICT8, 121)
+    GENERATE_ENUM(SET1_EVICT1, 130)
+    GENERATE_ENUM(SET1_EVICT2, 131)
+    GENERATE_ENUM(SET1_EVICT3, 132)
+    GENERATE_ENUM(SET1_EVICT4, 133)
+    GENERATE_ENUM(SET1_EVICT5, 134)
+    GENERATE_ENUM(SET1_EVICT6, 135)
+    GENERATE_ENUM(SET1_EVICT7, 136)
+    GENERATE_ENUM(SET1_EVICT8, 137)
+    GENERATE_ENUM(SET2_EVICT1, 146)
+    GENERATE_ENUM(SET2_EVICT2, 147)
+    GENERATE_ENUM(SET2_EVICT3, 148)
+    GENERATE_ENUM(SET2_EVICT4, 149)
+    GENERATE_ENUM(SET2_EVICT5, 150)
+    GENERATE_ENUM(SET2_EVICT6, 151)
+    GENERATE_ENUM(SET2_EVICT7, 152)
+    GENERATE_ENUM(SET2_EVICT8, 153)
+    GENERATE_ENUM(SET3_EVICT1, 162)
+    GENERATE_ENUM(SET3_EVICT2, 163)
+    GENERATE_ENUM(SET3_EVICT3, 164)
+    GENERATE_ENUM(SET3_EVICT4, 165)
+    GENERATE_ENUM(SET3_EVICT5, 166)
+    GENERATE_ENUM(SET3_EVICT6, 167)
+    GENERATE_ENUM(SET3_EVICT7, 168)
+    GENERATE_ENUM(SET3_EVICT8, 169)
+    GENERATE_ENUM(FF_EMPTY, 178)
+    GENERATE_ENUM(FF_LT_HALF_FULL, 179)
+    GENERATE_ENUM(FF_HALF_FULL, 180)
+    GENERATE_ENUM(FF_FULL, 181)
+    GENERATE_ENUM(FF_XFC, 182)
+    GENERATE_ENUM(FF_STALLED, 183)
+    GENERATE_ENUM(FG_MASKS, 184)
+    GENERATE_ENUM(FG_LEFT_MASKS, 185)
+    GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186)
+    GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187)
+    GENERATE_ENUM(FG_LEFT_FG_STALL, 188)
+    GENERATE_ENUM(FG_LEFT_SECTORS, 189)
+    GENERATE_ENUM(FG0_REQUESTS, 195)
+    GENERATE_ENUM(FG0_STALLED, 196)
+    GENERATE_ENUM(MEM_REQ512, 199)
+    GENERATE_ENUM(MEM_REQ_SENT, 200)
+    GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202)
+    GENERATE_ENUM(TC0_MH_STALLED, 203)
+END_ENUMTYPE(TCF_PERFCOUNT_SELECT)
+
+START_ENUMTYPE(SQ_PERFCNT_SELECT)
+    GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0)
+    GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9)
+    GENERATE_ENUM(SQ_EXPORT_CYCLES, 10)
+    GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11)
+    GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12)
+    GENERATE_ENUM(SQ_ALU_CST_STALL, 13)
+    GENERATE_ENUM(SQ_ALU_TEX_STALL, 14)
+    GENERATE_ENUM(SQ_INST_WRITTEN, 15)
+    GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16)
+    GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18)
+    GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20)
+    GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21)
+    GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22)
+    GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23)
+    GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24)
+    GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25)
+    GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26)
+    GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27)
+    GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28)
+    GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33)
+    GENERATE_ENUM(SQ_ALU_NOPS, 34)
+    GENERATE_ENUM(SQ_PRED_SKIP, 35)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41)
+    GENERATE_ENUM(SQ_GPR_STALL_VTX, 42)
+    GENERATE_ENUM(SQ_GPR_STALL_PIX, 43)
+    GENERATE_ENUM(SQ_VTX_RS_STALL, 44)
+    GENERATE_ENUM(SQ_PIX_RS_STALL, 45)
+    GENERATE_ENUM(SQ_SX_PC_FULL, 46)
+    GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47)
+    GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48)
+    GENERATE_ENUM(SQ_INTERP_QUADS, 49)
+    GENERATE_ENUM(SQ_INTERP_ACTIVE, 50)
+    GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51)
+    GENERATE_ENUM(SQ_IN_VTX_STALL, 52)
+    GENERATE_ENUM(SQ_VTX_CNT, 53)
+    GENERATE_ENUM(SQ_VTX_VECTOR2, 54)
+    GENERATE_ENUM(SQ_VTX_VECTOR3, 55)
+    GENERATE_ENUM(SQ_VTX_VECTOR4, 56)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58)
+    GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61)
+    GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65)
+    GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68)
+    GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72)
+    GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73)
+    GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78)
+    GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80)
+    GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81)
+    GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82)
+    GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83)
+    GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84)
+    GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85)
+    GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92)
+    GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93)
+    GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94)
+    GENERATE_ENUM(VC_PERF_STATIC, 95)
+    GENERATE_ENUM(VC_PERF_STALLED, 96)
+    GENERATE_ENUM(VC_PERF_STARVED, 97)
+    GENERATE_ENUM(VC_PERF_SEND, 98)
+    GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99)
+    GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100)
+    GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101)
+    GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102)
+    GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103)
+    GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104)
+    GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105)
+    GENERATE_ENUM(PTRBUFF_EF_PUSH, 106)
+    GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107)
+    GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108)
+    GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111)
+    GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112)
+    GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113)
+    GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114)
+    GENERATE_ENUM(PTRBUFF_PI_RTR, 115)
+    GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116)
+    GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117)
+    GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118)
+    GENERATE_ENUM(PTRBUFF_SQ_DEC, 119)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120)
+    GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121)
+    GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122)
+    GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123)
+    GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124)
+    GENERATE_ENUM(PTRBUFF_END_BUFFER, 125)
+    GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126)
+    GENERATE_ENUM(VERTS_WRITTEN_SPI, 127)
+    GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128)
+    GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129)
+    GENERATE_ENUM(TP_DATA_RETURN, 130)
+    GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131)
+    GENERATE_ENUM(SPI_WRITES_SP, 132)
+    GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133)
+    GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134)
+    GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135)
+    GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136)
+    GENERATE_ENUM(SP_EXPORTS_TO_SX, 137)
+    GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138)
+    GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139)
+    GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140)
+    GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141)
+    GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142)
+    GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143)
+    GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144)
+    GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145)
+    GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146)
+    GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147)
+    GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148)
+    GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149)
+    GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150)
+    GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151)
+    GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152)
+    GENERATE_ENUM(SQ_PIX_TOTAL, 153)
+    GENERATE_ENUM(SQ_PIX_KILLED, 154)
+END_ENUMTYPE(SQ_PERFCNT_SELECT)
+
+START_ENUMTYPE(SX_PERFCNT_SELECT)
+    GENERATE_ENUM(SX_EXPORT_VECTORS, 0)
+    GENERATE_ENUM(SX_DUMMY_QUADS, 1)
+    GENERATE_ENUM(SX_ALPHA_FAIL, 2)
+    GENERATE_ENUM(SX_RB_QUAD_BUSY, 3)
+    GENERATE_ENUM(SX_RB_COLOR_BUSY, 4)
+    GENERATE_ENUM(SX_RB_QUAD_STALL, 5)
+    GENERATE_ENUM(SX_RB_COLOR_STALL, 6)
+END_ENUMTYPE(SX_PERFCNT_SELECT)
+
+START_ENUMTYPE(Abs_modifier)
+    GENERATE_ENUM(NO_ABS_MOD, 0)
+    GENERATE_ENUM(ABS_MOD, 1)
+END_ENUMTYPE(Abs_modifier)
+
+START_ENUMTYPE(Exporting)
+    GENERATE_ENUM(NOT_EXPORTING, 0)
+    GENERATE_ENUM(EXPORTING, 1)
+END_ENUMTYPE(Exporting)
+
+START_ENUMTYPE(ScalarOpcode)
+    GENERATE_ENUM(ADDs, 0)
+    GENERATE_ENUM(ADD_PREVs, 1)
+    GENERATE_ENUM(MULs, 2)
+    GENERATE_ENUM(MUL_PREVs, 3)
+    GENERATE_ENUM(MUL_PREV2s, 4)
+    GENERATE_ENUM(MAXs, 5)
+    GENERATE_ENUM(MINs, 6)
+    GENERATE_ENUM(SETEs, 7)
+    GENERATE_ENUM(SETGTs, 8)
+    GENERATE_ENUM(SETGTEs, 9)
+    GENERATE_ENUM(SETNEs, 10)
+    GENERATE_ENUM(FRACs, 11)
+    GENERATE_ENUM(TRUNCs, 12)
+    GENERATE_ENUM(FLOORs, 13)
+    GENERATE_ENUM(EXP_IEEE, 14)
+    GENERATE_ENUM(LOG_CLAMP, 15)
+    GENERATE_ENUM(LOG_IEEE, 16)
+    GENERATE_ENUM(RECIP_CLAMP, 17)
+    GENERATE_ENUM(RECIP_FF, 18)
+    GENERATE_ENUM(RECIP_IEEE, 19)
+    GENERATE_ENUM(RECIPSQ_CLAMP, 20)
+    GENERATE_ENUM(RECIPSQ_FF, 21)
+    GENERATE_ENUM(RECIPSQ_IEEE, 22)
+    GENERATE_ENUM(MOVAs, 23)
+    GENERATE_ENUM(MOVA_FLOORs, 24)
+    GENERATE_ENUM(SUBs, 25)
+    GENERATE_ENUM(SUB_PREVs, 26)
+    GENERATE_ENUM(PRED_SETEs, 27)
+    GENERATE_ENUM(PRED_SETNEs, 28)
+    GENERATE_ENUM(PRED_SETGTs, 29)
+    GENERATE_ENUM(PRED_SETGTEs, 30)
+    GENERATE_ENUM(PRED_SET_INVs, 31)
+    GENERATE_ENUM(PRED_SET_POPs, 32)
+    GENERATE_ENUM(PRED_SET_CLRs, 33)
+    GENERATE_ENUM(PRED_SET_RESTOREs, 34)
+    GENERATE_ENUM(KILLEs, 35)
+    GENERATE_ENUM(KILLGTs, 36)
+    GENERATE_ENUM(KILLGTEs, 37)
+    GENERATE_ENUM(KILLNEs, 38)
+    GENERATE_ENUM(KILLONEs, 39)
+    GENERATE_ENUM(SQRT_IEEE, 40)
+    GENERATE_ENUM(MUL_CONST_0, 42)
+    GENERATE_ENUM(MUL_CONST_1, 43)
+    GENERATE_ENUM(ADD_CONST_0, 44)
+    GENERATE_ENUM(ADD_CONST_1, 45)
+    GENERATE_ENUM(SUB_CONST_0, 46)
+    GENERATE_ENUM(SUB_CONST_1, 47)
+    GENERATE_ENUM(SIN, 48)
+    GENERATE_ENUM(COS, 49)
+    GENERATE_ENUM(RETAIN_PREV, 50)
+END_ENUMTYPE(ScalarOpcode)
+
+START_ENUMTYPE(SwizzleType)
+    GENERATE_ENUM(NO_SWIZZLE, 0)
+    GENERATE_ENUM(SHIFT_RIGHT_1, 1)
+    GENERATE_ENUM(SHIFT_RIGHT_2, 2)
+    GENERATE_ENUM(SHIFT_RIGHT_3, 3)
+END_ENUMTYPE(SwizzleType)
+
+START_ENUMTYPE(InputModifier)
+    GENERATE_ENUM(NIL, 0)
+    GENERATE_ENUM(NEGATE, 1)
+END_ENUMTYPE(InputModifier)
+
+START_ENUMTYPE(PredicateSelect)
+    GENERATE_ENUM(NO_PREDICATION, 0)
+    GENERATE_ENUM(PREDICATE_QUAD, 1)
+    GENERATE_ENUM(PREDICATED_2, 2)
+    GENERATE_ENUM(PREDICATED_3, 3)
+END_ENUMTYPE(PredicateSelect)
+
+START_ENUMTYPE(OperandSelect1)
+    GENERATE_ENUM(ABSOLUTE_REG, 0)
+    GENERATE_ENUM(RELATIVE_REG, 1)
+END_ENUMTYPE(OperandSelect1)
+
+START_ENUMTYPE(VectorOpcode)
+    GENERATE_ENUM(ADDv, 0)
+    GENERATE_ENUM(MULv, 1)
+    GENERATE_ENUM(MAXv, 2)
+    GENERATE_ENUM(MINv, 3)
+    GENERATE_ENUM(SETEv, 4)
+    GENERATE_ENUM(SETGTv, 5)
+    GENERATE_ENUM(SETGTEv, 6)
+    GENERATE_ENUM(SETNEv, 7)
+    GENERATE_ENUM(FRACv, 8)
+    GENERATE_ENUM(TRUNCv, 9)
+    GENERATE_ENUM(FLOORv, 10)
+    GENERATE_ENUM(MULADDv, 11)
+    GENERATE_ENUM(CNDEv, 12)
+    GENERATE_ENUM(CNDGTEv, 13)
+    GENERATE_ENUM(CNDGTv, 14)
+    GENERATE_ENUM(DOT4v, 15)
+    GENERATE_ENUM(DOT3v, 16)
+    GENERATE_ENUM(DOT2ADDv, 17)
+    GENERATE_ENUM(CUBEv, 18)
+    GENERATE_ENUM(MAX4v, 19)
+    GENERATE_ENUM(PRED_SETE_PUSHv, 20)
+    GENERATE_ENUM(PRED_SETNE_PUSHv, 21)
+    GENERATE_ENUM(PRED_SETGT_PUSHv, 22)
+    GENERATE_ENUM(PRED_SETGTE_PUSHv, 23)
+    GENERATE_ENUM(KILLEv, 24)
+    GENERATE_ENUM(KILLGTv, 25)
+    GENERATE_ENUM(KILLGTEv, 26)
+    GENERATE_ENUM(KILLNEv, 27)
+    GENERATE_ENUM(DSTv, 28)
+    GENERATE_ENUM(MOVAv, 29)
+END_ENUMTYPE(VectorOpcode)
+
+START_ENUMTYPE(OperandSelect0)
+    GENERATE_ENUM(CONSTANT, 0)
+    GENERATE_ENUM(NON_CONSTANT, 1)
+END_ENUMTYPE(OperandSelect0)
+
+START_ENUMTYPE(Ressource_type)
+    GENERATE_ENUM(ALU, 0)
+    GENERATE_ENUM(TEXTURE, 1)
+END_ENUMTYPE(Ressource_type)
+
+START_ENUMTYPE(Instruction_serial)
+    GENERATE_ENUM(NOT_SERIAL, 0)
+    GENERATE_ENUM(SERIAL, 1)
+END_ENUMTYPE(Instruction_serial)
+
+START_ENUMTYPE(VC_type)
+    GENERATE_ENUM(ALU_TP_REQUEST, 0)
+    GENERATE_ENUM(VC_REQUEST, 1)
+END_ENUMTYPE(VC_type)
+
+START_ENUMTYPE(Addressing)
+    GENERATE_ENUM(RELATIVE_ADDR, 0)
+    GENERATE_ENUM(ABSOLUTE_ADDR, 1)
+END_ENUMTYPE(Addressing)
+
+START_ENUMTYPE(CFOpcode)
+    GENERATE_ENUM(NOP, 0)
+    GENERATE_ENUM(EXECUTE, 1)
+    GENERATE_ENUM(EXECUTE_END, 2)
+    GENERATE_ENUM(COND_EXECUTE, 3)
+    GENERATE_ENUM(COND_EXECUTE_END, 4)
+    GENERATE_ENUM(COND_PRED_EXECUTE, 5)
+    GENERATE_ENUM(COND_PRED_EXECUTE_END, 6)
+    GENERATE_ENUM(LOOP_START, 7)
+    GENERATE_ENUM(LOOP_END, 8)
+    GENERATE_ENUM(COND_CALL, 9)
+    GENERATE_ENUM(RETURN, 10)
+    GENERATE_ENUM(COND_JMP, 11)
+    GENERATE_ENUM(ALLOCATE, 12)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13)
+    GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14)
+    GENERATE_ENUM(MARK_VS_FETCH_DONE, 15)
+END_ENUMTYPE(CFOpcode)
+
+START_ENUMTYPE(Allocation_type)
+    GENERATE_ENUM(SQ_NO_ALLOC, 0)
+    GENERATE_ENUM(SQ_POSITION, 1)
+    GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2)
+    GENERATE_ENUM(SQ_MEMORY, 3)
+END_ENUMTYPE(Allocation_type)
+
+START_ENUMTYPE(TexInstOpcode)
+    GENERATE_ENUM(TEX_INST_FETCH, 1)
+    GENERATE_ENUM(TEX_INST_RESERVED_1, 2)
+    GENERATE_ENUM(TEX_INST_RESERVED_2, 3)
+    GENERATE_ENUM(TEX_INST_RESERVED_3, 4)
+    GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16)
+    GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17)
+    GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18)
+    GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19)
+    GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25)
+    GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26)
+    GENERATE_ENUM(TEX_INST_RESERVED_4, 27)
+END_ENUMTYPE(TexInstOpcode)
+
+START_ENUMTYPE(Addressmode)
+    GENERATE_ENUM(LOGICAL, 0)
+    GENERATE_ENUM(LOOP_RELATIVE, 1)
+END_ENUMTYPE(Addressmode)
+
+START_ENUMTYPE(TexCoordDenorm)
+    GENERATE_ENUM(TEX_COORD_NORMALIZED, 0)
+    GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1)
+END_ENUMTYPE(TexCoordDenorm)
+
+START_ENUMTYPE(SrcSel)
+    GENERATE_ENUM(SRC_SEL_X, 0)
+    GENERATE_ENUM(SRC_SEL_Y, 1)
+    GENERATE_ENUM(SRC_SEL_Z, 2)
+    GENERATE_ENUM(SRC_SEL_W, 3)
+END_ENUMTYPE(SrcSel)
+
+START_ENUMTYPE(DstSel)
+    GENERATE_ENUM(DST_SEL_X, 0)
+    GENERATE_ENUM(DST_SEL_Y, 1)
+    GENERATE_ENUM(DST_SEL_Z, 2)
+    GENERATE_ENUM(DST_SEL_W, 3)
+    GENERATE_ENUM(DST_SEL_0, 4)
+    GENERATE_ENUM(DST_SEL_1, 5)
+    GENERATE_ENUM(DST_SEL_RSVD, 6)
+    GENERATE_ENUM(DST_SEL_MASK, 7)
+END_ENUMTYPE(DstSel)
+
+START_ENUMTYPE(MagFilter)
+    GENERATE_ENUM(MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MagFilter)
+
+START_ENUMTYPE(MinFilter)
+    GENERATE_ENUM(MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2)
+    GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MinFilter)
+
+START_ENUMTYPE(MipFilter)
+    GENERATE_ENUM(MIP_FILTER_POINT, 0)
+    GENERATE_ENUM(MIP_FILTER_LINEAR, 1)
+    GENERATE_ENUM(MIP_FILTER_BASEMAP, 2)
+    GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(MipFilter)
+
+START_ENUMTYPE(AnisoFilter)
+    GENERATE_ENUM(ANISO_FILTER_DISABLED, 0)
+    GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1)
+    GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2)
+    GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3)
+    GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4)
+    GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5)
+    GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(AnisoFilter)
+
+START_ENUMTYPE(ArbitraryFilter)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0)
+    GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4)
+    GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5)
+    GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7)
+END_ENUMTYPE(ArbitraryFilter)
+
+START_ENUMTYPE(VolMagFilter)
+    GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMagFilter)
+
+START_ENUMTYPE(VolMinFilter)
+    GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0)
+    GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1)
+    GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3)
+END_ENUMTYPE(VolMinFilter)
+
+START_ENUMTYPE(PredSelect)
+    GENERATE_ENUM(NOT_PREDICATED, 0)
+    GENERATE_ENUM(PREDICATED, 1)
+END_ENUMTYPE(PredSelect)
+
+START_ENUMTYPE(SampleLocation)
+    GENERATE_ENUM(SAMPLE_CENTROID, 0)
+    GENERATE_ENUM(SAMPLE_CENTER, 1)
+END_ENUMTYPE(SampleLocation)
+
+START_ENUMTYPE(VertexMode)
+    GENERATE_ENUM(POSITION_1_VECTOR, 0)
+    GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3)
+    GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4)
+    GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5)
+    GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6)
+    GENERATE_ENUM(MULTIPASS, 7)
+END_ENUMTYPE(VertexMode)
+
+START_ENUMTYPE(Sample_Cntl)
+    GENERATE_ENUM(CENTROIDS_ONLY, 0)
+    GENERATE_ENUM(CENTERS_ONLY, 1)
+    GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2)
+    GENERATE_ENUM(UNDEF, 3)
+END_ENUMTYPE(Sample_Cntl)
+
+START_ENUMTYPE(MhPerfEncode)
+    GENERATE_ENUM(CP_R0_REQUESTS, 0)
+    GENERATE_ENUM(CP_R1_REQUESTS, 1)
+    GENERATE_ENUM(CP_R2_REQUESTS, 2)
+    GENERATE_ENUM(CP_R3_REQUESTS, 3)
+    GENERATE_ENUM(CP_R4_REQUESTS, 4)
+    GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5)
+    GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6)
+    GENERATE_ENUM(CP_TOTAL_REQUESTS, 7)
+    GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8)
+    GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9)
+    GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10)
+    GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11)
+    GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12)
+    GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13)
+    GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14)
+    GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15)
+    GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16)
+    GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17)
+    GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18)
+    GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19)
+    GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20)
+    GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21)
+    GENERATE_ENUM(VGT_R0_REQUESTS, 22)
+    GENERATE_ENUM(VGT_R1_REQUESTS, 23)
+    GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24)
+    GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25)
+    GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26)
+    GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27)
+    GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28)
+    GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29)
+    GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30)
+    GENERATE_ENUM(TC_TOTAL_REQUESTS, 31)
+    GENERATE_ENUM(TC_ROQ_REQUESTS, 32)
+    GENERATE_ENUM(TC_INFO_SENT, 33)
+    GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34)
+    GENERATE_ENUM(TC_DATA_BEATS_READ, 35)
+    GENERATE_ENUM(TCD_BURSTS_READ, 36)
+    GENERATE_ENUM(RB_REQUESTS, 37)
+    GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38)
+    GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46)
+    GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55)
+    GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56)
+    GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65)
+    GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73)
+    GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82)
+    GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83)
+    GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101)
+    GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110)
+    GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111)
+    GENERATE_ENUM(TOTAL_MMU_MISSES, 112)
+    GENERATE_ENUM(MMU_READ_MISSES, 113)
+    GENERATE_ENUM(MMU_WRITE_MISSES, 114)
+    GENERATE_ENUM(TOTAL_MMU_HITS, 115)
+    GENERATE_ENUM(MMU_READ_HITS, 116)
+    GENERATE_ENUM(MMU_WRITE_HITS, 117)
+    GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118)
+    GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120)
+    GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121)
+    GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122)
+    GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123)
+    GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124)
+    GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125)
+    GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127)
+    GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128)
+    GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129)
+    GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130)
+    GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131)
+    GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132)
+    GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133)
+    GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135)
+    GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136)
+    GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140)
+    GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143)
+    GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144)
+    GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145)
+    GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146)
+    GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147)
+    GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148)
+    GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149)
+    GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150)
+    GENERATE_ENUM(TOTAL_MH_REQUESTS, 151)
+    GENERATE_ENUM(MH_BUSY, 152)
+    GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153)
+    GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154)
+    GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155)
+    GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156)
+    GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157)
+    GENERATE_ENUM(ARQ_N_ENTRIES, 158)
+    GENERATE_ENUM(WDB_N_ENTRIES, 159)
+    GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160)
+    GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161)
+    GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162)
+    GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163)
+    GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164)
+    GENERATE_ENUM(CP_W_16B_REQUESTS, 165)
+    GENERATE_ENUM(CP_W_32B_REQUESTS, 166)
+    GENERATE_ENUM(TC_16B_REQUESTS, 167)
+    GENERATE_ENUM(TC_32B_REQUESTS, 168)
+    GENERATE_ENUM(PA_REQUESTS, 169)
+    GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170)
+    GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171)
+    GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179)
+    GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180)
+    GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181)
+END_ENUMTYPE(MhPerfEncode)
+
+START_ENUMTYPE(MmuClntBeh)
+    GENERATE_ENUM(BEH_NEVR, 0)
+    GENERATE_ENUM(BEH_TRAN_RNG, 1)
+    GENERATE_ENUM(BEH_TRAN_FLT, 2)
+END_ENUMTYPE(MmuClntBeh)
+
+START_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+    GENERATE_ENUM(RBBM1_COUNT, 0)
+    GENERATE_ENUM(RBBM1_NRT_BUSY, 1)
+    GENERATE_ENUM(RBBM1_RB_BUSY, 2)
+    GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3)
+    GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4)
+    GENERATE_ENUM(RBBM1_VGT_BUSY, 5)
+    GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6)
+    GENERATE_ENUM(RBBM1_PA_BUSY, 7)
+    GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8)
+    GENERATE_ENUM(RBBM1_TPC_BUSY, 9)
+    GENERATE_ENUM(RBBM1_TC_BUSY, 10)
+    GENERATE_ENUM(RBBM1_SX_BUSY, 11)
+    GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12)
+    GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13)
+    GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14)
+    GENERATE_ENUM(RBBM1_INTERRUPT, 15)
+END_ENUMTYPE(RBBM_PERFCOUNT1_SEL)
+
+START_ENUMTYPE(CP_PERFCOUNT_SEL)
+    GENERATE_ENUM(ALWAYS_COUNT, 0)
+    GENERATE_ENUM(TRANS_FIFO_FULL, 1)
+    GENERATE_ENUM(TRANS_FIFO_AF, 2)
+    GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3)
+    GENERATE_ENUM(Reserved_04, 4)
+    GENERATE_ENUM(Reserved_05, 5)
+    GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6)
+    GENERATE_ENUM(Reserved_07, 7)
+    GENERATE_ENUM(CSF_NRT_READ_WAIT, 8)
+    GENERATE_ENUM(CSF_I1_FIFO_FULL, 9)
+    GENERATE_ENUM(CSF_I2_FIFO_FULL, 10)
+    GENERATE_ENUM(CSF_ST_FIFO_FULL, 11)
+    GENERATE_ENUM(Reserved_12, 12)
+    GENERATE_ENUM(CSF_RING_ROQ_FULL, 13)
+    GENERATE_ENUM(CSF_I1_ROQ_FULL, 14)
+    GENERATE_ENUM(CSF_I2_ROQ_FULL, 15)
+    GENERATE_ENUM(CSF_ST_ROQ_FULL, 16)
+    GENERATE_ENUM(Reserved_17, 17)
+    GENERATE_ENUM(MIU_TAG_MEM_FULL, 18)
+    GENERATE_ENUM(MIU_WRITECLEAN, 19)
+    GENERATE_ENUM(Reserved_20, 20)
+    GENERATE_ENUM(Reserved_21, 21)
+    GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22)
+    GENERATE_ENUM(MIU_NRT_READ_STALLED, 23)
+    GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24)
+    GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25)
+    GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26)
+    GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27)
+    GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28)
+    GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29)
+    GENERATE_ENUM(ME_MICRO_RB_STARVED, 30)
+    GENERATE_ENUM(ME_MICRO_I1_STARVED, 31)
+    GENERATE_ENUM(ME_MICRO_I2_STARVED, 32)
+    GENERATE_ENUM(ME_MICRO_ST_STARVED, 33)
+    GENERATE_ENUM(Reserved_34, 34)
+    GENERATE_ENUM(Reserved_35, 35)
+    GENERATE_ENUM(Reserved_36, 36)
+    GENERATE_ENUM(Reserved_37, 37)
+    GENERATE_ENUM(Reserved_38, 38)
+    GENERATE_ENUM(Reserved_39, 39)
+    GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40)
+    GENERATE_ENUM(ME_BUSY_CLOCKS, 41)
+    GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42)
+    GENERATE_ENUM(PFP_TYPE0_PACKET, 43)
+    GENERATE_ENUM(PFP_TYPE3_PACKET, 44)
+    GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45)
+    GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46)
+    GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47)
+    GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48)
+    GENERATE_ENUM(Reserved_49, 49)
+    GENERATE_ENUM(Reserved_50, 50)
+    GENERATE_ENUM(Reserved_51, 51)
+    GENERATE_ENUM(Reserved_52, 52)
+    GENERATE_ENUM(Reserved_53, 53)
+    GENERATE_ENUM(Reserved_54, 54)
+    GENERATE_ENUM(Reserved_55, 55)
+    GENERATE_ENUM(Reserved_56, 56)
+    GENERATE_ENUM(Reserved_57, 57)
+    GENERATE_ENUM(Reserved_58, 58)
+    GENERATE_ENUM(Reserved_59, 59)
+    GENERATE_ENUM(Reserved_60, 60)
+    GENERATE_ENUM(Reserved_61, 61)
+    GENERATE_ENUM(Reserved_62, 62)
+    GENERATE_ENUM(Reserved_63, 63)
+END_ENUMTYPE(CP_PERFCOUNT_SEL)
+
+START_ENUMTYPE(ColorformatX)
+    GENERATE_ENUM(COLORX_4_4_4_4, 0)
+    GENERATE_ENUM(COLORX_1_5_5_5, 1)
+    GENERATE_ENUM(COLORX_5_6_5, 2)
+    GENERATE_ENUM(COLORX_8, 3)
+    GENERATE_ENUM(COLORX_8_8, 4)
+    GENERATE_ENUM(COLORX_8_8_8_8, 5)
+    GENERATE_ENUM(COLORX_S8_8_8_8, 6)
+    GENERATE_ENUM(COLORX_16_FLOAT, 7)
+    GENERATE_ENUM(COLORX_16_16_FLOAT, 8)
+    GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9)
+    GENERATE_ENUM(COLORX_32_FLOAT, 10)
+    GENERATE_ENUM(COLORX_32_32_FLOAT, 11)
+    GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12)
+    GENERATE_ENUM(COLORX_2_3_3, 13)
+    GENERATE_ENUM(COLORX_8_8_8, 14)
+END_ENUMTYPE(ColorformatX)
+
+START_ENUMTYPE(DepthformatX)
+    GENERATE_ENUM(DEPTHX_16, 0)
+    GENERATE_ENUM(DEPTHX_24_8, 1)
+END_ENUMTYPE(DepthformatX)
+
+START_ENUMTYPE(CompareFrag)
+    GENERATE_ENUM(FRAG_NEVER, 0)
+    GENERATE_ENUM(FRAG_LESS, 1)
+    GENERATE_ENUM(FRAG_EQUAL, 2)
+    GENERATE_ENUM(FRAG_LEQUAL, 3)
+    GENERATE_ENUM(FRAG_GREATER, 4)
+    GENERATE_ENUM(FRAG_NOTEQUAL, 5)
+    GENERATE_ENUM(FRAG_GEQUAL, 6)
+    GENERATE_ENUM(FRAG_ALWAYS, 7)
+END_ENUMTYPE(CompareFrag)
+
+START_ENUMTYPE(CompareRef)
+    GENERATE_ENUM(REF_NEVER, 0)
+    GENERATE_ENUM(REF_LESS, 1)
+    GENERATE_ENUM(REF_EQUAL, 2)
+    GENERATE_ENUM(REF_LEQUAL, 3)
+    GENERATE_ENUM(REF_GREATER, 4)
+    GENERATE_ENUM(REF_NOTEQUAL, 5)
+    GENERATE_ENUM(REF_GEQUAL, 6)
+    GENERATE_ENUM(REF_ALWAYS, 7)
+END_ENUMTYPE(CompareRef)
+
+START_ENUMTYPE(StencilOp)
+    GENERATE_ENUM(STENCIL_KEEP, 0)
+    GENERATE_ENUM(STENCIL_ZERO, 1)
+    GENERATE_ENUM(STENCIL_REPLACE, 2)
+    GENERATE_ENUM(STENCIL_INCR_CLAMP, 3)
+    GENERATE_ENUM(STENCIL_DECR_CLAMP, 4)
+    GENERATE_ENUM(STENCIL_INVERT, 5)
+    GENERATE_ENUM(STENCIL_INCR_WRAP, 6)
+    GENERATE_ENUM(STENCIL_DECR_WRAP, 7)
+END_ENUMTYPE(StencilOp)
+
+START_ENUMTYPE(BlendOpX)
+    GENERATE_ENUM(BLENDX_ZERO, 0)
+    GENERATE_ENUM(BLENDX_ONE, 1)
+    GENERATE_ENUM(BLENDX_SRC_COLOR, 4)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA, 6)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7)
+    GENERATE_ENUM(BLENDX_DST_COLOR, 8)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9)
+    GENERATE_ENUM(BLENDX_DST_ALPHA, 10)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11)
+    GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13)
+    GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14)
+    GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15)
+    GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16)
+END_ENUMTYPE(BlendOpX)
+
+START_ENUMTYPE(CombFuncX)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC, 0)
+    GENERATE_ENUM(COMB_SRC_MINUS_DST, 1)
+    GENERATE_ENUM(COMB_MIN_DST_SRC, 2)
+    GENERATE_ENUM(COMB_MAX_DST_SRC, 3)
+    GENERATE_ENUM(COMB_DST_MINUS_SRC, 4)
+    GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5)
+END_ENUMTYPE(CombFuncX)
+
+START_ENUMTYPE(DitherModeX)
+    GENERATE_ENUM(DITHER_DISABLE, 0)
+    GENERATE_ENUM(DITHER_ALWAYS, 1)
+    GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2)
+END_ENUMTYPE(DitherModeX)
+
+START_ENUMTYPE(DitherTypeX)
+    GENERATE_ENUM(DITHER_PIXEL, 0)
+    GENERATE_ENUM(DITHER_SUBPIXEL, 1)
+END_ENUMTYPE(DitherTypeX)
+
+START_ENUMTYPE(EdramMode)
+    GENERATE_ENUM(EDRAM_NOP, 0)
+    GENERATE_ENUM(COLOR_DEPTH, 4)
+    GENERATE_ENUM(DEPTH_ONLY, 5)
+    GENERATE_ENUM(EDRAM_COPY, 6)
+END_ENUMTYPE(EdramMode)
+
+START_ENUMTYPE(SurfaceEndian)
+    GENERATE_ENUM(ENDIAN_NONE, 0)
+    GENERATE_ENUM(ENDIAN_8IN16, 1)
+    GENERATE_ENUM(ENDIAN_8IN32, 2)
+    GENERATE_ENUM(ENDIAN_16IN32, 3)
+    GENERATE_ENUM(ENDIAN_8IN64, 4)
+    GENERATE_ENUM(ENDIAN_8IN128, 5)
+END_ENUMTYPE(SurfaceEndian)
+
+START_ENUMTYPE(EdramSizeX)
+    GENERATE_ENUM(EDRAMSIZE_16KB, 0)
+    GENERATE_ENUM(EDRAMSIZE_32KB, 1)
+    GENERATE_ENUM(EDRAMSIZE_64KB, 2)
+    GENERATE_ENUM(EDRAMSIZE_128KB, 3)
+    GENERATE_ENUM(EDRAMSIZE_256KB, 4)
+    GENERATE_ENUM(EDRAMSIZE_512KB, 5)
+    GENERATE_ENUM(EDRAMSIZE_1MB, 6)
+    GENERATE_ENUM(EDRAMSIZE_2MB, 7)
+    GENERATE_ENUM(EDRAMSIZE_4MB, 8)
+    GENERATE_ENUM(EDRAMSIZE_8MB, 9)
+    GENERATE_ENUM(EDRAMSIZE_16MB, 10)
+END_ENUMTYPE(EdramSizeX)
+
+START_ENUMTYPE(RB_PERFCNT_SELECT)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY, 0)
+    GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2)
+    GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4)
+    GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6)
+    GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7)
+    GENERATE_ENUM(RBPERF_MH_STARVED, 8)
+    GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10)
+    GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12)
+    GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14)
+    GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18)
+    GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20)
+    GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22)
+    GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23)
+    GENERATE_ENUM(RBPERF_ZXP_STALL, 24)
+    GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING, 26)
+    GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID, 28)
+    GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30)
+    GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32)
+    GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33)
+    GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34)
+    GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36)
+    GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37)
+    GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38)
+    GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41)
+    GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42)
+    GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43)
+    GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44)
+    GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45)
+    GENERATE_ENUM(RBPERF_ZPASS_DONE, 46)
+    GENERATE_ENUM(RBPERF_ZCMD_VALID, 47)
+    GENERATE_ENUM(RBPERF_CCMD_VALID, 48)
+    GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49)
+    GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50)
+    GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51)
+    GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52)
+    GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53)
+    GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54)
+    GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55)
+    GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56)
+END_ENUMTYPE(RB_PERFCNT_SELECT)
+
+START_ENUMTYPE(DepthFormat)
+    GENERATE_ENUM(DEPTH_24_8, 22)
+    GENERATE_ENUM(DEPTH_24_8_FLOAT, 23)
+    GENERATE_ENUM(DEPTH_16, 24)
+END_ENUMTYPE(DepthFormat)
+
+START_ENUMTYPE(SurfaceSwap)
+    GENERATE_ENUM(SWAP_LOWRED, 0)
+    GENERATE_ENUM(SWAP_LOWBLUE, 1)
+END_ENUMTYPE(SurfaceSwap)
+
+START_ENUMTYPE(DepthArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0)
+    GENERATE_ENUM(ARRAY_2D_DEPTH, 1)
+END_ENUMTYPE(DepthArray)
+
+START_ENUMTYPE(ColorArray)
+    GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0)
+    GENERATE_ENUM(ARRAY_2D_COLOR, 1)
+    GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3)
+END_ENUMTYPE(ColorArray)
+
+START_ENUMTYPE(ColorFormat)
+    GENERATE_ENUM(COLOR_8, 2)
+    GENERATE_ENUM(COLOR_1_5_5_5, 3)
+    GENERATE_ENUM(COLOR_5_6_5, 4)
+    GENERATE_ENUM(COLOR_6_5_5, 5)
+    GENERATE_ENUM(COLOR_8_8_8_8, 6)
+    GENERATE_ENUM(COLOR_2_10_10_10, 7)
+    GENERATE_ENUM(COLOR_8_A, 8)
+    GENERATE_ENUM(COLOR_8_B, 9)
+    GENERATE_ENUM(COLOR_8_8, 10)
+    GENERATE_ENUM(COLOR_8_8_8, 11)
+    GENERATE_ENUM(COLOR_8_8_8_8_A, 14)
+    GENERATE_ENUM(COLOR_4_4_4_4, 15)
+    GENERATE_ENUM(COLOR_10_11_11, 16)
+    GENERATE_ENUM(COLOR_11_11_10, 17)
+    GENERATE_ENUM(COLOR_16, 24)
+    GENERATE_ENUM(COLOR_16_16, 25)
+    GENERATE_ENUM(COLOR_16_16_16_16, 26)
+    GENERATE_ENUM(COLOR_16_FLOAT, 30)
+    GENERATE_ENUM(COLOR_16_16_FLOAT, 31)
+    GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(COLOR_32_FLOAT, 36)
+    GENERATE_ENUM(COLOR_32_32_FLOAT, 37)
+    GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(COLOR_2_3_3, 39)
+END_ENUMTYPE(ColorFormat)
+
+START_ENUMTYPE(SurfaceNumber)
+    GENERATE_ENUM(NUMBER_UREPEAT, 0)
+    GENERATE_ENUM(NUMBER_SREPEAT, 1)
+    GENERATE_ENUM(NUMBER_UINTEGER, 2)
+    GENERATE_ENUM(NUMBER_SINTEGER, 3)
+    GENERATE_ENUM(NUMBER_GAMMA, 4)
+    GENERATE_ENUM(NUMBER_FIXED, 5)
+    GENERATE_ENUM(NUMBER_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumber)
+
+START_ENUMTYPE(SurfaceFormat)
+    GENERATE_ENUM(FMT_1_REVERSE, 0)
+    GENERATE_ENUM(FMT_1, 1)
+    GENERATE_ENUM(FMT_8, 2)
+    GENERATE_ENUM(FMT_1_5_5_5, 3)
+    GENERATE_ENUM(FMT_5_6_5, 4)
+    GENERATE_ENUM(FMT_6_5_5, 5)
+    GENERATE_ENUM(FMT_8_8_8_8, 6)
+    GENERATE_ENUM(FMT_2_10_10_10, 7)
+    GENERATE_ENUM(FMT_8_A, 8)
+    GENERATE_ENUM(FMT_8_B, 9)
+    GENERATE_ENUM(FMT_8_8, 10)
+    GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11)
+    GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12)
+    GENERATE_ENUM(FMT_5_5_5_1, 13)
+    GENERATE_ENUM(FMT_8_8_8_8_A, 14)
+    GENERATE_ENUM(FMT_4_4_4_4, 15)
+    GENERATE_ENUM(FMT_8_8_8, 16)
+    GENERATE_ENUM(FMT_DXT1, 18)
+    GENERATE_ENUM(FMT_DXT2_3, 19)
+    GENERATE_ENUM(FMT_DXT4_5, 20)
+    GENERATE_ENUM(FMT_10_10_10_2, 21)
+    GENERATE_ENUM(FMT_24_8, 22)
+    GENERATE_ENUM(FMT_16, 24)
+    GENERATE_ENUM(FMT_16_16, 25)
+    GENERATE_ENUM(FMT_16_16_16_16, 26)
+    GENERATE_ENUM(FMT_16_EXPAND, 27)
+    GENERATE_ENUM(FMT_16_16_EXPAND, 28)
+    GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29)
+    GENERATE_ENUM(FMT_16_FLOAT, 30)
+    GENERATE_ENUM(FMT_16_16_FLOAT, 31)
+    GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32)
+    GENERATE_ENUM(FMT_32, 33)
+    GENERATE_ENUM(FMT_32_32, 34)
+    GENERATE_ENUM(FMT_32_32_32_32, 35)
+    GENERATE_ENUM(FMT_32_FLOAT, 36)
+    GENERATE_ENUM(FMT_32_32_FLOAT, 37)
+    GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38)
+    GENERATE_ENUM(FMT_ATI_TC_RGB, 39)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA, 40)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42)
+    GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43)
+    GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44)
+    GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46)
+    GENERATE_ENUM(FMT_ETC1_RGB, 47)
+    GENERATE_ENUM(FMT_ETC1_RGBA, 48)
+    GENERATE_ENUM(FMT_DXN, 49)
+    GENERATE_ENUM(FMT_2_3_3, 51)
+    GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54)
+    GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55)
+    GENERATE_ENUM(FMT_32_32_32_FLOAT, 57)
+    GENERATE_ENUM(FMT_DXT3A, 58)
+    GENERATE_ENUM(FMT_DXT5A, 59)
+    GENERATE_ENUM(FMT_CTX1, 60)
+END_ENUMTYPE(SurfaceFormat)
+
+START_ENUMTYPE(SurfaceTiling)
+    GENERATE_ENUM(ARRAY_LINEAR, 0)
+    GENERATE_ENUM(ARRAY_TILED, 1)
+END_ENUMTYPE(SurfaceTiling)
+
+START_ENUMTYPE(SurfaceArray)
+    GENERATE_ENUM(ARRAY_1D, 0)
+    GENERATE_ENUM(ARRAY_2D, 1)
+    GENERATE_ENUM(ARRAY_3D, 2)
+    GENERATE_ENUM(ARRAY_3D_SLICE, 3)
+END_ENUMTYPE(SurfaceArray)
+
+START_ENUMTYPE(SurfaceNumberX)
+    GENERATE_ENUM(NUMBERX_UREPEAT, 0)
+    GENERATE_ENUM(NUMBERX_SREPEAT, 1)
+    GENERATE_ENUM(NUMBERX_UINTEGER, 2)
+    GENERATE_ENUM(NUMBERX_SINTEGER, 3)
+    GENERATE_ENUM(NUMBERX_FLOAT, 7)
+END_ENUMTYPE(SurfaceNumberX)
+
+START_ENUMTYPE(ColorArrayX)
+    GENERATE_ENUM(ARRAYX_2D_COLOR, 0)
+    GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1)
+END_ENUMTYPE(ColorArrayX)
+
+
+
+
+// **************************************************************************
+// These are ones that had to be added in addition to what's generated
+// by the autoreg (in CSIM)
+// **************************************************************************
+START_ENUMTYPE(DXClipSpaceDef)
+    GENERATE_ENUM(DXCLIP_OPENGL, 0)
+    GENERATE_ENUM(DXCLIP_DIRECTX, 1)
+END_ENUMTYPE(DXClipSpaceDef)
+
+START_ENUMTYPE(PixCenter)
+    GENERATE_ENUM(PIXCENTER_D3D, 0)
+    GENERATE_ENUM(PIXCENTER_OGL, 1)
+END_ENUMTYPE(PixCenter)
+
+START_ENUMTYPE(RoundMode)
+    GENERATE_ENUM(TRUNCATE,   0)
+    GENERATE_ENUM(ROUND,      1)
+    GENERATE_ENUM(ROUNDTOEVEN,    2)
+    GENERATE_ENUM(ROUNDTOODD,     3)
+END_ENUMTYPE(RoundMode)
+
+START_ENUMTYPE(QuantMode)
+    GENERATE_ENUM(ONE_SIXTEENTH,   0)
+    GENERATE_ENUM(ONE_EIGHTH,      1)
+    GENERATE_ENUM(ONE_QUARTER,     2)
+    GENERATE_ENUM(ONE_HALF,    3)
+    GENERATE_ENUM(ONE,         4)
+END_ENUMTYPE(QuantMode)
+
+START_ENUMTYPE(FrontFace)
+    GENERATE_ENUM(FRONT_CCW,        0)
+    GENERATE_ENUM(FRONT_CW,     1)
+END_ENUMTYPE(FrontFace)
+
+START_ENUMTYPE(PolyMode)
+    GENERATE_ENUM(DISABLED,    0)
+    GENERATE_ENUM(DUALMODE,    1)
+END_ENUMTYPE(PolyMode)
+
+START_ENUMTYPE(PType)
+    GENERATE_ENUM(DRAW_POINTS,      0)
+    GENERATE_ENUM(DRAW_LINES,       1)
+    GENERATE_ENUM(DRAW_TRIANGLES,   2)
+END_ENUMTYPE(PType)
+
+START_ENUMTYPE(MSAANumSamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     3)
+END_ENUMTYPE(MSAANumSamples)
+
+START_ENUMTYPE(PatternBitOrder)
+    GENERATE_ENUM(LITTLE,   0)
+    GENERATE_ENUM(BIG,      1)
+END_ENUMTYPE(PatternBitOrder)
+
+START_ENUMTYPE(AutoResetCntl)
+    GENERATE_ENUM(NEVER,        0)
+    GENERATE_ENUM(EACHPRIMITIVE,    1)
+    GENERATE_ENUM(EACHPACKET,       2)
+END_ENUMTYPE(AutoResetCntl)
+
+START_ENUMTYPE(ParamShade)
+    GENERATE_ENUM(FLAT,     0)
+    GENERATE_ENUM(GOURAUD,  1)
+END_ENUMTYPE(ParamShade)
+
+START_ENUMTYPE(SamplingPattern)
+    GENERATE_ENUM(CENTROID, 0)
+    GENERATE_ENUM(PIXCENTER, 1)
+END_ENUMTYPE(SamplingPattern)
+
+START_ENUMTYPE(MSAASamples)
+    GENERATE_ENUM(ONE,      0)
+    GENERATE_ENUM(TWO,      1)
+    GENERATE_ENUM(FOUR,     2)
+END_ENUMTYPE(MSAASamples)
+
+START_ENUMTYPE(CopySampleSelect)
+    GENERATE_ENUM(SAMPLE_0, 0)
+    GENERATE_ENUM(SAMPLE_1, 1)
+    GENERATE_ENUM(SAMPLE_2, 2)
+    GENERATE_ENUM(SAMPLE_3, 3)
+    GENERATE_ENUM(SAMPLE_01,    4)
+    GENERATE_ENUM(SAMPLE_23,    5)
+    GENERATE_ENUM(SAMPLE_0123,  6)
+END_ENUMTYPE(CopySampleSelect)
+
+
+#undef START_ENUMTYPE
+#undef GENERATE_ENUM
+#undef END_ENUMTYPE
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h
new file mode 100644
index 00000000000..d04379887b7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h
@@ -0,0 +1,3405 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+START_REGISTER(PA_CL_VPORT_XSCALE)
+    GENERATE_FIELD(VPORT_XSCALE, float)
+END_REGISTER(PA_CL_VPORT_XSCALE)
+
+START_REGISTER(PA_CL_VPORT_XOFFSET)
+    GENERATE_FIELD(VPORT_XOFFSET, float)
+END_REGISTER(PA_CL_VPORT_XOFFSET)
+
+START_REGISTER(PA_CL_VPORT_YSCALE)
+    GENERATE_FIELD(VPORT_YSCALE, float)
+END_REGISTER(PA_CL_VPORT_YSCALE)
+
+START_REGISTER(PA_CL_VPORT_YOFFSET)
+    GENERATE_FIELD(VPORT_YOFFSET, float)
+END_REGISTER(PA_CL_VPORT_YOFFSET)
+
+START_REGISTER(PA_CL_VPORT_ZSCALE)
+    GENERATE_FIELD(VPORT_ZSCALE, float)
+END_REGISTER(PA_CL_VPORT_ZSCALE)
+
+START_REGISTER(PA_CL_VPORT_ZOFFSET)
+    GENERATE_FIELD(VPORT_ZOFFSET, float)
+END_REGISTER(PA_CL_VPORT_ZOFFSET)
+
+START_REGISTER(PA_CL_VTE_CNTL)
+    GENERATE_FIELD(VPORT_X_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool)
+    GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool)
+    GENERATE_FIELD(VTX_XY_FMT, bool)
+    GENERATE_FIELD(VTX_Z_FMT, bool)
+    GENERATE_FIELD(VTX_W0_FMT, bool)
+    GENERATE_FIELD(PERFCOUNTER_REF, bool)
+END_REGISTER(PA_CL_VTE_CNTL)
+
+START_REGISTER(PA_CL_CLIP_CNTL)
+    GENERATE_FIELD(CLIP_DISABLE, bool)
+    GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool)
+    GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef)
+    GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool)
+    GENERATE_FIELD(VTX_KILL_OR, bool)
+    GENERATE_FIELD(XY_NAN_RETAIN, bool)
+    GENERATE_FIELD(Z_NAN_RETAIN, bool)
+    GENERATE_FIELD(W_NAN_RETAIN, bool)
+END_REGISTER(PA_CL_CLIP_CNTL)
+
+START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_VERT_DISC_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ)
+
+START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+    GENERATE_FIELD(DATA_REGISTER, float)
+END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ)
+
+START_REGISTER(PA_CL_ENHANCE)
+    GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_CL_ENHANCE)
+
+START_REGISTER(PA_SC_ENHANCE)
+    GENERATE_FIELD(ECO_SPARE3, int)
+    GENERATE_FIELD(ECO_SPARE2, int)
+    GENERATE_FIELD(ECO_SPARE1, int)
+    GENERATE_FIELD(ECO_SPARE0, int)
+END_REGISTER(PA_SC_ENHANCE)
+
+START_REGISTER(PA_SU_VTX_CNTL)
+    GENERATE_FIELD(PIX_CENTER, PixCenter)
+    GENERATE_FIELD(ROUND_MODE, RoundMode)
+    GENERATE_FIELD(QUANT_MODE, QuantMode)
+END_REGISTER(PA_SU_VTX_CNTL)
+
+START_REGISTER(PA_SU_POINT_SIZE)
+    GENERATE_FIELD(HEIGHT, fixed12_4)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_POINT_SIZE)
+
+START_REGISTER(PA_SU_POINT_MINMAX)
+    GENERATE_FIELD(MIN_SIZE, fixed12_4)
+    GENERATE_FIELD(MAX_SIZE, fixed12_4)
+END_REGISTER(PA_SU_POINT_MINMAX)
+
+START_REGISTER(PA_SU_LINE_CNTL)
+    GENERATE_FIELD(WIDTH, fixed12_4)
+END_REGISTER(PA_SU_LINE_CNTL)
+
+START_REGISTER(PA_SU_FACE_DATA)
+    GENERATE_FIELD(BASE_ADDR, int)
+END_REGISTER(PA_SU_FACE_DATA)
+
+START_REGISTER(PA_SU_SC_MODE_CNTL)
+    GENERATE_FIELD(CULL_FRONT, bool)
+    GENERATE_FIELD(CULL_BACK, bool)
+    GENERATE_FIELD(FACE, FrontFace)
+    GENERATE_FIELD(POLY_MODE, PolyMode)
+    GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType)
+    GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType)
+    GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool)
+    GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool)
+    GENERATE_FIELD(MSAA_ENABLE, bool)
+    GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool)
+    GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool)
+    GENERATE_FIELD(PROVOKING_VTX_LAST, bool)
+    GENERATE_FIELD(PERSP_CORR_DIS, bool)
+    GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool)
+    GENERATE_FIELD(QUAD_ORDER_ENABLE, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool)
+    GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool)
+    GENERATE_FIELD(CLAMPED_FACENESS, bool)
+    GENERATE_FIELD(ZERO_AREA_FACENESS, bool)
+    GENERATE_FIELD(FACE_KILL_ENABLE, bool)
+    GENERATE_FIELD(FACE_WRITE_ENABLE, bool)
+END_REGISTER(PA_SU_SC_MODE_CNTL)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+    GENERATE_FIELD(SCALE, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE)
+
+START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+    GENERATE_FIELD(OFFSET, float)
+END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT)
+END_REGISTER(PA_SU_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_SELECT)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER1_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER2_HI)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_LOW)
+
+START_REGISTER(PA_SU_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SU_PERFCOUNTER3_HI)
+
+START_REGISTER(PA_SC_WINDOW_OFFSET)
+    GENERATE_FIELD(WINDOW_X_OFFSET, signedint15)
+    GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15)
+END_REGISTER(PA_SC_WINDOW_OFFSET)
+
+START_REGISTER(PA_SC_AA_CONFIG)
+    GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples)
+    GENERATE_FIELD(MAX_SAMPLE_DIST, int)
+END_REGISTER(PA_SC_AA_CONFIG)
+
+START_REGISTER(PA_SC_AA_MASK)
+    GENERATE_FIELD(AA_MASK, hex)
+END_REGISTER(PA_SC_AA_MASK)
+
+START_REGISTER(PA_SC_LINE_STIPPLE)
+    GENERATE_FIELD(LINE_PATTERN, hex)
+    GENERATE_FIELD(REPEAT_COUNT, intMinusOne)
+    GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder)
+    GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl)
+END_REGISTER(PA_SC_LINE_STIPPLE)
+
+START_REGISTER(PA_SC_LINE_CNTL)
+    GENERATE_FIELD(BRES_CNTL, int)
+    GENERATE_FIELD(USE_BRES_CNTL, bool)
+    GENERATE_FIELD(EXPAND_LINE_WIDTH, bool)
+    GENERATE_FIELD(LAST_PIXEL, bool)
+END_REGISTER(PA_SC_LINE_CNTL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+    GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_TL)
+
+START_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_WINDOW_SCISSOR_BR)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+    GENERATE_FIELD(TL_X, int)
+    GENERATE_FIELD(TL_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_TL)
+
+START_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+    GENERATE_FIELD(BR_X, int)
+    GENERATE_FIELD(BR_Y, int)
+END_REGISTER(PA_SC_SCREEN_SCISSOR_BR)
+
+START_REGISTER(PA_SC_VIZ_QUERY)
+    GENERATE_FIELD(VIZ_QUERY_ENA, bool)
+    GENERATE_FIELD(VIZ_QUERY_ID, int)
+    GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool)
+END_REGISTER(PA_SC_VIZ_QUERY)
+
+START_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+    GENERATE_FIELD(STATUS_BITS, hex)
+END_REGISTER(PA_SC_VIZ_QUERY_STATUS)
+
+START_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+    GENERATE_FIELD(CURRENT_PTR, int)
+    GENERATE_FIELD(CURRENT_COUNT, int)
+END_REGISTER(PA_SC_LINE_STIPPLE_STATE)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT)
+END_REGISTER(PA_SC_PERFCOUNTER0_SELECT)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_LOW)
+
+START_REGISTER(PA_SC_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(PA_SC_PERFCOUNTER0_HI)
+
+START_REGISTER(PA_CL_CNTL_STATUS)
+    GENERATE_FIELD(CL_BUSY, int)
+END_REGISTER(PA_CL_CNTL_STATUS)
+
+START_REGISTER(PA_SU_CNTL_STATUS)
+    GENERATE_FIELD(SU_BUSY, int)
+END_REGISTER(PA_SU_CNTL_STATUS)
+
+START_REGISTER(PA_SC_CNTL_STATUS)
+    GENERATE_FIELD(SC_BUSY, int)
+END_REGISTER(PA_SC_CNTL_STATUS)
+
+START_REGISTER(PA_SU_DEBUG_CNTL)
+    GENERATE_FIELD(SU_DEBUG_INDX, int)
+END_REGISTER(PA_SU_DEBUG_CNTL)
+
+START_REGISTER(PA_SU_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(PA_SU_DEBUG_DATA)
+
+START_REGISTER(PA_SC_DEBUG_CNTL)
+    GENERATE_FIELD(SC_DEBUG_INDX, int)
+END_REGISTER(PA_SC_DEBUG_CNTL)
+
+START_REGISTER(PA_SC_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(PA_SC_DEBUG_DATA)
+
+START_REGISTER(GFX_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+END_REGISTER(GFX_COPY_STATE)
+
+START_REGISTER(VGT_DRAW_INITIATOR)
+    GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE)
+    GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT)
+    GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT)
+    GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE)
+    GENERATE_FIELD(NOT_EOP, bool)
+    GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX)
+    GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE)
+    GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE)
+    GENERATE_FIELD(NUM_INDICES, uint)
+END_REGISTER(VGT_DRAW_INITIATOR)
+
+START_REGISTER(VGT_EVENT_INITIATOR)
+    GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE)
+END_REGISTER(VGT_EVENT_INITIATOR)
+
+START_REGISTER(VGT_DMA_BASE)
+    GENERATE_FIELD(BASE_ADDR, uint)
+END_REGISTER(VGT_DMA_BASE)
+
+START_REGISTER(VGT_DMA_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+    GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE)
+END_REGISTER(VGT_DMA_SIZE)
+
+START_REGISTER(VGT_BIN_BASE)
+    GENERATE_FIELD(BIN_BASE_ADDR, uint)
+END_REGISTER(VGT_BIN_BASE)
+
+START_REGISTER(VGT_BIN_SIZE)
+    GENERATE_FIELD(NUM_WORDS, uint)
+    GENERATE_FIELD(FACENESS_FETCH, int)
+    GENERATE_FIELD(FACENESS_RESET, int)
+END_REGISTER(VGT_BIN_SIZE)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MIN)
+
+START_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+    GENERATE_FIELD(COLUMN, int)
+    GENERATE_FIELD(ROW, int)
+    GENERATE_FIELD(GUARD_BAND, int)
+END_REGISTER(VGT_CURRENT_BIN_ID_MAX)
+
+START_REGISTER(VGT_IMMED_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_IMMED_DATA)
+
+START_REGISTER(VGT_MAX_VTX_INDX)
+    GENERATE_FIELD(MAX_INDX, int)
+END_REGISTER(VGT_MAX_VTX_INDX)
+
+START_REGISTER(VGT_MIN_VTX_INDX)
+    GENERATE_FIELD(MIN_INDX, int)
+END_REGISTER(VGT_MIN_VTX_INDX)
+
+START_REGISTER(VGT_INDX_OFFSET)
+    GENERATE_FIELD(INDX_OFFSET, int)
+END_REGISTER(VGT_INDX_OFFSET)
+
+START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+    GENERATE_FIELD(VTX_REUSE_DEPTH, int)
+END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL)
+
+START_REGISTER(VGT_OUT_DEALLOC_CNTL)
+    GENERATE_FIELD(DEALLOC_DIST, int)
+END_REGISTER(VGT_OUT_DEALLOC_CNTL)
+
+START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+    GENERATE_FIELD(RESET_INDX, int)
+END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX)
+
+START_REGISTER(VGT_ENHANCE)
+    GENERATE_FIELD(MISC, hex)
+END_REGISTER(VGT_ENHANCE)
+
+START_REGISTER(VGT_VTX_VECT_EJECT_REG)
+    GENERATE_FIELD(PRIM_COUNT, int)
+END_REGISTER(VGT_VTX_VECT_EJECT_REG)
+
+START_REGISTER(VGT_LAST_COPY_STATE)
+    GENERATE_FIELD(SRC_STATE_ID, int)
+    GENERATE_FIELD(DST_STATE_ID, int)
+END_REGISTER(VGT_LAST_COPY_STATE)
+
+START_REGISTER(VGT_DEBUG_CNTL)
+    GENERATE_FIELD(VGT_DEBUG_INDX, int)
+END_REGISTER(VGT_DEBUG_CNTL)
+
+START_REGISTER(VGT_DEBUG_DATA)
+    GENERATE_FIELD(DATA, hex)
+END_REGISTER(VGT_DEBUG_DATA)
+
+START_REGISTER(VGT_CNTL_STATUS)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_BUSY, int)
+    GENERATE_FIELD(VGT_DMA_REQ_BUSY, int)
+    GENERATE_FIELD(VGT_GRP_BUSY, int)
+    GENERATE_FIELD(VGT_VR_BUSY, int)
+    GENERATE_FIELD(VGT_BIN_BUSY, int)
+    GENERATE_FIELD(VGT_PT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_BUSY, int)
+    GENERATE_FIELD(VGT_OUT_INDX_BUSY, int)
+END_REGISTER(VGT_CNTL_STATUS)
+
+START_REGISTER(VGT_CRC_SQ_DATA)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_DATA)
+
+START_REGISTER(VGT_CRC_SQ_CTRL)
+    GENERATE_FIELD(CRC, hex)
+END_REGISTER(VGT_CRC_SQ_CTRL)
+
+START_REGISTER(VGT_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER0_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER1_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER2_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT)
+END_REGISTER(VGT_PERFCOUNTER3_SELECT)
+
+START_REGISTER(VGT_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_LOW)
+
+START_REGISTER(VGT_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER0_HI)
+
+START_REGISTER(VGT_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER1_HI)
+
+START_REGISTER(VGT_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER2_HI)
+
+START_REGISTER(VGT_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(VGT_PERFCOUNTER3_HI)
+
+START_REGISTER(TC_CNTL_STATUS)
+    GENERATE_FIELD(L2_INVALIDATE, int)
+    GENERATE_FIELD(TC_L2_HIT_MISS, int)
+    GENERATE_FIELD(TC_BUSY, int)
+END_REGISTER(TC_CNTL_STATUS)
+
+START_REGISTER(TCR_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCR_CHICKEN)
+
+START_REGISTER(TCF_CHICKEN)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCF_CHICKEN)
+
+START_REGISTER(TCM_CHICKEN)
+    GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int)
+    GENERATE_FIELD(ETC_COLOR_ENDIAN, int)
+    GENERATE_FIELD(SPARE, hex)
+END_REGISTER(TCM_CHICKEN)
+
+START_REGISTER(TCR_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT)
+END_REGISTER(TCR_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCR_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER0_HI)
+
+START_REGISTER(TCR_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCR_PERFCOUNTER1_HI)
+
+START_REGISTER(TCR_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCR_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCR_PERFCOUNTER1_LOW)
+
+START_REGISTER(TP_TC_CLKGATE_CNTL)
+    GENERATE_FIELD(TP_BUSY_EXTEND, int)
+    GENERATE_FIELD(TC_BUSY_EXTEND, int)
+END_REGISTER(TP_TC_CLKGATE_CNTL)
+
+START_REGISTER(TPC_CNTL_STATUS)
+    GENERATE_FIELD(TPC_INPUT_BUSY, int)
+    GENERATE_FIELD(TPC_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_WALKER_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TPC_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int)
+    GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TPC_BLEND_BUSY, int)
+    GENERATE_FIELD(TF_TW_RTS, int)
+    GENERATE_FIELD(TF_TW_STATE_RTS, int)
+    GENERATE_FIELD(TF_TW_RTR, int)
+    GENERATE_FIELD(TW_TA_RTS, int)
+    GENERATE_FIELD(TW_TA_TT_RTS, int)
+    GENERATE_FIELD(TW_TA_LAST_RTS, int)
+    GENERATE_FIELD(TW_TA_RTR, int)
+    GENERATE_FIELD(TA_TB_RTS, int)
+    GENERATE_FIELD(TA_TB_TT_RTS, int)
+    GENERATE_FIELD(TA_TB_RTR, int)
+    GENERATE_FIELD(TA_TF_RTS, int)
+    GENERATE_FIELD(TA_TF_TC_FIFO_REN, int)
+    GENERATE_FIELD(TP_SQ_DEC, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+END_REGISTER(TPC_CNTL_STATUS)
+
+START_REGISTER(TPC_DEBUG0)
+    GENERATE_FIELD(LOD_CNTL, int)
+    GENERATE_FIELD(IC_CTR, int)
+    GENERATE_FIELD(WALKER_CNTL, int)
+    GENERATE_FIELD(ALIGNER_CNTL, int)
+    GENERATE_FIELD(PREV_TC_STATE_VALID, int)
+    GENERATE_FIELD(WALKER_STATE, int)
+    GENERATE_FIELD(ALIGNER_STATE, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(TPC_CLK_EN, int)
+    GENERATE_FIELD(SQ_TP_WAKEUP, int)
+END_REGISTER(TPC_DEBUG0)
+
+START_REGISTER(TPC_DEBUG1)
+    GENERATE_FIELD(UNUSED, int)
+END_REGISTER(TPC_DEBUG1)
+
+START_REGISTER(TPC_CHICKEN)
+    GENERATE_FIELD(BLEND_PRECISION, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TPC_CHICKEN)
+
+START_REGISTER(TP0_CNTL_STATUS)
+    GENERATE_FIELD(TP_INPUT_BUSY, int)
+    GENERATE_FIELD(TP_LOD_BUSY, int)
+    GENERATE_FIELD(TP_LOD_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ADDR_BUSY, int)
+    GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_ALIGNER_BUSY, int)
+    GENERATE_FIELD(TP_TC_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_RR_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_FETCH_BUSY, int)
+    GENERATE_FIELD(TP_CH_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_TT_BUSY, int)
+    GENERATE_FIELD(TP_HICOLOR_BUSY, int)
+    GENERATE_FIELD(TP_BLEND_BUSY, int)
+    GENERATE_FIELD(TP_OUT_FIFO_BUSY, int)
+    GENERATE_FIELD(TP_OUTPUT_BUSY, int)
+    GENERATE_FIELD(IN_LC_RTS, int)
+    GENERATE_FIELD(LC_LA_RTS, int)
+    GENERATE_FIELD(LA_FL_RTS, int)
+    GENERATE_FIELD(FL_TA_RTS, int)
+    GENERATE_FIELD(TA_FA_RTS, int)
+    GENERATE_FIELD(TA_FA_TT_RTS, int)
+    GENERATE_FIELD(FA_AL_RTS, int)
+    GENERATE_FIELD(FA_AL_TT_RTS, int)
+    GENERATE_FIELD(AL_TF_RTS, int)
+    GENERATE_FIELD(AL_TF_TT_RTS, int)
+    GENERATE_FIELD(TF_TB_RTS, int)
+    GENERATE_FIELD(TF_TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_RTS, int)
+    GENERATE_FIELD(TB_TT_TT_RESET, int)
+    GENERATE_FIELD(TB_TO_RTS, int)
+    GENERATE_FIELD(TP_BUSY, int)
+END_REGISTER(TP0_CNTL_STATUS)
+
+START_REGISTER(TP0_DEBUG)
+    GENERATE_FIELD(Q_LOD_CNTL, int)
+    GENERATE_FIELD(Q_SQ_TP_WAKEUP, int)
+    GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int)
+    GENERATE_FIELD(REG_CLK_EN, int)
+    GENERATE_FIELD(PERF_CLK_EN, int)
+    GENERATE_FIELD(TP_CLK_EN, int)
+    GENERATE_FIELD(Q_WALKER_CNTL, int)
+    GENERATE_FIELD(Q_ALIGNER_CNTL, int)
+END_REGISTER(TP0_DEBUG)
+
+START_REGISTER(TP0_CHICKEN)
+    GENERATE_FIELD(TT_MODE, int)
+    GENERATE_FIELD(VFETCH_ADDRESS_MODE, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(TP0_CHICKEN)
+
+START_REGISTER(TP0_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT)
+END_REGISTER(TP0_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER0_HI)
+
+START_REGISTER(TP0_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER0_LOW)
+
+START_REGISTER(TP0_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, int)
+END_REGISTER(TP0_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TP0_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TP0_PERFCOUNTER1_HI)
+
+START_REGISTER(TP0_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TP0_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT)
+END_REGISTER(TCM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCM_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER0_HI)
+
+START_REGISTER(TCM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCM_PERFCOUNTER1_HI)
+
+START_REGISTER(TCM_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCM_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCM_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER0_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER1_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER2_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER3_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER4_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER4_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER5_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER5_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER6_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER6_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER7_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER7_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER8_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER8_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER9_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER9_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER10_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER10_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER11_SELECT)
+    GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT)
+END_REGISTER(TCF_PERFCOUNTER11_SELECT)
+
+START_REGISTER(TCF_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER0_HI)
+
+START_REGISTER(TCF_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER1_HI)
+
+START_REGISTER(TCF_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER2_HI)
+
+START_REGISTER(TCF_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER3_HI)
+
+START_REGISTER(TCF_PERFCOUNTER4_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER4_HI)
+
+START_REGISTER(TCF_PERFCOUNTER5_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER5_HI)
+
+START_REGISTER(TCF_PERFCOUNTER6_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER6_HI)
+
+START_REGISTER(TCF_PERFCOUNTER7_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER7_HI)
+
+START_REGISTER(TCF_PERFCOUNTER8_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER8_HI)
+
+START_REGISTER(TCF_PERFCOUNTER9_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER9_HI)
+
+START_REGISTER(TCF_PERFCOUNTER10_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER10_HI)
+
+START_REGISTER(TCF_PERFCOUNTER11_HI)
+    GENERATE_FIELD(PERFCOUNTER_HI, int)
+END_REGISTER(TCF_PERFCOUNTER11_HI)
+
+START_REGISTER(TCF_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER0_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER1_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER2_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER3_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER4_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER4_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER5_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER5_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER6_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER6_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER7_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER7_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER8_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER8_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER9_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER9_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER10_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER10_LOW)
+
+START_REGISTER(TCF_PERFCOUNTER11_LOW)
+    GENERATE_FIELD(PERFCOUNTER_LOW, int)
+END_REGISTER(TCF_PERFCOUNTER11_LOW)
+
+START_REGISTER(TCF_DEBUG)
+    GENERATE_FIELD(not_MH_TC_rtr, int)
+    GENERATE_FIELD(TC_MH_send, int)
+    GENERATE_FIELD(not_FG0_rtr, int)
+    GENERATE_FIELD(not_TCB_TCO_rtr, int)
+    GENERATE_FIELD(TCB_ff_stall, int)
+    GENERATE_FIELD(TCB_miss_stall, int)
+    GENERATE_FIELD(TCA_TCB_stall, int)
+    GENERATE_FIELD(PF0_stall, int)
+    GENERATE_FIELD(TP0_full, int)
+    GENERATE_FIELD(TPC_full, int)
+    GENERATE_FIELD(not_TPC_rtr, int)
+    GENERATE_FIELD(tca_state_rts, int)
+    GENERATE_FIELD(tca_rts, int)
+END_REGISTER(TCF_DEBUG)
+
+START_REGISTER(TCA_FIFO_DEBUG)
+    GENERATE_FIELD(tp0_full, int)
+    GENERATE_FIELD(tpc_full, int)
+    GENERATE_FIELD(load_tpc_fifo, int)
+    GENERATE_FIELD(load_tp_fifos, int)
+    GENERATE_FIELD(FW_full, int)
+    GENERATE_FIELD(not_FW_rtr0, int)
+    GENERATE_FIELD(FW_rts0, int)
+    GENERATE_FIELD(not_FW_tpc_rtr, int)
+    GENERATE_FIELD(FW_tpc_rts, int)
+END_REGISTER(TCA_FIFO_DEBUG)
+
+START_REGISTER(TCA_PROBE_DEBUG)
+    GENERATE_FIELD(ProbeFilter_stall, int)
+END_REGISTER(TCA_PROBE_DEBUG)
+
+START_REGISTER(TCA_TPC_DEBUG)
+    GENERATE_FIELD(captue_state_rts, int)
+    GENERATE_FIELD(capture_tca_rts, int)
+END_REGISTER(TCA_TPC_DEBUG)
+
+START_REGISTER(TCB_CORE_DEBUG)
+    GENERATE_FIELD(access512, int)
+    GENERATE_FIELD(tiled, int)
+    GENERATE_FIELD(opcode, int)
+    GENERATE_FIELD(format, int)
+    GENERATE_FIELD(sector_format, int)
+    GENERATE_FIELD(sector_format512, int)
+END_REGISTER(TCB_CORE_DEBUG)
+
+START_REGISTER(TCB_TAG0_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG0_DEBUG)
+
+START_REGISTER(TCB_TAG1_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG1_DEBUG)
+
+START_REGISTER(TCB_TAG2_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG2_DEBUG)
+
+START_REGISTER(TCB_TAG3_DEBUG)
+    GENERATE_FIELD(mem_read_cycle, int)
+    GENERATE_FIELD(tag_access_cycle, int)
+    GENERATE_FIELD(miss_stall, int)
+    GENERATE_FIELD(num_feee_lines, int)
+    GENERATE_FIELD(max_misses, int)
+END_REGISTER(TCB_TAG3_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+    GENERATE_FIELD(left_done, int)
+    GENERATE_FIELD(fg0_sends_left, int)
+    GENERATE_FIELD(one_sector_to_go_left_q, int)
+    GENERATE_FIELD(no_sectors_to_go, int)
+    GENERATE_FIELD(update_left, int)
+    GENERATE_FIELD(sector_mask_left_count_q, int)
+    GENERATE_FIELD(sector_mask_left_q, int)
+    GENERATE_FIELD(valid_left_q, int)
+END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+    GENERATE_FIELD(quad_sel_left, int)
+    GENERATE_FIELD(set_sel_left, int)
+    GENERATE_FIELD(right_eq_left, int)
+    GENERATE_FIELD(ff_fg_type512, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(setquads_to_send, int)
+END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG)
+
+START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+    GENERATE_FIELD(tc0_arb_rts, int)
+    GENERATE_FIELD(ga_out_rts, int)
+    GENERATE_FIELD(tc_arb_format, int)
+    GENERATE_FIELD(tc_arb_fmsopcode, int)
+    GENERATE_FIELD(tc_arb_request_type, int)
+    GENERATE_FIELD(busy, int)
+    GENERATE_FIELD(fgo_busy, int)
+    GENERATE_FIELD(ga_busy, int)
+    GENERATE_FIELD(mc_sel_q, int)
+    GENERATE_FIELD(valid_q, int)
+    GENERATE_FIELD(arb_RTR, int)
+END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG)
+
+START_REGISTER(TCD_INPUT0_DEBUG)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(valid_q1, int)
+    GENERATE_FIELD(cnt_q1, int)
+    GENERATE_FIELD(last_send_q1, int)
+    GENERATE_FIELD(ip_send, int)
+    GENERATE_FIELD(ipbuf_dxt_send, int)
+    GENERATE_FIELD(ipbuf_busy, int)
+END_REGISTER(TCD_INPUT0_DEBUG)
+
+START_REGISTER(TCD_DEGAMMA_DEBUG)
+    GENERATE_FIELD(dgmm_ftfconv_dgmmen, int)
+    GENERATE_FIELD(dgmm_ctrl_dgmm8, int)
+    GENERATE_FIELD(dgmm_ctrl_last_send, int)
+    GENERATE_FIELD(dgmm_ctrl_send, int)
+    GENERATE_FIELD(dgmm_stall, int)
+    GENERATE_FIELD(dgmm_pstate, int)
+END_REGISTER(TCD_DEGAMMA_DEBUG)
+
+START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(sctrmx_rtr, int)
+    GENERATE_FIELD(dxtc_rtr, int)
+    GENERATE_FIELD(sctrarb_multcyl_send, int)
+    GENERATE_FIELD(sctrmx0_sctrarb_rts, int)
+    GENERATE_FIELD(dxtc_sctrarb_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_last_send, int)
+    GENERATE_FIELD(dxtc_dgmmpd_send, int)
+    GENERATE_FIELD(dcmp_mux_send, int)
+END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG)
+
+START_REGISTER(TCD_DXTC_ARB_DEBUG)
+    GENERATE_FIELD(n0_stall, int)
+    GENERATE_FIELD(pstate, int)
+    GENERATE_FIELD(arb_dcmp01_last_send, int)
+    GENERATE_FIELD(arb_dcmp01_cnt, int)
+    GENERATE_FIELD(arb_dcmp01_sector, int)
+    GENERATE_FIELD(arb_dcmp01_cacheline, int)
+    GENERATE_FIELD(arb_dcmp01_format, int)
+    GENERATE_FIELD(arb_dcmp01_send, int)
+    GENERATE_FIELD(n0_dxt2_4_types, int)
+END_REGISTER(TCD_DXTC_ARB_DEBUG)
+
+START_REGISTER(TCD_STALLS_DEBUG)
+    GENERATE_FIELD(not_multcyl_sctrarb_rtr, int)
+    GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int)
+    GENERATE_FIELD(not_dcmp0_arb_rtr, int)
+    GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int)
+    GENERATE_FIELD(not_mux_dcmp_rtr, int)
+    GENERATE_FIELD(not_incoming_rtr, int)
+END_REGISTER(TCD_STALLS_DEBUG)
+
+START_REGISTER(TCO_STALLS_DEBUG)
+    GENERATE_FIELD(quad0_sg_crd_RTR, int)
+    GENERATE_FIELD(quad0_rl_sg_RTR, int)
+    GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int)
+END_REGISTER(TCO_STALLS_DEBUG)
+
+START_REGISTER(TCO_QUAD0_DEBUG0)
+    GENERATE_FIELD(rl_sg_sector_format, int)
+    GENERATE_FIELD(rl_sg_end_of_sample, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_end_of_sample, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(stageN1_valid_q, int)
+    GENERATE_FIELD(read_cache_q, int)
+    GENERATE_FIELD(cache_read_RTR, int)
+    GENERATE_FIELD(all_sectors_written_set3, int)
+    GENERATE_FIELD(all_sectors_written_set2, int)
+    GENERATE_FIELD(all_sectors_written_set1, int)
+    GENERATE_FIELD(all_sectors_written_set0, int)
+    GENERATE_FIELD(busy, int)
+END_REGISTER(TCO_QUAD0_DEBUG0)
+
+START_REGISTER(TCO_QUAD0_DEBUG1)
+    GENERATE_FIELD(fifo_busy, int)
+    GENERATE_FIELD(empty, int)
+    GENERATE_FIELD(full, int)
+    GENERATE_FIELD(write_enable, int)
+    GENERATE_FIELD(fifo_write_ptr, int)
+    GENERATE_FIELD(fifo_read_ptr, int)
+    GENERATE_FIELD(cache_read_busy, int)
+    GENERATE_FIELD(latency_fifo_busy, int)
+    GENERATE_FIELD(input_quad_busy, int)
+    GENERATE_FIELD(tco_quad_pipe_busy, int)
+    GENERATE_FIELD(TCB_TCO_rtr_d, int)
+    GENERATE_FIELD(TCB_TCO_xfc_q, int)
+    GENERATE_FIELD(rl_sg_rtr, int)
+    GENERATE_FIELD(rl_sg_rts, int)
+    GENERATE_FIELD(sg_crd_rtr, int)
+    GENERATE_FIELD(sg_crd_rts, int)
+    GENERATE_FIELD(TCO_TCB_read_xfc, int)
+END_REGISTER(TCO_QUAD0_DEBUG1)
+
+START_REGISTER(SQ_GPR_MANAGEMENT)
+    GENERATE_FIELD(REG_DYNAMIC, int)
+    GENERATE_FIELD(REG_SIZE_PIX, int)
+    GENERATE_FIELD(REG_SIZE_VTX, int)
+END_REGISTER(SQ_GPR_MANAGEMENT)
+
+START_REGISTER(SQ_FLOW_CONTROL)
+    GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ONE_THREAD, int)
+    GENERATE_FIELD(ONE_ALU, int)
+    GENERATE_FIELD(CF_WR_BASE, hex)
+    GENERATE_FIELD(NO_PV_PS, int)
+    GENERATE_FIELD(NO_LOOP_EXIT, int)
+    GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int)
+    GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(VC_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(ALU_ARBITRATION_POLICY, int)
+    GENERATE_FIELD(NO_ARB_EJECT, int)
+    GENERATE_FIELD(NO_CFS_EJECT, int)
+    GENERATE_FIELD(POS_EXP_PRIORITY, int)
+    GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int)
+    GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int)
+END_REGISTER(SQ_FLOW_CONTROL)
+
+START_REGISTER(SQ_INST_STORE_MANAGMENT)
+    GENERATE_FIELD(INST_BASE_PIX, int)
+    GENERATE_FIELD(INST_BASE_VTX, int)
+END_REGISTER(SQ_INST_STORE_MANAGMENT)
+
+START_REGISTER(SQ_RESOURCE_MANAGMENT)
+    GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int)
+    GENERATE_FIELD(EXPORT_BUF_ENTRIES, int)
+END_REGISTER(SQ_RESOURCE_MANAGMENT)
+
+START_REGISTER(SQ_EO_RT)
+    GENERATE_FIELD(EO_CONSTANTS_RT, int)
+    GENERATE_FIELD(EO_TSTATE_RT, int)
+END_REGISTER(SQ_EO_RT)
+
+START_REGISTER(SQ_DEBUG_MISC)
+    GENERATE_FIELD(DB_ALUCST_SIZE, int)
+    GENERATE_FIELD(DB_TSTATE_SIZE, int)
+    GENERATE_FIELD(DB_READ_CTX, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DB_READ_MEMORY, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_0, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_1, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_2, int)
+    GENERATE_FIELD(DB_WEN_MEMORY_3, int)
+END_REGISTER(SQ_DEBUG_MISC)
+
+START_REGISTER(SQ_ACTIVITY_METER_CNTL)
+    GENERATE_FIELD(TIMEBASE, int)
+    GENERATE_FIELD(THRESHOLD_LOW, int)
+    GENERATE_FIELD(THRESHOLD_HIGH, int)
+    GENERATE_FIELD(SPARE, int)
+END_REGISTER(SQ_ACTIVITY_METER_CNTL)
+
+START_REGISTER(SQ_ACTIVITY_METER_STATUS)
+    GENERATE_FIELD(PERCENT_BUSY, int)
+END_REGISTER(SQ_ACTIVITY_METER_STATUS)
+
+START_REGISTER(SQ_INPUT_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+END_REGISTER(SQ_INPUT_ARB_PRIORITY)
+
+START_REGISTER(SQ_THREAD_ARB_PRIORITY)
+    GENERATE_FIELD(PC_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(PC_AVAIL_SIGN, int)
+    GENERATE_FIELD(SX_AVAIL_WEIGHT, int)
+    GENERATE_FIELD(SX_AVAIL_SIGN, int)
+    GENERATE_FIELD(THRESHOLD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int)
+    GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int)
+END_REGISTER(SQ_THREAD_ARB_PRIORITY)
+
+START_REGISTER(SQ_VS_WATCHDOG_TIMER)
+    GENERATE_FIELD(ENABLE, int)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+END_REGISTER(SQ_VS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_PS_WATCHDOG_TIMER)
+    GENERATE_FIELD(ENABLE, int)
+    GENERATE_FIELD(TIMEOUT_COUNT, int)
+END_REGISTER(SQ_PS_WATCHDOG_TIMER)
+
+START_REGISTER(SQ_INT_CNTL)
+    GENERATE_FIELD(PS_WATCHDOG_MASK, int)
+    GENERATE_FIELD(VS_WATCHDOG_MASK, int)
+END_REGISTER(SQ_INT_CNTL)
+
+START_REGISTER(SQ_INT_STATUS)
+    GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int)
+    GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int)
+END_REGISTER(SQ_INT_STATUS)
+
+START_REGISTER(SQ_INT_ACK)
+    GENERATE_FIELD(PS_WATCHDOG_ACK, int)
+    GENERATE_FIELD(VS_WATCHDOG_ACK, int)
+END_REGISTER(SQ_INT_ACK)
+
+START_REGISTER(SQ_DEBUG_INPUT_FSM)
+    GENERATE_FIELD(VC_VSR_LD, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VC_GPR_LD, int)
+    GENERATE_FIELD(PC_PISM, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PC_AS, int)
+    GENERATE_FIELD(PC_INTERP_CNT, int)
+    GENERATE_FIELD(PC_GPR_SIZE, int)
+END_REGISTER(SQ_DEBUG_INPUT_FSM)
+
+START_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+    GENERATE_FIELD(TEX_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(ALU_CONST_EVENT_STATE, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(ALU_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(TEX_CONST_CNTX_VALID, int)
+    GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int)
+    GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int)
+END_REGISTER(SQ_DEBUG_CONST_MGR_FSM)
+
+START_REGISTER(SQ_DEBUG_TP_FSM)
+    GENERATE_FIELD(EX_TP, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_TP, int)
+    GENERATE_FIELD(IF_TP, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(TIS_TP, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(GS_TP, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(FCR_TP, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(FCS_TP, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_TP, int)
+END_REGISTER(SQ_DEBUG_TP_FSM)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_0)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_0)
+
+START_REGISTER(SQ_DEBUG_FSM_ALU_1)
+    GENERATE_FIELD(EX_ALU_0, int)
+    GENERATE_FIELD(RESERVED0, int)
+    GENERATE_FIELD(CF_ALU_0, int)
+    GENERATE_FIELD(IF_ALU_0, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(DU1_ALU_0, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(DU0_ALU_0, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(AIS_ALU_0, int)
+    GENERATE_FIELD(RESERVED4, int)
+    GENERATE_FIELD(ACS_ALU_0, int)
+    GENERATE_FIELD(RESERVED5, int)
+    GENERATE_FIELD(ARB_TR_ALU, int)
+END_REGISTER(SQ_DEBUG_FSM_ALU_1)
+
+START_REGISTER(SQ_DEBUG_EXP_ALLOC)
+    GENERATE_FIELD(POS_BUF_AVAIL, int)
+    GENERATE_FIELD(COLOR_BUF_AVAIL, int)
+    GENERATE_FIELD(EA_BUF_AVAIL, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int)
+END_REGISTER(SQ_DEBUG_EXP_ALLOC)
+
+START_REGISTER(SQ_DEBUG_PTR_BUFF)
+    GENERATE_FIELD(END_OF_BUFFER, int)
+    GENERATE_FIELD(DEALLOC_CNT, int)
+    GENERATE_FIELD(QUAL_NEW_VECTOR, int)
+    GENERATE_FIELD(EVENT_CONTEXT_ID, int)
+    GENERATE_FIELD(SC_EVENT_ID, int)
+    GENERATE_FIELD(QUAL_EVENT, int)
+    GENERATE_FIELD(PRIM_TYPE_POLYGON, int)
+    GENERATE_FIELD(EF_EMPTY, int)
+    GENERATE_FIELD(VTX_SYNC_CNT, int)
+END_REGISTER(SQ_DEBUG_PTR_BUFF)
+
+START_REGISTER(SQ_DEBUG_GPR_VTX)
+    GENERATE_FIELD(VTX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(VTX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(VTX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(VTX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_VTX)
+
+START_REGISTER(SQ_DEBUG_GPR_PIX)
+    GENERATE_FIELD(PIX_TAIL_PTR, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(PIX_MAX, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(PIX_FREE, int)
+END_REGISTER(SQ_DEBUG_GPR_PIX)
+
+START_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+    GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int)
+    GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int)
+    GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int)
+    GENERATE_FIELD(VC_THREAD_BUF_DLY, int)
+    GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int)
+END_REGISTER(SQ_DEBUG_TB_STATUS_SEL)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_0)
+    GENERATE_FIELD(VTX_HEAD_PTR_Q, int)
+    GENERATE_FIELD(TAIL_PTR_Q, int)
+    GENERATE_FIELD(FULL_CNT_Q, int)
+    GENERATE_FIELD(NXT_POS_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PC_ALLOC_CNT, int)
+    GENERATE_FIELD(SX_EVENT_FULL, int)
+    GENERATE_FIELD(BUSY_Q, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_0)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_1)
+    GENERATE_FIELD(VS_DONE_PTR, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_1)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+    GENERATE_FIELD(VS_STATUS_REG, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG)
+
+START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+    GENERATE_FIELD(VS_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_0)
+    GENERATE_FIELD(PIX_HEAD_PTR, int)
+    GENERATE_FIELD(TAIL_PTR, int)
+    GENERATE_FIELD(FULL_CNT, int)
+    GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int)
+    GENERATE_FIELD(NXT_PIX_EXP_CNT, int)
+    GENERATE_FIELD(BUSY, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_0, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_1, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_2, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+    GENERATE_FIELD(PIX_TB_STATUS_REG_3, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3)
+
+START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+    GENERATE_FIELD(PIX_TB_STATE_MEM, int)
+END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM)
+
+START_REGISTER(SQ_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT)
+END_REGISTER(SQ_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER1_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER2_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER2_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER3_SELECT)
+    GENERATE_FIELD(PERF_SEL, int)
+END_REGISTER(SQ_PERFCOUNTER3_SELECT)
+
+START_REGISTER(SQ_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER1_HI)
+
+START_REGISTER(SQ_PERFCOUNTER2_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER2_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER2_HI)
+
+START_REGISTER(SQ_PERFCOUNTER3_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_LOW)
+
+START_REGISTER(SQ_PERFCOUNTER3_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SQ_PERFCOUNTER3_HI)
+
+START_REGISTER(SX_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT)
+END_REGISTER(SX_PERFCOUNTER0_SELECT)
+
+START_REGISTER(SX_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_LOW)
+
+START_REGISTER(SX_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(SX_PERFCOUNTER0_HI)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_0)
+    GENERATE_FIELD(VECTOR_RESULT, int)
+    GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier)
+    GENERATE_FIELD(LOW_PRECISION_16B_FP, int)
+    GENERATE_FIELD(SCALAR_RESULT, int)
+    GENERATE_FIELD(SCALAR_DST_REL, int)
+    GENERATE_FIELD(EXPORT_DATA, Exporting)
+    GENERATE_FIELD(VECTOR_WRT_MSK, int)
+    GENERATE_FIELD(SCALAR_WRT_MSK, int)
+    GENERATE_FIELD(VECTOR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_CLAMP, int)
+    GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode)
+END_REGISTER(SQ_INSTRUCTION_ALU_0)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_1)
+    GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType)
+    GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType)
+    GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier)
+    GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier)
+    GENERATE_FIELD(PRED_SELECT, PredicateSelect)
+    GENERATE_FIELD(RELATIVE_ADDR, int)
+    GENERATE_FIELD(CONST_1_REL_ABS, int)
+    GENERATE_FIELD(CONST_0_REL_ABS, int)
+END_REGISTER(SQ_INSTRUCTION_ALU_1)
+
+START_REGISTER(SQ_INSTRUCTION_ALU_2)
+    GENERATE_FIELD(SRC_C_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_C, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier)
+    GENERATE_FIELD(SRC_B_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_B, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier)
+    GENERATE_FIELD(SRC_A_REG_PTR, int)
+    GENERATE_FIELD(REG_SELECT_A, OperandSelect1)
+    GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier)
+    GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode)
+    GENERATE_FIELD(SRC_C_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_B_SEL, OperandSelect0)
+    GENERATE_FIELD(SRC_A_SEL, OperandSelect0)
+END_REGISTER(SQ_INSTRUCTION_ALU_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(COUNT, int)
+    GENERATE_FIELD(YIELD, int)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+    GENERATE_FIELD(INST_TYPE_0, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_0, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_1, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_1, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_2, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_2, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_3, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_3, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_4, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_4, Instruction_serial)
+    GENERATE_FIELD(INST_TYPE_5, Ressource_type)
+    GENERATE_FIELD(INST_SERIAL_5, Instruction_serial)
+    GENERATE_FIELD(INST_VC_0, VC_type)
+    GENERATE_FIELD(INST_VC_1, VC_type)
+    GENERATE_FIELD(INST_VC_2, VC_type)
+    GENERATE_FIELD(INST_VC_3, VC_type)
+    GENERATE_FIELD(INST_VC_4, VC_type)
+    GENERATE_FIELD(INST_VC_5, VC_type)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+    GENERATE_FIELD(LOOP_ID, int)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(PREDICATED_JMP, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(ADDRESS, int)
+    GENERATE_FIELD(RESERVED_1, int)
+    GENERATE_FIELD(FORCE_CALL, int)
+    GENERATE_FIELD(RESERVED_2, int)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(DIRECTION, int)
+    GENERATE_FIELD(BOOL_ADDR, int)
+    GENERATE_FIELD(CONDITION, int)
+    GENERATE_FIELD(ADDRESS_MODE, Addressing)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+    GENERATE_FIELD(RESERVED_0, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+    GENERATE_FIELD(SIZE, int)
+    GENERATE_FIELD(RESERVED_1, int)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1)
+
+START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+    GENERATE_FIELD(RESERVED, int)
+    GENERATE_FIELD(NO_SERIAL, int)
+    GENERATE_FIELD(BUFFER_SELECT, Allocation_type)
+    GENERATE_FIELD(ALLOC_MODE, int)
+    GENERATE_FIELD(OPCODE, CFOpcode)
+END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+    GENERATE_FIELD(OPCODE, TexInstOpcode)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, Addressmode)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, Addressmode)
+    GENERATE_FIELD(FETCH_VALID_ONLY, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm)
+    GENERATE_FIELD(SRC_SEL_X, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Y, SrcSel)
+    GENERATE_FIELD(SRC_SEL_Z, SrcSel)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, DstSel)
+    GENERATE_FIELD(DST_SEL_Y, DstSel)
+    GENERATE_FIELD(DST_SEL_Z, DstSel)
+    GENERATE_FIELD(DST_SEL_W, DstSel)
+    GENERATE_FIELD(MAG_FILTER, MagFilter)
+    GENERATE_FIELD(MIN_FILTER, MinFilter)
+    GENERATE_FIELD(MIP_FILTER, MipFilter)
+    GENERATE_FIELD(ANISO_FILTER, AnisoFilter)
+    GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter)
+    GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter)
+    GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter)
+    GENERATE_FIELD(USE_COMP_LOD, int)
+    GENERATE_FIELD(USE_REG_LOD, int)
+    GENERATE_FIELD(PRED_SELECT, PredSelect)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+    GENERATE_FIELD(USE_REG_GRADIENTS, int)
+    GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation)
+    GENERATE_FIELD(LOD_BIAS, int)
+    GENERATE_FIELD(UNUSED, int)
+    GENERATE_FIELD(OFFSET_X, int)
+    GENERATE_FIELD(OFFSET_Y, int)
+    GENERATE_FIELD(OFFSET_Z, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_TFETCH_2)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+    GENERATE_FIELD(OPCODE, int)
+    GENERATE_FIELD(SRC_GPR, int)
+    GENERATE_FIELD(SRC_GPR_AM, int)
+    GENERATE_FIELD(DST_GPR, int)
+    GENERATE_FIELD(DST_GPR_AM, int)
+    GENERATE_FIELD(MUST_BE_ONE, int)
+    GENERATE_FIELD(CONST_INDEX, int)
+    GENERATE_FIELD(CONST_INDEX_SEL, int)
+    GENERATE_FIELD(SRC_SEL, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_0)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+    GENERATE_FIELD(DST_SEL_X, int)
+    GENERATE_FIELD(DST_SEL_Y, int)
+    GENERATE_FIELD(DST_SEL_Z, int)
+    GENERATE_FIELD(DST_SEL_W, int)
+    GENERATE_FIELD(FORMAT_COMP_ALL, int)
+    GENERATE_FIELD(NUM_FORMAT_ALL, int)
+    GENERATE_FIELD(SIGNED_RF_MODE_ALL, int)
+    GENERATE_FIELD(DATA_FORMAT, int)
+    GENERATE_FIELD(EXP_ADJUST_ALL, int)
+    GENERATE_FIELD(PRED_SELECT, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_1)
+
+START_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+    GENERATE_FIELD(STRIDE, int)
+    GENERATE_FIELD(OFFSET, int)
+    GENERATE_FIELD(PRED_CONDITION, int)
+END_REGISTER(SQ_INSTRUCTION_VFETCH_2)
+
+START_REGISTER(SQ_CONSTANT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_0)
+
+START_REGISTER(SQ_CONSTANT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_1)
+
+START_REGISTER(SQ_CONSTANT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_2)
+
+START_REGISTER(SQ_CONSTANT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_3)
+
+START_REGISTER(SQ_FETCH_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_0)
+
+START_REGISTER(SQ_FETCH_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_1)
+
+START_REGISTER(SQ_FETCH_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_2)
+
+START_REGISTER(SQ_FETCH_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_3)
+
+START_REGISTER(SQ_FETCH_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_4)
+
+START_REGISTER(SQ_FETCH_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_5)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_0)
+    GENERATE_FIELD(TYPE, int)
+    GENERATE_FIELD(STATE, int)
+    GENERATE_FIELD(BASE_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_0)
+
+START_REGISTER(SQ_CONSTANT_VFETCH_1)
+    GENERATE_FIELD(ENDIAN_SWAP, int)
+    GENERATE_FIELD(LIMIT_ADDRESS, hex)
+END_REGISTER(SQ_CONSTANT_VFETCH_1)
+
+START_REGISTER(SQ_CONSTANT_T2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T2)
+
+START_REGISTER(SQ_CONSTANT_T3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_CONSTANT_T3)
+
+START_REGISTER(SQ_CF_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_BOOLEANS)
+
+START_REGISTER(SQ_CF_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_LOOP)
+
+START_REGISTER(SQ_CONSTANT_RT_0)
+    GENERATE_FIELD(RED, float)
+END_REGISTER(SQ_CONSTANT_RT_0)
+
+START_REGISTER(SQ_CONSTANT_RT_1)
+    GENERATE_FIELD(GREEN, float)
+END_REGISTER(SQ_CONSTANT_RT_1)
+
+START_REGISTER(SQ_CONSTANT_RT_2)
+    GENERATE_FIELD(BLUE, float)
+END_REGISTER(SQ_CONSTANT_RT_2)
+
+START_REGISTER(SQ_CONSTANT_RT_3)
+    GENERATE_FIELD(ALPHA, float)
+END_REGISTER(SQ_CONSTANT_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_0)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_0)
+
+START_REGISTER(SQ_FETCH_RT_1)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_1)
+
+START_REGISTER(SQ_FETCH_RT_2)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_2)
+
+START_REGISTER(SQ_FETCH_RT_3)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_3)
+
+START_REGISTER(SQ_FETCH_RT_4)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_4)
+
+START_REGISTER(SQ_FETCH_RT_5)
+    GENERATE_FIELD(VALUE, int)
+END_REGISTER(SQ_FETCH_RT_5)
+
+START_REGISTER(SQ_CF_RT_BOOLEANS)
+    GENERATE_FIELD(CF_BOOLEANS_0, int)
+    GENERATE_FIELD(CF_BOOLEANS_1, int)
+    GENERATE_FIELD(CF_BOOLEANS_2, int)
+    GENERATE_FIELD(CF_BOOLEANS_3, int)
+END_REGISTER(SQ_CF_RT_BOOLEANS)
+
+START_REGISTER(SQ_CF_RT_LOOP)
+    GENERATE_FIELD(CF_LOOP_COUNT, int)
+    GENERATE_FIELD(CF_LOOP_START, int)
+    GENERATE_FIELD(CF_LOOP_STEP, int)
+END_REGISTER(SQ_CF_RT_LOOP)
+
+START_REGISTER(SQ_VS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_PROGRAM)
+
+START_REGISTER(SQ_PS_PROGRAM)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_PROGRAM)
+
+START_REGISTER(SQ_CF_PROGRAM_SIZE)
+    GENERATE_FIELD(VS_CF_SIZE, int)
+    GENERATE_FIELD(PS_CF_SIZE, int)
+END_REGISTER(SQ_CF_PROGRAM_SIZE)
+
+START_REGISTER(SQ_INTERPOLATOR_CNTL)
+    GENERATE_FIELD(PARAM_SHADE, ParamShade)
+    GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern)
+END_REGISTER(SQ_INTERPOLATOR_CNTL)
+
+START_REGISTER(SQ_PROGRAM_CNTL)
+    GENERATE_FIELD(VS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(PS_NUM_REG, intMinusOne)
+    GENERATE_FIELD(VS_RESOURCE, int)
+    GENERATE_FIELD(PS_RESOURCE, int)
+    GENERATE_FIELD(PARAM_GEN, int)
+    GENERATE_FIELD(GEN_INDEX_PIX, int)
+    GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne)
+    GENERATE_FIELD(VS_EXPORT_MODE, VertexMode)
+    GENERATE_FIELD(PS_EXPORT_MODE, int)
+    GENERATE_FIELD(GEN_INDEX_VTX, int)
+END_REGISTER(SQ_PROGRAM_CNTL)
+
+START_REGISTER(SQ_WRAPPING_0)
+    GENERATE_FIELD(PARAM_WRAP_0, hex)
+    GENERATE_FIELD(PARAM_WRAP_1, hex)
+    GENERATE_FIELD(PARAM_WRAP_2, hex)
+    GENERATE_FIELD(PARAM_WRAP_3, hex)
+    GENERATE_FIELD(PARAM_WRAP_4, hex)
+    GENERATE_FIELD(PARAM_WRAP_5, hex)
+    GENERATE_FIELD(PARAM_WRAP_6, hex)
+    GENERATE_FIELD(PARAM_WRAP_7, hex)
+END_REGISTER(SQ_WRAPPING_0)
+
+START_REGISTER(SQ_WRAPPING_1)
+    GENERATE_FIELD(PARAM_WRAP_8, hex)
+    GENERATE_FIELD(PARAM_WRAP_9, hex)
+    GENERATE_FIELD(PARAM_WRAP_10, hex)
+    GENERATE_FIELD(PARAM_WRAP_11, hex)
+    GENERATE_FIELD(PARAM_WRAP_12, hex)
+    GENERATE_FIELD(PARAM_WRAP_13, hex)
+    GENERATE_FIELD(PARAM_WRAP_14, hex)
+    GENERATE_FIELD(PARAM_WRAP_15, hex)
+END_REGISTER(SQ_WRAPPING_1)
+
+START_REGISTER(SQ_VS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_VS_CONST)
+
+START_REGISTER(SQ_PS_CONST)
+    GENERATE_FIELD(BASE, int)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(SQ_PS_CONST)
+
+START_REGISTER(SQ_CONTEXT_MISC)
+    GENERATE_FIELD(INST_PRED_OPTIMIZE, int)
+    GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int)
+    GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl)
+    GENERATE_FIELD(PARAM_GEN_POS, int)
+    GENERATE_FIELD(PERFCOUNTER_REF, int)
+    GENERATE_FIELD(YEILD_OPTIMIZE, int)
+    GENERATE_FIELD(TX_CACHE_SEL, int)
+END_REGISTER(SQ_CONTEXT_MISC)
+
+START_REGISTER(SQ_CF_RD_BASE)
+    GENERATE_FIELD(RD_BASE, hex)
+END_REGISTER(SQ_CF_RD_BASE)
+
+START_REGISTER(SQ_DEBUG_MISC_0)
+    GENERATE_FIELD(DB_PROB_ON, int)
+    GENERATE_FIELD(DB_PROB_BREAK, int)
+    GENERATE_FIELD(DB_PROB_ADDR, int)
+    GENERATE_FIELD(DB_PROB_COUNT, int)
+END_REGISTER(SQ_DEBUG_MISC_0)
+
+START_REGISTER(SQ_DEBUG_MISC_1)
+    GENERATE_FIELD(DB_ON_PIX, int)
+    GENERATE_FIELD(DB_ON_VTX, int)
+    GENERATE_FIELD(DB_INST_COUNT, int)
+    GENERATE_FIELD(DB_BREAK_ADDR, int)
+END_REGISTER(SQ_DEBUG_MISC_1)
+
+START_REGISTER(MH_ARBITER_CONFIG)
+    GENERATE_FIELD(SAME_PAGE_LIMIT, int)
+    GENERATE_FIELD(SAME_PAGE_GRANULARITY, int)
+    GENERATE_FIELD(L1_ARB_ENABLE, bool)
+    GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int)
+    GENERATE_FIELD(L2_ARB_CONTROL, int)
+    GENERATE_FIELD(PAGE_SIZE, int)
+    GENERATE_FIELD(TC_REORDER_ENABLE, bool)
+    GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool)
+    GENERATE_FIELD(IN_FLIGHT_LIMIT, int)
+    GENERATE_FIELD(CP_CLNT_ENABLE, bool)
+    GENERATE_FIELD(VGT_CLNT_ENABLE, bool)
+    GENERATE_FIELD(TC_CLNT_ENABLE, bool)
+    GENERATE_FIELD(RB_CLNT_ENABLE, bool)
+    GENERATE_FIELD(PA_CLNT_ENABLE, bool)
+END_REGISTER(MH_ARBITER_CONFIG)
+
+START_REGISTER(MH_CLNT_AXI_ID_REUSE)
+    GENERATE_FIELD(CPw_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RBw_ID, int)
+    GENERATE_FIELD(RESERVED2, int)
+    GENERATE_FIELD(MMUr_ID, int)
+    GENERATE_FIELD(RESERVED3, int)
+    GENERATE_FIELD(PAw_ID, int)
+END_REGISTER(MH_CLNT_AXI_ID_REUSE)
+
+START_REGISTER(MH_INTERRUPT_MASK)
+    GENERATE_FIELD(AXI_READ_ERROR, bool)
+    GENERATE_FIELD(AXI_WRITE_ERROR, bool)
+    GENERATE_FIELD(MMU_PAGE_FAULT, bool)
+END_REGISTER(MH_INTERRUPT_MASK)
+
+START_REGISTER(MH_INTERRUPT_STATUS)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_STATUS)
+
+START_REGISTER(MH_INTERRUPT_CLEAR)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+    GENERATE_FIELD(MMU_PAGE_FAULT, int)
+END_REGISTER(MH_INTERRUPT_CLEAR)
+
+START_REGISTER(MH_AXI_ERROR)
+    GENERATE_FIELD(AXI_READ_ID, int)
+    GENERATE_FIELD(AXI_READ_ERROR, int)
+    GENERATE_FIELD(AXI_WRITE_ID, int)
+    GENERATE_FIELD(AXI_WRITE_ERROR, int)
+END_REGISTER(MH_AXI_ERROR)
+
+START_REGISTER(MH_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER0_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_SEL, MhPerfEncode)
+END_REGISTER(MH_PERFCOUNTER1_SELECT)
+
+START_REGISTER(MH_PERFCOUNTER0_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER0_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER1_CONFIG)
+    GENERATE_FIELD(N_VALUE, int)
+END_REGISTER(MH_PERFCOUNTER1_CONFIG)
+
+START_REGISTER(MH_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER0_LOW)
+
+START_REGISTER(MH_PERFCOUNTER1_LOW)
+    GENERATE_FIELD(PERF_COUNTER_LOW, int)
+END_REGISTER(MH_PERFCOUNTER1_LOW)
+
+START_REGISTER(MH_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER0_HI)
+
+START_REGISTER(MH_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNTER_HI, int)
+END_REGISTER(MH_PERFCOUNTER1_HI)
+
+START_REGISTER(MH_DEBUG_CTRL)
+    GENERATE_FIELD(INDEX, int)
+END_REGISTER(MH_DEBUG_CTRL)
+
+START_REGISTER(MH_DEBUG_DATA)
+    GENERATE_FIELD(DATA, int)
+END_REGISTER(MH_DEBUG_DATA)
+
+START_REGISTER(MH_AXI_HALT_CONTROL)
+    GENERATE_FIELD(AXI_HALT, bool)
+END_REGISTER(MH_AXI_HALT_CONTROL)
+
+START_REGISTER(MH_MMU_CONFIG)
+    GENERATE_FIELD(MMU_ENABLE, bool)
+    GENERATE_FIELD(SPLIT_MODE_ENABLE, bool)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh)
+END_REGISTER(MH_MMU_CONFIG)
+
+START_REGISTER(MH_MMU_VA_RANGE)
+    GENERATE_FIELD(NUM_64KB_REGIONS, int)
+    GENERATE_FIELD(VA_BASE, int)
+END_REGISTER(MH_MMU_VA_RANGE)
+
+START_REGISTER(MH_MMU_PT_BASE)
+    GENERATE_FIELD(PT_BASE, int)
+END_REGISTER(MH_MMU_PT_BASE)
+
+START_REGISTER(MH_MMU_PAGE_FAULT)
+    GENERATE_FIELD(PAGE_FAULT, int)
+    GENERATE_FIELD(OP_TYPE, int)
+    GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh)
+    GENERATE_FIELD(AXI_ID, int)
+    GENERATE_FIELD(RESERVED1, int)
+    GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int)
+    GENERATE_FIELD(READ_PROTECTION_ERROR, int)
+    GENERATE_FIELD(WRITE_PROTECTION_ERROR, int)
+    GENERATE_FIELD(REQ_VA, int)
+END_REGISTER(MH_MMU_PAGE_FAULT)
+
+START_REGISTER(MH_MMU_TRAN_ERROR)
+    GENERATE_FIELD(TRAN_ERROR, int)
+END_REGISTER(MH_MMU_TRAN_ERROR)
+
+START_REGISTER(MH_MMU_INVALIDATE)
+    GENERATE_FIELD(INVALIDATE_ALL, int)
+    GENERATE_FIELD(INVALIDATE_TC, int)
+END_REGISTER(MH_MMU_INVALIDATE)
+
+START_REGISTER(MH_MMU_MPU_BASE)
+    GENERATE_FIELD(MPU_BASE, int)
+END_REGISTER(MH_MMU_MPU_BASE)
+
+START_REGISTER(MH_MMU_MPU_END)
+    GENERATE_FIELD(MPU_END, int)
+END_REGISTER(MH_MMU_MPU_END)
+
+START_REGISTER(WAIT_UNTIL)
+    GENERATE_FIELD(WAIT_RE_VSYNC, int)
+    GENERATE_FIELD(WAIT_FE_VSYNC, int)
+    GENERATE_FIELD(WAIT_VSYNC, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID0, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID1, int)
+    GENERATE_FIELD(WAIT_DSPLY_ID2, int)
+    GENERATE_FIELD(WAIT_CMDFIFO, int)
+    GENERATE_FIELD(WAIT_2D_IDLE, int)
+    GENERATE_FIELD(WAIT_3D_IDLE, int)
+    GENERATE_FIELD(WAIT_2D_IDLECLEAN, int)
+    GENERATE_FIELD(WAIT_3D_IDLECLEAN, int)
+    GENERATE_FIELD(CMDFIFO_ENTRIES, int)
+END_REGISTER(WAIT_UNTIL)
+
+START_REGISTER(RBBM_ISYNC_CNTL)
+    GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int)
+    GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int)
+END_REGISTER(RBBM_ISYNC_CNTL)
+
+START_REGISTER(RBBM_STATUS)
+    GENERATE_FIELD(CMDFIFO_AVAIL, int)
+    GENERATE_FIELD(TC_BUSY, int)
+    GENERATE_FIELD(HIRQ_PENDING, int)
+    GENERATE_FIELD(CPRQ_PENDING, int)
+    GENERATE_FIELD(CFRQ_PENDING, int)
+    GENERATE_FIELD(PFRQ_PENDING, int)
+    GENERATE_FIELD(VGT_BUSY_NO_DMA, int)
+    GENERATE_FIELD(RBBM_WU_BUSY, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(MH_BUSY, int)
+    GENERATE_FIELD(MH_COHERENCY_BUSY, int)
+    GENERATE_FIELD(SX_BUSY, int)
+    GENERATE_FIELD(TPC_BUSY, int)
+    GENERATE_FIELD(SC_CNTX_BUSY, int)
+    GENERATE_FIELD(PA_BUSY, int)
+    GENERATE_FIELD(VGT_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX17_BUSY, int)
+    GENERATE_FIELD(SQ_CNTX0_BUSY, int)
+    GENERATE_FIELD(RB_CNTX_BUSY, int)
+    GENERATE_FIELD(GUI_ACTIVE, int)
+END_REGISTER(RBBM_STATUS)
+
+START_REGISTER(RBBM_DSPLY)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int)
+    GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int)
+    GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH1_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH1_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH1_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH2_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH2_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH2_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CHANNEL_SELECT, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH3_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH3_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH3_NUM_BUFS, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID0, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID1, int)
+    GENERATE_FIELD(DMI_CH4_USE_BUFID2, int)
+    GENERATE_FIELD(DMI_CH4_SW_CNTL, int)
+    GENERATE_FIELD(DMI_CH4_NUM_BUFS, int)
+END_REGISTER(RBBM_DSPLY)
+
+START_REGISTER(RBBM_RENDER_LATEST)
+    GENERATE_FIELD(DMI_CH1_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH2_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH3_BUFFER_ID, int)
+    GENERATE_FIELD(DMI_CH4_BUFFER_ID, int)
+END_REGISTER(RBBM_RENDER_LATEST)
+
+START_REGISTER(RBBM_RTL_RELEASE)
+    GENERATE_FIELD(CHANGELIST, int)
+END_REGISTER(RBBM_RTL_RELEASE)
+
+START_REGISTER(RBBM_PATCH_RELEASE)
+    GENERATE_FIELD(PATCH_REVISION, int)
+    GENERATE_FIELD(PATCH_SELECTION, int)
+    GENERATE_FIELD(CUSTOMER_ID, int)
+END_REGISTER(RBBM_PATCH_RELEASE)
+
+START_REGISTER(RBBM_AUXILIARY_CONFIG)
+    GENERATE_FIELD(RESERVED, int)
+END_REGISTER(RBBM_AUXILIARY_CONFIG)
+
+START_REGISTER(RBBM_PERIPHID0)
+    GENERATE_FIELD(PARTNUMBER0, int)
+END_REGISTER(RBBM_PERIPHID0)
+
+START_REGISTER(RBBM_PERIPHID1)
+    GENERATE_FIELD(PARTNUMBER1, int)
+    GENERATE_FIELD(DESIGNER0, int)
+END_REGISTER(RBBM_PERIPHID1)
+
+START_REGISTER(RBBM_PERIPHID2)
+    GENERATE_FIELD(DESIGNER1, int)
+    GENERATE_FIELD(REVISION, int)
+END_REGISTER(RBBM_PERIPHID2)
+
+START_REGISTER(RBBM_PERIPHID3)
+    GENERATE_FIELD(RBBM_HOST_INTERFACE, int)
+    GENERATE_FIELD(GARB_SLAVE_INTERFACE, int)
+    GENERATE_FIELD(MH_INTERFACE, int)
+    GENERATE_FIELD(CONTINUATION, int)
+END_REGISTER(RBBM_PERIPHID3)
+
+START_REGISTER(RBBM_CNTL)
+    GENERATE_FIELD(READ_TIMEOUT, int)
+    GENERATE_FIELD(REGCLK_DEASSERT_TIME, int)
+END_REGISTER(RBBM_CNTL)
+
+START_REGISTER(RBBM_SKEW_CNTL)
+    GENERATE_FIELD(SKEW_TOP_THRESHOLD, int)
+    GENERATE_FIELD(SKEW_COUNT, int)
+END_REGISTER(RBBM_SKEW_CNTL)
+
+START_REGISTER(RBBM_SOFT_RESET)
+    GENERATE_FIELD(SOFT_RESET_CP, int)
+    GENERATE_FIELD(SOFT_RESET_PA, int)
+    GENERATE_FIELD(SOFT_RESET_MH, int)
+    GENERATE_FIELD(SOFT_RESET_BC, int)
+    GENERATE_FIELD(SOFT_RESET_SQ, int)
+    GENERATE_FIELD(SOFT_RESET_SX, int)
+    GENERATE_FIELD(SOFT_RESET_CIB, int)
+    GENERATE_FIELD(SOFT_RESET_SC, int)
+    GENERATE_FIELD(SOFT_RESET_VGT, int)
+END_REGISTER(RBBM_SOFT_RESET)
+
+START_REGISTER(RBBM_PM_OVERRIDE1)
+    GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE1)
+
+START_REGISTER(RBBM_PM_OVERRIDE2)
+    GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int)
+    GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int)
+END_REGISTER(RBBM_PM_OVERRIDE2)
+
+START_REGISTER(GC_SYS_IDLE)
+    GENERATE_FIELD(GC_SYS_IDLE_DELAY, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI, int)
+    GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int)
+    GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int)
+END_REGISTER(GC_SYS_IDLE)
+
+START_REGISTER(NQWAIT_UNTIL)
+    GENERATE_FIELD(WAIT_GUI_IDLE, int)
+END_REGISTER(NQWAIT_UNTIL)
+
+START_REGISTER(RBBM_DEBUG_OUT)
+    GENERATE_FIELD(DEBUG_BUS_OUT, int)
+END_REGISTER(RBBM_DEBUG_OUT)
+
+START_REGISTER(RBBM_DEBUG_CNTL)
+    GENERATE_FIELD(SUB_BLOCK_ADDR, int)
+    GENERATE_FIELD(SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(SW_ENABLE, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int)
+    GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int)
+    GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int)
+END_REGISTER(RBBM_DEBUG_CNTL)
+
+START_REGISTER(RBBM_DEBUG)
+    GENERATE_FIELD(IGNORE_RTR, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_WU, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int)
+    GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int)
+    GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int)
+    GENERATE_FIELD(IGNORE_RTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int)
+    GENERATE_FIELD(CP_RBBM_NRTRTR, int)
+    GENERATE_FIELD(VGT_RBBM_NRTRTR, int)
+    GENERATE_FIELD(SQ_RBBM_NRTRTR, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int)
+    GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int)
+    GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int)
+END_REGISTER(RBBM_DEBUG)
+
+START_REGISTER(RBBM_READ_ERROR)
+    GENERATE_FIELD(READ_ADDRESS, int)
+    GENERATE_FIELD(READ_REQUESTER, int)
+    GENERATE_FIELD(READ_ERROR, int)
+END_REGISTER(RBBM_READ_ERROR)
+
+START_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+    GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int)
+END_REGISTER(RBBM_WAIT_IDLE_CLOCKS)
+
+START_REGISTER(RBBM_INT_CNTL)
+    GENERATE_FIELD(RDERR_INT_MASK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_MASK, int)
+END_REGISTER(RBBM_INT_CNTL)
+
+START_REGISTER(RBBM_INT_STATUS)
+    GENERATE_FIELD(RDERR_INT_STAT, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int)
+    GENERATE_FIELD(GUI_IDLE_INT_STAT, int)
+END_REGISTER(RBBM_INT_STATUS)
+
+START_REGISTER(RBBM_INT_ACK)
+    GENERATE_FIELD(RDERR_INT_ACK, int)
+    GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int)
+    GENERATE_FIELD(GUI_IDLE_INT_ACK, int)
+END_REGISTER(RBBM_INT_ACK)
+
+START_REGISTER(MASTER_INT_SIGNAL)
+    GENERATE_FIELD(MH_INT_STAT, int)
+    GENERATE_FIELD(SQ_INT_STAT, int)
+    GENERATE_FIELD(CP_INT_STAT, int)
+    GENERATE_FIELD(RBBM_INT_STAT, int)
+END_REGISTER(MASTER_INT_SIGNAL)
+
+START_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+    GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL)
+END_REGISTER(RBBM_PERFCOUNTER1_SELECT)
+
+START_REGISTER(RBBM_PERFCOUNTER1_LO)
+    GENERATE_FIELD(PERF_COUNT1_LO, int)
+END_REGISTER(RBBM_PERFCOUNTER1_LO)
+
+START_REGISTER(RBBM_PERFCOUNTER1_HI)
+    GENERATE_FIELD(PERF_COUNT1_HI, int)
+END_REGISTER(RBBM_PERFCOUNTER1_HI)
+
+START_REGISTER(CP_RB_BASE)
+    GENERATE_FIELD(RB_BASE, int)
+END_REGISTER(CP_RB_BASE)
+
+START_REGISTER(CP_RB_CNTL)
+    GENERATE_FIELD(RB_BUFSZ, int)
+    GENERATE_FIELD(RB_BLKSZ, int)
+    GENERATE_FIELD(BUF_SWAP, int)
+    GENERATE_FIELD(RB_POLL_EN, int)
+    GENERATE_FIELD(RB_NO_UPDATE, int)
+    GENERATE_FIELD(RB_RPTR_WR_ENA, int)
+END_REGISTER(CP_RB_CNTL)
+
+START_REGISTER(CP_RB_RPTR_ADDR)
+    GENERATE_FIELD(RB_RPTR_SWAP, int)
+    GENERATE_FIELD(RB_RPTR_ADDR, int)
+END_REGISTER(CP_RB_RPTR_ADDR)
+
+START_REGISTER(CP_RB_RPTR)
+    GENERATE_FIELD(RB_RPTR, int)
+END_REGISTER(CP_RB_RPTR)
+
+START_REGISTER(CP_RB_RPTR_WR)
+    GENERATE_FIELD(RB_RPTR_WR, int)
+END_REGISTER(CP_RB_RPTR_WR)
+
+START_REGISTER(CP_RB_WPTR)
+    GENERATE_FIELD(RB_WPTR, int)
+END_REGISTER(CP_RB_WPTR)
+
+START_REGISTER(CP_RB_WPTR_DELAY)
+    GENERATE_FIELD(PRE_WRITE_TIMER, int)
+    GENERATE_FIELD(PRE_WRITE_LIMIT, int)
+END_REGISTER(CP_RB_WPTR_DELAY)
+
+START_REGISTER(CP_RB_WPTR_BASE)
+    GENERATE_FIELD(RB_WPTR_SWAP, int)
+    GENERATE_FIELD(RB_WPTR_BASE, int)
+END_REGISTER(CP_RB_WPTR_BASE)
+
+START_REGISTER(CP_IB1_BASE)
+    GENERATE_FIELD(IB1_BASE, int)
+END_REGISTER(CP_IB1_BASE)
+
+START_REGISTER(CP_IB1_BUFSZ)
+    GENERATE_FIELD(IB1_BUFSZ, int)
+END_REGISTER(CP_IB1_BUFSZ)
+
+START_REGISTER(CP_IB2_BASE)
+    GENERATE_FIELD(IB2_BASE, int)
+END_REGISTER(CP_IB2_BASE)
+
+START_REGISTER(CP_IB2_BUFSZ)
+    GENERATE_FIELD(IB2_BUFSZ, int)
+END_REGISTER(CP_IB2_BUFSZ)
+
+START_REGISTER(CP_ST_BASE)
+    GENERATE_FIELD(ST_BASE, int)
+END_REGISTER(CP_ST_BASE)
+
+START_REGISTER(CP_ST_BUFSZ)
+    GENERATE_FIELD(ST_BUFSZ, int)
+END_REGISTER(CP_ST_BUFSZ)
+
+START_REGISTER(CP_QUEUE_THRESHOLDS)
+    GENERATE_FIELD(CSQ_IB1_START, int)
+    GENERATE_FIELD(CSQ_IB2_START, int)
+    GENERATE_FIELD(CSQ_ST_START, int)
+END_REGISTER(CP_QUEUE_THRESHOLDS)
+
+START_REGISTER(CP_MEQ_THRESHOLDS)
+    GENERATE_FIELD(MEQ_END, int)
+    GENERATE_FIELD(ROQ_END, int)
+END_REGISTER(CP_MEQ_THRESHOLDS)
+
+START_REGISTER(CP_CSQ_AVAIL)
+    GENERATE_FIELD(CSQ_CNT_RING, int)
+    GENERATE_FIELD(CSQ_CNT_IB1, int)
+    GENERATE_FIELD(CSQ_CNT_IB2, int)
+END_REGISTER(CP_CSQ_AVAIL)
+
+START_REGISTER(CP_STQ_AVAIL)
+    GENERATE_FIELD(STQ_CNT_ST, int)
+END_REGISTER(CP_STQ_AVAIL)
+
+START_REGISTER(CP_MEQ_AVAIL)
+    GENERATE_FIELD(MEQ_CNT, int)
+END_REGISTER(CP_MEQ_AVAIL)
+
+START_REGISTER(CP_CSQ_RB_STAT)
+    GENERATE_FIELD(CSQ_RPTR_PRIMARY, int)
+    GENERATE_FIELD(CSQ_WPTR_PRIMARY, int)
+END_REGISTER(CP_CSQ_RB_STAT)
+
+START_REGISTER(CP_CSQ_IB1_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int)
+END_REGISTER(CP_CSQ_IB1_STAT)
+
+START_REGISTER(CP_CSQ_IB2_STAT)
+    GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int)
+    GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int)
+END_REGISTER(CP_CSQ_IB2_STAT)
+
+START_REGISTER(CP_NON_PREFETCH_CNTRS)
+    GENERATE_FIELD(IB1_COUNTER, int)
+    GENERATE_FIELD(IB2_COUNTER, int)
+END_REGISTER(CP_NON_PREFETCH_CNTRS)
+
+START_REGISTER(CP_STQ_ST_STAT)
+    GENERATE_FIELD(STQ_RPTR_ST, int)
+    GENERATE_FIELD(STQ_WPTR_ST, int)
+END_REGISTER(CP_STQ_ST_STAT)
+
+START_REGISTER(CP_MEQ_STAT)
+    GENERATE_FIELD(MEQ_RPTR, int)
+    GENERATE_FIELD(MEQ_WPTR, int)
+END_REGISTER(CP_MEQ_STAT)
+
+START_REGISTER(CP_MIU_TAG_STAT)
+    GENERATE_FIELD(TAG_0_STAT, int)
+    GENERATE_FIELD(TAG_1_STAT, int)
+    GENERATE_FIELD(TAG_2_STAT, int)
+    GENERATE_FIELD(TAG_3_STAT, int)
+    GENERATE_FIELD(TAG_4_STAT, int)
+    GENERATE_FIELD(TAG_5_STAT, int)
+    GENERATE_FIELD(TAG_6_STAT, int)
+    GENERATE_FIELD(TAG_7_STAT, int)
+    GENERATE_FIELD(TAG_8_STAT, int)
+    GENERATE_FIELD(TAG_9_STAT, int)
+    GENERATE_FIELD(TAG_10_STAT, int)
+    GENERATE_FIELD(TAG_11_STAT, int)
+    GENERATE_FIELD(TAG_12_STAT, int)
+    GENERATE_FIELD(TAG_13_STAT, int)
+    GENERATE_FIELD(TAG_14_STAT, int)
+    GENERATE_FIELD(TAG_15_STAT, int)
+    GENERATE_FIELD(TAG_16_STAT, int)
+    GENERATE_FIELD(TAG_17_STAT, int)
+    GENERATE_FIELD(INVALID_RETURN_TAG, int)
+END_REGISTER(CP_MIU_TAG_STAT)
+
+START_REGISTER(CP_CMD_INDEX)
+    GENERATE_FIELD(CMD_INDEX, int)
+    GENERATE_FIELD(CMD_QUEUE_SEL, int)
+END_REGISTER(CP_CMD_INDEX)
+
+START_REGISTER(CP_CMD_DATA)
+    GENERATE_FIELD(CMD_DATA, int)
+END_REGISTER(CP_CMD_DATA)
+
+START_REGISTER(CP_ME_CNTL)
+    GENERATE_FIELD(ME_STATMUX, int)
+    GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int)
+    GENERATE_FIELD(ME_HALT, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(PROG_CNT_SIZE, int)
+END_REGISTER(CP_ME_CNTL)
+
+START_REGISTER(CP_ME_STATUS)
+    GENERATE_FIELD(ME_DEBUG_DATA, int)
+END_REGISTER(CP_ME_STATUS)
+
+START_REGISTER(CP_ME_RAM_WADDR)
+    GENERATE_FIELD(ME_RAM_WADDR, int)
+END_REGISTER(CP_ME_RAM_WADDR)
+
+START_REGISTER(CP_ME_RAM_RADDR)
+    GENERATE_FIELD(ME_RAM_RADDR, int)
+END_REGISTER(CP_ME_RAM_RADDR)
+
+START_REGISTER(CP_ME_RAM_DATA)
+    GENERATE_FIELD(ME_RAM_DATA, int)
+END_REGISTER(CP_ME_RAM_DATA)
+
+START_REGISTER(CP_ME_RDADDR)
+    GENERATE_FIELD(ME_RDADDR, int)
+END_REGISTER(CP_ME_RDADDR)
+
+START_REGISTER(CP_DEBUG)
+    GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int)
+    GENERATE_FIELD(PREDICATE_DISABLE, int)
+    GENERATE_FIELD(PROG_END_PTR_ENABLE, int)
+    GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int)
+    GENERATE_FIELD(PREFETCH_PASS_NOPS, int)
+    GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int)
+    GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int)
+    GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int)
+    GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int)
+END_REGISTER(CP_DEBUG)
+
+START_REGISTER(SCRATCH_REG0)
+    GENERATE_FIELD(SCRATCH_REG0, int)
+END_REGISTER(SCRATCH_REG0)
+
+START_REGISTER(SCRATCH_REG1)
+    GENERATE_FIELD(SCRATCH_REG1, int)
+END_REGISTER(SCRATCH_REG1)
+
+START_REGISTER(SCRATCH_REG2)
+    GENERATE_FIELD(SCRATCH_REG2, int)
+END_REGISTER(SCRATCH_REG2)
+
+START_REGISTER(SCRATCH_REG3)
+    GENERATE_FIELD(SCRATCH_REG3, int)
+END_REGISTER(SCRATCH_REG3)
+
+START_REGISTER(SCRATCH_REG4)
+    GENERATE_FIELD(SCRATCH_REG4, int)
+END_REGISTER(SCRATCH_REG4)
+
+START_REGISTER(SCRATCH_REG5)
+    GENERATE_FIELD(SCRATCH_REG5, int)
+END_REGISTER(SCRATCH_REG5)
+
+START_REGISTER(SCRATCH_REG6)
+    GENERATE_FIELD(SCRATCH_REG6, int)
+END_REGISTER(SCRATCH_REG6)
+
+START_REGISTER(SCRATCH_REG7)
+    GENERATE_FIELD(SCRATCH_REG7, int)
+END_REGISTER(SCRATCH_REG7)
+
+START_REGISTER(SCRATCH_UMSK)
+    GENERATE_FIELD(SCRATCH_UMSK, int)
+    GENERATE_FIELD(SCRATCH_SWAP, int)
+END_REGISTER(SCRATCH_UMSK)
+
+START_REGISTER(SCRATCH_ADDR)
+    GENERATE_FIELD(SCRATCH_ADDR, hex)
+END_REGISTER(SCRATCH_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_SRC)
+    GENERATE_FIELD(VS_DONE_SWM, int)
+    GENERATE_FIELD(VS_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_EVENT_SRC)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR)
+    GENERATE_FIELD(VS_DONE_SWAP, int)
+    GENERATE_FIELD(VS_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA)
+    GENERATE_FIELD(VS_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA)
+
+START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(VS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(VS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+    GENERATE_FIELD(VS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_VS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_SRC)
+    GENERATE_FIELD(PS_DONE_SWM, int)
+    GENERATE_FIELD(PS_DONE_CNTR, int)
+END_REGISTER(CP_ME_PS_EVENT_SRC)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR)
+    GENERATE_FIELD(PS_DONE_SWAP, int)
+    GENERATE_FIELD(PS_DONE_ADDR, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA)
+    GENERATE_FIELD(PS_DONE_DATA, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA)
+
+START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+    GENERATE_FIELD(PS_DONE_SWAP_SWM, int)
+    GENERATE_FIELD(PS_DONE_ADDR_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM)
+
+START_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+    GENERATE_FIELD(PS_DONE_DATA_SWM, int)
+END_REGISTER(CP_ME_PS_EVENT_DATA_SWM)
+
+START_REGISTER(CP_ME_CF_EVENT_SRC)
+    GENERATE_FIELD(CF_DONE_SRC, int)
+END_REGISTER(CP_ME_CF_EVENT_SRC)
+
+START_REGISTER(CP_ME_CF_EVENT_ADDR)
+    GENERATE_FIELD(CF_DONE_SWAP, int)
+    GENERATE_FIELD(CF_DONE_ADDR, int)
+END_REGISTER(CP_ME_CF_EVENT_ADDR)
+
+START_REGISTER(CP_ME_CF_EVENT_DATA)
+    GENERATE_FIELD(CF_DONE_DATA, int)
+END_REGISTER(CP_ME_CF_EVENT_DATA)
+
+START_REGISTER(CP_ME_NRT_ADDR)
+    GENERATE_FIELD(NRT_WRITE_SWAP, int)
+    GENERATE_FIELD(NRT_WRITE_ADDR, int)
+END_REGISTER(CP_ME_NRT_ADDR)
+
+START_REGISTER(CP_ME_NRT_DATA)
+    GENERATE_FIELD(NRT_WRITE_DATA, int)
+END_REGISTER(CP_ME_NRT_DATA)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+    GENERATE_FIELD(VS_FETCH_DONE_CNTR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_SRC)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+    GENERATE_FIELD(VS_FETCH_DONE_SWAP, int)
+    GENERATE_FIELD(VS_FETCH_DONE_ADDR, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR)
+
+START_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+    GENERATE_FIELD(VS_FETCH_DONE_DATA, int)
+END_REGISTER(CP_ME_VS_FETCH_DONE_DATA)
+
+START_REGISTER(CP_INT_CNTL)
+    GENERATE_FIELD(SW_INT_MASK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int)
+    GENERATE_FIELD(OPCODE_ERROR_MASK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int)
+    GENERATE_FIELD(IB_ERROR_MASK, int)
+    GENERATE_FIELD(IB2_INT_MASK, int)
+    GENERATE_FIELD(IB1_INT_MASK, int)
+    GENERATE_FIELD(RB_INT_MASK, int)
+END_REGISTER(CP_INT_CNTL)
+
+START_REGISTER(CP_INT_STATUS)
+    GENERATE_FIELD(SW_INT_STAT, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int)
+    GENERATE_FIELD(OPCODE_ERROR_STAT, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int)
+    GENERATE_FIELD(IB_ERROR_STAT, int)
+    GENERATE_FIELD(IB2_INT_STAT, int)
+    GENERATE_FIELD(IB1_INT_STAT, int)
+    GENERATE_FIELD(RB_INT_STAT, int)
+END_REGISTER(CP_INT_STATUS)
+
+START_REGISTER(CP_INT_ACK)
+    GENERATE_FIELD(SW_INT_ACK, int)
+    GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int)
+    GENERATE_FIELD(OPCODE_ERROR_ACK, int)
+    GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int)
+    GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int)
+    GENERATE_FIELD(IB_ERROR_ACK, int)
+    GENERATE_FIELD(IB2_INT_ACK, int)
+    GENERATE_FIELD(IB1_INT_ACK, int)
+    GENERATE_FIELD(RB_INT_ACK, int)
+END_REGISTER(CP_INT_ACK)
+
+START_REGISTER(CP_PFP_UCODE_ADDR)
+    GENERATE_FIELD(UCODE_ADDR, hex)
+END_REGISTER(CP_PFP_UCODE_ADDR)
+
+START_REGISTER(CP_PFP_UCODE_DATA)
+    GENERATE_FIELD(UCODE_DATA, hex)
+END_REGISTER(CP_PFP_UCODE_DATA)
+
+START_REGISTER(CP_PERFMON_CNTL)
+    GENERATE_FIELD(PERFMON_STATE, int)
+    GENERATE_FIELD(PERFMON_ENABLE_MODE, int)
+END_REGISTER(CP_PERFMON_CNTL)
+
+START_REGISTER(CP_PERFCOUNTER_SELECT)
+    GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL)
+END_REGISTER(CP_PERFCOUNTER_SELECT)
+
+START_REGISTER(CP_PERFCOUNTER_LO)
+    GENERATE_FIELD(PERFCOUNT_LO, int)
+END_REGISTER(CP_PERFCOUNTER_LO)
+
+START_REGISTER(CP_PERFCOUNTER_HI)
+    GENERATE_FIELD(PERFCOUNT_HI, int)
+END_REGISTER(CP_PERFCOUNTER_HI)
+
+START_REGISTER(CP_BIN_MASK_LO)
+    GENERATE_FIELD(BIN_MASK_LO, int)
+END_REGISTER(CP_BIN_MASK_LO)
+
+START_REGISTER(CP_BIN_MASK_HI)
+    GENERATE_FIELD(BIN_MASK_HI, int)
+END_REGISTER(CP_BIN_MASK_HI)
+
+START_REGISTER(CP_BIN_SELECT_LO)
+    GENERATE_FIELD(BIN_SELECT_LO, int)
+END_REGISTER(CP_BIN_SELECT_LO)
+
+START_REGISTER(CP_BIN_SELECT_HI)
+    GENERATE_FIELD(BIN_SELECT_HI, int)
+END_REGISTER(CP_BIN_SELECT_HI)
+
+START_REGISTER(CP_NV_FLAGS_0)
+    GENERATE_FIELD(DISCARD_0, int)
+    GENERATE_FIELD(END_RCVD_0, int)
+    GENERATE_FIELD(DISCARD_1, int)
+    GENERATE_FIELD(END_RCVD_1, int)
+    GENERATE_FIELD(DISCARD_2, int)
+    GENERATE_FIELD(END_RCVD_2, int)
+    GENERATE_FIELD(DISCARD_3, int)
+    GENERATE_FIELD(END_RCVD_3, int)
+    GENERATE_FIELD(DISCARD_4, int)
+    GENERATE_FIELD(END_RCVD_4, int)
+    GENERATE_FIELD(DISCARD_5, int)
+    GENERATE_FIELD(END_RCVD_5, int)
+    GENERATE_FIELD(DISCARD_6, int)
+    GENERATE_FIELD(END_RCVD_6, int)
+    GENERATE_FIELD(DISCARD_7, int)
+    GENERATE_FIELD(END_RCVD_7, int)
+    GENERATE_FIELD(DISCARD_8, int)
+    GENERATE_FIELD(END_RCVD_8, int)
+    GENERATE_FIELD(DISCARD_9, int)
+    GENERATE_FIELD(END_RCVD_9, int)
+    GENERATE_FIELD(DISCARD_10, int)
+    GENERATE_FIELD(END_RCVD_10, int)
+    GENERATE_FIELD(DISCARD_11, int)
+    GENERATE_FIELD(END_RCVD_11, int)
+    GENERATE_FIELD(DISCARD_12, int)
+    GENERATE_FIELD(END_RCVD_12, int)
+    GENERATE_FIELD(DISCARD_13, int)
+    GENERATE_FIELD(END_RCVD_13, int)
+    GENERATE_FIELD(DISCARD_14, int)
+    GENERATE_FIELD(END_RCVD_14, int)
+    GENERATE_FIELD(DISCARD_15, int)
+    GENERATE_FIELD(END_RCVD_15, int)
+END_REGISTER(CP_NV_FLAGS_0)
+
+START_REGISTER(CP_NV_FLAGS_1)
+    GENERATE_FIELD(DISCARD_16, int)
+    GENERATE_FIELD(END_RCVD_16, int)
+    GENERATE_FIELD(DISCARD_17, int)
+    GENERATE_FIELD(END_RCVD_17, int)
+    GENERATE_FIELD(DISCARD_18, int)
+    GENERATE_FIELD(END_RCVD_18, int)
+    GENERATE_FIELD(DISCARD_19, int)
+    GENERATE_FIELD(END_RCVD_19, int)
+    GENERATE_FIELD(DISCARD_20, int)
+    GENERATE_FIELD(END_RCVD_20, int)
+    GENERATE_FIELD(DISCARD_21, int)
+    GENERATE_FIELD(END_RCVD_21, int)
+    GENERATE_FIELD(DISCARD_22, int)
+    GENERATE_FIELD(END_RCVD_22, int)
+    GENERATE_FIELD(DISCARD_23, int)
+    GENERATE_FIELD(END_RCVD_23, int)
+    GENERATE_FIELD(DISCARD_24, int)
+    GENERATE_FIELD(END_RCVD_24, int)
+    GENERATE_FIELD(DISCARD_25, int)
+    GENERATE_FIELD(END_RCVD_25, int)
+    GENERATE_FIELD(DISCARD_26, int)
+    GENERATE_FIELD(END_RCVD_26, int)
+    GENERATE_FIELD(DISCARD_27, int)
+    GENERATE_FIELD(END_RCVD_27, int)
+    GENERATE_FIELD(DISCARD_28, int)
+    GENERATE_FIELD(END_RCVD_28, int)
+    GENERATE_FIELD(DISCARD_29, int)
+    GENERATE_FIELD(END_RCVD_29, int)
+    GENERATE_FIELD(DISCARD_30, int)
+    GENERATE_FIELD(END_RCVD_30, int)
+    GENERATE_FIELD(DISCARD_31, int)
+    GENERATE_FIELD(END_RCVD_31, int)
+END_REGISTER(CP_NV_FLAGS_1)
+
+START_REGISTER(CP_NV_FLAGS_2)
+    GENERATE_FIELD(DISCARD_32, int)
+    GENERATE_FIELD(END_RCVD_32, int)
+    GENERATE_FIELD(DISCARD_33, int)
+    GENERATE_FIELD(END_RCVD_33, int)
+    GENERATE_FIELD(DISCARD_34, int)
+    GENERATE_FIELD(END_RCVD_34, int)
+    GENERATE_FIELD(DISCARD_35, int)
+    GENERATE_FIELD(END_RCVD_35, int)
+    GENERATE_FIELD(DISCARD_36, int)
+    GENERATE_FIELD(END_RCVD_36, int)
+    GENERATE_FIELD(DISCARD_37, int)
+    GENERATE_FIELD(END_RCVD_37, int)
+    GENERATE_FIELD(DISCARD_38, int)
+    GENERATE_FIELD(END_RCVD_38, int)
+    GENERATE_FIELD(DISCARD_39, int)
+    GENERATE_FIELD(END_RCVD_39, int)
+    GENERATE_FIELD(DISCARD_40, int)
+    GENERATE_FIELD(END_RCVD_40, int)
+    GENERATE_FIELD(DISCARD_41, int)
+    GENERATE_FIELD(END_RCVD_41, int)
+    GENERATE_FIELD(DISCARD_42, int)
+    GENERATE_FIELD(END_RCVD_42, int)
+    GENERATE_FIELD(DISCARD_43, int)
+    GENERATE_FIELD(END_RCVD_43, int)
+    GENERATE_FIELD(DISCARD_44, int)
+    GENERATE_FIELD(END_RCVD_44, int)
+    GENERATE_FIELD(DISCARD_45, int)
+    GENERATE_FIELD(END_RCVD_45, int)
+    GENERATE_FIELD(DISCARD_46, int)
+    GENERATE_FIELD(END_RCVD_46, int)
+    GENERATE_FIELD(DISCARD_47, int)
+    GENERATE_FIELD(END_RCVD_47, int)
+END_REGISTER(CP_NV_FLAGS_2)
+
+START_REGISTER(CP_NV_FLAGS_3)
+    GENERATE_FIELD(DISCARD_48, int)
+    GENERATE_FIELD(END_RCVD_48, int)
+    GENERATE_FIELD(DISCARD_49, int)
+    GENERATE_FIELD(END_RCVD_49, int)
+    GENERATE_FIELD(DISCARD_50, int)
+    GENERATE_FIELD(END_RCVD_50, int)
+    GENERATE_FIELD(DISCARD_51, int)
+    GENERATE_FIELD(END_RCVD_51, int)
+    GENERATE_FIELD(DISCARD_52, int)
+    GENERATE_FIELD(END_RCVD_52, int)
+    GENERATE_FIELD(DISCARD_53, int)
+    GENERATE_FIELD(END_RCVD_53, int)
+    GENERATE_FIELD(DISCARD_54, int)
+    GENERATE_FIELD(END_RCVD_54, int)
+    GENERATE_FIELD(DISCARD_55, int)
+    GENERATE_FIELD(END_RCVD_55, int)
+    GENERATE_FIELD(DISCARD_56, int)
+    GENERATE_FIELD(END_RCVD_56, int)
+    GENERATE_FIELD(DISCARD_57, int)
+    GENERATE_FIELD(END_RCVD_57, int)
+    GENERATE_FIELD(DISCARD_58, int)
+    GENERATE_FIELD(END_RCVD_58, int)
+    GENERATE_FIELD(DISCARD_59, int)
+    GENERATE_FIELD(END_RCVD_59, int)
+    GENERATE_FIELD(DISCARD_60, int)
+    GENERATE_FIELD(END_RCVD_60, int)
+    GENERATE_FIELD(DISCARD_61, int)
+    GENERATE_FIELD(END_RCVD_61, int)
+    GENERATE_FIELD(DISCARD_62, int)
+    GENERATE_FIELD(END_RCVD_62, int)
+    GENERATE_FIELD(DISCARD_63, int)
+    GENERATE_FIELD(END_RCVD_63, int)
+END_REGISTER(CP_NV_FLAGS_3)
+
+START_REGISTER(CP_STATE_DEBUG_INDEX)
+    GENERATE_FIELD(STATE_DEBUG_INDEX, int)
+END_REGISTER(CP_STATE_DEBUG_INDEX)
+
+START_REGISTER(CP_STATE_DEBUG_DATA)
+    GENERATE_FIELD(STATE_DEBUG_DATA, int)
+END_REGISTER(CP_STATE_DEBUG_DATA)
+
+START_REGISTER(CP_PROG_COUNTER)
+    GENERATE_FIELD(COUNTER, int)
+END_REGISTER(CP_PROG_COUNTER)
+
+START_REGISTER(CP_STAT)
+    GENERATE_FIELD(MIU_WR_BUSY, int)
+    GENERATE_FIELD(MIU_RD_REQ_BUSY, int)
+    GENERATE_FIELD(MIU_RD_RETURN_BUSY, int)
+    GENERATE_FIELD(RBIU_BUSY, int)
+    GENERATE_FIELD(RCIU_BUSY, int)
+    GENERATE_FIELD(CSF_RING_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(CSF_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(CSF_ST_BUSY, int)
+    GENERATE_FIELD(CSF_BUSY, int)
+    GENERATE_FIELD(RING_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int)
+    GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int)
+    GENERATE_FIELD(ST_QUEUE_BUSY, int)
+    GENERATE_FIELD(PFP_BUSY, int)
+    GENERATE_FIELD(MEQ_RING_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int)
+    GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int)
+    GENERATE_FIELD(MIU_WC_STALL, int)
+    GENERATE_FIELD(CP_NRT_BUSY, int)
+    GENERATE_FIELD(_3D_BUSY, int)
+    GENERATE_FIELD(ME_BUSY, int)
+    GENERATE_FIELD(ME_WC_BUSY, int)
+    GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int)
+    GENERATE_FIELD(CP_BUSY, int)
+END_REGISTER(CP_STAT)
+
+START_REGISTER(BIOS_0_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_0_SCRATCH)
+
+START_REGISTER(BIOS_1_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_1_SCRATCH)
+
+START_REGISTER(BIOS_2_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_2_SCRATCH)
+
+START_REGISTER(BIOS_3_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_3_SCRATCH)
+
+START_REGISTER(BIOS_4_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_4_SCRATCH)
+
+START_REGISTER(BIOS_5_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_5_SCRATCH)
+
+START_REGISTER(BIOS_6_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_6_SCRATCH)
+
+START_REGISTER(BIOS_7_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_7_SCRATCH)
+
+START_REGISTER(BIOS_8_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_8_SCRATCH)
+
+START_REGISTER(BIOS_9_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_9_SCRATCH)
+
+START_REGISTER(BIOS_10_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_10_SCRATCH)
+
+START_REGISTER(BIOS_11_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_11_SCRATCH)
+
+START_REGISTER(BIOS_12_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_12_SCRATCH)
+
+START_REGISTER(BIOS_13_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_13_SCRATCH)
+
+START_REGISTER(BIOS_14_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_14_SCRATCH)
+
+START_REGISTER(BIOS_15_SCRATCH)
+    GENERATE_FIELD(BIOS_SCRATCH, hex)
+END_REGISTER(BIOS_15_SCRATCH)
+
+START_REGISTER(COHER_SIZE_PM4)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_PM4)
+
+START_REGISTER(COHER_BASE_PM4)
+    GENERATE_FIELD(BASE, int)
+END_REGISTER(COHER_BASE_PM4)
+
+START_REGISTER(COHER_STATUS_PM4)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_PM4)
+
+START_REGISTER(COHER_SIZE_HOST)
+    GENERATE_FIELD(SIZE, int)
+END_REGISTER(COHER_SIZE_HOST)
+
+START_REGISTER(COHER_BASE_HOST)
+    GENERATE_FIELD(BASE, hex)
+END_REGISTER(COHER_BASE_HOST)
+
+START_REGISTER(COHER_STATUS_HOST)
+    GENERATE_FIELD(MATCHING_CONTEXTS, int)
+    GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int)
+    GENERATE_FIELD(DEST_BASE_0_ENA, int)
+    GENERATE_FIELD(DEST_BASE_1_ENA, int)
+    GENERATE_FIELD(DEST_BASE_2_ENA, int)
+    GENERATE_FIELD(DEST_BASE_3_ENA, int)
+    GENERATE_FIELD(DEST_BASE_4_ENA, int)
+    GENERATE_FIELD(DEST_BASE_5_ENA, int)
+    GENERATE_FIELD(DEST_BASE_6_ENA, int)
+    GENERATE_FIELD(DEST_BASE_7_ENA, int)
+    GENERATE_FIELD(RB_COLOR_INFO_ENA, int)
+    GENERATE_FIELD(TC_ACTION_ENA, int)
+    GENERATE_FIELD(STATUS, int)
+END_REGISTER(COHER_STATUS_HOST)
+
+START_REGISTER(COHER_DEST_BASE_0)
+    GENERATE_FIELD(DEST_BASE_0, hex)
+END_REGISTER(COHER_DEST_BASE_0)
+
+START_REGISTER(COHER_DEST_BASE_1)
+    GENERATE_FIELD(DEST_BASE_1, hex)
+END_REGISTER(COHER_DEST_BASE_1)
+
+START_REGISTER(COHER_DEST_BASE_2)
+    GENERATE_FIELD(DEST_BASE_2, hex)
+END_REGISTER(COHER_DEST_BASE_2)
+
+START_REGISTER(COHER_DEST_BASE_3)
+    GENERATE_FIELD(DEST_BASE_3, hex)
+END_REGISTER(COHER_DEST_BASE_3)
+
+START_REGISTER(COHER_DEST_BASE_4)
+    GENERATE_FIELD(DEST_BASE_4, hex)
+END_REGISTER(COHER_DEST_BASE_4)
+
+START_REGISTER(COHER_DEST_BASE_5)
+    GENERATE_FIELD(DEST_BASE_5, hex)
+END_REGISTER(COHER_DEST_BASE_5)
+
+START_REGISTER(COHER_DEST_BASE_6)
+    GENERATE_FIELD(DEST_BASE_6, hex)
+END_REGISTER(COHER_DEST_BASE_6)
+
+START_REGISTER(COHER_DEST_BASE_7)
+    GENERATE_FIELD(DEST_BASE_7, hex)
+END_REGISTER(COHER_DEST_BASE_7)
+
+START_REGISTER(RB_SURFACE_INFO)
+    GENERATE_FIELD(SURFACE_PITCH, uint)
+    GENERATE_FIELD(MSAA_SAMPLES, MSAASamples)
+END_REGISTER(RB_SURFACE_INFO)
+
+START_REGISTER(RB_COLOR_INFO)
+    GENERATE_FIELD(COLOR_FORMAT, ColorformatX)
+    GENERATE_FIELD(COLOR_ROUND_MODE, uint)
+    GENERATE_FIELD(COLOR_LINEAR, bool)
+    GENERATE_FIELD(COLOR_ENDIAN, uint)
+    GENERATE_FIELD(COLOR_SWAP, uint)
+    GENERATE_FIELD(COLOR_BASE, uint)
+END_REGISTER(RB_COLOR_INFO)
+
+START_REGISTER(RB_DEPTH_INFO)
+    GENERATE_FIELD(DEPTH_FORMAT, DepthformatX)
+    GENERATE_FIELD(DEPTH_BASE, uint)
+END_REGISTER(RB_DEPTH_INFO)
+
+START_REGISTER(RB_STENCILREFMASK)
+    GENERATE_FIELD(STENCILREF, hex)
+    GENERATE_FIELD(STENCILMASK, hex)
+    GENERATE_FIELD(STENCILWRITEMASK, hex)
+    GENERATE_FIELD(RESERVED0, bool)
+    GENERATE_FIELD(RESERVED1, bool)
+END_REGISTER(RB_STENCILREFMASK)
+
+START_REGISTER(RB_ALPHA_REF)
+    GENERATE_FIELD(ALPHA_REF, float)
+END_REGISTER(RB_ALPHA_REF)
+
+START_REGISTER(RB_COLOR_MASK)
+    GENERATE_FIELD(WRITE_RED, bool)
+    GENERATE_FIELD(WRITE_GREEN, bool)
+    GENERATE_FIELD(WRITE_BLUE, bool)
+    GENERATE_FIELD(WRITE_ALPHA, bool)
+    GENERATE_FIELD(RESERVED2, bool)
+    GENERATE_FIELD(RESERVED3, bool)
+END_REGISTER(RB_COLOR_MASK)
+
+START_REGISTER(RB_BLEND_RED)
+    GENERATE_FIELD(BLEND_RED, uint)
+END_REGISTER(RB_BLEND_RED)
+
+START_REGISTER(RB_BLEND_GREEN)
+    GENERATE_FIELD(BLEND_GREEN, uint)
+END_REGISTER(RB_BLEND_GREEN)
+
+START_REGISTER(RB_BLEND_BLUE)
+    GENERATE_FIELD(BLEND_BLUE, uint)
+END_REGISTER(RB_BLEND_BLUE)
+
+START_REGISTER(RB_BLEND_ALPHA)
+    GENERATE_FIELD(BLEND_ALPHA, uint)
+END_REGISTER(RB_BLEND_ALPHA)
+
+START_REGISTER(RB_FOG_COLOR)
+    GENERATE_FIELD(FOG_RED, uint)
+    GENERATE_FIELD(FOG_GREEN, uint)
+    GENERATE_FIELD(FOG_BLUE, uint)
+END_REGISTER(RB_FOG_COLOR)
+
+START_REGISTER(RB_STENCILREFMASK_BF)
+    GENERATE_FIELD(STENCILREF_BF, hex)
+    GENERATE_FIELD(STENCILMASK_BF, hex)
+    GENERATE_FIELD(STENCILWRITEMASK_BF, hex)
+    GENERATE_FIELD(RESERVED4, bool)
+    GENERATE_FIELD(RESERVED5, bool)
+END_REGISTER(RB_STENCILREFMASK_BF)
+
+START_REGISTER(RB_DEPTHCONTROL)
+    GENERATE_FIELD(STENCIL_ENABLE, bool)
+    GENERATE_FIELD(Z_ENABLE, bool)
+    GENERATE_FIELD(Z_WRITE_ENABLE, bool)
+    GENERATE_FIELD(EARLY_Z_ENABLE, bool)
+    GENERATE_FIELD(ZFUNC, CompareFrag)
+    GENERATE_FIELD(BACKFACE_ENABLE, bool)
+    GENERATE_FIELD(STENCILFUNC, CompareRef)
+    GENERATE_FIELD(STENCILFAIL, StencilOp)
+    GENERATE_FIELD(STENCILZPASS, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL, StencilOp)
+    GENERATE_FIELD(STENCILFUNC_BF, CompareRef)
+    GENERATE_FIELD(STENCILFAIL_BF, StencilOp)
+    GENERATE_FIELD(STENCILZPASS_BF, StencilOp)
+    GENERATE_FIELD(STENCILZFAIL_BF, StencilOp)
+END_REGISTER(RB_DEPTHCONTROL)
+
+START_REGISTER(RB_BLENDCONTROL)
+    GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX)
+    GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX)
+    GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX)
+    GENERATE_FIELD(BLEND_FORCE_ENABLE, bool)
+    GENERATE_FIELD(BLEND_FORCE, bool)
+END_REGISTER(RB_BLENDCONTROL)
+
+START_REGISTER(RB_COLORCONTROL)
+    GENERATE_FIELD(ALPHA_FUNC, CompareRef)
+    GENERATE_FIELD(ALPHA_TEST_ENABLE, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool)
+    GENERATE_FIELD(BLEND_DISABLE, bool)
+    GENERATE_FIELD(FOG_ENABLE, bool)
+    GENERATE_FIELD(VS_EXPORTS_FOG, bool)
+    GENERATE_FIELD(ROP_CODE, uint)
+    GENERATE_FIELD(DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(PIXEL_FOG, bool)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex)
+    GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex)
+END_REGISTER(RB_COLORCONTROL)
+
+START_REGISTER(RB_MODECONTROL)
+    GENERATE_FIELD(EDRAM_MODE, EdramMode)
+END_REGISTER(RB_MODECONTROL)
+
+START_REGISTER(RB_COLOR_DEST_MASK)
+    GENERATE_FIELD(COLOR_DEST_MASK, uint)
+END_REGISTER(RB_COLOR_DEST_MASK)
+
+START_REGISTER(RB_COPY_CONTROL)
+    GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect)
+    GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool)
+    GENERATE_FIELD(CLEAR_MASK, uint)
+END_REGISTER(RB_COPY_CONTROL)
+
+START_REGISTER(RB_COPY_DEST_BASE)
+    GENERATE_FIELD(COPY_DEST_BASE, uint)
+END_REGISTER(RB_COPY_DEST_BASE)
+
+START_REGISTER(RB_COPY_DEST_PITCH)
+    GENERATE_FIELD(COPY_DEST_PITCH, uint)
+END_REGISTER(RB_COPY_DEST_PITCH)
+
+START_REGISTER(RB_COPY_DEST_INFO)
+    GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian)
+    GENERATE_FIELD(COPY_DEST_LINEAR, uint)
+    GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX)
+    GENERATE_FIELD(COPY_DEST_SWAP, uint)
+    GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX)
+    GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX)
+    GENERATE_FIELD(COPY_MASK_WRITE_RED, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex)
+    GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex)
+END_REGISTER(RB_COPY_DEST_INFO)
+
+START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+    GENERATE_FIELD(OFFSET_X, uint)
+    GENERATE_FIELD(OFFSET_Y, uint)
+END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET)
+
+START_REGISTER(RB_DEPTH_CLEAR)
+    GENERATE_FIELD(DEPTH_CLEAR, uint)
+END_REGISTER(RB_DEPTH_CLEAR)
+
+START_REGISTER(RB_SAMPLE_COUNT_CTL)
+    GENERATE_FIELD(RESET_SAMPLE_COUNT, bool)
+    GENERATE_FIELD(COPY_SAMPLE_COUNT, bool)
+END_REGISTER(RB_SAMPLE_COUNT_CTL)
+
+START_REGISTER(RB_SAMPLE_COUNT_ADDR)
+    GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint)
+END_REGISTER(RB_SAMPLE_COUNT_ADDR)
+
+START_REGISTER(RB_BC_CONTROL)
+    GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint)
+    GENERATE_FIELD(DISABLE_EDRAM_CAM, bool)
+    GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool)
+    GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool)
+    GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool)
+    GENERATE_FIELD(AZ_THROTTLE_COUNT, uint)
+    GENERATE_FIELD(ENABLE_CRC_UPDATE, bool)
+    GENERATE_FIELD(CRC_MODE, bool)
+    GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool)
+    GENERATE_FIELD(DISABLE_ACCUM, bool)
+    GENERATE_FIELD(ACCUM_ALLOC_MASK, uint)
+    GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool)
+    GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int)
+    GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool)
+    GENERATE_FIELD(CRC_SYSTEM, bool)
+    GENERATE_FIELD(RESERVED6, bool)
+END_REGISTER(RB_BC_CONTROL)
+
+START_REGISTER(RB_EDRAM_INFO)
+    GENERATE_FIELD(EDRAM_SIZE, EdramSizeX)
+    GENERATE_FIELD(EDRAM_MAPPING_MODE, uint)
+    GENERATE_FIELD(EDRAM_RANGE, hex)
+END_REGISTER(RB_EDRAM_INFO)
+
+START_REGISTER(RB_CRC_RD_PORT)
+    GENERATE_FIELD(CRC_DATA, hex)
+END_REGISTER(RB_CRC_RD_PORT)
+
+START_REGISTER(RB_CRC_CONTROL)
+    GENERATE_FIELD(CRC_RD_ADVANCE, bool)
+END_REGISTER(RB_CRC_CONTROL)
+
+START_REGISTER(RB_CRC_MASK)
+    GENERATE_FIELD(CRC_MASK, hex)
+END_REGISTER(RB_CRC_MASK)
+
+START_REGISTER(RB_PERFCOUNTER0_SELECT)
+    GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT)
+END_REGISTER(RB_PERFCOUNTER0_SELECT)
+
+START_REGISTER(RB_PERFCOUNTER0_LOW)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_LOW)
+
+START_REGISTER(RB_PERFCOUNTER0_HI)
+    GENERATE_FIELD(PERF_COUNT, int)
+END_REGISTER(RB_PERFCOUNTER0_HI)
+
+START_REGISTER(RB_TOTAL_SAMPLES)
+    GENERATE_FIELD(TOTAL_SAMPLES, int)
+END_REGISTER(RB_TOTAL_SAMPLES)
+
+START_REGISTER(RB_ZPASS_SAMPLES)
+    GENERATE_FIELD(ZPASS_SAMPLES, int)
+END_REGISTER(RB_ZPASS_SAMPLES)
+
+START_REGISTER(RB_ZFAIL_SAMPLES)
+    GENERATE_FIELD(ZFAIL_SAMPLES, int)
+END_REGISTER(RB_ZFAIL_SAMPLES)
+
+START_REGISTER(RB_SFAIL_SAMPLES)
+    GENERATE_FIELD(SFAIL_SAMPLES, int)
+END_REGISTER(RB_SFAIL_SAMPLES)
+
+START_REGISTER(RB_DEBUG_0)
+    GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z1_FULL, bool)
+    GENERATE_FIELD(RDREQ_Z0_FULL, bool)
+    GENERATE_FIELD(RDREQ_C1_FULL, bool)
+    GENERATE_FIELD(RDREQ_C0_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z1_FULL, bool)
+    GENERATE_FIELD(WRREQ_Z0_FULL, bool)
+    GENERATE_FIELD(WRREQ_C1_FULL, bool)
+    GENERATE_FIELD(WRREQ_C0_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool)
+    GENERATE_FIELD(C_SX_LAT_FULL, bool)
+    GENERATE_FIELD(C_SX_CMD_FULL, bool)
+    GENERATE_FIELD(C_EZ_TILE_FULL, bool)
+    GENERATE_FIELD(C_REQ_FULL, bool)
+    GENERATE_FIELD(C_MASK_FULL, bool)
+    GENERATE_FIELD(EZ_INFSAMP_FULL, bool)
+END_REGISTER(RB_DEBUG_0)
+
+START_REGISTER(RB_DEBUG_1)
+    GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C1_EMPTY, bool)
+    GENERATE_FIELD(RDREQ_C0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z1_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_Z0_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool)
+    GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool)
+    GENERATE_FIELD(C_SX_LAT_EMPTY, bool)
+    GENERATE_FIELD(C_SX_CMD_EMPTY, bool)
+    GENERATE_FIELD(C_EZ_TILE_EMPTY, bool)
+    GENERATE_FIELD(C_REQ_EMPTY, bool)
+    GENERATE_FIELD(C_MASK_EMPTY, bool)
+    GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool)
+END_REGISTER(RB_DEBUG_1)
+
+START_REGISTER(RB_DEBUG_2)
+    GENERATE_FIELD(TILE_FIFO_COUNT, bool)
+    GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool)
+    GENERATE_FIELD(MEM_EXPORT_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool)
+    GENERATE_FIELD(CURRENT_TILE_EVENT, bool)
+    GENERATE_FIELD(EZ_INFTILE_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool)
+    GENERATE_FIELD(Z0_MASK_FULL, bool)
+    GENERATE_FIELD(Z1_MASK_FULL, bool)
+    GENERATE_FIELD(Z0_REQ_FULL, bool)
+    GENERATE_FIELD(Z1_REQ_FULL, bool)
+    GENERATE_FIELD(Z_SAMP_FULL, bool)
+    GENERATE_FIELD(Z_TILE_FULL, bool)
+    GENERATE_FIELD(EZ_INFTILE_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool)
+    GENERATE_FIELD(Z0_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z1_MASK_EMPTY, bool)
+    GENERATE_FIELD(Z0_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z1_REQ_EMPTY, bool)
+    GENERATE_FIELD(Z_SAMP_EMPTY, bool)
+    GENERATE_FIELD(Z_TILE_EMPTY, bool)
+END_REGISTER(RB_DEBUG_2)
+
+START_REGISTER(RB_DEBUG_3)
+    GENERATE_FIELD(ACCUM_VALID, bool)
+    GENERATE_FIELD(ACCUM_FLUSHING, bool)
+    GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool)
+    GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool)
+    GENERATE_FIELD(SHD_FULL, bool)
+    GENERATE_FIELD(SHD_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool)
+    GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool)
+    GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool)
+    GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool)
+    GENERATE_FIELD(ZEXP_LOWER_FULL, bool)
+    GENERATE_FIELD(ZEXP_UPPER_FULL, bool)
+END_REGISTER(RB_DEBUG_3)
+
+START_REGISTER(RB_DEBUG_4)
+    GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool)
+    GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool)
+    GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool)
+    GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool)
+    GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool)
+    GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool)
+END_REGISTER(RB_DEBUG_4)
+
+START_REGISTER(RB_FLAG_CONTROL)
+    GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool)
+END_REGISTER(RB_FLAG_CONTROL)
+
+START_REGISTER(RB_BC_SPARES)
+    GENERATE_FIELD(RESERVED, bool)
+END_REGISTER(RB_BC_SPARES)
+
+START_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap)
+    GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling)
+    GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray)
+    GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX)
+END_REGISTER(BC_DUMMY_CRAYRB_ENUMS)
+
+START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+    GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX)
+END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS)
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h
new file mode 100644
index 00000000000..0e32e421d0a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h
@@ -0,0 +1,95 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _R400IPT_H_
+#define _R400IPT_H_
+
+// Hand-generated list from Yamato_PM4_Spec.doc
+
+#define PM4_PACKET0_NOP     0x00000000          // Empty type-0 packet header
+#define PM4_PACKET1_NOP     0x40000000          // Empty type-1 packet header
+#define PM4_PACKET2_NOP     0x80000000          // Empty type-2 packet header (reserved)
+
+#define PM4_COUNT_SHIFT     16  
+#define PM4_COUNT_MASK      
+#define PM4_PACKET_COUNT(__x)   ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000)
+// Type 3 packet headers
+
+#define PM4_PACKET3_NOP                         0xC0001000  // Do nothing.
+#define PM4_PACKET3_IB_PREFETCH_END             0xC0001700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_SUBBLK_PREFETCH             0xC0001F00  // Internal Packet Used Only by CP
+
+#define PM4_PACKET3_INSTR_PREFETCH              0xC0002000  // Internal Packet Used Only by CP
+#define PM4_PACKET3_REG_RMW                     0xC0002100  // Register Read-Modify-Write                               New for R400
+#define PM4_PACKET3_DRAW_INDX                   0xC0002200  // Initiate fetch of index buffer                           New for R400
+#define PM4_PACKET3_VIZ_QUERY                   0xC0002300  // Begin/End initiator for Viz Query extent processing      New for R400
+#define PM4_PACKET3_SET_STATE                   0xC0002500  // Fetch State Sub-Blocks and Initiate Shader Code DMAs     New for R400
+#define PM4_PACKET3_WAIT_FOR_IDLE               0xC0002600  // Wait for the engine to be idle. 
+#define PM4_PACKET3_IM_LOAD                     0xC0002700  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_IM_LOAD_IMMEDIATE           0xC0002B00  // Load Sequencer Instruction Memory for a Specific Shader  New for R400
+#define PM4_PACKET3_SET_CONSTANT                0xC0002D00  // Load Constant Into Chip & Shadow to Memory               New for R400
+#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT       0xC0002E00  // Load All Constants from a Location in Memory             New for R400
+#define PM4_PACKET3_LOAD_ALU_CONSTANT           0xC0002F00  // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants
+
+#define PM4_PACKET3_DRAW_INDX_BIN               0xC0003400  // Initiate fetch of index buffer and BIN info used for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2_BIN          0xC0003500  // Draw using supplied indices and initiate fetch of BIN info for visibility test
+#define PM4_PACKET3_3D_DRAW_INDX_2              0xC0003600  // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt
+#define PM4_PACKET3_INDIRECT_BUFFER_PFD         0xC0003700
+#define PM4_PACKET3_INVALIDATE_STATE            0xC0003B00  // Selective Invalidation of State Pointers                 New for R400
+#define PM4_PACKET3_WAIT_REG_MEM                0xC0003C00  // Wait Until a Register or Memory Location is a Specific Value.   New for R400
+#define PM4_PACKET3_MEM_WRITE                   0xC0003D00  // Write DWORD to Memory For Synchronization                New for R400
+#define PM4_PACKET3_REG_TO_MEM                  0xC0003E00  // Reads Register in Chip and Writes to Memory              New for R400
+#define PM4_PACKET3_INDIRECT_BUFFER             0xC0003F00  // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer.  Supported
+
+#define PM4_PACKET3_CP_INTERRUPT                0xC0004000  // Generate Interrupt from the Command Stream               New for R400
+#define PM4_PACKET3_COND_EXEC                   0xC0004400  // Conditional execution of a sequence of packets
+#define PM4_PACKET3_COND_WRITE                  0xC0004500  // Conditional Write to Memory                              New for R400
+#define PM4_PACKET3_EVENT_WRITE                 0xC0004600  // Generate An Event that Creates a Write to Memory when Completed  New for R400
+#define PM4_PACKET3_INSTR_MATCH                 0xC0004700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_ME_INIT                     0xC0004800  // Initialize CP's Micro Engine                             New for R400
+#define PM4_PACKET3_CONST_PREFETCH              0xC0004900  // Internal packet used only by CP
+#define PM4_PACKET3_MEM_WRITE_CNTR              0xC0004F00
+
+#define PM4_PACKET3_SET_BIN_MASK                0xC0005000  // Sets the 64-bit BIN_MASK register in the PFP
+#define PM4_PACKET3_SET_BIN_SELECT              0xC0005100  // Sets the 64-bit BIN_SELECT register in the PFP
+#define PM4_PACKET3_WAIT_REG_EQ                 0xC0005200  // Wait until a register location is equal to a specific value
+#define PM4_PACKET3_WAIT_REG_GTE                0xC0005300  // Wait until a register location is greater than or equal to a specific value
+#define PM4_PACKET3_INCR_UPDT_STATE             0xC0005500  // Internal Packet Used Only by CP  
+#define PM4_PACKET3_INCR_UPDT_CONST             0xC0005600  // Internal Packet Used Only by CP
+#define PM4_PACKET3_INCR_UPDT_INSTR             0xC0005700  // Internal Packet Used Only by CP
+#define PM4_PACKET3_EVENT_WRITE_SHD             0xC0005800  // Generate a VS|PS_Done Event.
+#define PM4_PACKET3_EVENT_WRITE_CFL             0xC0005900  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_EVENT_WRITE_ZPD             0xC0005B00  // Generate a Cach Flush Done Event
+#define PM4_PACKET3_WAIT_UNTIL_READ             0xC0005C00  // Wait Until a Read completes.
+#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE        0xC0005D00  // Wait Until all Base/Size writes from an IB_PFD packet have completed.
+#define PM4_PACKET3_CONTEXT_UPDATE              0xC0005E00  // Updates the current context if needed.
+
+    /****** New Opcodes For R400 (all decode values are TBD) ******/
+
+
+#endif //  _R400IPT_H_
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h
new file mode 100644
index 00000000000..52ced9af774
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h
@@ -0,0 +1,5908 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_MASK_HEADER)
+#define _yamato_MASK_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK            0xffffffffL
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK              0xffffffffL
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK            0xffffffffL
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK             0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA                  0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK            0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA                 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK             0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA                  0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK            0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA                 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK             0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA                  0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK            0x00000020L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA                 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                    0x00000100L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT                         0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                     0x00000200L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT                          0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                    0x00000400L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT                         0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK               0x00000800L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF                    0x00000800L
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                 0x00010000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE                      0x00010000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK       0x00040000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA            0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK            0x00080000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF                 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK          0x00100000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT               0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                  0x00200000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR                       0x00200000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK                0x00400000L
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN                     0x00400000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK                 0x00800000L
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN                      0x00800000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK                 0x01000000L
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN                      0x01000000L
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK         0xffffffffL
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK           0x00000001L
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA                0x00000001L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_CL_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3_MASK                     0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE3                          0x10000000L
+#define PA_SC_ENHANCE__ECO_SPARE2_MASK                     0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE2                          0x20000000L
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK                     0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE1                          0x40000000L
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK                     0x80000000L
+#define PA_SC_ENHANCE__ECO_SPARE0                          0x80000000L
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK                    0x00000001L
+#define PA_SU_VTX_CNTL__PIX_CENTER                         0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK                    0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK                    0x00000038L
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT_MASK                      0x0000ffffL
+#define PA_SU_POINT_SIZE__WIDTH_MASK                       0xffff0000L
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                  0x0000ffffL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                  0xffff0000L
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH_MASK                        0x0000ffffL
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR_MASK                    0xffffffe0L
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT                     0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                 0x00000002L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK                      0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK                      0x00000004L
+#define PA_SU_SC_MODE_CNTL__FACE                           0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK      0x000000e0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK       0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK  0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE       0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK   0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE        0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK   0x00002000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE        0x00002000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK               0x00008000L
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE                    0x00008000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK  0x00010000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE       0x00010000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK       0x00040000L
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE            0x00040000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK        0x00080000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST             0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK            0x00100000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS                 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK         0x00200000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA              0x00200000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK         0x00800000L
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE              0x00800000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK      0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI           0x02000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L
+#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS_MASK          0x10000000L
+#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS               0x10000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK        0x20000000L
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS             0x20000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK          0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE               0x40000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK         0x80000000L
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE              0x80000000L
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK          0xffffffffL
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK        0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK           0xffffffffL
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK         0xffffffffL
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK          0x00007fffL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK          0x7fff0000L
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK             0x00000007L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK              0x0001e000L
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK_MASK                        0x0000ffffL
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK              0x0000ffffL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK              0x00ff0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK         0x10000000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER              0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK           0x60000000L
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL_MASK                    0x000000ffL
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK                0x00000100L
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL                     0x00000100L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK            0x00000200L
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH                 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                   0x00000400L
+#define PA_SC_LINE_CNTL__LAST_PIXEL                        0x00000400L
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                 0x3fff0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE     0x80000000L
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                 0x00003fffL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                 0x3fff0000L
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                 0x7fff0000L
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                 0x00007fffL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                 0x7fff0000L
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK                0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA                     0x00000001L
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK                 0x0000003eL
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK        0x00000080L
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z             0x00000080L
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK           0xffffffffL
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK         0x0000000fL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK       0x0000ff00L
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK           0x000000ffL
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK            0xffffffffL
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK             0x0000ffffL
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK                    0x80000000L
+#define PA_CL_CNTL_STATUS__CL_BUSY                         0x80000000L
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK                    0x80000000L
+#define PA_SU_CNTL_STATUS__SU_BUSY                         0x80000000L
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY_MASK                    0x80000000L
+#define PA_SC_CNTL_STATUS__SC_BUSY                         0x80000000L
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK    0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write         0x00000001L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK     0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full          0x00000002L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK    0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write         0x00000004L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK     0x00000008L
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full          0x00000008L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty   0x00000010L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full    0x00000020L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty      0x00000040L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK  0x00000080L
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full       0x00000080L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK  0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty       0x00000100L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK   0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full        0x00000200L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK  0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty       0x00000400L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK   0x00000800L
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full        0x00000800L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty      0x00001000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK       0x00002000L
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full            0x00002000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty  0x00004000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full   0x00008000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty  0x00010000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full   0x00020000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty    0x00040000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full     0x00080000L
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK              0xfff00000L
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet   0x00000001L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim    0x00000020L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive  0x00000040L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK      0x00380000L
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK              0xff000000L
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK             0x001fffffL
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK             0x7f000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK             0x000fff00L
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK             0xfc000000L
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK             0x00000007L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK             0x00000070L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event  0x00000080L
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK             0xffffff00L
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK             0x00000006L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK             0x00c00000L
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK             0xf0000000L
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK     0x00000001L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event          0x00000001L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK             0x000000c0L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK             0x00003000L
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK             0x000c0000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK          0x00100000L
+#define CLIPPER_DEBUG_REG09__prim_back_valid               0x00100000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait      0x08000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK     0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty          0x10000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK      0x20000000L
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full           0x20000000L
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK             0x00000030L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK             0x00000c00L
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK             0x00030000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK             0x00180000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet  0x00200000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK  0xfc000000L
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK              0xfffffff0L
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK             0x0000001cL
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK   0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty        0x00000020L
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK             0x00007800L
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK   0x00200000L
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid        0x00200000L
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK             0xffc00000L
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK        0x0000000fL
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK       0x000007f0L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK             0x00003800L
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK      0x0003c000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1  0x00040000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0  0x00080000L
+#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK        0x07f00000L
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK             0xf8000000L
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK             0x0000000fL
+#define SXIFCCG_DEBUG_REG0__position_address_MASK          0x00000070L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK              0x00000380L
+#define SXIFCCG_DEBUG_REG0__point_address_MASK             0x00001c00L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK              0x0000e000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx   0x00010000L
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK              0x00060000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK    0x00780000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK         0x3f800000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK     0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc          0x40000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK     0x80000000L
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel          0x80000000L
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK              0x00000003L
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK            0x0000000cL
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK       0x00000070L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK              0x00000780L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK        0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance             0x00000800L
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK           0x00007000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector  0x00008000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK              0x000f0000L
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK                   0x00100000L
+#define SXIFCCG_DEBUG_REG1__aux_sel                        0x00100000L
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK              0x00600000L
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK              0x01800000L
+#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK          0xfe000000L
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent_MASK                   0x00000001L
+#define SXIFCCG_DEBUG_REG2__sx_sent                        0x00000001L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK              0x00000002L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3                   0x00000002L
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK                    0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_aux                         0x00000004L
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK           0x000001f8L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK          0x0000fe00L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK              0x00010000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2                   0x00010000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx    0x00020000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK              0x000c0000L
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK              0x03c00000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK   0x04000000L
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded        0x04000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK     0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty          0x08000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK      0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full           0x10000000L
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK  0xe0000000L
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK              0x00000010L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3                   0x00000010L
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK       0x000000e0L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK              0x00000f00L
+#define SXIFCCG_DEBUG_REG3__current_state_MASK             0x00003000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK         0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty              0x00004000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK          0x00008000L
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full               0x00008000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK              0x00030000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK    0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty         0x00040000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK     0x00080000L
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full          0x00080000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK   0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty        0x00100000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK    0x00200000L
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full         0x00200000L
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK              0xffc00000L
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK               0x0000001fL
+#define SETUP_DEBUG_REG0__pmode_state_MASK                 0x000007e0L
+#define SETUP_DEBUG_REG0__ge_stallb_MASK                   0x00000800L
+#define SETUP_DEBUG_REG0__ge_stallb                        0x00000800L
+#define SETUP_DEBUG_REG0__geom_enable_MASK                 0x00001000L
+#define SETUP_DEBUG_REG0__geom_enable                      0x00001000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK           0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr                0x00002000L
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK                 0x00004000L
+#define SETUP_DEBUG_REG0__su_clip_rtr                      0x00004000L
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK                  0x00008000L
+#define SETUP_DEBUG_REG0__pfifo_busy                       0x00008000L
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK                0x00010000L
+#define SETUP_DEBUG_REG0__su_cntl_busy                     0x00010000L
+#define SETUP_DEBUG_REG0__geom_busy_MASK                   0x00020000L
+#define SETUP_DEBUG_REG0__geom_busy                        0x00020000L
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK          0x00003fffL
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK          0x0fffc000L
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK             0x00000800L
+#define SETUP_DEBUG_REG4__null_prim_gated                  0x00000800L
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK            0x00001000L
+#define SETUP_DEBUG_REG4__backfacing_gated                 0x00001000L
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK               0x0000e000L
+#define SETUP_DEBUG_REG4__clipped_gated_MASK               0x00010000L
+#define SETUP_DEBUG_REG4__clipped_gated                    0x00010000L
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK          0x000e0000L
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK                0x00100000L
+#define SETUP_DEBUG_REG4__xmajor_gated                     0x00100000L
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK          0x00600000L
+#define SETUP_DEBUG_REG4__type_gated_MASK                  0x03800000L
+#define SETUP_DEBUG_REG4__fpov_gated_MASK                  0x04000000L
+#define SETUP_DEBUG_REG4__fpov_gated                       0x04000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK            0x08000000L
+#define SETUP_DEBUG_REG4__pmode_prim_gated                 0x08000000L
+#define SETUP_DEBUG_REG4__event_gated_MASK                 0x10000000L
+#define SETUP_DEBUG_REG4__event_gated                      0x10000000L
+#define SETUP_DEBUG_REG4__eop_gated_MASK                   0x20000000L
+#define SETUP_DEBUG_REG4__eop_gated                        0x20000000L
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK       0x000007ffL
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK       0x003ff800L
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK         0x00c00000L
+#define SETUP_DEBUG_REG5__event_id_gated_MASK              0x1f000000L
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK               0x0000001fL
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA_MASK                        0xffffffffL
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1_MASK                      0x00000001L
+#define SC_DEBUG_0__pa_freeze_b1                           0x00000001L
+#define SC_DEBUG_0__pa_sc_valid_MASK                       0x00000002L
+#define SC_DEBUG_0__pa_sc_valid                            0x00000002L
+#define SC_DEBUG_0__pa_sc_phase_MASK                       0x0000001cL
+#define SC_DEBUG_0__cntx_cnt_MASK                          0x00000fe0L
+#define SC_DEBUG_0__decr_cntx_cnt_MASK                     0x00001000L
+#define SC_DEBUG_0__decr_cntx_cnt                          0x00001000L
+#define SC_DEBUG_0__incr_cntx_cnt_MASK                     0x00002000L
+#define SC_DEBUG_0__incr_cntx_cnt                          0x00002000L
+#define SC_DEBUG_0__trigger_MASK                           0x80000000L
+#define SC_DEBUG_0__trigger                                0x80000000L
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state_MASK                          0x00000007L
+#define SC_DEBUG_1__em1_data_ready_MASK                    0x00000008L
+#define SC_DEBUG_1__em1_data_ready                         0x00000008L
+#define SC_DEBUG_1__em2_data_ready_MASK                    0x00000010L
+#define SC_DEBUG_1__em2_data_ready                         0x00000010L
+#define SC_DEBUG_1__move_em1_to_em2_MASK                   0x00000020L
+#define SC_DEBUG_1__move_em1_to_em2                        0x00000020L
+#define SC_DEBUG_1__ef_data_ready_MASK                     0x00000040L
+#define SC_DEBUG_1__ef_data_ready                          0x00000040L
+#define SC_DEBUG_1__ef_state_MASK                          0x00000180L
+#define SC_DEBUG_1__pipe_valid_MASK                        0x00000200L
+#define SC_DEBUG_1__pipe_valid                             0x00000200L
+#define SC_DEBUG_1__trigger_MASK                           0x80000000L
+#define SC_DEBUG_1__trigger                                0x80000000L
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly_MASK                        0x00000001L
+#define SC_DEBUG_2__rc_rtr_dly                             0x00000001L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK              0x00000002L
+#define SC_DEBUG_2__qmask_ff_alm_full_d1                   0x00000002L
+#define SC_DEBUG_2__pipe_freeze_b_MASK                     0x00000008L
+#define SC_DEBUG_2__pipe_freeze_b                          0x00000008L
+#define SC_DEBUG_2__prim_rts_MASK                          0x00000010L
+#define SC_DEBUG_2__prim_rts                               0x00000010L
+#define SC_DEBUG_2__next_prim_rts_dly_MASK                 0x00000020L
+#define SC_DEBUG_2__next_prim_rts_dly                      0x00000020L
+#define SC_DEBUG_2__next_prim_rtr_dly_MASK                 0x00000040L
+#define SC_DEBUG_2__next_prim_rtr_dly                      0x00000040L
+#define SC_DEBUG_2__pre_stage1_rts_d1_MASK                 0x00000080L
+#define SC_DEBUG_2__pre_stage1_rts_d1                      0x00000080L
+#define SC_DEBUG_2__stage0_rts_MASK                        0x00000100L
+#define SC_DEBUG_2__stage0_rts                             0x00000100L
+#define SC_DEBUG_2__phase_rts_dly_MASK                     0x00000200L
+#define SC_DEBUG_2__phase_rts_dly                          0x00000200L
+#define SC_DEBUG_2__end_of_prim_s1_dly_MASK                0x00008000L
+#define SC_DEBUG_2__end_of_prim_s1_dly                     0x00008000L
+#define SC_DEBUG_2__pass_empty_prim_s1_MASK                0x00010000L
+#define SC_DEBUG_2__pass_empty_prim_s1                     0x00010000L
+#define SC_DEBUG_2__event_id_s1_MASK                       0x003e0000L
+#define SC_DEBUG_2__event_s1_MASK                          0x00400000L
+#define SC_DEBUG_2__event_s1                               0x00400000L
+#define SC_DEBUG_2__trigger_MASK                           0x80000000L
+#define SC_DEBUG_2__trigger                                0x80000000L
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1_MASK                         0x000007ffL
+#define SC_DEBUG_3__y_curr_s1_MASK                         0x003ff800L
+#define SC_DEBUG_3__trigger_MASK                           0x80000000L
+#define SC_DEBUG_3__trigger                                0x80000000L
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_4__y_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_4__y_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_4__y_dir_s1                               0x10000000L
+#define SC_DEBUG_4__trigger_MASK                           0x80000000L
+#define SC_DEBUG_4__trigger                                0x80000000L
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1_MASK                          0x00003fffL
+#define SC_DEBUG_5__x_start_s1_MASK                        0x0fffc000L
+#define SC_DEBUG_5__x_dir_s1_MASK                          0x10000000L
+#define SC_DEBUG_5__x_dir_s1                               0x10000000L
+#define SC_DEBUG_5__trigger_MASK                           0x80000000L
+#define SC_DEBUG_5__trigger                                0x80000000L
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty_MASK                        0x00000001L
+#define SC_DEBUG_6__z_ff_empty                             0x00000001L
+#define SC_DEBUG_6__qmcntl_ff_empty_MASK                   0x00000002L
+#define SC_DEBUG_6__qmcntl_ff_empty                        0x00000002L
+#define SC_DEBUG_6__xy_ff_empty_MASK                       0x00000004L
+#define SC_DEBUG_6__xy_ff_empty                            0x00000004L
+#define SC_DEBUG_6__event_flag_MASK                        0x00000008L
+#define SC_DEBUG_6__event_flag                             0x00000008L
+#define SC_DEBUG_6__z_mask_needed_MASK                     0x00000010L
+#define SC_DEBUG_6__z_mask_needed                          0x00000010L
+#define SC_DEBUG_6__state_MASK                             0x000000e0L
+#define SC_DEBUG_6__state_delayed_MASK                     0x00000700L
+#define SC_DEBUG_6__data_valid_MASK                        0x00000800L
+#define SC_DEBUG_6__data_valid                             0x00000800L
+#define SC_DEBUG_6__data_valid_d_MASK                      0x00001000L
+#define SC_DEBUG_6__data_valid_d                           0x00001000L
+#define SC_DEBUG_6__tilex_delayed_MASK                     0x003fe000L
+#define SC_DEBUG_6__tiley_delayed_MASK                     0x7fc00000L
+#define SC_DEBUG_6__trigger_MASK                           0x80000000L
+#define SC_DEBUG_6__trigger                                0x80000000L
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag_MASK                        0x00000001L
+#define SC_DEBUG_7__event_flag                             0x00000001L
+#define SC_DEBUG_7__deallocate_MASK                        0x0000000eL
+#define SC_DEBUG_7__fposition_MASK                         0x00000010L
+#define SC_DEBUG_7__fposition                              0x00000010L
+#define SC_DEBUG_7__sr_prim_we_MASK                        0x00000020L
+#define SC_DEBUG_7__sr_prim_we                             0x00000020L
+#define SC_DEBUG_7__last_tile_MASK                         0x00000040L
+#define SC_DEBUG_7__last_tile                              0x00000040L
+#define SC_DEBUG_7__tile_ff_we_MASK                        0x00000080L
+#define SC_DEBUG_7__tile_ff_we                             0x00000080L
+#define SC_DEBUG_7__qs_data_valid_MASK                     0x00000100L
+#define SC_DEBUG_7__qs_data_valid                          0x00000100L
+#define SC_DEBUG_7__qs_q0_y_MASK                           0x00000600L
+#define SC_DEBUG_7__qs_q0_x_MASK                           0x00001800L
+#define SC_DEBUG_7__qs_q0_valid_MASK                       0x00002000L
+#define SC_DEBUG_7__qs_q0_valid                            0x00002000L
+#define SC_DEBUG_7__prim_ff_we_MASK                        0x00004000L
+#define SC_DEBUG_7__prim_ff_we                             0x00004000L
+#define SC_DEBUG_7__tile_ff_re_MASK                        0x00008000L
+#define SC_DEBUG_7__tile_ff_re                             0x00008000L
+#define SC_DEBUG_7__fw_prim_data_valid_MASK                0x00010000L
+#define SC_DEBUG_7__fw_prim_data_valid                     0x00010000L
+#define SC_DEBUG_7__last_quad_of_tile_MASK                 0x00020000L
+#define SC_DEBUG_7__last_quad_of_tile                      0x00020000L
+#define SC_DEBUG_7__first_quad_of_tile_MASK                0x00040000L
+#define SC_DEBUG_7__first_quad_of_tile                     0x00040000L
+#define SC_DEBUG_7__first_quad_of_prim_MASK                0x00080000L
+#define SC_DEBUG_7__first_quad_of_prim                     0x00080000L
+#define SC_DEBUG_7__new_prim_MASK                          0x00100000L
+#define SC_DEBUG_7__new_prim                               0x00100000L
+#define SC_DEBUG_7__load_new_tile_data_MASK                0x00200000L
+#define SC_DEBUG_7__load_new_tile_data                     0x00200000L
+#define SC_DEBUG_7__state_MASK                             0x00c00000L
+#define SC_DEBUG_7__fifos_ready_MASK                       0x01000000L
+#define SC_DEBUG_7__fifos_ready                            0x01000000L
+#define SC_DEBUG_7__trigger_MASK                           0x80000000L
+#define SC_DEBUG_7__trigger                                0x80000000L
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last_MASK                       0x00000001L
+#define SC_DEBUG_8__sample_last                            0x00000001L
+#define SC_DEBUG_8__sample_mask_MASK                       0x0000001eL
+#define SC_DEBUG_8__sample_y_MASK                          0x00000060L
+#define SC_DEBUG_8__sample_x_MASK                          0x00000180L
+#define SC_DEBUG_8__sample_send_MASK                       0x00000200L
+#define SC_DEBUG_8__sample_send                            0x00000200L
+#define SC_DEBUG_8__next_cycle_MASK                        0x00000c00L
+#define SC_DEBUG_8__ez_sample_ff_full_MASK                 0x00001000L
+#define SC_DEBUG_8__ez_sample_ff_full                      0x00001000L
+#define SC_DEBUG_8__rb_sc_samp_rtr_MASK                    0x00002000L
+#define SC_DEBUG_8__rb_sc_samp_rtr                         0x00002000L
+#define SC_DEBUG_8__num_samples_MASK                       0x0000c000L
+#define SC_DEBUG_8__last_quad_of_tile_MASK                 0x00010000L
+#define SC_DEBUG_8__last_quad_of_tile                      0x00010000L
+#define SC_DEBUG_8__last_quad_of_prim_MASK                 0x00020000L
+#define SC_DEBUG_8__last_quad_of_prim                      0x00020000L
+#define SC_DEBUG_8__first_quad_of_prim_MASK                0x00040000L
+#define SC_DEBUG_8__first_quad_of_prim                     0x00040000L
+#define SC_DEBUG_8__sample_we_MASK                         0x00080000L
+#define SC_DEBUG_8__sample_we                              0x00080000L
+#define SC_DEBUG_8__fposition_MASK                         0x00100000L
+#define SC_DEBUG_8__fposition                              0x00100000L
+#define SC_DEBUG_8__event_id_MASK                          0x03e00000L
+#define SC_DEBUG_8__event_flag_MASK                        0x04000000L
+#define SC_DEBUG_8__event_flag                             0x04000000L
+#define SC_DEBUG_8__fw_prim_data_valid_MASK                0x08000000L
+#define SC_DEBUG_8__fw_prim_data_valid                     0x08000000L
+#define SC_DEBUG_8__trigger_MASK                           0x80000000L
+#define SC_DEBUG_8__trigger                                0x80000000L
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send_MASK                        0x00000001L
+#define SC_DEBUG_9__rb_sc_send                             0x00000001L
+#define SC_DEBUG_9__rb_sc_ez_mask_MASK                     0x0000001eL
+#define SC_DEBUG_9__fifo_data_ready_MASK                   0x00000020L
+#define SC_DEBUG_9__fifo_data_ready                        0x00000020L
+#define SC_DEBUG_9__early_z_enable_MASK                    0x00000040L
+#define SC_DEBUG_9__early_z_enable                         0x00000040L
+#define SC_DEBUG_9__mask_state_MASK                        0x00000180L
+#define SC_DEBUG_9__next_ez_mask_MASK                      0x01fffe00L
+#define SC_DEBUG_9__mask_ready_MASK                        0x02000000L
+#define SC_DEBUG_9__mask_ready                             0x02000000L
+#define SC_DEBUG_9__drop_sample_MASK                       0x04000000L
+#define SC_DEBUG_9__drop_sample                            0x04000000L
+#define SC_DEBUG_9__fetch_new_sample_data_MASK             0x08000000L
+#define SC_DEBUG_9__fetch_new_sample_data                  0x08000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK          0x10000000L
+#define SC_DEBUG_9__fetch_new_ez_sample_mask               0x10000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK         0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_sample_data              0x20000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK           0x40000000L
+#define SC_DEBUG_9__pkr_fetch_new_prim_data                0x40000000L
+#define SC_DEBUG_9__trigger_MASK                           0x80000000L
+#define SC_DEBUG_9__trigger                                0x80000000L
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask_MASK             0x0000ffffL
+#define SC_DEBUG_10__trigger_MASK                          0x80000000L
+#define SC_DEBUG_10__trigger                               0x80000000L
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready_MASK             0x00000001L
+#define SC_DEBUG_11__ez_sample_data_ready                  0x00000001L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK        0x00000002L
+#define SC_DEBUG_11__pkr_fetch_new_sample_data             0x00000002L
+#define SC_DEBUG_11__ez_prim_data_ready_MASK               0x00000004L
+#define SC_DEBUG_11__ez_prim_data_ready                    0x00000004L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK          0x00000008L
+#define SC_DEBUG_11__pkr_fetch_new_prim_data               0x00000008L
+#define SC_DEBUG_11__iterator_input_fz_MASK                0x00000010L
+#define SC_DEBUG_11__iterator_input_fz                     0x00000010L
+#define SC_DEBUG_11__packer_send_quads_MASK                0x00000020L
+#define SC_DEBUG_11__packer_send_quads                     0x00000020L
+#define SC_DEBUG_11__packer_send_cmd_MASK                  0x00000040L
+#define SC_DEBUG_11__packer_send_cmd                       0x00000040L
+#define SC_DEBUG_11__packer_send_event_MASK                0x00000080L
+#define SC_DEBUG_11__packer_send_event                     0x00000080L
+#define SC_DEBUG_11__next_state_MASK                       0x00000700L
+#define SC_DEBUG_11__state_MASK                            0x00003800L
+#define SC_DEBUG_11__stall_MASK                            0x00004000L
+#define SC_DEBUG_11__stall                                 0x00004000L
+#define SC_DEBUG_11__trigger_MASK                          0x80000000L
+#define SC_DEBUG_11__trigger                               0x80000000L
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff_MASK            0x00000001L
+#define SC_DEBUG_12__SQ_iterator_free_buff                 0x00000001L
+#define SC_DEBUG_12__event_id_MASK                         0x0000003eL
+#define SC_DEBUG_12__event_flag_MASK                       0x00000040L
+#define SC_DEBUG_12__event_flag                            0x00000040L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK          0x00000080L
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly               0x00000080L
+#define SC_DEBUG_12__itercmdfifo_full_MASK                 0x00000100L
+#define SC_DEBUG_12__itercmdfifo_full                      0x00000100L
+#define SC_DEBUG_12__itercmdfifo_empty_MASK                0x00000200L
+#define SC_DEBUG_12__itercmdfifo_empty                     0x00000200L
+#define SC_DEBUG_12__iter_ds_one_clk_command_MASK          0x00000400L
+#define SC_DEBUG_12__iter_ds_one_clk_command               0x00000400L
+#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK             0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_prim0                  0x00000800L
+#define SC_DEBUG_12__iter_ds_end_of_vector_MASK            0x00001000L
+#define SC_DEBUG_12__iter_ds_end_of_vector                 0x00001000L
+#define SC_DEBUG_12__iter_qdhit0_MASK                      0x00002000L
+#define SC_DEBUG_12__iter_qdhit0                           0x00002000L
+#define SC_DEBUG_12__bc_use_centers_reg_MASK               0x00004000L
+#define SC_DEBUG_12__bc_use_centers_reg                    0x00004000L
+#define SC_DEBUG_12__bc_output_xy_reg_MASK                 0x00008000L
+#define SC_DEBUG_12__bc_output_xy_reg                      0x00008000L
+#define SC_DEBUG_12__iter_phase_out_MASK                   0x00030000L
+#define SC_DEBUG_12__iter_phase_reg_MASK                   0x000c0000L
+#define SC_DEBUG_12__iterator_SP_valid_MASK                0x00100000L
+#define SC_DEBUG_12__iterator_SP_valid                     0x00100000L
+#define SC_DEBUG_12__eopv_reg_MASK                         0x00200000L
+#define SC_DEBUG_12__eopv_reg                              0x00200000L
+#define SC_DEBUG_12__one_clk_cmd_reg_MASK                  0x00400000L
+#define SC_DEBUG_12__one_clk_cmd_reg                       0x00400000L
+#define SC_DEBUG_12__iter_dx_end_of_prim_MASK              0x00800000L
+#define SC_DEBUG_12__iter_dx_end_of_prim                   0x00800000L
+#define SC_DEBUG_12__trigger_MASK                          0x80000000L
+#define SC_DEBUG_12__trigger                               0x80000000L
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK                  0x00000001L
+#define GFX_COPY_STATE__SRC_STATE_ID                       0x00000001L
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK                 0x0000003fL
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK             0x000000c0L
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK      0x00000300L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK                0x00000800L
+#define VGT_DRAW_INITIATOR__INDEX_SIZE                     0x00000800L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK                   0x00001000L
+#define VGT_DRAW_INITIATOR__NOT_EOP                        0x00001000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK               0x00002000L
+#define VGT_DRAW_INITIATOR__SMALL_INDEX                    0x00002000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK     0x00004000L
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE          0x00004000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK           0x00008000L
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE                0x00008000L
+#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK               0xffff0000L
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK               0x0000003fL
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR_MASK                       0xffffffffL
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_DMA_SIZE__SWAP_MODE_MASK                       0xc0000000L
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK                   0xffffffffL
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS_MASK                       0x00ffffffL
+#define VGT_BIN_SIZE__FACENESS_FETCH_MASK                  0x40000000L
+#define VGT_BIN_SIZE__FACENESS_FETCH                       0x40000000L
+#define VGT_BIN_SIZE__FACENESS_RESET_MASK                  0x80000000L
+#define VGT_BIN_SIZE__FACENESS_RESET                       0x80000000L
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK                0x00000007L
+#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK                   0x00000038L
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK            0x000001c0L
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK                    0x00ffffffL
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK                    0x00ffffffL
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK                  0x00ffffffL
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK  0x00000007L
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK            0x00000003L
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK      0x00ffffffL
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC_MASK                             0x0000ffffL
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK            0x0000001fL
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK             0x00000001L
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID                  0x00000001L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK             0x00010000L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID                  0x00010000L
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK                0x0000001fL
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA_MASK                          0xffffffffL
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK                     0x00000001L
+#define VGT_CNTL_STATUS__VGT_BUSY                          0x00000001L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK                 0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY                      0x00000002L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK             0x00000004L
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY                  0x00000004L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK                 0x00000008L
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY                      0x00000008L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                  0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY                       0x00000010L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK                 0x00000020L
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY                      0x00000020L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                  0x00000040L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY                       0x00000040L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                 0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY                      0x00000080L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK            0x00000100L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY                 0x00000100L
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy_MASK                   0x00000001L
+#define VGT_DEBUG_REG0__te_grp_busy                        0x00000001L
+#define VGT_DEBUG_REG0__pt_grp_busy_MASK                   0x00000002L
+#define VGT_DEBUG_REG0__pt_grp_busy                        0x00000002L
+#define VGT_DEBUG_REG0__vr_grp_busy_MASK                   0x00000004L
+#define VGT_DEBUG_REG0__vr_grp_busy                        0x00000004L
+#define VGT_DEBUG_REG0__dma_request_busy_MASK              0x00000008L
+#define VGT_DEBUG_REG0__dma_request_busy                   0x00000008L
+#define VGT_DEBUG_REG0__out_busy_MASK                      0x00000010L
+#define VGT_DEBUG_REG0__out_busy                           0x00000010L
+#define VGT_DEBUG_REG0__grp_backend_busy_MASK              0x00000020L
+#define VGT_DEBUG_REG0__grp_backend_busy                   0x00000020L
+#define VGT_DEBUG_REG0__grp_busy_MASK                      0x00000040L
+#define VGT_DEBUG_REG0__grp_busy                           0x00000040L
+#define VGT_DEBUG_REG0__dma_busy_MASK                      0x00000080L
+#define VGT_DEBUG_REG0__dma_busy                           0x00000080L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK         0x00000100L
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy              0x00000100L
+#define VGT_DEBUG_REG0__rbiu_busy_MASK                     0x00000200L
+#define VGT_DEBUG_REG0__rbiu_busy                          0x00000200L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK      0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended           0x00000400L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK               0x00000800L
+#define VGT_DEBUG_REG0__vgt_no_dma_busy                    0x00000800L
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK             0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_extended                  0x00001000L
+#define VGT_DEBUG_REG0__vgt_busy_MASK                      0x00002000L
+#define VGT_DEBUG_REG0__vgt_busy                           0x00002000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK       0x00004000L
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out            0x00004000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK          0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy               0x00008000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK                 0x00010000L
+#define VGT_DEBUG_REG0__VGT_RBBM_busy                      0x00010000L
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read_MASK              0x00000001L
+#define VGT_DEBUG_REG1__out_te_data_read                   0x00000001L
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK             0x00000002L
+#define VGT_DEBUG_REG1__te_out_data_valid                  0x00000002L
+#define VGT_DEBUG_REG1__out_pt_prim_read_MASK              0x00000004L
+#define VGT_DEBUG_REG1__out_pt_prim_read                   0x00000004L
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK             0x00000008L
+#define VGT_DEBUG_REG1__pt_out_prim_valid                  0x00000008L
+#define VGT_DEBUG_REG1__out_pt_data_read_MASK              0x00000010L
+#define VGT_DEBUG_REG1__out_pt_data_read                   0x00000010L
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK             0x00000020L
+#define VGT_DEBUG_REG1__pt_out_indx_valid                  0x00000020L
+#define VGT_DEBUG_REG1__out_vr_prim_read_MASK              0x00000040L
+#define VGT_DEBUG_REG1__out_vr_prim_read                   0x00000040L
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK             0x00000080L
+#define VGT_DEBUG_REG1__vr_out_prim_valid                  0x00000080L
+#define VGT_DEBUG_REG1__out_vr_indx_read_MASK              0x00000100L
+#define VGT_DEBUG_REG1__out_vr_indx_read                   0x00000100L
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK             0x00000200L
+#define VGT_DEBUG_REG1__vr_out_indx_valid                  0x00000200L
+#define VGT_DEBUG_REG1__te_grp_read_MASK                   0x00000400L
+#define VGT_DEBUG_REG1__te_grp_read                        0x00000400L
+#define VGT_DEBUG_REG1__grp_te_valid_MASK                  0x00000800L
+#define VGT_DEBUG_REG1__grp_te_valid                       0x00000800L
+#define VGT_DEBUG_REG1__pt_grp_read_MASK                   0x00001000L
+#define VGT_DEBUG_REG1__pt_grp_read                        0x00001000L
+#define VGT_DEBUG_REG1__grp_pt_valid_MASK                  0x00002000L
+#define VGT_DEBUG_REG1__grp_pt_valid                       0x00002000L
+#define VGT_DEBUG_REG1__vr_grp_read_MASK                   0x00004000L
+#define VGT_DEBUG_REG1__vr_grp_read                        0x00004000L
+#define VGT_DEBUG_REG1__grp_vr_valid_MASK                  0x00008000L
+#define VGT_DEBUG_REG1__grp_vr_valid                       0x00008000L
+#define VGT_DEBUG_REG1__grp_dma_read_MASK                  0x00010000L
+#define VGT_DEBUG_REG1__grp_dma_read                       0x00010000L
+#define VGT_DEBUG_REG1__dma_grp_valid_MASK                 0x00020000L
+#define VGT_DEBUG_REG1__dma_grp_valid                      0x00020000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK              0x00040000L
+#define VGT_DEBUG_REG1__grp_rbiu_di_read                   0x00040000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK             0x00080000L
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid                  0x00080000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK                    0x00100000L
+#define VGT_DEBUG_REG1__MH_VGT_rtr                         0x00100000L
+#define VGT_DEBUG_REG1__VGT_MH_send_MASK                   0x00200000L
+#define VGT_DEBUG_REG1__VGT_MH_send                        0x00200000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK             0x00400000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr                  0x00400000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK            0x00800000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send                 0x00800000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK             0x01000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr                  0x01000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK            0x02000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send                 0x02000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK             0x04000000L
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr                  0x04000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK            0x08000000L
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send                 0x08000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK                    0x10000000L
+#define VGT_DEBUG_REG1__SQ_VGT_rtr                         0x10000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send_MASK                   0x20000000L
+#define VGT_DEBUG_REG1__VGT_SQ_send                        0x20000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK                0x40000000L
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q                     0x40000000L
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en_MASK                    0x00000001L
+#define VGT_DEBUG_REG3__vgt_clk_en                         0x00000001L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK              0x00000002L
+#define VGT_DEBUG_REG3__reg_fifos_clk_en                   0x00000002L
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK          0x0000001fL
+#define VGT_DEBUG_REG6__right_word_indx_q_MASK             0x000003e0L
+#define VGT_DEBUG_REG6__input_data_valid_MASK              0x00000400L
+#define VGT_DEBUG_REG6__input_data_valid                   0x00000400L
+#define VGT_DEBUG_REG6__input_data_xfer_MASK               0x00000800L
+#define VGT_DEBUG_REG6__input_data_xfer                    0x00000800L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK        0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q             0x00001000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK        0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d             0x00002000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK    0x00004000L
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d         0x00004000L
+#define VGT_DEBUG_REG6__space_avail_from_shift_MASK        0x00008000L
+#define VGT_DEBUG_REG6__space_avail_from_shift             0x00008000L
+#define VGT_DEBUG_REG6__shifter_first_load_MASK            0x00010000L
+#define VGT_DEBUG_REG6__shifter_first_load                 0x00010000L
+#define VGT_DEBUG_REG6__di_state_sel_q_MASK                0x00020000L
+#define VGT_DEBUG_REG6__di_state_sel_q                     0x00020000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q   0x00040000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK         0x00080000L
+#define VGT_DEBUG_REG6__di_first_group_flag_q              0x00080000L
+#define VGT_DEBUG_REG6__di_event_flag_q_MASK               0x00100000L
+#define VGT_DEBUG_REG6__di_event_flag_q                    0x00100000L
+#define VGT_DEBUG_REG6__read_draw_initiator_MASK           0x00200000L
+#define VGT_DEBUG_REG6__read_draw_initiator                0x00200000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK   0x00400000L
+#define VGT_DEBUG_REG6__loading_di_requires_shifter        0x00400000L
+#define VGT_DEBUG_REG6__last_shift_of_packet_MASK          0x00800000L
+#define VGT_DEBUG_REG6__last_shift_of_packet               0x00800000L
+#define VGT_DEBUG_REG6__last_decr_of_packet_MASK           0x01000000L
+#define VGT_DEBUG_REG6__last_decr_of_packet                0x01000000L
+#define VGT_DEBUG_REG6__extract_vector_MASK                0x02000000L
+#define VGT_DEBUG_REG6__extract_vector                     0x02000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr_MASK                0x04000000L
+#define VGT_DEBUG_REG6__shift_vect_rtr                     0x04000000L
+#define VGT_DEBUG_REG6__destination_rtr_MASK               0x08000000L
+#define VGT_DEBUG_REG6__destination_rtr                    0x08000000L
+#define VGT_DEBUG_REG6__grp_trigger_MASK                   0x10000000L
+#define VGT_DEBUG_REG6__grp_trigger                        0x10000000L
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q_MASK            0x0000ffffL
+#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK       0x000f0000L
+#define VGT_DEBUG_REG7__shift_amount_extract_MASK          0x00f00000L
+#define VGT_DEBUG_REG7__di_prim_type_q_MASK                0x3f000000L
+#define VGT_DEBUG_REG7__current_source_sel_MASK            0xc0000000L
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel_MASK            0x00000003L
+#define VGT_DEBUG_REG8__left_word_indx_q_MASK              0x0000007cL
+#define VGT_DEBUG_REG8__input_data_cnt_MASK                0x00000f80L
+#define VGT_DEBUG_REG8__input_data_lsw_MASK                0x0001f000L
+#define VGT_DEBUG_REG8__input_data_msw_MASK                0x003e0000L
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q_MASK                 0x0000001fL
+#define VGT_DEBUG_REG9__next_stride_d_MASK                 0x000003e0L
+#define VGT_DEBUG_REG9__current_shift_q_MASK               0x00007c00L
+#define VGT_DEBUG_REG9__current_shift_d_MASK               0x000f8000L
+#define VGT_DEBUG_REG9__current_stride_q_MASK              0x01f00000L
+#define VGT_DEBUG_REG9__current_stride_d_MASK              0x3e000000L
+#define VGT_DEBUG_REG9__grp_trigger_MASK                   0x40000000L
+#define VGT_DEBUG_REG9__grp_trigger                        0x40000000L
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0      0x00000001L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0    0x00000002L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0    0x00000004L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L
+#define VGT_DEBUG_REG10__di_state_sel_q_MASK               0x00000010L
+#define VGT_DEBUG_REG10__di_state_sel_q                    0x00000010L
+#define VGT_DEBUG_REG10__last_decr_of_packet_MASK          0x00000020L
+#define VGT_DEBUG_REG10__last_decr_of_packet               0x00000020L
+#define VGT_DEBUG_REG10__bin_valid_MASK                    0x00000040L
+#define VGT_DEBUG_REG10__bin_valid                         0x00000040L
+#define VGT_DEBUG_REG10__read_block_MASK                   0x00000080L
+#define VGT_DEBUG_REG10__read_block                        0x00000080L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK       0x00000100L
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read            0x00000100L
+#define VGT_DEBUG_REG10__last_bit_enable_q_MASK            0x00000200L
+#define VGT_DEBUG_REG10__last_bit_enable_q                 0x00000200L
+#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK            0x00000400L
+#define VGT_DEBUG_REG10__last_bit_end_di_q                 0x00000400L
+#define VGT_DEBUG_REG10__selected_data_MASK                0x0007f800L
+#define VGT_DEBUG_REG10__mask_input_data_MASK              0x07f80000L
+#define VGT_DEBUG_REG10__gap_q_MASK                        0x08000000L
+#define VGT_DEBUG_REG10__gap_q                             0x08000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK            0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_z                 0x10000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK            0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_y                 0x20000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK            0x40000000L
+#define VGT_DEBUG_REG10__temp_mini_reset_x                 0x40000000L
+#define VGT_DEBUG_REG10__grp_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG10__grp_trigger                       0x80000000L
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK         0x0000001fL
+#define VGT_DEBUG_REG12__right_word_indx_q_MASK            0x000003e0L
+#define VGT_DEBUG_REG12__input_data_valid_MASK             0x00000400L
+#define VGT_DEBUG_REG12__input_data_valid                  0x00000400L
+#define VGT_DEBUG_REG12__input_data_xfer_MASK              0x00000800L
+#define VGT_DEBUG_REG12__input_data_xfer                   0x00000800L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK       0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q            0x00001000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK       0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d            0x00002000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK   0x00004000L
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d        0x00004000L
+#define VGT_DEBUG_REG12__space_avail_from_shift_MASK       0x00008000L
+#define VGT_DEBUG_REG12__space_avail_from_shift            0x00008000L
+#define VGT_DEBUG_REG12__shifter_first_load_MASK           0x00010000L
+#define VGT_DEBUG_REG12__shifter_first_load                0x00010000L
+#define VGT_DEBUG_REG12__di_state_sel_q_MASK               0x00020000L
+#define VGT_DEBUG_REG12__di_state_sel_q                    0x00020000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q  0x00040000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK        0x00080000L
+#define VGT_DEBUG_REG12__di_first_group_flag_q             0x00080000L
+#define VGT_DEBUG_REG12__di_event_flag_q_MASK              0x00100000L
+#define VGT_DEBUG_REG12__di_event_flag_q                   0x00100000L
+#define VGT_DEBUG_REG12__read_draw_initiator_MASK          0x00200000L
+#define VGT_DEBUG_REG12__read_draw_initiator               0x00200000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK  0x00400000L
+#define VGT_DEBUG_REG12__loading_di_requires_shifter       0x00400000L
+#define VGT_DEBUG_REG12__last_shift_of_packet_MASK         0x00800000L
+#define VGT_DEBUG_REG12__last_shift_of_packet              0x00800000L
+#define VGT_DEBUG_REG12__last_decr_of_packet_MASK          0x01000000L
+#define VGT_DEBUG_REG12__last_decr_of_packet               0x01000000L
+#define VGT_DEBUG_REG12__extract_vector_MASK               0x02000000L
+#define VGT_DEBUG_REG12__extract_vector                    0x02000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr_MASK               0x04000000L
+#define VGT_DEBUG_REG12__shift_vect_rtr                    0x04000000L
+#define VGT_DEBUG_REG12__destination_rtr_MASK              0x08000000L
+#define VGT_DEBUG_REG12__destination_rtr                   0x08000000L
+#define VGT_DEBUG_REG12__bgrp_trigger_MASK                 0x10000000L
+#define VGT_DEBUG_REG12__bgrp_trigger                      0x10000000L
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q_MASK           0x0000ffffL
+#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK      0x000f0000L
+#define VGT_DEBUG_REG13__shift_amount_extract_MASK         0x00f00000L
+#define VGT_DEBUG_REG13__di_prim_type_q_MASK               0x3f000000L
+#define VGT_DEBUG_REG13__current_source_sel_MASK           0xc0000000L
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel_MASK           0x00000003L
+#define VGT_DEBUG_REG14__left_word_indx_q_MASK             0x0000007cL
+#define VGT_DEBUG_REG14__input_data_cnt_MASK               0x00000f80L
+#define VGT_DEBUG_REG14__input_data_lsw_MASK               0x0001f000L
+#define VGT_DEBUG_REG14__input_data_msw_MASK               0x003e0000L
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q_MASK                0x0000001fL
+#define VGT_DEBUG_REG15__next_stride_d_MASK                0x000003e0L
+#define VGT_DEBUG_REG15__current_shift_q_MASK              0x00007c00L
+#define VGT_DEBUG_REG15__current_shift_d_MASK              0x000f8000L
+#define VGT_DEBUG_REG15__current_stride_q_MASK             0x01f00000L
+#define VGT_DEBUG_REG15__current_stride_d_MASK             0x3e000000L
+#define VGT_DEBUG_REG15__bgrp_trigger_MASK                 0x40000000L
+#define VGT_DEBUG_REG15__bgrp_trigger                      0x40000000L
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK    0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full         0x00000001L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK   0x00000002L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty        0x00000002L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK     0x00000004L
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read          0x00000004L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK      0x00000008L
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we           0x00000008L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK     0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full          0x00000010L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK    0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty         0x00000020L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK     0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q          0x00000040L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK       0x00000080L
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we            0x00000080L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK           0x00000100L
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill                0x00000100L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK           0x00000200L
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid                0x00000200L
+#define VGT_DEBUG_REG16__rst_last_bit_MASK                 0x00000400L
+#define VGT_DEBUG_REG16__rst_last_bit                      0x00000400L
+#define VGT_DEBUG_REG16__current_state_q_MASK              0x00000800L
+#define VGT_DEBUG_REG16__current_state_q                   0x00000800L
+#define VGT_DEBUG_REG16__old_state_q_MASK                  0x00001000L
+#define VGT_DEBUG_REG16__old_state_q                       0x00001000L
+#define VGT_DEBUG_REG16__old_state_en_MASK                 0x00002000L
+#define VGT_DEBUG_REG16__old_state_en                      0x00002000L
+#define VGT_DEBUG_REG16__prev_last_bit_q_MASK              0x00004000L
+#define VGT_DEBUG_REG16__prev_last_bit_q                   0x00004000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK               0x00008000L
+#define VGT_DEBUG_REG16__dbl_last_bit_q                    0x00008000L
+#define VGT_DEBUG_REG16__last_bit_block_q_MASK             0x00010000L
+#define VGT_DEBUG_REG16__last_bit_block_q                  0x00010000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK             0x00020000L
+#define VGT_DEBUG_REG16__ast_bit_block2_q                  0x00020000L
+#define VGT_DEBUG_REG16__load_empty_reg_MASK               0x00040000L
+#define VGT_DEBUG_REG16__load_empty_reg                    0x00040000L
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK     0x07f80000L
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK  0x18000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable      0x20000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK     0x40000000L
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q          0x40000000L
+#define VGT_DEBUG_REG16__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG16__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q_MASK                  0x00000001L
+#define VGT_DEBUG_REG17__save_read_q                       0x00000001L
+#define VGT_DEBUG_REG17__extend_read_q_MASK                0x00000002L
+#define VGT_DEBUG_REG17__extend_read_q                     0x00000002L
+#define VGT_DEBUG_REG17__grp_indx_size_MASK                0x0000000cL
+#define VGT_DEBUG_REG17__cull_prim_true_MASK               0x00000010L
+#define VGT_DEBUG_REG17__cull_prim_true                    0x00000010L
+#define VGT_DEBUG_REG17__reset_bit2_q_MASK                 0x00000020L
+#define VGT_DEBUG_REG17__reset_bit2_q                      0x00000020L
+#define VGT_DEBUG_REG17__reset_bit1_q_MASK                 0x00000040L
+#define VGT_DEBUG_REG17__reset_bit1_q                      0x00000040L
+#define VGT_DEBUG_REG17__first_reg_first_q_MASK            0x00000080L
+#define VGT_DEBUG_REG17__first_reg_first_q                 0x00000080L
+#define VGT_DEBUG_REG17__check_second_reg_MASK             0x00000100L
+#define VGT_DEBUG_REG17__check_second_reg                  0x00000100L
+#define VGT_DEBUG_REG17__check_first_reg_MASK              0x00000200L
+#define VGT_DEBUG_REG17__check_first_reg                   0x00000200L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK   0x00000400L
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata        0x00000400L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK      0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q           0x00000800L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK      0x00001000L
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q           0x00001000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK       0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q            0x00002000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK       0x00004000L
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q            0x00004000L
+#define VGT_DEBUG_REG17__to_second_reg_q_MASK              0x00008000L
+#define VGT_DEBUG_REG17__to_second_reg_q                   0x00008000L
+#define VGT_DEBUG_REG17__roll_over_msk_q_MASK              0x00010000L
+#define VGT_DEBUG_REG17__roll_over_msk_q                   0x00010000L
+#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK                0x00fe0000L
+#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK                0x7f000000L
+#define VGT_DEBUG_REG17__bgrp_trigger_MASK                 0x80000000L
+#define VGT_DEBUG_REG17__bgrp_trigger                      0x80000000L
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK      0x0000003fL
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK      0x00000fc0L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK   0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re        0x00001000L
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK  0x00006000L
+#define VGT_DEBUG_REG18__dma_mem_full_MASK                 0x00008000L
+#define VGT_DEBUG_REG18__dma_mem_full                      0x00008000L
+#define VGT_DEBUG_REG18__dma_ram_re_MASK                   0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_re                        0x00010000L
+#define VGT_DEBUG_REG18__dma_ram_we_MASK                   0x00020000L
+#define VGT_DEBUG_REG18__dma_ram_we                        0x00020000L
+#define VGT_DEBUG_REG18__dma_mem_empty_MASK                0x00040000L
+#define VGT_DEBUG_REG18__dma_mem_empty                     0x00040000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK         0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re              0x00080000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK         0x00100000L
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we              0x00100000L
+#define VGT_DEBUG_REG18__bin_mem_full_MASK                 0x00200000L
+#define VGT_DEBUG_REG18__bin_mem_full                      0x00200000L
+#define VGT_DEBUG_REG18__bin_ram_we_MASK                   0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_we                        0x00400000L
+#define VGT_DEBUG_REG18__bin_ram_re_MASK                   0x00800000L
+#define VGT_DEBUG_REG18__bin_ram_re                        0x00800000L
+#define VGT_DEBUG_REG18__bin_mem_empty_MASK                0x01000000L
+#define VGT_DEBUG_REG18__bin_mem_empty                     0x01000000L
+#define VGT_DEBUG_REG18__start_bin_req_MASK                0x02000000L
+#define VGT_DEBUG_REG18__start_bin_req                     0x02000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK          0x04000000L
+#define VGT_DEBUG_REG18__fetch_cull_not_used               0x04000000L
+#define VGT_DEBUG_REG18__dma_req_xfer_MASK                 0x08000000L
+#define VGT_DEBUG_REG18__dma_req_xfer                      0x08000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req_MASK           0x10000000L
+#define VGT_DEBUG_REG18__have_valid_bin_req                0x10000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req_MASK           0x20000000L
+#define VGT_DEBUG_REG18__have_valid_dma_req                0x20000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK  0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable       0x40000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK         0x00000001L
+#define VGT_DEBUG_REG20__prim_side_indx_valid              0x00000001L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK         0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_empty              0x00000002L
+#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK            0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_re                 0x00000004L
+#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK            0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_we                 0x00000008L
+#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK          0x00000010L
+#define VGT_DEBUG_REG20__indx_side_fifo_full               0x00000010L
+#define VGT_DEBUG_REG20__prim_buffer_empty_MASK            0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_empty                 0x00000020L
+#define VGT_DEBUG_REG20__prim_buffer_re_MASK               0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_re                    0x00000040L
+#define VGT_DEBUG_REG20__prim_buffer_we_MASK               0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_we                    0x00000080L
+#define VGT_DEBUG_REG20__prim_buffer_full_MASK             0x00000100L
+#define VGT_DEBUG_REG20__prim_buffer_full                  0x00000100L
+#define VGT_DEBUG_REG20__indx_buffer_empty_MASK            0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_empty                 0x00000200L
+#define VGT_DEBUG_REG20__indx_buffer_re_MASK               0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_re                    0x00000400L
+#define VGT_DEBUG_REG20__indx_buffer_we_MASK               0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_we                    0x00000800L
+#define VGT_DEBUG_REG20__indx_buffer_full_MASK             0x00001000L
+#define VGT_DEBUG_REG20__indx_buffer_full                  0x00001000L
+#define VGT_DEBUG_REG20__hold_prim_MASK                    0x00002000L
+#define VGT_DEBUG_REG20__hold_prim                         0x00002000L
+#define VGT_DEBUG_REG20__sent_cnt_MASK                     0x0003c000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK          0x00040000L
+#define VGT_DEBUG_REG20__start_of_vtx_vector               0x00040000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK         0x00080000L
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim              0x00080000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK         0x00100000L
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim              0x00100000L
+#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK     0x03e00000L
+#define VGT_DEBUG_REG20__out_trigger_MASK                  0x04000000L
+#define VGT_DEBUG_REG20__out_trigger                       0x04000000L
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK    0x00000001L
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector         0x00000001L
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK   0x0000000eL
+#define VGT_DEBUG_REG21__alloc_counter_q_MASK              0x00000070L
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK      0x00000380L
+#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK            0x00003c00L
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK      0x0003c000L
+#define VGT_DEBUG_REG21__new_packet_q_MASK                 0x00040000L
+#define VGT_DEBUG_REG21__new_packet_q                      0x00040000L
+#define VGT_DEBUG_REG21__new_allocate_q_MASK               0x00080000L
+#define VGT_DEBUG_REG21__new_allocate_q                    0x00080000L
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK      0x00300000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK         0x00400000L
+#define VGT_DEBUG_REG21__inserted_null_prim_q              0x00400000L
+#define VGT_DEBUG_REG21__insert_null_prim_MASK             0x00800000L
+#define VGT_DEBUG_REG21__insert_null_prim                  0x00800000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK        0x01000000L
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux             0x01000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK        0x02000000L
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux             0x02000000L
+#define VGT_DEBUG_REG21__buffered_thread_size_MASK         0x04000000L
+#define VGT_DEBUG_REG21__buffered_thread_size              0x04000000L
+#define VGT_DEBUG_REG21__out_trigger_MASK                  0x80000000L
+#define VGT_DEBUG_REG21__out_trigger                       0x80000000L
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC_MASK                          0xffffffffL
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC_MASK                          0xffffffffL
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK             0x000000ffL
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK              0xffffffffL
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK               0x0000ffffL
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE_MASK                 0x00000001L
+#define TC_CNTL_STATUS__L2_INVALIDATE                      0x00000001L
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK                0x000c0000L
+#define TC_CNTL_STATUS__TC_BUSY_MASK                       0x80000000L
+#define TC_CNTL_STATUS__TC_BUSY                            0x80000000L
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE_MASK                            0xffffffffL
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK                 0x00000100L
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN                      0x00000100L
+#define TCM_CHICKEN__SPARE_MASK                            0xfffffe00L
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK            0x00000007L
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK            0x00000038L
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK               0x00000001L
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY                    0x00000001L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK             0x00000002L
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY                  0x00000002L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK          0x00000004L
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY               0x00000004L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK          0x00000008L
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY               0x00000008L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK         0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY              0x00000010L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK           0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY                0x00000020L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK              0x00000040L
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY                   0x00000040L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK        0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY             0x00000100L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK          0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY               0x00000200L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK             0x00000400L
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY                  0x00000400L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK             0x00001000L
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY                  0x00001000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK          0x00002000L
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY               0x00002000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK            0x00004000L
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY                 0x00004000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK               0x00008000L
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY                    0x00008000L
+#define TPC_CNTL_STATUS__TF_TW_RTS_MASK                    0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_RTS                         0x00010000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK              0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS                   0x00020000L
+#define TPC_CNTL_STATUS__TF_TW_RTR_MASK                    0x00080000L
+#define TPC_CNTL_STATUS__TF_TW_RTR                         0x00080000L
+#define TPC_CNTL_STATUS__TW_TA_RTS_MASK                    0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_RTS                         0x00100000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK                 0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS                      0x00200000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK               0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS                    0x00400000L
+#define TPC_CNTL_STATUS__TW_TA_RTR_MASK                    0x00800000L
+#define TPC_CNTL_STATUS__TW_TA_RTR                         0x00800000L
+#define TPC_CNTL_STATUS__TA_TB_RTS_MASK                    0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_RTS                         0x01000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK                 0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS                      0x02000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR_MASK                    0x08000000L
+#define TPC_CNTL_STATUS__TA_TB_RTR                         0x08000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS_MASK                    0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_RTS                         0x10000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK            0x20000000L
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN                 0x20000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK                    0x40000000L
+#define TPC_CNTL_STATUS__TP_SQ_DEC                         0x40000000L
+#define TPC_CNTL_STATUS__TPC_BUSY_MASK                     0x80000000L
+#define TPC_CNTL_STATUS__TPC_BUSY                          0x80000000L
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL_MASK                          0x00000003L
+#define TPC_DEBUG0__IC_CTR_MASK                            0x0000000cL
+#define TPC_DEBUG0__WALKER_CNTL_MASK                       0x000000f0L
+#define TPC_DEBUG0__ALIGNER_CNTL_MASK                      0x00000700L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK               0x00001000L
+#define TPC_DEBUG0__PREV_TC_STATE_VALID                    0x00001000L
+#define TPC_DEBUG0__WALKER_STATE_MASK                      0x03ff0000L
+#define TPC_DEBUG0__ALIGNER_STATE_MASK                     0x0c000000L
+#define TPC_DEBUG0__REG_CLK_EN_MASK                        0x20000000L
+#define TPC_DEBUG0__REG_CLK_EN                             0x20000000L
+#define TPC_DEBUG0__TPC_CLK_EN_MASK                        0x40000000L
+#define TPC_DEBUG0__TPC_CLK_EN                             0x40000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK                      0x80000000L
+#define TPC_DEBUG0__SQ_TP_WAKEUP                           0x80000000L
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED_MASK                            0x00000001L
+#define TPC_DEBUG1__UNUSED                                 0x00000001L
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION_MASK                  0x00000001L
+#define TPC_CHICKEN__BLEND_PRECISION                       0x00000001L
+#define TPC_CHICKEN__SPARE_MASK                            0xfffffffeL
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK                0x00000001L
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY                     0x00000001L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK                  0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_BUSY                       0x00000002L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK             0x00000004L
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY                  0x00000004L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK                 0x00000008L
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY                      0x00000008L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK           0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY                0x00000010L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK              0x00000020L
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY                   0x00000020L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK              0x00000040L
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY                   0x00000040L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK              0x00000080L
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY                   0x00000080L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK                0x00000100L
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY                     0x00000100L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK             0x00000200L
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY                  0x00000200L
+#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK                   0x00000400L
+#define TP0_CNTL_STATUS__TP_TT_BUSY                        0x00000400L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK              0x00000800L
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY                   0x00000800L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK                0x00001000L
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY                     0x00001000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK             0x00002000L
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY                  0x00002000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK               0x00004000L
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY                    0x00004000L
+#define TP0_CNTL_STATUS__IN_LC_RTS_MASK                    0x00010000L
+#define TP0_CNTL_STATUS__IN_LC_RTS                         0x00010000L
+#define TP0_CNTL_STATUS__LC_LA_RTS_MASK                    0x00020000L
+#define TP0_CNTL_STATUS__LC_LA_RTS                         0x00020000L
+#define TP0_CNTL_STATUS__LA_FL_RTS_MASK                    0x00040000L
+#define TP0_CNTL_STATUS__LA_FL_RTS                         0x00040000L
+#define TP0_CNTL_STATUS__FL_TA_RTS_MASK                    0x00080000L
+#define TP0_CNTL_STATUS__FL_TA_RTS                         0x00080000L
+#define TP0_CNTL_STATUS__TA_FA_RTS_MASK                    0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_RTS                         0x00100000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK                 0x00200000L
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS                      0x00200000L
+#define TP0_CNTL_STATUS__FA_AL_RTS_MASK                    0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_RTS                         0x00400000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK                 0x00800000L
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS                      0x00800000L
+#define TP0_CNTL_STATUS__AL_TF_RTS_MASK                    0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_RTS                         0x01000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK                 0x02000000L
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS                      0x02000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS_MASK                    0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_RTS                         0x04000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK                 0x08000000L
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS                      0x08000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS_MASK                    0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_RTS                         0x10000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK               0x20000000L
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET                    0x20000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS_MASK                    0x40000000L
+#define TP0_CNTL_STATUS__TB_TO_RTS                         0x40000000L
+#define TP0_CNTL_STATUS__TP_BUSY_MASK                      0x80000000L
+#define TP0_CNTL_STATUS__TP_BUSY                           0x80000000L
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL_MASK                         0x00000003L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK                     0x00000008L
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP                          0x00000008L
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK               0x001ffff0L
+#define TP0_DEBUG__REG_CLK_EN_MASK                         0x00200000L
+#define TP0_DEBUG__REG_CLK_EN                              0x00200000L
+#define TP0_DEBUG__PERF_CLK_EN_MASK                        0x00400000L
+#define TP0_DEBUG__PERF_CLK_EN                             0x00400000L
+#define TP0_DEBUG__TP_CLK_EN_MASK                          0x00800000L
+#define TP0_DEBUG__TP_CLK_EN                               0x00800000L
+#define TP0_DEBUG__Q_WALKER_CNTL_MASK                      0x0f000000L
+#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK                     0x70000000L
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE_MASK                          0x00000001L
+#define TP0_CHICKEN__TT_MODE                               0x00000001L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK              0x00000002L
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE                   0x00000002L
+#define TP0_CHICKEN__SPARE_MASK                            0xfffffffcL
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK   0x000000ffL
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK  0x000000ffL
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK           0x0000ffffL
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK          0x0000ffffL
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK         0xffffffffL
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK        0xffffffffL
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr_MASK                      0x00000040L
+#define TCF_DEBUG__not_MH_TC_rtr                           0x00000040L
+#define TCF_DEBUG__TC_MH_send_MASK                         0x00000080L
+#define TCF_DEBUG__TC_MH_send                              0x00000080L
+#define TCF_DEBUG__not_FG0_rtr_MASK                        0x00000100L
+#define TCF_DEBUG__not_FG0_rtr                             0x00000100L
+#define TCF_DEBUG__not_TCB_TCO_rtr_MASK                    0x00001000L
+#define TCF_DEBUG__not_TCB_TCO_rtr                         0x00001000L
+#define TCF_DEBUG__TCB_ff_stall_MASK                       0x00002000L
+#define TCF_DEBUG__TCB_ff_stall                            0x00002000L
+#define TCF_DEBUG__TCB_miss_stall_MASK                     0x00004000L
+#define TCF_DEBUG__TCB_miss_stall                          0x00004000L
+#define TCF_DEBUG__TCA_TCB_stall_MASK                      0x00008000L
+#define TCF_DEBUG__TCA_TCB_stall                           0x00008000L
+#define TCF_DEBUG__PF0_stall_MASK                          0x00010000L
+#define TCF_DEBUG__PF0_stall                               0x00010000L
+#define TCF_DEBUG__TP0_full_MASK                           0x00100000L
+#define TCF_DEBUG__TP0_full                                0x00100000L
+#define TCF_DEBUG__TPC_full_MASK                           0x01000000L
+#define TCF_DEBUG__TPC_full                                0x01000000L
+#define TCF_DEBUG__not_TPC_rtr_MASK                        0x02000000L
+#define TCF_DEBUG__not_TPC_rtr                             0x02000000L
+#define TCF_DEBUG__tca_state_rts_MASK                      0x04000000L
+#define TCF_DEBUG__tca_state_rts                           0x04000000L
+#define TCF_DEBUG__tca_rts_MASK                            0x08000000L
+#define TCF_DEBUG__tca_rts                                 0x08000000L
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full_MASK                      0x00000001L
+#define TCA_FIFO_DEBUG__tp0_full                           0x00000001L
+#define TCA_FIFO_DEBUG__tpc_full_MASK                      0x00000010L
+#define TCA_FIFO_DEBUG__tpc_full                           0x00000010L
+#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK                 0x00000020L
+#define TCA_FIFO_DEBUG__load_tpc_fifo                      0x00000020L
+#define TCA_FIFO_DEBUG__load_tp_fifos_MASK                 0x00000040L
+#define TCA_FIFO_DEBUG__load_tp_fifos                      0x00000040L
+#define TCA_FIFO_DEBUG__FW_full_MASK                       0x00000080L
+#define TCA_FIFO_DEBUG__FW_full                            0x00000080L
+#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK                   0x00000100L
+#define TCA_FIFO_DEBUG__not_FW_rtr0                        0x00000100L
+#define TCA_FIFO_DEBUG__FW_rts0_MASK                       0x00001000L
+#define TCA_FIFO_DEBUG__FW_rts0                            0x00001000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK                0x00010000L
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr                     0x00010000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK                    0x00020000L
+#define TCA_FIFO_DEBUG__FW_tpc_rts                         0x00020000L
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK            0x00000001L
+#define TCA_PROBE_DEBUG__ProbeFilter_stall                 0x00000001L
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts_MASK               0x00001000L
+#define TCA_TPC_DEBUG__captue_state_rts                    0x00001000L
+#define TCA_TPC_DEBUG__capture_tca_rts_MASK                0x00002000L
+#define TCA_TPC_DEBUG__capture_tca_rts                     0x00002000L
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512_MASK                     0x00000001L
+#define TCB_CORE_DEBUG__access512                          0x00000001L
+#define TCB_CORE_DEBUG__tiled_MASK                         0x00000002L
+#define TCB_CORE_DEBUG__tiled                              0x00000002L
+#define TCB_CORE_DEBUG__opcode_MASK                        0x00000070L
+#define TCB_CORE_DEBUG__format_MASK                        0x00003f00L
+#define TCB_CORE_DEBUG__sector_format_MASK                 0x001f0000L
+#define TCB_CORE_DEBUG__sector_format512_MASK              0x07000000L
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG0_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG0_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG0_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG0_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG0_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG1_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG1_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG1_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG1_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG1_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG2_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG2_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG2_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG2_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG2_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle_MASK                0x000003ffL
+#define TCB_TAG3_DEBUG__tag_access_cycle_MASK              0x001ff000L
+#define TCB_TAG3_DEBUG__miss_stall_MASK                    0x00800000L
+#define TCB_TAG3_DEBUG__miss_stall                         0x00800000L
+#define TCB_TAG3_DEBUG__num_feee_lines_MASK                0x1f000000L
+#define TCB_TAG3_DEBUG__max_misses_MASK                    0xe0000000L
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done      0x00000001L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left    0x00000040L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q   0x10000000L
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK     0x00000030L
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK      0x000000c0L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK     0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left          0x00000800L
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK     0x00007000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK              0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy                   0x00008000L
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK  0x000f0000L
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK        0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts             0x00000001L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK         0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts              0x00000004L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK      0x0000fff0L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK   0x001f0000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK               0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy                    0x00800000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK           0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy                0x01000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK            0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy                 0x02000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK           0x0c000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK            0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q                 0x10000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK            0x40000000L
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR                 0x40000000L
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty_MASK                       0x00010000L
+#define TCD_INPUT0_DEBUG__empty                            0x00010000L
+#define TCD_INPUT0_DEBUG__full_MASK                        0x00020000L
+#define TCD_INPUT0_DEBUG__full                             0x00020000L
+#define TCD_INPUT0_DEBUG__valid_q1_MASK                    0x00100000L
+#define TCD_INPUT0_DEBUG__valid_q1                         0x00100000L
+#define TCD_INPUT0_DEBUG__cnt_q1_MASK                      0x00600000L
+#define TCD_INPUT0_DEBUG__last_send_q1_MASK                0x00800000L
+#define TCD_INPUT0_DEBUG__last_send_q1                     0x00800000L
+#define TCD_INPUT0_DEBUG__ip_send_MASK                     0x01000000L
+#define TCD_INPUT0_DEBUG__ip_send                          0x01000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK              0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send                   0x02000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK                  0x04000000L
+#define TCD_INPUT0_DEBUG__ipbuf_busy                       0x04000000L
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK        0x00000003L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK            0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8                 0x00000004L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK        0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send             0x00000008L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK             0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send                  0x00000010L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK                 0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_stall                      0x00000020L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK                0x00000040L
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate                     0x00000040L
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK               0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate                    0x00000200L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK           0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr                0x00000400L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK             0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr                  0x00000800L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send      0x00008000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK  0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts       0x00010000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK    0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send         0x00100000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send     0x08000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK     0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send          0x10000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK        0x20000000L
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send             0x20000000L
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK                  0x00000010L
+#define TCD_DXTC_ARB_DEBUG__n0_stall                       0x00000010L
+#define TCD_DXTC_ARB_DEBUG__pstate_MASK                    0x00000020L
+#define TCD_DXTC_ARB_DEBUG__pstate                         0x00000020L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK      0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send           0x00000040L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK            0x00000180L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK         0x00000e00L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK      0x0003f000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK         0x3ffc0000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK           0x40000000L
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send                0x40000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK           0x80000000L
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types                0x80000000L
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK     0x00000400L
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr          0x00000400L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK     0x00000800L
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr          0x00000800L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK           0x00020000L
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr                0x00020000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK         0x00040000L
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr              0x00040000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK            0x00080000L
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr                 0x00080000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK            0x80000000L
+#define TCD_STALLS_DEBUG__not_incoming_rtr                 0x80000000L
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK            0x00000020L
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR                 0x00000020L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK             0x00000040L
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR                  0x00000040L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK         0x00000080L
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d              0x00000080L
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK         0x000000ffL
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK         0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample              0x00000100L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK                   0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr                        0x00000200L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK                   0x00000400L
+#define TCO_QUAD0_DEBUG0__rl_sg_rts                        0x00000400L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK        0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample             0x00000800L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK                  0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr                       0x00001000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK                  0x00002000L
+#define TCO_QUAD0_DEBUG0__sg_crd_rts                       0x00002000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK             0x00010000L
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q                  0x00010000L
+#define TCO_QUAD0_DEBUG0__read_cache_q_MASK                0x01000000L
+#define TCO_QUAD0_DEBUG0__read_cache_q                     0x01000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK              0x02000000L
+#define TCO_QUAD0_DEBUG0__cache_read_RTR                   0x02000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK    0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3         0x04000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK    0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2         0x08000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK    0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1         0x10000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK    0x20000000L
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0         0x20000000L
+#define TCO_QUAD0_DEBUG0__busy_MASK                        0x40000000L
+#define TCO_QUAD0_DEBUG0__busy                             0x40000000L
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy_MASK                   0x00000001L
+#define TCO_QUAD0_DEBUG1__fifo_busy                        0x00000001L
+#define TCO_QUAD0_DEBUG1__empty_MASK                       0x00000002L
+#define TCO_QUAD0_DEBUG1__empty                            0x00000002L
+#define TCO_QUAD0_DEBUG1__full_MASK                        0x00000004L
+#define TCO_QUAD0_DEBUG1__full                             0x00000004L
+#define TCO_QUAD0_DEBUG1__write_enable_MASK                0x00000008L
+#define TCO_QUAD0_DEBUG1__write_enable                     0x00000008L
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK              0x000007f0L
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK               0x0003f800L
+#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK             0x00100000L
+#define TCO_QUAD0_DEBUG1__cache_read_busy                  0x00100000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK           0x00200000L
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy                0x00200000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK             0x00400000L
+#define TCO_QUAD0_DEBUG1__input_quad_busy                  0x00400000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK          0x00800000L
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy               0x00800000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK               0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d                    0x01000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK               0x02000000L
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q                    0x02000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK                   0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr                        0x04000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK                   0x08000000L
+#define TCO_QUAD0_DEBUG1__rl_sg_rts                        0x08000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK                  0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr                       0x10000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK                  0x20000000L
+#define TCO_QUAD0_DEBUG1__sg_crd_rts                       0x20000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK            0x40000000L
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc                 0x40000000L
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK                0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC                     0x00000001L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK               0x000007f0L
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK               0x0007f000L
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK     0x00000003L
+#define SQ_FLOW_CONTROL__ONE_THREAD_MASK                   0x00000010L
+#define SQ_FLOW_CONTROL__ONE_THREAD                        0x00000010L
+#define SQ_FLOW_CONTROL__ONE_ALU_MASK                      0x00000100L
+#define SQ_FLOW_CONTROL__ONE_ALU                           0x00000100L
+#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK                   0x0000f000L
+#define SQ_FLOW_CONTROL__NO_PV_PS_MASK                     0x00010000L
+#define SQ_FLOW_CONTROL__NO_PV_PS                          0x00010000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK                 0x00020000L
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT                      0x00020000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK            0x00040000L
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE                 0x00040000L
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK   0x00180000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK        0x00200000L
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY             0x00200000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK       0x00400000L
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY            0x00400000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK                 0x00800000L
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT                      0x00800000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK                 0x01000000L
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT                      0x01000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK             0x02000000L
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY                  0x02000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK  0x04000000L
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION       0x04000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK      0x08000000L
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC           0x08000000L
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK        0x00000fffL
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK        0x0fff0000L
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK     0x01ff0000L
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT_MASK                     0x000000ffL
+#define SQ_EO_RT__EO_TSTATE_RT_MASK                        0x00ff0000L
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK                 0x000007ffL
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK                 0x000ff000L
+#define SQ_DEBUG_MISC__DB_READ_CTX_MASK                    0x00100000L
+#define SQ_DEBUG_MISC__DB_READ_CTX                         0x00100000L
+#define SQ_DEBUG_MISC__RESERVED_MASK                       0x00600000L
+#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK                 0x01800000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK                0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0                     0x02000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK                0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1                     0x04000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK                0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2                     0x08000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK                0x10000000L
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3                     0x10000000L
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK              0x000000ffL
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK         0x0000ff00L
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK        0x00ff0000L
+#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK                 0xff000000L
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK        0x000000ffL
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK        0x00000007L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK          0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN               0x00000008L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK        0x00000070L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK          0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN               0x00000080L
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK              0x0003ff00L
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK       0x00000007L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK         0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN              0x00000008L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK       0x00000070L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK         0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN              0x00000080L
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK             0x0003ff00L
+#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK              0x000c0000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK  0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL       0x00100000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK  0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL       0x00200000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK                  0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__ENABLE                       0x00000001L
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK           0xfffffffeL
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK                 0x00000001L
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK                      0x00000001L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK                 0x00000002L
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK                      0x00000002L
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK            0x00000001L
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT                 0x00000001L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK            0x00000002L
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT                 0x00000002L
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK                   0x00000001L
+#define SQ_INT_ACK__PS_WATCHDOG_ACK                        0x00000001L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK                   0x00000002L
+#define SQ_INT_ACK__VS_WATCHDOG_ACK                        0x00000002L
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK                 0x00000007L
+#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK                  0x00000008L
+#define SQ_DEBUG_INPUT_FSM__RESERVED                       0x00000008L
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK                 0x000000f0L
+#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK                   0x00000700L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_INPUT_FSM__RESERVED1                      0x00000800L
+#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK                     0x00007000L
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK             0x000f8000L
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK               0x0ff00000L
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK             0x000000e0L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK             0x0000e000L
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK  0x00030000L
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK  0x000c0000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK  0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE       0x00100000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK  0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE       0x00200000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK  0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE       0x00400000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK  0x00800000L
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE       0x00800000L
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP_MASK                        0x00000007L
+#define SQ_DEBUG_TP_FSM__RESERVED0_MASK                    0x00000008L
+#define SQ_DEBUG_TP_FSM__RESERVED0                         0x00000008L
+#define SQ_DEBUG_TP_FSM__CF_TP_MASK                        0x000000f0L
+#define SQ_DEBUG_TP_FSM__IF_TP_MASK                        0x00000700L
+#define SQ_DEBUG_TP_FSM__RESERVED1_MASK                    0x00000800L
+#define SQ_DEBUG_TP_FSM__RESERVED1                         0x00000800L
+#define SQ_DEBUG_TP_FSM__TIS_TP_MASK                       0x00003000L
+#define SQ_DEBUG_TP_FSM__RESERVED2_MASK                    0x0000c000L
+#define SQ_DEBUG_TP_FSM__GS_TP_MASK                        0x00030000L
+#define SQ_DEBUG_TP_FSM__RESERVED3_MASK                    0x000c0000L
+#define SQ_DEBUG_TP_FSM__FCR_TP_MASK                       0x00300000L
+#define SQ_DEBUG_TP_FSM__RESERVED4_MASK                    0x00c00000L
+#define SQ_DEBUG_TP_FSM__FCS_TP_MASK                       0x03000000L
+#define SQ_DEBUG_TP_FSM__RESERVED5_MASK                    0x0c000000L
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK                    0x70000000L
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK                  0x00000007L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK                 0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0                      0x00000008L
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK                  0x000000f0L
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK                  0x00000700L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK                 0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1                      0x00000800L
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK                 0x00007000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK                 0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2                      0x00008000L
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK                 0x00070000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK                 0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3                      0x00080000L
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK                 0x00700000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK                 0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4                      0x00800000L
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK                 0x07000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK                 0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5                      0x08000000L
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK                0x70000000L
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK             0x0000000fL
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK           0x00000ff0L
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK              0x00007000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK                  0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__RESERVED                       0x00008000L
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK       0x003f0000L
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK              0x00000001L
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER                   0x00000001L
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK                0x0000001eL
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK            0x00000020L
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR                 0x00000020L
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK           0x000001c0L
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK                0x00003e00L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK                 0x00004000L
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT                      0x00004000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK          0x00008000L
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON               0x00008000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK                   0x00010000L
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY                        0x00010000L
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK               0x0ffe0000L
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_VTX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_VTX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_VTX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_VTX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK                0x0000007fL
+#define SQ_DEBUG_GPR_PIX__RESERVED_MASK                    0x00000080L
+#define SQ_DEBUG_GPR_PIX__RESERVED                         0x00000080L
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK                0x00007f00L
+#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK                   0x00008000L
+#define SQ_DEBUG_GPR_PIX__RESERVED1                        0x00008000L
+#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK                     0x007f0000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK                   0x00800000L
+#define SQ_DEBUG_GPR_PIX__RESERVED2                        0x00800000L
+#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK                    0x7f000000L
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN     0x00000800L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN     0x00001000L
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK     0x60000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC    0x80000000L
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK             0x0000000fL
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK                 0x000000f0L
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK                 0x00000f00L
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK          0x0000f000L
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK           0x000f0000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK              0x00100000L
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL                   0x00100000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK                     0x00200000L
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q                          0x00200000L
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK                0x0000ffffL
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK     0xffffffffL
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK       0xffffffffL
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK               0x0000003fL
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK                   0x00000fc0L
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK                   0x0007f000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK          0x01f80000L
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK            0x7e000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY_MASK                       0x80000000L
+#define SQ_DEBUG_PIX_TB_0__BUSY                            0x80000000L
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK   0xffffffffL
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK          0x00000040L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL               0x00000040L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK    0x00000080L
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP         0x00000080L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK          0x00004000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL               0x00004000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK             0x00008000L
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA                  0x00008000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK          0x000f0000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK          0x00f00000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK            0x01000000L
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP                 0x01000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK            0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP                 0x02000000L
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK           0xfc000000L
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK         0x00000003L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK         0x0000000cL
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK         0x00000030L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK         0x000000c0L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK         0x00000300L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK         0x00000c00L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK         0x00003000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK         0x0000c000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK         0x00030000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK         0x000c0000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK         0x00300000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK         0x00c00000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK           0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD                0x01000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK           0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD                0x02000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK           0x04000000L
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD                0x04000000L
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK             0x18000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK           0x20000000L
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR                0x20000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK         0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS              0x40000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK         0x80000000L
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS              0x80000000L
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK           0x0000003fL
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK            0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C                 0x00000040L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK           0x00000080L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C                0x00000080L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK           0x00003f00L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK            0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B                 0x00004000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK           0x00008000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B                0x00008000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK           0x003f0000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK            0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A                 0x00400000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK           0x00800000L
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A                0x00800000L
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK           0x1f000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK               0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL                    0x20000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK               0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL                    0x40000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK               0x80000000L
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK             0x000001ffL
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK            0x00000e00L
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK               0x00007000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK               0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD                    0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK         0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0              0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0            0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK         0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1              0x00040000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK       0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1            0x00080000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK         0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2              0x00100000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK       0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2            0x00200000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK         0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3              0x00400000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK       0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3            0x00800000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK         0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4              0x01000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK       0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4            0x02000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK         0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5              0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK       0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5            0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK           0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0                0x10000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK           0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1                0x20000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK           0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2                0x40000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK           0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3                0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK           0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4                0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK           0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5                0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK           0x000003fcL
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK           0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION                0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK             0x01ff0000L
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK            0x0e000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK               0x70000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK               0x80000000L
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD                    0x80000000L
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK         0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0              0x00000001L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0            0x00000002L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK         0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1              0x00000004L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK       0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1            0x00000008L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK         0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2              0x00000010L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK       0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2            0x00000020L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK         0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3              0x00000040L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK       0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3            0x00000080L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK         0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4              0x00000100L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK       0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4            0x00000200L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK         0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5              0x00000400L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK       0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5            0x00000800L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK           0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0                0x00001000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK           0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1                0x00002000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK           0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2                0x00004000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK           0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3                0x00008000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK           0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4                0x00010000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK           0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5                0x00020000L
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK           0x03fc0000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK           0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION                0x04000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK             0x000003ffL
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK          0x0000fc00L
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK             0x001f0000L
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK          0xffe00000L
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK          0x000007ffL
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK        0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE             0x00000800L
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK              0x0000f000L
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK             0x03ff0000L
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK          0xfc000000L
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK             0x0000001fL
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK            0x07ffffe0L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK        0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE             0x08000000L
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK              0xf0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK         0x000003ffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK      0x00001c00L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK      0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL           0x00002000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK  0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP       0x00004000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK      0xffff8000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK      0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0           0x00000001L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK       0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION            0x00000002L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK       0x000003fcL
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK       0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION            0x00000400L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK    0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE         0x00000800L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK          0x0000f000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK         0x03ff0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK      0x1c000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK      0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL           0x20000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK      0xc0000000L
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK        0x0001ffffL
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK       0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION            0x00020000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK       0x03fc0000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK       0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION            0x04000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK    0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE         0x08000000L
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK          0xf0000000L
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK               0x0000000fL
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK           0xfffffff0L
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK         0x000000ffL
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK          0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL               0x00000100L
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK      0x00000600L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK         0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE              0x00000800L
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK             0x0000f000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK               0x000f0000L
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK         0xfff00000L
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK           0x00ffffffL
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK          0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL               0x01000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK      0x06000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK         0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE              0x08000000L
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK             0xf0000000L
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK     0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY          0x00080000L
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK      0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM           0x02000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK            0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK            0x30000000L
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK            0xc0000000L
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK           0x00003000L
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK           0x0000c000L
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK           0x00030000L
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK         0x001c0000L
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK     0x00e00000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK       0x03000000L
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK       0x0c000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK         0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD              0x10000000L
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK          0x60000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK    0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS         0x00000001L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK      0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION           0x00000002L
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK             0x000001fcL
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK               0x0000fe00L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK             0x001f0000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK             0x03e00000L
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK             0x7c000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK               0x0000001fL
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK              0x000007e0L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK           0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM                0x00000800L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK              0x0003f000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK           0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM                0x00040000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK          0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE               0x00080000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK          0x01f00000L
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK      0x06000000L
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK              0xc0000000L
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK            0x00000007L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK            0x00000038L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK            0x000001c0L
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK            0x00000e00L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK      0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL           0x00001000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK       0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL            0x00002000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK   0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL        0x00004000L
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK          0x003f0000L
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK       0x3f800000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK          0x80000000L
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT               0x80000000L
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK               0x000000ffL
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK               0x00ff0000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK       0x80000000L
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION            0x80000000L
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED_MASK                            0xffffffffL
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN_MASK                          0xffffffffL
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE_MASK                           0xffffffffL
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA_MASK                          0xffffffffL
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE_MASK                             0xffffffffL
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE_MASK                             0xffffffffL
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE_MASK                    0x00000001L
+#define SQ_CONSTANT_VFETCH_0__TYPE                         0x00000001L
+#define SQ_CONSTANT_VFETCH_0__STATE_MASK                   0x00000002L
+#define SQ_CONSTANT_VFETCH_0__STATE                        0x00000002L
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK            0xfffffffcL
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK             0x00000003L
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK           0xfffffffcL
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE_MASK                         0xffffffffL
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE_MASK                         0xffffffffL
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK                 0x000000ffL
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK                 0x0000ff00L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK                 0x00ff0000L
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK                 0xff000000L
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK                     0x000000ffL
+#define SQ_CF_LOOP__CF_LOOP_START_MASK                     0x0000ff00L
+#define SQ_CF_LOOP__CF_LOOP_STEP_MASK                      0x00ff0000L
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED_MASK                         0xffffffffL
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN_MASK                       0xffffffffL
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE_MASK                        0xffffffffL
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA_MASK                       0xffffffffL
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE_MASK                          0xffffffffL
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE_MASK                          0xffffffffL
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK              0x000000ffL
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK              0x0000ff00L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK              0x00ff0000L
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK              0xff000000L
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK                  0x000000ffL
+#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK                  0x0000ff00L
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK                   0x00ff0000L
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_VS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE_MASK                           0x00000fffL
+#define SQ_PS_PROGRAM__SIZE_MASK                           0x00fff000L
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK                0x000007ffL
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK                0x007ff000L
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK             0x0000ffffL
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK        0xffff0000L
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK                   0x0000003fL
+#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK                   0x00003f00L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK                  0x00010000L
+#define SQ_PROGRAM_CNTL__VS_RESOURCE                       0x00010000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK                  0x00020000L
+#define SQ_PROGRAM_CNTL__PS_RESOURCE                       0x00020000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK                    0x00040000L
+#define SQ_PROGRAM_CNTL__PARAM_GEN                         0x00040000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK                0x00080000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX                     0x00080000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK              0x00f00000L
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK               0x07000000L
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK               0x78000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK                0x80000000L
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX                     0x80000000L
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK                   0x0000000fL
+#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK                   0x000000f0L
+#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK                   0x00000f00L
+#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK                   0x0000f000L
+#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK                   0x000f0000L
+#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK                   0x00f00000L
+#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK                   0x0f000000L
+#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK                   0xf0000000L
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK                   0x0000000fL
+#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK                   0x000000f0L
+#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK                  0x00000f00L
+#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK                  0x0000f000L
+#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK                  0x000f0000L
+#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK                  0x00f00000L
+#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK                  0x0f000000L
+#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK                  0xf0000000L
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_VS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE_MASK                             0x000001ffL
+#define SQ_PS_CONST__SIZE_MASK                             0x001ff000L
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK           0x00000001L
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE                0x00000001L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK          0x00000002L
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY               0x00000002L
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK               0x0000000cL
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK                0x0000ff00L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK              0x00010000L
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF                   0x00010000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK               0x00020000L
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE                    0x00020000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK                 0x00040000L
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL                      0x00040000L
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE_MASK                        0x00000007L
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK                   0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_ON                        0x00000001L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK                0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK                     0x00000010L
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK                 0x0007ff00L
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK                0xff000000L
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK                    0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_PIX                         0x00000001L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK                    0x00000002L
+#define SQ_DEBUG_MISC_1__DB_ON_VTX                         0x00000002L
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK                0x0000ff00L
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK                0x07ff0000L
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK            0x0000003fL
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK      0x00000040L
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY           0x00000040L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK              0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE                   0x00000080L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK         0x00000100L
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE              0x00000100L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK             0x00000200L
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL                  0x00000200L
+#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK                  0x00001c00L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK          0x00002000L
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE               0x00002000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK         0x00004000L
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE              0x00004000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK     0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE          0x00008000L
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK            0x003f0000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK             0x00400000L
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE                  0x00400000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK            0x00800000L
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE                 0x00800000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK             0x01000000L
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE                  0x01000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK             0x02000000L
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE                  0x02000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK             0x04000000L
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE                  0x04000000L
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK                  0x00000007L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK               0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1                    0x00000008L
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK                  0x00000070L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK               0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2                    0x00000080L
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK                 0x00000700L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK               0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3                    0x00000800L
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK                  0x00007000L
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK             0x00000001L
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR                  0x00000001L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK            0x00000002L
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR                 0x00000002L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK             0x00000004L
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT                  0x00000004L
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK           0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR                0x00000001L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK          0x00000002L
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR               0x00000002L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK           0x00000004L
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT                0x00000004L
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK            0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR                 0x00000001L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK           0x00000002L
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR                0x00000002L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK            0x00000004L
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT                 0x00000004L
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID_MASK                     0x00000007L
+#define MH_AXI_ERROR__AXI_READ_ERROR_MASK                  0x00000008L
+#define MH_AXI_ERROR__AXI_READ_ERROR                       0x00000008L
+#define MH_AXI_ERROR__AXI_WRITE_ID_MASK                    0x00000070L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK                 0x00000080L
+#define MH_AXI_ERROR__AXI_WRITE_ERROR                      0x00000080L
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK               0x000000ffL
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK         0xffffffffL
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK           0x0000ffffL
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX_MASK                          0x0000003fL
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA_MASK                           0xffffffffL
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK                 0x00000001L
+#define MH_AXI_HALT_CONTROL__AXI_HALT                      0x00000001L
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY_MASK                       0x00000001L
+#define MH_DEBUG_REG00__MH_BUSY                            0x00000001L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK             0x00000002L
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING                  0x00000002L
+#define MH_DEBUG_REG00__CP_REQUEST_MASK                    0x00000004L
+#define MH_DEBUG_REG00__CP_REQUEST                         0x00000004L
+#define MH_DEBUG_REG00__VGT_REQUEST_MASK                   0x00000008L
+#define MH_DEBUG_REG00__VGT_REQUEST                        0x00000008L
+#define MH_DEBUG_REG00__TC_REQUEST_MASK                    0x00000010L
+#define MH_DEBUG_REG00__TC_REQUEST                         0x00000010L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK                  0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_EMPTY                       0x00000020L
+#define MH_DEBUG_REG00__TC_CAM_FULL_MASK                   0x00000040L
+#define MH_DEBUG_REG00__TC_CAM_FULL                        0x00000040L
+#define MH_DEBUG_REG00__TCD_EMPTY_MASK                     0x00000080L
+#define MH_DEBUG_REG00__TCD_EMPTY                          0x00000080L
+#define MH_DEBUG_REG00__TCD_FULL_MASK                      0x00000100L
+#define MH_DEBUG_REG00__TCD_FULL                           0x00000100L
+#define MH_DEBUG_REG00__RB_REQUEST_MASK                    0x00000200L
+#define MH_DEBUG_REG00__RB_REQUEST                         0x00000200L
+#define MH_DEBUG_REG00__PA_REQUEST_MASK                    0x00000400L
+#define MH_DEBUG_REG00__PA_REQUEST                         0x00000400L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK               0x00000800L
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE                    0x00000800L
+#define MH_DEBUG_REG00__ARQ_EMPTY_MASK                     0x00001000L
+#define MH_DEBUG_REG00__ARQ_EMPTY                          0x00001000L
+#define MH_DEBUG_REG00__ARQ_FULL_MASK                      0x00002000L
+#define MH_DEBUG_REG00__ARQ_FULL                           0x00002000L
+#define MH_DEBUG_REG00__WDB_EMPTY_MASK                     0x00004000L
+#define MH_DEBUG_REG00__WDB_EMPTY                          0x00004000L
+#define MH_DEBUG_REG00__WDB_FULL_MASK                      0x00008000L
+#define MH_DEBUG_REG00__WDB_FULL                           0x00008000L
+#define MH_DEBUG_REG00__AXI_AVALID_MASK                    0x00010000L
+#define MH_DEBUG_REG00__AXI_AVALID                         0x00010000L
+#define MH_DEBUG_REG00__AXI_AREADY_MASK                    0x00020000L
+#define MH_DEBUG_REG00__AXI_AREADY                         0x00020000L
+#define MH_DEBUG_REG00__AXI_ARVALID_MASK                   0x00040000L
+#define MH_DEBUG_REG00__AXI_ARVALID                        0x00040000L
+#define MH_DEBUG_REG00__AXI_ARREADY_MASK                   0x00080000L
+#define MH_DEBUG_REG00__AXI_ARREADY                        0x00080000L
+#define MH_DEBUG_REG00__AXI_WVALID_MASK                    0x00100000L
+#define MH_DEBUG_REG00__AXI_WVALID                         0x00100000L
+#define MH_DEBUG_REG00__AXI_WREADY_MASK                    0x00200000L
+#define MH_DEBUG_REG00__AXI_WREADY                         0x00200000L
+#define MH_DEBUG_REG00__AXI_RVALID_MASK                    0x00400000L
+#define MH_DEBUG_REG00__AXI_RVALID                         0x00400000L
+#define MH_DEBUG_REG00__AXI_RREADY_MASK                    0x00800000L
+#define MH_DEBUG_REG00__AXI_RREADY                         0x00800000L
+#define MH_DEBUG_REG00__AXI_BVALID_MASK                    0x01000000L
+#define MH_DEBUG_REG00__AXI_BVALID                         0x01000000L
+#define MH_DEBUG_REG00__AXI_BREADY_MASK                    0x02000000L
+#define MH_DEBUG_REG00__AXI_BREADY                         0x02000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK                  0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_REQ                       0x04000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK                  0x08000000L
+#define MH_DEBUG_REG00__AXI_HALT_ACK                       0x08000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK                   0x10000000L
+#define MH_DEBUG_REG00__AXI_RDY_ENA                        0x10000000L
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q_MASK                     0x00000001L
+#define MH_DEBUG_REG01__CP_SEND_q                          0x00000001L
+#define MH_DEBUG_REG01__CP_RTR_q_MASK                      0x00000002L
+#define MH_DEBUG_REG01__CP_RTR_q                           0x00000002L
+#define MH_DEBUG_REG01__CP_WRITE_q_MASK                    0x00000004L
+#define MH_DEBUG_REG01__CP_WRITE_q                         0x00000004L
+#define MH_DEBUG_REG01__CP_TAG_q_MASK                      0x00000038L
+#define MH_DEBUG_REG01__CP_BLEN_q_MASK                     0x00000040L
+#define MH_DEBUG_REG01__CP_BLEN_q                          0x00000040L
+#define MH_DEBUG_REG01__VGT_SEND_q_MASK                    0x00000080L
+#define MH_DEBUG_REG01__VGT_SEND_q                         0x00000080L
+#define MH_DEBUG_REG01__VGT_RTR_q_MASK                     0x00000100L
+#define MH_DEBUG_REG01__VGT_RTR_q                          0x00000100L
+#define MH_DEBUG_REG01__VGT_TAG_q_MASK                     0x00000200L
+#define MH_DEBUG_REG01__VGT_TAG_q                          0x00000200L
+#define MH_DEBUG_REG01__TC_SEND_q_MASK                     0x00000400L
+#define MH_DEBUG_REG01__TC_SEND_q                          0x00000400L
+#define MH_DEBUG_REG01__TC_RTR_q_MASK                      0x00000800L
+#define MH_DEBUG_REG01__TC_RTR_q                           0x00000800L
+#define MH_DEBUG_REG01__TC_BLEN_q_MASK                     0x00001000L
+#define MH_DEBUG_REG01__TC_BLEN_q                          0x00001000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK                 0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q                      0x00002000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK                  0x00004000L
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q                       0x00004000L
+#define MH_DEBUG_REG01__TC_MH_written_MASK                 0x00008000L
+#define MH_DEBUG_REG01__TC_MH_written                      0x00008000L
+#define MH_DEBUG_REG01__RB_SEND_q_MASK                     0x00010000L
+#define MH_DEBUG_REG01__RB_SEND_q                          0x00010000L
+#define MH_DEBUG_REG01__RB_RTR_q_MASK                      0x00020000L
+#define MH_DEBUG_REG01__RB_RTR_q                           0x00020000L
+#define MH_DEBUG_REG01__PA_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG01__PA_SEND_q                          0x00040000L
+#define MH_DEBUG_REG01__PA_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG01__PA_RTR_q                           0x00080000L
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG02__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG02__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG02__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG02__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK                 0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_rlast                      0x00000008L
+#define MH_DEBUG_REG02__MH_CLNT_tag_MASK                   0x00000070L
+#define MH_DEBUG_REG02__RDC_RID_MASK                       0x00000380L
+#define MH_DEBUG_REG02__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG02__MH_CP_writeclean_MASK              0x00001000L
+#define MH_DEBUG_REG02__MH_CP_writeclean                   0x00001000L
+#define MH_DEBUG_REG02__MH_RB_writeclean_MASK              0x00002000L
+#define MH_DEBUG_REG02__MH_RB_writeclean                   0x00002000L
+#define MH_DEBUG_REG02__MH_PA_writeclean_MASK              0x00004000L
+#define MH_DEBUG_REG02__MH_PA_writeclean                   0x00004000L
+#define MH_DEBUG_REG02__BRC_BID_MASK                       0x00038000L
+#define MH_DEBUG_REG02__BRC_BRESP_MASK                     0x000c0000L
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK             0xffffffffL
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK            0xffffffffL
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG05__CP_MH_send                         0x00000001L
+#define MH_DEBUG_REG05__CP_MH_write_MASK                   0x00000002L
+#define MH_DEBUG_REG05__CP_MH_write                        0x00000002L
+#define MH_DEBUG_REG05__CP_MH_tag_MASK                     0x0000001cL
+#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK                 0xffffffe0L
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be_MASK                      0x000000ffL
+#define MH_DEBUG_REG08__RB_MH_be_MASK                      0x0000ff00L
+#define MH_DEBUG_REG08__PA_MH_be_MASK                      0x00ff0000L
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK                   0x00000007L
+#define MH_DEBUG_REG09__VGT_MH_send_MASK                   0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_send                        0x00000008L
+#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK                  0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_tagbe                       0x00000010L
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK                0xffffffe0L
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG10__TC_MH_send_MASK                    0x00000004L
+#define MH_DEBUG_REG10__TC_MH_send                         0x00000004L
+#define MH_DEBUG_REG10__TC_MH_mask_MASK                    0x00000018L
+#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info_MASK                    0x01ffffffL
+#define MH_DEBUG_REG11__TC_MH_send_MASK                    0x02000000L
+#define MH_DEBUG_REG11__TC_MH_send                         0x02000000L
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK                  0x01ffffffL
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK             0x02000000L
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send                  0x02000000L
+#define MH_DEBUG_REG12__TC_MH_written_MASK                 0x04000000L
+#define MH_DEBUG_REG12__TC_MH_written                      0x04000000L
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK                   0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_SEND                        0x00000004L
+#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK                   0x00000018L
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK              0xffffffe0L
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK                   0x01ffffffL
+#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK                   0x02000000L
+#define MH_DEBUG_REG14__TC_ROQ_SEND                        0x02000000L
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG15__RB_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG15__RB_MH_send                         0x00000010L
+#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK                   0x0000000fL
+#define MH_DEBUG_REG18__PA_MH_send_MASK                    0x00000010L
+#define MH_DEBUG_REG18__PA_MH_send                         0x00000010L
+#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK               0xffffffe0L
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK               0xffffffffL
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK              0xffffffffL
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG21__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG21__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG21__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG21__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG21__ALEN_q_2_0_MASK                    0x000000e0L
+#define MH_DEBUG_REG21__ARVALID_q_MASK                     0x00000100L
+#define MH_DEBUG_REG21__ARVALID_q                          0x00000100L
+#define MH_DEBUG_REG21__ARREADY_q_MASK                     0x00000200L
+#define MH_DEBUG_REG21__ARREADY_q                          0x00000200L
+#define MH_DEBUG_REG21__ARID_q_MASK                        0x00001c00L
+#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK                   0x00006000L
+#define MH_DEBUG_REG21__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG21__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG21__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG21__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG21__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG21__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG21__RID_q_MASK                         0x001c0000L
+#define MH_DEBUG_REG21__WVALID_q_MASK                      0x00200000L
+#define MH_DEBUG_REG21__WVALID_q                           0x00200000L
+#define MH_DEBUG_REG21__WREADY_q_MASK                      0x00400000L
+#define MH_DEBUG_REG21__WREADY_q                           0x00400000L
+#define MH_DEBUG_REG21__WLAST_q_MASK                       0x00800000L
+#define MH_DEBUG_REG21__WLAST_q                            0x00800000L
+#define MH_DEBUG_REG21__WID_q_MASK                         0x07000000L
+#define MH_DEBUG_REG21__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG21__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG21__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG21__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG21__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q_MASK                      0x00000001L
+#define MH_DEBUG_REG22__AVALID_q                           0x00000001L
+#define MH_DEBUG_REG22__AREADY_q_MASK                      0x00000002L
+#define MH_DEBUG_REG22__AREADY_q                           0x00000002L
+#define MH_DEBUG_REG22__AID_q_MASK                         0x0000001cL
+#define MH_DEBUG_REG22__ALEN_q_1_0_MASK                    0x00000060L
+#define MH_DEBUG_REG22__ARVALID_q_MASK                     0x00000080L
+#define MH_DEBUG_REG22__ARVALID_q                          0x00000080L
+#define MH_DEBUG_REG22__ARREADY_q_MASK                     0x00000100L
+#define MH_DEBUG_REG22__ARREADY_q                          0x00000100L
+#define MH_DEBUG_REG22__ARID_q_MASK                        0x00000e00L
+#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK                   0x00001000L
+#define MH_DEBUG_REG22__ARLEN_q_1_1                        0x00001000L
+#define MH_DEBUG_REG22__WVALID_q_MASK                      0x00002000L
+#define MH_DEBUG_REG22__WVALID_q                           0x00002000L
+#define MH_DEBUG_REG22__WREADY_q_MASK                      0x00004000L
+#define MH_DEBUG_REG22__WREADY_q                           0x00004000L
+#define MH_DEBUG_REG22__WLAST_q_MASK                       0x00008000L
+#define MH_DEBUG_REG22__WLAST_q                            0x00008000L
+#define MH_DEBUG_REG22__WID_q_MASK                         0x00070000L
+#define MH_DEBUG_REG22__WSTRB_q_MASK                       0x07f80000L
+#define MH_DEBUG_REG22__BVALID_q_MASK                      0x08000000L
+#define MH_DEBUG_REG22__BVALID_q                           0x08000000L
+#define MH_DEBUG_REG22__BREADY_q_MASK                      0x10000000L
+#define MH_DEBUG_REG22__BREADY_q                           0x10000000L
+#define MH_DEBUG_REG22__BID_q_MASK                         0xe0000000L
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q                      0x00000001L
+#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK                   0x0000000eL
+#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK                  0xfffffff0L
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK                   0x00000003L
+#define MH_DEBUG_REG24__REG_A_MASK                         0x0000fffcL
+#define MH_DEBUG_REG24__REG_RE_MASK                        0x00010000L
+#define MH_DEBUG_REG24__REG_RE                             0x00010000L
+#define MH_DEBUG_REG24__REG_WE_MASK                        0x00020000L
+#define MH_DEBUG_REG24__REG_WE                             0x00020000L
+#define MH_DEBUG_REG24__BLOCK_RS_MASK                      0x00040000L
+#define MH_DEBUG_REG24__BLOCK_RS                           0x00040000L
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD_MASK                        0xffffffffL
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy_MASK                  0x00000001L
+#define MH_DEBUG_REG26__MH_RBBM_busy                       0x00000001L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK          0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int               0x00000002L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK         0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int              0x00000004L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK       0x00000008L
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int            0x00000008L
+#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK                   0x00000010L
+#define MH_DEBUG_REG26__GAT_CLK_ENA                        0x00000010L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK       0x00000020L
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override            0x00000020L
+#define MH_DEBUG_REG26__CNT_q_MASK                         0x00000fc0L
+#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK                   0x00001000L
+#define MH_DEBUG_REG26__TCD_EMPTY_q                        0x00001000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK                  0x00002000L
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY                       0x00002000L
+#define MH_DEBUG_REG26__MH_BUSY_d_MASK                     0x00004000L
+#define MH_DEBUG_REG26__MH_BUSY_d                          0x00004000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK                 0x00008000L
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY                      0x00008000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL   0x00010000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC    0x00020000L
+#define MH_DEBUG_REG26__CP_SEND_q_MASK                     0x00040000L
+#define MH_DEBUG_REG26__CP_SEND_q                          0x00040000L
+#define MH_DEBUG_REG26__CP_RTR_q_MASK                      0x00080000L
+#define MH_DEBUG_REG26__CP_RTR_q                           0x00080000L
+#define MH_DEBUG_REG26__VGT_SEND_q_MASK                    0x00100000L
+#define MH_DEBUG_REG26__VGT_SEND_q                         0x00100000L
+#define MH_DEBUG_REG26__VGT_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG26__VGT_RTR_q                          0x00200000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK                 0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q                      0x00400000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK              0x00800000L
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q                   0x00800000L
+#define MH_DEBUG_REG26__RB_SEND_q_MASK                     0x01000000L
+#define MH_DEBUG_REG26__RB_SEND_q                          0x01000000L
+#define MH_DEBUG_REG26__RB_RTR_q_MASK                      0x02000000L
+#define MH_DEBUG_REG26__RB_RTR_q                           0x02000000L
+#define MH_DEBUG_REG26__PA_SEND_q_MASK                     0x04000000L
+#define MH_DEBUG_REG26__PA_SEND_q                          0x04000000L
+#define MH_DEBUG_REG26__PA_RTR_q_MASK                      0x08000000L
+#define MH_DEBUG_REG26__PA_RTR_q                           0x08000000L
+#define MH_DEBUG_REG26__RDC_VALID_MASK                     0x10000000L
+#define MH_DEBUG_REG26__RDC_VALID                          0x10000000L
+#define MH_DEBUG_REG26__RDC_RLAST_MASK                     0x20000000L
+#define MH_DEBUG_REG26__RDC_RLAST                          0x20000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID_MASK                 0x40000000L
+#define MH_DEBUG_REG26__TLBMISS_VALID                      0x40000000L
+#define MH_DEBUG_REG26__BRC_VALID_MASK                     0x80000000L
+#define MH_DEBUG_REG26__BRC_VALID                          0x80000000L
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK                0x00000007L
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK           0x00000038L
+#define MH_DEBUG_REG27__EFF1_WINNER_MASK                   0x000001c0L
+#define MH_DEBUG_REG27__ARB_WINNER_MASK                    0x00000e00L
+#define MH_DEBUG_REG27__ARB_WINNER_q_MASK                  0x00007000L
+#define MH_DEBUG_REG27__EFF1_WIN_MASK                      0x00008000L
+#define MH_DEBUG_REG27__EFF1_WIN                           0x00008000L
+#define MH_DEBUG_REG27__KILL_EFF1_MASK                     0x00010000L
+#define MH_DEBUG_REG27__KILL_EFF1                          0x00010000L
+#define MH_DEBUG_REG27__ARB_HOLD_MASK                      0x00020000L
+#define MH_DEBUG_REG27__ARB_HOLD                           0x00020000L
+#define MH_DEBUG_REG27__ARB_RTR_q_MASK                     0x00040000L
+#define MH_DEBUG_REG27__ARB_RTR_q                          0x00040000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK                  0x00080000L
+#define MH_DEBUG_REG27__CP_SEND_QUAL                       0x00080000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK                 0x00100000L
+#define MH_DEBUG_REG27__VGT_SEND_QUAL                      0x00100000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK                  0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_QUAL                       0x00200000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK             0x00400000L
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL                  0x00400000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK                  0x00800000L
+#define MH_DEBUG_REG27__RB_SEND_QUAL                       0x00800000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK                  0x01000000L
+#define MH_DEBUG_REG27__PA_SEND_QUAL                       0x01000000L
+#define MH_DEBUG_REG27__ARB_QUAL_MASK                      0x02000000L
+#define MH_DEBUG_REG27__ARB_QUAL                           0x02000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK                   0x04000000L
+#define MH_DEBUG_REG27__CP_EFF1_REQ                        0x04000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK                  0x08000000L
+#define MH_DEBUG_REG27__VGT_EFF1_REQ                       0x08000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK                   0x10000000L
+#define MH_DEBUG_REG27__TC_EFF1_REQ                        0x10000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK                   0x20000000L
+#define MH_DEBUG_REG27__RB_EFF1_REQ                        0x20000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK                0x40000000L
+#define MH_DEBUG_REG27__TCD_NEARFULL_q                     0x40000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK                   0x80000000L
+#define MH_DEBUG_REG27__TCHOLD_IP_q                        0x80000000L
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER_MASK                   0x00000007L
+#define MH_DEBUG_REG28__ARB_WINNER_MASK                    0x00000038L
+#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK                  0x00000040L
+#define MH_DEBUG_REG28__CP_SEND_QUAL                       0x00000040L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK                 0x00000080L
+#define MH_DEBUG_REG28__VGT_SEND_QUAL                      0x00000080L
+#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK                  0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_QUAL                       0x00000100L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK             0x00000200L
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL                  0x00000200L
+#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK                  0x00000400L
+#define MH_DEBUG_REG28__RB_SEND_QUAL                       0x00000400L
+#define MH_DEBUG_REG28__ARB_QUAL_MASK                      0x00000800L
+#define MH_DEBUG_REG28__ARB_QUAL                           0x00000800L
+#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK                   0x00001000L
+#define MH_DEBUG_REG28__CP_EFF1_REQ                        0x00001000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK                  0x00002000L
+#define MH_DEBUG_REG28__VGT_EFF1_REQ                       0x00002000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK                   0x00004000L
+#define MH_DEBUG_REG28__TC_EFF1_REQ                        0x00004000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK                   0x00008000L
+#define MH_DEBUG_REG28__RB_EFF1_REQ                        0x00008000L
+#define MH_DEBUG_REG28__EFF1_WIN_MASK                      0x00010000L
+#define MH_DEBUG_REG28__EFF1_WIN                           0x00010000L
+#define MH_DEBUG_REG28__KILL_EFF1_MASK                     0x00020000L
+#define MH_DEBUG_REG28__KILL_EFF1                          0x00020000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK                0x00040000L
+#define MH_DEBUG_REG28__TCD_NEARFULL_q                     0x00040000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK                   0x00080000L
+#define MH_DEBUG_REG28__TC_ARB_HOLD                        0x00080000L
+#define MH_DEBUG_REG28__ARB_HOLD_MASK                      0x00100000L
+#define MH_DEBUG_REG28__ARB_HOLD                           0x00100000L
+#define MH_DEBUG_REG28__ARB_RTR_q_MASK                     0x00200000L
+#define MH_DEBUG_REG28__ARB_RTR_q                          0x00200000L
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK       0xffc00000L
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK           0x00000007L
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK          0x00000038L
+#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK                0x000001c0L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK         0x00000200L
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d              0x00000200L
+#define MH_DEBUG_REG29__ARB_HOLD_MASK                      0x00000400L
+#define MH_DEBUG_REG29__ARB_HOLD                           0x00000400L
+#define MH_DEBUG_REG29__ARB_RTR_q_MASK                     0x00000800L
+#define MH_DEBUG_REG29__ARB_RTR_q                          0x00000800L
+#define MH_DEBUG_REG29__CLNT_REQ_MASK                      0x0001f000L
+#define MH_DEBUG_REG29__RECENT_d_0_MASK                    0x000e0000L
+#define MH_DEBUG_REG29__RECENT_d_1_MASK                    0x00700000L
+#define MH_DEBUG_REG29__RECENT_d_2_MASK                    0x03800000L
+#define MH_DEBUG_REG29__RECENT_d_3_MASK                    0x1c000000L
+#define MH_DEBUG_REG29__RECENT_d_4_MASK                    0xe0000000L
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK                   0x00000001L
+#define MH_DEBUG_REG30__TC_ARB_HOLD                        0x00000001L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK        0x00000002L
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK             0x00000002L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK          0x00000004L
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK               0x00000004L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK                0x00000008L
+#define MH_DEBUG_REG30__TCD_NEARFULL_q                     0x00000008L
+#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK                   0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_IP_q                        0x00000010L
+#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK                  0x000000e0L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK              0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q                   0x00000200L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK                 0x00000400L
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q                      0x00000400L
+#define MH_DEBUG_REG30__TC_MH_written_MASK                 0x00000800L
+#define MH_DEBUG_REG30__TC_MH_written                      0x00000800L
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK            0x0007f000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK                 0x00080000L
+#define MH_DEBUG_REG30__WBURST_ACTIVE                      0x00080000L
+#define MH_DEBUG_REG30__WLAST_q_MASK                       0x00100000L
+#define MH_DEBUG_REG30__WLAST_q                            0x00100000L
+#define MH_DEBUG_REG30__WBURST_IP_q_MASK                   0x00200000L
+#define MH_DEBUG_REG30__WBURST_IP_q                        0x00200000L
+#define MH_DEBUG_REG30__WBURST_CNT_q_MASK                  0x01c00000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK                  0x02000000L
+#define MH_DEBUG_REG30__CP_SEND_QUAL                       0x02000000L
+#define MH_DEBUG_REG30__CP_MH_write_MASK                   0x04000000L
+#define MH_DEBUG_REG30__CP_MH_write                        0x04000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK                  0x08000000L
+#define MH_DEBUG_REG30__RB_SEND_QUAL                       0x08000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK                  0x10000000L
+#define MH_DEBUG_REG30__PA_SEND_QUAL                       0x10000000L
+#define MH_DEBUG_REG30__ARB_WINNER_MASK                    0xe0000000L
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK           0x03ffffffL
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0x1c000000L
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG32__ROQ_MARK_q_MASK                    0x0000ff00L
+#define MH_DEBUG_REG32__ROQ_VALID_q_MASK                   0x00ff0000L
+#define MH_DEBUG_REG32__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG32__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG32__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG32__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG32__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG32__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK               0x000000ffL
+#define MH_DEBUG_REG33__ROQ_MARK_d_MASK                    0x0000ff00L
+#define MH_DEBUG_REG33__ROQ_VALID_d_MASK                   0x00ff0000L
+#define MH_DEBUG_REG33__TC_MH_send_MASK                    0x01000000L
+#define MH_DEBUG_REG33__TC_MH_send                         0x01000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK                  0x02000000L
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q                       0x02000000L
+#define MH_DEBUG_REG33__KILL_EFF1_MASK                     0x04000000L
+#define MH_DEBUG_REG33__KILL_EFF1                          0x04000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK      0x08000000L
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL           0x08000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK             0x10000000L
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK                  0x10000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK                  0x20000000L
+#define MH_DEBUG_REG33__TC_EFF1_QUAL                       0x20000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK                  0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY                       0x40000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK                   0x80000000L
+#define MH_DEBUG_REG33__TC_ROQ_FULL                        0x80000000L
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK             0x000000ffL
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK             0x0000ff00L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK         0x00ff0000L
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK         0xff000000L
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG35__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK                  0x00000004L
+#define MH_DEBUG_REG35__ROQ_MARK_q_0                       0x00000004L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK                 0x00000008L
+#define MH_DEBUG_REG35__ROQ_VALID_q_0                      0x00000008L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK             0x00000010L
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0                  0x00000010L
+#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG36__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK                  0x00000004L
+#define MH_DEBUG_REG36__ROQ_MARK_q_1                       0x00000004L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK                 0x00000008L
+#define MH_DEBUG_REG36__ROQ_VALID_q_1                      0x00000008L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK             0x00000010L
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1                  0x00000010L
+#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG37__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK                  0x00000004L
+#define MH_DEBUG_REG37__ROQ_MARK_q_2                       0x00000004L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK                 0x00000008L
+#define MH_DEBUG_REG37__ROQ_VALID_q_2                      0x00000008L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK             0x00000010L
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2                  0x00000010L
+#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG38__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK                  0x00000004L
+#define MH_DEBUG_REG38__ROQ_MARK_q_3                       0x00000004L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK                 0x00000008L
+#define MH_DEBUG_REG38__ROQ_VALID_q_3                      0x00000008L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK             0x00000010L
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3                  0x00000010L
+#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG39__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK                  0x00000004L
+#define MH_DEBUG_REG39__ROQ_MARK_q_4                       0x00000004L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK                 0x00000008L
+#define MH_DEBUG_REG39__ROQ_VALID_q_4                      0x00000008L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK             0x00000010L
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4                  0x00000010L
+#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG40__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK                  0x00000004L
+#define MH_DEBUG_REG40__ROQ_MARK_q_5                       0x00000004L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK                 0x00000008L
+#define MH_DEBUG_REG40__ROQ_VALID_q_5                      0x00000008L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK             0x00000010L
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5                  0x00000010L
+#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG41__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK                  0x00000004L
+#define MH_DEBUG_REG41__ROQ_MARK_q_6                       0x00000004L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK                 0x00000008L
+#define MH_DEBUG_REG41__ROQ_VALID_q_6                      0x00000008L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK             0x00000010L
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6                  0x00000010L
+#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send_MASK                    0x00000001L
+#define MH_DEBUG_REG42__TC_MH_send                         0x00000001L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK                  0x00000002L
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q                       0x00000002L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK                  0x00000004L
+#define MH_DEBUG_REG42__ROQ_MARK_q_7                       0x00000004L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK                 0x00000008L
+#define MH_DEBUG_REG42__ROQ_VALID_q_7                      0x00000008L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK             0x00000010L
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7                  0x00000010L
+#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK                    0xffffffe0L
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK                  0x00000001L
+#define MH_DEBUG_REG43__ARB_REG_WE_q                       0x00000001L
+#define MH_DEBUG_REG43__ARB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG43__ARB_WE                             0x00000002L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK               0x00000004L
+#define MH_DEBUG_REG43__ARB_REG_VALID_q                    0x00000004L
+#define MH_DEBUG_REG43__ARB_RTR_q_MASK                     0x00000008L
+#define MH_DEBUG_REG43__ARB_RTR_q                          0x00000008L
+#define MH_DEBUG_REG43__ARB_REG_RTR_MASK                   0x00000010L
+#define MH_DEBUG_REG43__ARB_REG_RTR                        0x00000010L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK                0x00000020L
+#define MH_DEBUG_REG43__WDAT_BURST_RTR                     0x00000020L
+#define MH_DEBUG_REG43__MMU_RTR_MASK                       0x00000040L
+#define MH_DEBUG_REG43__MMU_RTR                            0x00000040L
+#define MH_DEBUG_REG43__ARB_ID_q_MASK                      0x00000380L
+#define MH_DEBUG_REG43__ARB_WRITE_q_MASK                   0x00000400L
+#define MH_DEBUG_REG43__ARB_WRITE_q                        0x00000400L
+#define MH_DEBUG_REG43__ARB_BLEN_q_MASK                    0x00000800L
+#define MH_DEBUG_REG43__ARB_BLEN_q                         0x00000800L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK                0x00001000L
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY                     0x00001000L
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK                0x0000e000L
+#define MH_DEBUG_REG43__MMU_WE_MASK                        0x00010000L
+#define MH_DEBUG_REG43__MMU_WE                             0x00010000L
+#define MH_DEBUG_REG43__ARQ_RTR_MASK                       0x00020000L
+#define MH_DEBUG_REG43__ARQ_RTR                            0x00020000L
+#define MH_DEBUG_REG43__MMU_ID_MASK                        0x001c0000L
+#define MH_DEBUG_REG43__MMU_WRITE_MASK                     0x00200000L
+#define MH_DEBUG_REG43__MMU_WRITE                          0x00200000L
+#define MH_DEBUG_REG43__MMU_BLEN_MASK                      0x00400000L
+#define MH_DEBUG_REG43__MMU_BLEN                           0x00400000L
+#define MH_DEBUG_REG43__WBURST_IP_q_MASK                   0x00800000L
+#define MH_DEBUG_REG43__WBURST_IP_q                        0x00800000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK                 0x01000000L
+#define MH_DEBUG_REG43__WDAT_REG_WE_q                      0x01000000L
+#define MH_DEBUG_REG43__WDB_WE_MASK                        0x02000000L
+#define MH_DEBUG_REG43__WDB_WE                             0x02000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK                0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4                     0x04000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK                0x08000000L
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3                     0x08000000L
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG44__ARB_WE                             0x00000001L
+#define MH_DEBUG_REG44__ARB_ID_q_MASK                      0x0000000eL
+#define MH_DEBUG_REG44__ARB_VAD_q_MASK                     0xfffffff0L
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE_MASK                        0x00000001L
+#define MH_DEBUG_REG45__MMU_WE                             0x00000001L
+#define MH_DEBUG_REG45__MMU_ID_MASK                        0x0000000eL
+#define MH_DEBUG_REG45__MMU_PAD_MASK                       0xfffffff0L
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK                 0x00000001L
+#define MH_DEBUG_REG46__WDAT_REG_WE_q                      0x00000001L
+#define MH_DEBUG_REG46__WDB_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG46__WDB_WE                             0x00000002L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK              0x00000004L
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q                   0x00000004L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK                0x00000008L
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4                     0x00000008L
+#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK                   0x00000ff0L
+#define MH_DEBUG_REG46__ARB_WLAST_MASK                     0x00001000L
+#define MH_DEBUG_REG46__ARB_WLAST                          0x00001000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK                0x00002000L
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY                     0x00002000L
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK                0x0007c000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK                  0x00080000L
+#define MH_DEBUG_REG46__WDC_WDB_RE_q                       0x00080000L
+#define MH_DEBUG_REG46__WDB_WDC_WID_MASK                   0x00700000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK                 0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WLAST                      0x00800000L
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK                 0xff000000L
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK            0xffffffffL
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK           0xffffffffL
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK                0x00000001L
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY                     0x00000001L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK               0x00000002L
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY                    0x00000002L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK                0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY                     0x00000004L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK                0x00000008L
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE                     0x00000008L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK              0x00000010L
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS                   0x00000010L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK             0x00000020L
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q                  0x00000020L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK                 0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_q                      0x00000040L
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK             0x00001f80L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK                 0x00002000L
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q                      0x00002000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK                0x00004000L
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q                     0x00004000L
+#define MH_DEBUG_REG49__RVALID_q_MASK                      0x00008000L
+#define MH_DEBUG_REG49__RVALID_q                           0x00008000L
+#define MH_DEBUG_REG49__RREADY_q_MASK                      0x00010000L
+#define MH_DEBUG_REG49__RREADY_q                           0x00010000L
+#define MH_DEBUG_REG49__RLAST_q_MASK                       0x00020000L
+#define MH_DEBUG_REG49__RLAST_q                            0x00020000L
+#define MH_DEBUG_REG49__BVALID_q_MASK                      0x00040000L
+#define MH_DEBUG_REG49__BVALID_q                           0x00040000L
+#define MH_DEBUG_REG49__BREADY_q_MASK                      0x00080000L
+#define MH_DEBUG_REG49__BREADY_q                           0x00080000L
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send_MASK                0x00000001L
+#define MH_DEBUG_REG50__MH_CP_grb_send                     0x00000001L
+#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK               0x00000002L
+#define MH_DEBUG_REG50__MH_VGT_grb_send                    0x00000002L
+#define MH_DEBUG_REG50__MH_TC_mcsend_MASK                  0x00000004L
+#define MH_DEBUG_REG50__MH_TC_mcsend                       0x00000004L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK               0x00000008L
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND                    0x00000008L
+#define MH_DEBUG_REG50__TLBMISS_VALID_MASK                 0x00000010L
+#define MH_DEBUG_REG50__TLBMISS_VALID                      0x00000010L
+#define MH_DEBUG_REG50__RDC_VALID_MASK                     0x00000020L
+#define MH_DEBUG_REG50__RDC_VALID                          0x00000020L
+#define MH_DEBUG_REG50__RDC_RID_MASK                       0x000001c0L
+#define MH_DEBUG_REG50__RDC_RLAST_MASK                     0x00000200L
+#define MH_DEBUG_REG50__RDC_RLAST                          0x00000200L
+#define MH_DEBUG_REG50__RDC_RRESP_MASK                     0x00000c00L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK              0x00001000L
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS                   0x00001000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK             0x00002000L
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q                  0x00002000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK              0x00004000L
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q                   0x00004000L
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK       0x001f8000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK               0x00200000L
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE                    0x00200000L
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK          0x0fc00000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK                   0x10000000L
+#define MH_DEBUG_REG50__CNT_HOLD_q1                        0x10000000L
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK  0xe0000000L
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK             0xffffffffL
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK        0x00000003L
+#define MH_DEBUG_REG52__ARB_WE_MASK                        0x00000004L
+#define MH_DEBUG_REG52__ARB_WE                             0x00000004L
+#define MH_DEBUG_REG52__MMU_RTR_MASK                       0x00000008L
+#define MH_DEBUG_REG52__MMU_RTR                            0x00000008L
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK       0x03fffff0L
+#define MH_DEBUG_REG52__ARB_ID_q_MASK                      0x1c000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q_MASK                   0x20000000L
+#define MH_DEBUG_REG52__ARB_WRITE_q                        0x20000000L
+#define MH_DEBUG_REG52__client_behavior_q_MASK             0xc0000000L
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid_MASK                  0x00000001L
+#define MH_DEBUG_REG53__stage1_valid                       0x00000001L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK             0x00000002L
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q                  0x00000002L
+#define MH_DEBUG_REG53__pa_in_mpu_range_MASK               0x00000004L
+#define MH_DEBUG_REG53__pa_in_mpu_range                    0x00000004L
+#define MH_DEBUG_REG53__tag_match_q_MASK                   0x00000008L
+#define MH_DEBUG_REG53__tag_match_q                        0x00000008L
+#define MH_DEBUG_REG53__tag_miss_q_MASK                    0x00000010L
+#define MH_DEBUG_REG53__tag_miss_q                         0x00000010L
+#define MH_DEBUG_REG53__va_in_range_q_MASK                 0x00000020L
+#define MH_DEBUG_REG53__va_in_range_q                      0x00000020L
+#define MH_DEBUG_REG53__MMU_MISS_MASK                      0x00000040L
+#define MH_DEBUG_REG53__MMU_MISS                           0x00000040L
+#define MH_DEBUG_REG53__MMU_READ_MISS_MASK                 0x00000080L
+#define MH_DEBUG_REG53__MMU_READ_MISS                      0x00000080L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK                0x00000100L
+#define MH_DEBUG_REG53__MMU_WRITE_MISS                     0x00000100L
+#define MH_DEBUG_REG53__MMU_HIT_MASK                       0x00000200L
+#define MH_DEBUG_REG53__MMU_HIT                            0x00000200L
+#define MH_DEBUG_REG53__MMU_READ_HIT_MASK                  0x00000400L
+#define MH_DEBUG_REG53__MMU_READ_HIT                       0x00000400L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK                 0x00000800L
+#define MH_DEBUG_REG53__MMU_WRITE_HIT                      0x00000800L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK        0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS             0x00001000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK         0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT              0x00002000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK     0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS          0x00004000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK      0x00008000L
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT           0x00008000L
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK               0xffff0000L
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR_MASK                       0x00000001L
+#define MH_DEBUG_REG54__ARQ_RTR                            0x00000001L
+#define MH_DEBUG_REG54__MMU_WE_MASK                        0x00000002L
+#define MH_DEBUG_REG54__MMU_WE                             0x00000002L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK             0x00000004L
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q                  0x00000004L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK              0x00000008L
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS                   0x00000008L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK               0x00000010L
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND                    0x00000010L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH  0x00000020L
+#define MH_DEBUG_REG54__pa_in_mpu_range_MASK               0x00000040L
+#define MH_DEBUG_REG54__pa_in_mpu_range                    0x00000040L
+#define MH_DEBUG_REG54__stage1_valid_MASK                  0x00000080L
+#define MH_DEBUG_REG54__stage1_valid                       0x00000080L
+#define MH_DEBUG_REG54__stage2_valid_MASK                  0x00000100L
+#define MH_DEBUG_REG54__stage2_valid                       0x00000100L
+#define MH_DEBUG_REG54__client_behavior_q_MASK             0x00000600L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK             0x00000800L
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q                  0x00000800L
+#define MH_DEBUG_REG54__tag_match_q_MASK                   0x00001000L
+#define MH_DEBUG_REG54__tag_match_q                        0x00001000L
+#define MH_DEBUG_REG54__tag_miss_q_MASK                    0x00002000L
+#define MH_DEBUG_REG54__tag_miss_q                         0x00002000L
+#define MH_DEBUG_REG54__va_in_range_q_MASK                 0x00004000L
+#define MH_DEBUG_REG54__va_in_range_q                      0x00004000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK          0x00008000L
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q               0x00008000L
+#define MH_DEBUG_REG54__TAG_valid_q_MASK                   0xffff0000L
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG55__TAG_valid_q_0_MASK                 0x00002000L
+#define MH_DEBUG_REG55__TAG_valid_q_0                      0x00002000L
+#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG55__TAG1_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG55__TAG_valid_q_1_MASK                 0x20000000L
+#define MH_DEBUG_REG55__TAG_valid_q_1                      0x20000000L
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG56__TAG_valid_q_2_MASK                 0x00002000L
+#define MH_DEBUG_REG56__TAG_valid_q_2                      0x00002000L
+#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG56__TAG3_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG56__TAG_valid_q_3_MASK                 0x20000000L
+#define MH_DEBUG_REG56__TAG_valid_q_3                      0x20000000L
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG57__TAG_valid_q_4_MASK                 0x00002000L
+#define MH_DEBUG_REG57__TAG_valid_q_4                      0x00002000L
+#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG57__TAG5_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG57__TAG_valid_q_5_MASK                 0x20000000L
+#define MH_DEBUG_REG57__TAG_valid_q_5                      0x20000000L
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG58__TAG_valid_q_6_MASK                 0x00002000L
+#define MH_DEBUG_REG58__TAG_valid_q_6                      0x00002000L
+#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG58__TAG7_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG58__TAG_valid_q_7_MASK                 0x20000000L
+#define MH_DEBUG_REG58__TAG_valid_q_7                      0x20000000L
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA_MASK                       0x00001fffL
+#define MH_DEBUG_REG59__TAG_valid_q_8_MASK                 0x00002000L
+#define MH_DEBUG_REG59__TAG_valid_q_8                      0x00002000L
+#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG59__TAG9_VA_MASK                       0x1fff0000L
+#define MH_DEBUG_REG59__TAG_valid_q_9_MASK                 0x20000000L
+#define MH_DEBUG_REG59__TAG_valid_q_9                      0x20000000L
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG60__TAG_valid_q_10_MASK                0x00002000L
+#define MH_DEBUG_REG60__TAG_valid_q_10                     0x00002000L
+#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG60__TAG11_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG60__TAG_valid_q_11_MASK                0x20000000L
+#define MH_DEBUG_REG60__TAG_valid_q_11                     0x20000000L
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG61__TAG_valid_q_12_MASK                0x00002000L
+#define MH_DEBUG_REG61__TAG_valid_q_12                     0x00002000L
+#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG61__TAG13_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG61__TAG_valid_q_13_MASK                0x20000000L
+#define MH_DEBUG_REG61__TAG_valid_q_13                     0x20000000L
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA_MASK                      0x00001fffL
+#define MH_DEBUG_REG62__TAG_valid_q_14_MASK                0x00002000L
+#define MH_DEBUG_REG62__TAG_valid_q_14                     0x00002000L
+#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK                   0x0000c000L
+#define MH_DEBUG_REG62__TAG15_VA_MASK                      0x1fff0000L
+#define MH_DEBUG_REG62__TAG_valid_q_15_MASK                0x20000000L
+#define MH_DEBUG_REG62__TAG_valid_q_15                     0x20000000L
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK                0xffffffffL
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE_MASK                     0x00000001L
+#define MH_MMU_CONFIG__MMU_ENABLE                          0x00000001L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK              0x00000002L
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE                   0x00000002L
+#define MH_MMU_CONFIG__RESERVED1_MASK                      0x0000000cL
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK             0x00000030L
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK             0x000000c0L
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK            0x00000300L
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK            0x00000c00L
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK            0x00003000L
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK            0x0000c000L
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK            0x00030000L
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK           0x000c0000L
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK           0x00300000L
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK             0x00c00000L
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK             0x03000000L
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK             0x00000fffL
+#define MH_MMU_VA_RANGE__VA_BASE_MASK                      0xfffff000L
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE_MASK                       0xfffff000L
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK                 0x00000001L
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT                      0x00000001L
+#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK                    0x00000002L
+#define MH_MMU_PAGE_FAULT__OP_TYPE                         0x00000002L
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK              0x0000000cL
+#define MH_MMU_PAGE_FAULT__AXI_ID_MASK                     0x00000070L
+#define MH_MMU_PAGE_FAULT__RESERVED1_MASK                  0x00000080L
+#define MH_MMU_PAGE_FAULT__RESERVED1                       0x00000080L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK   0x00000100L
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE        0x00000100L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK       0x00000200L
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE            0x00000200L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK      0x00000400L
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR           0x00000400L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK     0x00000800L
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR          0x00000800L
+#define MH_MMU_PAGE_FAULT__REQ_VA_MASK                     0xfffff000L
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK                 0xffffffe0L
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK             0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL                  0x00000001L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK              0x00000002L
+#define MH_MMU_INVALIDATE__INVALIDATE_TC                   0x00000002L
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE_MASK                     0xfffff000L
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END_MASK                       0xfffff000L
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK                     0x00000002L
+#define WAIT_UNTIL__WAIT_RE_VSYNC                          0x00000002L
+#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK                     0x00000004L
+#define WAIT_UNTIL__WAIT_FE_VSYNC                          0x00000004L
+#define WAIT_UNTIL__WAIT_VSYNC_MASK                        0x00000008L
+#define WAIT_UNTIL__WAIT_VSYNC                             0x00000008L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK                    0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID0                         0x00000010L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK                    0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID1                         0x00000020L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK                    0x00000040L
+#define WAIT_UNTIL__WAIT_DSPLY_ID2                         0x00000040L
+#define WAIT_UNTIL__WAIT_CMDFIFO_MASK                      0x00000400L
+#define WAIT_UNTIL__WAIT_CMDFIFO                           0x00000400L
+#define WAIT_UNTIL__WAIT_2D_IDLE_MASK                      0x00004000L
+#define WAIT_UNTIL__WAIT_2D_IDLE                           0x00004000L
+#define WAIT_UNTIL__WAIT_3D_IDLE_MASK                      0x00008000L
+#define WAIT_UNTIL__WAIT_3D_IDLE                           0x00008000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK                 0x00010000L
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN                      0x00010000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK                 0x00020000L
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN                      0x00020000L
+#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK                   0x00f00000L
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK           0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI                0x00000010L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK      0x00000020L
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI           0x00000020L
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL_MASK                    0x0000001fL
+#define RBBM_STATUS__TC_BUSY_MASK                          0x00000020L
+#define RBBM_STATUS__TC_BUSY                               0x00000020L
+#define RBBM_STATUS__HIRQ_PENDING_MASK                     0x00000100L
+#define RBBM_STATUS__HIRQ_PENDING                          0x00000100L
+#define RBBM_STATUS__CPRQ_PENDING_MASK                     0x00000200L
+#define RBBM_STATUS__CPRQ_PENDING                          0x00000200L
+#define RBBM_STATUS__CFRQ_PENDING_MASK                     0x00000400L
+#define RBBM_STATUS__CFRQ_PENDING                          0x00000400L
+#define RBBM_STATUS__PFRQ_PENDING_MASK                     0x00000800L
+#define RBBM_STATUS__PFRQ_PENDING                          0x00000800L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK                  0x00001000L
+#define RBBM_STATUS__VGT_BUSY_NO_DMA                       0x00001000L
+#define RBBM_STATUS__RBBM_WU_BUSY_MASK                     0x00004000L
+#define RBBM_STATUS__RBBM_WU_BUSY                          0x00004000L
+#define RBBM_STATUS__CP_NRT_BUSY_MASK                      0x00010000L
+#define RBBM_STATUS__CP_NRT_BUSY                           0x00010000L
+#define RBBM_STATUS__MH_BUSY_MASK                          0x00040000L
+#define RBBM_STATUS__MH_BUSY                               0x00040000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK                0x00080000L
+#define RBBM_STATUS__MH_COHERENCY_BUSY                     0x00080000L
+#define RBBM_STATUS__SX_BUSY_MASK                          0x00200000L
+#define RBBM_STATUS__SX_BUSY                               0x00200000L
+#define RBBM_STATUS__TPC_BUSY_MASK                         0x00400000L
+#define RBBM_STATUS__TPC_BUSY                              0x00400000L
+#define RBBM_STATUS__SC_CNTX_BUSY_MASK                     0x01000000L
+#define RBBM_STATUS__SC_CNTX_BUSY                          0x01000000L
+#define RBBM_STATUS__PA_BUSY_MASK                          0x02000000L
+#define RBBM_STATUS__PA_BUSY                               0x02000000L
+#define RBBM_STATUS__VGT_BUSY_MASK                         0x04000000L
+#define RBBM_STATUS__VGT_BUSY                              0x04000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK                   0x08000000L
+#define RBBM_STATUS__SQ_CNTX17_BUSY                        0x08000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK                    0x10000000L
+#define RBBM_STATUS__SQ_CNTX0_BUSY                         0x10000000L
+#define RBBM_STATUS__RB_CNTX_BUSY_MASK                     0x40000000L
+#define RBBM_STATUS__RB_CNTX_BUSY                          0x40000000L
+#define RBBM_STATUS__GUI_ACTIVE_MASK                       0x80000000L
+#define RBBM_STATUS__GUI_ACTIVE                            0x80000000L
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK             0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0                  0x00000001L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK             0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1                  0x00000002L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK             0x00000004L
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2                  0x00000004L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK               0x00000008L
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID                    0x00000008L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK                0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0                     0x00000010L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK                0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1                     0x00000020L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK                0x00000040L
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2                     0x00000040L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK                   0x00000080L
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL                        0x00000080L
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK                  0x00000300L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK                0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0                     0x00000400L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK                0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1                     0x00000800L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK                0x00001000L
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2                     0x00001000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK                   0x00002000L
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL                        0x00002000L
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK                  0x0000c000L
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK                0x00030000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK                0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0                     0x00100000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK                0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1                     0x00200000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK                0x00400000L
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2                     0x00400000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK                   0x00800000L
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL                        0x00800000L
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK                  0x03000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK                0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0                     0x04000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK                0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1                     0x08000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK                0x10000000L
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2                     0x10000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK                   0x20000000L
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL                        0x20000000L
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK                  0xc0000000L
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK         0x00000003L
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK         0x00000300L
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK         0x00030000L
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK         0x03000000L
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST_MASK                  0xffffffffL
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK            0x0000ffffL
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK           0x00ff0000L
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK               0xff000000L
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK               0xffffffffL
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0_MASK                   0x000000ffL
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1_MASK                   0x0000000fL
+#define RBBM_PERIPHID1__DESIGNER0_MASK                     0x000000f0L
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1_MASK                     0x0000000fL
+#define RBBM_PERIPHID2__REVISION_MASK                      0x000000f0L
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK           0x00000003L
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK          0x0000000cL
+#define RBBM_PERIPHID3__MH_INTERFACE_MASK                  0x00000030L
+#define RBBM_PERIPHID3__CONTINUATION_MASK                  0x00000080L
+#define RBBM_PERIPHID3__CONTINUATION                       0x00000080L
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT_MASK                       0x000000ffL
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK               0x0001ff00L
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK            0x0000001fL
+#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK                    0x000003e0L
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK                0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_CP                     0x00000001L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK                0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_PA                     0x00000004L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK                0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_MH                     0x00000008L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK                0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_BC                     0x00000010L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK                0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ                     0x00000020L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK                0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_SX                     0x00000040L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK               0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB                    0x00001000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK                0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_SC                     0x00008000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK               0x00010000L
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT                    0x00010000L
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK    0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE         0x00000002L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK        0x00000004L
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE             0x00000004L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK    0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE         0x00000008L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK     0x00000010L
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE          0x00000010L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK    0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE         0x00000020L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK     0x00000100L
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE          0x00000100L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK        0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE             0x00000200L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK   0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE        0x00000800L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK   0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE        0x00001000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK   0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE        0x00002000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK   0x00004000L
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE        0x00004000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK   0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE        0x00008000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK   0x00010000L
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE        0x00010000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK   0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE        0x00020000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK   0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE        0x00040000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK     0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE          0x00100000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK    0x00200000L
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE         0x00200000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK      0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE           0x00400000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK    0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE         0x00800000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK  0x01000000L
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE       0x01000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK       0x02000000L
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE            0x02000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK    0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE         0x04000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK        0x08000000L
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE             0x08000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK     0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE          0x10000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK    0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE         0x20000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK    0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE         0x40000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK  0x80000000L
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000L
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK    0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE         0x00000001L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK     0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE          0x00000002L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK     0x00000004L
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE          0x00000004L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK   0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE        0x00000008L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE      0x00000010L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK   0x00000020L
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE        0x00000020L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE     0x00000040L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK      0x00000080L
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE           0x00000080L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK    0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE         0x00000100L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK    0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE         0x00000200L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK    0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE         0x00000400L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK    0x00000800L
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE         0x00000800L
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK                0x0000ffffL
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK             0x003f0000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK               0x01000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP                    0x01000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK                  0x02000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI                       0x02000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK      0x20000000L
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE           0x20000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK         0x40000000L
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE              0x40000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK             0x80000000L
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE                  0x80000000L
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK                   0x00000001L
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE                        0x00000001L
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK                 0xffffffffL
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK               0x0000003fL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK                0x00000f00L
+#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK                    0x00001000L
+#define RBBM_DEBUG_CNTL__SW_ENABLE                         0x00001000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK          0x003f0000L
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK           0x0f000000L
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK           0xf0000000L
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR_MASK                        0x00000002L
+#define RBBM_DEBUG__IGNORE_RTR                             0x00000002L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK                0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU                     0x00000004L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK             0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC                  0x00000008L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK             0x00000010L
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI                  0x00000010L
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK         0x00000f00L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK                 0x00010000L
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI                      0x00010000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK      0x00020000L
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI           0x00020000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK     0x00040000L
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI          0x00040000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK      0x00080000L
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI           0x00080000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK                    0x00100000L
+#define RBBM_DEBUG__CP_RBBM_NRTRTR                         0x00100000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK                   0x00200000L
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR                        0x00200000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK                    0x00400000L
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR                         0x00400000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK        0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI             0x00800000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK               0x01000000L
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR                    0x01000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK               0x80000000L
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY                    0x80000000L
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS_MASK                 0x0001fffcL
+#define RBBM_READ_ERROR__READ_REQUESTER_MASK               0x40000000L
+#define RBBM_READ_ERROR__READ_REQUESTER                    0x40000000L
+#define RBBM_READ_ERROR__READ_ERROR_MASK                   0x80000000L
+#define RBBM_READ_ERROR__READ_ERROR                        0x80000000L
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK   0x000000ffL
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK                 0x00000001L
+#define RBBM_INT_CNTL__RDERR_INT_MASK                      0x00000001L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK        0x00000002L
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK             0x00000002L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK              0x00080000L
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK                   0x00080000L
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK               0x00000001L
+#define RBBM_INT_STATUS__RDERR_INT_STAT                    0x00000001L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK      0x00000002L
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT           0x00000002L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK            0x00080000L
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT                 0x00080000L
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK_MASK                   0x00000001L
+#define RBBM_INT_ACK__RDERR_INT_ACK                        0x00000001L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK          0x00000002L
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK               0x00000002L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK                0x00080000L
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK                     0x00080000L
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK                0x00000020L
+#define MASTER_INT_SIGNAL__MH_INT_STAT                     0x00000020L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK                0x04000000L
+#define MASTER_INT_SIGNAL__SQ_INT_STAT                     0x04000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK                0x40000000L
+#define MASTER_INT_SIGNAL__CP_INT_STAT                     0x40000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK              0x80000000L
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT                   0x80000000L
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK     0x0000003fL
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK          0xffffffffL
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK          0x0000ffffL
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE_MASK                           0xffffffe0L
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ_MASK                          0x0000003fL
+#define CP_RB_CNTL__RB_BLKSZ_MASK                          0x00003f00L
+#define CP_RB_CNTL__BUF_SWAP_MASK                          0x00030000L
+#define CP_RB_CNTL__RB_POLL_EN_MASK                        0x00100000L
+#define CP_RB_CNTL__RB_POLL_EN                             0x00100000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK                      0x08000000L
+#define CP_RB_CNTL__RB_NO_UPDATE                           0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                    0x80000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA                         0x80000000L
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                 0xfffffffcL
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR_MASK                           0x000fffffL
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                     0x000fffffL
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR_MASK                           0x000fffffL
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK             0x0fffffffL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK             0xf0000000L
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK                 0x00000003L
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK                 0xfffffffcL
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE_MASK                         0xfffffffcL
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                       0x000fffffL
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE_MASK                         0xfffffffcL
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                       0x000fffffL
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE_MASK                           0xfffffffcL
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK                         0x000fffffL
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK            0x0000000fL
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK            0x00000f00L
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK             0x000f0000L
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END_MASK                    0x001f0000L
+#define CP_MEQ_THRESHOLDS__ROQ_END_MASK                    0x1f000000L
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK                    0x0000007fL
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK                     0x00007f00L
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK                     0x007f0000L
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST_MASK                      0x0000007fL
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK                         0x0000001fL
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK              0x0000007fL
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK              0x007f0000L
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK           0x0000007fL
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK           0x007f0000L
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK           0x0000007fL
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK           0x007f0000L
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK            0x00000007L
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK            0x00000700L
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK                   0x0000007fL
+#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK                   0x007f0000L
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR_MASK                         0x000003ffL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK                         0x03ff0000L
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK                   0x00000001L
+#define CP_MIU_TAG_STAT__TAG_0_STAT                        0x00000001L
+#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK                   0x00000002L
+#define CP_MIU_TAG_STAT__TAG_1_STAT                        0x00000002L
+#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK                   0x00000004L
+#define CP_MIU_TAG_STAT__TAG_2_STAT                        0x00000004L
+#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK                   0x00000008L
+#define CP_MIU_TAG_STAT__TAG_3_STAT                        0x00000008L
+#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK                   0x00000010L
+#define CP_MIU_TAG_STAT__TAG_4_STAT                        0x00000010L
+#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK                   0x00000020L
+#define CP_MIU_TAG_STAT__TAG_5_STAT                        0x00000020L
+#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK                   0x00000040L
+#define CP_MIU_TAG_STAT__TAG_6_STAT                        0x00000040L
+#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK                   0x00000080L
+#define CP_MIU_TAG_STAT__TAG_7_STAT                        0x00000080L
+#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK                   0x00000100L
+#define CP_MIU_TAG_STAT__TAG_8_STAT                        0x00000100L
+#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK                   0x00000200L
+#define CP_MIU_TAG_STAT__TAG_9_STAT                        0x00000200L
+#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK                  0x00000400L
+#define CP_MIU_TAG_STAT__TAG_10_STAT                       0x00000400L
+#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK                  0x00000800L
+#define CP_MIU_TAG_STAT__TAG_11_STAT                       0x00000800L
+#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK                  0x00001000L
+#define CP_MIU_TAG_STAT__TAG_12_STAT                       0x00001000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK                  0x00002000L
+#define CP_MIU_TAG_STAT__TAG_13_STAT                       0x00002000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK                  0x00004000L
+#define CP_MIU_TAG_STAT__TAG_14_STAT                       0x00004000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK                  0x00008000L
+#define CP_MIU_TAG_STAT__TAG_15_STAT                       0x00008000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK                  0x00010000L
+#define CP_MIU_TAG_STAT__TAG_16_STAT                       0x00010000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK                  0x00020000L
+#define CP_MIU_TAG_STAT__TAG_17_STAT                       0x00020000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK           0x80000000L
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG                0x80000000L
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX_MASK                       0x0000007fL
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                   0x00030000L
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA_MASK                         0xffffffffL
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX_MASK                        0x0000ffffL
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK            0x02000000L
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY                 0x02000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK            0x04000000L
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY                 0x04000000L
+#define CP_ME_CNTL__ME_HALT_MASK                           0x10000000L
+#define CP_ME_CNTL__ME_HALT                                0x10000000L
+#define CP_ME_CNTL__ME_BUSY_MASK                           0x20000000L
+#define CP_ME_CNTL__ME_BUSY                                0x20000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE_MASK                     0x80000000L
+#define CP_ME_CNTL__PROG_CNT_SIZE                          0x80000000L
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA_MASK                   0xffffffffL
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                 0x000003ffL
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                   0xffffffffL
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR_MASK                       0xffffffffL
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK             0x007fffffL
+#define CP_DEBUG__PREDICATE_DISABLE_MASK                   0x00800000L
+#define CP_DEBUG__PREDICATE_DISABLE                        0x00800000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK                 0x01000000L
+#define CP_DEBUG__PROG_END_PTR_ENABLE                      0x01000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK             0x02000000L
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE                  0x02000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK                  0x04000000L
+#define CP_DEBUG__PREFETCH_PASS_NOPS                       0x04000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK                 0x08000000L
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE                      0x08000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK              0x10000000L
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE                   0x10000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK              0x40000000L
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL                   0x40000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK              0x80000000L
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE                   0x80000000L
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK                0xffffffffL
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK                0xffffffffL
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK                0xffffffffL
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK                0xffffffffL
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK                0xffffffffL
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK                0xffffffffL
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK                0xffffffffL
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7_MASK                    0xffffffffL
+#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK                0xffffffffL
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK_MASK                    0x000000ffL
+#define SCRATCH_UMSK__SCRATCH_SWAP_MASK                    0x00030000L
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR_MASK                    0xffffffe0L
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM                    0x00000001L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR                   0x00000002L
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK               0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM                    0x00000001L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK              0x00000002L
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR                   0x00000002L
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK     0x00000003L
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK     0xfffffffcL
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK     0xffffffffL
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK               0x00000001L
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC                    0x00000001L
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK             0x00000003L
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK             0xfffffffcL
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK             0xffffffffL
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK                0x00000003L
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK                0xfffffffcL
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK                0xffffffffL
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK   0x00000001L
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR        0x00000001L
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK  0x00000003L
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK  0xfffffffcL
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK  0xffffffffL
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK_MASK                      0x00080000L
+#define CP_INT_CNTL__SW_INT_MASK                           0x00080000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK             0x00800000L
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK                  0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK                0x01000000L
+#define CP_INT_CNTL__OPCODE_ERROR_MASK                     0x01000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK        0x02000000L
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK             0x02000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK          0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK               0x04000000L
+#define CP_INT_CNTL__IB_ERROR_MASK_MASK                    0x08000000L
+#define CP_INT_CNTL__IB_ERROR_MASK                         0x08000000L
+#define CP_INT_CNTL__IB2_INT_MASK_MASK                     0x20000000L
+#define CP_INT_CNTL__IB2_INT_MASK                          0x20000000L
+#define CP_INT_CNTL__IB1_INT_MASK_MASK                     0x40000000L
+#define CP_INT_CNTL__IB1_INT_MASK                          0x40000000L
+#define CP_INT_CNTL__RB_INT_MASK_MASK                      0x80000000L
+#define CP_INT_CNTL__RB_INT_MASK                           0x80000000L
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT_MASK                    0x00080000L
+#define CP_INT_STATUS__SW_INT_STAT                         0x00080000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK           0x00800000L
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT                0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK              0x01000000L
+#define CP_INT_STATUS__OPCODE_ERROR_STAT                   0x01000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK      0x02000000L
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT           0x02000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK        0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT             0x04000000L
+#define CP_INT_STATUS__IB_ERROR_STAT_MASK                  0x08000000L
+#define CP_INT_STATUS__IB_ERROR_STAT                       0x08000000L
+#define CP_INT_STATUS__IB2_INT_STAT_MASK                   0x20000000L
+#define CP_INT_STATUS__IB2_INT_STAT                        0x20000000L
+#define CP_INT_STATUS__IB1_INT_STAT_MASK                   0x40000000L
+#define CP_INT_STATUS__IB1_INT_STAT                        0x40000000L
+#define CP_INT_STATUS__RB_INT_STAT_MASK                    0x80000000L
+#define CP_INT_STATUS__RB_INT_STAT                         0x80000000L
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK_MASK                        0x00080000L
+#define CP_INT_ACK__SW_INT_ACK                             0x00080000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK               0x00800000L
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK                    0x00800000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK                  0x01000000L
+#define CP_INT_ACK__OPCODE_ERROR_ACK                       0x01000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK          0x02000000L
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK               0x02000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK            0x04000000L
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK                 0x04000000L
+#define CP_INT_ACK__IB_ERROR_ACK_MASK                      0x08000000L
+#define CP_INT_ACK__IB_ERROR_ACK                           0x08000000L
+#define CP_INT_ACK__IB2_INT_ACK_MASK                       0x20000000L
+#define CP_INT_ACK__IB2_INT_ACK                            0x20000000L
+#define CP_INT_ACK__IB1_INT_ACK_MASK                       0x40000000L
+#define CP_INT_ACK__IB1_INT_ACK                            0x40000000L
+#define CP_INT_ACK__RB_INT_ACK_MASK                        0x80000000L
+#define CP_INT_ACK__RB_INT_ACK                             0x80000000L
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                 0x000001ffL
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                 0x00ffffffL
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK                0x0000000fL
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK          0x00000300L
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK          0x0000003fL
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK               0xffffffffL
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK               0x0000ffffL
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK                   0xffffffffL
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK                   0xffffffffL
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK               0xffffffffL
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK               0xffffffffL
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0_MASK                      0x00000001L
+#define CP_NV_FLAGS_0__DISCARD_0                           0x00000001L
+#define CP_NV_FLAGS_0__END_RCVD_0_MASK                     0x00000002L
+#define CP_NV_FLAGS_0__END_RCVD_0                          0x00000002L
+#define CP_NV_FLAGS_0__DISCARD_1_MASK                      0x00000004L
+#define CP_NV_FLAGS_0__DISCARD_1                           0x00000004L
+#define CP_NV_FLAGS_0__END_RCVD_1_MASK                     0x00000008L
+#define CP_NV_FLAGS_0__END_RCVD_1                          0x00000008L
+#define CP_NV_FLAGS_0__DISCARD_2_MASK                      0x00000010L
+#define CP_NV_FLAGS_0__DISCARD_2                           0x00000010L
+#define CP_NV_FLAGS_0__END_RCVD_2_MASK                     0x00000020L
+#define CP_NV_FLAGS_0__END_RCVD_2                          0x00000020L
+#define CP_NV_FLAGS_0__DISCARD_3_MASK                      0x00000040L
+#define CP_NV_FLAGS_0__DISCARD_3                           0x00000040L
+#define CP_NV_FLAGS_0__END_RCVD_3_MASK                     0x00000080L
+#define CP_NV_FLAGS_0__END_RCVD_3                          0x00000080L
+#define CP_NV_FLAGS_0__DISCARD_4_MASK                      0x00000100L
+#define CP_NV_FLAGS_0__DISCARD_4                           0x00000100L
+#define CP_NV_FLAGS_0__END_RCVD_4_MASK                     0x00000200L
+#define CP_NV_FLAGS_0__END_RCVD_4                          0x00000200L
+#define CP_NV_FLAGS_0__DISCARD_5_MASK                      0x00000400L
+#define CP_NV_FLAGS_0__DISCARD_5                           0x00000400L
+#define CP_NV_FLAGS_0__END_RCVD_5_MASK                     0x00000800L
+#define CP_NV_FLAGS_0__END_RCVD_5                          0x00000800L
+#define CP_NV_FLAGS_0__DISCARD_6_MASK                      0x00001000L
+#define CP_NV_FLAGS_0__DISCARD_6                           0x00001000L
+#define CP_NV_FLAGS_0__END_RCVD_6_MASK                     0x00002000L
+#define CP_NV_FLAGS_0__END_RCVD_6                          0x00002000L
+#define CP_NV_FLAGS_0__DISCARD_7_MASK                      0x00004000L
+#define CP_NV_FLAGS_0__DISCARD_7                           0x00004000L
+#define CP_NV_FLAGS_0__END_RCVD_7_MASK                     0x00008000L
+#define CP_NV_FLAGS_0__END_RCVD_7                          0x00008000L
+#define CP_NV_FLAGS_0__DISCARD_8_MASK                      0x00010000L
+#define CP_NV_FLAGS_0__DISCARD_8                           0x00010000L
+#define CP_NV_FLAGS_0__END_RCVD_8_MASK                     0x00020000L
+#define CP_NV_FLAGS_0__END_RCVD_8                          0x00020000L
+#define CP_NV_FLAGS_0__DISCARD_9_MASK                      0x00040000L
+#define CP_NV_FLAGS_0__DISCARD_9                           0x00040000L
+#define CP_NV_FLAGS_0__END_RCVD_9_MASK                     0x00080000L
+#define CP_NV_FLAGS_0__END_RCVD_9                          0x00080000L
+#define CP_NV_FLAGS_0__DISCARD_10_MASK                     0x00100000L
+#define CP_NV_FLAGS_0__DISCARD_10                          0x00100000L
+#define CP_NV_FLAGS_0__END_RCVD_10_MASK                    0x00200000L
+#define CP_NV_FLAGS_0__END_RCVD_10                         0x00200000L
+#define CP_NV_FLAGS_0__DISCARD_11_MASK                     0x00400000L
+#define CP_NV_FLAGS_0__DISCARD_11                          0x00400000L
+#define CP_NV_FLAGS_0__END_RCVD_11_MASK                    0x00800000L
+#define CP_NV_FLAGS_0__END_RCVD_11                         0x00800000L
+#define CP_NV_FLAGS_0__DISCARD_12_MASK                     0x01000000L
+#define CP_NV_FLAGS_0__DISCARD_12                          0x01000000L
+#define CP_NV_FLAGS_0__END_RCVD_12_MASK                    0x02000000L
+#define CP_NV_FLAGS_0__END_RCVD_12                         0x02000000L
+#define CP_NV_FLAGS_0__DISCARD_13_MASK                     0x04000000L
+#define CP_NV_FLAGS_0__DISCARD_13                          0x04000000L
+#define CP_NV_FLAGS_0__END_RCVD_13_MASK                    0x08000000L
+#define CP_NV_FLAGS_0__END_RCVD_13                         0x08000000L
+#define CP_NV_FLAGS_0__DISCARD_14_MASK                     0x10000000L
+#define CP_NV_FLAGS_0__DISCARD_14                          0x10000000L
+#define CP_NV_FLAGS_0__END_RCVD_14_MASK                    0x20000000L
+#define CP_NV_FLAGS_0__END_RCVD_14                         0x20000000L
+#define CP_NV_FLAGS_0__DISCARD_15_MASK                     0x40000000L
+#define CP_NV_FLAGS_0__DISCARD_15                          0x40000000L
+#define CP_NV_FLAGS_0__END_RCVD_15_MASK                    0x80000000L
+#define CP_NV_FLAGS_0__END_RCVD_15                         0x80000000L
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16_MASK                     0x00000001L
+#define CP_NV_FLAGS_1__DISCARD_16                          0x00000001L
+#define CP_NV_FLAGS_1__END_RCVD_16_MASK                    0x00000002L
+#define CP_NV_FLAGS_1__END_RCVD_16                         0x00000002L
+#define CP_NV_FLAGS_1__DISCARD_17_MASK                     0x00000004L
+#define CP_NV_FLAGS_1__DISCARD_17                          0x00000004L
+#define CP_NV_FLAGS_1__END_RCVD_17_MASK                    0x00000008L
+#define CP_NV_FLAGS_1__END_RCVD_17                         0x00000008L
+#define CP_NV_FLAGS_1__DISCARD_18_MASK                     0x00000010L
+#define CP_NV_FLAGS_1__DISCARD_18                          0x00000010L
+#define CP_NV_FLAGS_1__END_RCVD_18_MASK                    0x00000020L
+#define CP_NV_FLAGS_1__END_RCVD_18                         0x00000020L
+#define CP_NV_FLAGS_1__DISCARD_19_MASK                     0x00000040L
+#define CP_NV_FLAGS_1__DISCARD_19                          0x00000040L
+#define CP_NV_FLAGS_1__END_RCVD_19_MASK                    0x00000080L
+#define CP_NV_FLAGS_1__END_RCVD_19                         0x00000080L
+#define CP_NV_FLAGS_1__DISCARD_20_MASK                     0x00000100L
+#define CP_NV_FLAGS_1__DISCARD_20                          0x00000100L
+#define CP_NV_FLAGS_1__END_RCVD_20_MASK                    0x00000200L
+#define CP_NV_FLAGS_1__END_RCVD_20                         0x00000200L
+#define CP_NV_FLAGS_1__DISCARD_21_MASK                     0x00000400L
+#define CP_NV_FLAGS_1__DISCARD_21                          0x00000400L
+#define CP_NV_FLAGS_1__END_RCVD_21_MASK                    0x00000800L
+#define CP_NV_FLAGS_1__END_RCVD_21                         0x00000800L
+#define CP_NV_FLAGS_1__DISCARD_22_MASK                     0x00001000L
+#define CP_NV_FLAGS_1__DISCARD_22                          0x00001000L
+#define CP_NV_FLAGS_1__END_RCVD_22_MASK                    0x00002000L
+#define CP_NV_FLAGS_1__END_RCVD_22                         0x00002000L
+#define CP_NV_FLAGS_1__DISCARD_23_MASK                     0x00004000L
+#define CP_NV_FLAGS_1__DISCARD_23                          0x00004000L
+#define CP_NV_FLAGS_1__END_RCVD_23_MASK                    0x00008000L
+#define CP_NV_FLAGS_1__END_RCVD_23                         0x00008000L
+#define CP_NV_FLAGS_1__DISCARD_24_MASK                     0x00010000L
+#define CP_NV_FLAGS_1__DISCARD_24                          0x00010000L
+#define CP_NV_FLAGS_1__END_RCVD_24_MASK                    0x00020000L
+#define CP_NV_FLAGS_1__END_RCVD_24                         0x00020000L
+#define CP_NV_FLAGS_1__DISCARD_25_MASK                     0x00040000L
+#define CP_NV_FLAGS_1__DISCARD_25                          0x00040000L
+#define CP_NV_FLAGS_1__END_RCVD_25_MASK                    0x00080000L
+#define CP_NV_FLAGS_1__END_RCVD_25                         0x00080000L
+#define CP_NV_FLAGS_1__DISCARD_26_MASK                     0x00100000L
+#define CP_NV_FLAGS_1__DISCARD_26                          0x00100000L
+#define CP_NV_FLAGS_1__END_RCVD_26_MASK                    0x00200000L
+#define CP_NV_FLAGS_1__END_RCVD_26                         0x00200000L
+#define CP_NV_FLAGS_1__DISCARD_27_MASK                     0x00400000L
+#define CP_NV_FLAGS_1__DISCARD_27                          0x00400000L
+#define CP_NV_FLAGS_1__END_RCVD_27_MASK                    0x00800000L
+#define CP_NV_FLAGS_1__END_RCVD_27                         0x00800000L
+#define CP_NV_FLAGS_1__DISCARD_28_MASK                     0x01000000L
+#define CP_NV_FLAGS_1__DISCARD_28                          0x01000000L
+#define CP_NV_FLAGS_1__END_RCVD_28_MASK                    0x02000000L
+#define CP_NV_FLAGS_1__END_RCVD_28                         0x02000000L
+#define CP_NV_FLAGS_1__DISCARD_29_MASK                     0x04000000L
+#define CP_NV_FLAGS_1__DISCARD_29                          0x04000000L
+#define CP_NV_FLAGS_1__END_RCVD_29_MASK                    0x08000000L
+#define CP_NV_FLAGS_1__END_RCVD_29                         0x08000000L
+#define CP_NV_FLAGS_1__DISCARD_30_MASK                     0x10000000L
+#define CP_NV_FLAGS_1__DISCARD_30                          0x10000000L
+#define CP_NV_FLAGS_1__END_RCVD_30_MASK                    0x20000000L
+#define CP_NV_FLAGS_1__END_RCVD_30                         0x20000000L
+#define CP_NV_FLAGS_1__DISCARD_31_MASK                     0x40000000L
+#define CP_NV_FLAGS_1__DISCARD_31                          0x40000000L
+#define CP_NV_FLAGS_1__END_RCVD_31_MASK                    0x80000000L
+#define CP_NV_FLAGS_1__END_RCVD_31                         0x80000000L
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32_MASK                     0x00000001L
+#define CP_NV_FLAGS_2__DISCARD_32                          0x00000001L
+#define CP_NV_FLAGS_2__END_RCVD_32_MASK                    0x00000002L
+#define CP_NV_FLAGS_2__END_RCVD_32                         0x00000002L
+#define CP_NV_FLAGS_2__DISCARD_33_MASK                     0x00000004L
+#define CP_NV_FLAGS_2__DISCARD_33                          0x00000004L
+#define CP_NV_FLAGS_2__END_RCVD_33_MASK                    0x00000008L
+#define CP_NV_FLAGS_2__END_RCVD_33                         0x00000008L
+#define CP_NV_FLAGS_2__DISCARD_34_MASK                     0x00000010L
+#define CP_NV_FLAGS_2__DISCARD_34                          0x00000010L
+#define CP_NV_FLAGS_2__END_RCVD_34_MASK                    0x00000020L
+#define CP_NV_FLAGS_2__END_RCVD_34                         0x00000020L
+#define CP_NV_FLAGS_2__DISCARD_35_MASK                     0x00000040L
+#define CP_NV_FLAGS_2__DISCARD_35                          0x00000040L
+#define CP_NV_FLAGS_2__END_RCVD_35_MASK                    0x00000080L
+#define CP_NV_FLAGS_2__END_RCVD_35                         0x00000080L
+#define CP_NV_FLAGS_2__DISCARD_36_MASK                     0x00000100L
+#define CP_NV_FLAGS_2__DISCARD_36                          0x00000100L
+#define CP_NV_FLAGS_2__END_RCVD_36_MASK                    0x00000200L
+#define CP_NV_FLAGS_2__END_RCVD_36                         0x00000200L
+#define CP_NV_FLAGS_2__DISCARD_37_MASK                     0x00000400L
+#define CP_NV_FLAGS_2__DISCARD_37                          0x00000400L
+#define CP_NV_FLAGS_2__END_RCVD_37_MASK                    0x00000800L
+#define CP_NV_FLAGS_2__END_RCVD_37                         0x00000800L
+#define CP_NV_FLAGS_2__DISCARD_38_MASK                     0x00001000L
+#define CP_NV_FLAGS_2__DISCARD_38                          0x00001000L
+#define CP_NV_FLAGS_2__END_RCVD_38_MASK                    0x00002000L
+#define CP_NV_FLAGS_2__END_RCVD_38                         0x00002000L
+#define CP_NV_FLAGS_2__DISCARD_39_MASK                     0x00004000L
+#define CP_NV_FLAGS_2__DISCARD_39                          0x00004000L
+#define CP_NV_FLAGS_2__END_RCVD_39_MASK                    0x00008000L
+#define CP_NV_FLAGS_2__END_RCVD_39                         0x00008000L
+#define CP_NV_FLAGS_2__DISCARD_40_MASK                     0x00010000L
+#define CP_NV_FLAGS_2__DISCARD_40                          0x00010000L
+#define CP_NV_FLAGS_2__END_RCVD_40_MASK                    0x00020000L
+#define CP_NV_FLAGS_2__END_RCVD_40                         0x00020000L
+#define CP_NV_FLAGS_2__DISCARD_41_MASK                     0x00040000L
+#define CP_NV_FLAGS_2__DISCARD_41                          0x00040000L
+#define CP_NV_FLAGS_2__END_RCVD_41_MASK                    0x00080000L
+#define CP_NV_FLAGS_2__END_RCVD_41                         0x00080000L
+#define CP_NV_FLAGS_2__DISCARD_42_MASK                     0x00100000L
+#define CP_NV_FLAGS_2__DISCARD_42                          0x00100000L
+#define CP_NV_FLAGS_2__END_RCVD_42_MASK                    0x00200000L
+#define CP_NV_FLAGS_2__END_RCVD_42                         0x00200000L
+#define CP_NV_FLAGS_2__DISCARD_43_MASK                     0x00400000L
+#define CP_NV_FLAGS_2__DISCARD_43                          0x00400000L
+#define CP_NV_FLAGS_2__END_RCVD_43_MASK                    0x00800000L
+#define CP_NV_FLAGS_2__END_RCVD_43                         0x00800000L
+#define CP_NV_FLAGS_2__DISCARD_44_MASK                     0x01000000L
+#define CP_NV_FLAGS_2__DISCARD_44                          0x01000000L
+#define CP_NV_FLAGS_2__END_RCVD_44_MASK                    0x02000000L
+#define CP_NV_FLAGS_2__END_RCVD_44                         0x02000000L
+#define CP_NV_FLAGS_2__DISCARD_45_MASK                     0x04000000L
+#define CP_NV_FLAGS_2__DISCARD_45                          0x04000000L
+#define CP_NV_FLAGS_2__END_RCVD_45_MASK                    0x08000000L
+#define CP_NV_FLAGS_2__END_RCVD_45                         0x08000000L
+#define CP_NV_FLAGS_2__DISCARD_46_MASK                     0x10000000L
+#define CP_NV_FLAGS_2__DISCARD_46                          0x10000000L
+#define CP_NV_FLAGS_2__END_RCVD_46_MASK                    0x20000000L
+#define CP_NV_FLAGS_2__END_RCVD_46                         0x20000000L
+#define CP_NV_FLAGS_2__DISCARD_47_MASK                     0x40000000L
+#define CP_NV_FLAGS_2__DISCARD_47                          0x40000000L
+#define CP_NV_FLAGS_2__END_RCVD_47_MASK                    0x80000000L
+#define CP_NV_FLAGS_2__END_RCVD_47                         0x80000000L
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48_MASK                     0x00000001L
+#define CP_NV_FLAGS_3__DISCARD_48                          0x00000001L
+#define CP_NV_FLAGS_3__END_RCVD_48_MASK                    0x00000002L
+#define CP_NV_FLAGS_3__END_RCVD_48                         0x00000002L
+#define CP_NV_FLAGS_3__DISCARD_49_MASK                     0x00000004L
+#define CP_NV_FLAGS_3__DISCARD_49                          0x00000004L
+#define CP_NV_FLAGS_3__END_RCVD_49_MASK                    0x00000008L
+#define CP_NV_FLAGS_3__END_RCVD_49                         0x00000008L
+#define CP_NV_FLAGS_3__DISCARD_50_MASK                     0x00000010L
+#define CP_NV_FLAGS_3__DISCARD_50                          0x00000010L
+#define CP_NV_FLAGS_3__END_RCVD_50_MASK                    0x00000020L
+#define CP_NV_FLAGS_3__END_RCVD_50                         0x00000020L
+#define CP_NV_FLAGS_3__DISCARD_51_MASK                     0x00000040L
+#define CP_NV_FLAGS_3__DISCARD_51                          0x00000040L
+#define CP_NV_FLAGS_3__END_RCVD_51_MASK                    0x00000080L
+#define CP_NV_FLAGS_3__END_RCVD_51                         0x00000080L
+#define CP_NV_FLAGS_3__DISCARD_52_MASK                     0x00000100L
+#define CP_NV_FLAGS_3__DISCARD_52                          0x00000100L
+#define CP_NV_FLAGS_3__END_RCVD_52_MASK                    0x00000200L
+#define CP_NV_FLAGS_3__END_RCVD_52                         0x00000200L
+#define CP_NV_FLAGS_3__DISCARD_53_MASK                     0x00000400L
+#define CP_NV_FLAGS_3__DISCARD_53                          0x00000400L
+#define CP_NV_FLAGS_3__END_RCVD_53_MASK                    0x00000800L
+#define CP_NV_FLAGS_3__END_RCVD_53                         0x00000800L
+#define CP_NV_FLAGS_3__DISCARD_54_MASK                     0x00001000L
+#define CP_NV_FLAGS_3__DISCARD_54                          0x00001000L
+#define CP_NV_FLAGS_3__END_RCVD_54_MASK                    0x00002000L
+#define CP_NV_FLAGS_3__END_RCVD_54                         0x00002000L
+#define CP_NV_FLAGS_3__DISCARD_55_MASK                     0x00004000L
+#define CP_NV_FLAGS_3__DISCARD_55                          0x00004000L
+#define CP_NV_FLAGS_3__END_RCVD_55_MASK                    0x00008000L
+#define CP_NV_FLAGS_3__END_RCVD_55                         0x00008000L
+#define CP_NV_FLAGS_3__DISCARD_56_MASK                     0x00010000L
+#define CP_NV_FLAGS_3__DISCARD_56                          0x00010000L
+#define CP_NV_FLAGS_3__END_RCVD_56_MASK                    0x00020000L
+#define CP_NV_FLAGS_3__END_RCVD_56                         0x00020000L
+#define CP_NV_FLAGS_3__DISCARD_57_MASK                     0x00040000L
+#define CP_NV_FLAGS_3__DISCARD_57                          0x00040000L
+#define CP_NV_FLAGS_3__END_RCVD_57_MASK                    0x00080000L
+#define CP_NV_FLAGS_3__END_RCVD_57                         0x00080000L
+#define CP_NV_FLAGS_3__DISCARD_58_MASK                     0x00100000L
+#define CP_NV_FLAGS_3__DISCARD_58                          0x00100000L
+#define CP_NV_FLAGS_3__END_RCVD_58_MASK                    0x00200000L
+#define CP_NV_FLAGS_3__END_RCVD_58                         0x00200000L
+#define CP_NV_FLAGS_3__DISCARD_59_MASK                     0x00400000L
+#define CP_NV_FLAGS_3__DISCARD_59                          0x00400000L
+#define CP_NV_FLAGS_3__END_RCVD_59_MASK                    0x00800000L
+#define CP_NV_FLAGS_3__END_RCVD_59                         0x00800000L
+#define CP_NV_FLAGS_3__DISCARD_60_MASK                     0x01000000L
+#define CP_NV_FLAGS_3__DISCARD_60                          0x01000000L
+#define CP_NV_FLAGS_3__END_RCVD_60_MASK                    0x02000000L
+#define CP_NV_FLAGS_3__END_RCVD_60                         0x02000000L
+#define CP_NV_FLAGS_3__DISCARD_61_MASK                     0x04000000L
+#define CP_NV_FLAGS_3__DISCARD_61                          0x04000000L
+#define CP_NV_FLAGS_3__END_RCVD_61_MASK                    0x08000000L
+#define CP_NV_FLAGS_3__END_RCVD_61                         0x08000000L
+#define CP_NV_FLAGS_3__DISCARD_62_MASK                     0x10000000L
+#define CP_NV_FLAGS_3__DISCARD_62                          0x10000000L
+#define CP_NV_FLAGS_3__END_RCVD_62_MASK                    0x20000000L
+#define CP_NV_FLAGS_3__END_RCVD_62                         0x20000000L
+#define CP_NV_FLAGS_3__DISCARD_63_MASK                     0x40000000L
+#define CP_NV_FLAGS_3__DISCARD_63                          0x40000000L
+#define CP_NV_FLAGS_3__END_RCVD_63_MASK                    0x80000000L
+#define CP_NV_FLAGS_3__END_RCVD_63                         0x80000000L
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK       0x0000001fL
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK         0xffffffffL
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER_MASK                      0xffffffffL
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY_MASK                          0x00000001L
+#define CP_STAT__MIU_WR_BUSY                               0x00000001L
+#define CP_STAT__MIU_RD_REQ_BUSY_MASK                      0x00000002L
+#define CP_STAT__MIU_RD_REQ_BUSY                           0x00000002L
+#define CP_STAT__MIU_RD_RETURN_BUSY_MASK                   0x00000004L
+#define CP_STAT__MIU_RD_RETURN_BUSY                        0x00000004L
+#define CP_STAT__RBIU_BUSY_MASK                            0x00000008L
+#define CP_STAT__RBIU_BUSY                                 0x00000008L
+#define CP_STAT__RCIU_BUSY_MASK                            0x00000010L
+#define CP_STAT__RCIU_BUSY                                 0x00000010L
+#define CP_STAT__CSF_RING_BUSY_MASK                        0x00000020L
+#define CP_STAT__CSF_RING_BUSY                             0x00000020L
+#define CP_STAT__CSF_INDIRECTS_BUSY_MASK                   0x00000040L
+#define CP_STAT__CSF_INDIRECTS_BUSY                        0x00000040L
+#define CP_STAT__CSF_INDIRECT2_BUSY_MASK                   0x00000080L
+#define CP_STAT__CSF_INDIRECT2_BUSY                        0x00000080L
+#define CP_STAT__CSF_ST_BUSY_MASK                          0x00000200L
+#define CP_STAT__CSF_ST_BUSY                               0x00000200L
+#define CP_STAT__CSF_BUSY_MASK                             0x00000400L
+#define CP_STAT__CSF_BUSY                                  0x00000400L
+#define CP_STAT__RING_QUEUE_BUSY_MASK                      0x00000800L
+#define CP_STAT__RING_QUEUE_BUSY                           0x00000800L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK                 0x00001000L
+#define CP_STAT__INDIRECTS_QUEUE_BUSY                      0x00001000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK                 0x00002000L
+#define CP_STAT__INDIRECT2_QUEUE_BUSY                      0x00002000L
+#define CP_STAT__ST_QUEUE_BUSY_MASK                        0x00010000L
+#define CP_STAT__ST_QUEUE_BUSY                             0x00010000L
+#define CP_STAT__PFP_BUSY_MASK                             0x00020000L
+#define CP_STAT__PFP_BUSY                                  0x00020000L
+#define CP_STAT__MEQ_RING_BUSY_MASK                        0x00040000L
+#define CP_STAT__MEQ_RING_BUSY                             0x00040000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK                   0x00080000L
+#define CP_STAT__MEQ_INDIRECTS_BUSY                        0x00080000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK                   0x00100000L
+#define CP_STAT__MEQ_INDIRECT2_BUSY                        0x00100000L
+#define CP_STAT__MIU_WC_STALL_MASK                         0x00200000L
+#define CP_STAT__MIU_WC_STALL                              0x00200000L
+#define CP_STAT__CP_NRT_BUSY_MASK                          0x00400000L
+#define CP_STAT__CP_NRT_BUSY                               0x00400000L
+#define CP_STAT___3D_BUSY_MASK                             0x00800000L
+#define CP_STAT___3D_BUSY                                  0x00800000L
+#define CP_STAT__ME_BUSY_MASK                              0x04000000L
+#define CP_STAT__ME_BUSY                                   0x04000000L
+#define CP_STAT__ME_WC_BUSY_MASK                           0x20000000L
+#define CP_STAT__ME_WC_BUSY                                0x20000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK              0x40000000L
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY                   0x40000000L
+#define CP_STAT__CP_BUSY_MASK                              0x80000000L
+#define CP_STAT__CP_BUSY                                   0x80000000L
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK                  0xffffffffL
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK                 0xffffffffL
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE_MASK                          0xffffffffL
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE_MASK                          0xffffffffL
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK           0x000000ffL
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK       0x00000100L
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA            0x00000100L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK             0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA                  0x00000200L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK             0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA                  0x00000400L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK             0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA                  0x00000800L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK             0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA                  0x00001000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK             0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA                  0x00002000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK             0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA                  0x00004000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK             0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA                  0x00008000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK             0x00010000L
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA                  0x00010000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK           0x00020000L
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA                0x00020000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK               0x02000000L
+#define COHER_STATUS_PM4__TC_ACTION_ENA                    0x02000000L
+#define COHER_STATUS_PM4__STATUS_MASK                      0x80000000L
+#define COHER_STATUS_PM4__STATUS                           0x80000000L
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE_MASK                         0xffffffffL
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE_MASK                         0xffffffffL
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK          0x000000ffL
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK      0x00000100L
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA           0x00000100L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK            0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA                 0x00000200L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK            0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA                 0x00000400L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK            0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA                 0x00000800L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK            0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA                 0x00001000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK            0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA                 0x00002000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK            0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA                 0x00004000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK            0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA                 0x00008000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK            0x00010000L
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA                 0x00010000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK          0x00020000L
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA               0x00020000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK              0x02000000L
+#define COHER_STATUS_HOST__TC_ACTION_ENA                   0x02000000L
+#define COHER_STATUS_HOST__STATUS_MASK                     0x80000000L
+#define COHER_STATUS_HOST__STATUS                          0x80000000L
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0_MASK                0xfffff000L
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1_MASK                0xfffff000L
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2_MASK                0xfffff000L
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3_MASK                0xfffff000L
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4_MASK                0xfffff000L
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5_MASK                0xfffff000L
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6_MASK                0xfffff000L
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7_MASK                0xfffff000L
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH_MASK                0x00003fffL
+#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK                 0x0000c000L
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT_MASK                   0x0000000fL
+#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK               0x00000030L
+#define RB_COLOR_INFO__COLOR_LINEAR_MASK                   0x00000040L
+#define RB_COLOR_INFO__COLOR_LINEAR                        0x00000040L
+#define RB_COLOR_INFO__COLOR_ENDIAN_MASK                   0x00000180L
+#define RB_COLOR_INFO__COLOR_SWAP_MASK                     0x00000600L
+#define RB_COLOR_INFO__COLOR_BASE_MASK                     0xfffff000L
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK                   0x00000001L
+#define RB_DEPTH_INFO__DEPTH_FORMAT                        0x00000001L
+#define RB_DEPTH_INFO__DEPTH_BASE_MASK                     0xfffff000L
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF_MASK                 0x000000ffL
+#define RB_STENCILREFMASK__STENCILMASK_MASK                0x0000ff00L
+#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK           0x00ff0000L
+#define RB_STENCILREFMASK__RESERVED0_MASK                  0x01000000L
+#define RB_STENCILREFMASK__RESERVED0                       0x01000000L
+#define RB_STENCILREFMASK__RESERVED1_MASK                  0x02000000L
+#define RB_STENCILREFMASK__RESERVED1                       0x02000000L
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF_MASK                       0xffffffffL
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED_MASK                      0x00000001L
+#define RB_COLOR_MASK__WRITE_RED                           0x00000001L
+#define RB_COLOR_MASK__WRITE_GREEN_MASK                    0x00000002L
+#define RB_COLOR_MASK__WRITE_GREEN                         0x00000002L
+#define RB_COLOR_MASK__WRITE_BLUE_MASK                     0x00000004L
+#define RB_COLOR_MASK__WRITE_BLUE                          0x00000004L
+#define RB_COLOR_MASK__WRITE_ALPHA_MASK                    0x00000008L
+#define RB_COLOR_MASK__WRITE_ALPHA                         0x00000008L
+#define RB_COLOR_MASK__RESERVED2_MASK                      0x00000010L
+#define RB_COLOR_MASK__RESERVED2                           0x00000010L
+#define RB_COLOR_MASK__RESERVED3_MASK                      0x00000020L
+#define RB_COLOR_MASK__RESERVED3                           0x00000020L
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED_MASK                       0x000000ffL
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN_MASK                   0x000000ffL
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE_MASK                     0x000000ffL
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK                   0x000000ffL
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED_MASK                         0x000000ffL
+#define RB_FOG_COLOR__FOG_GREEN_MASK                       0x0000ff00L
+#define RB_FOG_COLOR__FOG_BLUE_MASK                        0x00ff0000L
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK           0x000000ffL
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK          0x0000ff00L
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK     0x00ff0000L
+#define RB_STENCILREFMASK_BF__RESERVED4_MASK               0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED4                    0x01000000L
+#define RB_STENCILREFMASK_BF__RESERVED5_MASK               0x02000000L
+#define RB_STENCILREFMASK_BF__RESERVED5                    0x02000000L
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK               0x00000001L
+#define RB_DEPTHCONTROL__STENCIL_ENABLE                    0x00000001L
+#define RB_DEPTHCONTROL__Z_ENABLE_MASK                     0x00000002L
+#define RB_DEPTHCONTROL__Z_ENABLE                          0x00000002L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK               0x00000004L
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE                    0x00000004L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK               0x00000008L
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE                    0x00000008L
+#define RB_DEPTHCONTROL__ZFUNC_MASK                        0x00000070L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK              0x00000080L
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE                   0x00000080L
+#define RB_DEPTHCONTROL__STENCILFUNC_MASK                  0x00000700L
+#define RB_DEPTHCONTROL__STENCILFAIL_MASK                  0x00003800L
+#define RB_DEPTHCONTROL__STENCILZPASS_MASK                 0x0001c000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_MASK                 0x000e0000L
+#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK               0x00700000L
+#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK               0x03800000L
+#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK              0x1c000000L
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK              0xe0000000L
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK               0x0000001fL
+#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK               0x000000e0L
+#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK              0x00001f00L
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK               0x001f0000L
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK               0x00e00000L
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK              0x1f000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK           0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE                0x20000000L
+#define RB_BLENDCONTROL__BLEND_FORCE_MASK                  0x40000000L
+#define RB_BLENDCONTROL__BLEND_FORCE                       0x40000000L
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC_MASK                   0x00000007L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK            0x00000008L
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE                 0x00000008L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK         0x00000010L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE              0x00000010L
+#define RB_COLORCONTROL__BLEND_DISABLE_MASK                0x00000020L
+#define RB_COLORCONTROL__BLEND_DISABLE                     0x00000020L
+#define RB_COLORCONTROL__FOG_ENABLE_MASK                   0x00000040L
+#define RB_COLORCONTROL__FOG_ENABLE                        0x00000040L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK               0x00000080L
+#define RB_COLORCONTROL__VS_EXPORTS_FOG                    0x00000080L
+#define RB_COLORCONTROL__ROP_CODE_MASK                     0x00000f00L
+#define RB_COLORCONTROL__DITHER_MODE_MASK                  0x00003000L
+#define RB_COLORCONTROL__DITHER_TYPE_MASK                  0x0000c000L
+#define RB_COLORCONTROL__PIXEL_FOG_MASK                    0x00010000L
+#define RB_COLORCONTROL__PIXEL_FOG                         0x00010000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK        0x03000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK        0x0c000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK        0x30000000L
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK        0xc0000000L
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE_MASK                    0x00000007L
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK           0xffffffffL
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK           0x00000007L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK           0x00000008L
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE                0x00000008L
+#define RB_COPY_CONTROL__CLEAR_MASK_MASK                   0x000000f0L
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK             0xfffff000L
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK           0x000001ffL
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK           0x00000007L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK           0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR                0x00000008L
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK           0x000000f0L
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK             0x00000300L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK      0x00000c00L
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK      0x00003000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK        0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED             0x00004000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK      0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN           0x00008000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK       0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE            0x00010000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK      0x00020000L
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA           0x00020000L
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK           0x00001fffL
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK           0x03ffe000L
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                   0xffffffffL
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK       0x00000001L
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT            0x00000001L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK        0x00000002L
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT             0x00000002L
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK       0xffffffffL
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK       0x00000001L
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE            0x00000001L
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK           0x00000006L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK              0x00000008L
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM                   0x00000008L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK      0x00000020L
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP           0x00000020L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK      0x00000040L
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP           0x00000040L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK             0x00000080L
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE                  0x00000080L
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK              0x00001f00L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK              0x00004000L
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE                   0x00004000L
+#define RB_BC_CONTROL__CRC_MODE_MASK                       0x00008000L
+#define RB_BC_CONTROL__CRC_MODE                            0x00008000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK        0x00010000L
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS             0x00010000L
+#define RB_BC_CONTROL__DISABLE_ACCUM_MASK                  0x00020000L
+#define RB_BC_CONTROL__DISABLE_ACCUM                       0x00020000L
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK               0x003c0000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK      0x00400000L
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE           0x00400000L
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK          0x07800000L
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK      0x18000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK  0x20000000L
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000L
+#define RB_BC_CONTROL__CRC_SYSTEM_MASK                     0x40000000L
+#define RB_BC_CONTROL__CRC_SYSTEM                          0x40000000L
+#define RB_BC_CONTROL__RESERVED6_MASK                      0x80000000L
+#define RB_BC_CONTROL__RESERVED6                           0x80000000L
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE_MASK                     0x0000000fL
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK             0x00000030L
+#define RB_EDRAM_INFO__EDRAM_RANGE_MASK                    0xffffc000L
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA_MASK                      0xffffffffL
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK                0x00000001L
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE                     0x00000001L
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK_MASK                         0xffffffffL
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK              0x000000ffL
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK               0xffffffffL
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK                0x0000ffffL
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK               0xffffffffL
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK               0xffffffffL
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK               0xffffffffL
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK             0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL                  0x00000001L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK             0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL                  0x00000002L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK             0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL                  0x00000004L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK             0x00000008L
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL                  0x00000008L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK            0x00000010L
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL                 0x00000010L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK            0x00000020L
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL                 0x00000020L
+#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK                     0x00000040L
+#define RB_DEBUG_0__RDREQ_Z1_FULL                          0x00000040L
+#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK                     0x00000080L
+#define RB_DEBUG_0__RDREQ_Z0_FULL                          0x00000080L
+#define RB_DEBUG_0__RDREQ_C1_FULL_MASK                     0x00000100L
+#define RB_DEBUG_0__RDREQ_C1_FULL                          0x00000100L
+#define RB_DEBUG_0__RDREQ_C0_FULL_MASK                     0x00000200L
+#define RB_DEBUG_0__RDREQ_C0_FULL                          0x00000200L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK            0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL                 0x00000400L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK            0x00000800L
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL                 0x00000800L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK            0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL                 0x00001000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK            0x00002000L
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL                 0x00002000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK                0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL                     0x00004000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK                0x00008000L
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL                     0x00008000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK                     0x00010000L
+#define RB_DEBUG_0__WRREQ_Z1_FULL                          0x00010000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK                     0x00020000L
+#define RB_DEBUG_0__WRREQ_Z0_FULL                          0x00020000L
+#define RB_DEBUG_0__WRREQ_C1_FULL_MASK                     0x00040000L
+#define RB_DEBUG_0__WRREQ_C1_FULL                          0x00040000L
+#define RB_DEBUG_0__WRREQ_C0_FULL_MASK                     0x00080000L
+#define RB_DEBUG_0__WRREQ_C0_FULL                          0x00080000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK              0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL                   0x00100000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK              0x00200000L
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL                   0x00200000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK              0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL                   0x00400000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK              0x00800000L
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL                   0x00800000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK           0x01000000L
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL                0x01000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK           0x02000000L
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL                0x02000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL_MASK                     0x04000000L
+#define RB_DEBUG_0__C_SX_LAT_FULL                          0x04000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL_MASK                     0x08000000L
+#define RB_DEBUG_0__C_SX_CMD_FULL                          0x08000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK                    0x10000000L
+#define RB_DEBUG_0__C_EZ_TILE_FULL                         0x10000000L
+#define RB_DEBUG_0__C_REQ_FULL_MASK                        0x20000000L
+#define RB_DEBUG_0__C_REQ_FULL                             0x20000000L
+#define RB_DEBUG_0__C_MASK_FULL_MASK                       0x40000000L
+#define RB_DEBUG_0__C_MASK_FULL                            0x40000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK                   0x80000000L
+#define RB_DEBUG_0__EZ_INFSAMP_FULL                        0x80000000L
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK                0x00000001L
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY                     0x00000001L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK                0x00000002L
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY                     0x00000002L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK                0x00000004L
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY                     0x00000004L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK                0x00000008L
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY                     0x00000008L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK           0x00000010L
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY                0x00000010L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK           0x00000020L
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY                0x00000020L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK                    0x00000040L
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY                         0x00000040L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK                    0x00000080L
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY                         0x00000080L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK                    0x00000100L
+#define RB_DEBUG_1__RDREQ_C1_EMPTY                         0x00000100L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK                    0x00000200L
+#define RB_DEBUG_1__RDREQ_C0_EMPTY                         0x00000200L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK           0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY                0x00000400L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK           0x00000800L
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY                0x00000800L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK           0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY                0x00001000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK           0x00002000L
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY                0x00002000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK               0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY                    0x00004000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK               0x00008000L
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY                    0x00008000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK                    0x00010000L
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY                         0x00010000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK                    0x00020000L
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY                         0x00020000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK                0x00040000L
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY                     0x00040000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK                0x00080000L
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY                     0x00080000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK             0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY                  0x00100000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY                  0x00200000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY                  0x00400000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK             0x00800000L
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY                  0x00800000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK          0x01000000L
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY               0x01000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK          0x02000000L
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY               0x02000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK                    0x04000000L
+#define RB_DEBUG_1__C_SX_LAT_EMPTY                         0x04000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK                    0x08000000L
+#define RB_DEBUG_1__C_SX_CMD_EMPTY                         0x08000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK                   0x10000000L
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY                        0x10000000L
+#define RB_DEBUG_1__C_REQ_EMPTY_MASK                       0x20000000L
+#define RB_DEBUG_1__C_REQ_EMPTY                            0x20000000L
+#define RB_DEBUG_1__C_MASK_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_1__C_MASK_EMPTY                           0x40000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK                  0x80000000L
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY                       0x80000000L
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK                   0x0000000fL
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK                 0x000007f0L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK                   0x00000800L
+#define RB_DEBUG_2__MEM_EXPORT_FLAG                        0x00000800L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK                 0x00001000L
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG                      0x00001000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK                0x00002000L
+#define RB_DEBUG_2__CURRENT_TILE_EVENT                     0x00002000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK                   0x00004000L
+#define RB_DEBUG_2__EZ_INFTILE_FULL                        0x00004000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK                0x00008000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL                     0x00008000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK                0x00010000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL                     0x00010000L
+#define RB_DEBUG_2__Z0_MASK_FULL_MASK                      0x00020000L
+#define RB_DEBUG_2__Z0_MASK_FULL                           0x00020000L
+#define RB_DEBUG_2__Z1_MASK_FULL_MASK                      0x00040000L
+#define RB_DEBUG_2__Z1_MASK_FULL                           0x00040000L
+#define RB_DEBUG_2__Z0_REQ_FULL_MASK                       0x00080000L
+#define RB_DEBUG_2__Z0_REQ_FULL                            0x00080000L
+#define RB_DEBUG_2__Z1_REQ_FULL_MASK                       0x00100000L
+#define RB_DEBUG_2__Z1_REQ_FULL                            0x00100000L
+#define RB_DEBUG_2__Z_SAMP_FULL_MASK                       0x00200000L
+#define RB_DEBUG_2__Z_SAMP_FULL                            0x00200000L
+#define RB_DEBUG_2__Z_TILE_FULL_MASK                       0x00400000L
+#define RB_DEBUG_2__Z_TILE_FULL                            0x00400000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK                  0x00800000L
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY                       0x00800000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK               0x01000000L
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY                    0x01000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK               0x02000000L
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY                    0x02000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK                     0x04000000L
+#define RB_DEBUG_2__Z0_MASK_EMPTY                          0x04000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK                     0x08000000L
+#define RB_DEBUG_2__Z1_MASK_EMPTY                          0x08000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK                      0x10000000L
+#define RB_DEBUG_2__Z0_REQ_EMPTY                           0x10000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK                      0x20000000L
+#define RB_DEBUG_2__Z1_REQ_EMPTY                           0x20000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK                      0x40000000L
+#define RB_DEBUG_2__Z_SAMP_EMPTY                           0x40000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY_MASK                      0x80000000L
+#define RB_DEBUG_2__Z_TILE_EMPTY                           0x80000000L
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID_MASK                       0x0000000fL
+#define RB_DEBUG_3__ACCUM_FLUSHING_MASK                    0x000000f0L
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK           0x00003f00L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK             0x00004000L
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID                  0x00004000L
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK               0x00078000L
+#define RB_DEBUG_3__SHD_FULL_MASK                          0x00080000L
+#define RB_DEBUG_3__SHD_FULL                               0x00080000L
+#define RB_DEBUG_3__SHD_EMPTY_MASK                         0x00100000L
+#define RB_DEBUG_3__SHD_EMPTY                              0x00100000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK             0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY                  0x00200000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK             0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY                  0x00400000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK              0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL                   0x00800000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK              0x01000000L
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL                   0x01000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK                  0x02000000L
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY                       0x02000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK                  0x04000000L
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY                       0x04000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK                   0x08000000L
+#define RB_DEBUG_3__ZEXP_LOWER_FULL                        0x08000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK                   0x10000000L
+#define RB_DEBUG_3__ZEXP_UPPER_FULL                        0x10000000L
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK               0x00000001L
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG                    0x00000001L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK               0x00000002L
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG                    0x00000002L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK             0x00000004L
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG                  0x00000004L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK             0x00000008L
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG                  0x00000008L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK             0x00000010L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY                  0x00000010L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK            0x00000020L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY                 0x00000020L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK              0x00000040L
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL                   0x00000040L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK             0x00000080L
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL                  0x00000080L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK       0x00000100L
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW            0x00000100L
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK               0x00001e00L
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK             0x00000001L
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR                  0x00000001L
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED_MASK                        0xffffffffL
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP   0x00000040L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK     0x00000600L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h
new file mode 100644
index 00000000000..83be5f82ed8
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h
@@ -0,0 +1,591 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _yamato_OFFSET_HEADER
+#define _yamato_OFFSET_HEADER
+
+
+// Registers from PA block
+
+#define mmPA_CL_VPORT_XSCALE           0x210F
+#define mmPA_CL_VPORT_XOFFSET          0x2110
+#define mmPA_CL_VPORT_YSCALE           0x2111
+#define mmPA_CL_VPORT_YOFFSET          0x2112
+#define mmPA_CL_VPORT_ZSCALE           0x2113
+#define mmPA_CL_VPORT_ZOFFSET          0x2114
+#define mmPA_CL_VTE_CNTL               0x2206
+#define mmPA_CL_CLIP_CNTL              0x2204
+#define mmPA_CL_GB_VERT_CLIP_ADJ       0x2303
+#define mmPA_CL_GB_VERT_DISC_ADJ       0x2304
+#define mmPA_CL_GB_HORZ_CLIP_ADJ       0x2305
+#define mmPA_CL_GB_HORZ_DISC_ADJ       0x2306
+#define mmPA_CL_ENHANCE                0x0C85
+#define mmPA_SC_ENHANCE                0x0CA5
+#define mmPA_SU_VTX_CNTL               0x2302
+#define mmPA_SU_POINT_SIZE             0x2280
+#define mmPA_SU_POINT_MINMAX           0x2281
+#define mmPA_SU_LINE_CNTL              0x2282
+#define mmPA_SU_FACE_DATA              0x0C86
+#define mmPA_SU_SC_MODE_CNTL           0x2205
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
+#define mmPA_SU_PERFCOUNTER0_SELECT    0x0C88
+#define mmPA_SU_PERFCOUNTER1_SELECT    0x0C89
+#define mmPA_SU_PERFCOUNTER2_SELECT    0x0C8A
+#define mmPA_SU_PERFCOUNTER3_SELECT    0x0C8B
+#define mmPA_SU_PERFCOUNTER0_LOW       0x0C8C
+#define mmPA_SU_PERFCOUNTER0_HI        0x0C8D
+#define mmPA_SU_PERFCOUNTER1_LOW       0x0C8E
+#define mmPA_SU_PERFCOUNTER1_HI        0x0C8F
+#define mmPA_SU_PERFCOUNTER2_LOW       0x0C90
+#define mmPA_SU_PERFCOUNTER2_HI        0x0C91
+#define mmPA_SU_PERFCOUNTER3_LOW       0x0C92
+#define mmPA_SU_PERFCOUNTER3_HI        0x0C93
+#define mmPA_SC_WINDOW_OFFSET          0x2080
+#define mmPA_SC_AA_CONFIG              0x2301
+#define mmPA_SC_AA_MASK                0x2312
+#define mmPA_SC_LINE_STIPPLE           0x2283
+#define mmPA_SC_LINE_CNTL              0x2300
+#define mmPA_SC_WINDOW_SCISSOR_TL      0x2081
+#define mmPA_SC_WINDOW_SCISSOR_BR      0x2082
+#define mmPA_SC_SCREEN_SCISSOR_TL      0x200E
+#define mmPA_SC_SCREEN_SCISSOR_BR      0x200F
+#define mmPA_SC_VIZ_QUERY              0x2293
+#define mmPA_SC_VIZ_QUERY_STATUS       0x0C44
+#define mmPA_SC_LINE_STIPPLE_STATE     0x0C40
+#define mmPA_SC_PERFCOUNTER0_SELECT    0x0C98
+#define mmPA_SC_PERFCOUNTER0_LOW       0x0C99
+#define mmPA_SC_PERFCOUNTER0_HI        0x0C9A
+#define mmPA_CL_CNTL_STATUS            0x0C84
+#define mmPA_SU_CNTL_STATUS            0x0C94
+#define mmPA_SC_CNTL_STATUS            0x0CA4
+#define mmPA_SU_DEBUG_CNTL             0x0C80
+#define mmPA_SU_DEBUG_DATA             0x0C81
+#define mmPA_SC_DEBUG_CNTL             0x0C82
+#define mmPA_SC_DEBUG_DATA             0x0C83
+
+
+// Registers from VGT block
+
+#define mmGFX_COPY_STATE               0x21F4
+#define mmVGT_DRAW_INITIATOR           0x21FC
+#define mmVGT_EVENT_INITIATOR          0x21F9
+#define mmVGT_DMA_BASE                 0x21FA
+#define mmVGT_DMA_SIZE                 0x21FB
+#define mmVGT_BIN_BASE                 0x21FE
+#define mmVGT_BIN_SIZE                 0x21FF
+#define mmVGT_CURRENT_BIN_ID_MIN       0x2207
+#define mmVGT_CURRENT_BIN_ID_MAX       0x2203
+#define mmVGT_IMMED_DATA               0x21FD
+#define mmVGT_MAX_VTX_INDX             0x2100
+#define mmVGT_MIN_VTX_INDX             0x2101
+#define mmVGT_INDX_OFFSET              0x2102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL  0x2316
+#define mmVGT_OUT_DEALLOC_CNTL         0x2317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103
+#define mmVGT_ENHANCE                  0x2294
+#define mmVGT_VTX_VECT_EJECT_REG       0x0C2C
+#define mmVGT_LAST_COPY_STATE          0x0C30
+#define mmVGT_DEBUG_CNTL               0x0C38
+#define mmVGT_DEBUG_DATA               0x0C39
+#define mmVGT_CNTL_STATUS              0x0C3C
+#define mmVGT_CRC_SQ_DATA              0x0C3A
+#define mmVGT_CRC_SQ_CTRL              0x0C3B
+#define mmVGT_PERFCOUNTER0_SELECT      0x0C48
+#define mmVGT_PERFCOUNTER1_SELECT      0x0C49
+#define mmVGT_PERFCOUNTER2_SELECT      0x0C4A
+#define mmVGT_PERFCOUNTER3_SELECT      0x0C4B
+#define mmVGT_PERFCOUNTER0_LOW         0x0C4C
+#define mmVGT_PERFCOUNTER1_LOW         0x0C4E
+#define mmVGT_PERFCOUNTER2_LOW         0x0C50
+#define mmVGT_PERFCOUNTER3_LOW         0x0C52
+#define mmVGT_PERFCOUNTER0_HI          0x0C4D
+#define mmVGT_PERFCOUNTER1_HI          0x0C4F
+#define mmVGT_PERFCOUNTER2_HI          0x0C51
+#define mmVGT_PERFCOUNTER3_HI          0x0C53
+
+
+// Registers from TP block
+
+#define mmTC_CNTL_STATUS               0x0E00
+#define mmTCR_CHICKEN                  0x0E02
+#define mmTCF_CHICKEN                  0x0E03
+#define mmTCM_CHICKEN                  0x0E04
+#define mmTCR_PERFCOUNTER0_SELECT      0x0E05
+#define mmTCR_PERFCOUNTER1_SELECT      0x0E08
+#define mmTCR_PERFCOUNTER0_HI          0x0E06
+#define mmTCR_PERFCOUNTER1_HI          0x0E09
+#define mmTCR_PERFCOUNTER0_LOW         0x0E07
+#define mmTCR_PERFCOUNTER1_LOW         0x0E0A
+#define mmTP_TC_CLKGATE_CNTL           0x0E17
+#define mmTPC_CNTL_STATUS              0x0E18
+#define mmTPC_DEBUG0                   0x0E19
+#define mmTPC_DEBUG1                   0x0E1A
+#define mmTPC_CHICKEN                  0x0E1B
+#define mmTP0_CNTL_STATUS              0x0E1C
+#define mmTP0_DEBUG                    0x0E1D
+#define mmTP0_CHICKEN                  0x0E1E
+#define mmTP0_PERFCOUNTER0_SELECT      0x0E1F
+#define mmTP0_PERFCOUNTER0_HI          0x0E20
+#define mmTP0_PERFCOUNTER0_LOW         0x0E21
+#define mmTP0_PERFCOUNTER1_SELECT      0x0E22
+#define mmTP0_PERFCOUNTER1_HI          0x0E23
+#define mmTP0_PERFCOUNTER1_LOW         0x0E24
+#define mmTCM_PERFCOUNTER0_SELECT      0x0E54
+#define mmTCM_PERFCOUNTER1_SELECT      0x0E57
+#define mmTCM_PERFCOUNTER0_HI          0x0E55
+#define mmTCM_PERFCOUNTER1_HI          0x0E58
+#define mmTCM_PERFCOUNTER0_LOW         0x0E56
+#define mmTCM_PERFCOUNTER1_LOW         0x0E59
+#define mmTCF_PERFCOUNTER0_SELECT      0x0E5A
+#define mmTCF_PERFCOUNTER1_SELECT      0x0E5D
+#define mmTCF_PERFCOUNTER2_SELECT      0x0E60
+#define mmTCF_PERFCOUNTER3_SELECT      0x0E63
+#define mmTCF_PERFCOUNTER4_SELECT      0x0E66
+#define mmTCF_PERFCOUNTER5_SELECT      0x0E69
+#define mmTCF_PERFCOUNTER6_SELECT      0x0E6C
+#define mmTCF_PERFCOUNTER7_SELECT      0x0E6F
+#define mmTCF_PERFCOUNTER8_SELECT      0x0E72
+#define mmTCF_PERFCOUNTER9_SELECT      0x0E75
+#define mmTCF_PERFCOUNTER10_SELECT     0x0E78
+#define mmTCF_PERFCOUNTER11_SELECT     0x0E7B
+#define mmTCF_PERFCOUNTER0_HI          0x0E5B
+#define mmTCF_PERFCOUNTER1_HI          0x0E5E
+#define mmTCF_PERFCOUNTER2_HI          0x0E61
+#define mmTCF_PERFCOUNTER3_HI          0x0E64
+#define mmTCF_PERFCOUNTER4_HI          0x0E67
+#define mmTCF_PERFCOUNTER5_HI          0x0E6A
+#define mmTCF_PERFCOUNTER6_HI          0x0E6D
+#define mmTCF_PERFCOUNTER7_HI          0x0E70
+#define mmTCF_PERFCOUNTER8_HI          0x0E73
+#define mmTCF_PERFCOUNTER9_HI          0x0E76
+#define mmTCF_PERFCOUNTER10_HI         0x0E79
+#define mmTCF_PERFCOUNTER11_HI         0x0E7C
+#define mmTCF_PERFCOUNTER0_LOW         0x0E5C
+#define mmTCF_PERFCOUNTER1_LOW         0x0E5F
+#define mmTCF_PERFCOUNTER2_LOW         0x0E62
+#define mmTCF_PERFCOUNTER3_LOW         0x0E65
+#define mmTCF_PERFCOUNTER4_LOW         0x0E68
+#define mmTCF_PERFCOUNTER5_LOW         0x0E6B
+#define mmTCF_PERFCOUNTER6_LOW         0x0E6E
+#define mmTCF_PERFCOUNTER7_LOW         0x0E71
+#define mmTCF_PERFCOUNTER8_LOW         0x0E74
+#define mmTCF_PERFCOUNTER9_LOW         0x0E77
+#define mmTCF_PERFCOUNTER10_LOW        0x0E7A
+#define mmTCF_PERFCOUNTER11_LOW        0x0E7D
+#define mmTCF_DEBUG                    0x0EC0
+#define mmTCA_FIFO_DEBUG               0x0EC1
+#define mmTCA_PROBE_DEBUG              0x0EC2
+#define mmTCA_TPC_DEBUG                0x0EC3
+#define mmTCB_CORE_DEBUG               0x0EC4
+#define mmTCB_TAG0_DEBUG               0x0EC5
+#define mmTCB_TAG1_DEBUG               0x0EC6
+#define mmTCB_TAG2_DEBUG               0x0EC7
+#define mmTCB_TAG3_DEBUG               0x0EC8
+#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9
+#define mmTCB_FETCH_GEN_WALKER_DEBUG   0x0ECB
+#define mmTCB_FETCH_GEN_PIPE0_DEBUG    0x0ECC
+#define mmTCD_INPUT0_DEBUG             0x0ED0
+#define mmTCD_DEGAMMA_DEBUG            0x0ED4
+#define mmTCD_DXTMUX_SCTARB_DEBUG      0x0ED5
+#define mmTCD_DXTC_ARB_DEBUG           0x0ED6
+#define mmTCD_STALLS_DEBUG             0x0ED7
+#define mmTCO_STALLS_DEBUG             0x0EE0
+#define mmTCO_QUAD0_DEBUG0             0x0EE1
+#define mmTCO_QUAD0_DEBUG1             0x0EE2
+
+
+// Registers from TC block
+
+
+
+// Registers from SQ block
+
+#define mmSQ_GPR_MANAGEMENT            0x0D00
+#define mmSQ_FLOW_CONTROL              0x0D01
+#define mmSQ_INST_STORE_MANAGMENT      0x0D02
+#define mmSQ_RESOURCE_MANAGMENT        0x0D03
+#define mmSQ_EO_RT                     0x0D04
+#define mmSQ_DEBUG_MISC                0x0D05
+#define mmSQ_ACTIVITY_METER_CNTL       0x0D06
+#define mmSQ_ACTIVITY_METER_STATUS     0x0D07
+#define mmSQ_INPUT_ARB_PRIORITY        0x0D08
+#define mmSQ_THREAD_ARB_PRIORITY       0x0D09
+#define mmSQ_VS_WATCHDOG_TIMER         0x0D0A
+#define mmSQ_PS_WATCHDOG_TIMER         0x0D0B
+#define mmSQ_INT_CNTL                  0x0D34
+#define mmSQ_INT_STATUS                0x0D35
+#define mmSQ_INT_ACK                   0x0D36
+#define mmSQ_DEBUG_INPUT_FSM           0x0DAE
+#define mmSQ_DEBUG_CONST_MGR_FSM       0x0DAF
+#define mmSQ_DEBUG_TP_FSM              0x0DB0
+#define mmSQ_DEBUG_FSM_ALU_0           0x0DB1
+#define mmSQ_DEBUG_FSM_ALU_1           0x0DB2
+#define mmSQ_DEBUG_EXP_ALLOC           0x0DB3
+#define mmSQ_DEBUG_PTR_BUFF            0x0DB4
+#define mmSQ_DEBUG_GPR_VTX             0x0DB5
+#define mmSQ_DEBUG_GPR_PIX             0x0DB6
+#define mmSQ_DEBUG_TB_STATUS_SEL       0x0DB7
+#define mmSQ_DEBUG_VTX_TB_0            0x0DB8
+#define mmSQ_DEBUG_VTX_TB_1            0x0DB9
+#define mmSQ_DEBUG_VTX_TB_STATUS_REG   0x0DBA
+#define mmSQ_DEBUG_VTX_TB_STATE_MEM    0x0DBB
+#define mmSQ_DEBUG_PIX_TB_0            0x0DBC
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
+#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
+#define mmSQ_DEBUG_PIX_TB_STATE_MEM    0x0DC1
+#define mmSQ_PERFCOUNTER0_SELECT       0x0DC8
+#define mmSQ_PERFCOUNTER1_SELECT       0x0DC9
+#define mmSQ_PERFCOUNTER2_SELECT       0x0DCA
+#define mmSQ_PERFCOUNTER3_SELECT       0x0DCB
+#define mmSQ_PERFCOUNTER0_LOW          0x0DCC
+#define mmSQ_PERFCOUNTER0_HI           0x0DCD
+#define mmSQ_PERFCOUNTER1_LOW          0x0DCE
+#define mmSQ_PERFCOUNTER1_HI           0x0DCF
+#define mmSQ_PERFCOUNTER2_LOW          0x0DD0
+#define mmSQ_PERFCOUNTER2_HI           0x0DD1
+#define mmSQ_PERFCOUNTER3_LOW          0x0DD2
+#define mmSQ_PERFCOUNTER3_HI           0x0DD3
+#define mmSX_PERFCOUNTER0_SELECT       0x0DD4
+#define mmSX_PERFCOUNTER0_LOW          0x0DD8
+#define mmSX_PERFCOUNTER0_HI           0x0DD9
+#define mmSQ_INSTRUCTION_ALU_0         0x5000
+#define mmSQ_INSTRUCTION_ALU_1         0x5001
+#define mmSQ_INSTRUCTION_ALU_2         0x5002
+#define mmSQ_INSTRUCTION_CF_EXEC_0     0x5080
+#define mmSQ_INSTRUCTION_CF_EXEC_1     0x5081
+#define mmSQ_INSTRUCTION_CF_EXEC_2     0x5082
+#define mmSQ_INSTRUCTION_CF_LOOP_0     0x5083
+#define mmSQ_INSTRUCTION_CF_LOOP_1     0x5084
+#define mmSQ_INSTRUCTION_CF_LOOP_2     0x5085
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087
+#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088
+#define mmSQ_INSTRUCTION_CF_ALLOC_0    0x5089
+#define mmSQ_INSTRUCTION_CF_ALLOC_1    0x508A
+#define mmSQ_INSTRUCTION_CF_ALLOC_2    0x508B
+#define mmSQ_INSTRUCTION_TFETCH_0      0x5043
+#define mmSQ_INSTRUCTION_TFETCH_1      0x5044
+#define mmSQ_INSTRUCTION_TFETCH_2      0x5045
+#define mmSQ_INSTRUCTION_VFETCH_0      0x5040
+#define mmSQ_INSTRUCTION_VFETCH_1      0x5041
+#define mmSQ_INSTRUCTION_VFETCH_2      0x5042
+#define mmSQ_CONSTANT_0                0x4000
+#define mmSQ_CONSTANT_1                0x4001
+#define mmSQ_CONSTANT_2                0x4002
+#define mmSQ_CONSTANT_3                0x4003
+#define mmSQ_FETCH_0                   0x4800
+#define mmSQ_FETCH_1                   0x4801
+#define mmSQ_FETCH_2                   0x4802
+#define mmSQ_FETCH_3                   0x4803
+#define mmSQ_FETCH_4                   0x4804
+#define mmSQ_FETCH_5                   0x4805
+#define mmSQ_CONSTANT_VFETCH_0         0x4806
+#define mmSQ_CONSTANT_VFETCH_1         0x4808
+#define mmSQ_CONSTANT_T2               0x480C
+#define mmSQ_CONSTANT_T3               0x4812
+#define mmSQ_CF_BOOLEANS               0x4900
+#define mmSQ_CF_LOOP                   0x4908
+#define mmSQ_CONSTANT_RT_0             0x4940
+#define mmSQ_CONSTANT_RT_1             0x4941
+#define mmSQ_CONSTANT_RT_2             0x4942
+#define mmSQ_CONSTANT_RT_3             0x4943
+#define mmSQ_FETCH_RT_0                0x4D40
+#define mmSQ_FETCH_RT_1                0x4D41
+#define mmSQ_FETCH_RT_2                0x4D42
+#define mmSQ_FETCH_RT_3                0x4D43
+#define mmSQ_FETCH_RT_4                0x4D44
+#define mmSQ_FETCH_RT_5                0x4D45
+#define mmSQ_CF_RT_BOOLEANS            0x4E00
+#define mmSQ_CF_RT_LOOP                0x4E14
+#define mmSQ_VS_PROGRAM                0x21F7
+#define mmSQ_PS_PROGRAM                0x21F6
+#define mmSQ_CF_PROGRAM_SIZE           0x2315
+#define mmSQ_INTERPOLATOR_CNTL         0x2182
+#define mmSQ_PROGRAM_CNTL              0x2180
+#define mmSQ_WRAPPING_0                0x2183
+#define mmSQ_WRAPPING_1                0x2184
+#define mmSQ_VS_CONST                  0x2307
+#define mmSQ_PS_CONST                  0x2308
+#define mmSQ_CONTEXT_MISC              0x2181
+#define mmSQ_CF_RD_BASE                0x21F5
+#define mmSQ_DEBUG_MISC_0              0x2309
+#define mmSQ_DEBUG_MISC_1              0x230A
+
+
+// Registers from SX block
+
+
+
+// Registers from MH block
+
+#define mmMH_ARBITER_CONFIG            0x0A40
+#define mmMH_CLNT_AXI_ID_REUSE         0x0A41
+#define mmMH_INTERRUPT_MASK            0x0A42
+#define mmMH_INTERRUPT_STATUS          0x0A43
+#define mmMH_INTERRUPT_CLEAR           0x0A44
+#define mmMH_AXI_ERROR                 0x0A45
+#define mmMH_PERFCOUNTER0_SELECT       0x0A46
+#define mmMH_PERFCOUNTER1_SELECT       0x0A4A
+#define mmMH_PERFCOUNTER0_CONFIG       0x0A47
+#define mmMH_PERFCOUNTER1_CONFIG       0x0A4B
+#define mmMH_PERFCOUNTER0_LOW          0x0A48
+#define mmMH_PERFCOUNTER1_LOW          0x0A4C
+#define mmMH_PERFCOUNTER0_HI           0x0A49
+#define mmMH_PERFCOUNTER1_HI           0x0A4D
+#define mmMH_DEBUG_CTRL                0x0A4E
+#define mmMH_DEBUG_DATA                0x0A4F
+#define mmMH_AXI_HALT_CONTROL          0x0A50
+#define mmMH_MMU_CONFIG                0x0040
+#define mmMH_MMU_VA_RANGE              0x0041
+#define mmMH_MMU_PT_BASE               0x0042
+#define mmMH_MMU_PAGE_FAULT            0x0043
+#define mmMH_MMU_TRAN_ERROR            0x0044
+#define mmMH_MMU_INVALIDATE            0x0045
+#define mmMH_MMU_MPU_BASE              0x0046
+#define mmMH_MMU_MPU_END               0x0047
+
+
+// Registers from RBBM block
+
+#define mmWAIT_UNTIL                   0x05C8
+#define mmRBBM_ISYNC_CNTL              0x05C9
+#define mmRBBM_STATUS                  0x05D0
+#define mmRBBM_DSPLY                   0x0391
+#define mmRBBM_RENDER_LATEST           0x0392
+#define mmRBBM_RTL_RELEASE             0x0000
+#define mmRBBM_PATCH_RELEASE           0x0001
+#define mmRBBM_AUXILIARY_CONFIG        0x0002
+#define mmRBBM_PERIPHID0               0x03F8
+#define mmRBBM_PERIPHID1               0x03F9
+#define mmRBBM_PERIPHID2               0x03FA
+#define mmRBBM_PERIPHID3               0x03FB
+#define mmRBBM_CNTL                    0x003B
+#define mmRBBM_SKEW_CNTL               0x003D
+#define mmRBBM_SOFT_RESET              0x003C
+#define mmRBBM_PM_OVERRIDE1            0x039C
+#define mmRBBM_PM_OVERRIDE2            0x039D
+#define mmGC_SYS_IDLE                  0x039E
+#define mmNQWAIT_UNTIL                 0x0394
+#define mmRBBM_DEBUG_OUT               0x03A0
+#define mmRBBM_DEBUG_CNTL              0x03A1
+#define mmRBBM_DEBUG                   0x039B
+#define mmRBBM_READ_ERROR              0x03B3
+#define mmRBBM_WAIT_IDLE_CLOCKS        0x03B2
+#define mmRBBM_INT_CNTL                0x03B4
+#define mmRBBM_INT_STATUS              0x03B5
+#define mmRBBM_INT_ACK                 0x03B6
+#define mmMASTER_INT_SIGNAL            0x03B7
+#define mmRBBM_PERFCOUNTER1_SELECT     0x0395
+#define mmRBBM_PERFCOUNTER1_LO         0x0397
+#define mmRBBM_PERFCOUNTER1_HI         0x0398
+
+
+// Registers from CP block
+
+#define mmCP_RB_BASE                   0x01C0
+#define mmCP_RB_CNTL                   0x01C1
+#define mmCP_RB_RPTR_ADDR              0x01C3
+#define mmCP_RB_RPTR                   0x01C4
+#define mmCP_RB_RPTR_WR                0x01C7
+#define mmCP_RB_WPTR                   0x01C5
+#define mmCP_RB_WPTR_DELAY             0x01C6
+#define mmCP_RB_WPTR_BASE              0x01C8
+#define mmCP_IB1_BASE                  0x0458
+#define mmCP_IB1_BUFSZ                 0x0459
+#define mmCP_IB2_BASE                  0x045A
+#define mmCP_IB2_BUFSZ                 0x045B
+#define mmCP_ST_BASE                   0x044D
+#define mmCP_ST_BUFSZ                  0x044E
+#define mmCP_QUEUE_THRESHOLDS          0x01D5
+#define mmCP_MEQ_THRESHOLDS            0x01D6
+#define mmCP_CSQ_AVAIL                 0x01D7
+#define mmCP_STQ_AVAIL                 0x01D8
+#define mmCP_MEQ_AVAIL                 0x01D9
+#define mmCP_CSQ_RB_STAT               0x01FD
+#define mmCP_CSQ_IB1_STAT              0x01FE
+#define mmCP_CSQ_IB2_STAT              0x01FF
+#define mmCP_NON_PREFETCH_CNTRS        0x0440
+#define mmCP_STQ_ST_STAT               0x0443
+#define mmCP_MEQ_STAT                  0x044F
+#define mmCP_MIU_TAG_STAT              0x0452
+#define mmCP_CMD_INDEX                 0x01DA
+#define mmCP_CMD_DATA                  0x01DB
+#define mmCP_ME_CNTL                   0x01F6
+#define mmCP_ME_STATUS                 0x01F7
+#define mmCP_ME_RAM_WADDR              0x01F8
+#define mmCP_ME_RAM_RADDR              0x01F9
+#define mmCP_ME_RAM_DATA               0x01FA
+#define mmCP_ME_RDADDR                 0x01EA
+#define mmCP_DEBUG                     0x01FC
+#define mmSCRATCH_REG0                 0x0578
+#define mmGUI_SCRATCH_REG0             0x0578
+#define mmSCRATCH_REG1                 0x0579
+#define mmGUI_SCRATCH_REG1             0x0579
+#define mmSCRATCH_REG2                 0x057A
+#define mmGUI_SCRATCH_REG2             0x057A
+#define mmSCRATCH_REG3                 0x057B
+#define mmGUI_SCRATCH_REG3             0x057B
+#define mmSCRATCH_REG4                 0x057C
+#define mmGUI_SCRATCH_REG4             0x057C
+#define mmSCRATCH_REG5                 0x057D
+#define mmGUI_SCRATCH_REG5             0x057D
+#define mmSCRATCH_REG6                 0x057E
+#define mmGUI_SCRATCH_REG6             0x057E
+#define mmSCRATCH_REG7                 0x057F
+#define mmGUI_SCRATCH_REG7             0x057F
+#define mmSCRATCH_UMSK                 0x01DC
+#define mmSCRATCH_ADDR                 0x01DD
+#define mmCP_ME_VS_EVENT_SRC           0x0600
+#define mmCP_ME_VS_EVENT_ADDR          0x0601
+#define mmCP_ME_VS_EVENT_DATA          0x0602
+#define mmCP_ME_VS_EVENT_ADDR_SWM      0x0603
+#define mmCP_ME_VS_EVENT_DATA_SWM      0x0604
+#define mmCP_ME_PS_EVENT_SRC           0x0605
+#define mmCP_ME_PS_EVENT_ADDR          0x0606
+#define mmCP_ME_PS_EVENT_DATA          0x0607
+#define mmCP_ME_PS_EVENT_ADDR_SWM      0x0608
+#define mmCP_ME_PS_EVENT_DATA_SWM      0x0609
+#define mmCP_ME_CF_EVENT_SRC           0x060A
+#define mmCP_ME_CF_EVENT_ADDR          0x060B
+#define mmCP_ME_CF_EVENT_DATA          0x060C
+#define mmCP_ME_NRT_ADDR               0x060D
+#define mmCP_ME_NRT_DATA               0x060E
+#define mmCP_ME_VS_FETCH_DONE_SRC      0x0612
+#define mmCP_ME_VS_FETCH_DONE_ADDR     0x0613
+#define mmCP_ME_VS_FETCH_DONE_DATA     0x0614
+#define mmCP_INT_CNTL                  0x01F2
+#define mmCP_INT_STATUS                0x01F3
+#define mmCP_INT_ACK                   0x01F4
+#define mmCP_PFP_UCODE_ADDR            0x00C0
+#define mmCP_PFP_UCODE_DATA            0x00C1
+#define mmCP_PERFMON_CNTL              0x0444
+#define mmCP_PERFCOUNTER_SELECT        0x0445
+#define mmCP_PERFCOUNTER_LO            0x0446
+#define mmCP_PERFCOUNTER_HI            0x0447
+#define mmCP_BIN_MASK_LO               0x0454
+#define mmCP_BIN_MASK_HI               0x0455
+#define mmCP_BIN_SELECT_LO             0x0456
+#define mmCP_BIN_SELECT_HI             0x0457
+#define mmCP_NV_FLAGS_0                0x01EE
+#define mmCP_NV_FLAGS_1                0x01EF
+#define mmCP_NV_FLAGS_2                0x01F0
+#define mmCP_NV_FLAGS_3                0x01F1
+#define mmCP_STATE_DEBUG_INDEX         0x01EC
+#define mmCP_STATE_DEBUG_DATA          0x01ED
+#define mmCP_PROG_COUNTER              0x044B
+#define mmCP_STAT                      0x047F
+#define mmBIOS_0_SCRATCH               0x0004
+#define mmBIOS_1_SCRATCH               0x0005
+#define mmBIOS_2_SCRATCH               0x0006
+#define mmBIOS_3_SCRATCH               0x0007
+#define mmBIOS_4_SCRATCH               0x0008
+#define mmBIOS_5_SCRATCH               0x0009
+#define mmBIOS_6_SCRATCH               0x000A
+#define mmBIOS_7_SCRATCH               0x000B
+#define mmBIOS_8_SCRATCH               0x0580
+#define mmBIOS_9_SCRATCH               0x0581
+#define mmBIOS_10_SCRATCH              0x0582
+#define mmBIOS_11_SCRATCH              0x0583
+#define mmBIOS_12_SCRATCH              0x0584
+#define mmBIOS_13_SCRATCH              0x0585
+#define mmBIOS_14_SCRATCH              0x0586
+#define mmBIOS_15_SCRATCH              0x0587
+#define mmCOHER_SIZE_PM4               0x0A29
+#define mmCOHER_BASE_PM4               0x0A2A
+#define mmCOHER_STATUS_PM4             0x0A2B
+#define mmCOHER_SIZE_HOST              0x0A2F
+#define mmCOHER_BASE_HOST              0x0A30
+#define mmCOHER_STATUS_HOST            0x0A31
+#define mmCOHER_DEST_BASE_0            0x2006
+#define mmCOHER_DEST_BASE_1            0x2007
+#define mmCOHER_DEST_BASE_2            0x2008
+#define mmCOHER_DEST_BASE_3            0x2009
+#define mmCOHER_DEST_BASE_4            0x200A
+#define mmCOHER_DEST_BASE_5            0x200B
+#define mmCOHER_DEST_BASE_6            0x200C
+#define mmCOHER_DEST_BASE_7            0x200D
+
+
+// Registers from SC block
+
+
+
+// Registers from BC block
+
+#define mmRB_SURFACE_INFO              0x2000
+#define mmRB_COLOR_INFO                0x2001
+#define mmRB_DEPTH_INFO                0x2002
+#define mmRB_STENCILREFMASK            0x210D
+#define mmRB_ALPHA_REF                 0x210E
+#define mmRB_COLOR_MASK                0x2104
+#define mmRB_BLEND_RED                 0x2105
+#define mmRB_BLEND_GREEN               0x2106
+#define mmRB_BLEND_BLUE                0x2107
+#define mmRB_BLEND_ALPHA               0x2108
+#define mmRB_FOG_COLOR                 0x2109
+#define mmRB_STENCILREFMASK_BF         0x210C
+#define mmRB_DEPTHCONTROL              0x2200
+#define mmRB_BLENDCONTROL              0x2201
+#define mmRB_COLORCONTROL              0x2202
+#define mmRB_MODECONTROL               0x2208
+#define mmRB_COLOR_DEST_MASK           0x2326
+#define mmRB_COPY_CONTROL              0x2318
+#define mmRB_COPY_DEST_BASE            0x2319
+#define mmRB_COPY_DEST_PITCH           0x231A
+#define mmRB_COPY_DEST_INFO            0x231B
+#define mmRB_COPY_DEST_PIXEL_OFFSET    0x231C
+#define mmRB_DEPTH_CLEAR               0x231D
+#define mmRB_SAMPLE_COUNT_CTL          0x2324
+#define mmRB_SAMPLE_COUNT_ADDR         0x2325
+#define mmRB_BC_CONTROL                0x0F01
+#define mmRB_EDRAM_INFO                0x0F02
+#define mmRB_CRC_RD_PORT               0x0F0C
+#define mmRB_CRC_CONTROL               0x0F0D
+#define mmRB_CRC_MASK                  0x0F0E
+#define mmRB_PERFCOUNTER0_SELECT       0x0F04
+#define mmRB_PERFCOUNTER0_LOW          0x0F08
+#define mmRB_PERFCOUNTER0_HI           0x0F09
+#define mmRB_TOTAL_SAMPLES             0x0F0F
+#define mmRB_ZPASS_SAMPLES             0x0F10
+#define mmRB_ZFAIL_SAMPLES             0x0F11
+#define mmRB_SFAIL_SAMPLES             0x0F12
+#define mmRB_DEBUG_0                   0x0F26
+#define mmRB_DEBUG_1                   0x0F27
+#define mmRB_DEBUG_2                   0x0F28
+#define mmRB_DEBUG_3                   0x0F29
+#define mmRB_DEBUG_4                   0x0F2A
+#define mmRB_FLAG_CONTROL              0x0F2B
+#define mmRB_BC_SPARES                 0x0F2C
+#define mmBC_DUMMY_CRAYRB_ENUMS        0x0F15
+#define mmBC_DUMMY_CRAYRB_MOREENUMS    0x0F16
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h
new file mode 100644
index 00000000000..17379dcfa0e
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h
@@ -0,0 +1,223 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_RANDOM_HEADER)
+#define _yamato_RANDOM_HEADER
+
+/*************************************************************
+ * THIS FILE IS AUTOMATICALLY CREATED.  DO NOT EDIT THIS FILE.
+ *************************************************************/
+/*******************************************************
+ * PA Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SU_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SC_PERFCNT_SELECT>;
+
+/*******************************************************
+ * VGT Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRIM_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SOURCE_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_FACENESS_CULL_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_INDEX_SIZE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_SMALL_INDEX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_PRE_FETCH_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DI_GRP_CULL_ENABLE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_EVENT_TYPE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_DMA_SWAP_MODE>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VGT_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCR_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TP_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCM_PERFCOUNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TCF_PERFCOUNT_SELECT>;
+
+/*******************************************************
+ * TC Enums
+ *******************************************************/
+/*******************************************************
+ * SQ Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SQ_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SX_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Abs_modifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Exporting>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ScalarOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SwizzleType>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<InputModifier>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredicateSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect1>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VectorOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<OperandSelect0>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Ressource_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Instruction_serial>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VC_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressing>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CFOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Allocation_type>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexInstOpcode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Addressmode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<TexCoordDenorm>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SrcSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DstSel>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MipFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<AnisoFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ArbitraryFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMagFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VolMinFilter>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<PredSelect>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SampleLocation>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<VertexMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<Sample_Cntl>;
+
+/*******************************************************
+ * SX Enums
+ *******************************************************/
+/*******************************************************
+ * MH Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MhPerfEncode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<MmuClntBeh>;
+
+/*******************************************************
+ * RBBM Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RBBM_PERFCOUNT1_SEL>;
+
+/*******************************************************
+ * CP Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CP_PERFCOUNT_SEL>;
+
+/*******************************************************
+ * SC Enums
+ *******************************************************/
+/*******************************************************
+ * BC Enums
+ *******************************************************/
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthformatX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareFrag>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CompareRef>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<StencilOp>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<BlendOpX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<CombFuncX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherModeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DitherTypeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramMode>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceEndian>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<EdramSizeX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<RB_PERFCNT_SELECT>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceSwap>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<DepthArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumber>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceFormat>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceTiling>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceArray>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<SurfaceNumberX>;
+
+template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM<ColorArrayX>;
+
+#endif /*_yamato_RANDOM_HEADER*/
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h
new file mode 100644
index 00000000000..bcc28f133b0
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h
@@ -0,0 +1,14280 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_REG_HEADER)
+#define _yamato_REG_HEADER
+
+    union PA_CL_VPORT_XSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_XSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_XSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_XOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_XOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_XOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_YSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_YSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_YOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_YOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_YOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZSCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VPORT_ZSCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VPORT_ZSCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VPORT_ZOFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VPORT_ZOFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VPORT_ZOFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_VTE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int                                 : 2;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                      VTX_W0_FMT : 1;
+        unsigned int                       VTX_Z_FMT : 1;
+        unsigned int                      VTX_XY_FMT : 1;
+        unsigned int                                 : 2;
+        unsigned int              VPORT_Z_OFFSET_ENA : 1;
+        unsigned int               VPORT_Z_SCALE_ENA : 1;
+        unsigned int              VPORT_Y_OFFSET_ENA : 1;
+        unsigned int               VPORT_Y_SCALE_ENA : 1;
+        unsigned int              VPORT_X_OFFSET_ENA : 1;
+        unsigned int               VPORT_X_SCALE_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CLIP_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int                    W_NAN_RETAIN : 1;
+        unsigned int                    Z_NAN_RETAIN : 1;
+        unsigned int                   XY_NAN_RETAIN : 1;
+        unsigned int                     VTX_KILL_OR : 1;
+        unsigned int             DIS_CLIP_ERR_DETECT : 1;
+        unsigned int               DX_CLIP_SPACE_DEF : 1;
+        unsigned int          BOUNDARY_EDGE_FLAG_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    CLIP_DISABLE : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_VERT_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_CLIP_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_GB_HORZ_DISC_ADJ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DATA_REGISTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DATA_REGISTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+        unsigned int                                 : 27;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 27;
+        unsigned int            CLIP_VTX_REORDER_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 28;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE0 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ECO_SPARE0 : 1;
+        unsigned int                      ECO_SPARE1 : 1;
+        unsigned int                      ECO_SPARE2 : 1;
+        unsigned int                      ECO_SPARE3 : 1;
+        unsigned int                                 : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_VTX_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PIX_CENTER : 1;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      QUANT_MODE : 3;
+        unsigned int                      ROUND_MODE : 2;
+        unsigned int                      PIX_CENTER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          HEIGHT : 16;
+        unsigned int                           WIDTH : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           WIDTH : 16;
+        unsigned int                          HEIGHT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POINT_MINMAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_SIZE : 16;
+        unsigned int                        MAX_SIZE : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MAX_SIZE : 16;
+        unsigned int                        MIN_SIZE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           WIDTH : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                           WIDTH : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_FACE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                       BASE_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_SC_MODE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CULL_FRONT : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                            FACE : 1;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int                                 : 1;
+        unsigned int                CLAMPED_FACENESS : 1;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int               FACE_WRITE_ENABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               FACE_WRITE_ENABLE : 1;
+        unsigned int                FACE_KILL_ENABLE : 1;
+        unsigned int              ZERO_AREA_FACENESS : 1;
+        unsigned int                CLAMPED_FACENESS : 1;
+        unsigned int                                 : 1;
+        unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1;
+        unsigned int            WAIT_RB_IDLE_ALL_TRI : 1;
+        unsigned int                                 : 1;
+        unsigned int               QUAD_ORDER_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int               MULTI_PRIM_IB_ENA : 1;
+        unsigned int                  PERSP_CORR_DIS : 1;
+        unsigned int              PROVOKING_VTX_LAST : 1;
+        unsigned int             LINE_STIPPLE_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int        VTX_WINDOW_OFFSET_ENABLE : 1;
+        unsigned int                     MSAA_ENABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int         POLY_OFFSET_PARA_ENABLE : 1;
+        unsigned int         POLY_OFFSET_BACK_ENABLE : 1;
+        unsigned int        POLY_OFFSET_FRONT_ENABLE : 1;
+        unsigned int             POLYMODE_BACK_PTYPE : 3;
+        unsigned int            POLYMODE_FRONT_PTYPE : 3;
+        unsigned int                       POLY_MODE : 2;
+        unsigned int                            FACE : 1;
+        unsigned int                       CULL_BACK : 1;
+        unsigned int                      CULL_FRONT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_FRONT_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_SCALE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SCALE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SCALE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_POLY_OFFSET_BACK_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OFFSET : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OFFSET : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 WINDOW_X_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_Y_OFFSET : 15;
+        unsigned int                                 : 1;
+        unsigned int                 WINDOW_X_OFFSET : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+        unsigned int                                 : 10;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                 MAX_SAMPLE_DIST : 4;
+        unsigned int                                 : 10;
+        unsigned int                MSAA_NUM_SAMPLES : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_AA_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         AA_MASK : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                         AA_MASK : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    LINE_PATTERN : 16;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                 AUTO_RESET_CNTL : 2;
+        unsigned int               PATTERN_BIT_ORDER : 1;
+        unsigned int                                 : 4;
+        unsigned int                    REPEAT_COUNT : 8;
+        unsigned int                    LINE_PATTERN : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BRES_CNTL : 8;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                      LAST_PIXEL : 1;
+        unsigned int               EXPAND_LINE_WIDTH : 1;
+        unsigned int                   USE_BRES_CNTL : 1;
+        unsigned int                       BRES_CNTL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 1;
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           WINDOW_OFFSET_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            TL_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_WINDOW_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                            BR_Y : 14;
+        unsigned int                                 : 2;
+        unsigned int                            BR_X : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_TL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TL_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            TL_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            TL_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_SCREEN_SCISSOR_BR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BR_X : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            BR_Y : 15;
+        unsigned int                                 : 1;
+        unsigned int                            BR_X : 15;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VIZ_QUERY_ENA : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                                 : 1;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int           KILL_PIX_POST_EARLY_Z : 1;
+        unsigned int                                 : 1;
+        unsigned int                    VIZ_QUERY_ID : 5;
+        unsigned int                   VIZ_QUERY_ENA : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_VIZ_QUERY_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STATUS_BITS : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     STATUS_BITS : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_LINE_STIPPLE_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CURRENT_PTR : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                   CURRENT_COUNT : 8;
+        unsigned int                                 : 4;
+        unsigned int                     CURRENT_PTR : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_CL_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         CL_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CL_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SU_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SU_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 31;
+        unsigned int                         SC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SC_BUSY : 1;
+        unsigned int                                 : 31;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SU_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SU_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SU_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           clip_ga_bc_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int                     ALWAYS_ZERO : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 12;
+        unsigned int       ccgen_to_clipcc_fifo_full : 1;
+        unsigned int      ccgen_to_clipcc_fifo_empty : 1;
+        unsigned int     vte_out_orig_fifo_fifo_full : 1;
+        unsigned int    vte_out_orig_fifo_fifo_empty : 1;
+        unsigned int     vte_out_clip_fifo_fifo_full : 1;
+        unsigned int    vte_out_clip_fifo_fifo_empty : 1;
+        unsigned int              clipcode_fifo_full : 1;
+        unsigned int        clipcode_fifo_fifo_empty : 1;
+        unsigned int          vgt_to_clips_fifo_full : 1;
+        unsigned int         vgt_to_clips_fifo_empty : 1;
+        unsigned int          vgt_to_clipp_fifo_full : 1;
+        unsigned int         vgt_to_clipp_fifo_empty : 1;
+        unsigned int         clip_to_outsm_fifo_full : 1;
+        unsigned int        clip_to_outsm_fifo_empty : 1;
+        unsigned int      primic_to_clprim_fifo_full : 1;
+        unsigned int     primic_to_clprim_fifo_empty : 1;
+        unsigned int            clip_to_ga_fifo_full : 1;
+        unsigned int           clip_to_ga_fifo_write : 1;
+        unsigned int            clip_ga_bc_fifo_full : 1;
+        unsigned int           clip_ga_bc_fifo_write : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int                     ALWAYS_ZERO : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 8;
+        unsigned int vte_out_clip_rd_vertex_store_indx : 2;
+        unsigned int             clip_vert_vte_valid : 3;
+        unsigned int clip_to_outsm_vertex_store_indx_0 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_1 : 4;
+        unsigned int clip_to_outsm_vertex_store_indx_2 : 4;
+        unsigned int    clip_to_outsm_null_primitive : 1;
+        unsigned int      clip_to_outsm_clipped_prim : 1;
+        unsigned int   clip_to_outsm_deallocate_slot : 3;
+        unsigned int clip_to_outsm_first_prim_of_slot : 1;
+        unsigned int     clip_to_outsm_end_of_packet : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO1 : 21;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int clipsm0_clprim_to_clip_prim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 7;
+        unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3;
+        unsigned int                    ALWAYS_ZERO1 : 21;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO0 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 6;
+        unsigned int clipsm0_clprim_to_clip_clip_code_or : 6;
+        unsigned int                    ALWAYS_ZERO1 : 12;
+        unsigned int clipsm0_clprim_to_clip_null_primitive : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_clip_primitive : 1;
+        unsigned int                    ALWAYS_ZERO3 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO0 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 24;
+        unsigned int    clipsm0_clprim_to_clip_event : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4;
+        unsigned int clipsm0_clprim_to_clip_event_id : 6;
+        unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int clipsm0_clprim_to_clip_state_var_indx : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            clprim_in_back_event : 1;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int     clip_priority_seq_indx_load : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int     clip_priority_seq_indx_load : 2;
+        unsigned int             outsm_clr_fifo_full : 1;
+        unsigned int            outsm_clr_fifo_empty : 1;
+        unsigned int        outsm_clr_rd_clipsm_wait : 1;
+        unsigned int      outsm_clr_rd_orig_vertices : 2;
+        unsigned int  clip_priority_seq_indx_out_cnt : 4;
+        unsigned int                 prim_back_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int clprim_in_back_vertex_store_indx_2 : 4;
+        unsigned int outputclprimtoclip_null_primitive : 1;
+        unsigned int            clprim_in_back_event : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int         clprim_in_back_event_id : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         clprim_in_back_event_id : 6;
+        unsigned int  clprim_in_back_deallocate_slot : 3;
+        unsigned int clprim_in_back_first_prim_of_slot : 1;
+        unsigned int    clprim_in_back_end_of_packet : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int   clprim_in_back_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4;
+        unsigned int                    ALWAYS_ZERO2 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+        unsigned int                     ALWAYS_ZERO : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ALWAYS_ZERO : 28;
+        unsigned int vertval_bits_vertex_vertex_store_msb : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int clip_priority_available_vte_out_clip : 2;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          primic_to_clprim_valid : 1;
+        unsigned int        clipcc_vertex_store_indx : 2;
+        unsigned int vertval_bits_vertex_cc_next_valid : 4;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int clip_priority_available_clip_verts : 5;
+        unsigned int          clip_vertex_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int clip_priority_available_vte_out_clip : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CLIPPER_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               sm0_clip_vert_cnt : 4;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int               sm0_current_state : 7;
+        unsigned int                    ALWAYS_ZERO0 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 5;
+        unsigned int               sm0_current_state : 7;
+        unsigned int    sm0_inv_to_clip_data_valid_0 : 1;
+        unsigned int    sm0_inv_to_clip_data_valid_1 : 1;
+        unsigned int             sm0_vertex_clip_cnt : 4;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int              sm0_prim_end_state : 7;
+        unsigned int               sm0_clip_vert_cnt : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   nan_kill_flag : 4;
+        unsigned int                position_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int           sx_pending_rd_aux_sel : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           sx_pending_rd_aux_sel : 1;
+        unsigned int           sx_pending_rd_aux_inc : 1;
+        unsigned int               sx_pending_rd_pci : 7;
+        unsigned int          sx_pending_rd_req_mask : 4;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int    sx_pending_rd_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 3;
+        unsigned int                   point_address : 3;
+        unsigned int                    ALWAYS_ZERO2 : 3;
+        unsigned int                position_address : 3;
+        unsigned int                   nan_kill_flag : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ALWAYS_ZERO3 : 2;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                param_cache_base : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                param_cache_base : 7;
+        unsigned int                    pasx_req_cnt : 2;
+        unsigned int                    ALWAYS_ZERO0 : 2;
+        unsigned int                         aux_sel : 1;
+        unsigned int                    ALWAYS_ZERO1 : 4;
+        unsigned int   statevar_bits_sxpa_aux_vector : 1;
+        unsigned int                 sx_receive_indx : 3;
+        unsigned int              sx_pending_advance : 1;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                  sx_to_pa_empty : 2;
+        unsigned int                    ALWAYS_ZERO3 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         sx_sent : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                          sx_aux : 1;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                req_active_verts : 7;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int        sx_pending_fifo_contents : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int        sx_pending_fifo_contents : 3;
+        unsigned int            sx_pending_fifo_full : 1;
+        unsigned int           sx_pending_fifo_empty : 1;
+        unsigned int         req_active_verts_loaded : 1;
+        unsigned int                    ALWAYS_ZERO0 : 4;
+        unsigned int       vgt_to_ccgen_active_verts : 2;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int     vgt_to_ccgen_state_var_indx : 1;
+        unsigned int                    ALWAYS_ZERO2 : 1;
+        unsigned int                req_active_verts : 7;
+        unsigned int                 sx_request_indx : 6;
+        unsigned int                          sx_aux : 1;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int                         sx_sent : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SXIFCCG_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    vertex_fifo_entriesavailable : 4;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int                   current_state : 2;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int                    ALWAYS_ZERO0 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    ALWAYS_ZERO0 : 10;
+        unsigned int          vgt_to_ccgen_fifo_full : 1;
+        unsigned int         vgt_to_ccgen_fifo_empty : 1;
+        unsigned int           sx0_receive_fifo_full : 1;
+        unsigned int          sx0_receive_fifo_empty : 1;
+        unsigned int                    ALWAYS_ZERO1 : 2;
+        unsigned int                vertex_fifo_full : 1;
+        unsigned int               vertex_fifo_empty : 1;
+        unsigned int                   current_state : 2;
+        unsigned int                    ALWAYS_ZERO2 : 4;
+        unsigned int             available_positions : 3;
+        unsigned int                    ALWAYS_ZERO3 : 1;
+        unsigned int    vertex_fifo_entriesavailable : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   su_cntl_state : 5;
+        unsigned int                     pmode_state : 6;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                       geom_busy : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       geom_busy : 1;
+        unsigned int                    su_cntl_busy : 1;
+        unsigned int                      pfifo_busy : 1;
+        unsigned int                     su_clip_rtr : 1;
+        unsigned int               su_clip_baryc_rtr : 1;
+        unsigned int                     geom_enable : 1;
+        unsigned int                       ge_stallb : 1;
+        unsigned int                     pmode_state : 6;
+        unsigned int                   su_cntl_state : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort0_gated_17_4 : 14;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort0_gated_17_4 : 14;
+        unsigned int              y_sort0_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort1_gated_17_4 : 14;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort1_gated_17_4 : 14;
+        unsigned int              y_sort1_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              y_sort2_gated_17_4 : 14;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int              x_sort2_gated_17_4 : 14;
+        unsigned int              y_sort2_gated_17_4 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort0_gated : 11;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                      type_gated : 3;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                       eop_gated : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                       eop_gated : 1;
+        unsigned int                     event_gated : 1;
+        unsigned int                pmode_prim_gated : 1;
+        unsigned int                      fpov_gated : 1;
+        unsigned int                      type_gated : 3;
+        unsigned int              diamond_rule_gated : 2;
+        unsigned int                    xmajor_gated : 1;
+        unsigned int              dealloc_slot_gated : 3;
+        unsigned int                   clipped_gated : 1;
+        unsigned int                   st_indx_gated : 3;
+        unsigned int                backfacing_gated : 1;
+        unsigned int                 null_prim_gated : 1;
+        unsigned int           attr_indx_sort0_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SETUP_DEBUG_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           attr_indx_sort2_gated : 11;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int                  event_id_gated : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                  event_id_gated : 5;
+        unsigned int             provoking_vtx_gated : 2;
+        unsigned int           attr_indx_sort1_gated : 11;
+        unsigned int           attr_indx_sort2_gated : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SC_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                   SC_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union PA_SC_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    pa_freeze_b1 : 1;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                                 : 17;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 17;
+        unsigned int                   incr_cntx_cnt : 1;
+        unsigned int                   decr_cntx_cnt : 1;
+        unsigned int                        cntx_cnt : 7;
+        unsigned int                     pa_sc_phase : 3;
+        unsigned int                     pa_sc_valid : 1;
+        unsigned int                    pa_freeze_b1 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        em_state : 3;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                                 : 21;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 21;
+        unsigned int                      pipe_valid : 1;
+        unsigned int                        ef_state : 2;
+        unsigned int                   ef_data_ready : 1;
+        unsigned int                 move_em1_to_em2 : 1;
+        unsigned int                  em2_data_ready : 1;
+        unsigned int                  em1_data_ready : 1;
+        unsigned int                        em_state : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rc_rtr_dly : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                                 : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int                        event_s1 : 1;
+        unsigned int                                 : 8;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 8;
+        unsigned int                        event_s1 : 1;
+        unsigned int                     event_id_s1 : 5;
+        unsigned int              pass_empty_prim_s1 : 1;
+        unsigned int              end_of_prim_s1_dly : 1;
+        unsigned int                                 : 5;
+        unsigned int                   phase_rts_dly : 1;
+        unsigned int                      stage0_rts : 1;
+        unsigned int               pre_stage1_rts_d1 : 1;
+        unsigned int               next_prim_rtr_dly : 1;
+        unsigned int               next_prim_rts_dly : 1;
+        unsigned int                        prim_rts : 1;
+        unsigned int                   pipe_freeze_b : 1;
+        unsigned int                                 : 1;
+        unsigned int            qmask_ff_alm_full_d1 : 1;
+        unsigned int                      rc_rtr_dly : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       x_curr_s1 : 11;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                                 : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 9;
+        unsigned int                       y_curr_s1 : 11;
+        unsigned int                       x_curr_s1 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        y_end_s1 : 14;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        y_dir_s1 : 1;
+        unsigned int                      y_start_s1 : 14;
+        unsigned int                        y_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        x_end_s1 : 14;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 2;
+        unsigned int                        x_dir_s1 : 1;
+        unsigned int                      x_start_s1 : 14;
+        unsigned int                        x_end_s1 : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      z_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                           state : 3;
+        unsigned int                   state_delayed : 3;
+        unsigned int                      data_valid : 1;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                   tiley_delayed : 9;
+        unsigned int                   tilex_delayed : 9;
+        unsigned int                    data_valid_d : 1;
+        unsigned int                      data_valid : 1;
+        unsigned int                   state_delayed : 3;
+        unsigned int                           state : 3;
+        unsigned int                   z_mask_needed : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                     xy_ff_empty : 1;
+        unsigned int                 qmcntl_ff_empty : 1;
+        unsigned int                      z_ff_empty : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      event_flag : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                       fposition : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                           state : 2;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                                 : 6;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 6;
+        unsigned int                     fifos_ready : 1;
+        unsigned int                           state : 2;
+        unsigned int              load_new_tile_data : 1;
+        unsigned int                        new_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int              first_quad_of_tile : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      tile_ff_re : 1;
+        unsigned int                      prim_ff_we : 1;
+        unsigned int                     qs_q0_valid : 1;
+        unsigned int                         qs_q0_x : 2;
+        unsigned int                         qs_q0_y : 2;
+        unsigned int                   qs_data_valid : 1;
+        unsigned int                      tile_ff_we : 1;
+        unsigned int                       last_tile : 1;
+        unsigned int                      sr_prim_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                      deallocate : 3;
+        unsigned int                      event_flag : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     sample_last : 1;
+        unsigned int                     sample_mask : 4;
+        unsigned int                        sample_y : 2;
+        unsigned int                        sample_x : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int                       fposition : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                                 : 3;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 3;
+        unsigned int              fw_prim_data_valid : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                       fposition : 1;
+        unsigned int                       sample_we : 1;
+        unsigned int              first_quad_of_prim : 1;
+        unsigned int               last_quad_of_prim : 1;
+        unsigned int               last_quad_of_tile : 1;
+        unsigned int                     num_samples : 2;
+        unsigned int                  rb_sc_samp_rtr : 1;
+        unsigned int               ez_sample_ff_full : 1;
+        unsigned int                      next_cycle : 2;
+        unsigned int                     sample_send : 1;
+        unsigned int                        sample_x : 2;
+        unsigned int                        sample_y : 2;
+        unsigned int                     sample_mask : 4;
+        unsigned int                     sample_last : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      rb_sc_send : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                      mask_state : 2;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_ready : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int        fetch_new_ez_sample_mask : 1;
+        unsigned int           fetch_new_sample_data : 1;
+        unsigned int                     drop_sample : 1;
+        unsigned int                      mask_ready : 1;
+        unsigned int                    next_ez_mask : 16;
+        unsigned int                      mask_state : 2;
+        unsigned int                  early_z_enable : 1;
+        unsigned int                 fifo_data_ready : 1;
+        unsigned int                   rb_sc_ez_mask : 4;
+        unsigned int                      rb_sc_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            combined_sample_mask : 16;
+        unsigned int                                 : 15;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 15;
+        unsigned int            combined_sample_mask : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            ez_sample_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_event : 1;
+        unsigned int                      next_state : 3;
+        unsigned int                           state : 3;
+        unsigned int                           stall : 1;
+        unsigned int                                 : 16;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 16;
+        unsigned int                           stall : 1;
+        unsigned int                           state : 3;
+        unsigned int                      next_state : 3;
+        unsigned int               packer_send_event : 1;
+        unsigned int                 packer_send_cmd : 1;
+        unsigned int               packer_send_quads : 1;
+        unsigned int               iterator_input_fz : 1;
+        unsigned int         pkr_fetch_new_prim_data : 1;
+        unsigned int              ez_prim_data_ready : 1;
+        unsigned int       pkr_fetch_new_sample_data : 1;
+        unsigned int            ez_sample_data_ready : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SC_DEBUG_12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SQ_iterator_free_buff : 1;
+        unsigned int                        event_id : 5;
+        unsigned int                      event_flag : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                                 : 7;
+        unsigned int                         trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         trigger : 1;
+        unsigned int                                 : 7;
+        unsigned int             iter_dx_end_of_prim : 1;
+        unsigned int                 one_clk_cmd_reg : 1;
+        unsigned int                        eopv_reg : 1;
+        unsigned int               iterator_SP_valid : 1;
+        unsigned int                  iter_phase_reg : 2;
+        unsigned int                  iter_phase_out : 2;
+        unsigned int                bc_output_xy_reg : 1;
+        unsigned int              bc_use_centers_reg : 1;
+        unsigned int                     iter_qdhit0 : 1;
+        unsigned int           iter_ds_end_of_vector : 1;
+        unsigned int            iter_ds_end_of_prim0 : 1;
+        unsigned int         iter_ds_one_clk_command : 1;
+        unsigned int               itercmdfifo_empty : 1;
+        unsigned int                itercmdfifo_full : 1;
+        unsigned int         itercmdfifo_busy_nc_dly : 1;
+        unsigned int                      event_flag : 1;
+        unsigned int                        event_id : 5;
+        unsigned int           SQ_iterator_free_buff : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GFX_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DRAW_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       PRIM_TYPE : 6;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                                 : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int                     NUM_INDICES : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     NUM_INDICES : 16;
+        unsigned int                 GRP_CULL_ENABLE : 1;
+        unsigned int           PRE_FETCH_CULL_ENABLE : 1;
+        unsigned int                     SMALL_INDEX : 1;
+        unsigned int                         NOT_EOP : 1;
+        unsigned int                      INDEX_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int            FACENESS_CULL_SELECT : 2;
+        unsigned int                   SOURCE_SELECT : 2;
+        unsigned int                       PRIM_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_EVENT_INITIATOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EVENT_TYPE : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                      EVENT_TYPE : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DMA_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                       SWAP_MODE : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SWAP_MODE : 2;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_BASE_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_BASE_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_BIN_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       NUM_WORDS : 24;
+        unsigned int                                 : 6;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                  FACENESS_RESET : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  FACENESS_RESET : 1;
+        unsigned int                  FACENESS_FETCH : 1;
+        unsigned int                                 : 6;
+        unsigned int                       NUM_WORDS : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MIN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CURRENT_BIN_ID_MAX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          COLUMN : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      GUARD_BAND : 3;
+        unsigned int                             ROW : 3;
+        unsigned int                          COLUMN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_IMMED_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MAX_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MAX_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MAX_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MIN_VTX_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MIN_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        MIN_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_INDX_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INDX_OFFSET : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                     INDX_OFFSET : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VERTEX_REUSE_BLOCK_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                 VTX_REUSE_DEPTH : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_OUT_DEALLOC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEALLOC_DIST : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    DEALLOC_DIST : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_MULTI_PRIM_IB_RESET_INDX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESET_INDX : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      RESET_INDX : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_ENHANCE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            MISC : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                            MISC : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_VTX_VECT_EJECT_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PRIM_COUNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                      PRIM_COUNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_LAST_COPY_STATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SRC_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                    DST_STATE_ID : 1;
+        unsigned int                                 : 15;
+        unsigned int                    SRC_STATE_ID : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VGT_DEBUG_INDX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                  VGT_DEBUG_INDX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int               VGT_OUT_INDX_BUSY : 1;
+        unsigned int                    VGT_OUT_BUSY : 1;
+        unsigned int                     VGT_PT_BUSY : 1;
+        unsigned int                    VGT_BIN_BUSY : 1;
+        unsigned int                     VGT_VR_BUSY : 1;
+        unsigned int                    VGT_GRP_BUSY : 1;
+        unsigned int                VGT_DMA_REQ_BUSY : 1;
+        unsigned int                    VGT_DMA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     te_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                   VGT_RBBM_busy : 1;
+        unsigned int            VGT_RBBM_no_dma_busy : 1;
+        unsigned int         rbbm_skid_fifo_busy_out : 1;
+        unsigned int                        vgt_busy : 1;
+        unsigned int               vgt_busy_extended : 1;
+        unsigned int                 vgt_no_dma_busy : 1;
+        unsigned int        vgt_no_dma_busy_extended : 1;
+        unsigned int                       rbiu_busy : 1;
+        unsigned int           rbiu_dma_request_busy : 1;
+        unsigned int                        dma_busy : 1;
+        unsigned int                        grp_busy : 1;
+        unsigned int                grp_backend_busy : 1;
+        unsigned int                        out_busy : 1;
+        unsigned int                dma_request_busy : 1;
+        unsigned int                     vr_grp_busy : 1;
+        unsigned int                     pt_grp_busy : 1;
+        unsigned int                     te_grp_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                out_te_data_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  mh_vgt_tag_7_q : 1;
+        unsigned int                     VGT_SQ_send : 1;
+        unsigned int                      SQ_VGT_rtr : 1;
+        unsigned int              VGT_PA_clip_v_send : 1;
+        unsigned int               PA_VGT_clip_v_rtr : 1;
+        unsigned int              VGT_PA_clip_p_send : 1;
+        unsigned int               PA_VGT_clip_p_rtr : 1;
+        unsigned int              VGT_PA_clip_s_send : 1;
+        unsigned int               PA_VGT_clip_s_rtr : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                      MH_VGT_rtr : 1;
+        unsigned int               rbiu_grp_di_valid : 1;
+        unsigned int                grp_rbiu_di_read : 1;
+        unsigned int                   dma_grp_valid : 1;
+        unsigned int                    grp_dma_read : 1;
+        unsigned int                    grp_vr_valid : 1;
+        unsigned int                     vr_grp_read : 1;
+        unsigned int                    grp_pt_valid : 1;
+        unsigned int                     pt_grp_read : 1;
+        unsigned int                    grp_te_valid : 1;
+        unsigned int                     te_grp_read : 1;
+        unsigned int               vr_out_indx_valid : 1;
+        unsigned int                out_vr_indx_read : 1;
+        unsigned int               vr_out_prim_valid : 1;
+        unsigned int                out_vr_prim_read : 1;
+        unsigned int               pt_out_indx_valid : 1;
+        unsigned int                out_pt_data_read : 1;
+        unsigned int               pt_out_prim_valid : 1;
+        unsigned int                out_pt_prim_read : 1;
+        unsigned int               te_out_data_valid : 1;
+        unsigned int                out_te_data_read : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      vgt_clk_en : 1;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                reg_fifos_clk_en : 1;
+        unsigned int                      vgt_clk_en : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG8 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG9 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     grp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int                      read_block : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int                   selected_data : 8;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                           gap_q : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int                     grp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     grp_trigger : 1;
+        unsigned int               temp_mini_reset_x : 1;
+        unsigned int               temp_mini_reset_y : 1;
+        unsigned int               temp_mini_reset_z : 1;
+        unsigned int                           gap_q : 1;
+        unsigned int                 mask_input_data : 8;
+        unsigned int                   selected_data : 8;
+        unsigned int               last_bit_end_di_q : 1;
+        unsigned int               last_bit_enable_q : 1;
+        unsigned int          grp_bgrp_last_bit_read : 1;
+        unsigned int                      read_block : 1;
+        unsigned int                       bin_valid : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_cull_enable_t0 : 1;
+        unsigned int  temp_derived_di_small_index_t0 : 1;
+        unsigned int    temp_derived_di_prim_type_t0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            shifter_byte_count_q : 5;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int                input_data_valid : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                 destination_rtr : 1;
+        unsigned int                  shift_vect_rtr : 1;
+        unsigned int                  extract_vector : 1;
+        unsigned int             last_decr_of_packet : 1;
+        unsigned int            last_shift_of_packet : 1;
+        unsigned int     loading_di_requires_shifter : 1;
+        unsigned int             read_draw_initiator : 1;
+        unsigned int                 di_event_flag_q : 1;
+        unsigned int           di_first_group_flag_q : 1;
+        unsigned int shifter_waiting_for_first_load_q : 1;
+        unsigned int                  di_state_sel_q : 1;
+        unsigned int              shifter_first_load : 1;
+        unsigned int          space_avail_from_shift : 1;
+        unsigned int      next_shift_is_vect_1_pre_d : 1;
+        unsigned int          next_shift_is_vect_1_d : 1;
+        unsigned int          next_shift_is_vect_1_q : 1;
+        unsigned int                 input_data_xfer : 1;
+        unsigned int                input_data_valid : 1;
+        unsigned int               right_word_indx_q : 5;
+        unsigned int            shifter_byte_count_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              di_index_counter_q : 16;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int              current_source_sel : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              current_source_sel : 2;
+        unsigned int                  di_prim_type_q : 6;
+        unsigned int            shift_amount_extract : 4;
+        unsigned int         shift_amount_no_extract : 4;
+        unsigned int              di_index_counter_q : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              current_source_sel : 2;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int current_small_stride_shift_limit_q : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int current_small_stride_shift_limit_q : 5;
+        unsigned int next_small_stride_shift_limit_q : 5;
+        unsigned int                  input_data_msw : 5;
+        unsigned int                  input_data_lsw : 5;
+        unsigned int                  input_data_cnt : 5;
+        unsigned int                left_word_indx_q : 5;
+        unsigned int              current_source_sel : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   next_stride_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                current_stride_d : 5;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                current_stride_d : 5;
+        unsigned int                current_stride_q : 5;
+        unsigned int                 current_shift_d : 5;
+        unsigned int                 current_shift_q : 5;
+        unsigned int                   next_stride_d : 5;
+        unsigned int                   next_stride_q : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int        top_di_grp_cull_enable_q : 1;
+        unsigned int    top_di_pre_fetch_cull_enable : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int        bgrp_grp_byte_mask_rdata : 8;
+        unsigned int                  load_empty_reg : 1;
+        unsigned int                ast_bit_block2_q : 1;
+        unsigned int                last_bit_block_q : 1;
+        unsigned int                  dbl_last_bit_q : 1;
+        unsigned int                 prev_last_bit_q : 1;
+        unsigned int                    old_state_en : 1;
+        unsigned int                     old_state_q : 1;
+        unsigned int                 current_state_q : 1;
+        unsigned int                    rst_last_bit : 1;
+        unsigned int              bgrp_grp_bin_valid : 1;
+        unsigned int              bgrp_dma_mask_kill : 1;
+        unsigned int          bgrp_byte_mask_fifo_we : 1;
+        unsigned int        bgrp_byte_mask_fifo_re_q : 1;
+        unsigned int       bgrp_byte_mask_fifo_empty : 1;
+        unsigned int        bgrp_byte_mask_fifo_full : 1;
+        unsigned int         bgrp_cull_fetch_fifo_we : 1;
+        unsigned int        dma_bgrp_cull_fetch_read : 1;
+        unsigned int      bgrp_cull_fetch_fifo_empty : 1;
+        unsigned int       bgrp_cull_fetch_fifo_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     save_read_q : 1;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                    bgrp_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    bgrp_trigger : 1;
+        unsigned int                   min_msk_ptr_q : 7;
+        unsigned int                   max_msk_ptr_q : 7;
+        unsigned int                 roll_over_msk_q : 1;
+        unsigned int                 to_second_reg_q : 1;
+        unsigned int          save_byte_mask_data1_q : 1;
+        unsigned int          save_byte_mask_data2_q : 1;
+        unsigned int         save_cull_fetch_data1_q : 1;
+        unsigned int         save_cull_fetch_data2_q : 1;
+        unsigned int      bgrp_cull_fetch_fifo_wdata : 1;
+        unsigned int                 check_first_reg : 1;
+        unsigned int                check_second_reg : 1;
+        unsigned int               first_reg_first_q : 1;
+        unsigned int                    reset_bit1_q : 1;
+        unsigned int                    reset_bit2_q : 1;
+        unsigned int                  cull_prim_true : 1;
+        unsigned int                   grp_indx_size : 2;
+        unsigned int                   extend_read_q : 1;
+        unsigned int                     save_read_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1;
+        unsigned int     bgrp_dma_di_grp_cull_enable : 1;
+        unsigned int              have_valid_dma_req : 1;
+        unsigned int              have_valid_bin_req : 1;
+        unsigned int                    dma_req_xfer : 1;
+        unsigned int             fetch_cull_not_used : 1;
+        unsigned int                   start_bin_req : 1;
+        unsigned int                   bin_mem_empty : 1;
+        unsigned int                      bin_ram_re : 1;
+        unsigned int                      bin_ram_we : 1;
+        unsigned int                    bin_mem_full : 1;
+        unsigned int            dma_data_fifo_mem_we : 1;
+        unsigned int            dma_data_fifo_mem_re : 1;
+        unsigned int                   dma_mem_empty : 1;
+        unsigned int                      dma_ram_we : 1;
+        unsigned int                      dma_ram_re : 1;
+        unsigned int                    dma_mem_full : 1;
+        unsigned int     dma_bgrp_dma_data_fifo_rptr : 2;
+        unsigned int      dma_bgrp_byte_mask_fifo_re : 1;
+        unsigned int         dma_data_fifo_mem_waddr : 6;
+        unsigned int         dma_data_fifo_mem_raddr : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            prim_side_indx_valid : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                       hold_prim : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                     out_trigger : 1;
+        unsigned int        buffered_prim_type_event : 5;
+        unsigned int            clip_p_pre_hold_prim : 1;
+        unsigned int            clip_s_pre_hold_prim : 1;
+        unsigned int             start_of_vtx_vector : 1;
+        unsigned int                        sent_cnt : 4;
+        unsigned int                       hold_prim : 1;
+        unsigned int                indx_buffer_full : 1;
+        unsigned int                  indx_buffer_we : 1;
+        unsigned int                  indx_buffer_re : 1;
+        unsigned int               indx_buffer_empty : 1;
+        unsigned int                prim_buffer_full : 1;
+        unsigned int                  prim_buffer_we : 1;
+        unsigned int                  prim_buffer_re : 1;
+        unsigned int               prim_buffer_empty : 1;
+        unsigned int             indx_side_fifo_full : 1;
+        unsigned int               indx_side_fifo_we : 1;
+        unsigned int               indx_side_fifo_re : 1;
+        unsigned int            indx_side_fifo_empty : 1;
+        unsigned int            prim_side_indx_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       null_terminate_vtx_vector : 1;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int                    new_packet_q : 1;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int                                 : 4;
+        unsigned int                     out_trigger : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     out_trigger : 1;
+        unsigned int                                 : 4;
+        unsigned int            buffered_thread_size : 1;
+        unsigned int           prim_buffer_empty_mux : 1;
+        unsigned int           buffered_prim_eop_mux : 1;
+        unsigned int                insert_null_prim : 1;
+        unsigned int            inserted_null_prim_q : 1;
+        unsigned int         num_new_unique_rel_indx : 2;
+        unsigned int                  new_allocate_q : 1;
+        unsigned int                    new_packet_q : 1;
+        unsigned int         curr_dealloc_distance_q : 4;
+        unsigned int               int_vtx_counter_q : 4;
+        unsigned int         curr_slot_in_vtx_vect_q : 3;
+        unsigned int                 alloc_counter_q : 3;
+        unsigned int      prim_end_of_vtx_vect_flags : 3;
+        unsigned int       null_terminate_vtx_vector : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_CRC_SQ_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             CRC : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             CRC : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union VGT_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   L2_INVALIDATE : 1;
+        unsigned int                                 : 17;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 11;
+        unsigned int                         TC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 11;
+        unsigned int                  TC_L2_HIT_MISS : 2;
+        unsigned int                                 : 17;
+        unsigned int                   L2_INVALIDATE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           SPARE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int                           SPARE : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 23;
+        unsigned int                ETC_COLOR_ENDIAN : 1;
+        unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCR_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP_TC_CLKGATE_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TP_BUSY_EXTEND : 3;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                  TC_BUSY_EXTEND : 3;
+        unsigned int                  TP_BUSY_EXTEND : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  TPC_INPUT_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int                        TPC_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                       TP_SQ_DEC : 1;
+        unsigned int               TA_TF_TC_FIFO_REN : 1;
+        unsigned int                       TA_TF_RTS : 1;
+        unsigned int                       TA_TB_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                    TA_TB_TT_RTS : 1;
+        unsigned int                       TA_TB_RTS : 1;
+        unsigned int                       TW_TA_RTR : 1;
+        unsigned int                  TW_TA_LAST_RTS : 1;
+        unsigned int                    TW_TA_TT_RTS : 1;
+        unsigned int                       TW_TA_RTS : 1;
+        unsigned int                       TF_TW_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TF_TW_STATE_RTS : 1;
+        unsigned int                       TF_TW_RTS : 1;
+        unsigned int                  TPC_BLEND_BUSY : 1;
+        unsigned int               TPC_OUT_FIFO_BUSY : 1;
+        unsigned int             TPC_BLEND_PIPE_BUSY : 1;
+        unsigned int                TPC_RR_FIFO_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                TPC_ALIGNER_BUSY : 1;
+        unsigned int             TPC_ALIGN_FIFO_BUSY : 1;
+        unsigned int           TPC_ALIGNER_PIPE_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 TPC_WALKER_BUSY : 1;
+        unsigned int              TPC_WALK_FIFO_BUSY : 1;
+        unsigned int            TPC_WALKER_PIPE_BUSY : 1;
+        unsigned int             TPC_FETCH_FIFO_BUSY : 1;
+        unsigned int             TPC_STATE_FIFO_BUSY : 1;
+        unsigned int                TPC_TC_FIFO_BUSY : 1;
+        unsigned int                  TPC_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        LOD_CNTL : 2;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                                 : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                    SQ_TP_WAKEUP : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SQ_TP_WAKEUP : 1;
+        unsigned int                      TPC_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int                   ALIGNER_STATE : 2;
+        unsigned int                    WALKER_STATE : 10;
+        unsigned int                                 : 3;
+        unsigned int             PREV_TC_STATE_VALID : 1;
+        unsigned int                                 : 1;
+        unsigned int                    ALIGNER_CNTL : 3;
+        unsigned int                     WALKER_CNTL : 4;
+        unsigned int                          IC_CTR : 2;
+        unsigned int                        LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          UNUSED : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                          UNUSED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TPC_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 BLEND_PRECISION : 1;
+        unsigned int                           SPARE : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 31;
+        unsigned int                 BLEND_PRECISION : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CNTL_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TP_INPUT_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                         TP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         TP_BUSY : 1;
+        unsigned int                       TB_TO_RTS : 1;
+        unsigned int                  TB_TT_TT_RESET : 1;
+        unsigned int                       TB_TT_RTS : 1;
+        unsigned int                    TF_TB_TT_RTS : 1;
+        unsigned int                       TF_TB_RTS : 1;
+        unsigned int                    AL_TF_TT_RTS : 1;
+        unsigned int                       AL_TF_RTS : 1;
+        unsigned int                    FA_AL_TT_RTS : 1;
+        unsigned int                       FA_AL_RTS : 1;
+        unsigned int                    TA_FA_TT_RTS : 1;
+        unsigned int                       TA_FA_RTS : 1;
+        unsigned int                       FL_TA_RTS : 1;
+        unsigned int                       LA_FL_RTS : 1;
+        unsigned int                       LC_LA_RTS : 1;
+        unsigned int                       IN_LC_RTS : 1;
+        unsigned int                                 : 1;
+        unsigned int                  TP_OUTPUT_BUSY : 1;
+        unsigned int                TP_OUT_FIFO_BUSY : 1;
+        unsigned int                   TP_BLEND_BUSY : 1;
+        unsigned int                 TP_HICOLOR_BUSY : 1;
+        unsigned int                      TP_TT_BUSY : 1;
+        unsigned int                TP_CH_BLEND_BUSY : 1;
+        unsigned int                   TP_FETCH_BUSY : 1;
+        unsigned int                 TP_RR_FIFO_BUSY : 1;
+        unsigned int                 TP_TC_FIFO_BUSY : 1;
+        unsigned int                 TP_ALIGNER_BUSY : 1;
+        unsigned int              TP_ALIGN_FIFO_BUSY : 1;
+        unsigned int                    TP_ADDR_BUSY : 1;
+        unsigned int                TP_LOD_FIFO_BUSY : 1;
+        unsigned int                     TP_LOD_BUSY : 1;
+        unsigned int                   TP_INPUT_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      Q_LOD_CNTL : 2;
+        unsigned int                                 : 1;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                  Q_ALIGNER_CNTL : 3;
+        unsigned int                   Q_WALKER_CNTL : 4;
+        unsigned int                       TP_CLK_EN : 1;
+        unsigned int                     PERF_CLK_EN : 1;
+        unsigned int                      REG_CLK_EN : 1;
+        unsigned int            FL_TA_ADDRESSER_CNTL : 17;
+        unsigned int                  Q_SQ_TP_WAKEUP : 1;
+        unsigned int                                 : 1;
+        unsigned int                      Q_LOD_CNTL : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_CHICKEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TT_MODE : 1;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                           SPARE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 30;
+        unsigned int             VFETCH_ADDRESS_MODE : 1;
+        unsigned int                         TT_MODE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TP0_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCM_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              PERFCOUNTER_SELECT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int              PERFCOUNTER_SELECT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERFCOUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERFCOUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER4_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER5_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER6_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER7_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER8_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER9_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER10_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_PERFCOUNTER11_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PERFCOUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCF_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 6;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TPC_full : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                         tca_rts : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                         tca_rts : 1;
+        unsigned int                   tca_state_rts : 1;
+        unsigned int                     not_TPC_rtr : 1;
+        unsigned int                        TPC_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        TP0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                       PF0_stall : 1;
+        unsigned int                   TCA_TCB_stall : 1;
+        unsigned int                  TCB_miss_stall : 1;
+        unsigned int                    TCB_ff_stall : 1;
+        unsigned int                 not_TCB_TCO_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FG0_rtr : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                   not_MH_TC_rtr : 1;
+        unsigned int                                 : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_FIFO_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        tp0_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tpc_full : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                      FW_tpc_rts : 1;
+        unsigned int                  not_FW_tpc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int                         FW_rts0 : 1;
+        unsigned int                                 : 3;
+        unsigned int                     not_FW_rtr0 : 1;
+        unsigned int                         FW_full : 1;
+        unsigned int                   load_tp_fifos : 1;
+        unsigned int                   load_tpc_fifo : 1;
+        unsigned int                        tpc_full : 1;
+        unsigned int                                 : 3;
+        unsigned int                        tp0_full : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_PROBE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               ProbeFilter_stall : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int               ProbeFilter_stall : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCA_TPC_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                                 : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 18;
+        unsigned int                 capture_tca_rts : 1;
+        unsigned int                captue_state_rts : 1;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_CORE_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       access512 : 1;
+        unsigned int                           tiled : 1;
+        unsigned int                                 : 2;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 1;
+        unsigned int                          format : 6;
+        unsigned int                                 : 2;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 3;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                sector_format512 : 3;
+        unsigned int                                 : 3;
+        unsigned int                   sector_format : 5;
+        unsigned int                                 : 2;
+        unsigned int                          format : 6;
+        unsigned int                                 : 1;
+        unsigned int                          opcode : 3;
+        unsigned int                                 : 2;
+        unsigned int                           tiled : 1;
+        unsigned int                       access512 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG1_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG2_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_TAG3_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  mem_read_cycle : 10;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                      miss_stall : 1;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      max_misses : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      max_misses : 3;
+        unsigned int                  num_feee_lines : 5;
+        unsigned int                      miss_stall : 1;
+        unsigned int                                 : 2;
+        unsigned int                tag_access_cycle : 9;
+        unsigned int                                 : 2;
+        unsigned int                  mem_read_cycle : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       left_done : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int                     update_left : 1;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int                    valid_left_q : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                    valid_left_q : 1;
+        unsigned int              sector_mask_left_q : 16;
+        unsigned int        sector_mask_left_count_q : 5;
+        unsigned int                     update_left : 1;
+        unsigned int                no_sectors_to_go : 1;
+        unsigned int         one_sector_to_go_left_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                  fg0_sends_left : 1;
+        unsigned int                                 : 1;
+        unsigned int                       left_done : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_WALKER_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                                 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                            busy : 1;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                setquads_to_send : 4;
+        unsigned int                            busy : 1;
+        unsigned int                   ff_fg_type512 : 3;
+        unsigned int                   right_eq_left : 1;
+        unsigned int                                 : 3;
+        unsigned int                    set_sel_left : 2;
+        unsigned int                   quad_sel_left : 2;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCB_FETCH_GEN_PIPE0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     tc0_arb_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                            busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         valid_q : 1;
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                         arb_RTR : 1;
+        unsigned int                                 : 1;
+        unsigned int                         valid_q : 1;
+        unsigned int                        mc_sel_q : 2;
+        unsigned int                         ga_busy : 1;
+        unsigned int                        fgo_busy : 1;
+        unsigned int                            busy : 1;
+        unsigned int             tc_arb_request_type : 2;
+        unsigned int                tc_arb_fmsopcode : 5;
+        unsigned int                   tc_arb_format : 12;
+        unsigned int                                 : 1;
+        unsigned int                      ga_out_rts : 1;
+        unsigned int                                 : 1;
+        unsigned int                     tc0_arb_rts : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_INPUT0_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                                 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                      ipbuf_busy : 1;
+        unsigned int                  ipbuf_dxt_send : 1;
+        unsigned int                         ip_send : 1;
+        unsigned int                    last_send_q1 : 1;
+        unsigned int                          cnt_q1 : 2;
+        unsigned int                        valid_q1 : 1;
+        unsigned int                                 : 2;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DEGAMMA_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                     dgmm_pstate : 1;
+        unsigned int                      dgmm_stall : 1;
+        unsigned int                  dgmm_ctrl_send : 1;
+        unsigned int             dgmm_ctrl_last_send : 1;
+        unsigned int                 dgmm_ctrl_dgmm8 : 1;
+        unsigned int             dgmm_ftfconv_dgmmen : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTMUX_SCTARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 9;
+        unsigned int                          pstate : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                                 : 3;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int                                 : 3;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 6;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   dcmp_mux_send : 1;
+        unsigned int                dxtc_dgmmpd_send : 1;
+        unsigned int           dxtc_dgmmpd_last_send : 1;
+        unsigned int                                 : 6;
+        unsigned int               dxtc_sctrarb_send : 1;
+        unsigned int                                 : 3;
+        unsigned int             sctrmx0_sctrarb_rts : 1;
+        unsigned int            sctrarb_multcyl_send : 1;
+        unsigned int                                 : 3;
+        unsigned int                        dxtc_rtr : 1;
+        unsigned int                      sctrmx_rtr : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                                 : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_DXTC_ARB_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int                        n0_stall : 1;
+        unsigned int                          pstate : 1;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int                 n0_dxt2_4_types : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 n0_dxt2_4_types : 1;
+        unsigned int                 arb_dcmp01_send : 1;
+        unsigned int               arb_dcmp01_format : 12;
+        unsigned int            arb_dcmp01_cacheline : 6;
+        unsigned int               arb_dcmp01_sector : 3;
+        unsigned int                  arb_dcmp01_cnt : 2;
+        unsigned int            arb_dcmp01_last_send : 1;
+        unsigned int                          pstate : 1;
+        unsigned int                        n0_stall : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCD_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 10;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_incoming_rtr : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                not_incoming_rtr : 1;
+        unsigned int                                 : 11;
+        unsigned int                not_mux_dcmp_rtr : 1;
+        unsigned int             not_dgmmpd_dxtc_rtr : 1;
+        unsigned int               not_dcmp0_arb_rtr : 1;
+        unsigned int                                 : 5;
+        unsigned int         not_sctrmx0_sctrarb_rtr : 1;
+        unsigned int         not_multcyl_sctrarb_rtr : 1;
+        unsigned int                                 : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_STALLS_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int             quad0_TCO_TCB_rtr_d : 1;
+        unsigned int                 quad0_rl_sg_RTR : 1;
+        unsigned int                quad0_sg_crd_RTR : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             rl_sg_sector_format : 8;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                                 : 2;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int                            busy : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                            busy : 1;
+        unsigned int        all_sectors_written_set0 : 1;
+        unsigned int        all_sectors_written_set1 : 1;
+        unsigned int        all_sectors_written_set2 : 1;
+        unsigned int        all_sectors_written_set3 : 1;
+        unsigned int                  cache_read_RTR : 1;
+        unsigned int                    read_cache_q : 1;
+        unsigned int                                 : 7;
+        unsigned int                 stageN1_valid_q : 1;
+        unsigned int                                 : 2;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int            sg_crd_end_of_sample : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int             rl_sg_end_of_sample : 1;
+        unsigned int             rl_sg_sector_format : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union TCO_QUAD0_DEBUG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       fifo_busy : 1;
+        unsigned int                           empty : 1;
+        unsigned int                            full : 1;
+        unsigned int                    write_enable : 1;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                                 : 2;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                TCO_TCB_read_xfc : 1;
+        unsigned int                      sg_crd_rts : 1;
+        unsigned int                      sg_crd_rtr : 1;
+        unsigned int                       rl_sg_rts : 1;
+        unsigned int                       rl_sg_rtr : 1;
+        unsigned int                   TCB_TCO_xfc_q : 1;
+        unsigned int                   TCB_TCO_rtr_d : 1;
+        unsigned int              tco_quad_pipe_busy : 1;
+        unsigned int                 input_quad_busy : 1;
+        unsigned int               latency_fifo_busy : 1;
+        unsigned int                 cache_read_busy : 1;
+        unsigned int                                 : 2;
+        unsigned int                   fifo_read_ptr : 7;
+        unsigned int                  fifo_write_ptr : 7;
+        unsigned int                    write_enable : 1;
+        unsigned int                            full : 1;
+        unsigned int                           empty : 1;
+        unsigned int                       fifo_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_GPR_MANAGEMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     REG_DYNAMIC : 1;
+        unsigned int                                 : 3;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    REG_SIZE_VTX : 7;
+        unsigned int                                 : 1;
+        unsigned int                    REG_SIZE_PIX : 7;
+        unsigned int                                 : 3;
+        unsigned int                     REG_DYNAMIC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FLOW_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+        unsigned int                                 : 2;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int         PS_PREFETCH_COLOR_ALLOC : 1;
+        unsigned int     NO_EARLY_THREAD_TERMINATION : 1;
+        unsigned int                POS_EXP_PRIORITY : 1;
+        unsigned int                    NO_CFS_EJECT : 1;
+        unsigned int                    NO_ARB_EJECT : 1;
+        unsigned int          ALU_ARBITRATION_POLICY : 1;
+        unsigned int           VC_ARBITRATION_POLICY : 1;
+        unsigned int      TEXTURE_ARBITRATION_POLICY : 2;
+        unsigned int               NO_CEXEC_OPTIMIZE : 1;
+        unsigned int                    NO_LOOP_EXIT : 1;
+        unsigned int                        NO_PV_PS : 1;
+        unsigned int                      CF_WR_BASE : 4;
+        unsigned int                                 : 3;
+        unsigned int                         ONE_ALU : 1;
+        unsigned int                                 : 3;
+        unsigned int                      ONE_THREAD : 1;
+        unsigned int                                 : 2;
+        unsigned int        INPUT_ARBITRATION_POLICY : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INST_STORE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   INST_BASE_PIX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_VTX : 12;
+        unsigned int                                 : 4;
+        unsigned int                   INST_BASE_PIX : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_RESOURCE_MANAGMENT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int                                 : 7;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 7;
+        unsigned int              EXPORT_BUF_ENTRIES : 9;
+        unsigned int          PIX_THREAD_BUF_ENTRIES : 8;
+        unsigned int          VTX_THREAD_BUF_ENTRIES : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_EO_RT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 EO_CONSTANTS_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    EO_TSTATE_RT : 8;
+        unsigned int                                 : 8;
+        unsigned int                 EO_CONSTANTS_RT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  DB_ALUCST_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 DB_WEN_MEMORY_3 : 1;
+        unsigned int                 DB_WEN_MEMORY_2 : 1;
+        unsigned int                 DB_WEN_MEMORY_1 : 1;
+        unsigned int                 DB_WEN_MEMORY_0 : 1;
+        unsigned int                  DB_READ_MEMORY : 2;
+        unsigned int                        RESERVED : 2;
+        unsigned int                     DB_READ_CTX : 1;
+        unsigned int                  DB_TSTATE_SIZE : 8;
+        unsigned int                                 : 1;
+        unsigned int                  DB_ALUCST_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TIMEBASE : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                           SPARE : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           SPARE : 8;
+        unsigned int                  THRESHOLD_HIGH : 8;
+        unsigned int                   THRESHOLD_LOW : 8;
+        unsigned int                        TIMEBASE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_ACTIVITY_METER_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERCENT_BUSY : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    PERCENT_BUSY : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INPUT_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_THREAD_ARB_PRIORITY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                        RESERVED : 2;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int      USE_SERIAL_COUNT_THRESHOLD : 1;
+        unsigned int            PS_PRIORITIZE_SERIAL : 1;
+        unsigned int            VS_PRIORITIZE_SERIAL : 1;
+        unsigned int                        RESERVED : 2;
+        unsigned int                       THRESHOLD : 10;
+        unsigned int                   SX_AVAIL_SIGN : 1;
+        unsigned int                 SX_AVAIL_WEIGHT : 3;
+        unsigned int                   PC_AVAIL_SIGN : 1;
+        unsigned int                 PC_AVAIL_WEIGHT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_WATCHDOG_TIMER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ENABLE : 1;
+        unsigned int                   TIMEOUT_COUNT : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TIMEOUT_COUNT : 31;
+        unsigned int                          ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_WATCHDOG_MASK : 1;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                VS_WATCHDOG_MASK : 1;
+        unsigned int                PS_WATCHDOG_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int             VS_WATCHDOG_TIMEOUT : 1;
+        unsigned int             PS_WATCHDOG_TIMEOUT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                 VS_WATCHDOG_ACK : 1;
+        unsigned int                 PS_WATCHDOG_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_INPUT_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       VC_VSR_LD : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           PC_AS : 3;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                     PC_GPR_SIZE : 8;
+        unsigned int                   PC_INTERP_CNT : 5;
+        unsigned int                           PC_AS : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PC_PISM : 3;
+        unsigned int                       VC_GPR_LD : 4;
+        unsigned int                        RESERVED : 1;
+        unsigned int                       VC_VSR_LD : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_CONST_MGR_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int            CNTX1_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX1_VTX_EVENT_DONE : 1;
+        unsigned int            CNTX0_PIX_EVENT_DONE : 1;
+        unsigned int            CNTX0_VTX_EVENT_DONE : 1;
+        unsigned int            TEX_CONST_CNTX_VALID : 2;
+        unsigned int            ALU_CONST_CNTX_VALID : 2;
+        unsigned int                       RESERVED2 : 3;
+        unsigned int           ALU_CONST_EVENT_STATE : 5;
+        unsigned int                       RESERVED1 : 3;
+        unsigned int           TEX_CONST_EVENT_STATE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TP_FSM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           EX_TP : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           CF_TP : 4;
+        unsigned int                           IF_TP : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                       ARB_TR_TP : 3;
+        unsigned int                       RESERVED5 : 2;
+        unsigned int                          FCS_TP : 2;
+        unsigned int                       RESERVED4 : 2;
+        unsigned int                          FCR_TP : 2;
+        unsigned int                       RESERVED3 : 2;
+        unsigned int                           GS_TP : 2;
+        unsigned int                       RESERVED2 : 2;
+        unsigned int                          TIS_TP : 2;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                           IF_TP : 3;
+        unsigned int                           CF_TP : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                           EX_TP : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_FSM_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        EX_ALU_0 : 3;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                      ARB_TR_ALU : 3;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       ACS_ALU_0 : 3;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       AIS_ALU_0 : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       DU0_ALU_0 : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       DU1_ALU_0 : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                        IF_ALU_0 : 3;
+        unsigned int                        CF_ALU_0 : 4;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                        EX_ALU_0 : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_EXP_ALLOC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   POS_BUF_AVAIL : 4;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                        RESERVED : 1;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int             ALLOC_TBL_BUF_AVAIL : 6;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    EA_BUF_AVAIL : 3;
+        unsigned int                 COLOR_BUF_AVAIL : 8;
+        unsigned int                   POS_BUF_AVAIL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PTR_BUFF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   END_OF_BUFFER : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                    VTX_SYNC_CNT : 11;
+        unsigned int                        EF_EMPTY : 1;
+        unsigned int               PRIM_TYPE_POLYGON : 1;
+        unsigned int                      QUAL_EVENT : 1;
+        unsigned int                     SC_EVENT_ID : 5;
+        unsigned int                EVENT_CONTEXT_ID : 3;
+        unsigned int                 QUAL_NEW_VECTOR : 1;
+        unsigned int                     DEALLOC_CNT : 4;
+        unsigned int                   END_OF_BUFFER : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_VTX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VTX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        VTX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         VTX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    VTX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    VTX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_GPR_PIX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_TAIL_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                        PIX_FREE : 7;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         PIX_MAX : 7;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                    PIX_HEAD_PTR : 7;
+        unsigned int                        RESERVED : 1;
+        unsigned int                    PIX_TAIL_PTR : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_TB_STATUS_SEL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int                                 : 1;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         DISABLE_STRICT_CTX_SYNC : 1;
+        unsigned int               VC_THREAD_BUF_DLY : 2;
+        unsigned int        PIX_TB_STATE_MEM_RD_ADDR : 6;
+        unsigned int         PIX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           PIX_TB_STATUS_REG_SEL : 4;
+        unsigned int           DEBUG_BUS_TRIGGER_SEL : 2;
+        unsigned int                                 : 1;
+        unsigned int          PIX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int          VTX_TB_STATE_MEM_RD_EN : 1;
+        unsigned int        VTX_TB_STATE_MEM_RD_ADDR : 4;
+        unsigned int         VTX_TB_STATE_MEM_DW_SEL : 3;
+        unsigned int           VTX_TB_STATUS_REG_SEL : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                                 : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 10;
+        unsigned int                          BUSY_Q : 1;
+        unsigned int                   SX_EVENT_FULL : 1;
+        unsigned int                NXT_PC_ALLOC_CNT : 4;
+        unsigned int               NXT_POS_ALLOC_CNT : 4;
+        unsigned int                      FULL_CNT_Q : 4;
+        unsigned int                      TAIL_PTR_Q : 4;
+        unsigned int                  VTX_HEAD_PTR_Q : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_PTR : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                     VS_DONE_PTR : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATUS_REG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VS_STATUS_REG : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   VS_STATUS_REG : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_VTX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PIX_HEAD_PTR : 6;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int                            BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BUSY : 1;
+        unsigned int                 NXT_PIX_EXP_CNT : 6;
+        unsigned int               NXT_PIX_ALLOC_CNT : 6;
+        unsigned int                        FULL_CNT : 7;
+        unsigned int                        TAIL_PTR : 6;
+        unsigned int                    PIX_HEAD_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATUS_REG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             PIX_TB_STATUS_REG_3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_PIX_TB_STATE_MEM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PIX_TB_STATE_MEM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER2_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PERFCOUNTER3_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SX_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   VECTOR_RESULT : 6;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                   SCALAR_OPCODE : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SCALAR_OPCODE : 6;
+        unsigned int                    SCALAR_CLAMP : 1;
+        unsigned int                    VECTOR_CLAMP : 1;
+        unsigned int                  SCALAR_WRT_MSK : 4;
+        unsigned int                  VECTOR_WRT_MSK : 4;
+        unsigned int                     EXPORT_DATA : 1;
+        unsigned int                  SCALAR_DST_REL : 1;
+        unsigned int                   SCALAR_RESULT : 6;
+        unsigned int            LOW_PRECISION_16B_FP : 1;
+        unsigned int                  VECTOR_DST_REL : 1;
+        unsigned int                   VECTOR_RESULT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                 CONST_0_REL_ABS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CONST_0_REL_ABS : 1;
+        unsigned int                 CONST_1_REL_ABS : 1;
+        unsigned int                   RELATIVE_ADDR : 1;
+        unsigned int                     PRED_SELECT : 2;
+        unsigned int                   SRC_A_ARG_MOD : 1;
+        unsigned int                   SRC_B_ARG_MOD : 1;
+        unsigned int                   SRC_C_ARG_MOD : 1;
+        unsigned int                 SRC_A_SWIZZLE_A : 2;
+        unsigned int                 SRC_A_SWIZZLE_B : 2;
+        unsigned int                 SRC_A_SWIZZLE_G : 2;
+        unsigned int                 SRC_A_SWIZZLE_R : 2;
+        unsigned int                 SRC_B_SWIZZLE_A : 2;
+        unsigned int                 SRC_B_SWIZZLE_B : 2;
+        unsigned int                 SRC_B_SWIZZLE_G : 2;
+        unsigned int                 SRC_B_SWIZZLE_R : 2;
+        unsigned int                 SRC_C_SWIZZLE_A : 2;
+        unsigned int                 SRC_C_SWIZZLE_B : 2;
+        unsigned int                 SRC_C_SWIZZLE_G : 2;
+        unsigned int                 SRC_C_SWIZZLE_R : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_ALU_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SRC_C_REG_PTR : 6;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_A_SEL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_A_SEL : 1;
+        unsigned int                       SRC_B_SEL : 1;
+        unsigned int                       SRC_C_SEL : 1;
+        unsigned int                   VECTOR_OPCODE : 5;
+        unsigned int                   REG_ABS_MOD_A : 1;
+        unsigned int                    REG_SELECT_A : 1;
+        unsigned int                   SRC_A_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_B : 1;
+        unsigned int                    REG_SELECT_B : 1;
+        unsigned int                   SRC_B_REG_PTR : 6;
+        unsigned int                   REG_ABS_MOD_C : 1;
+        unsigned int                    REG_SELECT_C : 1;
+        unsigned int                   SRC_C_REG_PTR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                        RESERVED : 3;
+        unsigned int                           COUNT : 3;
+        unsigned int                           YIELD : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           YIELD : 1;
+        unsigned int                           COUNT : 3;
+        unsigned int                        RESERVED : 3;
+        unsigned int                         ADDRESS : 9;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_EXEC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     INST_TYPE_0 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       INST_VC_5 : 1;
+        unsigned int                       INST_VC_4 : 1;
+        unsigned int                       INST_VC_3 : 1;
+        unsigned int                       INST_VC_2 : 1;
+        unsigned int                       INST_VC_1 : 1;
+        unsigned int                       INST_VC_0 : 1;
+        unsigned int                   INST_SERIAL_5 : 1;
+        unsigned int                     INST_TYPE_5 : 1;
+        unsigned int                   INST_SERIAL_4 : 1;
+        unsigned int                     INST_TYPE_4 : 1;
+        unsigned int                   INST_SERIAL_3 : 1;
+        unsigned int                     INST_TYPE_3 : 1;
+        unsigned int                   INST_SERIAL_2 : 1;
+        unsigned int                     INST_TYPE_2 : 1;
+        unsigned int                   INST_SERIAL_1 : 1;
+        unsigned int                     INST_TYPE_1 : 1;
+        unsigned int                   INST_SERIAL_0 : 1;
+        unsigned int                     INST_TYPE_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_1 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 11;
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                      RESERVED_0 : 6;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 11;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 6;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                      RESERVED_0 : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_LOOP_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         LOOP_ID : 5;
+        unsigned int                        RESERVED : 22;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                        RESERVED : 22;
+        unsigned int                         LOOP_ID : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      RESERVED_1 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 17;
+        unsigned int                  PREDICATED_JMP : 1;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_0 : 3;
+        unsigned int                         ADDRESS : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 1;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_2 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_2 : 2;
+        unsigned int                      FORCE_CALL : 1;
+        unsigned int                      RESERVED_1 : 3;
+        unsigned int                         ADDRESS : 10;
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                      RESERVED_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_JMP_CALL_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 17;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       CONDITION : 1;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                    ADDRESS_MODE : 1;
+        unsigned int                       CONDITION : 1;
+        unsigned int                       BOOL_ADDR : 8;
+        unsigned int                       DIRECTION : 1;
+        unsigned int                        RESERVED : 17;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 4;
+        unsigned int                        RESERVED : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 28;
+        unsigned int                            SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RESERVED_0 : 8;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+        unsigned int                            SIZE : 4;
+        unsigned int                      RESERVED_1 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RESERVED_1 : 12;
+        unsigned int                            SIZE : 4;
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                      RESERVED_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_CF_ALLOC_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 24;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                          OPCODE : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          OPCODE : 4;
+        unsigned int                      ALLOC_MODE : 1;
+        unsigned int                   BUFFER_SELECT : 2;
+        unsigned int                       NO_SERIAL : 1;
+        unsigned int                        RESERVED : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_Z : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       SRC_SEL_Z : 2;
+        unsigned int                       SRC_SEL_Y : 2;
+        unsigned int                       SRC_SEL_X : 2;
+        unsigned int                 TX_COORD_DENORM : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                FETCH_VALID_ONLY : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                     USE_REG_LOD : 2;
+        unsigned int                    USE_COMP_LOD : 1;
+        unsigned int                  VOL_MIN_FILTER : 2;
+        unsigned int                  VOL_MAG_FILTER : 2;
+        unsigned int                ARBITRARY_FILTER : 3;
+        unsigned int                    ANISO_FILTER : 3;
+        unsigned int                      MIP_FILTER : 2;
+        unsigned int                      MIN_FILTER : 2;
+        unsigned int                      MAG_FILTER : 2;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_TFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               USE_REG_GRADIENTS : 1;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                        OFFSET_Z : 5;
+        unsigned int                        OFFSET_Y : 5;
+        unsigned int                        OFFSET_X : 5;
+        unsigned int                          UNUSED : 7;
+        unsigned int                        LOD_BIAS : 7;
+        unsigned int                 SAMPLE_LOCATION : 1;
+        unsigned int               USE_REG_GRADIENTS : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          OPCODE : 5;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                         SRC_SEL : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         SRC_SEL : 2;
+        unsigned int                                 : 3;
+        unsigned int                 CONST_INDEX_SEL : 2;
+        unsigned int                     CONST_INDEX : 5;
+        unsigned int                     MUST_BE_ONE : 1;
+        unsigned int                      DST_GPR_AM : 1;
+        unsigned int                         DST_GPR : 6;
+        unsigned int                      SRC_GPR_AM : 1;
+        unsigned int                         SRC_GPR : 6;
+        unsigned int                          OPCODE : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DST_SEL_X : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     PRED_SELECT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     PRED_SELECT : 1;
+        unsigned int                                 : 1;
+        unsigned int                  EXP_ADJUST_ALL : 7;
+        unsigned int                                 : 1;
+        unsigned int                     DATA_FORMAT : 6;
+        unsigned int                                 : 1;
+        unsigned int              SIGNED_RF_MODE_ALL : 1;
+        unsigned int                  NUM_FORMAT_ALL : 1;
+        unsigned int                 FORMAT_COMP_ALL : 1;
+        unsigned int                       DST_SEL_W : 3;
+        unsigned int                       DST_SEL_Z : 3;
+        unsigned int                       DST_SEL_Y : 3;
+        unsigned int                       DST_SEL_X : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INSTRUCTION_VFETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          STRIDE : 8;
+        unsigned int                                 : 8;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 7;
+        unsigned int                  PRED_CONDITION : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PRED_CONDITION : 1;
+        unsigned int                                 : 7;
+        unsigned int                          OFFSET : 8;
+        unsigned int                                 : 8;
+        unsigned int                          STRIDE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            TYPE : 1;
+        unsigned int                           STATE : 1;
+        unsigned int                    BASE_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BASE_ADDRESS : 30;
+        unsigned int                           STATE : 1;
+        unsigned int                            TYPE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_VFETCH_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ENDIAN_SWAP : 2;
+        unsigned int                   LIMIT_ADDRESS : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   LIMIT_ADDRESS : 30;
+        unsigned int                     ENDIAN_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_T3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                             RED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                             RED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           GREEN : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           GREEN : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BLUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BLUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONSTANT_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           ALPHA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           ALPHA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_FETCH_RT_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           VALUE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           VALUE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_BOOLEANS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_BOOLEANS_0 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_3 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CF_BOOLEANS_3 : 8;
+        unsigned int                   CF_BOOLEANS_2 : 8;
+        unsigned int                   CF_BOOLEANS_1 : 8;
+        unsigned int                   CF_BOOLEANS_0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RT_LOOP {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CF_LOOP_COUNT : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                    CF_LOOP_STEP : 8;
+        unsigned int                   CF_LOOP_START : 8;
+        unsigned int                   CF_LOOP_COUNT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_PROGRAM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 12;
+        unsigned int                            SIZE : 12;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                            SIZE : 12;
+        unsigned int                            BASE : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_PROGRAM_SIZE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                      PS_CF_SIZE : 11;
+        unsigned int                                 : 1;
+        unsigned int                      VS_CF_SIZE : 11;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_INTERPOLATOR_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARAM_SHADE : 16;
+        unsigned int                SAMPLING_PATTERN : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                SAMPLING_PATTERN : 16;
+        unsigned int                     PARAM_SHADE : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PROGRAM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      VS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                   GEN_INDEX_VTX : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   GEN_INDEX_VTX : 1;
+        unsigned int                  PS_EXPORT_MODE : 4;
+        unsigned int                  VS_EXPORT_MODE : 3;
+        unsigned int                 VS_EXPORT_COUNT : 4;
+        unsigned int                   GEN_INDEX_PIX : 1;
+        unsigned int                       PARAM_GEN : 1;
+        unsigned int                     PS_RESOURCE : 1;
+        unsigned int                     VS_RESOURCE : 1;
+        unsigned int                                 : 2;
+        unsigned int                      PS_NUM_REG : 6;
+        unsigned int                                 : 2;
+        unsigned int                      VS_NUM_REG : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_0 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_7 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PARAM_WRAP_7 : 4;
+        unsigned int                    PARAM_WRAP_6 : 4;
+        unsigned int                    PARAM_WRAP_5 : 4;
+        unsigned int                    PARAM_WRAP_4 : 4;
+        unsigned int                    PARAM_WRAP_3 : 4;
+        unsigned int                    PARAM_WRAP_2 : 4;
+        unsigned int                    PARAM_WRAP_1 : 4;
+        unsigned int                    PARAM_WRAP_0 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_WRAPPING_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PARAM_WRAP_8 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_15 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PARAM_WRAP_15 : 4;
+        unsigned int                   PARAM_WRAP_14 : 4;
+        unsigned int                   PARAM_WRAP_13 : 4;
+        unsigned int                   PARAM_WRAP_12 : 4;
+        unsigned int                   PARAM_WRAP_11 : 4;
+        unsigned int                   PARAM_WRAP_10 : 4;
+        unsigned int                    PARAM_WRAP_9 : 4;
+        unsigned int                    PARAM_WRAP_8 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_VS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_PS_CONST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 11;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 11;
+        unsigned int                            SIZE : 9;
+        unsigned int                                 : 3;
+        unsigned int                            BASE : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CONTEXT_MISC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                    TX_CACHE_SEL : 1;
+        unsigned int                  YEILD_OPTIMIZE : 1;
+        unsigned int                 PERFCOUNTER_REF : 1;
+        unsigned int                   PARAM_GEN_POS : 8;
+        unsigned int                                 : 4;
+        unsigned int                  SC_SAMPLE_CNTL : 2;
+        unsigned int             SC_OUTPUT_SCREEN_XY : 1;
+        unsigned int              INST_PRED_OPTIMIZE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_CF_RD_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RD_BASE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                         RD_BASE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DB_PROB_ON : 1;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 5;
+        unsigned int                   DB_PROB_COUNT : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DB_PROB_COUNT : 8;
+        unsigned int                                 : 5;
+        unsigned int                    DB_PROB_ADDR : 11;
+        unsigned int                                 : 3;
+        unsigned int                   DB_PROB_BREAK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      DB_PROB_ON : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SQ_DEBUG_MISC_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DB_ON_PIX : 1;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                                 : 6;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   DB_BREAK_ADDR : 11;
+        unsigned int                   DB_INST_COUNT : 8;
+        unsigned int                                 : 6;
+        unsigned int                       DB_ON_VTX : 1;
+        unsigned int                       DB_ON_PIX : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_ARBITER_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                  PA_CLNT_ENABLE : 1;
+        unsigned int                  RB_CLNT_ENABLE : 1;
+        unsigned int                  TC_CLNT_ENABLE : 1;
+        unsigned int                 VGT_CLNT_ENABLE : 1;
+        unsigned int                  CP_CLNT_ENABLE : 1;
+        unsigned int                 IN_FLIGHT_LIMIT : 6;
+        unsigned int          IN_FLIGHT_LIMIT_ENABLE : 1;
+        unsigned int              TC_ARB_HOLD_ENABLE : 1;
+        unsigned int               TC_REORDER_ENABLE : 1;
+        unsigned int                       PAGE_SIZE : 3;
+        unsigned int                  L2_ARB_CONTROL : 1;
+        unsigned int              L1_ARB_HOLD_ENABLE : 1;
+        unsigned int                   L1_ARB_ENABLE : 1;
+        unsigned int           SAME_PAGE_GRANULARITY : 1;
+        unsigned int                 SAME_PAGE_LIMIT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_CLNT_AXI_ID_REUSE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          CPw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                                 : 17;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 17;
+        unsigned int                          PAw_ID : 3;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                         MMUr_ID : 3;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                          RBw_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          CPw_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_INTERRUPT_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                  MMU_PAGE_FAULT : 1;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                  AXI_READ_ERROR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     AXI_READ_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                 AXI_WRITE_ERROR : 1;
+        unsigned int                    AXI_WRITE_ID : 3;
+        unsigned int                  AXI_READ_ERROR : 1;
+        unsigned int                     AXI_READ_ID : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         N_VALUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                         N_VALUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PERF_COUNTER_LOW : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PERF_COUNTER_LOW : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNTER_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                 PERF_COUNTER_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_CTRL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                           INDEX : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                           INDEX : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_AXI_HALT_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AXI_HALT : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                        AXI_HALT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG00 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                     AXI_RDY_ENA : 1;
+        unsigned int                    AXI_HALT_ACK : 1;
+        unsigned int                    AXI_HALT_REQ : 1;
+        unsigned int                      AXI_BREADY : 1;
+        unsigned int                      AXI_BVALID : 1;
+        unsigned int                      AXI_RREADY : 1;
+        unsigned int                      AXI_RVALID : 1;
+        unsigned int                      AXI_WREADY : 1;
+        unsigned int                      AXI_WVALID : 1;
+        unsigned int                     AXI_ARREADY : 1;
+        unsigned int                     AXI_ARVALID : 1;
+        unsigned int                      AXI_AREADY : 1;
+        unsigned int                      AXI_AVALID : 1;
+        unsigned int                        WDB_FULL : 1;
+        unsigned int                       WDB_EMPTY : 1;
+        unsigned int                        ARQ_FULL : 1;
+        unsigned int                       ARQ_EMPTY : 1;
+        unsigned int                 MH_CLK_EN_STATE : 1;
+        unsigned int                      PA_REQUEST : 1;
+        unsigned int                      RB_REQUEST : 1;
+        unsigned int                        TCD_FULL : 1;
+        unsigned int                       TCD_EMPTY : 1;
+        unsigned int                     TC_CAM_FULL : 1;
+        unsigned int                    TC_CAM_EMPTY : 1;
+        unsigned int                      TC_REQUEST : 1;
+        unsigned int                     VGT_REQUEST : 1;
+        unsigned int                      CP_REQUEST : 1;
+        unsigned int               TRANS_OUTSTANDING : 1;
+        unsigned int                         MH_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG01 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       TC_BLEN_q : 1;
+        unsigned int                        TC_RTR_q : 1;
+        unsigned int                       TC_SEND_q : 1;
+        unsigned int                       VGT_TAG_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       CP_BLEN_q : 1;
+        unsigned int                        CP_TAG_q : 3;
+        unsigned int                      CP_WRITE_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG02 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       BRC_BRESP : 2;
+        unsigned int                         BRC_BID : 3;
+        unsigned int                MH_PA_writeclean : 1;
+        unsigned int                MH_RB_writeclean : 1;
+        unsigned int                MH_CP_writeclean : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                     MH_CLNT_tag : 3;
+        unsigned int                   MH_CLNT_rlast : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG03 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               MH_CLNT_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG04 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              MH_CLNT_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG05 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CP_MH_send : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                   CP_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   CP_MH_ad_31_5 : 27;
+        unsigned int                       CP_MH_tag : 3;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                      CP_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG06 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 CP_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 CP_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG07 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CP_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                CP_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG08 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CP_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        PA_MH_be : 8;
+        unsigned int                        RB_MH_be : 8;
+        unsigned int                        CP_MH_be : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG09 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 3;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  VGT_MH_ad_31_5 : 27;
+        unsigned int                    VGT_MH_tagbe : 1;
+        unsigned int                     VGT_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG10 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                 TC_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 TC_MH_addr_31_5 : 27;
+        unsigned int                      TC_MH_mask : 2;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG11 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_info : 25;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                      TC_MH_info : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG12 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_TC_mcinfo : 25;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                                 : 5;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 5;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int               MH_TC_mcinfo_send : 1;
+        unsigned int                    MH_TC_mcinfo : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG13 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                TC_ROQ_ADDR_31_5 : 27;
+        unsigned int                     TC_ROQ_MASK : 2;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG14 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ROQ_INFO : 25;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                     TC_ROQ_SEND : 1;
+        unsigned int                     TC_ROQ_INFO : 25;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG15 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                 RB_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_addr_31_5 : 27;
+        unsigned int                      RB_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG16 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 RB_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 RB_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG17 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                RB_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                RB_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG18 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 4;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                 PA_MH_addr_31_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_addr_31_5 : 27;
+        unsigned int                      PA_MH_send : 1;
+        unsigned int                     ALWAYS_ZERO : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG19 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PA_MH_data_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PA_MH_data_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG20 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PA_MH_data_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PA_MH_data_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG21 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                           RID_q : 3;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                     ARLEN_q_1_0 : 2;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_2_0 : 3;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG22 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        AVALID_q : 1;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                           AID_q : 3;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                           BID_q : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                           BID_q : 3;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         WSTRB_q : 8;
+        unsigned int                           WID_q : 3;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                        WREADY_q : 1;
+        unsigned int                        WVALID_q : 1;
+        unsigned int                     ARLEN_q_1_1 : 1;
+        unsigned int                          ARID_q : 3;
+        unsigned int                       ARREADY_q : 1;
+        unsigned int                       ARVALID_q : 1;
+        unsigned int                      ALEN_q_1_0 : 2;
+        unsigned int                           AID_q : 3;
+        unsigned int                        AREADY_q : 1;
+        unsigned int                        AVALID_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG23 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                    CTRL_ARC_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CTRL_ARC_PAD : 28;
+        unsigned int                     CTRL_ARC_ID : 3;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG24 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                           REG_A : 14;
+        unsigned int                          REG_RE : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                                 : 13;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 13;
+        unsigned int                        BLOCK_RS : 1;
+        unsigned int                          REG_WE : 1;
+        unsigned int                          REG_RE : 1;
+        unsigned int                           REG_A : 14;
+        unsigned int                     ALWAYS_ZERO : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG25 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          REG_WD : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REG_WD : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG26 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    MH_RBBM_busy : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       BRC_VALID : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       BRC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                        PA_RTR_q : 1;
+        unsigned int                       PA_SEND_q : 1;
+        unsigned int                        RB_RTR_q : 1;
+        unsigned int                       RB_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                       VGT_RTR_q : 1;
+        unsigned int                      VGT_SEND_q : 1;
+        unsigned int                        CP_RTR_q : 1;
+        unsigned int                       CP_SEND_q : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1;
+        unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1;
+        unsigned int                   ANY_CLNT_BUSY : 1;
+        unsigned int                       MH_BUSY_d : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TCD_EMPTY_q : 1;
+        unsigned int                           CNT_q : 6;
+        unsigned int         RBBM_MH_clk_en_override : 1;
+        unsigned int                     GAT_CLK_ENA : 1;
+        unsigned int         MH_CIB_tcroq_clk_en_int : 1;
+        unsigned int           MH_CIB_mmu_clk_en_int : 1;
+        unsigned int            MH_CIB_mh_clk_en_int : 1;
+        unsigned int                    MH_RBBM_busy : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG27 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  EFF2_FP_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                    ARB_WINNER_q : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int                  EFF2_FP_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG28 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     EFF1_WINNER : 3;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+#else       /* !defined(qLittleEndian) */
+        unsigned int         SAME_PAGE_LIMIT_COUNT_q : 10;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                        EFF1_WIN : 1;
+        unsigned int                     RB_EFF1_REQ : 1;
+        unsigned int                     TC_EFF1_REQ : 1;
+        unsigned int                    VGT_EFF1_REQ : 1;
+        unsigned int                     CP_EFF1_REQ : 1;
+        unsigned int                        ARB_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int               TC_SEND_EFF1_QUAL : 1;
+        unsigned int                    TC_SEND_QUAL : 1;
+        unsigned int                   VGT_SEND_QUAL : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                     EFF1_WINNER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG29 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_4 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RECENT_d_4 : 3;
+        unsigned int                      RECENT_d_3 : 3;
+        unsigned int                      RECENT_d_2 : 3;
+        unsigned int                      RECENT_d_1 : 3;
+        unsigned int                      RECENT_d_0 : 3;
+        unsigned int                        CLNT_REQ : 5;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                        ARB_HOLD : 1;
+        unsigned int           UPDATE_RECENT_STACK_d : 1;
+        unsigned int                  LEAST_RECENT_d : 3;
+        unsigned int            LEAST_RECENT_INDEX_d : 3;
+        unsigned int             EFF2_LRU_WINNER_out : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG30 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     TC_ARB_HOLD : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                      ARB_WINNER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ARB_WINNER : 3;
+        unsigned int                    PA_SEND_QUAL : 1;
+        unsigned int                    RB_SEND_QUAL : 1;
+        unsigned int                     CP_MH_write : 1;
+        unsigned int                    CP_SEND_QUAL : 1;
+        unsigned int                    WBURST_CNT_q : 3;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                         WLAST_q : 1;
+        unsigned int                   WBURST_ACTIVE : 1;
+        unsigned int              TCD_FULLNESS_CNT_q : 7;
+        unsigned int                   TC_MH_written : 1;
+        unsigned int                   TC_ROQ_SEND_q : 1;
+        unsigned int                TC_ROQ_RTR_DBG_q : 1;
+        unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1;
+        unsigned int                    TCHOLD_CNT_q : 3;
+        unsigned int                     TCHOLD_IP_q : 1;
+        unsigned int                  TCD_NEARFULL_q : 1;
+        unsigned int            TC_ROQ_SAME_ROW_BANK : 1;
+        unsigned int          TC_NOROQ_SAME_ROW_BANK : 1;
+        unsigned int                     TC_ARB_HOLD : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG31 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int             RF_ARBITER_CONFIG_q : 26;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG32 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_q : 8;
+        unsigned int                      ROQ_MARK_q : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG33 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 SAME_ROW_BANK_q : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                     TC_ROQ_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TC_ROQ_FULL : 1;
+        unsigned int                    TC_ROQ_EMPTY : 1;
+        unsigned int                    TC_EFF1_QUAL : 1;
+        unsigned int               ANY_SAME_ROW_BANK : 1;
+        unsigned int        TC_ROQ_SAME_ROW_BANK_SEL : 1;
+        unsigned int                       KILL_EFF1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                     ROQ_VALID_d : 8;
+        unsigned int                      ROQ_MARK_d : 8;
+        unsigned int                 SAME_ROW_BANK_q : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG34 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           NON_SAME_ROW_BANK_REQ : 8;
+        unsigned int           NON_SAME_ROW_BANK_WIN : 8;
+        unsigned int               SAME_ROW_BANK_REQ : 8;
+        unsigned int               SAME_ROW_BANK_WIN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG35 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                      ROQ_ADDR_0 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_0 : 27;
+        unsigned int               SAME_ROW_BANK_q_0 : 1;
+        unsigned int                   ROQ_VALID_q_0 : 1;
+        unsigned int                    ROQ_MARK_q_0 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG36 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                      ROQ_ADDR_1 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_1 : 27;
+        unsigned int               SAME_ROW_BANK_q_1 : 1;
+        unsigned int                   ROQ_VALID_q_1 : 1;
+        unsigned int                    ROQ_MARK_q_1 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG37 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                      ROQ_ADDR_2 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_2 : 27;
+        unsigned int               SAME_ROW_BANK_q_2 : 1;
+        unsigned int                   ROQ_VALID_q_2 : 1;
+        unsigned int                    ROQ_MARK_q_2 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG38 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                      ROQ_ADDR_3 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_3 : 27;
+        unsigned int               SAME_ROW_BANK_q_3 : 1;
+        unsigned int                   ROQ_VALID_q_3 : 1;
+        unsigned int                    ROQ_MARK_q_3 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG39 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                      ROQ_ADDR_4 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_4 : 27;
+        unsigned int               SAME_ROW_BANK_q_4 : 1;
+        unsigned int                   ROQ_VALID_q_4 : 1;
+        unsigned int                    ROQ_MARK_q_4 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG40 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                      ROQ_ADDR_5 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_5 : 27;
+        unsigned int               SAME_ROW_BANK_q_5 : 1;
+        unsigned int                   ROQ_VALID_q_5 : 1;
+        unsigned int                    ROQ_MARK_q_5 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG41 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                      ROQ_ADDR_6 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_6 : 27;
+        unsigned int               SAME_ROW_BANK_q_6 : 1;
+        unsigned int                   ROQ_VALID_q_6 : 1;
+        unsigned int                    ROQ_MARK_q_6 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG42 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TC_MH_send : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                      ROQ_ADDR_7 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      ROQ_ADDR_7 : 27;
+        unsigned int               SAME_ROW_BANK_q_7 : 1;
+        unsigned int                   ROQ_VALID_q_7 : 1;
+        unsigned int                    ROQ_MARK_q_7 : 1;
+        unsigned int                    TC_ROQ_RTR_q : 1;
+        unsigned int                      TC_MH_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG43 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ARB_REG_WE_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                                 : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 4;
+        unsigned int                  WDB_RTR_SKID_3 : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                     WBURST_IP_q : 1;
+        unsigned int                        MMU_BLEN : 1;
+        unsigned int                       MMU_WRITE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                  ARQ_FIFO_CNT_q : 3;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                      ARB_BLEN_q : 1;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                  WDAT_BURST_RTR : 1;
+        unsigned int                     ARB_REG_RTR : 1;
+        unsigned int                       ARB_RTR_q : 1;
+        unsigned int                 ARB_REG_VALID_q : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                    ARB_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG44 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          ARB_WE : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                       ARB_VAD_q : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ARB_VAD_q : 28;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                          ARB_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG45 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                          MMU_WE : 1;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                         MMU_PAD : 28;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MMU_PAD : 28;
+        unsigned int                          MMU_ID : 3;
+        unsigned int                          MMU_WE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG46 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WDAT_REG_WE_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                   WDB_WDC_WSTRB : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   WDB_WDC_WSTRB : 8;
+        unsigned int                   WDB_WDC_WLAST : 1;
+        unsigned int                     WDB_WDC_WID : 3;
+        unsigned int                    WDC_WDB_RE_q : 1;
+        unsigned int                  WDB_FIFO_CNT_q : 5;
+        unsigned int                  WDB_CTRL_EMPTY : 1;
+        unsigned int                       ARB_WLAST : 1;
+        unsigned int                     ARB_WSTRB_q : 8;
+        unsigned int                  WDB_RTR_SKID_4 : 1;
+        unsigned int                WDAT_REG_VALID_q : 1;
+        unsigned int                          WDB_WE : 1;
+        unsigned int                   WDAT_REG_WE_q : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG47 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              WDB_WDC_WDATA_31_0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG48 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             WDB_WDC_WDATA_63_32 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG49 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        BREADY_q : 1;
+        unsigned int                        BVALID_q : 1;
+        unsigned int                         RLAST_q : 1;
+        unsigned int                        RREADY_q : 1;
+        unsigned int                        RVALID_q : 1;
+        unsigned int                  RARC_CTRL_RE_q : 1;
+        unsigned int                   ARC_CTRL_RE_q : 1;
+        unsigned int               INFLT_LIMIT_CNT_q : 6;
+        unsigned int                   INFLT_LIMIT_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                  ARQ_CTRL_WRITE : 1;
+        unsigned int                  ARQ_CTRL_EMPTY : 1;
+        unsigned int                 CTRL_RARC_EMPTY : 1;
+        unsigned int                  CTRL_ARC_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG50 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_CP_grb_send : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int    MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3;
+        unsigned int                     CNT_HOLD_q1 : 1;
+        unsigned int            TLBMISS_RETURN_CNT_q : 6;
+        unsigned int                 MMU_ID_RESPONSE : 1;
+        unsigned int         OUTSTANDING_MMUID_CNT_q : 6;
+        unsigned int                MMU_ID_REQUEST_q : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                       RDC_RRESP : 2;
+        unsigned int                       RDC_RLAST : 1;
+        unsigned int                         RDC_RID : 3;
+        unsigned int                       RDC_VALID : 1;
+        unsigned int                   TLBMISS_VALID : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                    MH_TC_mcsend : 1;
+        unsigned int                 MH_VGT_grb_send : 1;
+        unsigned int                  MH_CP_grb_send : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG51 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               RF_MMU_PAGE_FAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG52 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+        unsigned int                          ARB_WE : 1;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int               client_behavior_q : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               client_behavior_q : 2;
+        unsigned int                     ARB_WRITE_q : 1;
+        unsigned int                        ARB_ID_q : 3;
+        unsigned int         RF_MMU_CONFIG_q_25_to_4 : 22;
+        unsigned int                         MMU_RTR : 1;
+        unsigned int                          ARB_WE : 1;
+        unsigned int          RF_MMU_CONFIG_q_1_to_0 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG53 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    stage1_valid : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 REQ_VA_OFFSET_q : 16;
+        unsigned int        MMU_SPLIT_MODE_nonTC_HIT : 1;
+        unsigned int       MMU_SPLIT_MODE_nonTC_MISS : 1;
+        unsigned int           MMU_SPLIT_MODE_TC_HIT : 1;
+        unsigned int          MMU_SPLIT_MODE_TC_MISS : 1;
+        unsigned int                   MMU_WRITE_HIT : 1;
+        unsigned int                    MMU_READ_HIT : 1;
+        unsigned int                         MMU_HIT : 1;
+        unsigned int                  MMU_WRITE_MISS : 1;
+        unsigned int                   MMU_READ_MISS : 1;
+        unsigned int                        MMU_MISS : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                    stage1_valid : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG54 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         ARQ_RTR : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                    stage2_valid : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                     TAG_valid_q : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     TAG_valid_q : 16;
+        unsigned int            PTE_FETCH_COMPLETE_q : 1;
+        unsigned int                   va_in_range_q : 1;
+        unsigned int                      tag_miss_q : 1;
+        unsigned int                     tag_match_q : 1;
+        unsigned int               IGNORE_TAG_MISS_q : 1;
+        unsigned int               client_behavior_q : 2;
+        unsigned int                    stage2_valid : 1;
+        unsigned int                    stage1_valid : 1;
+        unsigned int                 pa_in_mpu_range : 1;
+        unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1;
+        unsigned int                 MH_TLBMISS_SEND : 1;
+        unsigned int                TLBMISS_CTRL_RTS : 1;
+        unsigned int               CTRL_TLBMISS_RE_q : 1;
+        unsigned int                          MMU_WE : 1;
+        unsigned int                         ARQ_RTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG55 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG0_VA : 13;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_1 : 1;
+        unsigned int                         TAG1_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_0 : 1;
+        unsigned int                         TAG0_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG56 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG2_VA : 13;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_3 : 1;
+        unsigned int                         TAG3_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_2 : 1;
+        unsigned int                         TAG2_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG57 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG4_VA : 13;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_5 : 1;
+        unsigned int                         TAG5_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_4 : 1;
+        unsigned int                         TAG4_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG58 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG6_VA : 13;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_7 : 1;
+        unsigned int                         TAG7_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_6 : 1;
+        unsigned int                         TAG6_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG59 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         TAG8_VA : 13;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                   TAG_valid_q_9 : 1;
+        unsigned int                         TAG9_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                   TAG_valid_q_8 : 1;
+        unsigned int                         TAG8_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG60 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG10_VA : 13;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_11 : 1;
+        unsigned int                        TAG11_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_10 : 1;
+        unsigned int                        TAG10_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG61 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG12_VA : 13;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_13 : 1;
+        unsigned int                        TAG13_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_12 : 1;
+        unsigned int                        TAG12_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG62 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        TAG14_VA : 13;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                                 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 2;
+        unsigned int                  TAG_valid_q_15 : 1;
+        unsigned int                        TAG15_VA : 13;
+        unsigned int                     ALWAYS_ZERO : 2;
+        unsigned int                  TAG_valid_q_14 : 1;
+        unsigned int                        TAG14_VA : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_DEBUG_REG63 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  MH_DBG_DEFAULT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      MMU_ENABLE : 1;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int              PA_W_CLNT_BEHAVIOR : 2;
+        unsigned int              TC_R_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R1_CLNT_BEHAVIOR : 2;
+        unsigned int            VGT_R0_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R4_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R3_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R2_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R1_CLNT_BEHAVIOR : 2;
+        unsigned int             CP_R0_CLNT_BEHAVIOR : 2;
+        unsigned int              CP_W_CLNT_BEHAVIOR : 2;
+        unsigned int              RB_W_CLNT_BEHAVIOR : 2;
+        unsigned int                       RESERVED1 : 2;
+        unsigned int               SPLIT_MODE_ENABLE : 1;
+        unsigned int                      MMU_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_VA_RANGE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                NUM_64KB_REGIONS : 12;
+        unsigned int                         VA_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         VA_BASE : 20;
+        unsigned int                NUM_64KB_REGIONS : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PT_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         PT_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         PT_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_PAGE_FAULT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PAGE_FAULT : 1;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int                          REQ_VA : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          REQ_VA : 20;
+        unsigned int          WRITE_PROTECTION_ERROR : 1;
+        unsigned int           READ_PROTECTION_ERROR : 1;
+        unsigned int            ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int        MPU_ADDRESS_OUT_OF_RANGE : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                          AXI_ID : 3;
+        unsigned int                   CLNT_BEHAVIOR : 2;
+        unsigned int                         OP_TYPE : 1;
+        unsigned int                      PAGE_FAULT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_TRAN_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                      TRAN_ERROR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      TRAN_ERROR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_INVALIDATE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  INVALIDATE_ALL : 1;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                   INVALIDATE_TC : 1;
+        unsigned int                  INVALIDATE_ALL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                        MPU_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        MPU_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MH_MMU_MPU_END {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                         MPU_END : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         MPU_END : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union WAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int                                 : 2;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                 CMDFIFO_ENTRIES : 4;
+        unsigned int                                 : 2;
+        unsigned int               WAIT_3D_IDLECLEAN : 1;
+        unsigned int               WAIT_2D_IDLECLEAN : 1;
+        unsigned int                    WAIT_3D_IDLE : 1;
+        unsigned int                    WAIT_2D_IDLE : 1;
+        unsigned int                                 : 3;
+        unsigned int                    WAIT_CMDFIFO : 1;
+        unsigned int                                 : 3;
+        unsigned int                  WAIT_DSPLY_ID2 : 1;
+        unsigned int                  WAIT_DSPLY_ID1 : 1;
+        unsigned int                  WAIT_DSPLY_ID0 : 1;
+        unsigned int                      WAIT_VSYNC : 1;
+        unsigned int                   WAIT_FE_VSYNC : 1;
+        unsigned int                   WAIT_RE_VSYNC : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_ISYNC_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 4;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int         ISYNC_CPSCRATCH_IDLEGUI : 1;
+        unsigned int              ISYNC_WAIT_IDLEGUI : 1;
+        unsigned int                                 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CMDFIFO_AVAIL : 5;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                      GUI_ACTIVE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      GUI_ACTIVE : 1;
+        unsigned int                    RB_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SQ_CNTX0_BUSY : 1;
+        unsigned int                  SQ_CNTX17_BUSY : 1;
+        unsigned int                        VGT_BUSY : 1;
+        unsigned int                         PA_BUSY : 1;
+        unsigned int                    SC_CNTX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                        TPC_BUSY : 1;
+        unsigned int                         SX_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int               MH_COHERENCY_BUSY : 1;
+        unsigned int                         MH_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                    RBBM_WU_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                 VGT_BUSY_NO_DMA : 1;
+        unsigned int                    PFRQ_PENDING : 1;
+        unsigned int                    CFRQ_PENDING : 1;
+        unsigned int                    CPRQ_PENDING : 1;
+        unsigned int                    HIRQ_PENDING : 1;
+        unsigned int                                 : 2;
+        unsigned int                         TC_BUSY : 1;
+        unsigned int                   CMDFIFO_AVAIL : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DSPLY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                DMI_CH4_NUM_BUFS : 2;
+        unsigned int                 DMI_CH4_SW_CNTL : 1;
+        unsigned int              DMI_CH4_USE_BUFID2 : 1;
+        unsigned int              DMI_CH4_USE_BUFID1 : 1;
+        unsigned int              DMI_CH4_USE_BUFID0 : 1;
+        unsigned int                DMI_CH3_NUM_BUFS : 2;
+        unsigned int                 DMI_CH3_SW_CNTL : 1;
+        unsigned int              DMI_CH3_USE_BUFID2 : 1;
+        unsigned int              DMI_CH3_USE_BUFID1 : 1;
+        unsigned int              DMI_CH3_USE_BUFID0 : 1;
+        unsigned int                                 : 2;
+        unsigned int              DMI_CHANNEL_SELECT : 2;
+        unsigned int                DMI_CH2_NUM_BUFS : 2;
+        unsigned int                 DMI_CH2_SW_CNTL : 1;
+        unsigned int              DMI_CH2_USE_BUFID2 : 1;
+        unsigned int              DMI_CH2_USE_BUFID1 : 1;
+        unsigned int              DMI_CH2_USE_BUFID0 : 1;
+        unsigned int                DMI_CH1_NUM_BUFS : 2;
+        unsigned int                 DMI_CH1_SW_CNTL : 1;
+        unsigned int              DMI_CH1_USE_BUFID2 : 1;
+        unsigned int              DMI_CH1_USE_BUFID1 : 1;
+        unsigned int              DMI_CH1_USE_BUFID0 : 1;
+        unsigned int             SEL_DMI_VSYNC_VALID : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID2 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID1 : 1;
+        unsigned int           SEL_DMI_ACTIVE_BUFID0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RENDER_LATEST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH4_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH3_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH2_BUFFER_ID : 2;
+        unsigned int                                 : 6;
+        unsigned int               DMI_CH1_BUFFER_ID : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_RTL_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      CHANGELIST : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      CHANGELIST : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PATCH_RELEASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PATCH_REVISION : 16;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                     CUSTOMER_ID : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     CUSTOMER_ID : 8;
+        unsigned int                 PATCH_SELECTION : 8;
+        unsigned int                  PATCH_REVISION : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_AUXILIARY_CONFIG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER0 : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     PARTNUMBER0 : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PARTNUMBER1 : 4;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       DESIGNER0 : 4;
+        unsigned int                     PARTNUMBER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DESIGNER1 : 4;
+        unsigned int                        REVISION : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        REVISION : 4;
+        unsigned int                       DESIGNER1 : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERIPHID3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int                                 : 1;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                    CONTINUATION : 1;
+        unsigned int                                 : 1;
+        unsigned int                    MH_INTERFACE : 2;
+        unsigned int            GARB_SLAVE_INTERFACE : 2;
+        unsigned int             RBBM_HOST_INTERFACE : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    READ_TIMEOUT : 8;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int            REGCLK_DEASSERT_TIME : 9;
+        unsigned int                    READ_TIMEOUT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SKEW_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                      SKEW_COUNT : 5;
+        unsigned int              SKEW_TOP_THRESHOLD : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_SOFT_RESET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SOFT_RESET_CP : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                                 : 5;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 2;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                                 : 15;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 15;
+        unsigned int                  SOFT_RESET_VGT : 1;
+        unsigned int                   SOFT_RESET_SC : 1;
+        unsigned int                                 : 2;
+        unsigned int                  SOFT_RESET_CIB : 1;
+        unsigned int                                 : 5;
+        unsigned int                   SOFT_RESET_SX : 1;
+        unsigned int                   SOFT_RESET_SQ : 1;
+        unsigned int                   SOFT_RESET_BC : 1;
+        unsigned int                   SOFT_RESET_MH : 1;
+        unsigned int                   SOFT_RESET_PA : 1;
+        unsigned int                                 : 1;
+        unsigned int                   SOFT_RESET_CP : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int       MH_TCROQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_MMU_SCLK_PM_OVERRIDE : 1;
+        unsigned int         MH_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          MH_MH_SCLK_PM_OVERRIDE : 1;
+        unsigned int             RB_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RB_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int            SPI_SCLK_PM_OVERRIDE : 1;
+        unsigned int       CP_G_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         CP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int           CP_G_SCLK_PM_OVERRIDE : 1;
+        unsigned int         TP_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          TP_TP_SCLK_PM_OVERRIDE : 1;
+        unsigned int   TCF_TCB_READ_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCB_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCF_TCA_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TPC_TPC_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCD_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCM_SCLK_PM_OVERRIDE : 1;
+        unsigned int        TCM_TCO_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SX_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SX_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SQ_SQ_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1;
+        unsigned int   SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SQ_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          SP_V0_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SP_TOP_SCLK_PM_OVERRIDE : 1;
+        unsigned int             SC_SCLK_PM_OVERRIDE : 1;
+        unsigned int         SC_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int         RBBM_AHBCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PM_OVERRIDE2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int                                 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 20;
+        unsigned int         GC_GA_GMEM3_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM2_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM1_PM_OVERRIDE : 1;
+        unsigned int         GC_GA_GMEM0_PM_OVERRIDE : 1;
+        unsigned int           PERM_SCLK_PM_OVERRIDE : 1;
+        unsigned int     DEBUG_PERF_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_VGT_SCLK_PM_OVERRIDE : 1;
+        unsigned int      VGT_FIFOS_SCLK_PM_OVERRIDE : 1;
+        unsigned int        VGT_REG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_AG_SCLK_PM_OVERRIDE : 1;
+        unsigned int          PA_PA_SCLK_PM_OVERRIDE : 1;
+        unsigned int         PA_REG_SCLK_PM_OVERRIDE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union GC_SYS_IDLE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int                                 : 2;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int                                 : 3;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int            GC_SYS_IDLE_OVERRIDE : 1;
+        unsigned int        GC_SYS_WAIT_DMI_OVERRIDE : 1;
+        unsigned int     GC_SYS_URGENT_RAMP_OVERRIDE : 1;
+        unsigned int                                 : 3;
+        unsigned int                 GC_SYS_WAIT_DMI : 1;
+        unsigned int              GC_SYS_URGENT_RAMP : 1;
+        unsigned int                                 : 2;
+        unsigned int            GC_SYS_WAIT_DMI_MASK : 6;
+        unsigned int               GC_SYS_IDLE_DELAY : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union NQWAIT_UNTIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   WAIT_GUI_IDLE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                   WAIT_GUI_IDLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_OUT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   DEBUG_BUS_OUT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                                 : 3;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 2;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              GPIO_BYTE_LANE_ENB : 4;
+        unsigned int              GPIO_SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int             GPIO_SUB_BLOCK_ADDR : 6;
+        unsigned int                                 : 3;
+        unsigned int                       SW_ENABLE : 1;
+        unsigned int                   SUB_BLOCK_SEL : 4;
+        unsigned int                                 : 2;
+        unsigned int                  SUB_BLOCK_ADDR : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int                                 : 3;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 4;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int                                 : 6;
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int             IGNORE_SX_RBBM_BUSY : 1;
+        unsigned int                                 : 6;
+        unsigned int             CLIENTS_FOR_NRT_RTR : 1;
+        unsigned int      CLIENTS_FOR_NRT_RTR_FOR_HI : 1;
+        unsigned int                  SQ_RBBM_NRTRTR : 1;
+        unsigned int                 VGT_RBBM_NRTRTR : 1;
+        unsigned int                  CP_RBBM_NRTRTR : 1;
+        unsigned int    IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int   IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int    IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1;
+        unsigned int               IGNORE_RTR_FOR_HI : 1;
+        unsigned int                                 : 4;
+        unsigned int       HYSTERESIS_NRT_GUI_ACTIVE : 4;
+        unsigned int                                 : 3;
+        unsigned int           IGNORE_CP_SCHED_NQ_HI : 1;
+        unsigned int           IGNORE_CP_SCHED_ISYNC : 1;
+        unsigned int              IGNORE_CP_SCHED_WU : 1;
+        unsigned int                      IGNORE_RTR : 1;
+        unsigned int                                 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_READ_ERROR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 13;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                      READ_ERROR : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      READ_ERROR : 1;
+        unsigned int                  READ_REQUESTER : 1;
+        unsigned int                                 : 13;
+        unsigned int                    READ_ADDRESS : 15;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_WAIT_IDLE_CLOCKS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int            WAIT_IDLE_CLOCKS_NRT : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_MASK : 1;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_MASK : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_MASK : 1;
+        unsigned int                  RDERR_INT_MASK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  RDERR_INT_STAT : 1;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int               GUI_IDLE_INT_STAT : 1;
+        unsigned int                                 : 17;
+        unsigned int         DISPLAY_UPDATE_INT_STAT : 1;
+        unsigned int                  RDERR_INT_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   RDERR_INT_ACK : 1;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                GUI_IDLE_INT_ACK : 1;
+        unsigned int                                 : 17;
+        unsigned int          DISPLAY_UPDATE_INT_ACK : 1;
+        unsigned int                   RDERR_INT_ACK : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union MASTER_INT_SIGNAL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                   RBBM_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   RBBM_INT_STAT : 1;
+        unsigned int                     CP_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SQ_INT_STAT : 1;
+        unsigned int                                 : 20;
+        unsigned int                     MH_INT_STAT : 1;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PERF_COUNT1_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                 PERF_COUNT1_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  PERF_COUNT1_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RBBM_PERFCOUNTER1_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  PERF_COUNT1_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                  PERF_COUNT1_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                         RB_BASE : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         RB_BASE : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RB_BUFSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 6;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 3;
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  RB_RPTR_WR_ENA : 1;
+        unsigned int                                 : 3;
+        unsigned int                    RB_NO_UPDATE : 1;
+        unsigned int                                 : 6;
+        unsigned int                      RB_POLL_EN : 1;
+        unsigned int                                 : 2;
+        unsigned int                        BUF_SWAP : 2;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BLKSZ : 6;
+        unsigned int                                 : 2;
+        unsigned int                        RB_BUFSZ : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_RPTR_SWAP : 2;
+        unsigned int                    RB_RPTR_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_RPTR_ADDR : 30;
+        unsigned int                    RB_RPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_RPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_RPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_RPTR_WR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      RB_RPTR_WR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                      RB_RPTR_WR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         RB_WPTR : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                         RB_WPTR : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_DELAY {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 PRE_WRITE_TIMER : 28;
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 PRE_WRITE_LIMIT : 4;
+        unsigned int                 PRE_WRITE_TIMER : 28;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_RB_WPTR_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    RB_WPTR_SWAP : 2;
+        unsigned int                    RB_WPTR_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    RB_WPTR_BASE : 30;
+        unsigned int                    RB_WPTR_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB1_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB1_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB1_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB1_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB1_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                        IB2_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        IB2_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_IB2_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       IB2_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                       IB2_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 2;
+        unsigned int                         ST_BASE : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         ST_BASE : 30;
+        unsigned int                                 : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ST_BUFSZ {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        ST_BUFSZ : 20;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                        ST_BUFSZ : 20;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_QUEUE_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   CSQ_IB1_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 12;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 12;
+        unsigned int                    CSQ_ST_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB2_START : 4;
+        unsigned int                                 : 4;
+        unsigned int                   CSQ_IB1_START : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_THRESHOLDS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 16;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                         ROQ_END : 5;
+        unsigned int                                 : 3;
+        unsigned int                         MEQ_END : 5;
+        unsigned int                                 : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CSQ_CNT_RING : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     CSQ_CNT_IB2 : 7;
+        unsigned int                                 : 1;
+        unsigned int                     CSQ_CNT_IB1 : 7;
+        unsigned int                                 : 1;
+        unsigned int                    CSQ_CNT_RING : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STQ_CNT_ST : 7;
+        unsigned int                                 : 25;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 25;
+        unsigned int                      STQ_CNT_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_AVAIL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         MEQ_CNT : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int                         MEQ_CNT : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_RB_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                CSQ_WPTR_PRIMARY : 7;
+        unsigned int                                 : 9;
+        unsigned int                CSQ_RPTR_PRIMARY : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB1_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT1 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT1 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CSQ_IB2_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int              CSQ_WPTR_INDIRECT2 : 7;
+        unsigned int                                 : 9;
+        unsigned int              CSQ_RPTR_INDIRECT2 : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NON_PREFETCH_CNTRS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     IB1_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 21;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 21;
+        unsigned int                     IB2_COUNTER : 3;
+        unsigned int                                 : 5;
+        unsigned int                     IB1_COUNTER : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STQ_ST_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     STQ_RPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 9;
+        unsigned int                     STQ_WPTR_ST : 7;
+        unsigned int                                 : 9;
+        unsigned int                     STQ_RPTR_ST : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MEQ_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        MEQ_RPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_WPTR : 10;
+        unsigned int                                 : 6;
+        unsigned int                        MEQ_RPTR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_MIU_TAG_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      TAG_0_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                                 : 13;
+        unsigned int              INVALID_RETURN_TAG : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              INVALID_RETURN_TAG : 1;
+        unsigned int                                 : 13;
+        unsigned int                     TAG_17_STAT : 1;
+        unsigned int                     TAG_16_STAT : 1;
+        unsigned int                     TAG_15_STAT : 1;
+        unsigned int                     TAG_14_STAT : 1;
+        unsigned int                     TAG_13_STAT : 1;
+        unsigned int                     TAG_12_STAT : 1;
+        unsigned int                     TAG_11_STAT : 1;
+        unsigned int                     TAG_10_STAT : 1;
+        unsigned int                      TAG_9_STAT : 1;
+        unsigned int                      TAG_8_STAT : 1;
+        unsigned int                      TAG_7_STAT : 1;
+        unsigned int                      TAG_6_STAT : 1;
+        unsigned int                      TAG_5_STAT : 1;
+        unsigned int                      TAG_4_STAT : 1;
+        unsigned int                      TAG_3_STAT : 1;
+        unsigned int                      TAG_2_STAT : 1;
+        unsigned int                      TAG_1_STAT : 1;
+        unsigned int                      TAG_0_STAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       CMD_INDEX : 7;
+        unsigned int                                 : 9;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                   CMD_QUEUE_SEL : 2;
+        unsigned int                                 : 9;
+        unsigned int                       CMD_INDEX : 7;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_CMD_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CMD_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CMD_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ME_STATMUX : 16;
+        unsigned int                                 : 9;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                   PROG_CNT_SIZE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   PROG_CNT_SIZE : 1;
+        unsigned int                                 : 1;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                         ME_HALT : 1;
+        unsigned int                                 : 1;
+        unsigned int          PIX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int          VTX_DEALLOC_FIFO_EMPTY : 1;
+        unsigned int                                 : 9;
+        unsigned int                      ME_STATMUX : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ME_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ME_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_WADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_WADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_WADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_RADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    ME_RAM_RADDR : 10;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int                    ME_RAM_RADDR : 10;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RAM_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ME_RAM_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     ME_RAM_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_RDADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ME_RDADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ME_RDADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_DEBUG {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int                                 : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int          MIU_WRITE_PACK_DISABLE : 1;
+        unsigned int          SIMPLE_ME_FLOW_CONTROL : 1;
+        unsigned int                                 : 1;
+        unsigned int          PREFETCH_MATCH_DISABLE : 1;
+        unsigned int             DYNAMIC_CLK_DISABLE : 1;
+        unsigned int              PREFETCH_PASS_NOPS : 1;
+        unsigned int         MIU_128BIT_WRITE_ENABLE : 1;
+        unsigned int             PROG_END_PTR_ENABLE : 1;
+        unsigned int               PREDICATE_DISABLE : 1;
+        unsigned int         CP_DEBUG_UNUSED_22_to_0 : 23;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG0 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG0 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG1 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG1 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG2 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG2 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG3 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG3 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG4 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG4 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG5 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG5 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG6 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG6 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_REG7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_REG7 : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_REG7 : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_UMSK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    SCRATCH_UMSK : 8;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int                    SCRATCH_SWAP : 2;
+        unsigned int                                 : 8;
+        unsigned int                    SCRATCH_UMSK : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union SCRATCH_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 5;
+        unsigned int                    SCRATCH_ADDR : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    SCRATCH_ADDR : 27;
+        unsigned int                                 : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     VS_DONE_SWM : 1;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    VS_DONE_CNTR : 1;
+        unsigned int                     VS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_SWAP : 2;
+        unsigned int                    VS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_ADDR : 30;
+        unsigned int                    VS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    VS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    VS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_ADDR_SWM : 30;
+        unsigned int                VS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                VS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     PS_DONE_SWM : 1;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int                    PS_DONE_CNTR : 1;
+        unsigned int                     PS_DONE_SWM : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_SWAP : 2;
+        unsigned int                    PS_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_ADDR : 30;
+        unsigned int                    PS_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PS_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PS_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_ADDR_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_ADDR_SWM : 30;
+        unsigned int                PS_DONE_SWAP_SWM : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_PS_EVENT_DATA_SWM {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                PS_DONE_DATA_SWM : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     CF_DONE_SRC : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                     CF_DONE_SRC : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_SWAP : 2;
+        unsigned int                    CF_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_ADDR : 30;
+        unsigned int                    CF_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_CF_EVENT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    CF_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    CF_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_SWAP : 2;
+        unsigned int                  NRT_WRITE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_ADDR : 30;
+        unsigned int                  NRT_WRITE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_NRT_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  NRT_WRITE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  NRT_WRITE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_SRC {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int              VS_FETCH_DONE_CNTR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_ADDR : 30;
+        unsigned int              VS_FETCH_DONE_SWAP : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_ME_VS_FETCH_DONE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int              VS_FETCH_DONE_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                     RB_INT_MASK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_MASK : 1;
+        unsigned int                    IB1_INT_MASK : 1;
+        unsigned int                    IB2_INT_MASK : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_MASK : 1;
+        unsigned int         RESERVED_BIT_ERROR_MASK : 1;
+        unsigned int       PROTECTED_MODE_ERROR_MASK : 1;
+        unsigned int               OPCODE_ERROR_MASK : 1;
+        unsigned int            T0_PACKET_IN_IB_MASK : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_MASK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_STATUS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                     RB_INT_STAT : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     RB_INT_STAT : 1;
+        unsigned int                    IB1_INT_STAT : 1;
+        unsigned int                    IB2_INT_STAT : 1;
+        unsigned int                                 : 1;
+        unsigned int                   IB_ERROR_STAT : 1;
+        unsigned int         RESERVED_BIT_ERROR_STAT : 1;
+        unsigned int       PROTECTED_MODE_ERROR_STAT : 1;
+        unsigned int               OPCODE_ERROR_STAT : 1;
+        unsigned int            T0_PACKET_IN_IB_STAT : 1;
+        unsigned int                                 : 3;
+        unsigned int                     SW_INT_STAT : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_INT_ACK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 19;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                      RB_INT_ACK : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      RB_INT_ACK : 1;
+        unsigned int                     IB1_INT_ACK : 1;
+        unsigned int                     IB2_INT_ACK : 1;
+        unsigned int                                 : 1;
+        unsigned int                    IB_ERROR_ACK : 1;
+        unsigned int          RESERVED_BIT_ERROR_ACK : 1;
+        unsigned int        PROTECTED_MODE_ERROR_ACK : 1;
+        unsigned int                OPCODE_ERROR_ACK : 1;
+        unsigned int             T0_PACKET_IN_IB_ACK : 1;
+        unsigned int                                 : 3;
+        unsigned int                      SW_INT_ACK : 1;
+        unsigned int                                 : 19;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_ADDR : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                      UCODE_ADDR : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PFP_UCODE_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      UCODE_DATA : 24;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                      UCODE_DATA : 24;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFMON_CNTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFMON_STATE : 4;
+        unsigned int                                 : 4;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 22;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 22;
+        unsigned int             PERFMON_ENABLE_MODE : 2;
+        unsigned int                                 : 4;
+        unsigned int                   PERFMON_STATE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   PERFCOUNT_SEL : 6;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                   PERFCOUNT_SEL : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    PERFCOUNT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PERFCOUNTER_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    PERFCOUNT_HI : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    PERFCOUNT_HI : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_MASK_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BIN_MASK_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     BIN_MASK_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_LO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_LO : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_LO : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_BIN_SELECT_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   BIN_SELECT_HI : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   BIN_SELECT_HI : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       DISCARD_0 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_15 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_15 : 1;
+        unsigned int                      DISCARD_15 : 1;
+        unsigned int                     END_RCVD_14 : 1;
+        unsigned int                      DISCARD_14 : 1;
+        unsigned int                     END_RCVD_13 : 1;
+        unsigned int                      DISCARD_13 : 1;
+        unsigned int                     END_RCVD_12 : 1;
+        unsigned int                      DISCARD_12 : 1;
+        unsigned int                     END_RCVD_11 : 1;
+        unsigned int                      DISCARD_11 : 1;
+        unsigned int                     END_RCVD_10 : 1;
+        unsigned int                      DISCARD_10 : 1;
+        unsigned int                      END_RCVD_9 : 1;
+        unsigned int                       DISCARD_9 : 1;
+        unsigned int                      END_RCVD_8 : 1;
+        unsigned int                       DISCARD_8 : 1;
+        unsigned int                      END_RCVD_7 : 1;
+        unsigned int                       DISCARD_7 : 1;
+        unsigned int                      END_RCVD_6 : 1;
+        unsigned int                       DISCARD_6 : 1;
+        unsigned int                      END_RCVD_5 : 1;
+        unsigned int                       DISCARD_5 : 1;
+        unsigned int                      END_RCVD_4 : 1;
+        unsigned int                       DISCARD_4 : 1;
+        unsigned int                      END_RCVD_3 : 1;
+        unsigned int                       DISCARD_3 : 1;
+        unsigned int                      END_RCVD_2 : 1;
+        unsigned int                       DISCARD_2 : 1;
+        unsigned int                      END_RCVD_1 : 1;
+        unsigned int                       DISCARD_1 : 1;
+        unsigned int                      END_RCVD_0 : 1;
+        unsigned int                       DISCARD_0 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_16 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_31 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_31 : 1;
+        unsigned int                      DISCARD_31 : 1;
+        unsigned int                     END_RCVD_30 : 1;
+        unsigned int                      DISCARD_30 : 1;
+        unsigned int                     END_RCVD_29 : 1;
+        unsigned int                      DISCARD_29 : 1;
+        unsigned int                     END_RCVD_28 : 1;
+        unsigned int                      DISCARD_28 : 1;
+        unsigned int                     END_RCVD_27 : 1;
+        unsigned int                      DISCARD_27 : 1;
+        unsigned int                     END_RCVD_26 : 1;
+        unsigned int                      DISCARD_26 : 1;
+        unsigned int                     END_RCVD_25 : 1;
+        unsigned int                      DISCARD_25 : 1;
+        unsigned int                     END_RCVD_24 : 1;
+        unsigned int                      DISCARD_24 : 1;
+        unsigned int                     END_RCVD_23 : 1;
+        unsigned int                      DISCARD_23 : 1;
+        unsigned int                     END_RCVD_22 : 1;
+        unsigned int                      DISCARD_22 : 1;
+        unsigned int                     END_RCVD_21 : 1;
+        unsigned int                      DISCARD_21 : 1;
+        unsigned int                     END_RCVD_20 : 1;
+        unsigned int                      DISCARD_20 : 1;
+        unsigned int                     END_RCVD_19 : 1;
+        unsigned int                      DISCARD_19 : 1;
+        unsigned int                     END_RCVD_18 : 1;
+        unsigned int                      DISCARD_18 : 1;
+        unsigned int                     END_RCVD_17 : 1;
+        unsigned int                      DISCARD_17 : 1;
+        unsigned int                     END_RCVD_16 : 1;
+        unsigned int                      DISCARD_16 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_32 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_47 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_47 : 1;
+        unsigned int                      DISCARD_47 : 1;
+        unsigned int                     END_RCVD_46 : 1;
+        unsigned int                      DISCARD_46 : 1;
+        unsigned int                     END_RCVD_45 : 1;
+        unsigned int                      DISCARD_45 : 1;
+        unsigned int                     END_RCVD_44 : 1;
+        unsigned int                      DISCARD_44 : 1;
+        unsigned int                     END_RCVD_43 : 1;
+        unsigned int                      DISCARD_43 : 1;
+        unsigned int                     END_RCVD_42 : 1;
+        unsigned int                      DISCARD_42 : 1;
+        unsigned int                     END_RCVD_41 : 1;
+        unsigned int                      DISCARD_41 : 1;
+        unsigned int                     END_RCVD_40 : 1;
+        unsigned int                      DISCARD_40 : 1;
+        unsigned int                     END_RCVD_39 : 1;
+        unsigned int                      DISCARD_39 : 1;
+        unsigned int                     END_RCVD_38 : 1;
+        unsigned int                      DISCARD_38 : 1;
+        unsigned int                     END_RCVD_37 : 1;
+        unsigned int                      DISCARD_37 : 1;
+        unsigned int                     END_RCVD_36 : 1;
+        unsigned int                      DISCARD_36 : 1;
+        unsigned int                     END_RCVD_35 : 1;
+        unsigned int                      DISCARD_35 : 1;
+        unsigned int                     END_RCVD_34 : 1;
+        unsigned int                      DISCARD_34 : 1;
+        unsigned int                     END_RCVD_33 : 1;
+        unsigned int                      DISCARD_33 : 1;
+        unsigned int                     END_RCVD_32 : 1;
+        unsigned int                      DISCARD_32 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_NV_FLAGS_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      DISCARD_48 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_63 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     END_RCVD_63 : 1;
+        unsigned int                      DISCARD_63 : 1;
+        unsigned int                     END_RCVD_62 : 1;
+        unsigned int                      DISCARD_62 : 1;
+        unsigned int                     END_RCVD_61 : 1;
+        unsigned int                      DISCARD_61 : 1;
+        unsigned int                     END_RCVD_60 : 1;
+        unsigned int                      DISCARD_60 : 1;
+        unsigned int                     END_RCVD_59 : 1;
+        unsigned int                      DISCARD_59 : 1;
+        unsigned int                     END_RCVD_58 : 1;
+        unsigned int                      DISCARD_58 : 1;
+        unsigned int                     END_RCVD_57 : 1;
+        unsigned int                      DISCARD_57 : 1;
+        unsigned int                     END_RCVD_56 : 1;
+        unsigned int                      DISCARD_56 : 1;
+        unsigned int                     END_RCVD_55 : 1;
+        unsigned int                      DISCARD_55 : 1;
+        unsigned int                     END_RCVD_54 : 1;
+        unsigned int                      DISCARD_54 : 1;
+        unsigned int                     END_RCVD_53 : 1;
+        unsigned int                      DISCARD_53 : 1;
+        unsigned int                     END_RCVD_52 : 1;
+        unsigned int                      DISCARD_52 : 1;
+        unsigned int                     END_RCVD_51 : 1;
+        unsigned int                      DISCARD_51 : 1;
+        unsigned int                     END_RCVD_50 : 1;
+        unsigned int                      DISCARD_50 : 1;
+        unsigned int                     END_RCVD_49 : 1;
+        unsigned int                      DISCARD_49 : 1;
+        unsigned int                     END_RCVD_48 : 1;
+        unsigned int                      DISCARD_48 : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_INDEX {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               STATE_DEBUG_INDEX : 5;
+        unsigned int                                 : 27;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 27;
+        unsigned int               STATE_DEBUG_INDEX : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STATE_DEBUG_DATA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                STATE_DEBUG_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                STATE_DEBUG_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_PROG_COUNTER {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         COUNTER : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         COUNTER : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union CP_STAT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     MIU_WR_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                         CP_BUSY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                         CP_BUSY : 1;
+        unsigned int         MIU_WC_TRACK_FIFO_EMPTY : 1;
+        unsigned int                      ME_WC_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                         ME_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int                        _3D_BUSY : 1;
+        unsigned int                     CP_NRT_BUSY : 1;
+        unsigned int                    MIU_WC_STALL : 1;
+        unsigned int              MEQ_INDIRECT2_BUSY : 1;
+        unsigned int              MEQ_INDIRECTS_BUSY : 1;
+        unsigned int                   MEQ_RING_BUSY : 1;
+        unsigned int                        PFP_BUSY : 1;
+        unsigned int                   ST_QUEUE_BUSY : 1;
+        unsigned int                                 : 2;
+        unsigned int            INDIRECT2_QUEUE_BUSY : 1;
+        unsigned int            INDIRECTS_QUEUE_BUSY : 1;
+        unsigned int                 RING_QUEUE_BUSY : 1;
+        unsigned int                        CSF_BUSY : 1;
+        unsigned int                     CSF_ST_BUSY : 1;
+        unsigned int                                 : 1;
+        unsigned int              CSF_INDIRECT2_BUSY : 1;
+        unsigned int              CSF_INDIRECTS_BUSY : 1;
+        unsigned int                   CSF_RING_BUSY : 1;
+        unsigned int                       RCIU_BUSY : 1;
+        unsigned int                       RBIU_BUSY : 1;
+        unsigned int              MIU_RD_RETURN_BUSY : 1;
+        unsigned int                 MIU_RD_REQ_BUSY : 1;
+        unsigned int                     MIU_WR_BUSY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_0_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_1_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_2_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_3_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_4_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_5_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_6_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_7_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_8_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_9_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_10_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_11_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_12_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_13_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_14_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BIOS_15_SCRATCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    BIOS_SCRATCH : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    BIOS_SCRATCH : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_PM4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_SIZE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            SIZE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            SIZE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_BASE_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                            BASE : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                            BASE : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_STATUS_HOST {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               MATCHING_CONTEXTS : 8;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 5;
+        unsigned int                          STATUS : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                          STATUS : 1;
+        unsigned int                                 : 5;
+        unsigned int                   TC_ACTION_ENA : 1;
+        unsigned int                                 : 7;
+        unsigned int               RB_COLOR_INFO_ENA : 1;
+        unsigned int                 DEST_BASE_7_ENA : 1;
+        unsigned int                 DEST_BASE_6_ENA : 1;
+        unsigned int                 DEST_BASE_5_ENA : 1;
+        unsigned int                 DEST_BASE_4_ENA : 1;
+        unsigned int                 DEST_BASE_3_ENA : 1;
+        unsigned int                 DEST_BASE_2_ENA : 1;
+        unsigned int                 DEST_BASE_1_ENA : 1;
+        unsigned int                 DEST_BASE_0_ENA : 1;
+        unsigned int           RB_COPY_DEST_BASE_ENA : 1;
+        unsigned int               MATCHING_CONTEXTS : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_0 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_0 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_1 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_1 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_2 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_2 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_3 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_3 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_4 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_4 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_5 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_5 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_5 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_6 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_6 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_6 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union COHER_DEST_BASE_7 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                     DEST_BASE_7 : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEST_BASE_7 : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SURFACE_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SURFACE_PITCH : 14;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                    MSAA_SAMPLES : 2;
+        unsigned int                   SURFACE_PITCH : 14;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    COLOR_FORMAT : 4;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      COLOR_BASE : 20;
+        unsigned int                                 : 1;
+        unsigned int                      COLOR_SWAP : 2;
+        unsigned int                    COLOR_ENDIAN : 2;
+        unsigned int                    COLOR_LINEAR : 1;
+        unsigned int                COLOR_ROUND_MODE : 2;
+        unsigned int                    COLOR_FORMAT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                    DEPTH_FORMAT : 1;
+        unsigned int                                 : 11;
+        unsigned int                      DEPTH_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      DEPTH_BASE : 20;
+        unsigned int                                 : 11;
+        unsigned int                    DEPTH_FORMAT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      STENCILREF : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED1 : 1;
+        unsigned int                       RESERVED0 : 1;
+        unsigned int                STENCILWRITEMASK : 8;
+        unsigned int                     STENCILMASK : 8;
+        unsigned int                      STENCILREF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ALPHA_REF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       ALPHA_REF : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       ALPHA_REF : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       WRITE_RED : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                                 : 26;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 26;
+        unsigned int                       RESERVED3 : 1;
+        unsigned int                       RESERVED2 : 1;
+        unsigned int                     WRITE_ALPHA : 1;
+        unsigned int                      WRITE_BLUE : 1;
+        unsigned int                     WRITE_GREEN : 1;
+        unsigned int                       WRITE_RED : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_RED {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                       BLEND_RED : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                       BLEND_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_GREEN {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_GREEN : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_GREEN : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_BLUE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      BLEND_BLUE : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      BLEND_BLUE : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLEND_ALPHA {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     BLEND_ALPHA : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                     BLEND_ALPHA : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FOG_COLOR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                         FOG_RED : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                                 : 8;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 8;
+        unsigned int                        FOG_BLUE : 8;
+        unsigned int                       FOG_GREEN : 8;
+        unsigned int                         FOG_RED : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_STENCILREFMASK_BF {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   STENCILREF_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                       RESERVED5 : 1;
+        unsigned int                       RESERVED4 : 1;
+        unsigned int             STENCILWRITEMASK_BF : 8;
+        unsigned int                  STENCILMASK_BF : 8;
+        unsigned int                   STENCILREF_BF : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTHCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  STENCIL_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                 STENCILZFAIL_BF : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 STENCILZFAIL_BF : 3;
+        unsigned int                 STENCILZPASS_BF : 3;
+        unsigned int                  STENCILFAIL_BF : 3;
+        unsigned int                  STENCILFUNC_BF : 3;
+        unsigned int                    STENCILZFAIL : 3;
+        unsigned int                    STENCILZPASS : 3;
+        unsigned int                     STENCILFAIL : 3;
+        unsigned int                     STENCILFUNC : 3;
+        unsigned int                 BACKFACE_ENABLE : 1;
+        unsigned int                           ZFUNC : 3;
+        unsigned int                  EARLY_Z_ENABLE : 1;
+        unsigned int                  Z_WRITE_ENABLE : 1;
+        unsigned int                        Z_ENABLE : 1;
+        unsigned int                  STENCIL_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BLENDCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  COLOR_SRCBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int                                 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 1;
+        unsigned int                     BLEND_FORCE : 1;
+        unsigned int              BLEND_FORCE_ENABLE : 1;
+        unsigned int                 ALPHA_DESTBLEND : 5;
+        unsigned int                  ALPHA_COMB_FCN : 3;
+        unsigned int                  ALPHA_SRCBLEND : 5;
+        unsigned int                                 : 3;
+        unsigned int                 COLOR_DESTBLEND : 5;
+        unsigned int                  COLOR_COMB_FCN : 3;
+        unsigned int                  COLOR_SRCBLEND : 5;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLORCONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      ALPHA_FUNC : 3;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                                 : 7;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+#else       /* !defined(qLittleEndian) */
+        unsigned int           ALPHA_TO_MASK_OFFSET3 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET2 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET1 : 2;
+        unsigned int           ALPHA_TO_MASK_OFFSET0 : 2;
+        unsigned int                                 : 7;
+        unsigned int                       PIXEL_FOG : 1;
+        unsigned int                     DITHER_TYPE : 2;
+        unsigned int                     DITHER_MODE : 2;
+        unsigned int                        ROP_CODE : 4;
+        unsigned int                  VS_EXPORTS_FOG : 1;
+        unsigned int                      FOG_ENABLE : 1;
+        unsigned int                   BLEND_DISABLE : 1;
+        unsigned int            ALPHA_TO_MASK_ENABLE : 1;
+        unsigned int               ALPHA_TEST_ENABLE : 1;
+        unsigned int                      ALPHA_FUNC : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_MODECONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_MODE : 3;
+        unsigned int                                 : 29;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 29;
+        unsigned int                      EDRAM_MODE : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COLOR_DEST_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COLOR_DEST_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 COLOR_DEST_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                      CLEAR_MASK : 4;
+        unsigned int              DEPTH_CLEAR_ENABLE : 1;
+        unsigned int              COPY_SAMPLE_SELECT : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_BASE {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                                 : 12;
+        unsigned int                  COPY_DEST_BASE : 20;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                  COPY_DEST_BASE : 20;
+        unsigned int                                 : 12;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PITCH {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 COPY_DEST_PITCH : 9;
+        unsigned int                                 : 23;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 23;
+        unsigned int                 COPY_DEST_PITCH : 9;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                COPY_DEST_ENDIAN : 3;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int                                 : 14;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 14;
+        unsigned int           COPY_MASK_WRITE_ALPHA : 1;
+        unsigned int            COPY_MASK_WRITE_BLUE : 1;
+        unsigned int           COPY_MASK_WRITE_GREEN : 1;
+        unsigned int             COPY_MASK_WRITE_RED : 1;
+        unsigned int           COPY_DEST_DITHER_TYPE : 2;
+        unsigned int           COPY_DEST_DITHER_MODE : 2;
+        unsigned int                  COPY_DEST_SWAP : 2;
+        unsigned int                COPY_DEST_FORMAT : 4;
+        unsigned int                COPY_DEST_LINEAR : 1;
+        unsigned int                COPY_DEST_ENDIAN : 3;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_COPY_DEST_PIXEL_OFFSET {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        OFFSET_X : 13;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                                 : 6;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 6;
+        unsigned int                        OFFSET_Y : 13;
+        unsigned int                        OFFSET_X : 13;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEPTH_CLEAR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     DEPTH_CLEAR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     DEPTH_CLEAR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_CTL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int               COPY_SAMPLE_COUNT : 1;
+        unsigned int              RESET_SAMPLE_COUNT : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SAMPLE_COUNT_ADDR {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int               SAMPLE_COUNT_ADDR : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int                                 : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int                       RESERVED6 : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                       RESERVED6 : 1;
+        unsigned int                      CRC_SYSTEM : 1;
+        unsigned int   MEM_EXPORT_LINEAR_MODE_ENABLE : 1;
+        unsigned int       MEM_EXPORT_TIMEOUT_SELECT : 2;
+        unsigned int           ACCUM_DATA_FIFO_LIMIT : 4;
+        unsigned int       LINEAR_PERFORMANCE_ENABLE : 1;
+        unsigned int                ACCUM_ALLOC_MASK : 4;
+        unsigned int                   DISABLE_ACCUM : 1;
+        unsigned int         DISABLE_SAMPLE_COUNTERS : 1;
+        unsigned int                        CRC_MODE : 1;
+        unsigned int               ENABLE_CRC_UPDATE : 1;
+        unsigned int                                 : 1;
+        unsigned int               AZ_THROTTLE_COUNT : 5;
+        unsigned int              ENABLE_AZ_THROTTLE : 1;
+        unsigned int       DISABLE_LZ_NULL_ZCMD_DROP : 1;
+        unsigned int       DISABLE_EZ_NULL_ZCMD_DROP : 1;
+        unsigned int  DISABLE_EZ_FAST_CONTEXT_SWITCH : 1;
+        unsigned int               DISABLE_EDRAM_CAM : 1;
+        unsigned int            ACCUM_TIMEOUT_SELECT : 2;
+        unsigned int        ACCUM_LINEAR_MODE_ENABLE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_EDRAM_INFO {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      EDRAM_SIZE : 4;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                                 : 8;
+        unsigned int                     EDRAM_RANGE : 18;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                     EDRAM_RANGE : 18;
+        unsigned int                                 : 8;
+        unsigned int              EDRAM_MAPPING_MODE : 2;
+        unsigned int                      EDRAM_SIZE : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_RD_PORT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_DATA : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_DATA : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                  CRC_RD_ADVANCE : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                  CRC_RD_ADVANCE : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_CRC_MASK {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        CRC_MASK : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        CRC_MASK : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_SELECT {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        PERF_SEL : 8;
+        unsigned int                                 : 24;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 24;
+        unsigned int                        PERF_SEL : 8;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_LOW {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                      PERF_COUNT : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_PERFCOUNTER0_HI {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                      PERF_COUNT : 16;
+        unsigned int                                 : 16;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 16;
+        unsigned int                      PERF_COUNT : 16;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_TOTAL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   TOTAL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   TOTAL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZPASS_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZPASS_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZPASS_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_ZFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   ZFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_SFAIL_SAMPLES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                   SFAIL_SAMPLES : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                   SFAIL_SAMPLES : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_0 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                 EZ_INFSAMP_FULL : 1;
+        unsigned int                     C_MASK_FULL : 1;
+        unsigned int                      C_REQ_FULL : 1;
+        unsigned int                  C_EZ_TILE_FULL : 1;
+        unsigned int                   C_SX_CMD_FULL : 1;
+        unsigned int                   C_SX_LAT_FULL : 1;
+        unsigned int         CMDFIFO_C_ORDERING_FULL : 1;
+        unsigned int         CMDFIFO_Z_ORDERING_FULL : 1;
+        unsigned int            CMDFIFO_C0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_C1_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z0_HOLD_FULL : 1;
+        unsigned int            CMDFIFO_Z1_HOLD_FULL : 1;
+        unsigned int                   WRREQ_C0_FULL : 1;
+        unsigned int                   WRREQ_C1_FULL : 1;
+        unsigned int                   WRREQ_Z0_FULL : 1;
+        unsigned int                   WRREQ_Z1_FULL : 1;
+        unsigned int              WRREQ_C_WE_LO_FULL : 1;
+        unsigned int              WRREQ_C_WE_HI_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E0_MACRO_HI_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_LO_FULL : 1;
+        unsigned int          WRREQ_E1_MACRO_HI_FULL : 1;
+        unsigned int                   RDREQ_C0_FULL : 1;
+        unsigned int                   RDREQ_C1_FULL : 1;
+        unsigned int                   RDREQ_Z0_FULL : 1;
+        unsigned int                   RDREQ_Z1_FULL : 1;
+        unsigned int          RDREQ_E0_ORDERING_FULL : 1;
+        unsigned int          RDREQ_E1_ORDERING_FULL : 1;
+        unsigned int           RDREQ_CTL_C0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_C1_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z0_PRE_FULL : 1;
+        unsigned int           RDREQ_CTL_Z1_PRE_FULL : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_1 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                EZ_INFSAMP_EMPTY : 1;
+        unsigned int                    C_MASK_EMPTY : 1;
+        unsigned int                     C_REQ_EMPTY : 1;
+        unsigned int                 C_EZ_TILE_EMPTY : 1;
+        unsigned int                  C_SX_CMD_EMPTY : 1;
+        unsigned int                  C_SX_LAT_EMPTY : 1;
+        unsigned int        CMDFIFO_C_ORDERING_EMPTY : 1;
+        unsigned int        CMDFIFO_Z_ORDERING_EMPTY : 1;
+        unsigned int           CMDFIFO_C0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_C1_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z0_HOLD_EMPTY : 1;
+        unsigned int           CMDFIFO_Z1_HOLD_EMPTY : 1;
+        unsigned int              WRREQ_C0_PRE_EMPTY : 1;
+        unsigned int              WRREQ_C1_PRE_EMPTY : 1;
+        unsigned int                  WRREQ_Z0_EMPTY : 1;
+        unsigned int                  WRREQ_Z1_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_LO_EMPTY : 1;
+        unsigned int             WRREQ_C_WE_HI_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E0_MACRO_HI_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_LO_EMPTY : 1;
+        unsigned int         WRREQ_E1_MACRO_HI_EMPTY : 1;
+        unsigned int                  RDREQ_C0_EMPTY : 1;
+        unsigned int                  RDREQ_C1_EMPTY : 1;
+        unsigned int                  RDREQ_Z0_EMPTY : 1;
+        unsigned int                  RDREQ_Z1_EMPTY : 1;
+        unsigned int         RDREQ_E0_ORDERING_EMPTY : 1;
+        unsigned int         RDREQ_E1_ORDERING_EMPTY : 1;
+        unsigned int              RDREQ_C0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_C1_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z0_CMD_EMPTY : 1;
+        unsigned int              RDREQ_Z1_CMD_EMPTY : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_2 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                 TILE_FIFO_COUNT : 4;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z_TILE_EMPTY : 1;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                    Z_TILE_EMPTY : 1;
+        unsigned int                    Z_SAMP_EMPTY : 1;
+        unsigned int                    Z1_REQ_EMPTY : 1;
+        unsigned int                    Z0_REQ_EMPTY : 1;
+        unsigned int                   Z1_MASK_EMPTY : 1;
+        unsigned int                   Z0_MASK_EMPTY : 1;
+        unsigned int             EZ_MASK_UPPER_EMPTY : 1;
+        unsigned int             EZ_MASK_LOWER_EMPTY : 1;
+        unsigned int                EZ_INFTILE_EMPTY : 1;
+        unsigned int                     Z_TILE_FULL : 1;
+        unsigned int                     Z_SAMP_FULL : 1;
+        unsigned int                     Z1_REQ_FULL : 1;
+        unsigned int                     Z0_REQ_FULL : 1;
+        unsigned int                    Z1_MASK_FULL : 1;
+        unsigned int                    Z0_MASK_FULL : 1;
+        unsigned int              EZ_MASK_UPPER_FULL : 1;
+        unsigned int              EZ_MASK_LOWER_FULL : 1;
+        unsigned int                 EZ_INFTILE_FULL : 1;
+        unsigned int              CURRENT_TILE_EVENT : 1;
+        unsigned int               SYSMEM_BLEND_FLAG : 1;
+        unsigned int                 MEM_EXPORT_FLAG : 1;
+        unsigned int               SX_LAT_FIFO_COUNT : 7;
+        unsigned int                 TILE_FIFO_COUNT : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_3 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                     ACCUM_VALID : 4;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                                 : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 3;
+        unsigned int                 ZEXP_UPPER_FULL : 1;
+        unsigned int                 ZEXP_LOWER_FULL : 1;
+        unsigned int                ZEXP_UPPER_EMPTY : 1;
+        unsigned int                ZEXP_LOWER_EMPTY : 1;
+        unsigned int            EZ_RETURN_UPPER_FULL : 1;
+        unsigned int            EZ_RETURN_LOWER_FULL : 1;
+        unsigned int           EZ_RETURN_UPPER_EMPTY : 1;
+        unsigned int           EZ_RETURN_LOWER_EMPTY : 1;
+        unsigned int                       SHD_EMPTY : 1;
+        unsigned int                        SHD_FULL : 1;
+        unsigned int             ACCUM_DATA_FIFO_CNT : 4;
+        unsigned int           ACCUM_INPUT_REG_VALID : 1;
+        unsigned int         ACCUM_WRITE_CLEAN_COUNT : 6;
+        unsigned int                  ACCUM_FLUSHING : 4;
+        unsigned int                     ACCUM_VALID : 4;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_DEBUG_4 {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int                                 : 19;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 19;
+        unsigned int             CONTEXT_COUNT_DEBUG : 4;
+        unsigned int     SYSMEM_WRITE_COUNT_OVERFLOW : 1;
+        unsigned int           ACCUM_ORDER_FIFO_FULL : 1;
+        unsigned int            ACCUM_DATA_FIFO_FULL : 1;
+        unsigned int          ACCUM_ORDER_FIFO_EMPTY : 1;
+        unsigned int           ACCUM_DATA_FIFO_EMPTY : 1;
+        unsigned int           SYSMEM_WR_ACCESS_FLAG : 1;
+        unsigned int           SYSMEM_RD_ACCESS_FLAG : 1;
+        unsigned int             GMEM_WR_ACCESS_FLAG : 1;
+        unsigned int             GMEM_RD_ACCESS_FLAG : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_FLAG_CONTROL {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+        unsigned int                                 : 31;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 31;
+        unsigned int                DEBUG_FLAG_CLEAR : 1;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union RB_BC_SPARES {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int                        RESERVED : 32;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                        RESERVED : 32;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_ENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+#else       /* !defined(qLittleEndian) */
+        unsigned int  DUMMY_RB_COPY_DEST_INFO_NUMBER : 3;
+        unsigned int      DUMMY_CRAYRB_SURFACE_ARRAY : 2;
+        unsigned int     DUMMY_CRAYRB_SURFACE_TILING : 1;
+        unsigned int     DUMMY_CRAYRB_SURFACE_FORMAT : 6;
+        unsigned int     DUMMY_CRAYRB_SURFACE_NUMBER : 3;
+        unsigned int       DUMMY_CRAYRB_COLOR_FORMAT : 6;
+        unsigned int              DUMMY_CRAYRB_ARRAY : 2;
+        unsigned int        DUMMY_CRAYRB_DEPTH_ARRAY : 2;
+        unsigned int       DUMMY_CRAYRB_SURFACE_SWAP : 1;
+        unsigned int       DUMMY_CRAYRB_DEPTH_FORMAT : 6;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+    union BC_DUMMY_CRAYRB_MOREENUMS {
+    struct {
+#if     defined(qLittleEndian)
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+        unsigned int                                 : 30;
+#else       /* !defined(qLittleEndian) */
+        unsigned int                                 : 30;
+        unsigned int        DUMMY_CRAYRB_COLORARRAYX : 2;
+#endif      /* defined(qLittleEndian) */
+    } bitfields, bits;
+    unsigned int    u32All;
+    signed int  i32All;
+    float   f32All;
+    };
+
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h
new file mode 100644
index 00000000000..69677996b13
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h
@@ -0,0 +1,4184 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_SHIFT_HEADER)
+#define _yamato_SHIFT_HEADER
+
+// PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT          0x00000000
+
+// PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT            0x00000000
+
+// PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT          0x00000000
+
+// PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT           0x00000000
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT          0x00000001
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT           0x00000002
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT          0x00000003
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT           0x00000004
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT          0x00000005
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                  0x00000008
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                   0x00000009
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                  0x0000000a
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT             0x0000000b
+
+// PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT               0x00000010
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT     0x00000012
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT          0x00000013
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT        0x00000014
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                0x00000015
+#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT              0x00000016
+#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT               0x00000017
+#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT               0x00000018
+
+// PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT       0x00000000
+
+// PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT         0x00000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT                   0x0000001c
+#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT                   0x0000001d
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT                   0x0000001e
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT                   0x0000001f
+
+// PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                  0x00000000
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                  0x00000001
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                  0x00000003
+
+// PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT                    0x00000000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT                     0x00000010
+
+// PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                0x00000000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                0x00000010
+
+// PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT                      0x00000000
+
+// PA_SU_FACE_DATA
+#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT                  0x00000005
+
+// PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT              0x00000000
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT               0x00000001
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT                    0x00000002
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT               0x00000003
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT    0x00000005
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT     0x00000008
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
+#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT             0x0000000f
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
+#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT     0x00000012
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT      0x00000013
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT          0x00000014
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT       0x00000015
+#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT       0x00000017
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT    0x00000019
+#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a
+#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS__SHIFT        0x0000001c
+#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT      0x0000001d
+#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT        0x0000001e
+#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT       0x0000001f
+
+// PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT        0x00000000
+
+// PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT      0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT         0x00000000
+
+// PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT       0x00000000
+
+// PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SU_PERFCOUNTER0_LOW
+#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER1_LOW
+#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER2_LOW
+#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SU_PERFCOUNTER3_LOW
+#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT        0x00000000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT        0x00000010
+
+// PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT           0x00000000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT            0x0000000d
+
+// PA_SC_AA_MASK
+#define PA_SC_AA_MASK__AA_MASK__SHIFT                      0x00000000
+
+// PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT            0x00000000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT            0x00000010
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT       0x0000001c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT         0x0000001d
+
+// PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT                  0x00000000
+#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT              0x00000008
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT          0x00000009
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                 0x0000000a
+
+// PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
+
+// PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT               0x00000010
+
+// PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT               0x00000000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT               0x00000010
+
+// PA_SC_VIZ_QUERY
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT              0x00000000
+#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT               0x00000001
+#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT      0x00000007
+
+// PA_SC_VIZ_QUERY_STATUS
+#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT         0x00000000
+
+// PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT       0x00000000
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT     0x00000008
+
+// PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT         0x00000000
+
+// PA_SC_PERFCOUNTER0_LOW
+#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT          0x00000000
+
+// PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT           0x00000000
+
+// PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                  0x0000001f
+
+// PA_SC_CNTL_STATUS
+#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT                  0x0000001f
+
+// PA_SU_DEBUG_CNTL
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SU_DEBUG_DATA
+#define PA_SU_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// CLIPPER_DEBUG_REG00
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT  0x00000000
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT   0x00000001
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT  0x00000002
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT   0x00000003
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT     0x0000000d
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT            0x00000014
+
+// CLIPPER_DEBUG_REG01
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT    0x00000013
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT            0x00000018
+
+// CLIPPER_DEBUG_REG02
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT           0x00000018
+#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
+
+// CLIPPER_DEBUG_REG03
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT           0x00000008
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014
+#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT           0x0000001a
+
+// CLIPPER_DEBUG_REG04
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT           0x00000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007
+#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT           0x00000008
+
+// CLIPPER_DEBUG_REG05
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT           0x00000001
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT           0x00000016
+#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018
+#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT           0x0000001c
+
+// CLIPPER_DEBUG_REG09
+#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT   0x00000000
+#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT           0x00000006
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT           0x0000000c
+#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e
+#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT           0x00000012
+#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT        0x00000014
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019
+#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT   0x0000001c
+#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT    0x0000001d
+#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e
+
+// CLIPPER_DEBUG_REG10
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT           0x00000004
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT           0x0000000a
+#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT           0x00000010
+#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT           0x00000013
+#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016
+#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017
+#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a
+
+// CLIPPER_DEBUG_REG11
+#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT            0x00000004
+
+// CLIPPER_DEBUG_REG12
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT           0x00000002
+#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f
+#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT           0x00000016
+
+// CLIPPER_DEBUG_REG13
+#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT      0x00000000
+#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT     0x00000004
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT           0x0000000b
+#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT    0x0000000e
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
+#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
+#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT      0x00000014
+#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT           0x0000001b
+
+// SXIFCCG_DEBUG_REG0
+#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT           0x00000000
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT        0x00000004
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT           0x0000000a
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT            0x0000000d
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010
+#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT            0x00000011
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT  0x00000013
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT       0x00000017
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT   0x0000001e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT   0x0000001f
+
+// SXIFCCG_DEBUG_REG1
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT            0x00000000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT          0x00000002
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT     0x00000004
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT            0x00000007
+#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT      0x0000000b
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT         0x0000000c
+#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT                 0x00000014
+#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT            0x00000015
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT            0x00000017
+#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT        0x00000019
+
+// SXIFCCG_DEBUG_REG2
+#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT                 0x00000000
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT            0x00000001
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT                  0x00000002
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT         0x00000003
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT        0x00000009
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT            0x00000012
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT            0x00000016
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT   0x0000001b
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT    0x0000001c
+#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d
+
+// SXIFCCG_DEBUG_REG3
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT            0x00000004
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT     0x00000005
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT            0x00000008
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT           0x0000000c
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT       0x0000000e
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT        0x0000000f
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT            0x00000010
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT  0x00000012
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT   0x00000013
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT  0x00000015
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT            0x00000016
+
+// SETUP_DEBUG_REG0
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT             0x00000000
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT               0x00000005
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT                 0x0000000b
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT               0x0000000c
+#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT         0x0000000d
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT               0x0000000e
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT                0x0000000f
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT              0x00000010
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT                 0x00000011
+
+// SETUP_DEBUG_REG1
+#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG2
+#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG3
+#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT        0x00000000
+#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT        0x0000000e
+
+// SETUP_DEBUG_REG4
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT           0x0000000b
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT          0x0000000c
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT             0x0000000d
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT             0x00000010
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT        0x00000011
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT              0x00000014
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT        0x00000015
+#define SETUP_DEBUG_REG4__type_gated__SHIFT                0x00000017
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT                0x0000001a
+#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT          0x0000001b
+#define SETUP_DEBUG_REG4__event_gated__SHIFT               0x0000001c
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT                 0x0000001d
+
+// SETUP_DEBUG_REG5
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT     0x00000000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT     0x0000000b
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT       0x00000016
+#define SETUP_DEBUG_REG5__event_id_gated__SHIFT            0x00000018
+
+// PA_SC_DEBUG_CNTL
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT             0x00000000
+
+// PA_SC_DEBUG_DATA
+#define PA_SC_DEBUG_DATA__DATA__SHIFT                      0x00000000
+
+// SC_DEBUG_0
+#define SC_DEBUG_0__pa_freeze_b1__SHIFT                    0x00000000
+#define SC_DEBUG_0__pa_sc_valid__SHIFT                     0x00000001
+#define SC_DEBUG_0__pa_sc_phase__SHIFT                     0x00000002
+#define SC_DEBUG_0__cntx_cnt__SHIFT                        0x00000005
+#define SC_DEBUG_0__decr_cntx_cnt__SHIFT                   0x0000000c
+#define SC_DEBUG_0__incr_cntx_cnt__SHIFT                   0x0000000d
+#define SC_DEBUG_0__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_1
+#define SC_DEBUG_1__em_state__SHIFT                        0x00000000
+#define SC_DEBUG_1__em1_data_ready__SHIFT                  0x00000003
+#define SC_DEBUG_1__em2_data_ready__SHIFT                  0x00000004
+#define SC_DEBUG_1__move_em1_to_em2__SHIFT                 0x00000005
+#define SC_DEBUG_1__ef_data_ready__SHIFT                   0x00000006
+#define SC_DEBUG_1__ef_state__SHIFT                        0x00000007
+#define SC_DEBUG_1__pipe_valid__SHIFT                      0x00000009
+#define SC_DEBUG_1__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_2
+#define SC_DEBUG_2__rc_rtr_dly__SHIFT                      0x00000000
+#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT            0x00000001
+#define SC_DEBUG_2__pipe_freeze_b__SHIFT                   0x00000003
+#define SC_DEBUG_2__prim_rts__SHIFT                        0x00000004
+#define SC_DEBUG_2__next_prim_rts_dly__SHIFT               0x00000005
+#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT               0x00000006
+#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT               0x00000007
+#define SC_DEBUG_2__stage0_rts__SHIFT                      0x00000008
+#define SC_DEBUG_2__phase_rts_dly__SHIFT                   0x00000009
+#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT              0x0000000f
+#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT              0x00000010
+#define SC_DEBUG_2__event_id_s1__SHIFT                     0x00000011
+#define SC_DEBUG_2__event_s1__SHIFT                        0x00000016
+#define SC_DEBUG_2__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_3
+#define SC_DEBUG_3__x_curr_s1__SHIFT                       0x00000000
+#define SC_DEBUG_3__y_curr_s1__SHIFT                       0x0000000b
+#define SC_DEBUG_3__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_4
+#define SC_DEBUG_4__y_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_4__y_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_4__y_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_4__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_5
+#define SC_DEBUG_5__x_end_s1__SHIFT                        0x00000000
+#define SC_DEBUG_5__x_start_s1__SHIFT                      0x0000000e
+#define SC_DEBUG_5__x_dir_s1__SHIFT                        0x0000001c
+#define SC_DEBUG_5__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_6
+#define SC_DEBUG_6__z_ff_empty__SHIFT                      0x00000000
+#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT                 0x00000001
+#define SC_DEBUG_6__xy_ff_empty__SHIFT                     0x00000002
+#define SC_DEBUG_6__event_flag__SHIFT                      0x00000003
+#define SC_DEBUG_6__z_mask_needed__SHIFT                   0x00000004
+#define SC_DEBUG_6__state__SHIFT                           0x00000005
+#define SC_DEBUG_6__state_delayed__SHIFT                   0x00000008
+#define SC_DEBUG_6__data_valid__SHIFT                      0x0000000b
+#define SC_DEBUG_6__data_valid_d__SHIFT                    0x0000000c
+#define SC_DEBUG_6__tilex_delayed__SHIFT                   0x0000000d
+#define SC_DEBUG_6__tiley_delayed__SHIFT                   0x00000016
+#define SC_DEBUG_6__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_7
+#define SC_DEBUG_7__event_flag__SHIFT                      0x00000000
+#define SC_DEBUG_7__deallocate__SHIFT                      0x00000001
+#define SC_DEBUG_7__fposition__SHIFT                       0x00000004
+#define SC_DEBUG_7__sr_prim_we__SHIFT                      0x00000005
+#define SC_DEBUG_7__last_tile__SHIFT                       0x00000006
+#define SC_DEBUG_7__tile_ff_we__SHIFT                      0x00000007
+#define SC_DEBUG_7__qs_data_valid__SHIFT                   0x00000008
+#define SC_DEBUG_7__qs_q0_y__SHIFT                         0x00000009
+#define SC_DEBUG_7__qs_q0_x__SHIFT                         0x0000000b
+#define SC_DEBUG_7__qs_q0_valid__SHIFT                     0x0000000d
+#define SC_DEBUG_7__prim_ff_we__SHIFT                      0x0000000e
+#define SC_DEBUG_7__tile_ff_re__SHIFT                      0x0000000f
+#define SC_DEBUG_7__fw_prim_data_valid__SHIFT              0x00000010
+#define SC_DEBUG_7__last_quad_of_tile__SHIFT               0x00000011
+#define SC_DEBUG_7__first_quad_of_tile__SHIFT              0x00000012
+#define SC_DEBUG_7__first_quad_of_prim__SHIFT              0x00000013
+#define SC_DEBUG_7__new_prim__SHIFT                        0x00000014
+#define SC_DEBUG_7__load_new_tile_data__SHIFT              0x00000015
+#define SC_DEBUG_7__state__SHIFT                           0x00000016
+#define SC_DEBUG_7__fifos_ready__SHIFT                     0x00000018
+#define SC_DEBUG_7__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_8
+#define SC_DEBUG_8__sample_last__SHIFT                     0x00000000
+#define SC_DEBUG_8__sample_mask__SHIFT                     0x00000001
+#define SC_DEBUG_8__sample_y__SHIFT                        0x00000005
+#define SC_DEBUG_8__sample_x__SHIFT                        0x00000007
+#define SC_DEBUG_8__sample_send__SHIFT                     0x00000009
+#define SC_DEBUG_8__next_cycle__SHIFT                      0x0000000a
+#define SC_DEBUG_8__ez_sample_ff_full__SHIFT               0x0000000c
+#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT                  0x0000000d
+#define SC_DEBUG_8__num_samples__SHIFT                     0x0000000e
+#define SC_DEBUG_8__last_quad_of_tile__SHIFT               0x00000010
+#define SC_DEBUG_8__last_quad_of_prim__SHIFT               0x00000011
+#define SC_DEBUG_8__first_quad_of_prim__SHIFT              0x00000012
+#define SC_DEBUG_8__sample_we__SHIFT                       0x00000013
+#define SC_DEBUG_8__fposition__SHIFT                       0x00000014
+#define SC_DEBUG_8__event_id__SHIFT                        0x00000015
+#define SC_DEBUG_8__event_flag__SHIFT                      0x0000001a
+#define SC_DEBUG_8__fw_prim_data_valid__SHIFT              0x0000001b
+#define SC_DEBUG_8__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_9
+#define SC_DEBUG_9__rb_sc_send__SHIFT                      0x00000000
+#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT                   0x00000001
+#define SC_DEBUG_9__fifo_data_ready__SHIFT                 0x00000005
+#define SC_DEBUG_9__early_z_enable__SHIFT                  0x00000006
+#define SC_DEBUG_9__mask_state__SHIFT                      0x00000007
+#define SC_DEBUG_9__next_ez_mask__SHIFT                    0x00000009
+#define SC_DEBUG_9__mask_ready__SHIFT                      0x00000019
+#define SC_DEBUG_9__drop_sample__SHIFT                     0x0000001a
+#define SC_DEBUG_9__fetch_new_sample_data__SHIFT           0x0000001b
+#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT        0x0000001c
+#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT       0x0000001d
+#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT         0x0000001e
+#define SC_DEBUG_9__trigger__SHIFT                         0x0000001f
+
+// SC_DEBUG_10
+#define SC_DEBUG_10__combined_sample_mask__SHIFT           0x00000000
+#define SC_DEBUG_10__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_11
+#define SC_DEBUG_11__ez_sample_data_ready__SHIFT           0x00000000
+#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT      0x00000001
+#define SC_DEBUG_11__ez_prim_data_ready__SHIFT             0x00000002
+#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT        0x00000003
+#define SC_DEBUG_11__iterator_input_fz__SHIFT              0x00000004
+#define SC_DEBUG_11__packer_send_quads__SHIFT              0x00000005
+#define SC_DEBUG_11__packer_send_cmd__SHIFT                0x00000006
+#define SC_DEBUG_11__packer_send_event__SHIFT              0x00000007
+#define SC_DEBUG_11__next_state__SHIFT                     0x00000008
+#define SC_DEBUG_11__state__SHIFT                          0x0000000b
+#define SC_DEBUG_11__stall__SHIFT                          0x0000000e
+#define SC_DEBUG_11__trigger__SHIFT                        0x0000001f
+
+// SC_DEBUG_12
+#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT          0x00000000
+#define SC_DEBUG_12__event_id__SHIFT                       0x00000001
+#define SC_DEBUG_12__event_flag__SHIFT                     0x00000006
+#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT        0x00000007
+#define SC_DEBUG_12__itercmdfifo_full__SHIFT               0x00000008
+#define SC_DEBUG_12__itercmdfifo_empty__SHIFT              0x00000009
+#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT        0x0000000a
+#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT           0x0000000b
+#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT          0x0000000c
+#define SC_DEBUG_12__iter_qdhit0__SHIFT                    0x0000000d
+#define SC_DEBUG_12__bc_use_centers_reg__SHIFT             0x0000000e
+#define SC_DEBUG_12__bc_output_xy_reg__SHIFT               0x0000000f
+#define SC_DEBUG_12__iter_phase_out__SHIFT                 0x00000010
+#define SC_DEBUG_12__iter_phase_reg__SHIFT                 0x00000012
+#define SC_DEBUG_12__iterator_SP_valid__SHIFT              0x00000014
+#define SC_DEBUG_12__eopv_reg__SHIFT                       0x00000015
+#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT                0x00000016
+#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT            0x00000017
+#define SC_DEBUG_12__trigger__SHIFT                        0x0000001f
+
+// GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                0x00000000
+
+// VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT               0x00000000
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT           0x00000006
+#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT    0x00000008
+#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT              0x0000000b
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                 0x0000000c
+#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT             0x0000000d
+#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT   0x0000000e
+#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT         0x0000000f
+#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT             0x00000010
+
+// VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT             0x00000000
+
+// VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT                     0x00000000
+
+// VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_DMA_SIZE__SWAP_MODE__SHIFT                     0x0000001e
+
+// VGT_BIN_BASE
+#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT                 0x00000000
+
+// VGT_BIN_SIZE
+#define VGT_BIN_SIZE__NUM_WORDS__SHIFT                     0x00000000
+#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT                0x0000001e
+#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT                0x0000001f
+
+// VGT_CURRENT_BIN_ID_MIN
+#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_CURRENT_BIN_ID_MAX
+#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT              0x00000000
+#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT                 0x00000003
+#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT          0x00000006
+
+// VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                  0x00000000
+
+// VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                  0x00000000
+
+// VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                0x00000000
+
+// VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
+
+// VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT          0x00000000
+
+// VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT    0x00000000
+
+// VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT                           0x00000000
+
+// VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT          0x00000000
+
+// VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT           0x00000000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT           0x00000010
+
+// VGT_DEBUG_CNTL
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT              0x00000000
+
+// VGT_DEBUG_DATA
+#define VGT_DEBUG_DATA__DATA__SHIFT                        0x00000000
+
+// VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                   0x00000000
+#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT               0x00000001
+#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT           0x00000002
+#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT               0x00000003
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                0x00000004
+#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT               0x00000005
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                0x00000006
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT               0x00000007
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT          0x00000008
+
+// VGT_DEBUG_REG0
+#define VGT_DEBUG_REG0__te_grp_busy__SHIFT                 0x00000000
+#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT                 0x00000001
+#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT                 0x00000002
+#define VGT_DEBUG_REG0__dma_request_busy__SHIFT            0x00000003
+#define VGT_DEBUG_REG0__out_busy__SHIFT                    0x00000004
+#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT            0x00000005
+#define VGT_DEBUG_REG0__grp_busy__SHIFT                    0x00000006
+#define VGT_DEBUG_REG0__dma_busy__SHIFT                    0x00000007
+#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT       0x00000008
+#define VGT_DEBUG_REG0__rbiu_busy__SHIFT                   0x00000009
+#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT    0x0000000a
+#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT             0x0000000b
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT           0x0000000c
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT                    0x0000000d
+#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT     0x0000000e
+#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT        0x0000000f
+#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT               0x00000010
+
+// VGT_DEBUG_REG1
+#define VGT_DEBUG_REG1__out_te_data_read__SHIFT            0x00000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT           0x00000001
+#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT            0x00000002
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT           0x00000003
+#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT            0x00000004
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT           0x00000005
+#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT            0x00000006
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT           0x00000007
+#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT            0x00000008
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT           0x00000009
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT                 0x0000000a
+#define VGT_DEBUG_REG1__grp_te_valid__SHIFT                0x0000000b
+#define VGT_DEBUG_REG1__pt_grp_read__SHIFT                 0x0000000c
+#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT                0x0000000d
+#define VGT_DEBUG_REG1__vr_grp_read__SHIFT                 0x0000000e
+#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT                0x0000000f
+#define VGT_DEBUG_REG1__grp_dma_read__SHIFT                0x00000010
+#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT               0x00000011
+#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT            0x00000012
+#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT           0x00000013
+#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT                  0x00000014
+#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT                 0x00000015
+#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT           0x00000016
+#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT          0x00000017
+#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT           0x00000018
+#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT          0x00000019
+#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT           0x0000001a
+#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT          0x0000001b
+#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT                  0x0000001c
+#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT                 0x0000001d
+#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT              0x0000001e
+
+// VGT_DEBUG_REG3
+#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT                  0x00000000
+#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT            0x00000001
+
+// VGT_DEBUG_REG6
+#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT        0x00000000
+#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT           0x00000005
+#define VGT_DEBUG_REG6__input_data_valid__SHIFT            0x0000000a
+#define VGT_DEBUG_REG6__input_data_xfer__SHIFT             0x0000000b
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT      0x0000000c
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT      0x0000000d
+#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT  0x0000000e
+#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT      0x0000000f
+#define VGT_DEBUG_REG6__shifter_first_load__SHIFT          0x00000010
+#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT       0x00000013
+#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT             0x00000014
+#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT         0x00000015
+#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT        0x00000017
+#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT         0x00000018
+#define VGT_DEBUG_REG6__extract_vector__SHIFT              0x00000019
+#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT              0x0000001a
+#define VGT_DEBUG_REG6__destination_rtr__SHIFT             0x0000001b
+#define VGT_DEBUG_REG6__grp_trigger__SHIFT                 0x0000001c
+
+// VGT_DEBUG_REG7
+#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT          0x00000000
+#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT     0x00000010
+#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT        0x00000014
+#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG7__current_source_sel__SHIFT          0x0000001e
+
+// VGT_DEBUG_REG8
+#define VGT_DEBUG_REG8__current_source_sel__SHIFT          0x00000000
+#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT            0x00000002
+#define VGT_DEBUG_REG8__input_data_cnt__SHIFT              0x00000007
+#define VGT_DEBUG_REG8__input_data_lsw__SHIFT              0x0000000c
+#define VGT_DEBUG_REG8__input_data_msw__SHIFT              0x00000011
+#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG9
+#define VGT_DEBUG_REG9__next_stride_q__SHIFT               0x00000000
+#define VGT_DEBUG_REG9__next_stride_d__SHIFT               0x00000005
+#define VGT_DEBUG_REG9__current_shift_q__SHIFT             0x0000000a
+#define VGT_DEBUG_REG9__current_shift_d__SHIFT             0x0000000f
+#define VGT_DEBUG_REG9__current_stride_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG9__current_stride_d__SHIFT            0x00000019
+#define VGT_DEBUG_REG9__grp_trigger__SHIFT                 0x0000001e
+
+// VGT_DEBUG_REG10
+#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000
+#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001
+#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002
+#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003
+#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT             0x00000004
+#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT        0x00000005
+#define VGT_DEBUG_REG10__bin_valid__SHIFT                  0x00000006
+#define VGT_DEBUG_REG10__read_block__SHIFT                 0x00000007
+#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT     0x00000008
+#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT          0x00000009
+#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG10__selected_data__SHIFT              0x0000000b
+#define VGT_DEBUG_REG10__mask_input_data__SHIFT            0x00000013
+#define VGT_DEBUG_REG10__gap_q__SHIFT                      0x0000001b
+#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT          0x0000001c
+#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT          0x0000001d
+#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT          0x0000001e
+#define VGT_DEBUG_REG10__grp_trigger__SHIFT                0x0000001f
+
+// VGT_DEBUG_REG12
+#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT       0x00000000
+#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT          0x00000005
+#define VGT_DEBUG_REG12__input_data_valid__SHIFT           0x0000000a
+#define VGT_DEBUG_REG12__input_data_xfer__SHIFT            0x0000000b
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT     0x0000000c
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT     0x0000000d
+#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e
+#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT     0x0000000f
+#define VGT_DEBUG_REG12__shifter_first_load__SHIFT         0x00000010
+#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT             0x00000011
+#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012
+#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT      0x00000013
+#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT            0x00000014
+#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT        0x00000015
+#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016
+#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT       0x00000017
+#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT        0x00000018
+#define VGT_DEBUG_REG12__extract_vector__SHIFT             0x00000019
+#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT             0x0000001a
+#define VGT_DEBUG_REG12__destination_rtr__SHIFT            0x0000001b
+#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT               0x0000001c
+
+// VGT_DEBUG_REG13
+#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT         0x00000000
+#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT    0x00000010
+#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT       0x00000014
+#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT             0x00000018
+#define VGT_DEBUG_REG13__current_source_sel__SHIFT         0x0000001e
+
+// VGT_DEBUG_REG14
+#define VGT_DEBUG_REG14__current_source_sel__SHIFT         0x00000000
+#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT           0x00000002
+#define VGT_DEBUG_REG14__input_data_cnt__SHIFT             0x00000007
+#define VGT_DEBUG_REG14__input_data_lsw__SHIFT             0x0000000c
+#define VGT_DEBUG_REG14__input_data_msw__SHIFT             0x00000011
+#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016
+#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b
+
+// VGT_DEBUG_REG15
+#define VGT_DEBUG_REG15__next_stride_q__SHIFT              0x00000000
+#define VGT_DEBUG_REG15__next_stride_d__SHIFT              0x00000005
+#define VGT_DEBUG_REG15__current_shift_q__SHIFT            0x0000000a
+#define VGT_DEBUG_REG15__current_shift_d__SHIFT            0x0000000f
+#define VGT_DEBUG_REG15__current_stride_q__SHIFT           0x00000014
+#define VGT_DEBUG_REG15__current_stride_d__SHIFT           0x00000019
+#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT               0x0000001e
+
+// VGT_DEBUG_REG16
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT  0x00000000
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001
+#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT   0x00000002
+#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT    0x00000003
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT   0x00000004
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT  0x00000005
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT   0x00000006
+#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT     0x00000007
+#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT         0x00000008
+#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT         0x00000009
+#define VGT_DEBUG_REG16__rst_last_bit__SHIFT               0x0000000a
+#define VGT_DEBUG_REG16__current_state_q__SHIFT            0x0000000b
+#define VGT_DEBUG_REG16__old_state_q__SHIFT                0x0000000c
+#define VGT_DEBUG_REG16__old_state_en__SHIFT               0x0000000d
+#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT            0x0000000e
+#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT             0x0000000f
+#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT           0x00000010
+#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT           0x00000011
+#define VGT_DEBUG_REG16__load_empty_reg__SHIFT             0x00000012
+#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT   0x00000013
+#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b
+#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d
+#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT   0x0000001e
+#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG17
+#define VGT_DEBUG_REG17__save_read_q__SHIFT                0x00000000
+#define VGT_DEBUG_REG17__extend_read_q__SHIFT              0x00000001
+#define VGT_DEBUG_REG17__grp_indx_size__SHIFT              0x00000002
+#define VGT_DEBUG_REG17__cull_prim_true__SHIFT             0x00000004
+#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT               0x00000005
+#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT               0x00000006
+#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT          0x00000007
+#define VGT_DEBUG_REG17__check_second_reg__SHIFT           0x00000008
+#define VGT_DEBUG_REG17__check_first_reg__SHIFT            0x00000009
+#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a
+#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT    0x0000000b
+#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT    0x0000000c
+#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT     0x0000000d
+#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT     0x0000000e
+#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT            0x0000000f
+#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT            0x00000010
+#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT              0x00000011
+#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT              0x00000018
+#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT               0x0000001f
+
+// VGT_DEBUG_REG18
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT    0x00000000
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT    0x00000006
+#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c
+#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d
+#define VGT_DEBUG_REG18__dma_mem_full__SHIFT               0x0000000f
+#define VGT_DEBUG_REG18__dma_ram_re__SHIFT                 0x00000010
+#define VGT_DEBUG_REG18__dma_ram_we__SHIFT                 0x00000011
+#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT              0x00000012
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT       0x00000013
+#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT       0x00000014
+#define VGT_DEBUG_REG18__bin_mem_full__SHIFT               0x00000015
+#define VGT_DEBUG_REG18__bin_ram_we__SHIFT                 0x00000016
+#define VGT_DEBUG_REG18__bin_ram_re__SHIFT                 0x00000017
+#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT              0x00000018
+#define VGT_DEBUG_REG18__start_bin_req__SHIFT              0x00000019
+#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT        0x0000001a
+#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT               0x0000001b
+#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT         0x0000001c
+#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT         0x0000001d
+#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e
+#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f
+
+// VGT_DEBUG_REG20
+#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT       0x00000000
+#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT       0x00000001
+#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT          0x00000002
+#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT          0x00000003
+#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT        0x00000004
+#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT          0x00000005
+#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT             0x00000006
+#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT             0x00000007
+#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT           0x00000008
+#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT          0x00000009
+#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT             0x0000000a
+#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT             0x0000000b
+#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT           0x0000000c
+#define VGT_DEBUG_REG20__hold_prim__SHIFT                  0x0000000d
+#define VGT_DEBUG_REG20__sent_cnt__SHIFT                   0x0000000e
+#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT        0x00000012
+#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT       0x00000013
+#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT       0x00000014
+#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT   0x00000015
+#define VGT_DEBUG_REG20__out_trigger__SHIFT                0x0000001a
+
+// VGT_DEBUG_REG21
+#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT  0x00000000
+#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001
+#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT            0x00000004
+#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT    0x00000007
+#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT          0x0000000a
+#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT    0x0000000e
+#define VGT_DEBUG_REG21__new_packet_q__SHIFT               0x00000012
+#define VGT_DEBUG_REG21__new_allocate_q__SHIFT             0x00000013
+#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT    0x00000014
+#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT       0x00000016
+#define VGT_DEBUG_REG21__insert_null_prim__SHIFT           0x00000017
+#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT      0x00000018
+#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT      0x00000019
+#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT       0x0000001a
+#define VGT_DEBUG_REG21__out_trigger__SHIFT                0x0000001f
+
+// VGT_CRC_SQ_DATA
+#define VGT_CRC_SQ_DATA__CRC__SHIFT                        0x00000000
+
+// VGT_CRC_SQ_CTRL
+#define VGT_CRC_SQ_CTRL__CRC__SHIFT                        0x00000000
+
+// VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT           0x00000000
+
+// VGT_PERFCOUNTER0_LOW
+#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER1_LOW
+#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER2_LOW
+#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER3_LOW
+#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT            0x00000000
+
+// VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT             0x00000000
+
+// VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT             0x00000000
+
+// TC_CNTL_STATUS
+#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT               0x00000000
+#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT              0x00000012
+#define TC_CNTL_STATUS__TC_BUSY__SHIFT                     0x0000001f
+
+// TCR_CHICKEN
+#define TCR_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCF_CHICKEN
+#define TCF_CHICKEN__SPARE__SHIFT                          0x00000000
+
+// TCM_CHICKEN
+#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000
+#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT               0x00000008
+#define TCM_CHICKEN__SPARE__SHIFT                          0x00000009
+
+// TCR_PERFCOUNTER0_SELECT
+#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER1_SELECT
+#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCR_PERFCOUNTER0_HI
+#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER1_HI
+#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCR_PERFCOUNTER0_LOW
+#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCR_PERFCOUNTER1_LOW
+#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP_TC_CLKGATE_CNTL
+#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT          0x00000000
+#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT          0x00000003
+
+// TPC_CNTL_STATUS
+#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT             0x00000000
+#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT           0x00000001
+#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT        0x00000002
+#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT        0x00000003
+#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT       0x00000004
+#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT         0x00000005
+#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT            0x00000006
+#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT      0x00000008
+#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT        0x00000009
+#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT           0x0000000a
+#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT           0x0000000c
+#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT        0x0000000d
+#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT          0x0000000e
+#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT             0x0000000f
+#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT                  0x00000010
+#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT            0x00000011
+#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT                  0x00000013
+#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT                  0x00000014
+#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT               0x00000015
+#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT             0x00000016
+#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT                  0x00000017
+#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT                  0x00000018
+#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT               0x00000019
+#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT                  0x0000001b
+#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT                  0x0000001c
+#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT          0x0000001d
+#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT                  0x0000001e
+#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT                   0x0000001f
+
+// TPC_DEBUG0
+#define TPC_DEBUG0__LOD_CNTL__SHIFT                        0x00000000
+#define TPC_DEBUG0__IC_CTR__SHIFT                          0x00000002
+#define TPC_DEBUG0__WALKER_CNTL__SHIFT                     0x00000004
+#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT                    0x00000008
+#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT             0x0000000c
+#define TPC_DEBUG0__WALKER_STATE__SHIFT                    0x00000010
+#define TPC_DEBUG0__ALIGNER_STATE__SHIFT                   0x0000001a
+#define TPC_DEBUG0__REG_CLK_EN__SHIFT                      0x0000001d
+#define TPC_DEBUG0__TPC_CLK_EN__SHIFT                      0x0000001e
+#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT                    0x0000001f
+
+// TPC_DEBUG1
+#define TPC_DEBUG1__UNUSED__SHIFT                          0x00000000
+
+// TPC_CHICKEN
+#define TPC_CHICKEN__BLEND_PRECISION__SHIFT                0x00000000
+#define TPC_CHICKEN__SPARE__SHIFT                          0x00000001
+
+// TP0_CNTL_STATUS
+#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT              0x00000000
+#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT                0x00000001
+#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT           0x00000002
+#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT               0x00000003
+#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT         0x00000004
+#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT            0x00000005
+#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT            0x00000006
+#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT            0x00000007
+#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT              0x00000008
+#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT           0x00000009
+#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT                 0x0000000a
+#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT            0x0000000b
+#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT              0x0000000c
+#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT           0x0000000d
+#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT             0x0000000e
+#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT                  0x00000010
+#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT                  0x00000011
+#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT                  0x00000012
+#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT                  0x00000013
+#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT                  0x00000014
+#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT               0x00000015
+#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT                  0x00000016
+#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT               0x00000017
+#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT                  0x00000018
+#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT               0x00000019
+#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT                  0x0000001a
+#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT               0x0000001b
+#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT                  0x0000001c
+#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT             0x0000001d
+#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT                  0x0000001e
+#define TP0_CNTL_STATUS__TP_BUSY__SHIFT                    0x0000001f
+
+// TP0_DEBUG
+#define TP0_DEBUG__Q_LOD_CNTL__SHIFT                       0x00000000
+#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT                   0x00000003
+#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT             0x00000004
+#define TP0_DEBUG__REG_CLK_EN__SHIFT                       0x00000015
+#define TP0_DEBUG__PERF_CLK_EN__SHIFT                      0x00000016
+#define TP0_DEBUG__TP_CLK_EN__SHIFT                        0x00000017
+#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT                    0x00000018
+#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT                   0x0000001c
+
+// TP0_CHICKEN
+#define TP0_CHICKEN__TT_MODE__SHIFT                        0x00000000
+#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT            0x00000001
+#define TP0_CHICKEN__SPARE__SHIFT                          0x00000002
+
+// TP0_PERFCOUNTER0_SELECT
+#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER0_HI
+#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER0_LOW
+#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TP0_PERFCOUNTER1_SELECT
+#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TP0_PERFCOUNTER1_HI
+#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TP0_PERFCOUNTER1_LOW
+#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER0_SELECT
+#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER1_SELECT
+#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCM_PERFCOUNTER0_HI
+#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER1_HI
+#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCM_PERFCOUNTER0_LOW
+#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCM_PERFCOUNTER1_LOW
+#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER0_SELECT
+#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER1_SELECT
+#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER2_SELECT
+#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER3_SELECT
+#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER4_SELECT
+#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER5_SELECT
+#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER6_SELECT
+#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER7_SELECT
+#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER8_SELECT
+#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER9_SELECT
+#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER10_SELECT
+#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER11_SELECT
+#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
+
+// TCF_PERFCOUNTER0_HI
+#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER1_HI
+#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER2_HI
+#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER3_HI
+#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER4_HI
+#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER5_HI
+#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER6_HI
+#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER7_HI
+#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER8_HI
+#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER9_HI
+#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT         0x00000000
+
+// TCF_PERFCOUNTER10_HI
+#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER11_HI
+#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT        0x00000000
+
+// TCF_PERFCOUNTER0_LOW
+#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER1_LOW
+#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER2_LOW
+#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER3_LOW
+#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER4_LOW
+#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER5_LOW
+#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER6_LOW
+#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER7_LOW
+#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER8_LOW
+#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER9_LOW
+#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT       0x00000000
+
+// TCF_PERFCOUNTER10_LOW
+#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_PERFCOUNTER11_LOW
+#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT      0x00000000
+
+// TCF_DEBUG
+#define TCF_DEBUG__not_MH_TC_rtr__SHIFT                    0x00000006
+#define TCF_DEBUG__TC_MH_send__SHIFT                       0x00000007
+#define TCF_DEBUG__not_FG0_rtr__SHIFT                      0x00000008
+#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT                  0x0000000c
+#define TCF_DEBUG__TCB_ff_stall__SHIFT                     0x0000000d
+#define TCF_DEBUG__TCB_miss_stall__SHIFT                   0x0000000e
+#define TCF_DEBUG__TCA_TCB_stall__SHIFT                    0x0000000f
+#define TCF_DEBUG__PF0_stall__SHIFT                        0x00000010
+#define TCF_DEBUG__TP0_full__SHIFT                         0x00000014
+#define TCF_DEBUG__TPC_full__SHIFT                         0x00000018
+#define TCF_DEBUG__not_TPC_rtr__SHIFT                      0x00000019
+#define TCF_DEBUG__tca_state_rts__SHIFT                    0x0000001a
+#define TCF_DEBUG__tca_rts__SHIFT                          0x0000001b
+
+// TCA_FIFO_DEBUG
+#define TCA_FIFO_DEBUG__tp0_full__SHIFT                    0x00000000
+#define TCA_FIFO_DEBUG__tpc_full__SHIFT                    0x00000004
+#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT               0x00000005
+#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT               0x00000006
+#define TCA_FIFO_DEBUG__FW_full__SHIFT                     0x00000007
+#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT                 0x00000008
+#define TCA_FIFO_DEBUG__FW_rts0__SHIFT                     0x0000000c
+#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT              0x00000010
+#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT                  0x00000011
+
+// TCA_PROBE_DEBUG
+#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT          0x00000000
+
+// TCA_TPC_DEBUG
+#define TCA_TPC_DEBUG__captue_state_rts__SHIFT             0x0000000c
+#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT              0x0000000d
+
+// TCB_CORE_DEBUG
+#define TCB_CORE_DEBUG__access512__SHIFT                   0x00000000
+#define TCB_CORE_DEBUG__tiled__SHIFT                       0x00000001
+#define TCB_CORE_DEBUG__opcode__SHIFT                      0x00000004
+#define TCB_CORE_DEBUG__format__SHIFT                      0x00000008
+#define TCB_CORE_DEBUG__sector_format__SHIFT               0x00000010
+#define TCB_CORE_DEBUG__sector_format512__SHIFT            0x00000018
+
+// TCB_TAG0_DEBUG
+#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG0_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG0_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG1_DEBUG
+#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG1_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG1_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG2_DEBUG
+#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG2_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG2_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_TAG3_DEBUG
+#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT              0x00000000
+#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT            0x0000000c
+#define TCB_TAG3_DEBUG__miss_stall__SHIFT                  0x00000017
+#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT              0x00000018
+#define TCB_TAG3_DEBUG__max_misses__SHIFT                  0x0000001d
+
+// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c
+
+// TCB_FETCH_GEN_WALKER_DEBUG
+#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT   0x00000004
+#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT    0x00000006
+#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT   0x0000000b
+#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT   0x0000000c
+#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT            0x0000000f
+#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010
+
+// TCB_FETCH_GEN_PIPE0_DEBUG
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT      0x00000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT       0x00000002
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT    0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010
+#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015
+#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT             0x00000017
+#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT         0x00000018
+#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT          0x00000019
+#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT         0x0000001a
+#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT          0x0000001c
+#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT          0x0000001e
+
+// TCD_INPUT0_DEBUG
+#define TCD_INPUT0_DEBUG__empty__SHIFT                     0x00000010
+#define TCD_INPUT0_DEBUG__full__SHIFT                      0x00000011
+#define TCD_INPUT0_DEBUG__valid_q1__SHIFT                  0x00000014
+#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT                    0x00000015
+#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT              0x00000017
+#define TCD_INPUT0_DEBUG__ip_send__SHIFT                   0x00000018
+#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT            0x00000019
+#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT                0x0000001a
+
+// TCD_DEGAMMA_DEBUG
+#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT      0x00000000
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT          0x00000002
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT      0x00000003
+#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT           0x00000004
+#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT               0x00000005
+#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT              0x00000006
+
+// TCD_DXTMUX_SCTARB_DEBUG
+#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT             0x00000009
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT         0x0000000a
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT           0x0000000b
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f
+#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT  0x00000014
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b
+#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT   0x0000001c
+#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT      0x0000001d
+
+// TCD_DXTC_ARB_DEBUG
+#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT                0x00000004
+#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT                  0x00000005
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT    0x00000006
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT          0x00000007
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT       0x00000009
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT    0x0000000c
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT       0x00000012
+#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT         0x0000001e
+#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT         0x0000001f
+
+// TCD_STALLS_DEBUG
+#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT   0x0000000a
+#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT   0x0000000b
+#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT         0x00000011
+#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT       0x00000012
+#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT          0x00000013
+#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT          0x0000001f
+
+// TCO_STALLS_DEBUG
+#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT          0x00000005
+#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT           0x00000006
+#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT       0x00000007
+
+// TCO_QUAD0_DEBUG0
+#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT       0x00000000
+#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT       0x00000008
+#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT                 0x00000009
+#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT                 0x0000000a
+#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT      0x0000000b
+#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT                0x0000000c
+#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT                0x0000000d
+#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT           0x00000010
+#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT              0x00000018
+#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT            0x00000019
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT  0x0000001a
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT  0x0000001b
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT  0x0000001c
+#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT  0x0000001d
+#define TCO_QUAD0_DEBUG0__busy__SHIFT                      0x0000001e
+
+// TCO_QUAD0_DEBUG1
+#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT                 0x00000000
+#define TCO_QUAD0_DEBUG1__empty__SHIFT                     0x00000001
+#define TCO_QUAD0_DEBUG1__full__SHIFT                      0x00000002
+#define TCO_QUAD0_DEBUG1__write_enable__SHIFT              0x00000003
+#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT            0x00000004
+#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT             0x0000000b
+#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT           0x00000014
+#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT         0x00000015
+#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT           0x00000016
+#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT        0x00000017
+#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT             0x00000018
+#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT             0x00000019
+#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT                 0x0000001a
+#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT                 0x0000001b
+#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT                0x0000001c
+#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT                0x0000001d
+#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT          0x0000001e
+
+// SQ_GPR_MANAGEMENT
+#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT              0x00000000
+#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT             0x00000004
+#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT             0x0000000c
+
+// SQ_FLOW_CONTROL
+#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT   0x00000000
+#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT                 0x00000004
+#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT                    0x00000008
+#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT                 0x0000000c
+#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT                   0x00000010
+#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT               0x00000011
+#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT          0x00000012
+#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013
+#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT      0x00000015
+#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT     0x00000016
+#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT               0x00000017
+#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT               0x00000018
+#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT           0x00000019
+#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a
+#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT    0x0000001b
+
+// SQ_INST_STORE_MANAGMENT
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT      0x00000000
+#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT      0x00000010
+
+// SQ_RESOURCE_MANAGMENT
+#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000
+#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008
+#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT   0x00000010
+
+// SQ_EO_RT
+#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT                   0x00000000
+#define SQ_EO_RT__EO_TSTATE_RT__SHIFT                      0x00000010
+
+// SQ_DEBUG_MISC
+#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT               0x00000000
+#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT               0x0000000c
+#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT                  0x00000014
+#define SQ_DEBUG_MISC__RESERVED__SHIFT                     0x00000015
+#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT               0x00000017
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT              0x00000019
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT              0x0000001a
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT              0x0000001b
+#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT              0x0000001c
+
+// SQ_ACTIVITY_METER_CNTL
+#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT            0x00000000
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT       0x00000008
+#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT      0x00000010
+#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT               0x00000018
+
+// SQ_ACTIVITY_METER_STATUS
+#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT      0x00000000
+
+// SQ_INPUT_ARB_PRIORITY
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT      0x00000000
+#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT        0x00000003
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT      0x00000004
+#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT        0x00000007
+#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT            0x00000008
+
+// SQ_THREAD_ARB_PRIORITY
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT     0x00000000
+#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT       0x00000003
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT     0x00000004
+#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT       0x00000007
+#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT           0x00000008
+#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT            0x00000012
+#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014
+#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015
+#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016
+
+// SQ_VS_WATCHDOG_TIMER
+#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_PS_WATCHDOG_TIMER
+#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT                0x00000000
+#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT         0x00000001
+
+// SQ_INT_CNTL
+#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT               0x00000000
+#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT               0x00000001
+
+// SQ_INT_STATUS
+#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT          0x00000000
+#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT          0x00000001
+
+// SQ_INT_ACK
+#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT                 0x00000000
+#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT                 0x00000001
+
+// SQ_DEBUG_INPUT_FSM
+#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT               0x00000000
+#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT                0x00000003
+#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT               0x00000004
+#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT                 0x00000008
+#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT                   0x0000000c
+#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT           0x0000000f
+#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT             0x00000014
+
+// SQ_DEBUG_CONST_MGR_FSM
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT           0x00000005
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008
+#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT           0x0000000d
+#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010
+#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016
+#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017
+
+// SQ_DEBUG_TP_FSM
+#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT                      0x00000000
+#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT                  0x00000003
+#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT                      0x00000004
+#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT                      0x00000008
+#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT                  0x0000000b
+#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT                     0x0000000c
+#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT                  0x0000000e
+#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT                      0x00000010
+#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT                  0x00000012
+#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT                     0x00000014
+#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT                  0x00000016
+#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT                     0x00000018
+#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT                  0x0000001a
+#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT                  0x0000001c
+
+// SQ_DEBUG_FSM_ALU_0
+#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_FSM_ALU_1
+#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT                0x00000000
+#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT               0x00000003
+#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT                0x00000004
+#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT                0x00000008
+#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT               0x0000000b
+#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT               0x0000000c
+#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT               0x0000000f
+#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT               0x00000010
+#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT               0x00000013
+#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT               0x00000014
+#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT               0x00000017
+#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT               0x00000018
+#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT               0x0000001b
+#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT              0x0000001c
+
+// SQ_DEBUG_EXP_ALLOC
+#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT           0x00000000
+#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT         0x00000004
+#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT            0x0000000c
+#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT                0x0000000f
+#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT     0x00000010
+
+// SQ_DEBUG_PTR_BUFF
+#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT            0x00000000
+#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT              0x00000001
+#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT          0x00000005
+#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT         0x00000006
+#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT              0x00000009
+#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT               0x0000000e
+#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT        0x0000000f
+#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT                 0x00000010
+#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT             0x00000011
+
+// SQ_DEBUG_GPR_VTX
+#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_GPR_PIX
+#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT              0x00000000
+#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT                  0x00000007
+#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT              0x00000008
+#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT                 0x0000000f
+#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT                   0x00000010
+#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT                 0x00000017
+#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT                  0x00000018
+
+// SQ_DEBUG_TB_STATUS_SEL
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007
+#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c
+#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014
+#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017
+#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT   0x0000001d
+#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f
+
+// SQ_DEBUG_VTX_TB_0
+#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT           0x00000000
+#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT               0x00000004
+#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT               0x00000008
+#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT        0x0000000c
+#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT         0x00000010
+#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT            0x00000014
+#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT                   0x00000015
+
+// SQ_DEBUG_VTX_TB_1
+#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT              0x00000000
+
+// SQ_DEBUG_VTX_TB_STATUS_REG
+#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT   0x00000000
+
+// SQ_DEBUG_VTX_TB_STATE_MEM
+#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT     0x00000000
+
+// SQ_DEBUG_PIX_TB_0
+#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT             0x00000000
+#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT                 0x00000006
+#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT                 0x0000000c
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT        0x00000013
+#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT          0x00000019
+#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT                     0x0000001f
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_0
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_1
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_2
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATUS_REG_3
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000
+
+// SQ_DEBUG_PIX_TB_STATE_MEM
+#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000
+
+// SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SQ_PERFCOUNTER0_LOW
+#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER1_LOW
+#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER2_LOW
+#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_PERFCOUNTER3_LOW
+#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// SX_PERFCOUNTER0_LOW
+#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// SQ_INSTRUCTION_ALU_0
+#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT        0x00000006
+#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT  0x00000007
+#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT        0x0000000e
+#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT           0x0000000f
+#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT        0x00000010
+#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT        0x00000014
+#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT          0x00000018
+#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT          0x00000019
+#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT         0x0000001a
+
+// SQ_INSTRUCTION_ALU_1
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT       0x00000000
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT       0x00000002
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT       0x00000004
+#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT       0x00000006
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT       0x00000008
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT       0x0000000c
+#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT       0x0000000e
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT       0x00000010
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT       0x00000012
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT       0x00000014
+#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT       0x00000016
+#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT         0x00000019
+#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT           0x0000001b
+#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT       0x0000001e
+#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT       0x0000001f
+
+// SQ_INSTRUCTION_ALU_2
+#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT         0x00000000
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT          0x00000006
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT         0x00000007
+#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT         0x00000008
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT          0x0000000e
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT         0x00000010
+#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT          0x00000016
+#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT         0x00000017
+#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT         0x00000018
+#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT             0x0000001d
+#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT             0x0000001e
+#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_0
+#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT          0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT             0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT             0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT       0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT     0x00000013
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT       0x00000014
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT     0x00000015
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT       0x00000016
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT     0x00000017
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT       0x00000018
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT     0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT       0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT     0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT         0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT         0x0000001d
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT         0x0000001e
+#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT         0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_1
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT         0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT         0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT         0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT          0x00000019
+#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT             0x0000001c
+#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT             0x0000001f
+
+// SQ_INSTRUCTION_CF_EXEC_2
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT       0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT     0x00000003
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT       0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT     0x00000005
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT       0x00000006
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT     0x00000007
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT       0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT     0x00000009
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT       0x0000000a
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT     0x0000000b
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT         0x0000000d
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT         0x0000000f
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT         0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT         0x00000011
+#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT         0x00000012
+#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT         0x0000001a
+#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_LOOP_0
+#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT        0x0000000a
+#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT        0x00000015
+
+// SQ_INSTRUCTION_CF_LOOP_1
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT        0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT      0x0000000b
+#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT           0x00000010
+#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT        0x0000001a
+
+// SQ_INSTRUCTION_CF_LOOP_2
+#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT           0x00000000
+#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT          0x00000005
+#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT      0x0000001b
+#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT            0x0000001c
+
+// SQ_INSTRUCTION_CF_JMP_CALL_0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT    0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT    0x0000000d
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT    0x0000000f
+
+// SQ_INSTRUCTION_CF_JMP_CALL_1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT    0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT     0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT     0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT     0x0000000a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT  0x0000000b
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT        0x0000000c
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT       0x00000010
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT    0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT    0x0000001d
+#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT    0x0000001e
+
+// SQ_INSTRUCTION_CF_JMP_CALL_2
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT      0x00000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT     0x00000011
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT     0x00000012
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT  0x0000001b
+#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT        0x0000001c
+
+// SQ_INSTRUCTION_CF_ALLOC_0
+#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT         0x00000004
+
+// SQ_INSTRUCTION_CF_ALLOC_1
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT       0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT        0x00000008
+#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT    0x00000009
+#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT       0x0000000b
+#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT           0x0000000c
+#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT             0x00000010
+#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT       0x00000014
+
+// SQ_INSTRUCTION_CF_ALLOC_2
+#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT         0x00000000
+#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT        0x00000018
+#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT    0x00000019
+#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT       0x0000001b
+#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT           0x0000001c
+
+// SQ_INSTRUCTION_TFETCH_0
+#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT   0x00000013
+#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT    0x00000019
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT          0x0000001a
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT          0x0000001c
+#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT          0x0000001e
+
+// SQ_INSTRUCTION_TFETCH_1
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT         0x0000000c
+#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT         0x0000000e
+#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT         0x00000010
+#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT       0x00000012
+#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT   0x00000015
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT     0x00000018
+#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT     0x0000001a
+#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT       0x0000001c
+#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT        0x0000001d
+#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_TFETCH_2
+#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT  0x00000000
+#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT    0x00000001
+#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT           0x00000002
+#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT             0x00000009
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT           0x00000010
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT           0x00000015
+#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT           0x0000001a
+#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_0
+#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT            0x00000005
+#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT         0x0000000b
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT            0x0000000c
+#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT         0x00000012
+#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT        0x00000013
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT        0x00000014
+#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT    0x00000019
+#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT            0x0000001e
+
+// SQ_INSTRUCTION_VFETCH_1
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT          0x00000000
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT          0x00000003
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT          0x00000006
+#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT          0x00000009
+#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT    0x0000000c
+#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT     0x0000000d
+#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e
+#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT        0x00000010
+#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT     0x00000017
+#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT        0x0000001f
+
+// SQ_INSTRUCTION_VFETCH_2
+#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT             0x00000000
+#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT             0x00000010
+#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT     0x0000001f
+
+// SQ_CONSTANT_0
+#define SQ_CONSTANT_0__RED__SHIFT                          0x00000000
+
+// SQ_CONSTANT_1
+#define SQ_CONSTANT_1__GREEN__SHIFT                        0x00000000
+
+// SQ_CONSTANT_2
+#define SQ_CONSTANT_2__BLUE__SHIFT                         0x00000000
+
+// SQ_CONSTANT_3
+#define SQ_CONSTANT_3__ALPHA__SHIFT                        0x00000000
+
+// SQ_FETCH_0
+#define SQ_FETCH_0__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_1
+#define SQ_FETCH_1__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_2
+#define SQ_FETCH_2__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_3
+#define SQ_FETCH_3__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_4
+#define SQ_FETCH_4__VALUE__SHIFT                           0x00000000
+
+// SQ_FETCH_5
+#define SQ_FETCH_5__VALUE__SHIFT                           0x00000000
+
+// SQ_CONSTANT_VFETCH_0
+#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT                  0x00000000
+#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT                 0x00000001
+#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT          0x00000002
+
+// SQ_CONSTANT_VFETCH_1
+#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT           0x00000000
+#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT         0x00000002
+
+// SQ_CONSTANT_T2
+#define SQ_CONSTANT_T2__VALUE__SHIFT                       0x00000000
+
+// SQ_CONSTANT_T3
+#define SQ_CONSTANT_T3__VALUE__SHIFT                       0x00000000
+
+// SQ_CF_BOOLEANS
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT               0x00000000
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT               0x00000008
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT               0x00000010
+#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT               0x00000018
+
+// SQ_CF_LOOP
+#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT                   0x00000000
+#define SQ_CF_LOOP__CF_LOOP_START__SHIFT                   0x00000008
+#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT                    0x00000010
+
+// SQ_CONSTANT_RT_0
+#define SQ_CONSTANT_RT_0__RED__SHIFT                       0x00000000
+
+// SQ_CONSTANT_RT_1
+#define SQ_CONSTANT_RT_1__GREEN__SHIFT                     0x00000000
+
+// SQ_CONSTANT_RT_2
+#define SQ_CONSTANT_RT_2__BLUE__SHIFT                      0x00000000
+
+// SQ_CONSTANT_RT_3
+#define SQ_CONSTANT_RT_3__ALPHA__SHIFT                     0x00000000
+
+// SQ_FETCH_RT_0
+#define SQ_FETCH_RT_0__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_1
+#define SQ_FETCH_RT_1__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_2
+#define SQ_FETCH_RT_2__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_3
+#define SQ_FETCH_RT_3__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_4
+#define SQ_FETCH_RT_4__VALUE__SHIFT                        0x00000000
+
+// SQ_FETCH_RT_5
+#define SQ_FETCH_RT_5__VALUE__SHIFT                        0x00000000
+
+// SQ_CF_RT_BOOLEANS
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT            0x00000000
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT            0x00000008
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT            0x00000010
+#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT            0x00000018
+
+// SQ_CF_RT_LOOP
+#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT                0x00000000
+#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT                0x00000008
+#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT                 0x00000010
+
+// SQ_VS_PROGRAM
+#define SQ_VS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_VS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_PS_PROGRAM
+#define SQ_PS_PROGRAM__BASE__SHIFT                         0x00000000
+#define SQ_PS_PROGRAM__SIZE__SHIFT                         0x0000000c
+
+// SQ_CF_PROGRAM_SIZE
+#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT              0x00000000
+#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT              0x0000000c
+
+// SQ_INTERPOLATOR_CNTL
+#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT           0x00000000
+#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT      0x00000010
+
+// SQ_PROGRAM_CNTL
+#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT                 0x00000000
+#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT                 0x00000008
+#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT                0x00000010
+#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT                0x00000011
+#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT                  0x00000012
+#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT              0x00000013
+#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT            0x00000014
+#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT             0x00000018
+#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT             0x0000001b
+#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT              0x0000001f
+
+// SQ_WRAPPING_0
+#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT                 0x00000000
+#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT                 0x00000004
+#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT                 0x00000008
+#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT                 0x0000000c
+#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT                 0x00000010
+#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT                 0x00000014
+#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT                 0x00000018
+#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT                 0x0000001c
+
+// SQ_WRAPPING_1
+#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT                 0x00000000
+#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT                 0x00000004
+#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT                0x00000008
+#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT                0x0000000c
+#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT                0x00000010
+#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT                0x00000014
+#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT                0x00000018
+#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT                0x0000001c
+
+// SQ_VS_CONST
+#define SQ_VS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_VS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_PS_CONST
+#define SQ_PS_CONST__BASE__SHIFT                           0x00000000
+#define SQ_PS_CONST__SIZE__SHIFT                           0x0000000c
+
+// SQ_CONTEXT_MISC
+#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT         0x00000000
+#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT        0x00000001
+#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT             0x00000002
+#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT              0x00000008
+#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT            0x00000010
+#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT             0x00000011
+#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT               0x00000012
+
+// SQ_CF_RD_BASE
+#define SQ_CF_RD_BASE__RD_BASE__SHIFT                      0x00000000
+
+// SQ_DEBUG_MISC_0
+#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT                 0x00000000
+#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT              0x00000004
+#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT               0x00000008
+#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT              0x00000018
+
+// SQ_DEBUG_MISC_1
+#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT                  0x00000000
+#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT                  0x00000001
+#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT              0x00000008
+#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT              0x00000010
+
+// MH_ARBITER_CONFIG
+#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT          0x00000000
+#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT    0x00000006
+#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT            0x00000007
+#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT       0x00000008
+#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT           0x00000009
+#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT                0x0000000a
+#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT        0x0000000d
+#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT       0x0000000e
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT   0x0000000f
+#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT          0x00000010
+#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT           0x00000016
+#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT          0x00000017
+#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT           0x00000018
+#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT           0x00000019
+#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT           0x0000001a
+
+// MH_CLNT_AXI_ID_REUSE
+#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT                0x00000000
+#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT             0x00000003
+#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT                0x00000004
+#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT             0x00000007
+#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT               0x00000008
+#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT             0x0000000b
+#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT                0x0000000c
+
+// MH_INTERRUPT_MASK
+#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT           0x00000000
+#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT          0x00000001
+#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT           0x00000002
+
+// MH_INTERRUPT_STATUS
+#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT         0x00000000
+#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT        0x00000001
+#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT         0x00000002
+
+// MH_INTERRUPT_CLEAR
+#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT          0x00000000
+#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT         0x00000001
+#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT          0x00000002
+
+// MH_AXI_ERROR
+#define MH_AXI_ERROR__AXI_READ_ID__SHIFT                   0x00000000
+#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT                0x00000003
+#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT                  0x00000004
+#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT               0x00000007
+
+// MH_PERFCOUNTER0_SELECT
+#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER1_SELECT
+#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// MH_PERFCOUNTER0_CONFIG
+#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER1_CONFIG
+#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT             0x00000000
+
+// MH_PERFCOUNTER0_LOW
+#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER1_LOW
+#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT       0x00000000
+
+// MH_PERFCOUNTER0_HI
+#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_PERFCOUNTER1_HI
+#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT         0x00000000
+
+// MH_DEBUG_CTRL
+#define MH_DEBUG_CTRL__INDEX__SHIFT                        0x00000000
+
+// MH_DEBUG_DATA
+#define MH_DEBUG_DATA__DATA__SHIFT                         0x00000000
+
+// MH_AXI_HALT_CONTROL
+#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT               0x00000000
+
+// MH_DEBUG_REG00
+#define MH_DEBUG_REG00__MH_BUSY__SHIFT                     0x00000000
+#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT           0x00000001
+#define MH_DEBUG_REG00__CP_REQUEST__SHIFT                  0x00000002
+#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT                 0x00000003
+#define MH_DEBUG_REG00__TC_REQUEST__SHIFT                  0x00000004
+#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT                0x00000005
+#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT                 0x00000006
+#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT                   0x00000007
+#define MH_DEBUG_REG00__TCD_FULL__SHIFT                    0x00000008
+#define MH_DEBUG_REG00__RB_REQUEST__SHIFT                  0x00000009
+#define MH_DEBUG_REG00__PA_REQUEST__SHIFT                  0x0000000a
+#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT             0x0000000b
+#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT                   0x0000000c
+#define MH_DEBUG_REG00__ARQ_FULL__SHIFT                    0x0000000d
+#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT                   0x0000000e
+#define MH_DEBUG_REG00__WDB_FULL__SHIFT                    0x0000000f
+#define MH_DEBUG_REG00__AXI_AVALID__SHIFT                  0x00000010
+#define MH_DEBUG_REG00__AXI_AREADY__SHIFT                  0x00000011
+#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT                 0x00000012
+#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT                 0x00000013
+#define MH_DEBUG_REG00__AXI_WVALID__SHIFT                  0x00000014
+#define MH_DEBUG_REG00__AXI_WREADY__SHIFT                  0x00000015
+#define MH_DEBUG_REG00__AXI_RVALID__SHIFT                  0x00000016
+#define MH_DEBUG_REG00__AXI_RREADY__SHIFT                  0x00000017
+#define MH_DEBUG_REG00__AXI_BVALID__SHIFT                  0x00000018
+#define MH_DEBUG_REG00__AXI_BREADY__SHIFT                  0x00000019
+#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT                0x0000001a
+#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT                0x0000001b
+#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT                 0x0000001c
+
+// MH_DEBUG_REG01
+#define MH_DEBUG_REG01__CP_SEND_q__SHIFT                   0x00000000
+#define MH_DEBUG_REG01__CP_RTR_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT                  0x00000002
+#define MH_DEBUG_REG01__CP_TAG_q__SHIFT                    0x00000003
+#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT                   0x00000006
+#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT                  0x00000007
+#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG01__TC_SEND_q__SHIFT                   0x0000000a
+#define MH_DEBUG_REG01__TC_RTR_q__SHIFT                    0x0000000b
+#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT                   0x0000000c
+#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT                0x0000000e
+#define MH_DEBUG_REG01__TC_MH_written__SHIFT               0x0000000f
+#define MH_DEBUG_REG01__RB_SEND_q__SHIFT                   0x00000010
+#define MH_DEBUG_REG01__RB_RTR_q__SHIFT                    0x00000011
+#define MH_DEBUG_REG01__PA_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG01__PA_RTR_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG02
+#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT               0x00000003
+#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT                 0x00000004
+#define MH_DEBUG_REG02__RDC_RID__SHIFT                     0x00000007
+#define MH_DEBUG_REG02__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT            0x0000000c
+#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT            0x0000000d
+#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT            0x0000000e
+#define MH_DEBUG_REG02__BRC_BID__SHIFT                     0x0000000f
+#define MH_DEBUG_REG02__BRC_BRESP__SHIFT                   0x00000012
+
+// MH_DEBUG_REG03
+#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT           0x00000000
+
+// MH_DEBUG_REG04
+#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT          0x00000000
+
+// MH_DEBUG_REG05
+#define MH_DEBUG_REG05__CP_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG05__CP_MH_write__SHIFT                 0x00000001
+#define MH_DEBUG_REG05__CP_MH_tag__SHIFT                   0x00000002
+#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT               0x00000005
+
+// MH_DEBUG_REG06
+#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG07
+#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG08
+#define MH_DEBUG_REG08__CP_MH_be__SHIFT                    0x00000000
+#define MH_DEBUG_REG08__RB_MH_be__SHIFT                    0x00000008
+#define MH_DEBUG_REG08__PA_MH_be__SHIFT                    0x00000010
+
+// MH_DEBUG_REG09
+#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG09__VGT_MH_send__SHIFT                 0x00000003
+#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT                0x00000004
+#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT              0x00000005
+
+// MH_DEBUG_REG10
+#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG10__TC_MH_send__SHIFT                  0x00000002
+#define MH_DEBUG_REG10__TC_MH_mask__SHIFT                  0x00000003
+#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG11
+#define MH_DEBUG_REG11__TC_MH_info__SHIFT                  0x00000000
+#define MH_DEBUG_REG11__TC_MH_send__SHIFT                  0x00000019
+
+// MH_DEBUG_REG12
+#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT                0x00000000
+#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT           0x00000019
+#define MH_DEBUG_REG12__TC_MH_written__SHIFT               0x0000001a
+
+// MH_DEBUG_REG13
+#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT                 0x00000002
+#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT                 0x00000003
+#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT            0x00000005
+
+// MH_DEBUG_REG14
+#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT                 0x00000000
+#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT                 0x00000019
+
+// MH_DEBUG_REG15
+#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG15__RB_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG16
+#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG17
+#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG18
+#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG18__PA_MH_send__SHIFT                  0x00000004
+#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT             0x00000005
+
+// MH_DEBUG_REG19
+#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT             0x00000000
+
+// MH_DEBUG_REG20
+#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT            0x00000000
+
+// MH_DEBUG_REG21
+#define MH_DEBUG_REG21__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG21__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG21__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG21__ARVALID_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG21__ARREADY_q__SHIFT                   0x00000009
+#define MH_DEBUG_REG21__ARID_q__SHIFT                      0x0000000a
+#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT                 0x0000000d
+#define MH_DEBUG_REG21__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG21__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG21__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG21__RID_q__SHIFT                       0x00000012
+#define MH_DEBUG_REG21__WVALID_q__SHIFT                    0x00000015
+#define MH_DEBUG_REG21__WREADY_q__SHIFT                    0x00000016
+#define MH_DEBUG_REG21__WLAST_q__SHIFT                     0x00000017
+#define MH_DEBUG_REG21__WID_q__SHIFT                       0x00000018
+#define MH_DEBUG_REG21__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG21__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG21__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG22
+#define MH_DEBUG_REG22__AVALID_q__SHIFT                    0x00000000
+#define MH_DEBUG_REG22__AREADY_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG22__AID_q__SHIFT                       0x00000002
+#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT                  0x00000005
+#define MH_DEBUG_REG22__ARVALID_q__SHIFT                   0x00000007
+#define MH_DEBUG_REG22__ARREADY_q__SHIFT                   0x00000008
+#define MH_DEBUG_REG22__ARID_q__SHIFT                      0x00000009
+#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT                 0x0000000c
+#define MH_DEBUG_REG22__WVALID_q__SHIFT                    0x0000000d
+#define MH_DEBUG_REG22__WREADY_q__SHIFT                    0x0000000e
+#define MH_DEBUG_REG22__WLAST_q__SHIFT                     0x0000000f
+#define MH_DEBUG_REG22__WID_q__SHIFT                       0x00000010
+#define MH_DEBUG_REG22__WSTRB_q__SHIFT                     0x00000013
+#define MH_DEBUG_REG22__BVALID_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG22__BREADY_q__SHIFT                    0x0000001c
+#define MH_DEBUG_REG22__BID_q__SHIFT                       0x0000001d
+
+// MH_DEBUG_REG23
+#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT                 0x00000001
+#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT                0x00000004
+
+// MH_DEBUG_REG24
+#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT                 0x00000000
+#define MH_DEBUG_REG24__REG_A__SHIFT                       0x00000002
+#define MH_DEBUG_REG24__REG_RE__SHIFT                      0x00000010
+#define MH_DEBUG_REG24__REG_WE__SHIFT                      0x00000011
+#define MH_DEBUG_REG24__BLOCK_RS__SHIFT                    0x00000012
+
+// MH_DEBUG_REG25
+#define MH_DEBUG_REG25__REG_WD__SHIFT                      0x00000000
+
+// MH_DEBUG_REG26
+#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT                0x00000000
+#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT        0x00000001
+#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT       0x00000002
+#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT     0x00000003
+#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT                 0x00000004
+#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT     0x00000005
+#define MH_DEBUG_REG26__CNT_q__SHIFT                       0x00000006
+#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT                0x0000000d
+#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT                   0x0000000e
+#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT               0x0000000f
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010
+#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011
+#define MH_DEBUG_REG26__CP_SEND_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG26__CP_RTR_q__SHIFT                    0x00000013
+#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT                  0x00000014
+#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT               0x00000016
+#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT            0x00000017
+#define MH_DEBUG_REG26__RB_SEND_q__SHIFT                   0x00000018
+#define MH_DEBUG_REG26__RB_RTR_q__SHIFT                    0x00000019
+#define MH_DEBUG_REG26__PA_SEND_q__SHIFT                   0x0000001a
+#define MH_DEBUG_REG26__PA_RTR_q__SHIFT                    0x0000001b
+#define MH_DEBUG_REG26__RDC_VALID__SHIFT                   0x0000001c
+#define MH_DEBUG_REG26__RDC_RLAST__SHIFT                   0x0000001d
+#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT               0x0000001e
+#define MH_DEBUG_REG26__BRC_VALID__SHIFT                   0x0000001f
+
+// MH_DEBUG_REG27
+#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT              0x00000000
+#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT         0x00000003
+#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT                 0x00000006
+#define MH_DEBUG_REG27__ARB_WINNER__SHIFT                  0x00000009
+#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT                0x0000000c
+#define MH_DEBUG_REG27__EFF1_WIN__SHIFT                    0x0000000f
+#define MH_DEBUG_REG27__KILL_EFF1__SHIFT                   0x00000010
+#define MH_DEBUG_REG27__ARB_HOLD__SHIFT                    0x00000011
+#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT                   0x00000012
+#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT                0x00000013
+#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT               0x00000014
+#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT                0x00000015
+#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT           0x00000016
+#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT                0x00000017
+#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT                0x00000018
+#define MH_DEBUG_REG27__ARB_QUAL__SHIFT                    0x00000019
+#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT                 0x0000001a
+#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT                0x0000001b
+#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT                 0x0000001c
+#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT                 0x0000001d
+#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT              0x0000001e
+#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG28
+#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT                 0x00000000
+#define MH_DEBUG_REG28__ARB_WINNER__SHIFT                  0x00000003
+#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT                0x00000006
+#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT               0x00000007
+#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT                0x00000008
+#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT           0x00000009
+#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT                0x0000000a
+#define MH_DEBUG_REG28__ARB_QUAL__SHIFT                    0x0000000b
+#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT                 0x0000000c
+#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT                0x0000000d
+#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT                 0x0000000e
+#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT                 0x0000000f
+#define MH_DEBUG_REG28__EFF1_WIN__SHIFT                    0x00000010
+#define MH_DEBUG_REG28__KILL_EFF1__SHIFT                   0x00000011
+#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT              0x00000012
+#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT                 0x00000013
+#define MH_DEBUG_REG28__ARB_HOLD__SHIFT                    0x00000014
+#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT                   0x00000015
+#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT     0x00000016
+
+// MH_DEBUG_REG29
+#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT         0x00000000
+#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT        0x00000003
+#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT              0x00000006
+#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT       0x00000009
+#define MH_DEBUG_REG29__ARB_HOLD__SHIFT                    0x0000000a
+#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT                   0x0000000b
+#define MH_DEBUG_REG29__CLNT_REQ__SHIFT                    0x0000000c
+#define MH_DEBUG_REG29__RECENT_d_0__SHIFT                  0x00000011
+#define MH_DEBUG_REG29__RECENT_d_1__SHIFT                  0x00000014
+#define MH_DEBUG_REG29__RECENT_d_2__SHIFT                  0x00000017
+#define MH_DEBUG_REG29__RECENT_d_3__SHIFT                  0x0000001a
+#define MH_DEBUG_REG29__RECENT_d_4__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG30
+#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT                 0x00000000
+#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT      0x00000001
+#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT        0x00000002
+#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT              0x00000003
+#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT                0x00000005
+#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008
+#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT            0x00000009
+#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT               0x0000000a
+#define MH_DEBUG_REG30__TC_MH_written__SHIFT               0x0000000b
+#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT          0x0000000c
+#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT               0x00000013
+#define MH_DEBUG_REG30__WLAST_q__SHIFT                     0x00000014
+#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT                 0x00000015
+#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT                0x00000016
+#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT                0x00000019
+#define MH_DEBUG_REG30__CP_MH_write__SHIFT                 0x0000001a
+#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT                0x0000001b
+#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT                0x0000001c
+#define MH_DEBUG_REG30__ARB_WINNER__SHIFT                  0x0000001d
+
+// MH_DEBUG_REG31
+#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT         0x00000000
+#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a
+
+// MH_DEBUG_REG32
+#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT                  0x00000008
+#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT                 0x00000010
+#define MH_DEBUG_REG32__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG32__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG33
+#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT             0x00000000
+#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT                  0x00000008
+#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT                 0x00000010
+#define MH_DEBUG_REG33__TC_MH_send__SHIFT                  0x00000018
+#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT                0x00000019
+#define MH_DEBUG_REG33__KILL_EFF1__SHIFT                   0x0000001a
+#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT    0x0000001b
+#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT           0x0000001c
+#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT                0x0000001d
+#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT                0x0000001e
+#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT                 0x0000001f
+
+// MH_DEBUG_REG34
+#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT           0x00000000
+#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT           0x00000008
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT       0x00000010
+#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT       0x00000018
+
+// MH_DEBUG_REG35
+#define MH_DEBUG_REG35__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT                0x00000002
+#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT               0x00000003
+#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT           0x00000004
+#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT                  0x00000005
+
+// MH_DEBUG_REG36
+#define MH_DEBUG_REG36__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT                0x00000002
+#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT               0x00000003
+#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT           0x00000004
+#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT                  0x00000005
+
+// MH_DEBUG_REG37
+#define MH_DEBUG_REG37__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT                0x00000002
+#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT               0x00000003
+#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT           0x00000004
+#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT                  0x00000005
+
+// MH_DEBUG_REG38
+#define MH_DEBUG_REG38__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT                0x00000002
+#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT               0x00000003
+#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT           0x00000004
+#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT                  0x00000005
+
+// MH_DEBUG_REG39
+#define MH_DEBUG_REG39__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT                0x00000002
+#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT               0x00000003
+#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT           0x00000004
+#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT                  0x00000005
+
+// MH_DEBUG_REG40
+#define MH_DEBUG_REG40__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT                0x00000002
+#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT               0x00000003
+#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT           0x00000004
+#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT                  0x00000005
+
+// MH_DEBUG_REG41
+#define MH_DEBUG_REG41__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT                0x00000002
+#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT               0x00000003
+#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT           0x00000004
+#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT                  0x00000005
+
+// MH_DEBUG_REG42
+#define MH_DEBUG_REG42__TC_MH_send__SHIFT                  0x00000000
+#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT                0x00000001
+#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT                0x00000002
+#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT               0x00000003
+#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT           0x00000004
+#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT                  0x00000005
+
+// MH_DEBUG_REG43
+#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT                0x00000000
+#define MH_DEBUG_REG43__ARB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT             0x00000002
+#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT                   0x00000003
+#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT                 0x00000004
+#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT              0x00000005
+#define MH_DEBUG_REG43__MMU_RTR__SHIFT                     0x00000006
+#define MH_DEBUG_REG43__ARB_ID_q__SHIFT                    0x00000007
+#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT                 0x0000000a
+#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT                  0x0000000b
+#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT              0x0000000c
+#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT              0x0000000d
+#define MH_DEBUG_REG43__MMU_WE__SHIFT                      0x00000010
+#define MH_DEBUG_REG43__ARQ_RTR__SHIFT                     0x00000011
+#define MH_DEBUG_REG43__MMU_ID__SHIFT                      0x00000012
+#define MH_DEBUG_REG43__MMU_WRITE__SHIFT                   0x00000015
+#define MH_DEBUG_REG43__MMU_BLEN__SHIFT                    0x00000016
+#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT                 0x00000017
+#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT               0x00000018
+#define MH_DEBUG_REG43__WDB_WE__SHIFT                      0x00000019
+#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT              0x0000001a
+#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT              0x0000001b
+
+// MH_DEBUG_REG44
+#define MH_DEBUG_REG44__ARB_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG44__ARB_ID_q__SHIFT                    0x00000001
+#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT                   0x00000004
+
+// MH_DEBUG_REG45
+#define MH_DEBUG_REG45__MMU_WE__SHIFT                      0x00000000
+#define MH_DEBUG_REG45__MMU_ID__SHIFT                      0x00000001
+#define MH_DEBUG_REG45__MMU_PAD__SHIFT                     0x00000004
+
+// MH_DEBUG_REG46
+#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT               0x00000000
+#define MH_DEBUG_REG46__WDB_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT            0x00000002
+#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT              0x00000003
+#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT                 0x00000004
+#define MH_DEBUG_REG46__ARB_WLAST__SHIFT                   0x0000000c
+#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT              0x0000000d
+#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT                0x00000013
+#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT                 0x00000014
+#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT               0x00000017
+#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT               0x00000018
+
+// MH_DEBUG_REG47
+#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT          0x00000000
+
+// MH_DEBUG_REG48
+#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT         0x00000000
+
+// MH_DEBUG_REG49
+#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT              0x00000000
+#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT             0x00000001
+#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT              0x00000002
+#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT              0x00000003
+#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT            0x00000004
+#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT           0x00000005
+#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT               0x00000006
+#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT           0x00000007
+#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT               0x0000000d
+#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT              0x0000000e
+#define MH_DEBUG_REG49__RVALID_q__SHIFT                    0x0000000f
+#define MH_DEBUG_REG49__RREADY_q__SHIFT                    0x00000010
+#define MH_DEBUG_REG49__RLAST_q__SHIFT                     0x00000011
+#define MH_DEBUG_REG49__BVALID_q__SHIFT                    0x00000012
+#define MH_DEBUG_REG49__BREADY_q__SHIFT                    0x00000013
+
+// MH_DEBUG_REG50
+#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT              0x00000000
+#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT             0x00000001
+#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT                0x00000002
+#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT             0x00000003
+#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT               0x00000004
+#define MH_DEBUG_REG50__RDC_VALID__SHIFT                   0x00000005
+#define MH_DEBUG_REG50__RDC_RID__SHIFT                     0x00000006
+#define MH_DEBUG_REG50__RDC_RLAST__SHIFT                   0x00000009
+#define MH_DEBUG_REG50__RDC_RRESP__SHIFT                   0x0000000a
+#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT            0x0000000c
+#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT           0x0000000d
+#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT            0x0000000e
+#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT     0x0000000f
+#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT             0x00000015
+#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT        0x00000016
+#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT                 0x0000001c
+#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d
+
+// MH_DEBUG_REG51
+#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT           0x00000000
+
+// MH_DEBUG_REG52
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT      0x00000000
+#define MH_DEBUG_REG52__ARB_WE__SHIFT                      0x00000002
+#define MH_DEBUG_REG52__MMU_RTR__SHIFT                     0x00000003
+#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT     0x00000004
+#define MH_DEBUG_REG52__ARB_ID_q__SHIFT                    0x0000001a
+#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT                 0x0000001d
+#define MH_DEBUG_REG52__client_behavior_q__SHIFT           0x0000001e
+
+// MH_DEBUG_REG53
+#define MH_DEBUG_REG53__stage1_valid__SHIFT                0x00000000
+#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT           0x00000001
+#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT             0x00000002
+#define MH_DEBUG_REG53__tag_match_q__SHIFT                 0x00000003
+#define MH_DEBUG_REG53__tag_miss_q__SHIFT                  0x00000004
+#define MH_DEBUG_REG53__va_in_range_q__SHIFT               0x00000005
+#define MH_DEBUG_REG53__MMU_MISS__SHIFT                    0x00000006
+#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT               0x00000007
+#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT              0x00000008
+#define MH_DEBUG_REG53__MMU_HIT__SHIFT                     0x00000009
+#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT                0x0000000a
+#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT               0x0000000b
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT      0x0000000c
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT       0x0000000d
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT   0x0000000e
+#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT    0x0000000f
+#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT             0x00000010
+
+// MH_DEBUG_REG54
+#define MH_DEBUG_REG54__ARQ_RTR__SHIFT                     0x00000000
+#define MH_DEBUG_REG54__MMU_WE__SHIFT                      0x00000001
+#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT           0x00000002
+#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT            0x00000003
+#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT             0x00000004
+#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005
+#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT             0x00000006
+#define MH_DEBUG_REG54__stage1_valid__SHIFT                0x00000007
+#define MH_DEBUG_REG54__stage2_valid__SHIFT                0x00000008
+#define MH_DEBUG_REG54__client_behavior_q__SHIFT           0x00000009
+#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT           0x0000000b
+#define MH_DEBUG_REG54__tag_match_q__SHIFT                 0x0000000c
+#define MH_DEBUG_REG54__tag_miss_q__SHIFT                  0x0000000d
+#define MH_DEBUG_REG54__va_in_range_q__SHIFT               0x0000000e
+#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT        0x0000000f
+#define MH_DEBUG_REG54__TAG_valid_q__SHIFT                 0x00000010
+
+// MH_DEBUG_REG55
+#define MH_DEBUG_REG55__TAG0_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT               0x0000000d
+#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG55__TAG1_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT               0x0000001d
+
+// MH_DEBUG_REG56
+#define MH_DEBUG_REG56__TAG2_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT               0x0000000d
+#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG56__TAG3_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT               0x0000001d
+
+// MH_DEBUG_REG57
+#define MH_DEBUG_REG57__TAG4_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT               0x0000000d
+#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG57__TAG5_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT               0x0000001d
+
+// MH_DEBUG_REG58
+#define MH_DEBUG_REG58__TAG6_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT               0x0000000d
+#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG58__TAG7_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT               0x0000001d
+
+// MH_DEBUG_REG59
+#define MH_DEBUG_REG59__TAG8_VA__SHIFT                     0x00000000
+#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT               0x0000000d
+#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG59__TAG9_VA__SHIFT                     0x00000010
+#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT               0x0000001d
+
+// MH_DEBUG_REG60
+#define MH_DEBUG_REG60__TAG10_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT              0x0000000d
+#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG60__TAG11_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT              0x0000001d
+
+// MH_DEBUG_REG61
+#define MH_DEBUG_REG61__TAG12_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT              0x0000000d
+#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG61__TAG13_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT              0x0000001d
+
+// MH_DEBUG_REG62
+#define MH_DEBUG_REG62__TAG14_VA__SHIFT                    0x00000000
+#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT              0x0000000d
+#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT                 0x0000000e
+#define MH_DEBUG_REG62__TAG15_VA__SHIFT                    0x00000010
+#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT              0x0000001d
+
+// MH_DEBUG_REG63
+#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT              0x00000000
+
+// MH_MMU_CONFIG
+#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT                   0x00000000
+#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT            0x00000001
+#define MH_MMU_CONFIG__RESERVED1__SHIFT                    0x00000002
+#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT           0x00000004
+#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT           0x00000006
+#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT          0x00000008
+#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT          0x0000000a
+#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT          0x0000000c
+#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT          0x0000000e
+#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT          0x00000010
+#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT         0x00000012
+#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT         0x00000014
+#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT           0x00000016
+#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT           0x00000018
+
+// MH_MMU_VA_RANGE
+#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT           0x00000000
+#define MH_MMU_VA_RANGE__VA_BASE__SHIFT                    0x0000000c
+
+// MH_MMU_PT_BASE
+#define MH_MMU_PT_BASE__PT_BASE__SHIFT                     0x0000000c
+
+// MH_MMU_PAGE_FAULT
+#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT               0x00000000
+#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT                  0x00000001
+#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT            0x00000002
+#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT                   0x00000004
+#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT                0x00000007
+#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008
+#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT     0x00000009
+#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT    0x0000000a
+#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT   0x0000000b
+#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT                   0x0000000c
+
+// MH_MMU_TRAN_ERROR
+#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT               0x00000005
+
+// MH_MMU_INVALIDATE
+#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT           0x00000000
+#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT            0x00000001
+
+// MH_MMU_MPU_BASE
+#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT                   0x0000000c
+
+// MH_MMU_MPU_END
+#define MH_MMU_MPU_END__MPU_END__SHIFT                     0x0000000c
+
+// WAIT_UNTIL
+#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT                   0x00000001
+#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT                   0x00000002
+#define WAIT_UNTIL__WAIT_VSYNC__SHIFT                      0x00000003
+#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT                  0x00000004
+#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT                  0x00000005
+#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT                  0x00000006
+#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT                    0x0000000a
+#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT                    0x0000000e
+#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT                    0x0000000f
+#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT               0x00000010
+#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT               0x00000011
+#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT                 0x00000014
+
+// RBBM_ISYNC_CNTL
+#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT         0x00000004
+#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT    0x00000005
+
+// RBBM_STATUS
+#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT                  0x00000000
+#define RBBM_STATUS__TC_BUSY__SHIFT                        0x00000005
+#define RBBM_STATUS__HIRQ_PENDING__SHIFT                   0x00000008
+#define RBBM_STATUS__CPRQ_PENDING__SHIFT                   0x00000009
+#define RBBM_STATUS__CFRQ_PENDING__SHIFT                   0x0000000a
+#define RBBM_STATUS__PFRQ_PENDING__SHIFT                   0x0000000b
+#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT                0x0000000c
+#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT                   0x0000000e
+#define RBBM_STATUS__CP_NRT_BUSY__SHIFT                    0x00000010
+#define RBBM_STATUS__MH_BUSY__SHIFT                        0x00000012
+#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT              0x00000013
+#define RBBM_STATUS__SX_BUSY__SHIFT                        0x00000015
+#define RBBM_STATUS__TPC_BUSY__SHIFT                       0x00000016
+#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT                   0x00000018
+#define RBBM_STATUS__PA_BUSY__SHIFT                        0x00000019
+#define RBBM_STATUS__VGT_BUSY__SHIFT                       0x0000001a
+#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT                 0x0000001b
+#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT                  0x0000001c
+#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT                   0x0000001e
+#define RBBM_STATUS__GUI_ACTIVE__SHIFT                     0x0000001f
+
+// RBBM_DSPLY
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT           0x00000000
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT           0x00000001
+#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT           0x00000002
+#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT             0x00000003
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT              0x00000004
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT              0x00000005
+#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT              0x00000006
+#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT                 0x00000007
+#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT                0x00000008
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT              0x0000000a
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT              0x0000000b
+#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT              0x0000000c
+#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT                 0x0000000d
+#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT                0x0000000e
+#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT              0x00000010
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT              0x00000014
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT              0x00000015
+#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT              0x00000016
+#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT                 0x00000017
+#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT                0x00000018
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT              0x0000001a
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT              0x0000001b
+#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT              0x0000001c
+#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT                 0x0000001d
+#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT                0x0000001e
+
+// RBBM_RENDER_LATEST
+#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT       0x00000000
+#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT       0x00000008
+#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT       0x00000010
+#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT       0x00000018
+
+// RBBM_RTL_RELEASE
+#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT                0x00000000
+
+// RBBM_PATCH_RELEASE
+#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT          0x00000000
+#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT         0x00000010
+#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT             0x00000018
+
+// RBBM_AUXILIARY_CONFIG
+#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT             0x00000000
+
+// RBBM_PERIPHID0
+#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT                 0x00000000
+
+// RBBM_PERIPHID1
+#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT                 0x00000000
+#define RBBM_PERIPHID1__DESIGNER0__SHIFT                   0x00000004
+
+// RBBM_PERIPHID2
+#define RBBM_PERIPHID2__DESIGNER1__SHIFT                   0x00000000
+#define RBBM_PERIPHID2__REVISION__SHIFT                    0x00000004
+
+// RBBM_PERIPHID3
+#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT         0x00000000
+#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT        0x00000002
+#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT                0x00000004
+#define RBBM_PERIPHID3__CONTINUATION__SHIFT                0x00000007
+
+// RBBM_CNTL
+#define RBBM_CNTL__READ_TIMEOUT__SHIFT                     0x00000000
+#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT             0x00000008
+
+// RBBM_SKEW_CNTL
+#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT          0x00000000
+#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT                  0x00000005
+
+// RBBM_SOFT_RESET
+#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT              0x00000000
+#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT              0x00000002
+#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT              0x00000003
+#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT              0x00000004
+#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT              0x00000005
+#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT              0x00000006
+#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT             0x0000000c
+#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT              0x0000000f
+#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT             0x00000010
+
+// RBBM_PM_OVERRIDE1
+#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000001
+#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT      0x00000002
+#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT  0x00000003
+#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT   0x00000004
+#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000005
+#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007
+#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT   0x00000008
+#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT      0x00000009
+#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b
+#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c
+#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d
+#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e
+#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f
+#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010
+#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011
+#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012
+#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013
+#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT   0x00000014
+#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000015
+#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT    0x00000016
+#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000017
+#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018
+#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT     0x00000019
+#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001a
+#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT      0x0000001b
+#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT   0x0000001c
+#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT  0x0000001d
+#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT  0x0000001e
+#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f
+
+// RBBM_PM_OVERRIDE2
+#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT  0x00000000
+#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT   0x00000001
+#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT   0x00000002
+#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003
+#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004
+#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005
+#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006
+#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT    0x00000007
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT  0x00000008
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT  0x00000009
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT  0x0000000a
+#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT  0x0000000b
+
+// GC_SYS_IDLE
+#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT              0x00000000
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT           0x00000010
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT             0x00000018
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT                0x00000019
+#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT    0x0000001d
+#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT       0x0000001e
+#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT           0x0000001f
+
+// NQWAIT_UNTIL
+#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT                 0x00000000
+
+// RBBM_DEBUG_OUT
+#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT               0x00000000
+
+// RBBM_DEBUG_CNTL
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT             0x00000000
+#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT              0x00000008
+#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT                  0x0000000c
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT        0x00000010
+#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT         0x00000018
+#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT         0x0000001c
+
+// RBBM_DEBUG
+#define RBBM_DEBUG__IGNORE_RTR__SHIFT                      0x00000001
+#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT              0x00000002
+#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT           0x00000003
+#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT           0x00000004
+#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT       0x00000008
+#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT               0x00000010
+#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000011
+#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT   0x00000012
+#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT    0x00000013
+#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT                  0x00000014
+#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT                 0x00000015
+#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT                  0x00000016
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT      0x00000017
+#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT             0x00000018
+#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT             0x0000001f
+
+// RBBM_READ_ERROR
+#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT               0x00000002
+#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT             0x0000001e
+#define RBBM_READ_ERROR__READ_ERROR__SHIFT                 0x0000001f
+
+// RBBM_WAIT_IDLE_CLOCKS
+#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000
+
+// RBBM_INT_CNTL
+#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT               0x00000000
+#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT      0x00000001
+#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT            0x00000013
+
+// RBBM_INT_STATUS
+#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT             0x00000000
+#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT    0x00000001
+#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT          0x00000013
+
+// RBBM_INT_ACK
+#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT                 0x00000000
+#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT        0x00000001
+#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT              0x00000013
+
+// MASTER_INT_SIGNAL
+#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT              0x00000005
+#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT              0x0000001a
+#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT              0x0000001e
+#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT            0x0000001f
+
+// RBBM_PERFCOUNTER1_SELECT
+#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT   0x00000000
+
+// RBBM_PERFCOUNTER1_LO
+#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT        0x00000000
+
+// RBBM_PERFCOUNTER1_HI
+#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT        0x00000000
+
+// CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT                         0x00000005
+
+// CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT                        0x00000000
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT                        0x00000008
+#define CP_RB_CNTL__BUF_SWAP__SHIFT                        0x00000010
+#define CP_RB_CNTL__RB_POLL_EN__SHIFT                      0x00000014
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                    0x0000001b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                  0x0000001f
+
+// CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT               0x00000002
+
+// CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT                         0x00000000
+
+// CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                   0x00000000
+
+// CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT                         0x00000000
+
+// CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT           0x00000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT           0x0000001c
+
+// CP_RB_WPTR_BASE
+#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT               0x00000000
+#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT               0x00000002
+
+// CP_IB1_BASE
+#define CP_IB1_BASE__IB1_BASE__SHIFT                       0x00000002
+
+// CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                     0x00000000
+
+// CP_IB2_BASE
+#define CP_IB2_BASE__IB2_BASE__SHIFT                       0x00000002
+
+// CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                     0x00000000
+
+// CP_ST_BASE
+#define CP_ST_BASE__ST_BASE__SHIFT                         0x00000002
+
+// CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                       0x00000000
+
+// CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT          0x00000000
+#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT          0x00000008
+#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT           0x00000010
+
+// CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT                  0x00000010
+#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT                  0x00000018
+
+// CP_CSQ_AVAIL
+#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT                  0x00000000
+#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT                   0x00000008
+#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT                   0x00000010
+
+// CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT                    0x00000000
+
+// CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                       0x00000000
+
+// CP_CSQ_RB_STAT
+#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT            0x00000000
+#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT            0x00000010
+
+// CP_CSQ_IB1_STAT
+#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT         0x00000000
+#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT         0x00000010
+
+// CP_CSQ_IB2_STAT
+#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT         0x00000000
+#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT         0x00000010
+
+// CP_NON_PREFETCH_CNTRS
+#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT          0x00000000
+#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT          0x00000008
+
+// CP_STQ_ST_STAT
+#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT                 0x00000000
+#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT                 0x00000010
+
+// CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT                       0x00000000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT                       0x00000010
+
+// CP_MIU_TAG_STAT
+#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT                 0x00000000
+#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT                 0x00000001
+#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT                 0x00000002
+#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT                 0x00000003
+#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT                 0x00000004
+#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT                 0x00000005
+#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT                 0x00000006
+#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT                 0x00000007
+#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT                 0x00000008
+#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT                 0x00000009
+#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT                0x0000000a
+#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT                0x0000000b
+#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT                0x0000000c
+#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT                0x0000000d
+#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT                0x0000000e
+#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT                0x0000000f
+#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT                0x00000010
+#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT                0x00000011
+#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT         0x0000001f
+
+// CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT                     0x00000000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                 0x00000010
+
+// CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT                       0x00000000
+
+// CP_ME_CNTL
+#define CP_ME_CNTL__ME_STATMUX__SHIFT                      0x00000000
+#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT          0x00000019
+#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT          0x0000001a
+#define CP_ME_CNTL__ME_HALT__SHIFT                         0x0000001c
+#define CP_ME_CNTL__ME_BUSY__SHIFT                         0x0000001d
+#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT                   0x0000001f
+
+// CP_ME_STATUS
+#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT                 0x00000000
+
+// CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT               0x00000000
+
+// CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                 0x00000000
+
+// CP_ME_RDADDR
+#define CP_ME_RDADDR__ME_RDADDR__SHIFT                     0x00000000
+
+// CP_DEBUG
+#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT           0x00000000
+#define CP_DEBUG__PREDICATE_DISABLE__SHIFT                 0x00000017
+#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT               0x00000018
+#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT           0x00000019
+#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT                0x0000001a
+#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT               0x0000001b
+#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT            0x0000001c
+#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT            0x0000001e
+#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT            0x0000001f
+
+// SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT              0x00000000
+
+// SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT              0x00000000
+
+// SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT              0x00000000
+
+// SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT              0x00000000
+
+// SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT              0x00000000
+
+// SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT              0x00000000
+
+// SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT              0x00000000
+
+// SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT                  0x00000000
+#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT              0x00000000
+
+// SCRATCH_UMSK
+#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT                  0x00000000
+#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT                  0x00000010
+
+// SCRATCH_ADDR
+#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT                  0x00000005
+
+// CP_ME_VS_EVENT_SRC
+#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_VS_EVENT_ADDR
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_VS_EVENT_DATA
+#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_VS_EVENT_ADDR_SWM
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_VS_EVENT_DATA_SWM
+#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_PS_EVENT_SRC
+#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT             0x00000000
+#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT            0x00000001
+
+// CP_ME_PS_EVENT_ADDR
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_PS_EVENT_DATA
+#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_PS_EVENT_ADDR_SWM
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT   0x00000000
+#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT   0x00000002
+
+// CP_ME_PS_EVENT_DATA_SWM
+#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT   0x00000000
+
+// CP_ME_CF_EVENT_SRC
+#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT             0x00000000
+
+// CP_ME_CF_EVENT_ADDR
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT           0x00000000
+#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT           0x00000002
+
+// CP_ME_CF_EVENT_DATA
+#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT           0x00000000
+
+// CP_ME_NRT_ADDR
+#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT              0x00000000
+#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT              0x00000002
+
+// CP_ME_NRT_DATA
+#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT              0x00000000
+
+// CP_ME_VS_FETCH_DONE_SRC
+#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000
+
+// CP_ME_VS_FETCH_DONE_ADDR
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000
+#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002
+
+// CP_ME_VS_FETCH_DONE_DATA
+#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000
+
+// CP_INT_CNTL
+#define CP_INT_CNTL__SW_INT_MASK__SHIFT                    0x00000013
+#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT           0x00000017
+#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT              0x00000018
+#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT      0x00000019
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT        0x0000001a
+#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT                  0x0000001b
+#define CP_INT_CNTL__IB2_INT_MASK__SHIFT                   0x0000001d
+#define CP_INT_CNTL__IB1_INT_MASK__SHIFT                   0x0000001e
+#define CP_INT_CNTL__RB_INT_MASK__SHIFT                    0x0000001f
+
+// CP_INT_STATUS
+#define CP_INT_STATUS__SW_INT_STAT__SHIFT                  0x00000013
+#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT         0x00000017
+#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT            0x00000018
+#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT    0x00000019
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT      0x0000001a
+#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT                0x0000001b
+#define CP_INT_STATUS__IB2_INT_STAT__SHIFT                 0x0000001d
+#define CP_INT_STATUS__IB1_INT_STAT__SHIFT                 0x0000001e
+#define CP_INT_STATUS__RB_INT_STAT__SHIFT                  0x0000001f
+
+// CP_INT_ACK
+#define CP_INT_ACK__SW_INT_ACK__SHIFT                      0x00000013
+#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT             0x00000017
+#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT                0x00000018
+#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT        0x00000019
+#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT          0x0000001a
+#define CP_INT_ACK__IB_ERROR_ACK__SHIFT                    0x0000001b
+#define CP_INT_ACK__IB2_INT_ACK__SHIFT                     0x0000001d
+#define CP_INT_ACK__IB1_INT_ACK__SHIFT                     0x0000001e
+#define CP_INT_ACK__RB_INT_ACK__SHIFT                      0x0000001f
+
+// CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT               0x00000000
+
+// CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT               0x00000000
+
+// CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT              0x00000000
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT        0x00000008
+
+// CP_PERFCOUNTER_SELECT
+#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT        0x00000000
+
+// CP_PERFCOUNTER_LO
+#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT             0x00000000
+
+// CP_PERFCOUNTER_HI
+#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT             0x00000000
+
+// CP_BIN_MASK_LO
+#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT                 0x00000000
+
+// CP_BIN_MASK_HI
+#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT                 0x00000000
+
+// CP_BIN_SELECT_LO
+#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT             0x00000000
+
+// CP_BIN_SELECT_HI
+#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT             0x00000000
+
+// CP_NV_FLAGS_0
+#define CP_NV_FLAGS_0__DISCARD_0__SHIFT                    0x00000000
+#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT                   0x00000001
+#define CP_NV_FLAGS_0__DISCARD_1__SHIFT                    0x00000002
+#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT                   0x00000003
+#define CP_NV_FLAGS_0__DISCARD_2__SHIFT                    0x00000004
+#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT                   0x00000005
+#define CP_NV_FLAGS_0__DISCARD_3__SHIFT                    0x00000006
+#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT                   0x00000007
+#define CP_NV_FLAGS_0__DISCARD_4__SHIFT                    0x00000008
+#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT                   0x00000009
+#define CP_NV_FLAGS_0__DISCARD_5__SHIFT                    0x0000000a
+#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT                   0x0000000b
+#define CP_NV_FLAGS_0__DISCARD_6__SHIFT                    0x0000000c
+#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT                   0x0000000d
+#define CP_NV_FLAGS_0__DISCARD_7__SHIFT                    0x0000000e
+#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT                   0x0000000f
+#define CP_NV_FLAGS_0__DISCARD_8__SHIFT                    0x00000010
+#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT                   0x00000011
+#define CP_NV_FLAGS_0__DISCARD_9__SHIFT                    0x00000012
+#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT                   0x00000013
+#define CP_NV_FLAGS_0__DISCARD_10__SHIFT                   0x00000014
+#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT                  0x00000015
+#define CP_NV_FLAGS_0__DISCARD_11__SHIFT                   0x00000016
+#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT                  0x00000017
+#define CP_NV_FLAGS_0__DISCARD_12__SHIFT                   0x00000018
+#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT                  0x00000019
+#define CP_NV_FLAGS_0__DISCARD_13__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_0__DISCARD_14__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_0__DISCARD_15__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_1
+#define CP_NV_FLAGS_1__DISCARD_16__SHIFT                   0x00000000
+#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT                  0x00000001
+#define CP_NV_FLAGS_1__DISCARD_17__SHIFT                   0x00000002
+#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT                  0x00000003
+#define CP_NV_FLAGS_1__DISCARD_18__SHIFT                   0x00000004
+#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT                  0x00000005
+#define CP_NV_FLAGS_1__DISCARD_19__SHIFT                   0x00000006
+#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT                  0x00000007
+#define CP_NV_FLAGS_1__DISCARD_20__SHIFT                   0x00000008
+#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT                  0x00000009
+#define CP_NV_FLAGS_1__DISCARD_21__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_1__DISCARD_22__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_1__DISCARD_23__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_1__DISCARD_24__SHIFT                   0x00000010
+#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT                  0x00000011
+#define CP_NV_FLAGS_1__DISCARD_25__SHIFT                   0x00000012
+#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT                  0x00000013
+#define CP_NV_FLAGS_1__DISCARD_26__SHIFT                   0x00000014
+#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT                  0x00000015
+#define CP_NV_FLAGS_1__DISCARD_27__SHIFT                   0x00000016
+#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT                  0x00000017
+#define CP_NV_FLAGS_1__DISCARD_28__SHIFT                   0x00000018
+#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT                  0x00000019
+#define CP_NV_FLAGS_1__DISCARD_29__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_1__DISCARD_30__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_1__DISCARD_31__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_2
+#define CP_NV_FLAGS_2__DISCARD_32__SHIFT                   0x00000000
+#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT                  0x00000001
+#define CP_NV_FLAGS_2__DISCARD_33__SHIFT                   0x00000002
+#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT                  0x00000003
+#define CP_NV_FLAGS_2__DISCARD_34__SHIFT                   0x00000004
+#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT                  0x00000005
+#define CP_NV_FLAGS_2__DISCARD_35__SHIFT                   0x00000006
+#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT                  0x00000007
+#define CP_NV_FLAGS_2__DISCARD_36__SHIFT                   0x00000008
+#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT                  0x00000009
+#define CP_NV_FLAGS_2__DISCARD_37__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_2__DISCARD_38__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_2__DISCARD_39__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_2__DISCARD_40__SHIFT                   0x00000010
+#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT                  0x00000011
+#define CP_NV_FLAGS_2__DISCARD_41__SHIFT                   0x00000012
+#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT                  0x00000013
+#define CP_NV_FLAGS_2__DISCARD_42__SHIFT                   0x00000014
+#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT                  0x00000015
+#define CP_NV_FLAGS_2__DISCARD_43__SHIFT                   0x00000016
+#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT                  0x00000017
+#define CP_NV_FLAGS_2__DISCARD_44__SHIFT                   0x00000018
+#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT                  0x00000019
+#define CP_NV_FLAGS_2__DISCARD_45__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_2__DISCARD_46__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_2__DISCARD_47__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT                  0x0000001f
+
+// CP_NV_FLAGS_3
+#define CP_NV_FLAGS_3__DISCARD_48__SHIFT                   0x00000000
+#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT                  0x00000001
+#define CP_NV_FLAGS_3__DISCARD_49__SHIFT                   0x00000002
+#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT                  0x00000003
+#define CP_NV_FLAGS_3__DISCARD_50__SHIFT                   0x00000004
+#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT                  0x00000005
+#define CP_NV_FLAGS_3__DISCARD_51__SHIFT                   0x00000006
+#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT                  0x00000007
+#define CP_NV_FLAGS_3__DISCARD_52__SHIFT                   0x00000008
+#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT                  0x00000009
+#define CP_NV_FLAGS_3__DISCARD_53__SHIFT                   0x0000000a
+#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT                  0x0000000b
+#define CP_NV_FLAGS_3__DISCARD_54__SHIFT                   0x0000000c
+#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT                  0x0000000d
+#define CP_NV_FLAGS_3__DISCARD_55__SHIFT                   0x0000000e
+#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT                  0x0000000f
+#define CP_NV_FLAGS_3__DISCARD_56__SHIFT                   0x00000010
+#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT                  0x00000011
+#define CP_NV_FLAGS_3__DISCARD_57__SHIFT                   0x00000012
+#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT                  0x00000013
+#define CP_NV_FLAGS_3__DISCARD_58__SHIFT                   0x00000014
+#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT                  0x00000015
+#define CP_NV_FLAGS_3__DISCARD_59__SHIFT                   0x00000016
+#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT                  0x00000017
+#define CP_NV_FLAGS_3__DISCARD_60__SHIFT                   0x00000018
+#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT                  0x00000019
+#define CP_NV_FLAGS_3__DISCARD_61__SHIFT                   0x0000001a
+#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT                  0x0000001b
+#define CP_NV_FLAGS_3__DISCARD_62__SHIFT                   0x0000001c
+#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT                  0x0000001d
+#define CP_NV_FLAGS_3__DISCARD_63__SHIFT                   0x0000001e
+#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT                  0x0000001f
+
+// CP_STATE_DEBUG_INDEX
+#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT     0x00000000
+
+// CP_STATE_DEBUG_DATA
+#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT       0x00000000
+
+// CP_PROG_COUNTER
+#define CP_PROG_COUNTER__COUNTER__SHIFT                    0x00000000
+
+// CP_STAT
+#define CP_STAT__MIU_WR_BUSY__SHIFT                        0x00000000
+#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT                    0x00000001
+#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT                 0x00000002
+#define CP_STAT__RBIU_BUSY__SHIFT                          0x00000003
+#define CP_STAT__RCIU_BUSY__SHIFT                          0x00000004
+#define CP_STAT__CSF_RING_BUSY__SHIFT                      0x00000005
+#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT                 0x00000006
+#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT                 0x00000007
+#define CP_STAT__CSF_ST_BUSY__SHIFT                        0x00000009
+#define CP_STAT__CSF_BUSY__SHIFT                           0x0000000a
+#define CP_STAT__RING_QUEUE_BUSY__SHIFT                    0x0000000b
+#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT               0x0000000c
+#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT               0x0000000d
+#define CP_STAT__ST_QUEUE_BUSY__SHIFT                      0x00000010
+#define CP_STAT__PFP_BUSY__SHIFT                           0x00000011
+#define CP_STAT__MEQ_RING_BUSY__SHIFT                      0x00000012
+#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT                 0x00000013
+#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT                 0x00000014
+#define CP_STAT__MIU_WC_STALL__SHIFT                       0x00000015
+#define CP_STAT__CP_NRT_BUSY__SHIFT                        0x00000016
+#define CP_STAT___3D_BUSY__SHIFT                           0x00000017
+#define CP_STAT__ME_BUSY__SHIFT                            0x0000001a
+#define CP_STAT__ME_WC_BUSY__SHIFT                         0x0000001d
+#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT            0x0000001e
+#define CP_STAT__CP_BUSY__SHIFT                            0x0000001f
+
+// BIOS_0_SCRATCH
+#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_1_SCRATCH
+#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_2_SCRATCH
+#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_3_SCRATCH
+#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_4_SCRATCH
+#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_5_SCRATCH
+#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_6_SCRATCH
+#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_7_SCRATCH
+#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_8_SCRATCH
+#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_9_SCRATCH
+#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT                0x00000000
+
+// BIOS_10_SCRATCH
+#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_11_SCRATCH
+#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_12_SCRATCH
+#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_13_SCRATCH
+#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_14_SCRATCH
+#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// BIOS_15_SCRATCH
+#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT               0x00000000
+
+// COHER_SIZE_PM4
+#define COHER_SIZE_PM4__SIZE__SHIFT                        0x00000000
+
+// COHER_BASE_PM4
+#define COHER_BASE_PM4__BASE__SHIFT                        0x00000000
+
+// COHER_STATUS_PM4
+#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT         0x00000000
+#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT     0x00000008
+#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT           0x00000009
+#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT           0x0000000a
+#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT           0x0000000b
+#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT           0x0000000c
+#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT           0x0000000d
+#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT           0x0000000e
+#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT           0x0000000f
+#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT           0x00000010
+#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT         0x00000011
+#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT             0x00000019
+#define COHER_STATUS_PM4__STATUS__SHIFT                    0x0000001f
+
+// COHER_SIZE_HOST
+#define COHER_SIZE_HOST__SIZE__SHIFT                       0x00000000
+
+// COHER_BASE_HOST
+#define COHER_BASE_HOST__BASE__SHIFT                       0x00000000
+
+// COHER_STATUS_HOST
+#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT        0x00000000
+#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT    0x00000008
+#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT          0x00000009
+#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT          0x0000000a
+#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT          0x0000000b
+#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT          0x0000000c
+#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT          0x0000000d
+#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT          0x0000000e
+#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT          0x0000000f
+#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT          0x00000010
+#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT        0x00000011
+#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT            0x00000019
+#define COHER_STATUS_HOST__STATUS__SHIFT                   0x0000001f
+
+// COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_4
+#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_5
+#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_6
+#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT              0x0000000c
+
+// COHER_DEST_BASE_7
+#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT              0x0000000c
+
+// RB_SURFACE_INFO
+#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT              0x00000000
+#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT               0x0000000e
+
+// RB_COLOR_INFO
+#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT                 0x00000000
+#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT             0x00000004
+#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT                 0x00000006
+#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT                 0x00000007
+#define RB_COLOR_INFO__COLOR_SWAP__SHIFT                   0x00000009
+#define RB_COLOR_INFO__COLOR_BASE__SHIFT                   0x0000000c
+
+// RB_DEPTH_INFO
+#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT                 0x00000000
+#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT                   0x0000000c
+
+// RB_STENCILREFMASK
+#define RB_STENCILREFMASK__STENCILREF__SHIFT               0x00000000
+#define RB_STENCILREFMASK__STENCILMASK__SHIFT              0x00000008
+#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT         0x00000010
+#define RB_STENCILREFMASK__RESERVED0__SHIFT                0x00000018
+#define RB_STENCILREFMASK__RESERVED1__SHIFT                0x00000019
+
+// RB_ALPHA_REF
+#define RB_ALPHA_REF__ALPHA_REF__SHIFT                     0x00000000
+
+// RB_COLOR_MASK
+#define RB_COLOR_MASK__WRITE_RED__SHIFT                    0x00000000
+#define RB_COLOR_MASK__WRITE_GREEN__SHIFT                  0x00000001
+#define RB_COLOR_MASK__WRITE_BLUE__SHIFT                   0x00000002
+#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT                  0x00000003
+#define RB_COLOR_MASK__RESERVED2__SHIFT                    0x00000004
+#define RB_COLOR_MASK__RESERVED3__SHIFT                    0x00000005
+
+// RB_BLEND_RED
+#define RB_BLEND_RED__BLEND_RED__SHIFT                     0x00000000
+
+// RB_BLEND_GREEN
+#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT                 0x00000000
+
+// RB_BLEND_BLUE
+#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT                   0x00000000
+
+// RB_BLEND_ALPHA
+#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                 0x00000000
+
+// RB_FOG_COLOR
+#define RB_FOG_COLOR__FOG_RED__SHIFT                       0x00000000
+#define RB_FOG_COLOR__FOG_GREEN__SHIFT                     0x00000008
+#define RB_FOG_COLOR__FOG_BLUE__SHIFT                      0x00000010
+
+// RB_STENCILREFMASK_BF
+#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT         0x00000000
+#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT        0x00000008
+#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT   0x00000010
+#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT             0x00000018
+#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT             0x00000019
+
+// RB_DEPTHCONTROL
+#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT             0x00000000
+#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT                   0x00000001
+#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT             0x00000002
+#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT             0x00000003
+#define RB_DEPTHCONTROL__ZFUNC__SHIFT                      0x00000004
+#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT            0x00000007
+#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT                0x00000008
+#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT                0x0000000b
+#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT               0x0000000e
+#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT               0x00000011
+#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT             0x00000014
+#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT             0x00000017
+#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT            0x0000001a
+#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT            0x0000001d
+
+// RB_BLENDCONTROL
+#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT             0x00000000
+#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT             0x00000005
+#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT            0x00000008
+#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT             0x00000010
+#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT             0x00000015
+#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT            0x00000018
+#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT         0x0000001d
+#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT                0x0000001e
+
+// RB_COLORCONTROL
+#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT                 0x00000000
+#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT          0x00000003
+#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT       0x00000004
+#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT              0x00000005
+#define RB_COLORCONTROL__FOG_ENABLE__SHIFT                 0x00000006
+#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT             0x00000007
+#define RB_COLORCONTROL__ROP_CODE__SHIFT                   0x00000008
+#define RB_COLORCONTROL__DITHER_MODE__SHIFT                0x0000000c
+#define RB_COLORCONTROL__DITHER_TYPE__SHIFT                0x0000000e
+#define RB_COLORCONTROL__PIXEL_FOG__SHIFT                  0x00000010
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT      0x00000018
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT      0x0000001a
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT      0x0000001c
+#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT      0x0000001e
+
+// RB_MODECONTROL
+#define RB_MODECONTROL__EDRAM_MODE__SHIFT                  0x00000000
+
+// RB_COLOR_DEST_MASK
+#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT         0x00000000
+
+// RB_COPY_CONTROL
+#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT         0x00000000
+#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT         0x00000003
+#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT                 0x00000004
+
+// RB_COPY_DEST_BASE
+#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT           0x0000000c
+
+// RB_COPY_DEST_PITCH
+#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT         0x00000000
+
+// RB_COPY_DEST_INFO
+#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT         0x00000000
+#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT         0x00000003
+#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT         0x00000004
+#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT           0x00000008
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT    0x0000000a
+#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT    0x0000000c
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT      0x0000000e
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT    0x0000000f
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT     0x00000010
+#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT    0x00000011
+
+// RB_COPY_DEST_PIXEL_OFFSET
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT         0x00000000
+#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT         0x0000000d
+
+// RB_DEPTH_CLEAR
+#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                 0x00000000
+
+// RB_SAMPLE_COUNT_CTL
+#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT     0x00000000
+#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT      0x00000001
+
+// RB_SAMPLE_COUNT_ADDR
+#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT     0x00000000
+
+// RB_BC_CONTROL
+#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT     0x00000000
+#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT         0x00000001
+#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT            0x00000003
+#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004
+#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT    0x00000005
+#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT    0x00000006
+#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT           0x00000007
+#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT            0x00000008
+#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT            0x0000000e
+#define RB_BC_CONTROL__CRC_MODE__SHIFT                     0x0000000f
+#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT      0x00000010
+#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT                0x00000011
+#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT             0x00000012
+#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT    0x00000016
+#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT        0x00000017
+#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT    0x0000001b
+#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d
+#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT                   0x0000001e
+#define RB_BC_CONTROL__RESERVED6__SHIFT                    0x0000001f
+
+// RB_EDRAM_INFO
+#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT                   0x00000000
+#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT           0x00000004
+#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT                  0x0000000e
+
+// RB_CRC_RD_PORT
+#define RB_CRC_RD_PORT__CRC_DATA__SHIFT                    0x00000000
+
+// RB_CRC_CONTROL
+#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT              0x00000000
+
+// RB_CRC_MASK
+#define RB_CRC_MASK__CRC_MASK__SHIFT                       0x00000000
+
+// RB_PERFCOUNTER0_SELECT
+#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT            0x00000000
+
+// RB_PERFCOUNTER0_LOW
+#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT             0x00000000
+
+// RB_PERFCOUNTER0_HI
+#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT              0x00000000
+
+// RB_TOTAL_SAMPLES
+#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT             0x00000000
+
+// RB_ZPASS_SAMPLES
+#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT             0x00000000
+
+// RB_ZFAIL_SAMPLES
+#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_SFAIL_SAMPLES
+#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT             0x00000000
+
+// RB_DEBUG_0
+#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT           0x00000000
+#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT           0x00000001
+#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT           0x00000002
+#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT           0x00000003
+#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT          0x00000004
+#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT          0x00000005
+#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT                   0x00000006
+#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT                   0x00000007
+#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT                   0x00000008
+#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT                   0x00000009
+#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT          0x0000000a
+#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT          0x0000000b
+#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT          0x0000000c
+#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT          0x0000000d
+#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT              0x0000000e
+#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT                   0x00000010
+#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT                   0x00000011
+#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT                   0x00000012
+#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT                   0x00000013
+#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT            0x00000014
+#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT            0x00000015
+#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT            0x00000016
+#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT            0x00000017
+#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT         0x00000018
+#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT         0x00000019
+#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT                   0x0000001a
+#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT                   0x0000001b
+#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT                  0x0000001c
+#define RB_DEBUG_0__C_REQ_FULL__SHIFT                      0x0000001d
+#define RB_DEBUG_0__C_MASK_FULL__SHIFT                     0x0000001e
+#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT                 0x0000001f
+
+// RB_DEBUG_1
+#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT              0x00000000
+#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT              0x00000001
+#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT              0x00000002
+#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT              0x00000003
+#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT         0x00000004
+#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT         0x00000005
+#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT                  0x00000006
+#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT                  0x00000007
+#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT                  0x00000008
+#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT                  0x00000009
+#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT         0x0000000a
+#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT         0x0000000b
+#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT         0x0000000c
+#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT         0x0000000d
+#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT             0x0000000e
+#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT             0x0000000f
+#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT                  0x00000010
+#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT                  0x00000011
+#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT              0x00000012
+#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT              0x00000013
+#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT           0x00000014
+#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT           0x00000017
+#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT        0x00000018
+#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT        0x00000019
+#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT                  0x0000001a
+#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT                  0x0000001b
+#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT                 0x0000001c
+#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT                     0x0000001d
+#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT                0x0000001f
+
+// RB_DEBUG_2
+#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT                 0x00000000
+#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT               0x00000004
+#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT                 0x0000000b
+#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT               0x0000000c
+#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT              0x0000000d
+#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT                 0x0000000e
+#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT              0x0000000f
+#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT              0x00000010
+#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT                    0x00000011
+#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT                    0x00000012
+#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT                     0x00000013
+#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT                     0x00000014
+#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT                     0x00000015
+#define RB_DEBUG_2__Z_TILE_FULL__SHIFT                     0x00000016
+#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT                0x00000017
+#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT             0x00000018
+#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT             0x00000019
+#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT                   0x0000001a
+#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT                   0x0000001b
+#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT                    0x0000001c
+#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT                    0x0000001d
+#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT                    0x0000001e
+#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT                    0x0000001f
+
+// RB_DEBUG_3
+#define RB_DEBUG_3__ACCUM_VALID__SHIFT                     0x00000000
+#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT                  0x00000004
+#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT         0x00000008
+#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT           0x0000000e
+#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT             0x0000000f
+#define RB_DEBUG_3__SHD_FULL__SHIFT                        0x00000013
+#define RB_DEBUG_3__SHD_EMPTY__SHIFT                       0x00000014
+#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT           0x00000015
+#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT           0x00000016
+#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT            0x00000017
+#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT            0x00000018
+#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT                0x00000019
+#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT                0x0000001a
+#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT                 0x0000001b
+#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT                 0x0000001c
+
+// RB_DEBUG_4
+#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT             0x00000000
+#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT             0x00000001
+#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT           0x00000002
+#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT           0x00000003
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT           0x00000004
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT          0x00000005
+#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT            0x00000006
+#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT           0x00000007
+#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT     0x00000008
+#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT             0x00000009
+
+// RB_FLAG_CONTROL
+#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT           0x00000000
+
+// RB_BC_SPARES
+#define RB_BC_SPARES__RESERVED__SHIFT                      0x00000000
+
+// BC_DUMMY_CRAYRB_ENUMS
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT   0x00000009
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b
+#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d
+
+// BC_DUMMY_CRAYRB_MOREENUMS
+#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000
+
+#endif
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h
new file mode 100644
index 00000000000..21de35591e7
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h
@@ -0,0 +1,52433 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_CP_FIDDLE_H)
+#define _CP_FIDDLE_H
+
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * CP_RB_BASE struct
+ */
+
+#define CP_RB_BASE_RB_BASE_SIZE        27
+
+#define CP_RB_BASE_RB_BASE_SHIFT       5
+
+#define CP_RB_BASE_RB_BASE_MASK        0xffffffe0
+
+#define CP_RB_BASE_MASK \
+     (CP_RB_BASE_RB_BASE_MASK)
+
+#define CP_RB_BASE(rb_base) \
+     ((rb_base << CP_RB_BASE_RB_BASE_SHIFT))
+
+#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \
+     ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT)
+
+#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \
+     cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int                                : 5;
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+     } cp_rb_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_base_t {
+          unsigned int rb_base                        : CP_RB_BASE_RB_BASE_SIZE;
+          unsigned int                                : 5;
+     } cp_rb_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_base_t f;
+} cp_rb_base_u;
+
+
+/*
+ * CP_RB_CNTL struct
+ */
+
+#define CP_RB_CNTL_RB_BUFSZ_SIZE       6
+#define CP_RB_CNTL_RB_BLKSZ_SIZE       6
+#define CP_RB_CNTL_BUF_SWAP_SIZE       2
+#define CP_RB_CNTL_RB_POLL_EN_SIZE     1
+#define CP_RB_CNTL_RB_NO_UPDATE_SIZE   1
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
+
+#define CP_RB_CNTL_RB_BUFSZ_SHIFT      0
+#define CP_RB_CNTL_RB_BLKSZ_SHIFT      8
+#define CP_RB_CNTL_BUF_SWAP_SHIFT      16
+#define CP_RB_CNTL_RB_POLL_EN_SHIFT    20
+#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT  27
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31
+
+#define CP_RB_CNTL_RB_BUFSZ_MASK       0x0000003f
+#define CP_RB_CNTL_RB_BLKSZ_MASK       0x00003f00
+#define CP_RB_CNTL_BUF_SWAP_MASK       0x00030000
+#define CP_RB_CNTL_RB_POLL_EN_MASK     0x00100000
+#define CP_RB_CNTL_RB_NO_UPDATE_MASK   0x08000000
+#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000
+
+#define CP_RB_CNTL_MASK \
+     (CP_RB_CNTL_RB_BUFSZ_MASK | \
+      CP_RB_CNTL_RB_BLKSZ_MASK | \
+      CP_RB_CNTL_BUF_SWAP_MASK | \
+      CP_RB_CNTL_RB_POLL_EN_MASK | \
+      CP_RB_CNTL_RB_NO_UPDATE_MASK | \
+      CP_RB_CNTL_RB_RPTR_WR_ENA_MASK)
+
+#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \
+     ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \
+      (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \
+      (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \
+      (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \
+      (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \
+      (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT))
+
+#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \
+     ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT)
+#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT)
+#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT)
+#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT)
+#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT)
+#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \
+     cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+     } cp_rb_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_cntl_t {
+          unsigned int rb_rptr_wr_ena                 : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
+          unsigned int                                : 3;
+          unsigned int rb_no_update                   : CP_RB_CNTL_RB_NO_UPDATE_SIZE;
+          unsigned int                                : 6;
+          unsigned int rb_poll_en                     : CP_RB_CNTL_RB_POLL_EN_SIZE;
+          unsigned int                                : 2;
+          unsigned int buf_swap                       : CP_RB_CNTL_BUF_SWAP_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_blksz                       : CP_RB_CNTL_RB_BLKSZ_SIZE;
+          unsigned int                                : 2;
+          unsigned int rb_bufsz                       : CP_RB_CNTL_RB_BUFSZ_SIZE;
+     } cp_rb_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_cntl_t f;
+} cp_rb_cntl_u;
+
+
+/*
+ * CP_RB_RPTR_ADDR struct
+ */
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2
+
+#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003
+#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc
+
+#define CP_RB_RPTR_ADDR_MASK \
+     (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \
+      CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK)
+
+#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \
+     ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \
+      (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT))
+
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \
+     ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT)
+#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \
+     cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_addr_t {
+          unsigned int rb_rptr_addr                   : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE;
+          unsigned int rb_rptr_swap                   : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE;
+     } cp_rb_rptr_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_addr_t f;
+} cp_rb_rptr_addr_u;
+
+
+/*
+ * CP_RB_RPTR struct
+ */
+
+#define CP_RB_RPTR_RB_RPTR_SIZE        20
+
+#define CP_RB_RPTR_RB_RPTR_SHIFT       0
+
+#define CP_RB_RPTR_RB_RPTR_MASK        0x000fffff
+
+#define CP_RB_RPTR_MASK \
+     (CP_RB_RPTR_RB_RPTR_MASK)
+
+#define CP_RB_RPTR(rb_rptr) \
+     ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT))
+
+#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \
+     ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \
+     cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr                        : CP_RB_RPTR_RB_RPTR_SIZE;
+     } cp_rb_rptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_t f;
+} cp_rb_rptr_u;
+
+
+/*
+ * CP_RB_RPTR_WR struct
+ */
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE  20
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0
+
+#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK  0x000fffff
+
+#define CP_RB_RPTR_WR_MASK \
+     (CP_RB_RPTR_WR_RB_RPTR_WR_MASK)
+
+#define CP_RB_RPTR_WR(rb_rptr_wr) \
+     ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT))
+
+#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \
+     ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \
+     cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_rptr_wr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_rptr_wr_t {
+          unsigned int                                : 12;
+          unsigned int rb_rptr_wr                     : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE;
+     } cp_rb_rptr_wr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_rptr_wr_t f;
+} cp_rb_rptr_wr_u;
+
+
+/*
+ * CP_RB_WPTR struct
+ */
+
+#define CP_RB_WPTR_RB_WPTR_SIZE        20
+
+#define CP_RB_WPTR_RB_WPTR_SHIFT       0
+
+#define CP_RB_WPTR_RB_WPTR_MASK        0x000fffff
+
+#define CP_RB_WPTR_MASK \
+     (CP_RB_WPTR_RB_WPTR_MASK)
+
+#define CP_RB_WPTR(rb_wptr) \
+     ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT))
+
+#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \
+     ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \
+     cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+          unsigned int                                : 12;
+     } cp_rb_wptr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_t {
+          unsigned int                                : 12;
+          unsigned int rb_wptr                        : CP_RB_WPTR_RB_WPTR_SIZE;
+     } cp_rb_wptr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_t f;
+} cp_rb_wptr_u;
+
+
+/*
+ * CP_RB_WPTR_DELAY struct
+ */
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28
+
+#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff
+#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000
+
+#define CP_RB_WPTR_DELAY_MASK \
+     (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \
+      CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK)
+
+#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \
+     ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \
+      (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT))
+
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \
+     ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT)
+#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \
+     cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_delay_t {
+          unsigned int pre_write_limit                : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE;
+          unsigned int pre_write_timer                : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE;
+     } cp_rb_wptr_delay_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_delay_t f;
+} cp_rb_wptr_delay_u;
+
+
+/*
+ * CP_RB_WPTR_BASE struct
+ */
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2
+
+#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003
+#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc
+
+#define CP_RB_WPTR_BASE_MASK \
+     (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \
+      CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK)
+
+#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \
+     ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \
+      (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT))
+
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \
+     ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT)
+#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \
+     cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+     } cp_rb_wptr_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_rb_wptr_base_t {
+          unsigned int rb_wptr_base                   : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE;
+          unsigned int rb_wptr_swap                   : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE;
+     } cp_rb_wptr_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_rb_wptr_base_t f;
+} cp_rb_wptr_base_u;
+
+
+/*
+ * CP_IB1_BASE struct
+ */
+
+#define CP_IB1_BASE_IB1_BASE_SIZE      30
+
+#define CP_IB1_BASE_IB1_BASE_SHIFT     2
+
+#define CP_IB1_BASE_IB1_BASE_MASK      0xfffffffc
+
+#define CP_IB1_BASE_MASK \
+     (CP_IB1_BASE_IB1_BASE_MASK)
+
+#define CP_IB1_BASE(ib1_base) \
+     ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT))
+
+#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \
+     ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \
+     cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int                                : 2;
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+     } cp_ib1_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_base_t {
+          unsigned int ib1_base                       : CP_IB1_BASE_IB1_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib1_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_base_t f;
+} cp_ib1_base_u;
+
+
+/*
+ * CP_IB1_BUFSZ struct
+ */
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE    20
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT   0
+
+#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK    0x000fffff
+
+#define CP_IB1_BUFSZ_MASK \
+     (CP_IB1_BUFSZ_IB1_BUFSZ_MASK)
+
+#define CP_IB1_BUFSZ(ib1_bufsz) \
+     ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT))
+
+#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \
+     ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \
+     cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib1_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib1_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib1_bufsz                      : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE;
+     } cp_ib1_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib1_bufsz_t f;
+} cp_ib1_bufsz_u;
+
+
+/*
+ * CP_IB2_BASE struct
+ */
+
+#define CP_IB2_BASE_IB2_BASE_SIZE      30
+
+#define CP_IB2_BASE_IB2_BASE_SHIFT     2
+
+#define CP_IB2_BASE_IB2_BASE_MASK      0xfffffffc
+
+#define CP_IB2_BASE_MASK \
+     (CP_IB2_BASE_IB2_BASE_MASK)
+
+#define CP_IB2_BASE(ib2_base) \
+     ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT))
+
+#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \
+     ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \
+     cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int                                : 2;
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+     } cp_ib2_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_base_t {
+          unsigned int ib2_base                       : CP_IB2_BASE_IB2_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_ib2_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_base_t f;
+} cp_ib2_base_u;
+
+
+/*
+ * CP_IB2_BUFSZ struct
+ */
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE    20
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT   0
+
+#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK    0x000fffff
+
+#define CP_IB2_BUFSZ_MASK \
+     (CP_IB2_BUFSZ_IB2_BUFSZ_MASK)
+
+#define CP_IB2_BUFSZ(ib2_bufsz) \
+     ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT))
+
+#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \
+     ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \
+     cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_ib2_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_ib2_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int ib2_bufsz                      : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE;
+     } cp_ib2_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_ib2_bufsz_t f;
+} cp_ib2_bufsz_u;
+
+
+/*
+ * CP_ST_BASE struct
+ */
+
+#define CP_ST_BASE_ST_BASE_SIZE        30
+
+#define CP_ST_BASE_ST_BASE_SHIFT       2
+
+#define CP_ST_BASE_ST_BASE_MASK        0xfffffffc
+
+#define CP_ST_BASE_MASK \
+     (CP_ST_BASE_ST_BASE_MASK)
+
+#define CP_ST_BASE(st_base) \
+     ((st_base << CP_ST_BASE_ST_BASE_SHIFT))
+
+#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \
+     ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT)
+
+#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \
+     cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int                                : 2;
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+     } cp_st_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_base_t {
+          unsigned int st_base                        : CP_ST_BASE_ST_BASE_SIZE;
+          unsigned int                                : 2;
+     } cp_st_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_base_t f;
+} cp_st_base_u;
+
+
+/*
+ * CP_ST_BUFSZ struct
+ */
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SIZE      20
+
+#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT     0
+
+#define CP_ST_BUFSZ_ST_BUFSZ_MASK      0x000fffff
+
+#define CP_ST_BUFSZ_MASK \
+     (CP_ST_BUFSZ_ST_BUFSZ_MASK)
+
+#define CP_ST_BUFSZ(st_bufsz) \
+     ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT))
+
+#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \
+     ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \
+     cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+          unsigned int                                : 12;
+     } cp_st_bufsz_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_st_bufsz_t {
+          unsigned int                                : 12;
+          unsigned int st_bufsz                       : CP_ST_BUFSZ_ST_BUFSZ_SIZE;
+     } cp_st_bufsz_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_st_bufsz_t f;
+} cp_st_bufsz_u;
+
+
+/*
+ * CP_QUEUE_THRESHOLDS struct
+ */
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16
+
+#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f
+#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00
+#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000
+
+#define CP_QUEUE_THRESHOLDS_MASK \
+     (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \
+      CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK)
+
+#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \
+     ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \
+      (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \
+      (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT))
+
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \
+     ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT)
+#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \
+     cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 12;
+     } cp_queue_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_queue_thresholds_t {
+          unsigned int                                : 12;
+          unsigned int csq_st_start                   : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib2_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE;
+          unsigned int                                : 4;
+          unsigned int csq_ib1_start                  : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE;
+     } cp_queue_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_queue_thresholds_t f;
+} cp_queue_thresholds_u;
+
+
+/*
+ * CP_MEQ_THRESHOLDS struct
+ */
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5
+#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16
+#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24
+
+#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000
+#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000
+
+#define CP_MEQ_THRESHOLDS_MASK \
+     (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \
+      CP_MEQ_THRESHOLDS_ROQ_END_MASK)
+
+#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \
+     ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \
+      (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT))
+
+#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \
+     ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT)
+#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \
+     cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 16;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+     } cp_meq_thresholds_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_thresholds_t {
+          unsigned int                                : 3;
+          unsigned int roq_end                        : CP_MEQ_THRESHOLDS_ROQ_END_SIZE;
+          unsigned int                                : 3;
+          unsigned int meq_end                        : CP_MEQ_THRESHOLDS_MEQ_END_SIZE;
+          unsigned int                                : 16;
+     } cp_meq_thresholds_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_thresholds_t f;
+} cp_meq_thresholds_u;
+
+
+/*
+ * CP_CSQ_AVAIL struct
+ */
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE  7
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE  7
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16
+
+#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f
+#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK  0x00007f00
+#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK  0x007f0000
+
+#define CP_CSQ_AVAIL_MASK \
+     (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \
+      CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK)
+
+#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \
+     ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \
+      (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \
+      (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT))
+
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \
+     ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT)
+#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \
+     cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_avail_t {
+          unsigned int                                : 9;
+          unsigned int csq_cnt_ib2                    : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ib1                    : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE;
+          unsigned int                                : 1;
+          unsigned int csq_cnt_ring                   : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE;
+     } cp_csq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_avail_t f;
+} cp_csq_avail_u;
+
+
+/*
+ * CP_STQ_AVAIL struct
+ */
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE   7
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT  0
+
+#define CP_STQ_AVAIL_STQ_CNT_ST_MASK   0x0000007f
+
+#define CP_STQ_AVAIL_MASK \
+     (CP_STQ_AVAIL_STQ_CNT_ST_MASK)
+
+#define CP_STQ_AVAIL(stq_cnt_st) \
+     ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT))
+
+#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \
+     ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \
+     cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+          unsigned int                                : 25;
+     } cp_stq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_avail_t {
+          unsigned int                                : 25;
+          unsigned int stq_cnt_st                     : CP_STQ_AVAIL_STQ_CNT_ST_SIZE;
+     } cp_stq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_avail_t f;
+} cp_stq_avail_u;
+
+
+/*
+ * CP_MEQ_AVAIL struct
+ */
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SIZE      5
+
+#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT     0
+
+#define CP_MEQ_AVAIL_MEQ_CNT_MASK      0x0000001f
+
+#define CP_MEQ_AVAIL_MASK \
+     (CP_MEQ_AVAIL_MEQ_CNT_MASK)
+
+#define CP_MEQ_AVAIL(meq_cnt) \
+     ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT))
+
+#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \
+     ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \
+     cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+          unsigned int                                : 27;
+     } cp_meq_avail_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_avail_t {
+          unsigned int                                : 27;
+          unsigned int meq_cnt                        : CP_MEQ_AVAIL_MEQ_CNT_SIZE;
+     } cp_meq_avail_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_avail_t f;
+} cp_meq_avail_u;
+
+
+/*
+ * CP_CSQ_RB_STAT struct
+ */
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16
+
+#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f
+#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000
+
+#define CP_CSQ_RB_STAT_MASK \
+     (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \
+      CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK)
+
+#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \
+     ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \
+      (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT))
+
+#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \
+     ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT)
+#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \
+     cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_rb_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_rb_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_primary               : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_primary               : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE;
+     } cp_csq_rb_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_rb_stat_t f;
+} cp_csq_rb_stat_u;
+
+
+/*
+ * CP_CSQ_IB1_STAT struct
+ */
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16
+
+#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f
+#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000
+
+#define CP_CSQ_IB1_STAT_MASK \
+     (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \
+      CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK)
+
+#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \
+     ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \
+      (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT))
+
+#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \
+     ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT)
+#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \
+     cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib1_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib1_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect1             : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE;
+     } cp_csq_ib1_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib1_stat_t f;
+} cp_csq_ib1_stat_u;
+
+
+/*
+ * CP_CSQ_IB2_STAT struct
+ */
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16
+
+#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f
+#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000
+
+#define CP_CSQ_IB2_STAT_MASK \
+     (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \
+      CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK)
+
+#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \
+     ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \
+      (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT))
+
+#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \
+     ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT)
+#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \
+     cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+     } cp_csq_ib2_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_csq_ib2_stat_t {
+          unsigned int                                : 9;
+          unsigned int csq_wptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE;
+          unsigned int                                : 9;
+          unsigned int csq_rptr_indirect2             : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE;
+     } cp_csq_ib2_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_csq_ib2_stat_t f;
+} cp_csq_ib2_stat_u;
+
+
+/*
+ * CP_NON_PREFETCH_CNTRS struct
+ */
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8
+
+#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007
+#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700
+
+#define CP_NON_PREFETCH_CNTRS_MASK \
+     (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \
+      CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK)
+
+#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \
+     ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \
+      (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT))
+
+#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \
+     ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT)
+#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \
+     cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 21;
+     } cp_non_prefetch_cntrs_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_non_prefetch_cntrs_t {
+          unsigned int                                : 21;
+          unsigned int ib2_counter                    : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE;
+          unsigned int                                : 5;
+          unsigned int ib1_counter                    : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE;
+     } cp_non_prefetch_cntrs_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_non_prefetch_cntrs_t f;
+} cp_non_prefetch_cntrs_u;
+
+
+/*
+ * CP_STQ_ST_STAT struct
+ */
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16
+
+#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f
+#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000
+
+#define CP_STQ_ST_STAT_MASK \
+     (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \
+      CP_STQ_ST_STAT_STQ_WPTR_ST_MASK)
+
+#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \
+     ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \
+      (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT))
+
+#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \
+     ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT)
+#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \
+     cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+     } cp_stq_st_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stq_st_stat_t {
+          unsigned int                                : 9;
+          unsigned int stq_wptr_st                    : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE;
+          unsigned int                                : 9;
+          unsigned int stq_rptr_st                    : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE;
+     } cp_stq_st_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stq_st_stat_t f;
+} cp_stq_st_stat_u;
+
+
+/*
+ * CP_MEQ_STAT struct
+ */
+
+#define CP_MEQ_STAT_MEQ_RPTR_SIZE      10
+#define CP_MEQ_STAT_MEQ_WPTR_SIZE      10
+
+#define CP_MEQ_STAT_MEQ_RPTR_SHIFT     0
+#define CP_MEQ_STAT_MEQ_WPTR_SHIFT     16
+
+#define CP_MEQ_STAT_MEQ_RPTR_MASK      0x000003ff
+#define CP_MEQ_STAT_MEQ_WPTR_MASK      0x03ff0000
+
+#define CP_MEQ_STAT_MASK \
+     (CP_MEQ_STAT_MEQ_RPTR_MASK | \
+      CP_MEQ_STAT_MEQ_WPTR_MASK)
+
+#define CP_MEQ_STAT(meq_rptr, meq_wptr) \
+     ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \
+      (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT))
+
+#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \
+     ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT)
+#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \
+     cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+     } cp_meq_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_meq_stat_t {
+          unsigned int                                : 6;
+          unsigned int meq_wptr                       : CP_MEQ_STAT_MEQ_WPTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int meq_rptr                       : CP_MEQ_STAT_MEQ_RPTR_SIZE;
+     } cp_meq_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_meq_stat_t f;
+} cp_meq_stat_u;
+
+
+/*
+ * CP_MIU_TAG_STAT struct
+ */
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0
+#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1
+#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2
+#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3
+#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4
+#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5
+#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6
+#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7
+#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8
+#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9
+#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10
+#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11
+#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12
+#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13
+#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14
+#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15
+#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16
+#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31
+
+#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001
+#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002
+#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004
+#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008
+#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010
+#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020
+#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040
+#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080
+#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100
+#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200
+#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400
+#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800
+#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000
+#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000
+#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000
+#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000
+#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000
+#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000
+#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000
+
+#define CP_MIU_TAG_STAT_MASK \
+     (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \
+      CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \
+      CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK)
+
+#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \
+     ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \
+      (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \
+      (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \
+      (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \
+      (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \
+      (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \
+      (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \
+      (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \
+      (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \
+      (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \
+      (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \
+      (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \
+      (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \
+      (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \
+      (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \
+      (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \
+      (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \
+      (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \
+      (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT))
+
+#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \
+     ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT)
+#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \
+     cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int                                : 13;
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+     } cp_miu_tag_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_miu_tag_stat_t {
+          unsigned int invalid_return_tag             : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE;
+          unsigned int                                : 13;
+          unsigned int tag_17_stat                    : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE;
+          unsigned int tag_16_stat                    : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE;
+          unsigned int tag_15_stat                    : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE;
+          unsigned int tag_14_stat                    : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE;
+          unsigned int tag_13_stat                    : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE;
+          unsigned int tag_12_stat                    : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE;
+          unsigned int tag_11_stat                    : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE;
+          unsigned int tag_10_stat                    : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE;
+          unsigned int tag_9_stat                     : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE;
+          unsigned int tag_8_stat                     : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE;
+          unsigned int tag_7_stat                     : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE;
+          unsigned int tag_6_stat                     : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE;
+          unsigned int tag_5_stat                     : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE;
+          unsigned int tag_4_stat                     : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE;
+          unsigned int tag_3_stat                     : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE;
+          unsigned int tag_2_stat                     : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE;
+          unsigned int tag_1_stat                     : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE;
+          unsigned int tag_0_stat                     : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE;
+     } cp_miu_tag_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_miu_tag_stat_t f;
+} cp_miu_tag_stat_u;
+
+
+/*
+ * CP_CMD_INDEX struct
+ */
+
+#define CP_CMD_INDEX_CMD_INDEX_SIZE    7
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2
+
+#define CP_CMD_INDEX_CMD_INDEX_SHIFT   0
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16
+
+#define CP_CMD_INDEX_CMD_INDEX_MASK    0x0000007f
+#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000
+
+#define CP_CMD_INDEX_MASK \
+     (CP_CMD_INDEX_CMD_INDEX_MASK | \
+      CP_CMD_INDEX_CMD_QUEUE_SEL_MASK)
+
+#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \
+     ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \
+      (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT))
+
+#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \
+     ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT)
+#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \
+     cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 14;
+     } cp_cmd_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_index_t {
+          unsigned int                                : 14;
+          unsigned int cmd_queue_sel                  : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE;
+          unsigned int                                : 9;
+          unsigned int cmd_index                      : CP_CMD_INDEX_CMD_INDEX_SIZE;
+     } cp_cmd_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_index_t f;
+} cp_cmd_index_u;
+
+
+/*
+ * CP_CMD_DATA struct
+ */
+
+#define CP_CMD_DATA_CMD_DATA_SIZE      32
+
+#define CP_CMD_DATA_CMD_DATA_SHIFT     0
+
+#define CP_CMD_DATA_CMD_DATA_MASK      0xffffffff
+
+#define CP_CMD_DATA_MASK \
+     (CP_CMD_DATA_CMD_DATA_MASK)
+
+#define CP_CMD_DATA(cmd_data) \
+     ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT))
+
+#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \
+     ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \
+     cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_cmd_data_t {
+          unsigned int cmd_data                       : CP_CMD_DATA_CMD_DATA_SIZE;
+     } cp_cmd_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_cmd_data_t f;
+} cp_cmd_data_u;
+
+
+/*
+ * CP_ME_CNTL struct
+ */
+
+#define CP_ME_CNTL_ME_STATMUX_SIZE     16
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1
+#define CP_ME_CNTL_ME_HALT_SIZE        1
+#define CP_ME_CNTL_ME_BUSY_SIZE        1
+#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE  1
+
+#define CP_ME_CNTL_ME_STATMUX_SHIFT    0
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26
+#define CP_ME_CNTL_ME_HALT_SHIFT       28
+#define CP_ME_CNTL_ME_BUSY_SHIFT       29
+#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31
+
+#define CP_ME_CNTL_ME_STATMUX_MASK     0x0000ffff
+#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000
+#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000
+#define CP_ME_CNTL_ME_HALT_MASK        0x10000000
+#define CP_ME_CNTL_ME_BUSY_MASK        0x20000000
+#define CP_ME_CNTL_PROG_CNT_SIZE_MASK  0x80000000
+
+#define CP_ME_CNTL_MASK \
+     (CP_ME_CNTL_ME_STATMUX_MASK | \
+      CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \
+      CP_ME_CNTL_ME_HALT_MASK | \
+      CP_ME_CNTL_ME_BUSY_MASK | \
+      CP_ME_CNTL_PROG_CNT_SIZE_MASK)
+
+#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \
+     ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \
+      (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \
+      (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \
+      (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \
+      (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT))
+
+#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \
+     ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT)
+#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT)
+#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT)
+#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT)
+#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \
+     cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+          unsigned int                                : 9;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+     } cp_me_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cntl_t {
+          unsigned int prog_cnt_size                  : CP_ME_CNTL_PROG_CNT_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int me_busy                        : CP_ME_CNTL_ME_BUSY_SIZE;
+          unsigned int me_halt                        : CP_ME_CNTL_ME_HALT_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_dealloc_fifo_empty         : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int vtx_dealloc_fifo_empty         : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE;
+          unsigned int                                : 9;
+          unsigned int me_statmux                     : CP_ME_CNTL_ME_STATMUX_SIZE;
+     } cp_me_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cntl_t f;
+} cp_me_cntl_u;
+
+
+/*
+ * CP_ME_STATUS struct
+ */
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0
+
+#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_ME_STATUS_MASK \
+     (CP_ME_STATUS_ME_DEBUG_DATA_MASK)
+
+#define CP_ME_STATUS(me_debug_data) \
+     ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT))
+
+#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \
+     ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \
+     cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_status_t {
+          unsigned int me_debug_data                  : CP_ME_STATUS_ME_DEBUG_DATA_SIZE;
+     } cp_me_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_status_t f;
+} cp_me_status_u;
+
+
+/*
+ * CP_ME_RAM_WADDR struct
+ */
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0
+
+#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_WADDR_MASK \
+     (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK)
+
+#define CP_ME_RAM_WADDR(me_ram_waddr) \
+     ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT))
+
+#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \
+     ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \
+     cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_waddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_waddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_waddr                   : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE;
+     } cp_me_ram_waddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_waddr_t f;
+} cp_me_ram_waddr_u;
+
+
+/*
+ * CP_ME_RAM_RADDR struct
+ */
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0
+
+#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff
+
+#define CP_ME_RAM_RADDR_MASK \
+     (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK)
+
+#define CP_ME_RAM_RADDR(me_ram_raddr) \
+     ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT))
+
+#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \
+     ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \
+     cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+          unsigned int                                : 22;
+     } cp_me_ram_raddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_raddr_t {
+          unsigned int                                : 22;
+          unsigned int me_ram_raddr                   : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE;
+     } cp_me_ram_raddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_raddr_t f;
+} cp_me_ram_raddr_u;
+
+
+/*
+ * CP_ME_RAM_DATA struct
+ */
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0
+
+#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff
+
+#define CP_ME_RAM_DATA_MASK \
+     (CP_ME_RAM_DATA_ME_RAM_DATA_MASK)
+
+#define CP_ME_RAM_DATA(me_ram_data) \
+     ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT))
+
+#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \
+     ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \
+     cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ram_data_t {
+          unsigned int me_ram_data                    : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE;
+     } cp_me_ram_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ram_data_t f;
+} cp_me_ram_data_u;
+
+
+/*
+ * CP_ME_RDADDR struct
+ */
+
+#define CP_ME_RDADDR_ME_RDADDR_SIZE    32
+
+#define CP_ME_RDADDR_ME_RDADDR_SHIFT   0
+
+#define CP_ME_RDADDR_ME_RDADDR_MASK    0xffffffff
+
+#define CP_ME_RDADDR_MASK \
+     (CP_ME_RDADDR_ME_RDADDR_MASK)
+
+#define CP_ME_RDADDR(me_rdaddr) \
+     ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT))
+
+#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \
+     ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \
+     cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_rdaddr_t {
+          unsigned int me_rdaddr                      : CP_ME_RDADDR_ME_RDADDR_SIZE;
+     } cp_me_rdaddr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_rdaddr_t f;
+} cp_me_rdaddr_u;
+
+
+/*
+ * CP_DEBUG struct
+ */
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23
+#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0
+#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23
+#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25
+#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31
+
+#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff
+#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000
+#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000
+#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000
+#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000
+#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000
+#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000
+#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000
+#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000
+
+#define CP_DEBUG_MASK \
+     (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \
+      CP_DEBUG_PREDICATE_DISABLE_MASK | \
+      CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \
+      CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \
+      CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \
+      CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \
+      CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \
+      CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \
+      CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK)
+
+#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \
+     ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \
+      (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \
+      (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \
+      (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \
+      (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \
+      (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \
+      (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \
+      (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \
+      (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT))
+
+#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \
+     ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \
+     ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \
+     ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT)
+#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT)
+#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT)
+#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT)
+#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT)
+#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT)
+#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \
+     cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+     } cp_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_debug_t {
+          unsigned int miu_write_pack_disable         : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE;
+          unsigned int simple_me_flow_control         : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prefetch_match_disable         : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE;
+          unsigned int dynamic_clk_disable            : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE;
+          unsigned int prefetch_pass_nops             : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE;
+          unsigned int miu_128bit_write_enable        : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE;
+          unsigned int prog_end_ptr_enable            : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE;
+          unsigned int predicate_disable              : CP_DEBUG_PREDICATE_DISABLE_SIZE;
+          unsigned int cp_debug_unused_22_to_0        : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE;
+     } cp_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_debug_t f;
+} cp_debug_u;
+
+
+/*
+ * SCRATCH_REG0 struct
+ */
+
+#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32
+
+#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0
+
+#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff
+
+#define SCRATCH_REG0_MASK \
+     (SCRATCH_REG0_SCRATCH_REG0_MASK)
+
+#define SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT))
+
+#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \
+     ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \
+     scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg0_t {
+          unsigned int scratch_reg0                   : SCRATCH_REG0_SCRATCH_REG0_SIZE;
+     } scratch_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg0_t f;
+} scratch_reg0_u;
+
+
+/*
+ * SCRATCH_REG1 struct
+ */
+
+#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32
+
+#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0
+
+#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff
+
+#define SCRATCH_REG1_MASK \
+     (SCRATCH_REG1_SCRATCH_REG1_MASK)
+
+#define SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT))
+
+#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \
+     ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \
+     scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg1_t {
+          unsigned int scratch_reg1                   : SCRATCH_REG1_SCRATCH_REG1_SIZE;
+     } scratch_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg1_t f;
+} scratch_reg1_u;
+
+
+/*
+ * SCRATCH_REG2 struct
+ */
+
+#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32
+
+#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0
+
+#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff
+
+#define SCRATCH_REG2_MASK \
+     (SCRATCH_REG2_SCRATCH_REG2_MASK)
+
+#define SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT))
+
+#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \
+     ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \
+     scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg2_t {
+          unsigned int scratch_reg2                   : SCRATCH_REG2_SCRATCH_REG2_SIZE;
+     } scratch_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg2_t f;
+} scratch_reg2_u;
+
+
+/*
+ * SCRATCH_REG3 struct
+ */
+
+#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32
+
+#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0
+
+#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff
+
+#define SCRATCH_REG3_MASK \
+     (SCRATCH_REG3_SCRATCH_REG3_MASK)
+
+#define SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT))
+
+#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \
+     ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \
+     scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg3_t {
+          unsigned int scratch_reg3                   : SCRATCH_REG3_SCRATCH_REG3_SIZE;
+     } scratch_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg3_t f;
+} scratch_reg3_u;
+
+
+/*
+ * SCRATCH_REG4 struct
+ */
+
+#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32
+
+#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0
+
+#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff
+
+#define SCRATCH_REG4_MASK \
+     (SCRATCH_REG4_SCRATCH_REG4_MASK)
+
+#define SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT))
+
+#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \
+     ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \
+     scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg4_t {
+          unsigned int scratch_reg4                   : SCRATCH_REG4_SCRATCH_REG4_SIZE;
+     } scratch_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg4_t f;
+} scratch_reg4_u;
+
+
+/*
+ * SCRATCH_REG5 struct
+ */
+
+#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32
+
+#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0
+
+#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff
+
+#define SCRATCH_REG5_MASK \
+     (SCRATCH_REG5_SCRATCH_REG5_MASK)
+
+#define SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT))
+
+#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \
+     ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \
+     scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg5_t {
+          unsigned int scratch_reg5                   : SCRATCH_REG5_SCRATCH_REG5_SIZE;
+     } scratch_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg5_t f;
+} scratch_reg5_u;
+
+
+/*
+ * SCRATCH_REG6 struct
+ */
+
+#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32
+
+#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0
+
+#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff
+
+#define SCRATCH_REG6_MASK \
+     (SCRATCH_REG6_SCRATCH_REG6_MASK)
+
+#define SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT))
+
+#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \
+     ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \
+     scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg6_t {
+          unsigned int scratch_reg6                   : SCRATCH_REG6_SCRATCH_REG6_SIZE;
+     } scratch_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg6_t f;
+} scratch_reg6_u;
+
+
+/*
+ * SCRATCH_REG7 struct
+ */
+
+#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32
+
+#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0
+
+#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff
+
+#define SCRATCH_REG7_MASK \
+     (SCRATCH_REG7_SCRATCH_REG7_MASK)
+
+#define SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT))
+
+#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \
+     ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \
+     scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_reg7_t {
+          unsigned int scratch_reg7                   : SCRATCH_REG7_SCRATCH_REG7_SIZE;
+     } scratch_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_reg7_t f;
+} scratch_reg7_u;
+
+
+/*
+ * SCRATCH_UMSK struct
+ */
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8
+#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0
+#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16
+
+#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff
+#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000
+
+#define SCRATCH_UMSK_MASK \
+     (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \
+      SCRATCH_UMSK_SCRATCH_SWAP_MASK)
+
+#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \
+     ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \
+      (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT))
+
+#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \
+     ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT)
+#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \
+     scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 14;
+     } scratch_umsk_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_umsk_t {
+          unsigned int                                : 14;
+          unsigned int scratch_swap                   : SCRATCH_UMSK_SCRATCH_SWAP_SIZE;
+          unsigned int                                : 8;
+          unsigned int scratch_umsk                   : SCRATCH_UMSK_SCRATCH_UMSK_SIZE;
+     } scratch_umsk_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_umsk_t f;
+} scratch_umsk_u;
+
+
+/*
+ * SCRATCH_ADDR struct
+ */
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5
+
+#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0
+
+#define SCRATCH_ADDR_MASK \
+     (SCRATCH_ADDR_SCRATCH_ADDR_MASK)
+
+#define SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT))
+
+#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \
+     ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \
+     scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int                                : 5;
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+     } scratch_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _scratch_addr_t {
+          unsigned int scratch_addr                   : SCRATCH_ADDR_SCRATCH_ADDR_SIZE;
+          unsigned int                                : 5;
+     } scratch_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     scratch_addr_t f;
+} scratch_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_SRC struct
+ */
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001
+#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_VS_EVENT_SRC_MASK \
+     (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \
+      CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK)
+
+#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \
+     ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \
+      (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \
+     ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT)
+#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \
+     cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_vs_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_src_t {
+          unsigned int                                : 30;
+          unsigned int vs_done_cntr                   : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE;
+          unsigned int vs_done_swm                    : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE;
+     } cp_me_vs_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_src_t f;
+} cp_me_vs_event_src_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_MASK \
+     (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \
+      CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK)
+
+#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \
+     ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \
+      (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \
+     ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \
+     cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_t {
+          unsigned int vs_done_addr                   : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE;
+          unsigned int vs_done_swap                   : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE;
+     } cp_me_vs_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_t f;
+} cp_me_vs_event_addr_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_MASK \
+     (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK)
+
+#define CP_ME_VS_EVENT_DATA(vs_done_data) \
+     ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \
+     ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \
+     cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_t {
+          unsigned int vs_done_data                   : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE;
+     } cp_me_vs_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_t f;
+} cp_me_vs_event_data_u;
+
+
+/*
+ * CP_ME_VS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_VS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \
+      CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \
+     ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \
+      (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \
+     ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \
+     cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_addr_swm_t {
+          unsigned int vs_done_addr_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE;
+          unsigned int vs_done_swap_swm               : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE;
+     } cp_me_vs_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_addr_swm_t f;
+} cp_me_vs_event_addr_swm_u;
+
+
+/*
+ * CP_ME_VS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_VS_EVENT_DATA_SWM_MASK \
+     (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \
+     ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \
+     ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \
+     cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_event_data_swm_t {
+          unsigned int vs_done_data_swm               : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE;
+     } cp_me_vs_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_event_data_swm_t f;
+} cp_me_vs_event_data_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_SRC struct
+ */
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1
+
+#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001
+#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002
+
+#define CP_ME_PS_EVENT_SRC_MASK \
+     (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \
+      CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK)
+
+#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \
+     ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \
+      (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT))
+
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \
+     ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT)
+#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \
+     cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int                                : 30;
+     } cp_me_ps_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_src_t {
+          unsigned int                                : 30;
+          unsigned int ps_done_cntr                   : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE;
+          unsigned int ps_done_swm                    : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE;
+     } cp_me_ps_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_src_t f;
+} cp_me_ps_event_src_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_MASK \
+     (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \
+      CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK)
+
+#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \
+     ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \
+      (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \
+     ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \
+     cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_t {
+          unsigned int ps_done_addr                   : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE;
+          unsigned int ps_done_swap                   : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE;
+     } cp_me_ps_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_t f;
+} cp_me_ps_event_addr_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_MASK \
+     (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK)
+
+#define CP_ME_PS_EVENT_DATA(ps_done_data) \
+     ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \
+     ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \
+     cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_t {
+          unsigned int ps_done_data                   : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE;
+     } cp_me_ps_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_t f;
+} cp_me_ps_event_data_u;
+
+
+/*
+ * CP_ME_PS_EVENT_ADDR_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2
+
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003
+#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc
+
+#define CP_ME_PS_EVENT_ADDR_SWM_MASK \
+     (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \
+      CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK)
+
+#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \
+     ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \
+      (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \
+     ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT)
+#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \
+     cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_addr_swm_t {
+          unsigned int ps_done_addr_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE;
+          unsigned int ps_done_swap_swm               : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE;
+     } cp_me_ps_event_addr_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_addr_swm_t f;
+} cp_me_ps_event_addr_swm_u;
+
+
+/*
+ * CP_ME_PS_EVENT_DATA_SWM struct
+ */
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0
+
+#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff
+
+#define CP_ME_PS_EVENT_DATA_SWM_MASK \
+     (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK)
+
+#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \
+     ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT))
+
+#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \
+     ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \
+     cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_ps_event_data_swm_t {
+          unsigned int ps_done_data_swm               : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE;
+     } cp_me_ps_event_data_swm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_ps_event_data_swm_t f;
+} cp_me_ps_event_data_swm_u;
+
+
+/*
+ * CP_ME_CF_EVENT_SRC struct
+ */
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0
+
+#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001
+
+#define CP_ME_CF_EVENT_SRC_MASK \
+     (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK)
+
+#define CP_ME_CF_EVENT_SRC(cf_done_src) \
+     ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT))
+
+#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \
+     ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \
+     cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+          unsigned int                                : 31;
+     } cp_me_cf_event_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_src_t {
+          unsigned int                                : 31;
+          unsigned int cf_done_src                    : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE;
+     } cp_me_cf_event_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_src_t f;
+} cp_me_cf_event_src_u;
+
+
+/*
+ * CP_ME_CF_EVENT_ADDR struct
+ */
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2
+
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003
+#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_CF_EVENT_ADDR_MASK \
+     (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \
+      CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK)
+
+#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \
+     ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \
+      (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT))
+
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \
+     ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT)
+#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \
+     cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_addr_t {
+          unsigned int cf_done_addr                   : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE;
+          unsigned int cf_done_swap                   : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE;
+     } cp_me_cf_event_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_addr_t f;
+} cp_me_cf_event_addr_u;
+
+
+/*
+ * CP_ME_CF_EVENT_DATA struct
+ */
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0
+
+#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_CF_EVENT_DATA_MASK \
+     (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK)
+
+#define CP_ME_CF_EVENT_DATA(cf_done_data) \
+     ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT))
+
+#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \
+     ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \
+     cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_cf_event_data_t {
+          unsigned int cf_done_data                   : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE;
+     } cp_me_cf_event_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_cf_event_data_t f;
+} cp_me_cf_event_data_u;
+
+
+/*
+ * CP_ME_NRT_ADDR struct
+ */
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2
+
+#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003
+#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_NRT_ADDR_MASK \
+     (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \
+      CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK)
+
+#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \
+     ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \
+      (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT))
+
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \
+     ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT)
+#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \
+     cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+     } cp_me_nrt_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_addr_t {
+          unsigned int nrt_write_addr                 : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE;
+          unsigned int nrt_write_swap                 : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE;
+     } cp_me_nrt_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_addr_t f;
+} cp_me_nrt_addr_u;
+
+
+/*
+ * CP_ME_NRT_DATA struct
+ */
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0
+
+#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff
+
+#define CP_ME_NRT_DATA_MASK \
+     (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK)
+
+#define CP_ME_NRT_DATA(nrt_write_data) \
+     ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT))
+
+#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \
+     ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \
+     cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_nrt_data_t {
+          unsigned int nrt_write_data                 : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE;
+     } cp_me_nrt_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_nrt_data_t f;
+} cp_me_nrt_data_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_SRC struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001
+
+#define CP_ME_VS_FETCH_DONE_SRC_MASK \
+     (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \
+     ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \
+     ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \
+     cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+          unsigned int                                : 31;
+     } cp_me_vs_fetch_done_src_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_src_t {
+          unsigned int                                : 31;
+          unsigned int vs_fetch_done_cntr             : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE;
+     } cp_me_vs_fetch_done_src_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_src_t f;
+} cp_me_vs_fetch_done_src_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_ADDR struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2
+
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003
+#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc
+
+#define CP_ME_VS_FETCH_DONE_ADDR_MASK \
+     (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \
+      CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK)
+
+#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \
+     ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \
+      (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \
+     ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT)
+#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \
+     cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_addr_t {
+          unsigned int vs_fetch_done_addr             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE;
+          unsigned int vs_fetch_done_swap             : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE;
+     } cp_me_vs_fetch_done_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_addr_t f;
+} cp_me_vs_fetch_done_addr_u;
+
+
+/*
+ * CP_ME_VS_FETCH_DONE_DATA struct
+ */
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0
+
+#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff
+
+#define CP_ME_VS_FETCH_DONE_DATA_MASK \
+     (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK)
+
+#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \
+     ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT))
+
+#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \
+     ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \
+     cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_me_vs_fetch_done_data_t {
+          unsigned int vs_fetch_done_data             : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE;
+     } cp_me_vs_fetch_done_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_me_vs_fetch_done_data_t f;
+} cp_me_vs_fetch_done_data_u;
+
+
+/*
+ * CP_INT_CNTL struct
+ */
+
+#define CP_INT_CNTL_SW_INT_MASK_SIZE   1
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1
+#define CP_INT_CNTL_IB2_INT_MASK_SIZE  1
+#define CP_INT_CNTL_IB1_INT_MASK_SIZE  1
+#define CP_INT_CNTL_RB_INT_MASK_SIZE   1
+
+#define CP_INT_CNTL_SW_INT_MASK_SHIFT  19
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26
+#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27
+#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29
+#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30
+#define CP_INT_CNTL_RB_INT_MASK_SHIFT  31
+
+#define CP_INT_CNTL_SW_INT_MASK_MASK   0x00080000
+#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000
+#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000
+#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000
+#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000
+#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000
+#define CP_INT_CNTL_IB2_INT_MASK_MASK  0x20000000
+#define CP_INT_CNTL_IB1_INT_MASK_MASK  0x40000000
+#define CP_INT_CNTL_RB_INT_MASK_MASK   0x80000000
+
+#define CP_INT_CNTL_MASK \
+     (CP_INT_CNTL_SW_INT_MASK_MASK | \
+      CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \
+      CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \
+      CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB_ERROR_MASK_MASK | \
+      CP_INT_CNTL_IB2_INT_MASK_MASK | \
+      CP_INT_CNTL_IB1_INT_MASK_MASK | \
+      CP_INT_CNTL_RB_INT_MASK_MASK)
+
+#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \
+     ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \
+      (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \
+      (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \
+      (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \
+      (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \
+      (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \
+      (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \
+      (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \
+      (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT))
+
+#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \
+     ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT)
+#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT)
+#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \
+     cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+     } cp_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_cntl_t {
+          unsigned int rb_int_mask                    : CP_INT_CNTL_RB_INT_MASK_SIZE;
+          unsigned int ib1_int_mask                   : CP_INT_CNTL_IB1_INT_MASK_SIZE;
+          unsigned int ib2_int_mask                   : CP_INT_CNTL_IB2_INT_MASK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_mask                  : CP_INT_CNTL_IB_ERROR_MASK_SIZE;
+          unsigned int reserved_bit_error_mask        : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE;
+          unsigned int protected_mode_error_mask      : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE;
+          unsigned int opcode_error_mask              : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE;
+          unsigned int t0_packet_in_ib_mask           : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_mask                    : CP_INT_CNTL_SW_INT_MASK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_cntl_t f;
+} cp_int_cntl_u;
+
+
+/*
+ * CP_INT_STATUS struct
+ */
+
+#define CP_INT_STATUS_SW_INT_STAT_SIZE 1
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1
+#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1
+#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1
+#define CP_INT_STATUS_RB_INT_STAT_SIZE 1
+
+#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26
+#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27
+#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29
+#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30
+#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31
+
+#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000
+#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000
+#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000
+#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000
+#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000
+#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000
+#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000
+
+#define CP_INT_STATUS_MASK \
+     (CP_INT_STATUS_SW_INT_STAT_MASK | \
+      CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \
+      CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \
+      CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB_ERROR_STAT_MASK | \
+      CP_INT_STATUS_IB2_INT_STAT_MASK | \
+      CP_INT_STATUS_IB1_INT_STAT_MASK | \
+      CP_INT_STATUS_RB_INT_STAT_MASK)
+
+#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \
+     ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \
+      (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \
+      (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \
+      (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \
+      (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \
+      (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \
+      (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \
+      (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \
+      (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT))
+
+#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \
+     ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT)
+#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT)
+#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \
+     cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+     } cp_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_status_t {
+          unsigned int rb_int_stat                    : CP_INT_STATUS_RB_INT_STAT_SIZE;
+          unsigned int ib1_int_stat                   : CP_INT_STATUS_IB1_INT_STAT_SIZE;
+          unsigned int ib2_int_stat                   : CP_INT_STATUS_IB2_INT_STAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_stat                  : CP_INT_STATUS_IB_ERROR_STAT_SIZE;
+          unsigned int reserved_bit_error_stat        : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE;
+          unsigned int protected_mode_error_stat      : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE;
+          unsigned int opcode_error_stat              : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE;
+          unsigned int t0_packet_in_ib_stat           : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_stat                    : CP_INT_STATUS_SW_INT_STAT_SIZE;
+          unsigned int                                : 19;
+     } cp_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_status_t f;
+} cp_int_status_u;
+
+
+/*
+ * CP_INT_ACK struct
+ */
+
+#define CP_INT_ACK_SW_INT_ACK_SIZE     1
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1
+#define CP_INT_ACK_IB_ERROR_ACK_SIZE   1
+#define CP_INT_ACK_IB2_INT_ACK_SIZE    1
+#define CP_INT_ACK_IB1_INT_ACK_SIZE    1
+#define CP_INT_ACK_RB_INT_ACK_SIZE     1
+
+#define CP_INT_ACK_SW_INT_ACK_SHIFT    19
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23
+#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26
+#define CP_INT_ACK_IB_ERROR_ACK_SHIFT  27
+#define CP_INT_ACK_IB2_INT_ACK_SHIFT   29
+#define CP_INT_ACK_IB1_INT_ACK_SHIFT   30
+#define CP_INT_ACK_RB_INT_ACK_SHIFT    31
+
+#define CP_INT_ACK_SW_INT_ACK_MASK     0x00080000
+#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000
+#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000
+#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000
+#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000
+#define CP_INT_ACK_IB_ERROR_ACK_MASK   0x08000000
+#define CP_INT_ACK_IB2_INT_ACK_MASK    0x20000000
+#define CP_INT_ACK_IB1_INT_ACK_MASK    0x40000000
+#define CP_INT_ACK_RB_INT_ACK_MASK     0x80000000
+
+#define CP_INT_ACK_MASK \
+     (CP_INT_ACK_SW_INT_ACK_MASK | \
+      CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \
+      CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \
+      CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB_ERROR_ACK_MASK | \
+      CP_INT_ACK_IB2_INT_ACK_MASK | \
+      CP_INT_ACK_IB1_INT_ACK_MASK | \
+      CP_INT_ACK_RB_INT_ACK_MASK)
+
+#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \
+     ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \
+      (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \
+      (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \
+      (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \
+      (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \
+      (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \
+      (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \
+      (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \
+      (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT))
+
+#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \
+     ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT)
+#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT)
+#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \
+     cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int                                : 19;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+     } cp_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_int_ack_t {
+          unsigned int rb_int_ack                     : CP_INT_ACK_RB_INT_ACK_SIZE;
+          unsigned int ib1_int_ack                    : CP_INT_ACK_IB1_INT_ACK_SIZE;
+          unsigned int ib2_int_ack                    : CP_INT_ACK_IB2_INT_ACK_SIZE;
+          unsigned int                                : 1;
+          unsigned int ib_error_ack                   : CP_INT_ACK_IB_ERROR_ACK_SIZE;
+          unsigned int reserved_bit_error_ack         : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE;
+          unsigned int protected_mode_error_ack       : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE;
+          unsigned int opcode_error_ack               : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE;
+          unsigned int t0_packet_in_ib_ack            : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_int_ack                     : CP_INT_ACK_SW_INT_ACK_SIZE;
+          unsigned int                                : 19;
+     } cp_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_int_ack_t f;
+} cp_int_ack_u;
+
+
+/*
+ * CP_PFP_UCODE_ADDR struct
+ */
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0
+
+#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff
+
+#define CP_PFP_UCODE_ADDR_MASK \
+     (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK)
+
+#define CP_PFP_UCODE_ADDR(ucode_addr) \
+     ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT))
+
+#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \
+     ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \
+     cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+          unsigned int                                : 23;
+     } cp_pfp_ucode_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_addr_t {
+          unsigned int                                : 23;
+          unsigned int ucode_addr                     : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE;
+     } cp_pfp_ucode_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_addr_t f;
+} cp_pfp_ucode_addr_u;
+
+
+/*
+ * CP_PFP_UCODE_DATA struct
+ */
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0
+
+#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff
+
+#define CP_PFP_UCODE_DATA_MASK \
+     (CP_PFP_UCODE_DATA_UCODE_DATA_MASK)
+
+#define CP_PFP_UCODE_DATA(ucode_data) \
+     ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT))
+
+#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \
+     ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \
+     cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+          unsigned int                                : 8;
+     } cp_pfp_ucode_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_pfp_ucode_data_t {
+          unsigned int                                : 8;
+          unsigned int ucode_data                     : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE;
+     } cp_pfp_ucode_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_pfp_ucode_data_t f;
+} cp_pfp_ucode_data_u;
+
+
+/*
+ * CP_PERFMON_CNTL struct
+ */
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8
+
+#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f
+#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300
+
+#define CP_PERFMON_CNTL_MASK \
+     (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \
+      CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK)
+
+#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \
+     ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \
+      (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT))
+
+#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \
+     ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT)
+#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \
+     cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 22;
+     } cp_perfmon_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfmon_cntl_t {
+          unsigned int                                : 22;
+          unsigned int perfmon_enable_mode            : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE;
+          unsigned int                                : 4;
+          unsigned int perfmon_state                  : CP_PERFMON_CNTL_PERFMON_STATE_SIZE;
+     } cp_perfmon_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfmon_cntl_t f;
+} cp_perfmon_cntl_u;
+
+
+/*
+ * CP_PERFCOUNTER_SELECT struct
+ */
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0
+
+#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f
+
+#define CP_PERFCOUNTER_SELECT_MASK \
+     (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK)
+
+#define CP_PERFCOUNTER_SELECT(perfcount_sel) \
+     ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT))
+
+#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \
+     ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \
+     cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+          unsigned int                                : 26;
+     } cp_perfcounter_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_select_t {
+          unsigned int                                : 26;
+          unsigned int perfcount_sel                  : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE;
+     } cp_perfcounter_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_select_t f;
+} cp_perfcounter_select_u;
+
+
+/*
+ * CP_PERFCOUNTER_LO struct
+ */
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0
+
+#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff
+
+#define CP_PERFCOUNTER_LO_MASK \
+     (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK)
+
+#define CP_PERFCOUNTER_LO(perfcount_lo) \
+     ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT))
+
+#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \
+     ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \
+     cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_lo_t {
+          unsigned int perfcount_lo                   : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE;
+     } cp_perfcounter_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_lo_t f;
+} cp_perfcounter_lo_u;
+
+
+/*
+ * CP_PERFCOUNTER_HI struct
+ */
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0
+
+#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff
+
+#define CP_PERFCOUNTER_HI_MASK \
+     (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK)
+
+#define CP_PERFCOUNTER_HI(perfcount_hi) \
+     ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT))
+
+#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \
+     ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \
+     cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+          unsigned int                                : 16;
+     } cp_perfcounter_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_perfcounter_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcount_hi                   : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE;
+     } cp_perfcounter_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_perfcounter_hi_t f;
+} cp_perfcounter_hi_u;
+
+
+/*
+ * CP_BIN_MASK_LO struct
+ */
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0
+
+#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff
+
+#define CP_BIN_MASK_LO_MASK \
+     (CP_BIN_MASK_LO_BIN_MASK_LO_MASK)
+
+#define CP_BIN_MASK_LO(bin_mask_lo) \
+     ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT))
+
+#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \
+     ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \
+     cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_lo_t {
+          unsigned int bin_mask_lo                    : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE;
+     } cp_bin_mask_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_lo_t f;
+} cp_bin_mask_lo_u;
+
+
+/*
+ * CP_BIN_MASK_HI struct
+ */
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0
+
+#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff
+
+#define CP_BIN_MASK_HI_MASK \
+     (CP_BIN_MASK_HI_BIN_MASK_HI_MASK)
+
+#define CP_BIN_MASK_HI(bin_mask_hi) \
+     ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT))
+
+#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \
+     ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \
+     cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_mask_hi_t {
+          unsigned int bin_mask_hi                    : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE;
+     } cp_bin_mask_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_mask_hi_t f;
+} cp_bin_mask_hi_u;
+
+
+/*
+ * CP_BIN_SELECT_LO struct
+ */
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0
+
+#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff
+
+#define CP_BIN_SELECT_LO_MASK \
+     (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK)
+
+#define CP_BIN_SELECT_LO(bin_select_lo) \
+     ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT))
+
+#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \
+     ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \
+     cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_lo_t {
+          unsigned int bin_select_lo                  : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE;
+     } cp_bin_select_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_lo_t f;
+} cp_bin_select_lo_u;
+
+
+/*
+ * CP_BIN_SELECT_HI struct
+ */
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0
+
+#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff
+
+#define CP_BIN_SELECT_HI_MASK \
+     (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK)
+
+#define CP_BIN_SELECT_HI(bin_select_hi) \
+     ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT))
+
+#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \
+     ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \
+     cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_bin_select_hi_t {
+          unsigned int bin_select_hi                  : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE;
+     } cp_bin_select_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_bin_select_hi_t f;
+} cp_bin_select_hi_u;
+
+
+/*
+ * CP_NV_FLAGS_0 struct
+ */
+
+#define CP_NV_FLAGS_0_DISCARD_0_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_0_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_1_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_1_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_2_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_2_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_3_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_3_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_4_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_4_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_5_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_5_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_6_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_6_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_7_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_7_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_8_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_8_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_9_SIZE   1
+#define CP_NV_FLAGS_0_END_RCVD_9_SIZE  1
+#define CP_NV_FLAGS_0_DISCARD_10_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_11_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_12_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_13_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_14_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1
+#define CP_NV_FLAGS_0_DISCARD_15_SIZE  1
+#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1
+
+#define CP_NV_FLAGS_0_DISCARD_0_SHIFT  0
+#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1
+#define CP_NV_FLAGS_0_DISCARD_1_SHIFT  2
+#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3
+#define CP_NV_FLAGS_0_DISCARD_2_SHIFT  4
+#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5
+#define CP_NV_FLAGS_0_DISCARD_3_SHIFT  6
+#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7
+#define CP_NV_FLAGS_0_DISCARD_4_SHIFT  8
+#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9
+#define CP_NV_FLAGS_0_DISCARD_5_SHIFT  10
+#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11
+#define CP_NV_FLAGS_0_DISCARD_6_SHIFT  12
+#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13
+#define CP_NV_FLAGS_0_DISCARD_7_SHIFT  14
+#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15
+#define CP_NV_FLAGS_0_DISCARD_8_SHIFT  16
+#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17
+#define CP_NV_FLAGS_0_DISCARD_9_SHIFT  18
+#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19
+#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20
+#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21
+#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22
+#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23
+#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24
+#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25
+#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26
+#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27
+#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28
+#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29
+#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30
+#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31
+
+#define CP_NV_FLAGS_0_DISCARD_0_MASK   0x00000001
+#define CP_NV_FLAGS_0_END_RCVD_0_MASK  0x00000002
+#define CP_NV_FLAGS_0_DISCARD_1_MASK   0x00000004
+#define CP_NV_FLAGS_0_END_RCVD_1_MASK  0x00000008
+#define CP_NV_FLAGS_0_DISCARD_2_MASK   0x00000010
+#define CP_NV_FLAGS_0_END_RCVD_2_MASK  0x00000020
+#define CP_NV_FLAGS_0_DISCARD_3_MASK   0x00000040
+#define CP_NV_FLAGS_0_END_RCVD_3_MASK  0x00000080
+#define CP_NV_FLAGS_0_DISCARD_4_MASK   0x00000100
+#define CP_NV_FLAGS_0_END_RCVD_4_MASK  0x00000200
+#define CP_NV_FLAGS_0_DISCARD_5_MASK   0x00000400
+#define CP_NV_FLAGS_0_END_RCVD_5_MASK  0x00000800
+#define CP_NV_FLAGS_0_DISCARD_6_MASK   0x00001000
+#define CP_NV_FLAGS_0_END_RCVD_6_MASK  0x00002000
+#define CP_NV_FLAGS_0_DISCARD_7_MASK   0x00004000
+#define CP_NV_FLAGS_0_END_RCVD_7_MASK  0x00008000
+#define CP_NV_FLAGS_0_DISCARD_8_MASK   0x00010000
+#define CP_NV_FLAGS_0_END_RCVD_8_MASK  0x00020000
+#define CP_NV_FLAGS_0_DISCARD_9_MASK   0x00040000
+#define CP_NV_FLAGS_0_END_RCVD_9_MASK  0x00080000
+#define CP_NV_FLAGS_0_DISCARD_10_MASK  0x00100000
+#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000
+#define CP_NV_FLAGS_0_DISCARD_11_MASK  0x00400000
+#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000
+#define CP_NV_FLAGS_0_DISCARD_12_MASK  0x01000000
+#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000
+#define CP_NV_FLAGS_0_DISCARD_13_MASK  0x04000000
+#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000
+#define CP_NV_FLAGS_0_DISCARD_14_MASK  0x10000000
+#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000
+#define CP_NV_FLAGS_0_DISCARD_15_MASK  0x40000000
+#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000
+
+#define CP_NV_FLAGS_0_MASK \
+     (CP_NV_FLAGS_0_DISCARD_0_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_0_MASK | \
+      CP_NV_FLAGS_0_DISCARD_1_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_1_MASK | \
+      CP_NV_FLAGS_0_DISCARD_2_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_2_MASK | \
+      CP_NV_FLAGS_0_DISCARD_3_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_3_MASK | \
+      CP_NV_FLAGS_0_DISCARD_4_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_4_MASK | \
+      CP_NV_FLAGS_0_DISCARD_5_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_5_MASK | \
+      CP_NV_FLAGS_0_DISCARD_6_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_6_MASK | \
+      CP_NV_FLAGS_0_DISCARD_7_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_7_MASK | \
+      CP_NV_FLAGS_0_DISCARD_8_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_8_MASK | \
+      CP_NV_FLAGS_0_DISCARD_9_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_9_MASK | \
+      CP_NV_FLAGS_0_DISCARD_10_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_10_MASK | \
+      CP_NV_FLAGS_0_DISCARD_11_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_11_MASK | \
+      CP_NV_FLAGS_0_DISCARD_12_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_12_MASK | \
+      CP_NV_FLAGS_0_DISCARD_13_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_13_MASK | \
+      CP_NV_FLAGS_0_DISCARD_14_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_14_MASK | \
+      CP_NV_FLAGS_0_DISCARD_15_MASK | \
+      CP_NV_FLAGS_0_END_RCVD_15_MASK)
+
+#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \
+     ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \
+      (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \
+      (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \
+      (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \
+      (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \
+      (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \
+      (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \
+      (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \
+      (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \
+      (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \
+      (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \
+      (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \
+      (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \
+      (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \
+      (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \
+      (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \
+      (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \
+      (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \
+      (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \
+      (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \
+      (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \
+      (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \
+      (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \
+      (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \
+      (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \
+      (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \
+      (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \
+      (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \
+      (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \
+      (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \
+      (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \
+      (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT))
+
+#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \
+     ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT)
+#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT)
+#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \
+     cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+     } cp_nv_flags_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_0_t {
+          unsigned int end_rcvd_15                    : CP_NV_FLAGS_0_END_RCVD_15_SIZE;
+          unsigned int discard_15                     : CP_NV_FLAGS_0_DISCARD_15_SIZE;
+          unsigned int end_rcvd_14                    : CP_NV_FLAGS_0_END_RCVD_14_SIZE;
+          unsigned int discard_14                     : CP_NV_FLAGS_0_DISCARD_14_SIZE;
+          unsigned int end_rcvd_13                    : CP_NV_FLAGS_0_END_RCVD_13_SIZE;
+          unsigned int discard_13                     : CP_NV_FLAGS_0_DISCARD_13_SIZE;
+          unsigned int end_rcvd_12                    : CP_NV_FLAGS_0_END_RCVD_12_SIZE;
+          unsigned int discard_12                     : CP_NV_FLAGS_0_DISCARD_12_SIZE;
+          unsigned int end_rcvd_11                    : CP_NV_FLAGS_0_END_RCVD_11_SIZE;
+          unsigned int discard_11                     : CP_NV_FLAGS_0_DISCARD_11_SIZE;
+          unsigned int end_rcvd_10                    : CP_NV_FLAGS_0_END_RCVD_10_SIZE;
+          unsigned int discard_10                     : CP_NV_FLAGS_0_DISCARD_10_SIZE;
+          unsigned int end_rcvd_9                     : CP_NV_FLAGS_0_END_RCVD_9_SIZE;
+          unsigned int discard_9                      : CP_NV_FLAGS_0_DISCARD_9_SIZE;
+          unsigned int end_rcvd_8                     : CP_NV_FLAGS_0_END_RCVD_8_SIZE;
+          unsigned int discard_8                      : CP_NV_FLAGS_0_DISCARD_8_SIZE;
+          unsigned int end_rcvd_7                     : CP_NV_FLAGS_0_END_RCVD_7_SIZE;
+          unsigned int discard_7                      : CP_NV_FLAGS_0_DISCARD_7_SIZE;
+          unsigned int end_rcvd_6                     : CP_NV_FLAGS_0_END_RCVD_6_SIZE;
+          unsigned int discard_6                      : CP_NV_FLAGS_0_DISCARD_6_SIZE;
+          unsigned int end_rcvd_5                     : CP_NV_FLAGS_0_END_RCVD_5_SIZE;
+          unsigned int discard_5                      : CP_NV_FLAGS_0_DISCARD_5_SIZE;
+          unsigned int end_rcvd_4                     : CP_NV_FLAGS_0_END_RCVD_4_SIZE;
+          unsigned int discard_4                      : CP_NV_FLAGS_0_DISCARD_4_SIZE;
+          unsigned int end_rcvd_3                     : CP_NV_FLAGS_0_END_RCVD_3_SIZE;
+          unsigned int discard_3                      : CP_NV_FLAGS_0_DISCARD_3_SIZE;
+          unsigned int end_rcvd_2                     : CP_NV_FLAGS_0_END_RCVD_2_SIZE;
+          unsigned int discard_2                      : CP_NV_FLAGS_0_DISCARD_2_SIZE;
+          unsigned int end_rcvd_1                     : CP_NV_FLAGS_0_END_RCVD_1_SIZE;
+          unsigned int discard_1                      : CP_NV_FLAGS_0_DISCARD_1_SIZE;
+          unsigned int end_rcvd_0                     : CP_NV_FLAGS_0_END_RCVD_0_SIZE;
+          unsigned int discard_0                      : CP_NV_FLAGS_0_DISCARD_0_SIZE;
+     } cp_nv_flags_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_0_t f;
+} cp_nv_flags_0_u;
+
+
+/*
+ * CP_NV_FLAGS_1 struct
+ */
+
+#define CP_NV_FLAGS_1_DISCARD_16_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_17_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_18_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_19_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_20_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_21_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_22_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_23_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_24_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_25_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_26_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_27_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_28_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_29_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_30_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1
+#define CP_NV_FLAGS_1_DISCARD_31_SIZE  1
+#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1
+
+#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0
+#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1
+#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2
+#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3
+#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4
+#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5
+#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6
+#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7
+#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8
+#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9
+#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10
+#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11
+#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12
+#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13
+#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14
+#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15
+#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16
+#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17
+#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18
+#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19
+#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20
+#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21
+#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22
+#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23
+#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24
+#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25
+#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26
+#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27
+#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28
+#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29
+#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30
+#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31
+
+#define CP_NV_FLAGS_1_DISCARD_16_MASK  0x00000001
+#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002
+#define CP_NV_FLAGS_1_DISCARD_17_MASK  0x00000004
+#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008
+#define CP_NV_FLAGS_1_DISCARD_18_MASK  0x00000010
+#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020
+#define CP_NV_FLAGS_1_DISCARD_19_MASK  0x00000040
+#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080
+#define CP_NV_FLAGS_1_DISCARD_20_MASK  0x00000100
+#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200
+#define CP_NV_FLAGS_1_DISCARD_21_MASK  0x00000400
+#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800
+#define CP_NV_FLAGS_1_DISCARD_22_MASK  0x00001000
+#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000
+#define CP_NV_FLAGS_1_DISCARD_23_MASK  0x00004000
+#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000
+#define CP_NV_FLAGS_1_DISCARD_24_MASK  0x00010000
+#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000
+#define CP_NV_FLAGS_1_DISCARD_25_MASK  0x00040000
+#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000
+#define CP_NV_FLAGS_1_DISCARD_26_MASK  0x00100000
+#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000
+#define CP_NV_FLAGS_1_DISCARD_27_MASK  0x00400000
+#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000
+#define CP_NV_FLAGS_1_DISCARD_28_MASK  0x01000000
+#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000
+#define CP_NV_FLAGS_1_DISCARD_29_MASK  0x04000000
+#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000
+#define CP_NV_FLAGS_1_DISCARD_30_MASK  0x10000000
+#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000
+#define CP_NV_FLAGS_1_DISCARD_31_MASK  0x40000000
+#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000
+
+#define CP_NV_FLAGS_1_MASK \
+     (CP_NV_FLAGS_1_DISCARD_16_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_16_MASK | \
+      CP_NV_FLAGS_1_DISCARD_17_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_17_MASK | \
+      CP_NV_FLAGS_1_DISCARD_18_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_18_MASK | \
+      CP_NV_FLAGS_1_DISCARD_19_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_19_MASK | \
+      CP_NV_FLAGS_1_DISCARD_20_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_20_MASK | \
+      CP_NV_FLAGS_1_DISCARD_21_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_21_MASK | \
+      CP_NV_FLAGS_1_DISCARD_22_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_22_MASK | \
+      CP_NV_FLAGS_1_DISCARD_23_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_23_MASK | \
+      CP_NV_FLAGS_1_DISCARD_24_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_24_MASK | \
+      CP_NV_FLAGS_1_DISCARD_25_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_25_MASK | \
+      CP_NV_FLAGS_1_DISCARD_26_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_26_MASK | \
+      CP_NV_FLAGS_1_DISCARD_27_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_27_MASK | \
+      CP_NV_FLAGS_1_DISCARD_28_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_28_MASK | \
+      CP_NV_FLAGS_1_DISCARD_29_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_29_MASK | \
+      CP_NV_FLAGS_1_DISCARD_30_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_30_MASK | \
+      CP_NV_FLAGS_1_DISCARD_31_MASK | \
+      CP_NV_FLAGS_1_END_RCVD_31_MASK)
+
+#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \
+     ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \
+      (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \
+      (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \
+      (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \
+      (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \
+      (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \
+      (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \
+      (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \
+      (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \
+      (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \
+      (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \
+      (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \
+      (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \
+      (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \
+      (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \
+      (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \
+      (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \
+      (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \
+      (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \
+      (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \
+      (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \
+      (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \
+      (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \
+      (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \
+      (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \
+      (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \
+      (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \
+      (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \
+      (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \
+      (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \
+      (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \
+      (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT))
+
+#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \
+     ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT)
+#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT)
+#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \
+     cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+     } cp_nv_flags_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_1_t {
+          unsigned int end_rcvd_31                    : CP_NV_FLAGS_1_END_RCVD_31_SIZE;
+          unsigned int discard_31                     : CP_NV_FLAGS_1_DISCARD_31_SIZE;
+          unsigned int end_rcvd_30                    : CP_NV_FLAGS_1_END_RCVD_30_SIZE;
+          unsigned int discard_30                     : CP_NV_FLAGS_1_DISCARD_30_SIZE;
+          unsigned int end_rcvd_29                    : CP_NV_FLAGS_1_END_RCVD_29_SIZE;
+          unsigned int discard_29                     : CP_NV_FLAGS_1_DISCARD_29_SIZE;
+          unsigned int end_rcvd_28                    : CP_NV_FLAGS_1_END_RCVD_28_SIZE;
+          unsigned int discard_28                     : CP_NV_FLAGS_1_DISCARD_28_SIZE;
+          unsigned int end_rcvd_27                    : CP_NV_FLAGS_1_END_RCVD_27_SIZE;
+          unsigned int discard_27                     : CP_NV_FLAGS_1_DISCARD_27_SIZE;
+          unsigned int end_rcvd_26                    : CP_NV_FLAGS_1_END_RCVD_26_SIZE;
+          unsigned int discard_26                     : CP_NV_FLAGS_1_DISCARD_26_SIZE;
+          unsigned int end_rcvd_25                    : CP_NV_FLAGS_1_END_RCVD_25_SIZE;
+          unsigned int discard_25                     : CP_NV_FLAGS_1_DISCARD_25_SIZE;
+          unsigned int end_rcvd_24                    : CP_NV_FLAGS_1_END_RCVD_24_SIZE;
+          unsigned int discard_24                     : CP_NV_FLAGS_1_DISCARD_24_SIZE;
+          unsigned int end_rcvd_23                    : CP_NV_FLAGS_1_END_RCVD_23_SIZE;
+          unsigned int discard_23                     : CP_NV_FLAGS_1_DISCARD_23_SIZE;
+          unsigned int end_rcvd_22                    : CP_NV_FLAGS_1_END_RCVD_22_SIZE;
+          unsigned int discard_22                     : CP_NV_FLAGS_1_DISCARD_22_SIZE;
+          unsigned int end_rcvd_21                    : CP_NV_FLAGS_1_END_RCVD_21_SIZE;
+          unsigned int discard_21                     : CP_NV_FLAGS_1_DISCARD_21_SIZE;
+          unsigned int end_rcvd_20                    : CP_NV_FLAGS_1_END_RCVD_20_SIZE;
+          unsigned int discard_20                     : CP_NV_FLAGS_1_DISCARD_20_SIZE;
+          unsigned int end_rcvd_19                    : CP_NV_FLAGS_1_END_RCVD_19_SIZE;
+          unsigned int discard_19                     : CP_NV_FLAGS_1_DISCARD_19_SIZE;
+          unsigned int end_rcvd_18                    : CP_NV_FLAGS_1_END_RCVD_18_SIZE;
+          unsigned int discard_18                     : CP_NV_FLAGS_1_DISCARD_18_SIZE;
+          unsigned int end_rcvd_17                    : CP_NV_FLAGS_1_END_RCVD_17_SIZE;
+          unsigned int discard_17                     : CP_NV_FLAGS_1_DISCARD_17_SIZE;
+          unsigned int end_rcvd_16                    : CP_NV_FLAGS_1_END_RCVD_16_SIZE;
+          unsigned int discard_16                     : CP_NV_FLAGS_1_DISCARD_16_SIZE;
+     } cp_nv_flags_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_1_t f;
+} cp_nv_flags_1_u;
+
+
+/*
+ * CP_NV_FLAGS_2 struct
+ */
+
+#define CP_NV_FLAGS_2_DISCARD_32_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_33_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_34_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_35_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_36_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_37_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_38_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_39_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_40_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_41_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_42_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_43_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_44_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_45_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_46_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1
+#define CP_NV_FLAGS_2_DISCARD_47_SIZE  1
+#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1
+
+#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0
+#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1
+#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2
+#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3
+#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4
+#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5
+#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6
+#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7
+#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8
+#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9
+#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10
+#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11
+#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12
+#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13
+#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14
+#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15
+#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16
+#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17
+#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18
+#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19
+#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20
+#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21
+#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22
+#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23
+#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24
+#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25
+#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26
+#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27
+#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28
+#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29
+#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30
+#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31
+
+#define CP_NV_FLAGS_2_DISCARD_32_MASK  0x00000001
+#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002
+#define CP_NV_FLAGS_2_DISCARD_33_MASK  0x00000004
+#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008
+#define CP_NV_FLAGS_2_DISCARD_34_MASK  0x00000010
+#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020
+#define CP_NV_FLAGS_2_DISCARD_35_MASK  0x00000040
+#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080
+#define CP_NV_FLAGS_2_DISCARD_36_MASK  0x00000100
+#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200
+#define CP_NV_FLAGS_2_DISCARD_37_MASK  0x00000400
+#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800
+#define CP_NV_FLAGS_2_DISCARD_38_MASK  0x00001000
+#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000
+#define CP_NV_FLAGS_2_DISCARD_39_MASK  0x00004000
+#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000
+#define CP_NV_FLAGS_2_DISCARD_40_MASK  0x00010000
+#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000
+#define CP_NV_FLAGS_2_DISCARD_41_MASK  0x00040000
+#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000
+#define CP_NV_FLAGS_2_DISCARD_42_MASK  0x00100000
+#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000
+#define CP_NV_FLAGS_2_DISCARD_43_MASK  0x00400000
+#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000
+#define CP_NV_FLAGS_2_DISCARD_44_MASK  0x01000000
+#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000
+#define CP_NV_FLAGS_2_DISCARD_45_MASK  0x04000000
+#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000
+#define CP_NV_FLAGS_2_DISCARD_46_MASK  0x10000000
+#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000
+#define CP_NV_FLAGS_2_DISCARD_47_MASK  0x40000000
+#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000
+
+#define CP_NV_FLAGS_2_MASK \
+     (CP_NV_FLAGS_2_DISCARD_32_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_32_MASK | \
+      CP_NV_FLAGS_2_DISCARD_33_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_33_MASK | \
+      CP_NV_FLAGS_2_DISCARD_34_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_34_MASK | \
+      CP_NV_FLAGS_2_DISCARD_35_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_35_MASK | \
+      CP_NV_FLAGS_2_DISCARD_36_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_36_MASK | \
+      CP_NV_FLAGS_2_DISCARD_37_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_37_MASK | \
+      CP_NV_FLAGS_2_DISCARD_38_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_38_MASK | \
+      CP_NV_FLAGS_2_DISCARD_39_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_39_MASK | \
+      CP_NV_FLAGS_2_DISCARD_40_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_40_MASK | \
+      CP_NV_FLAGS_2_DISCARD_41_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_41_MASK | \
+      CP_NV_FLAGS_2_DISCARD_42_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_42_MASK | \
+      CP_NV_FLAGS_2_DISCARD_43_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_43_MASK | \
+      CP_NV_FLAGS_2_DISCARD_44_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_44_MASK | \
+      CP_NV_FLAGS_2_DISCARD_45_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_45_MASK | \
+      CP_NV_FLAGS_2_DISCARD_46_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_46_MASK | \
+      CP_NV_FLAGS_2_DISCARD_47_MASK | \
+      CP_NV_FLAGS_2_END_RCVD_47_MASK)
+
+#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \
+     ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \
+      (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \
+      (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \
+      (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \
+      (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \
+      (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \
+      (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \
+      (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \
+      (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \
+      (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \
+      (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \
+      (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \
+      (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \
+      (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \
+      (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \
+      (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \
+      (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \
+      (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \
+      (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \
+      (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \
+      (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \
+      (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \
+      (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \
+      (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \
+      (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \
+      (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \
+      (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \
+      (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \
+      (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \
+      (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \
+      (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \
+      (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT))
+
+#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \
+     ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT)
+#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT)
+#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \
+     cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+     } cp_nv_flags_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_2_t {
+          unsigned int end_rcvd_47                    : CP_NV_FLAGS_2_END_RCVD_47_SIZE;
+          unsigned int discard_47                     : CP_NV_FLAGS_2_DISCARD_47_SIZE;
+          unsigned int end_rcvd_46                    : CP_NV_FLAGS_2_END_RCVD_46_SIZE;
+          unsigned int discard_46                     : CP_NV_FLAGS_2_DISCARD_46_SIZE;
+          unsigned int end_rcvd_45                    : CP_NV_FLAGS_2_END_RCVD_45_SIZE;
+          unsigned int discard_45                     : CP_NV_FLAGS_2_DISCARD_45_SIZE;
+          unsigned int end_rcvd_44                    : CP_NV_FLAGS_2_END_RCVD_44_SIZE;
+          unsigned int discard_44                     : CP_NV_FLAGS_2_DISCARD_44_SIZE;
+          unsigned int end_rcvd_43                    : CP_NV_FLAGS_2_END_RCVD_43_SIZE;
+          unsigned int discard_43                     : CP_NV_FLAGS_2_DISCARD_43_SIZE;
+          unsigned int end_rcvd_42                    : CP_NV_FLAGS_2_END_RCVD_42_SIZE;
+          unsigned int discard_42                     : CP_NV_FLAGS_2_DISCARD_42_SIZE;
+          unsigned int end_rcvd_41                    : CP_NV_FLAGS_2_END_RCVD_41_SIZE;
+          unsigned int discard_41                     : CP_NV_FLAGS_2_DISCARD_41_SIZE;
+          unsigned int end_rcvd_40                    : CP_NV_FLAGS_2_END_RCVD_40_SIZE;
+          unsigned int discard_40                     : CP_NV_FLAGS_2_DISCARD_40_SIZE;
+          unsigned int end_rcvd_39                    : CP_NV_FLAGS_2_END_RCVD_39_SIZE;
+          unsigned int discard_39                     : CP_NV_FLAGS_2_DISCARD_39_SIZE;
+          unsigned int end_rcvd_38                    : CP_NV_FLAGS_2_END_RCVD_38_SIZE;
+          unsigned int discard_38                     : CP_NV_FLAGS_2_DISCARD_38_SIZE;
+          unsigned int end_rcvd_37                    : CP_NV_FLAGS_2_END_RCVD_37_SIZE;
+          unsigned int discard_37                     : CP_NV_FLAGS_2_DISCARD_37_SIZE;
+          unsigned int end_rcvd_36                    : CP_NV_FLAGS_2_END_RCVD_36_SIZE;
+          unsigned int discard_36                     : CP_NV_FLAGS_2_DISCARD_36_SIZE;
+          unsigned int end_rcvd_35                    : CP_NV_FLAGS_2_END_RCVD_35_SIZE;
+          unsigned int discard_35                     : CP_NV_FLAGS_2_DISCARD_35_SIZE;
+          unsigned int end_rcvd_34                    : CP_NV_FLAGS_2_END_RCVD_34_SIZE;
+          unsigned int discard_34                     : CP_NV_FLAGS_2_DISCARD_34_SIZE;
+          unsigned int end_rcvd_33                    : CP_NV_FLAGS_2_END_RCVD_33_SIZE;
+          unsigned int discard_33                     : CP_NV_FLAGS_2_DISCARD_33_SIZE;
+          unsigned int end_rcvd_32                    : CP_NV_FLAGS_2_END_RCVD_32_SIZE;
+          unsigned int discard_32                     : CP_NV_FLAGS_2_DISCARD_32_SIZE;
+     } cp_nv_flags_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_2_t f;
+} cp_nv_flags_2_u;
+
+
+/*
+ * CP_NV_FLAGS_3 struct
+ */
+
+#define CP_NV_FLAGS_3_DISCARD_48_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_49_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_50_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_51_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_52_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_53_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_54_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_55_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_56_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_57_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_58_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_59_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_60_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_61_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_62_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1
+#define CP_NV_FLAGS_3_DISCARD_63_SIZE  1
+#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1
+
+#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0
+#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1
+#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2
+#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3
+#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4
+#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5
+#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6
+#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7
+#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8
+#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9
+#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10
+#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11
+#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12
+#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13
+#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14
+#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15
+#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16
+#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17
+#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18
+#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19
+#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20
+#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21
+#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22
+#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23
+#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24
+#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25
+#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26
+#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27
+#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28
+#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29
+#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30
+#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31
+
+#define CP_NV_FLAGS_3_DISCARD_48_MASK  0x00000001
+#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002
+#define CP_NV_FLAGS_3_DISCARD_49_MASK  0x00000004
+#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008
+#define CP_NV_FLAGS_3_DISCARD_50_MASK  0x00000010
+#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020
+#define CP_NV_FLAGS_3_DISCARD_51_MASK  0x00000040
+#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080
+#define CP_NV_FLAGS_3_DISCARD_52_MASK  0x00000100
+#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200
+#define CP_NV_FLAGS_3_DISCARD_53_MASK  0x00000400
+#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800
+#define CP_NV_FLAGS_3_DISCARD_54_MASK  0x00001000
+#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000
+#define CP_NV_FLAGS_3_DISCARD_55_MASK  0x00004000
+#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000
+#define CP_NV_FLAGS_3_DISCARD_56_MASK  0x00010000
+#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000
+#define CP_NV_FLAGS_3_DISCARD_57_MASK  0x00040000
+#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000
+#define CP_NV_FLAGS_3_DISCARD_58_MASK  0x00100000
+#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000
+#define CP_NV_FLAGS_3_DISCARD_59_MASK  0x00400000
+#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000
+#define CP_NV_FLAGS_3_DISCARD_60_MASK  0x01000000
+#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000
+#define CP_NV_FLAGS_3_DISCARD_61_MASK  0x04000000
+#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000
+#define CP_NV_FLAGS_3_DISCARD_62_MASK  0x10000000
+#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000
+#define CP_NV_FLAGS_3_DISCARD_63_MASK  0x40000000
+#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000
+
+#define CP_NV_FLAGS_3_MASK \
+     (CP_NV_FLAGS_3_DISCARD_48_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_48_MASK | \
+      CP_NV_FLAGS_3_DISCARD_49_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_49_MASK | \
+      CP_NV_FLAGS_3_DISCARD_50_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_50_MASK | \
+      CP_NV_FLAGS_3_DISCARD_51_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_51_MASK | \
+      CP_NV_FLAGS_3_DISCARD_52_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_52_MASK | \
+      CP_NV_FLAGS_3_DISCARD_53_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_53_MASK | \
+      CP_NV_FLAGS_3_DISCARD_54_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_54_MASK | \
+      CP_NV_FLAGS_3_DISCARD_55_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_55_MASK | \
+      CP_NV_FLAGS_3_DISCARD_56_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_56_MASK | \
+      CP_NV_FLAGS_3_DISCARD_57_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_57_MASK | \
+      CP_NV_FLAGS_3_DISCARD_58_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_58_MASK | \
+      CP_NV_FLAGS_3_DISCARD_59_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_59_MASK | \
+      CP_NV_FLAGS_3_DISCARD_60_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_60_MASK | \
+      CP_NV_FLAGS_3_DISCARD_61_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_61_MASK | \
+      CP_NV_FLAGS_3_DISCARD_62_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_62_MASK | \
+      CP_NV_FLAGS_3_DISCARD_63_MASK | \
+      CP_NV_FLAGS_3_END_RCVD_63_MASK)
+
+#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \
+     ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \
+      (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \
+      (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \
+      (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \
+      (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \
+      (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \
+      (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \
+      (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \
+      (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \
+      (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \
+      (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \
+      (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \
+      (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \
+      (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \
+      (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \
+      (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \
+      (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \
+      (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \
+      (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \
+      (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \
+      (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \
+      (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \
+      (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \
+      (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \
+      (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \
+      (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \
+      (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \
+      (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \
+      (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \
+      (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \
+      (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \
+      (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT))
+
+#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \
+     ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT)
+#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT)
+#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \
+     cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+     } cp_nv_flags_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_nv_flags_3_t {
+          unsigned int end_rcvd_63                    : CP_NV_FLAGS_3_END_RCVD_63_SIZE;
+          unsigned int discard_63                     : CP_NV_FLAGS_3_DISCARD_63_SIZE;
+          unsigned int end_rcvd_62                    : CP_NV_FLAGS_3_END_RCVD_62_SIZE;
+          unsigned int discard_62                     : CP_NV_FLAGS_3_DISCARD_62_SIZE;
+          unsigned int end_rcvd_61                    : CP_NV_FLAGS_3_END_RCVD_61_SIZE;
+          unsigned int discard_61                     : CP_NV_FLAGS_3_DISCARD_61_SIZE;
+          unsigned int end_rcvd_60                    : CP_NV_FLAGS_3_END_RCVD_60_SIZE;
+          unsigned int discard_60                     : CP_NV_FLAGS_3_DISCARD_60_SIZE;
+          unsigned int end_rcvd_59                    : CP_NV_FLAGS_3_END_RCVD_59_SIZE;
+          unsigned int discard_59                     : CP_NV_FLAGS_3_DISCARD_59_SIZE;
+          unsigned int end_rcvd_58                    : CP_NV_FLAGS_3_END_RCVD_58_SIZE;
+          unsigned int discard_58                     : CP_NV_FLAGS_3_DISCARD_58_SIZE;
+          unsigned int end_rcvd_57                    : CP_NV_FLAGS_3_END_RCVD_57_SIZE;
+          unsigned int discard_57                     : CP_NV_FLAGS_3_DISCARD_57_SIZE;
+          unsigned int end_rcvd_56                    : CP_NV_FLAGS_3_END_RCVD_56_SIZE;
+          unsigned int discard_56                     : CP_NV_FLAGS_3_DISCARD_56_SIZE;
+          unsigned int end_rcvd_55                    : CP_NV_FLAGS_3_END_RCVD_55_SIZE;
+          unsigned int discard_55                     : CP_NV_FLAGS_3_DISCARD_55_SIZE;
+          unsigned int end_rcvd_54                    : CP_NV_FLAGS_3_END_RCVD_54_SIZE;
+          unsigned int discard_54                     : CP_NV_FLAGS_3_DISCARD_54_SIZE;
+          unsigned int end_rcvd_53                    : CP_NV_FLAGS_3_END_RCVD_53_SIZE;
+          unsigned int discard_53                     : CP_NV_FLAGS_3_DISCARD_53_SIZE;
+          unsigned int end_rcvd_52                    : CP_NV_FLAGS_3_END_RCVD_52_SIZE;
+          unsigned int discard_52                     : CP_NV_FLAGS_3_DISCARD_52_SIZE;
+          unsigned int end_rcvd_51                    : CP_NV_FLAGS_3_END_RCVD_51_SIZE;
+          unsigned int discard_51                     : CP_NV_FLAGS_3_DISCARD_51_SIZE;
+          unsigned int end_rcvd_50                    : CP_NV_FLAGS_3_END_RCVD_50_SIZE;
+          unsigned int discard_50                     : CP_NV_FLAGS_3_DISCARD_50_SIZE;
+          unsigned int end_rcvd_49                    : CP_NV_FLAGS_3_END_RCVD_49_SIZE;
+          unsigned int discard_49                     : CP_NV_FLAGS_3_DISCARD_49_SIZE;
+          unsigned int end_rcvd_48                    : CP_NV_FLAGS_3_END_RCVD_48_SIZE;
+          unsigned int discard_48                     : CP_NV_FLAGS_3_DISCARD_48_SIZE;
+     } cp_nv_flags_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_nv_flags_3_t f;
+} cp_nv_flags_3_u;
+
+
+/*
+ * CP_STATE_DEBUG_INDEX struct
+ */
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0
+
+#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f
+
+#define CP_STATE_DEBUG_INDEX_MASK \
+     (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK)
+
+#define CP_STATE_DEBUG_INDEX(state_debug_index) \
+     ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT))
+
+#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \
+     ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \
+     cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+          unsigned int                                : 27;
+     } cp_state_debug_index_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_index_t {
+          unsigned int                                : 27;
+          unsigned int state_debug_index              : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE;
+     } cp_state_debug_index_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_index_t f;
+} cp_state_debug_index_u;
+
+
+/*
+ * CP_STATE_DEBUG_DATA struct
+ */
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0
+
+#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff
+
+#define CP_STATE_DEBUG_DATA_MASK \
+     (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK)
+
+#define CP_STATE_DEBUG_DATA(state_debug_data) \
+     ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT))
+
+#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \
+     ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \
+     cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_state_debug_data_t {
+          unsigned int state_debug_data               : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE;
+     } cp_state_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_state_debug_data_t f;
+} cp_state_debug_data_u;
+
+
+/*
+ * CP_PROG_COUNTER struct
+ */
+
+#define CP_PROG_COUNTER_COUNTER_SIZE   32
+
+#define CP_PROG_COUNTER_COUNTER_SHIFT  0
+
+#define CP_PROG_COUNTER_COUNTER_MASK   0xffffffff
+
+#define CP_PROG_COUNTER_MASK \
+     (CP_PROG_COUNTER_COUNTER_MASK)
+
+#define CP_PROG_COUNTER(counter) \
+     ((counter << CP_PROG_COUNTER_COUNTER_SHIFT))
+
+#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \
+     ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \
+     cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_prog_counter_t {
+          unsigned int counter                        : CP_PROG_COUNTER_COUNTER_SIZE;
+     } cp_prog_counter_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_prog_counter_t f;
+} cp_prog_counter_u;
+
+
+/*
+ * CP_STAT struct
+ */
+
+#define CP_STAT_MIU_WR_BUSY_SIZE       1
+#define CP_STAT_MIU_RD_REQ_BUSY_SIZE   1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1
+#define CP_STAT_RBIU_BUSY_SIZE         1
+#define CP_STAT_RCIU_BUSY_SIZE         1
+#define CP_STAT_CSF_RING_BUSY_SIZE     1
+#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_CSF_ST_BUSY_SIZE       1
+#define CP_STAT_CSF_BUSY_SIZE          1
+#define CP_STAT_RING_QUEUE_BUSY_SIZE   1
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1
+#define CP_STAT_ST_QUEUE_BUSY_SIZE     1
+#define CP_STAT_PFP_BUSY_SIZE          1
+#define CP_STAT_MEQ_RING_BUSY_SIZE     1
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1
+#define CP_STAT_MIU_WC_STALL_SIZE      1
+#define CP_STAT_CP_NRT_BUSY_SIZE       1
+#define CP_STAT__3D_BUSY_SIZE          1
+#define CP_STAT_ME_BUSY_SIZE           1
+#define CP_STAT_ME_WC_BUSY_SIZE        1
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1
+#define CP_STAT_CP_BUSY_SIZE           1
+
+#define CP_STAT_MIU_WR_BUSY_SHIFT      0
+#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT  1
+#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2
+#define CP_STAT_RBIU_BUSY_SHIFT        3
+#define CP_STAT_RCIU_BUSY_SHIFT        4
+#define CP_STAT_CSF_RING_BUSY_SHIFT    5
+#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6
+#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7
+#define CP_STAT_CSF_ST_BUSY_SHIFT      9
+#define CP_STAT_CSF_BUSY_SHIFT         10
+#define CP_STAT_RING_QUEUE_BUSY_SHIFT  11
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13
+#define CP_STAT_ST_QUEUE_BUSY_SHIFT    16
+#define CP_STAT_PFP_BUSY_SHIFT         17
+#define CP_STAT_MEQ_RING_BUSY_SHIFT    18
+#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19
+#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20
+#define CP_STAT_MIU_WC_STALL_SHIFT     21
+#define CP_STAT_CP_NRT_BUSY_SHIFT      22
+#define CP_STAT__3D_BUSY_SHIFT         23
+#define CP_STAT_ME_BUSY_SHIFT          26
+#define CP_STAT_ME_WC_BUSY_SHIFT       29
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30
+#define CP_STAT_CP_BUSY_SHIFT          31
+
+#define CP_STAT_MIU_WR_BUSY_MASK       0x00000001
+#define CP_STAT_MIU_RD_REQ_BUSY_MASK   0x00000002
+#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004
+#define CP_STAT_RBIU_BUSY_MASK         0x00000008
+#define CP_STAT_RCIU_BUSY_MASK         0x00000010
+#define CP_STAT_CSF_RING_BUSY_MASK     0x00000020
+#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040
+#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080
+#define CP_STAT_CSF_ST_BUSY_MASK       0x00000200
+#define CP_STAT_CSF_BUSY_MASK          0x00000400
+#define CP_STAT_RING_QUEUE_BUSY_MASK   0x00000800
+#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000
+#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000
+#define CP_STAT_ST_QUEUE_BUSY_MASK     0x00010000
+#define CP_STAT_PFP_BUSY_MASK          0x00020000
+#define CP_STAT_MEQ_RING_BUSY_MASK     0x00040000
+#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000
+#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000
+#define CP_STAT_MIU_WC_STALL_MASK      0x00200000
+#define CP_STAT_CP_NRT_BUSY_MASK       0x00400000
+#define CP_STAT__3D_BUSY_MASK          0x00800000
+#define CP_STAT_ME_BUSY_MASK           0x04000000
+#define CP_STAT_ME_WC_BUSY_MASK        0x20000000
+#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000
+#define CP_STAT_CP_BUSY_MASK           0x80000000
+
+#define CP_STAT_MASK \
+     (CP_STAT_MIU_WR_BUSY_MASK | \
+      CP_STAT_MIU_RD_REQ_BUSY_MASK | \
+      CP_STAT_MIU_RD_RETURN_BUSY_MASK | \
+      CP_STAT_RBIU_BUSY_MASK | \
+      CP_STAT_RCIU_BUSY_MASK | \
+      CP_STAT_CSF_RING_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECTS_BUSY_MASK | \
+      CP_STAT_CSF_INDIRECT2_BUSY_MASK | \
+      CP_STAT_CSF_ST_BUSY_MASK | \
+      CP_STAT_CSF_BUSY_MASK | \
+      CP_STAT_RING_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \
+      CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \
+      CP_STAT_ST_QUEUE_BUSY_MASK | \
+      CP_STAT_PFP_BUSY_MASK | \
+      CP_STAT_MEQ_RING_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \
+      CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \
+      CP_STAT_MIU_WC_STALL_MASK | \
+      CP_STAT_CP_NRT_BUSY_MASK | \
+      CP_STAT__3D_BUSY_MASK | \
+      CP_STAT_ME_BUSY_MASK | \
+      CP_STAT_ME_WC_BUSY_MASK | \
+      CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \
+      CP_STAT_CP_BUSY_MASK)
+
+#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \
+     ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \
+      (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \
+      (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \
+      (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \
+      (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \
+      (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \
+      (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \
+      (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \
+      (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \
+      (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \
+      (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \
+      (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \
+      (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \
+      (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \
+      (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \
+      (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \
+      (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \
+      (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \
+      (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \
+      (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \
+      (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \
+      (me_busy << CP_STAT_ME_BUSY_SHIFT) | \
+      (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \
+      (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \
+      (cp_busy << CP_STAT_CP_BUSY_SHIFT))
+
+#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_GET_RBIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_GET_RCIU_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_GET_CSF_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_GET_PFP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_GET__3D_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_GET_ME_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \
+     ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_GET_CP_BUSY(cp_stat) \
+     ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT)
+
+#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT)
+#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT)
+#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT)
+#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT)
+#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT)
+#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT)
+#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT)
+#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT)
+#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT)
+#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT)
+#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT)
+#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT)
+#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \
+     cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+     } cp_stat_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _cp_stat_t {
+          unsigned int cp_busy                        : CP_STAT_CP_BUSY_SIZE;
+          unsigned int miu_wc_track_fifo_empty        : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE;
+          unsigned int me_wc_busy                     : CP_STAT_ME_WC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int me_busy                        : CP_STAT_ME_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int _3d_busy                       : CP_STAT__3D_BUSY_SIZE;
+          unsigned int cp_nrt_busy                    : CP_STAT_CP_NRT_BUSY_SIZE;
+          unsigned int miu_wc_stall                   : CP_STAT_MIU_WC_STALL_SIZE;
+          unsigned int meq_indirect2_busy             : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE;
+          unsigned int meq_indirects_busy             : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE;
+          unsigned int meq_ring_busy                  : CP_STAT_MEQ_RING_BUSY_SIZE;
+          unsigned int pfp_busy                       : CP_STAT_PFP_BUSY_SIZE;
+          unsigned int st_queue_busy                  : CP_STAT_ST_QUEUE_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int indirect2_queue_busy           : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE;
+          unsigned int indirects_queue_busy           : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE;
+          unsigned int ring_queue_busy                : CP_STAT_RING_QUEUE_BUSY_SIZE;
+          unsigned int csf_busy                       : CP_STAT_CSF_BUSY_SIZE;
+          unsigned int csf_st_busy                    : CP_STAT_CSF_ST_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int csf_indirect2_busy             : CP_STAT_CSF_INDIRECT2_BUSY_SIZE;
+          unsigned int csf_indirects_busy             : CP_STAT_CSF_INDIRECTS_BUSY_SIZE;
+          unsigned int csf_ring_busy                  : CP_STAT_CSF_RING_BUSY_SIZE;
+          unsigned int rciu_busy                      : CP_STAT_RCIU_BUSY_SIZE;
+          unsigned int rbiu_busy                      : CP_STAT_RBIU_BUSY_SIZE;
+          unsigned int miu_rd_return_busy             : CP_STAT_MIU_RD_RETURN_BUSY_SIZE;
+          unsigned int miu_rd_req_busy                : CP_STAT_MIU_RD_REQ_BUSY_SIZE;
+          unsigned int miu_wr_busy                    : CP_STAT_MIU_WR_BUSY_SIZE;
+     } cp_stat_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     cp_stat_t f;
+} cp_stat_u;
+
+
+/*
+ * BIOS_0_SCRATCH struct
+ */
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_0_SCRATCH_MASK \
+     (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_0_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \
+     ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \
+     bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_0_scratch_t {
+          unsigned int bios_scratch                   : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_0_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_0_scratch_t f;
+} bios_0_scratch_u;
+
+
+/*
+ * BIOS_1_SCRATCH struct
+ */
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_1_SCRATCH_MASK \
+     (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_1_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \
+     ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \
+     bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_1_scratch_t {
+          unsigned int bios_scratch                   : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_1_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_1_scratch_t f;
+} bios_1_scratch_u;
+
+
+/*
+ * BIOS_2_SCRATCH struct
+ */
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_2_SCRATCH_MASK \
+     (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_2_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \
+     ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \
+     bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_2_scratch_t {
+          unsigned int bios_scratch                   : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_2_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_2_scratch_t f;
+} bios_2_scratch_u;
+
+
+/*
+ * BIOS_3_SCRATCH struct
+ */
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_3_SCRATCH_MASK \
+     (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_3_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \
+     ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \
+     bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_3_scratch_t {
+          unsigned int bios_scratch                   : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_3_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_3_scratch_t f;
+} bios_3_scratch_u;
+
+
+/*
+ * BIOS_4_SCRATCH struct
+ */
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_4_SCRATCH_MASK \
+     (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_4_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \
+     ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \
+     bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_4_scratch_t {
+          unsigned int bios_scratch                   : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_4_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_4_scratch_t f;
+} bios_4_scratch_u;
+
+
+/*
+ * BIOS_5_SCRATCH struct
+ */
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_5_SCRATCH_MASK \
+     (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_5_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \
+     ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \
+     bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_5_scratch_t {
+          unsigned int bios_scratch                   : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_5_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_5_scratch_t f;
+} bios_5_scratch_u;
+
+
+/*
+ * BIOS_6_SCRATCH struct
+ */
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_6_SCRATCH_MASK \
+     (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_6_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \
+     ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \
+     bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_6_scratch_t {
+          unsigned int bios_scratch                   : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_6_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_6_scratch_t f;
+} bios_6_scratch_u;
+
+
+/*
+ * BIOS_7_SCRATCH struct
+ */
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_7_SCRATCH_MASK \
+     (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_7_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \
+     ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \
+     bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_7_scratch_t {
+          unsigned int bios_scratch                   : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_7_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_7_scratch_t f;
+} bios_7_scratch_u;
+
+
+/*
+ * BIOS_8_SCRATCH struct
+ */
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_8_SCRATCH_MASK \
+     (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_8_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \
+     ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \
+     bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_8_scratch_t {
+          unsigned int bios_scratch                   : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_8_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_8_scratch_t f;
+} bios_8_scratch_u;
+
+
+/*
+ * BIOS_9_SCRATCH struct
+ */
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_9_SCRATCH_MASK \
+     (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_9_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \
+     ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \
+     bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_9_scratch_t {
+          unsigned int bios_scratch                   : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_9_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_9_scratch_t f;
+} bios_9_scratch_u;
+
+
+/*
+ * BIOS_10_SCRATCH struct
+ */
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_10_SCRATCH_MASK \
+     (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_10_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \
+     ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \
+     bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_10_scratch_t {
+          unsigned int bios_scratch                   : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_10_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_10_scratch_t f;
+} bios_10_scratch_u;
+
+
+/*
+ * BIOS_11_SCRATCH struct
+ */
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_11_SCRATCH_MASK \
+     (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_11_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \
+     ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \
+     bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_11_scratch_t {
+          unsigned int bios_scratch                   : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_11_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_11_scratch_t f;
+} bios_11_scratch_u;
+
+
+/*
+ * BIOS_12_SCRATCH struct
+ */
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_12_SCRATCH_MASK \
+     (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_12_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \
+     ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \
+     bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_12_scratch_t {
+          unsigned int bios_scratch                   : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_12_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_12_scratch_t f;
+} bios_12_scratch_u;
+
+
+/*
+ * BIOS_13_SCRATCH struct
+ */
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_13_SCRATCH_MASK \
+     (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_13_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \
+     ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \
+     bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_13_scratch_t {
+          unsigned int bios_scratch                   : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_13_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_13_scratch_t f;
+} bios_13_scratch_u;
+
+
+/*
+ * BIOS_14_SCRATCH struct
+ */
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_14_SCRATCH_MASK \
+     (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_14_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \
+     ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \
+     bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_14_scratch_t {
+          unsigned int bios_scratch                   : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_14_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_14_scratch_t f;
+} bios_14_scratch_u;
+
+
+/*
+ * BIOS_15_SCRATCH struct
+ */
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0
+
+#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff
+
+#define BIOS_15_SCRATCH_MASK \
+     (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK)
+
+#define BIOS_15_SCRATCH(bios_scratch) \
+     ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT))
+
+#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \
+     ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \
+     bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bios_15_scratch_t {
+          unsigned int bios_scratch                   : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE;
+     } bios_15_scratch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bios_15_scratch_t f;
+} bios_15_scratch_u;
+
+
+/*
+ * COHER_SIZE_PM4 struct
+ */
+
+#define COHER_SIZE_PM4_SIZE_SIZE       32
+
+#define COHER_SIZE_PM4_SIZE_SHIFT      0
+
+#define COHER_SIZE_PM4_SIZE_MASK       0xffffffff
+
+#define COHER_SIZE_PM4_MASK \
+     (COHER_SIZE_PM4_SIZE_MASK)
+
+#define COHER_SIZE_PM4(size) \
+     ((size << COHER_SIZE_PM4_SIZE_SHIFT))
+
+#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \
+     ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT)
+
+#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \
+     coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_pm4_t {
+          unsigned int size                           : COHER_SIZE_PM4_SIZE_SIZE;
+     } coher_size_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_pm4_t f;
+} coher_size_pm4_u;
+
+
+/*
+ * COHER_BASE_PM4 struct
+ */
+
+#define COHER_BASE_PM4_BASE_SIZE       32
+
+#define COHER_BASE_PM4_BASE_SHIFT      0
+
+#define COHER_BASE_PM4_BASE_MASK       0xffffffff
+
+#define COHER_BASE_PM4_MASK \
+     (COHER_BASE_PM4_BASE_MASK)
+
+#define COHER_BASE_PM4(base) \
+     ((base << COHER_BASE_PM4_BASE_SHIFT))
+
+#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \
+     ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT)
+
+#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \
+     coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_pm4_t {
+          unsigned int base                           : COHER_BASE_PM4_BASE_SIZE;
+     } coher_base_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_pm4_t f;
+} coher_base_pm4_u;
+
+
+/*
+ * COHER_STATUS_PM4 struct
+ */
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_PM4_STATUS_SIZE   1
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_PM4_STATUS_SHIFT  31
+
+#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_PM4_STATUS_MASK   0x80000000
+
+#define COHER_STATUS_PM4_MASK \
+     (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_PM4_STATUS_MASK)
+
+#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_PM4_STATUS_SHIFT))
+
+#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \
+     ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT)
+
+#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \
+     coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+     } coher_status_pm4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_pm4_t {
+          unsigned int status                         : COHER_STATUS_PM4_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE;
+     } coher_status_pm4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_pm4_t f;
+} coher_status_pm4_u;
+
+
+/*
+ * COHER_SIZE_HOST struct
+ */
+
+#define COHER_SIZE_HOST_SIZE_SIZE      32
+
+#define COHER_SIZE_HOST_SIZE_SHIFT     0
+
+#define COHER_SIZE_HOST_SIZE_MASK      0xffffffff
+
+#define COHER_SIZE_HOST_MASK \
+     (COHER_SIZE_HOST_SIZE_MASK)
+
+#define COHER_SIZE_HOST(size) \
+     ((size << COHER_SIZE_HOST_SIZE_SHIFT))
+
+#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \
+     ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT)
+
+#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \
+     coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_size_host_t {
+          unsigned int size                           : COHER_SIZE_HOST_SIZE_SIZE;
+     } coher_size_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_size_host_t f;
+} coher_size_host_u;
+
+
+/*
+ * COHER_BASE_HOST struct
+ */
+
+#define COHER_BASE_HOST_BASE_SIZE      32
+
+#define COHER_BASE_HOST_BASE_SHIFT     0
+
+#define COHER_BASE_HOST_BASE_MASK      0xffffffff
+
+#define COHER_BASE_HOST_MASK \
+     (COHER_BASE_HOST_BASE_MASK)
+
+#define COHER_BASE_HOST(base) \
+     ((base << COHER_BASE_HOST_BASE_SHIFT))
+
+#define COHER_BASE_HOST_GET_BASE(coher_base_host) \
+     ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT)
+
+#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \
+     coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_base_host_t {
+          unsigned int base                           : COHER_BASE_HOST_BASE_SIZE;
+     } coher_base_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_base_host_t f;
+} coher_base_host_u;
+
+
+/*
+ * COHER_STATUS_HOST struct
+ */
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1
+#define COHER_STATUS_HOST_STATUS_SIZE  1
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17
+#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25
+#define COHER_STATUS_HOST_STATUS_SHIFT 31
+
+#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff
+#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100
+#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200
+#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400
+#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800
+#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000
+#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000
+#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000
+#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000
+#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000
+#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000
+#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000
+#define COHER_STATUS_HOST_STATUS_MASK  0x80000000
+
+#define COHER_STATUS_HOST_MASK \
+     (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \
+      COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \
+      COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \
+      COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \
+      COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \
+      COHER_STATUS_HOST_STATUS_MASK)
+
+#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \
+     ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \
+      (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \
+      (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \
+      (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \
+      (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \
+      (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \
+      (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \
+      (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \
+      (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \
+      (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \
+      (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \
+      (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \
+      (status << COHER_STATUS_HOST_STATUS_SHIFT))
+
+#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \
+     ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT)
+
+#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT)
+#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \
+     coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 5;
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+     } coher_status_host_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_status_host_t {
+          unsigned int status                         : COHER_STATUS_HOST_STATUS_SIZE;
+          unsigned int                                : 5;
+          unsigned int tc_action_ena                  : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE;
+          unsigned int                                : 7;
+          unsigned int rb_color_info_ena              : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE;
+          unsigned int dest_base_7_ena                : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE;
+          unsigned int dest_base_6_ena                : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE;
+          unsigned int dest_base_5_ena                : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE;
+          unsigned int dest_base_4_ena                : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE;
+          unsigned int dest_base_3_ena                : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE;
+          unsigned int dest_base_2_ena                : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE;
+          unsigned int dest_base_1_ena                : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE;
+          unsigned int dest_base_0_ena                : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE;
+          unsigned int rb_copy_dest_base_ena          : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE;
+          unsigned int matching_contexts              : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE;
+     } coher_status_host_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_status_host_t f;
+} coher_status_host_u;
+
+
+/*
+ * COHER_DEST_BASE_0 struct
+ */
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12
+
+#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000
+
+#define COHER_DEST_BASE_0_MASK \
+     (COHER_DEST_BASE_0_DEST_BASE_0_MASK)
+
+#define COHER_DEST_BASE_0(dest_base_0) \
+     ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT))
+
+#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \
+     ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \
+     coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+     } coher_dest_base_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_0_t {
+          unsigned int dest_base_0                    : COHER_DEST_BASE_0_DEST_BASE_0_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_0_t f;
+} coher_dest_base_0_u;
+
+
+/*
+ * COHER_DEST_BASE_1 struct
+ */
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12
+
+#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000
+
+#define COHER_DEST_BASE_1_MASK \
+     (COHER_DEST_BASE_1_DEST_BASE_1_MASK)
+
+#define COHER_DEST_BASE_1(dest_base_1) \
+     ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT))
+
+#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \
+     ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \
+     coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+     } coher_dest_base_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_1_t {
+          unsigned int dest_base_1                    : COHER_DEST_BASE_1_DEST_BASE_1_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_1_t f;
+} coher_dest_base_1_u;
+
+
+/*
+ * COHER_DEST_BASE_2 struct
+ */
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12
+
+#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000
+
+#define COHER_DEST_BASE_2_MASK \
+     (COHER_DEST_BASE_2_DEST_BASE_2_MASK)
+
+#define COHER_DEST_BASE_2(dest_base_2) \
+     ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT))
+
+#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \
+     ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \
+     coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+     } coher_dest_base_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_2_t {
+          unsigned int dest_base_2                    : COHER_DEST_BASE_2_DEST_BASE_2_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_2_t f;
+} coher_dest_base_2_u;
+
+
+/*
+ * COHER_DEST_BASE_3 struct
+ */
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12
+
+#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000
+
+#define COHER_DEST_BASE_3_MASK \
+     (COHER_DEST_BASE_3_DEST_BASE_3_MASK)
+
+#define COHER_DEST_BASE_3(dest_base_3) \
+     ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT))
+
+#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \
+     ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \
+     coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+     } coher_dest_base_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_3_t {
+          unsigned int dest_base_3                    : COHER_DEST_BASE_3_DEST_BASE_3_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_3_t f;
+} coher_dest_base_3_u;
+
+
+/*
+ * COHER_DEST_BASE_4 struct
+ */
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12
+
+#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000
+
+#define COHER_DEST_BASE_4_MASK \
+     (COHER_DEST_BASE_4_DEST_BASE_4_MASK)
+
+#define COHER_DEST_BASE_4(dest_base_4) \
+     ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT))
+
+#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \
+     ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \
+     coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+     } coher_dest_base_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_4_t {
+          unsigned int dest_base_4                    : COHER_DEST_BASE_4_DEST_BASE_4_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_4_t f;
+} coher_dest_base_4_u;
+
+
+/*
+ * COHER_DEST_BASE_5 struct
+ */
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12
+
+#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000
+
+#define COHER_DEST_BASE_5_MASK \
+     (COHER_DEST_BASE_5_DEST_BASE_5_MASK)
+
+#define COHER_DEST_BASE_5(dest_base_5) \
+     ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT))
+
+#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \
+     ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \
+     coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+     } coher_dest_base_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_5_t {
+          unsigned int dest_base_5                    : COHER_DEST_BASE_5_DEST_BASE_5_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_5_t f;
+} coher_dest_base_5_u;
+
+
+/*
+ * COHER_DEST_BASE_6 struct
+ */
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12
+
+#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000
+
+#define COHER_DEST_BASE_6_MASK \
+     (COHER_DEST_BASE_6_DEST_BASE_6_MASK)
+
+#define COHER_DEST_BASE_6(dest_base_6) \
+     ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT))
+
+#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \
+     ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \
+     coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+     } coher_dest_base_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_6_t {
+          unsigned int dest_base_6                    : COHER_DEST_BASE_6_DEST_BASE_6_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_6_t f;
+} coher_dest_base_6_u;
+
+
+/*
+ * COHER_DEST_BASE_7 struct
+ */
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12
+
+#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000
+
+#define COHER_DEST_BASE_7_MASK \
+     (COHER_DEST_BASE_7_DEST_BASE_7_MASK)
+
+#define COHER_DEST_BASE_7(dest_base_7) \
+     ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT))
+
+#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \
+     ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \
+     coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int                                : 12;
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+     } coher_dest_base_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _coher_dest_base_7_t {
+          unsigned int dest_base_7                    : COHER_DEST_BASE_7_DEST_BASE_7_SIZE;
+          unsigned int                                : 12;
+     } coher_dest_base_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     coher_dest_base_7_t f;
+} coher_dest_base_7_u;
+
+
+#endif
+
+
+#if !defined (_RBBM_FIDDLE_H)
+#define _RBBM_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * WAIT_UNTIL struct
+ */
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE  1
+#define WAIT_UNTIL_WAIT_VSYNC_SIZE     1
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1
+#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE   1
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1
+#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2
+#define WAIT_UNTIL_WAIT_VSYNC_SHIFT    3
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6
+#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT  10
+#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT  14
+#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT  15
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20
+
+#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK  0x00000002
+#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK  0x00000004
+#define WAIT_UNTIL_WAIT_VSYNC_MASK     0x00000008
+#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010
+#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020
+#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040
+#define WAIT_UNTIL_WAIT_CMDFIFO_MASK   0x00000400
+#define WAIT_UNTIL_WAIT_2D_IDLE_MASK   0x00004000
+#define WAIT_UNTIL_WAIT_3D_IDLE_MASK   0x00008000
+#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000
+#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000
+#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000
+
+#define WAIT_UNTIL_MASK \
+     (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_VSYNC_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \
+      WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \
+      WAIT_UNTIL_WAIT_CMDFIFO_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLE_MASK | \
+      WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \
+      WAIT_UNTIL_CMDFIFO_ENTRIES_MASK)
+
+#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \
+     ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \
+      (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \
+      (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \
+      (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \
+      (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \
+      (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \
+      (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \
+      (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \
+      (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \
+      (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \
+      (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \
+      (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT))
+
+#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \
+     ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \
+     ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT)
+#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \
+     wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 1;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int                                : 2;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 8;
+     } wait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _wait_until_t {
+          unsigned int                                : 8;
+          unsigned int cmdfifo_entries                : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE;
+          unsigned int                                : 2;
+          unsigned int wait_3d_idleclean              : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE;
+          unsigned int wait_2d_idleclean              : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE;
+          unsigned int wait_3d_idle                   : WAIT_UNTIL_WAIT_3D_IDLE_SIZE;
+          unsigned int wait_2d_idle                   : WAIT_UNTIL_WAIT_2D_IDLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_cmdfifo                   : WAIT_UNTIL_WAIT_CMDFIFO_SIZE;
+          unsigned int                                : 3;
+          unsigned int wait_dsply_id2                 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE;
+          unsigned int wait_dsply_id1                 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE;
+          unsigned int wait_dsply_id0                 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE;
+          unsigned int wait_vsync                     : WAIT_UNTIL_WAIT_VSYNC_SIZE;
+          unsigned int wait_fe_vsync                  : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE;
+          unsigned int wait_re_vsync                  : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE;
+          unsigned int                                : 1;
+     } wait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     wait_until_t f;
+} wait_until_u;
+
+
+/*
+ * RBBM_ISYNC_CNTL struct
+ */
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5
+
+#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010
+#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020
+
+#define RBBM_ISYNC_CNTL_MASK \
+     (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \
+      RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK)
+
+#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \
+     ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \
+      (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT))
+
+#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \
+     ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT)
+#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \
+     rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 4;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int                                : 26;
+     } rbbm_isync_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_isync_cntl_t {
+          unsigned int                                : 26;
+          unsigned int isync_cpscratch_idlegui        : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE;
+          unsigned int isync_wait_idlegui             : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE;
+          unsigned int                                : 4;
+     } rbbm_isync_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_isync_cntl_t f;
+} rbbm_isync_cntl_u;
+
+
+/*
+ * RBBM_STATUS struct
+ */
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5
+#define RBBM_STATUS_TC_BUSY_SIZE       1
+#define RBBM_STATUS_HIRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CPRQ_PENDING_SIZE  1
+#define RBBM_STATUS_CFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_PFRQ_PENDING_SIZE  1
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1
+#define RBBM_STATUS_RBBM_WU_BUSY_SIZE  1
+#define RBBM_STATUS_CP_NRT_BUSY_SIZE   1
+#define RBBM_STATUS_MH_BUSY_SIZE       1
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1
+#define RBBM_STATUS_SX_BUSY_SIZE       1
+#define RBBM_STATUS_TPC_BUSY_SIZE      1
+#define RBBM_STATUS_SC_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_PA_BUSY_SIZE       1
+#define RBBM_STATUS_VGT_BUSY_SIZE      1
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1
+#define RBBM_STATUS_RB_CNTX_BUSY_SIZE  1
+#define RBBM_STATUS_GUI_ACTIVE_SIZE    1
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0
+#define RBBM_STATUS_TC_BUSY_SHIFT      5
+#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8
+#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9
+#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10
+#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12
+#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14
+#define RBBM_STATUS_CP_NRT_BUSY_SHIFT  16
+#define RBBM_STATUS_MH_BUSY_SHIFT      18
+#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19
+#define RBBM_STATUS_SX_BUSY_SHIFT      21
+#define RBBM_STATUS_TPC_BUSY_SHIFT     22
+#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24
+#define RBBM_STATUS_PA_BUSY_SHIFT      25
+#define RBBM_STATUS_VGT_BUSY_SHIFT     26
+#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27
+#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28
+#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30
+#define RBBM_STATUS_GUI_ACTIVE_SHIFT   31
+
+#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f
+#define RBBM_STATUS_TC_BUSY_MASK       0x00000020
+#define RBBM_STATUS_HIRQ_PENDING_MASK  0x00000100
+#define RBBM_STATUS_CPRQ_PENDING_MASK  0x00000200
+#define RBBM_STATUS_CFRQ_PENDING_MASK  0x00000400
+#define RBBM_STATUS_PFRQ_PENDING_MASK  0x00000800
+#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000
+#define RBBM_STATUS_RBBM_WU_BUSY_MASK  0x00004000
+#define RBBM_STATUS_CP_NRT_BUSY_MASK   0x00010000
+#define RBBM_STATUS_MH_BUSY_MASK       0x00040000
+#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000
+#define RBBM_STATUS_SX_BUSY_MASK       0x00200000
+#define RBBM_STATUS_TPC_BUSY_MASK      0x00400000
+#define RBBM_STATUS_SC_CNTX_BUSY_MASK  0x01000000
+#define RBBM_STATUS_PA_BUSY_MASK       0x02000000
+#define RBBM_STATUS_VGT_BUSY_MASK      0x04000000
+#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000
+#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000
+#define RBBM_STATUS_RB_CNTX_BUSY_MASK  0x40000000
+#define RBBM_STATUS_GUI_ACTIVE_MASK    0x80000000
+
+#define RBBM_STATUS_MASK \
+     (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \
+      RBBM_STATUS_TC_BUSY_MASK | \
+      RBBM_STATUS_HIRQ_PENDING_MASK | \
+      RBBM_STATUS_CPRQ_PENDING_MASK | \
+      RBBM_STATUS_CFRQ_PENDING_MASK | \
+      RBBM_STATUS_PFRQ_PENDING_MASK | \
+      RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \
+      RBBM_STATUS_RBBM_WU_BUSY_MASK | \
+      RBBM_STATUS_CP_NRT_BUSY_MASK | \
+      RBBM_STATUS_MH_BUSY_MASK | \
+      RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \
+      RBBM_STATUS_SX_BUSY_MASK | \
+      RBBM_STATUS_TPC_BUSY_MASK | \
+      RBBM_STATUS_SC_CNTX_BUSY_MASK | \
+      RBBM_STATUS_PA_BUSY_MASK | \
+      RBBM_STATUS_VGT_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \
+      RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \
+      RBBM_STATUS_RB_CNTX_BUSY_MASK | \
+      RBBM_STATUS_GUI_ACTIVE_MASK)
+
+#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \
+     ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \
+      (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \
+      (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \
+      (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \
+      (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \
+      (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \
+      (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \
+      (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \
+      (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \
+      (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \
+      (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \
+      (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \
+      (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \
+      (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \
+      (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \
+      (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \
+      (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \
+      (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \
+      (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \
+      (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT))
+
+#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \
+     ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT)
+#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT)
+#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT)
+#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT)
+#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT)
+#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT)
+#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT)
+#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT)
+#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \
+     rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 2;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+     } rbbm_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_status_t {
+          unsigned int gui_active                     : RBBM_STATUS_GUI_ACTIVE_SIZE;
+          unsigned int rb_cntx_busy                   : RBBM_STATUS_RB_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int sq_cntx0_busy                  : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE;
+          unsigned int sq_cntx17_busy                 : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE;
+          unsigned int vgt_busy                       : RBBM_STATUS_VGT_BUSY_SIZE;
+          unsigned int pa_busy                        : RBBM_STATUS_PA_BUSY_SIZE;
+          unsigned int sc_cntx_busy                   : RBBM_STATUS_SC_CNTX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_busy                       : RBBM_STATUS_TPC_BUSY_SIZE;
+          unsigned int sx_busy                        : RBBM_STATUS_SX_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_coherency_busy              : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE;
+          unsigned int mh_busy                        : RBBM_STATUS_MH_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int cp_nrt_busy                    : RBBM_STATUS_CP_NRT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int rbbm_wu_busy                   : RBBM_STATUS_RBBM_WU_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int vgt_busy_no_dma                : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE;
+          unsigned int pfrq_pending                   : RBBM_STATUS_PFRQ_PENDING_SIZE;
+          unsigned int cfrq_pending                   : RBBM_STATUS_CFRQ_PENDING_SIZE;
+          unsigned int cprq_pending                   : RBBM_STATUS_CPRQ_PENDING_SIZE;
+          unsigned int hirq_pending                   : RBBM_STATUS_HIRQ_PENDING_SIZE;
+          unsigned int                                : 2;
+          unsigned int tc_busy                        : RBBM_STATUS_TC_BUSY_SIZE;
+          unsigned int cmdfifo_avail                  : RBBM_STATUS_CMDFIFO_AVAIL_SIZE;
+     } rbbm_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_status_t f;
+} rbbm_status_u;
+
+
+/*
+ * RBBM_DSPLY struct
+ */
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30
+
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002
+#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004
+#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020
+#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040
+#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080
+#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800
+#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000
+#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000
+#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000
+#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000
+#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000
+#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000
+#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000
+#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000
+#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000
+#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000
+
+#define RBBM_DSPLY_MASK \
+     (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \
+      RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \
+      RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \
+      RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \
+      RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \
+      RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK)
+
+#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \
+     ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \
+      (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \
+      (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \
+      (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \
+      (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \
+      (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \
+      (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \
+      (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \
+      (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \
+      (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \
+      (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \
+      (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \
+      (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \
+      (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \
+      (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \
+      (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \
+      (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \
+      (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \
+      (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \
+      (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \
+      (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \
+      (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \
+      (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \
+      (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \
+      (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT))
+
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \
+     ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT)
+#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \
+     rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+     } rbbm_dsply_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_dsply_t {
+          unsigned int dmi_ch4_num_bufs               : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE;
+          unsigned int dmi_ch4_sw_cntl                : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE;
+          unsigned int dmi_ch4_use_bufid2             : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE;
+          unsigned int dmi_ch4_use_bufid1             : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE;
+          unsigned int dmi_ch4_use_bufid0             : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE;
+          unsigned int dmi_ch3_num_bufs               : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE;
+          unsigned int dmi_ch3_sw_cntl                : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE;
+          unsigned int dmi_ch3_use_bufid2             : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE;
+          unsigned int dmi_ch3_use_bufid1             : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE;
+          unsigned int dmi_ch3_use_bufid0             : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE;
+          unsigned int                                : 2;
+          unsigned int dmi_channel_select             : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE;
+          unsigned int dmi_ch2_num_bufs               : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE;
+          unsigned int dmi_ch2_sw_cntl                : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE;
+          unsigned int dmi_ch2_use_bufid2             : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE;
+          unsigned int dmi_ch2_use_bufid1             : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE;
+          unsigned int dmi_ch2_use_bufid0             : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE;
+          unsigned int dmi_ch1_num_bufs               : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE;
+          unsigned int dmi_ch1_sw_cntl                : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE;
+          unsigned int dmi_ch1_use_bufid2             : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE;
+          unsigned int dmi_ch1_use_bufid1             : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE;
+          unsigned int dmi_ch1_use_bufid0             : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE;
+          unsigned int sel_dmi_vsync_valid            : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE;
+          unsigned int sel_dmi_active_bufid2          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE;
+          unsigned int sel_dmi_active_bufid1          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE;
+          unsigned int sel_dmi_active_bufid0          : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE;
+     } rbbm_dsply_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_dsply_t f;
+} rbbm_dsply_u;
+
+
+/*
+ * RBBM_RENDER_LATEST struct
+ */
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24
+
+#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003
+#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300
+#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000
+#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000
+
+#define RBBM_RENDER_LATEST_MASK \
+     (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \
+      RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK)
+
+#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \
+     ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \
+      (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \
+      (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \
+      (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT))
+
+#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \
+     ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT)
+#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \
+     rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+     } rbbm_render_latest_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_render_latest_t {
+          unsigned int                                : 6;
+          unsigned int dmi_ch4_buffer_id              : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch3_buffer_id              : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch2_buffer_id              : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE;
+          unsigned int                                : 6;
+          unsigned int dmi_ch1_buffer_id              : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE;
+     } rbbm_render_latest_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_render_latest_t f;
+} rbbm_render_latest_u;
+
+
+/*
+ * RBBM_RTL_RELEASE struct
+ */
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32
+
+#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0
+
+#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff
+
+#define RBBM_RTL_RELEASE_MASK \
+     (RBBM_RTL_RELEASE_CHANGELIST_MASK)
+
+#define RBBM_RTL_RELEASE(changelist) \
+     ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT))
+
+#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \
+     ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \
+     rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_rtl_release_t {
+          unsigned int changelist                     : RBBM_RTL_RELEASE_CHANGELIST_SIZE;
+     } rbbm_rtl_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_rtl_release_t f;
+} rbbm_rtl_release_u;
+
+
+/*
+ * RBBM_PATCH_RELEASE struct
+ */
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24
+
+#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff
+#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000
+#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000
+
+#define RBBM_PATCH_RELEASE_MASK \
+     (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \
+      RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \
+      RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK)
+
+#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \
+     ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \
+      (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \
+      (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT))
+
+#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \
+     ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT)
+#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \
+     rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+     } rbbm_patch_release_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_patch_release_t {
+          unsigned int customer_id                    : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE;
+          unsigned int patch_selection                : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE;
+          unsigned int patch_revision                 : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE;
+     } rbbm_patch_release_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_patch_release_t f;
+} rbbm_patch_release_u;
+
+
+/*
+ * RBBM_AUXILIARY_CONFIG struct
+ */
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0
+
+#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff
+
+#define RBBM_AUXILIARY_CONFIG_MASK \
+     (RBBM_AUXILIARY_CONFIG_RESERVED_MASK)
+
+#define RBBM_AUXILIARY_CONFIG(reserved) \
+     ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT))
+
+#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \
+     ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \
+     rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_auxiliary_config_t {
+          unsigned int reserved                       : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE;
+     } rbbm_auxiliary_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_auxiliary_config_t f;
+} rbbm_auxiliary_config_u;
+
+
+/*
+ * RBBM_PERIPHID0 struct
+ */
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8
+
+#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0
+
+#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff
+
+#define RBBM_PERIPHID0_MASK \
+     (RBBM_PERIPHID0_PARTNUMBER0_MASK)
+
+#define RBBM_PERIPHID0(partnumber0) \
+     ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT))
+
+#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \
+     ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \
+     rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid0_t {
+          unsigned int                                : 24;
+          unsigned int partnumber0                    : RBBM_PERIPHID0_PARTNUMBER0_SIZE;
+     } rbbm_periphid0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid0_t f;
+} rbbm_periphid0_u;
+
+
+/*
+ * RBBM_PERIPHID1 struct
+ */
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4
+#define RBBM_PERIPHID1_DESIGNER0_SIZE  4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0
+#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4
+
+#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f
+#define RBBM_PERIPHID1_DESIGNER0_MASK  0x000000f0
+
+#define RBBM_PERIPHID1_MASK \
+     (RBBM_PERIPHID1_PARTNUMBER1_MASK | \
+      RBBM_PERIPHID1_DESIGNER0_MASK)
+
+#define RBBM_PERIPHID1(partnumber1, designer0) \
+     ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \
+      (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT))
+
+#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \
+     ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT)
+#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \
+     rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid1_t {
+          unsigned int                                : 24;
+          unsigned int designer0                      : RBBM_PERIPHID1_DESIGNER0_SIZE;
+          unsigned int partnumber1                    : RBBM_PERIPHID1_PARTNUMBER1_SIZE;
+     } rbbm_periphid1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid1_t f;
+} rbbm_periphid1_u;
+
+
+/*
+ * RBBM_PERIPHID2 struct
+ */
+
+#define RBBM_PERIPHID2_DESIGNER1_SIZE  4
+#define RBBM_PERIPHID2_REVISION_SIZE   4
+
+#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0
+#define RBBM_PERIPHID2_REVISION_SHIFT  4
+
+#define RBBM_PERIPHID2_DESIGNER1_MASK  0x0000000f
+#define RBBM_PERIPHID2_REVISION_MASK   0x000000f0
+
+#define RBBM_PERIPHID2_MASK \
+     (RBBM_PERIPHID2_DESIGNER1_MASK | \
+      RBBM_PERIPHID2_REVISION_MASK)
+
+#define RBBM_PERIPHID2(designer1, revision) \
+     ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \
+      (revision << RBBM_PERIPHID2_REVISION_SHIFT))
+
+#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \
+     ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT)
+
+#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT)
+#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \
+     rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid2_t {
+          unsigned int                                : 24;
+          unsigned int revision                       : RBBM_PERIPHID2_REVISION_SIZE;
+          unsigned int designer1                      : RBBM_PERIPHID2_DESIGNER1_SIZE;
+     } rbbm_periphid2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid2_t f;
+} rbbm_periphid2_u;
+
+
+/*
+ * RBBM_PERIPHID3 struct
+ */
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2
+#define RBBM_PERIPHID3_CONTINUATION_SIZE 1
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2
+#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4
+#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7
+
+#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003
+#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c
+#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030
+#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080
+
+#define RBBM_PERIPHID3_MASK \
+     (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \
+      RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \
+      RBBM_PERIPHID3_MH_INTERFACE_MASK | \
+      RBBM_PERIPHID3_CONTINUATION_MASK)
+
+#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \
+     ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \
+      (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \
+      (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \
+      (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT))
+
+#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \
+     ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT)
+#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \
+     rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int                                : 1;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 24;
+     } rbbm_periphid3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_periphid3_t {
+          unsigned int                                : 24;
+          unsigned int continuation                   : RBBM_PERIPHID3_CONTINUATION_SIZE;
+          unsigned int                                : 1;
+          unsigned int mh_interface                   : RBBM_PERIPHID3_MH_INTERFACE_SIZE;
+          unsigned int garb_slave_interface           : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE;
+          unsigned int rbbm_host_interface            : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE;
+     } rbbm_periphid3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_periphid3_t f;
+} rbbm_periphid3_u;
+
+
+/*
+ * RBBM_CNTL struct
+ */
+
+#define RBBM_CNTL_READ_TIMEOUT_SIZE    8
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9
+
+#define RBBM_CNTL_READ_TIMEOUT_SHIFT   0
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8
+
+#define RBBM_CNTL_READ_TIMEOUT_MASK    0x000000ff
+#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00
+
+#define RBBM_CNTL_MASK \
+     (RBBM_CNTL_READ_TIMEOUT_MASK | \
+      RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK)
+
+#define RBBM_CNTL(read_timeout, regclk_deassert_time) \
+     ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \
+      (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT))
+
+#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \
+     ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT)
+#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \
+     rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int                                : 15;
+     } rbbm_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_cntl_t {
+          unsigned int                                : 15;
+          unsigned int regclk_deassert_time           : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE;
+          unsigned int read_timeout                   : RBBM_CNTL_READ_TIMEOUT_SIZE;
+     } rbbm_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_cntl_t f;
+} rbbm_cntl_u;
+
+
+/*
+ * RBBM_SKEW_CNTL struct
+ */
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0
+#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5
+
+#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f
+#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0
+
+#define RBBM_SKEW_CNTL_MASK \
+     (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \
+      RBBM_SKEW_CNTL_SKEW_COUNT_MASK)
+
+#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \
+     ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \
+      (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT))
+
+#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \
+     ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT)
+#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \
+     rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int                                : 22;
+     } rbbm_skew_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_skew_cntl_t {
+          unsigned int                                : 22;
+          unsigned int skew_count                     : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE;
+          unsigned int skew_top_threshold             : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE;
+     } rbbm_skew_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_skew_cntl_t f;
+} rbbm_skew_cntl_u;
+
+
+/*
+ * RBBM_SOFT_RESET struct
+ */
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16
+
+#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001
+#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004
+#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008
+#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010
+#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020
+#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040
+#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000
+#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000
+#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000
+
+#define RBBM_SOFT_RESET_MASK \
+     (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \
+      RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK)
+
+#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \
+     ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \
+      (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \
+      (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \
+      (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \
+      (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \
+      (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \
+      (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \
+      (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \
+      (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT))
+
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \
+     ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT)
+#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \
+     rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int                                : 15;
+     } rbbm_soft_reset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_soft_reset_t {
+          unsigned int                                : 15;
+          unsigned int soft_reset_vgt                 : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE;
+          unsigned int soft_reset_sc                  : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE;
+          unsigned int                                : 2;
+          unsigned int soft_reset_cib                 : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE;
+          unsigned int                                : 5;
+          unsigned int soft_reset_sx                  : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE;
+          unsigned int soft_reset_sq                  : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE;
+          unsigned int soft_reset_bc                  : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE;
+          unsigned int soft_reset_mh                  : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE;
+          unsigned int soft_reset_pa                  : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE;
+          unsigned int                                : 1;
+          unsigned int soft_reset_cp                  : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE;
+     } rbbm_soft_reset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_soft_reset_t f;
+} rbbm_soft_reset_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE1 struct
+ */
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31
+
+#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800
+#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000
+#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000
+#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000
+#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000
+#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000
+#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000
+#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000
+#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000
+#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000
+#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000
+#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000
+#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000
+#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000
+#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000
+#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000
+#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000
+#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000
+#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000
+#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000
+
+#define RBBM_PM_OVERRIDE1_MASK \
+     (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \
+     ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \
+      (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \
+      (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \
+      (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \
+     ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \
+     rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override1_t {
+          unsigned int mh_tcroq_sclk_pm_override      : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mmu_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int mh_mh_sclk_pm_override         : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_sclk_pm_override            : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rb_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int spi_sclk_pm_override           : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_reg_sclk_pm_override      : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int cp_g_sclk_pm_override          : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tp_tp_sclk_pm_override         : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_read_sclk_pm_override  : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tcb_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcf_tca_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tpc_tpc_sclk_pm_override       : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_reg_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcd_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tcm_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int tcm_tco_sclk_pm_override       : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sx_sclk_pm_override            : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_sq_sclk_pm_override         : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_const_mem_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_fifos_sclk_pm_override  : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sq_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_v0_sclk_pm_override         : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sp_top_sclk_pm_override        : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_sclk_pm_override            : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int sc_reg_sclk_pm_override        : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int rbbm_ahbclk_pm_override        : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override1_t f;
+} rbbm_pm_override1_u;
+
+
+/*
+ * RBBM_PM_OVERRIDE2 struct
+ */
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11
+
+#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001
+#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002
+#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004
+#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008
+#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010
+#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020
+#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040
+#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400
+#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800
+
+#define RBBM_PM_OVERRIDE2_MASK \
+     (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \
+      RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK)
+
+#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \
+     ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \
+      (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \
+      (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \
+      (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \
+      (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \
+      (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT))
+
+#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \
+     ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT)
+#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \
+     rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int                                : 20;
+     } rbbm_pm_override2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_pm_override2_t {
+          unsigned int                                : 20;
+          unsigned int gc_ga_gmem3_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem2_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem1_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE;
+          unsigned int gc_ga_gmem0_pm_override        : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE;
+          unsigned int perm_sclk_pm_override          : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int debug_perf_sclk_pm_override    : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_vgt_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_fifos_sclk_pm_override     : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int vgt_reg_sclk_pm_override       : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_ag_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_pa_sclk_pm_override         : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE;
+          unsigned int pa_reg_sclk_pm_override        : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE;
+     } rbbm_pm_override2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_pm_override2_t f;
+} rbbm_pm_override2_u;
+
+
+/*
+ * GC_SYS_IDLE struct
+ */
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31
+
+#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000
+#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000
+#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000
+#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000
+
+#define GC_SYS_IDLE_MASK \
+     (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \
+      GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \
+      GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK)
+
+#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \
+     ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \
+      (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \
+      (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \
+      (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \
+      (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \
+      (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \
+      (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT))
+
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \
+     ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT)
+#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \
+     gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+     } gc_sys_idle_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gc_sys_idle_t {
+          unsigned int gc_sys_idle_override           : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE;
+          unsigned int gc_sys_wait_dmi_override       : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE;
+          unsigned int gc_sys_urgent_ramp_override    : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gc_sys_wait_dmi                : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE;
+          unsigned int gc_sys_urgent_ramp             : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE;
+          unsigned int                                : 2;
+          unsigned int gc_sys_wait_dmi_mask           : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE;
+          unsigned int gc_sys_idle_delay              : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE;
+     } gc_sys_idle_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gc_sys_idle_t f;
+} gc_sys_idle_u;
+
+
+/*
+ * NQWAIT_UNTIL struct
+ */
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0
+
+#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001
+
+#define NQWAIT_UNTIL_MASK \
+     (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK)
+
+#define NQWAIT_UNTIL(wait_gui_idle) \
+     ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT))
+
+#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \
+     ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \
+     nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+          unsigned int                                : 31;
+     } nqwait_until_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _nqwait_until_t {
+          unsigned int                                : 31;
+          unsigned int wait_gui_idle                  : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE;
+     } nqwait_until_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     nqwait_until_t f;
+} nqwait_until_u;
+
+
+/*
+ * RBBM_DEBUG_OUT struct
+ */
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0
+
+#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff
+
+#define RBBM_DEBUG_OUT_MASK \
+     (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK)
+
+#define RBBM_DEBUG_OUT(debug_bus_out) \
+     ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT))
+
+#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \
+     ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \
+     rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_out_t {
+          unsigned int debug_bus_out                  : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE;
+     } rbbm_debug_out_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_out_t f;
+} rbbm_debug_out_u;
+
+
+/*
+ * RBBM_DEBUG_CNTL struct
+ */
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8
+#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28
+
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f
+#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00
+#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000
+#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000
+#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000
+
+#define RBBM_DEBUG_CNTL_MASK \
+     (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \
+      RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK)
+
+#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \
+     ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \
+      (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \
+      (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \
+      (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \
+      (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \
+      (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT))
+
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \
+     ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT)
+#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \
+     rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int                                : 3;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+     } rbbm_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_cntl_t {
+          unsigned int gpio_byte_lane_enb             : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE;
+          unsigned int gpio_sub_block_sel             : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int gpio_sub_block_addr            : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int sw_enable                      : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE;
+          unsigned int sub_block_sel                  : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE;
+          unsigned int                                : 2;
+          unsigned int sub_block_addr                 : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE;
+     } rbbm_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_cntl_t f;
+} rbbm_debug_cntl_u;
+
+
+/*
+ * RBBM_DEBUG struct
+ */
+
+#define RBBM_DEBUG_IGNORE_RTR_SIZE     1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1
+
+#define RBBM_DEBUG_IGNORE_RTR_SHIFT    1
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31
+
+#define RBBM_DEBUG_IGNORE_RTR_MASK     0x00000002
+#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004
+#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008
+#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010
+#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00
+#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000
+#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000
+#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000
+#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000
+#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000
+#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000
+#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000
+#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000
+#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000
+
+#define RBBM_DEBUG_MASK \
+     (RBBM_DEBUG_IGNORE_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \
+      RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \
+      RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \
+      RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \
+      RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \
+      RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK)
+
+#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \
+     ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \
+      (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \
+      (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \
+      (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \
+      (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \
+      (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \
+      (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \
+      (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \
+      (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \
+      (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \
+      (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \
+      (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \
+      (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT))
+
+#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \
+     ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT)
+#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT)
+#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT)
+#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \
+     rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int                                : 1;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int                                : 3;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 4;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int                                : 6;
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+     } rbbm_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_debug_t {
+          unsigned int ignore_sx_rbbm_busy            : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE;
+          unsigned int                                : 6;
+          unsigned int clients_for_nrt_rtr            : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE;
+          unsigned int clients_for_nrt_rtr_for_hi     : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE;
+          unsigned int sq_rbbm_nrtrtr                 : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE;
+          unsigned int vgt_rbbm_nrtrtr                : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE;
+          unsigned int cp_rbbm_nrtrtr                 : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE;
+          unsigned int ignore_sq_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_vgt_rbbm_nrtrtr_for_hi  : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_cp_rbbm_nrtrtr_for_hi   : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE;
+          unsigned int ignore_rtr_for_hi              : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE;
+          unsigned int                                : 4;
+          unsigned int hysteresis_nrt_gui_active      : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE;
+          unsigned int                                : 3;
+          unsigned int ignore_cp_sched_nq_hi          : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE;
+          unsigned int ignore_cp_sched_isync          : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE;
+          unsigned int ignore_cp_sched_wu             : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE;
+          unsigned int ignore_rtr                     : RBBM_DEBUG_IGNORE_RTR_SIZE;
+          unsigned int                                : 1;
+     } rbbm_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_debug_t f;
+} rbbm_debug_u;
+
+
+/*
+ * RBBM_READ_ERROR struct
+ */
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15
+#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1
+#define RBBM_READ_ERROR_READ_ERROR_SIZE 1
+
+#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2
+#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30
+#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31
+
+#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc
+#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000
+#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000
+
+#define RBBM_READ_ERROR_MASK \
+     (RBBM_READ_ERROR_READ_ADDRESS_MASK | \
+      RBBM_READ_ERROR_READ_REQUESTER_MASK | \
+      RBBM_READ_ERROR_READ_ERROR_MASK)
+
+#define RBBM_READ_ERROR(read_address, read_requester, read_error) \
+     ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \
+      (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \
+      (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT))
+
+#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \
+     ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT)
+#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \
+     rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int                                : 2;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+     } rbbm_read_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_read_error_t {
+          unsigned int read_error                     : RBBM_READ_ERROR_READ_ERROR_SIZE;
+          unsigned int read_requester                 : RBBM_READ_ERROR_READ_REQUESTER_SIZE;
+          unsigned int                                : 13;
+          unsigned int read_address                   : RBBM_READ_ERROR_READ_ADDRESS_SIZE;
+          unsigned int                                : 2;
+     } rbbm_read_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_read_error_t f;
+} rbbm_read_error_u;
+
+
+/*
+ * RBBM_WAIT_IDLE_CLOCKS struct
+ */
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0
+
+#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff
+
+#define RBBM_WAIT_IDLE_CLOCKS_MASK \
+     (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK)
+
+#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \
+     ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT))
+
+#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \
+     ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \
+     rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+          unsigned int                                : 24;
+     } rbbm_wait_idle_clocks_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_wait_idle_clocks_t {
+          unsigned int                                : 24;
+          unsigned int wait_idle_clocks_nrt           : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE;
+     } rbbm_wait_idle_clocks_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_wait_idle_clocks_t f;
+} rbbm_wait_idle_clocks_u;
+
+
+/*
+ * RBBM_INT_CNTL struct
+ */
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19
+
+#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001
+#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002
+#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000
+
+#define RBBM_INT_CNTL_MASK \
+     (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \
+      RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \
+      RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK)
+
+#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \
+     ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \
+      (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \
+      (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT))
+
+#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \
+     ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT)
+#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \
+     rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_cntl_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_mask              : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_mask        : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE;
+          unsigned int rderr_int_mask                 : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE;
+     } rbbm_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_cntl_t f;
+} rbbm_int_cntl_u;
+
+
+/*
+ * RBBM_INT_STATUS struct
+ */
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19
+
+#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001
+#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002
+#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000
+
+#define RBBM_INT_STATUS_MASK \
+     (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \
+      RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \
+      RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK)
+
+#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \
+     ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \
+      (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \
+      (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT))
+
+#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \
+     ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT)
+#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \
+     rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_status_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_stat              : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_stat        : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE;
+          unsigned int rderr_int_stat                 : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE;
+     } rbbm_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_status_t f;
+} rbbm_int_status_u;
+
+
+/*
+ * RBBM_INT_ACK struct
+ */
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19
+
+#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001
+#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002
+#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000
+
+#define RBBM_INT_ACK_MASK \
+     (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \
+      RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \
+      RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK)
+
+#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \
+     ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \
+      (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \
+      (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT))
+
+#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \
+     ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT)
+#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \
+     rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 12;
+     } rbbm_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_int_ack_t {
+          unsigned int                                : 12;
+          unsigned int gui_idle_int_ack               : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE;
+          unsigned int                                : 17;
+          unsigned int display_update_int_ack         : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE;
+          unsigned int rderr_int_ack                  : RBBM_INT_ACK_RDERR_INT_ACK_SIZE;
+     } rbbm_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_int_ack_t f;
+} rbbm_int_ack_u;
+
+
+/*
+ * MASTER_INT_SIGNAL struct
+ */
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26
+#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31
+
+#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020
+#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000
+#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000
+#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000
+
+#define MASTER_INT_SIGNAL_MASK \
+     (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \
+      MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK)
+
+#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \
+     ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \
+      (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \
+      (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \
+      (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT))
+
+#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \
+     ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT)
+#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \
+     master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int                                : 5;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+     } master_int_signal_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _master_int_signal_t {
+          unsigned int rbbm_int_stat                  : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE;
+          unsigned int cp_int_stat                    : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE;
+          unsigned int                                : 3;
+          unsigned int sq_int_stat                    : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE;
+          unsigned int                                : 20;
+          unsigned int mh_int_stat                    : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE;
+          unsigned int                                : 5;
+     } master_int_signal_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     master_int_signal_t f;
+} master_int_signal_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_SELECT struct
+ */
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f
+
+#define RBBM_PERFCOUNTER1_SELECT_MASK \
+     (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK)
+
+#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \
+     ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT))
+
+#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \
+     ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \
+     rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+          unsigned int                                : 26;
+     } rbbm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_select_t {
+          unsigned int                                : 26;
+          unsigned int perf_count1_sel                : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE;
+     } rbbm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_select_t f;
+} rbbm_perfcounter1_select_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_LO struct
+ */
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff
+
+#define RBBM_PERFCOUNTER1_LO_MASK \
+     (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK)
+
+#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \
+     ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT))
+
+#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \
+     ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \
+     rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_lo_t {
+          unsigned int perf_count1_lo                 : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE;
+     } rbbm_perfcounter1_lo_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_lo_t f;
+} rbbm_perfcounter1_lo_u;
+
+
+/*
+ * RBBM_PERFCOUNTER1_HI struct
+ */
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0
+
+#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff
+
+#define RBBM_PERFCOUNTER1_HI_MASK \
+     (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK)
+
+#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \
+     ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT))
+
+#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \
+     ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \
+     rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+          unsigned int                                : 16;
+     } rbbm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rbbm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count1_hi                 : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE;
+     } rbbm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rbbm_perfcounter1_hi_t f;
+} rbbm_perfcounter1_hi_u;
+
+
+#endif
+
+
+#if !defined (_MH_FIDDLE_H)
+#define _MH_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * MH_ARBITER_CONFIG struct
+ */
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9
+#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26
+
+#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f
+#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040
+#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080
+#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100
+#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200
+#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00
+#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000
+#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000
+#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000
+#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000
+#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000
+#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000
+#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000
+#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000
+
+#define MH_ARBITER_CONFIG_MASK \
+     (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \
+      MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \
+      MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \
+      MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \
+      MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK)
+
+#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \
+     ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \
+      (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \
+      (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \
+      (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \
+      (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \
+      (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \
+      (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \
+      (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \
+      (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \
+      (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \
+      (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \
+      (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \
+      (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \
+      (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT))
+
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \
+     ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT)
+#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)
+#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \
+     mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int                                : 5;
+     } mh_arbiter_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_arbiter_config_t {
+          unsigned int                                : 5;
+          unsigned int pa_clnt_enable                 : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE;
+          unsigned int rb_clnt_enable                 : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE;
+          unsigned int tc_clnt_enable                 : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE;
+          unsigned int vgt_clnt_enable                : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE;
+          unsigned int cp_clnt_enable                 : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE;
+          unsigned int in_flight_limit                : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE;
+          unsigned int in_flight_limit_enable         : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE;
+          unsigned int tc_arb_hold_enable             : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE;
+          unsigned int tc_reorder_enable              : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int page_size                      : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE;
+          unsigned int l2_arb_control                 : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE;
+          unsigned int l1_arb_hold_enable             : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE;
+          unsigned int l1_arb_enable                  : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE;
+          unsigned int same_page_granularity          : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE;
+          unsigned int same_page_limit                : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE;
+     } mh_arbiter_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_arbiter_config_t f;
+} mh_arbiter_config_u;
+
+
+/*
+ * MH_CLNT_AXI_ID_REUSE struct
+ */
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12
+
+#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007
+#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008
+#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070
+#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080
+#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700
+#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800
+#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000
+
+#define MH_CLNT_AXI_ID_REUSE_MASK \
+     (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \
+      MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \
+      MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \
+      MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK)
+
+#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \
+     ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \
+      (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \
+      (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \
+      (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \
+      (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \
+      (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \
+      (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT))
+
+#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \
+     ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT)
+#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \
+     mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int                                : 17;
+     } mh_clnt_axi_id_reuse_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_clnt_axi_id_reuse_t {
+          unsigned int                                : 17;
+          unsigned int paw_id                         : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE;
+          unsigned int reserved3                      : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE;
+          unsigned int mmur_id                        : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int reserved2                      : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE;
+          unsigned int rbw_id                         : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE;
+          unsigned int reserved1                      : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE;
+          unsigned int cpw_id                         : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE;
+     } mh_clnt_axi_id_reuse_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_clnt_axi_id_reuse_t f;
+} mh_clnt_axi_id_reuse_u;
+
+
+/*
+ * MH_INTERRUPT_MASK struct
+ */
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_MASK_MASK \
+     (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \
+     ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \
+     mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_mask_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_mask_t f;
+} mh_interrupt_mask_u;
+
+
+/*
+ * MH_INTERRUPT_STATUS struct
+ */
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_STATUS_MASK \
+     (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \
+     ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \
+     mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_status_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_status_t f;
+} mh_interrupt_status_u;
+
+
+/*
+ * MH_INTERRUPT_CLEAR struct
+ */
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2
+
+#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001
+#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002
+#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004
+
+#define MH_INTERRUPT_CLEAR_MASK \
+     (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \
+      MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK)
+
+#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \
+     ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \
+      (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \
+     ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT)
+#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \
+     mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int                                : 29;
+     } mh_interrupt_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_interrupt_clear_t {
+          unsigned int                                : 29;
+          unsigned int mmu_page_fault                 : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE;
+          unsigned int axi_write_error                : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_read_error                 : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE;
+     } mh_interrupt_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_interrupt_clear_t f;
+} mh_interrupt_clear_u;
+
+
+/*
+ * MH_AXI_ERROR struct
+ */
+
+#define MH_AXI_ERROR_AXI_READ_ID_SIZE  3
+#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1
+#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1
+
+#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0
+#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3
+#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7
+
+#define MH_AXI_ERROR_AXI_READ_ID_MASK  0x00000007
+#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008
+#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070
+#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080
+
+#define MH_AXI_ERROR_MASK \
+     (MH_AXI_ERROR_AXI_READ_ID_MASK | \
+      MH_AXI_ERROR_AXI_READ_ERROR_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ID_MASK | \
+      MH_AXI_ERROR_AXI_WRITE_ERROR_MASK)
+
+#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \
+     ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \
+      (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \
+      (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \
+      (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT))
+
+#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \
+     ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT)
+#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \
+     mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int                                : 24;
+     } mh_axi_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_error_t {
+          unsigned int                                : 24;
+          unsigned int axi_write_error                : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE;
+          unsigned int axi_write_id                   : MH_AXI_ERROR_AXI_WRITE_ID_SIZE;
+          unsigned int axi_read_error                 : MH_AXI_ERROR_AXI_READ_ERROR_SIZE;
+          unsigned int axi_read_id                    : MH_AXI_ERROR_AXI_READ_ID_SIZE;
+     } mh_axi_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_error_t f;
+} mh_axi_error_u;
+
+
+/*
+ * MH_PERFCOUNTER0_SELECT struct
+ */
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_SELECT_MASK \
+     (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \
+     ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \
+     mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_select_t f;
+} mh_perfcounter0_select_u;
+
+
+/*
+ * MH_PERFCOUNTER1_SELECT struct
+ */
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_SELECT_MASK \
+     (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define MH_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \
+     ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \
+     mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } mh_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_select_t f;
+} mh_perfcounter1_select_u;
+
+
+/*
+ * MH_PERFCOUNTER0_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER0_CONFIG_MASK \
+     (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER0_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \
+     ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \
+     mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter0_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter0_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_config_t f;
+} mh_perfcounter0_config_u;
+
+
+/*
+ * MH_PERFCOUNTER1_CONFIG struct
+ */
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0
+
+#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff
+
+#define MH_PERFCOUNTER1_CONFIG_MASK \
+     (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK)
+
+#define MH_PERFCOUNTER1_CONFIG(n_value) \
+     ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT))
+
+#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \
+     ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \
+     mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+          unsigned int                                : 24;
+     } mh_perfcounter1_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_config_t {
+          unsigned int                                : 24;
+          unsigned int n_value                        : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE;
+     } mh_perfcounter1_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_config_t f;
+} mh_perfcounter1_config_u;
+
+
+/*
+ * MH_PERFCOUNTER0_LOW struct
+ */
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER0_LOW_MASK \
+     (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER0_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \
+     ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \
+     mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_low_t f;
+} mh_perfcounter0_low_u;
+
+
+/*
+ * MH_PERFCOUNTER1_LOW struct
+ */
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0
+
+#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff
+
+#define MH_PERFCOUNTER1_LOW_MASK \
+     (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK)
+
+#define MH_PERFCOUNTER1_LOW(perf_counter_low) \
+     ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT))
+
+#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \
+     ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \
+     mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_low_t {
+          unsigned int perf_counter_low               : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE;
+     } mh_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_low_t f;
+} mh_perfcounter1_low_u;
+
+
+/*
+ * MH_PERFCOUNTER0_HI struct
+ */
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER0_HI_MASK \
+     (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER0_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \
+     ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \
+     mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter0_hi_t f;
+} mh_perfcounter0_hi_u;
+
+
+/*
+ * MH_PERFCOUNTER1_HI struct
+ */
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0
+
+#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff
+
+#define MH_PERFCOUNTER1_HI_MASK \
+     (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK)
+
+#define MH_PERFCOUNTER1_HI(perf_counter_hi) \
+     ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT))
+
+#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \
+     ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \
+     mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } mh_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_counter_hi                : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE;
+     } mh_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_perfcounter1_hi_t f;
+} mh_perfcounter1_hi_u;
+
+
+/*
+ * MH_DEBUG_CTRL struct
+ */
+
+#define MH_DEBUG_CTRL_INDEX_SIZE       6
+
+#define MH_DEBUG_CTRL_INDEX_SHIFT      0
+
+#define MH_DEBUG_CTRL_INDEX_MASK       0x0000003f
+
+#define MH_DEBUG_CTRL_MASK \
+     (MH_DEBUG_CTRL_INDEX_MASK)
+
+#define MH_DEBUG_CTRL(index) \
+     ((index << MH_DEBUG_CTRL_INDEX_SHIFT))
+
+#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \
+     ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \
+     mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+          unsigned int                                : 26;
+     } mh_debug_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_ctrl_t {
+          unsigned int                                : 26;
+          unsigned int index                          : MH_DEBUG_CTRL_INDEX_SIZE;
+     } mh_debug_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_ctrl_t f;
+} mh_debug_ctrl_u;
+
+
+/*
+ * MH_DEBUG_DATA struct
+ */
+
+#define MH_DEBUG_DATA_DATA_SIZE        32
+
+#define MH_DEBUG_DATA_DATA_SHIFT       0
+
+#define MH_DEBUG_DATA_DATA_MASK        0xffffffff
+
+#define MH_DEBUG_DATA_MASK \
+     (MH_DEBUG_DATA_DATA_MASK)
+
+#define MH_DEBUG_DATA(data) \
+     ((data << MH_DEBUG_DATA_DATA_SHIFT))
+
+#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \
+     ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT)
+
+#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \
+     mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_data_t {
+          unsigned int data                           : MH_DEBUG_DATA_DATA_SIZE;
+     } mh_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_data_t f;
+} mh_debug_data_u;
+
+
+/*
+ * MH_AXI_HALT_CONTROL struct
+ */
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0
+
+#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001
+
+#define MH_AXI_HALT_CONTROL_MASK \
+     (MH_AXI_HALT_CONTROL_AXI_HALT_MASK)
+
+#define MH_AXI_HALT_CONTROL(axi_halt) \
+     ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT))
+
+#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \
+     ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \
+     mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+          unsigned int                                : 31;
+     } mh_axi_halt_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_axi_halt_control_t {
+          unsigned int                                : 31;
+          unsigned int axi_halt                       : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE;
+     } mh_axi_halt_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_axi_halt_control_t f;
+} mh_axi_halt_control_u;
+
+
+/*
+ * MH_DEBUG_REG00 struct
+ */
+
+#define MH_DEBUG_REG00_MH_BUSY_SIZE    1
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1
+#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1
+#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1
+#define MH_DEBUG_REG00_TCD_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_TCD_FULL_SIZE   1
+#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1
+#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_ARQ_FULL_SIZE   1
+#define MH_DEBUG_REG00_WDB_EMPTY_SIZE  1
+#define MH_DEBUG_REG00_WDB_FULL_SIZE   1
+#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1
+#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1
+
+#define MH_DEBUG_REG00_MH_BUSY_SHIFT   0
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1
+#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2
+#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3
+#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5
+#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6
+#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7
+#define MH_DEBUG_REG00_TCD_FULL_SHIFT  8
+#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9
+#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11
+#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12
+#define MH_DEBUG_REG00_ARQ_FULL_SHIFT  13
+#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14
+#define MH_DEBUG_REG00_WDB_FULL_SHIFT  15
+#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16
+#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17
+#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18
+#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19
+#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20
+#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21
+#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22
+#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23
+#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24
+#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25
+#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26
+#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27
+#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28
+
+#define MH_DEBUG_REG00_MH_BUSY_MASK    0x00000001
+#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002
+#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004
+#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008
+#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010
+#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020
+#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040
+#define MH_DEBUG_REG00_TCD_EMPTY_MASK  0x00000080
+#define MH_DEBUG_REG00_TCD_FULL_MASK   0x00000100
+#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200
+#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400
+#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800
+#define MH_DEBUG_REG00_ARQ_EMPTY_MASK  0x00001000
+#define MH_DEBUG_REG00_ARQ_FULL_MASK   0x00002000
+#define MH_DEBUG_REG00_WDB_EMPTY_MASK  0x00004000
+#define MH_DEBUG_REG00_WDB_FULL_MASK   0x00008000
+#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000
+#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000
+#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000
+#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000
+#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000
+#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000
+#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000
+#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000
+#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000
+#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000
+#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000
+#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000
+#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000
+
+#define MH_DEBUG_REG00_MASK \
+     (MH_DEBUG_REG00_MH_BUSY_MASK | \
+      MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \
+      MH_DEBUG_REG00_CP_REQUEST_MASK | \
+      MH_DEBUG_REG00_VGT_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_REQUEST_MASK | \
+      MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \
+      MH_DEBUG_REG00_TC_CAM_FULL_MASK | \
+      MH_DEBUG_REG00_TCD_EMPTY_MASK | \
+      MH_DEBUG_REG00_TCD_FULL_MASK | \
+      MH_DEBUG_REG00_RB_REQUEST_MASK | \
+      MH_DEBUG_REG00_PA_REQUEST_MASK | \
+      MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \
+      MH_DEBUG_REG00_ARQ_EMPTY_MASK | \
+      MH_DEBUG_REG00_ARQ_FULL_MASK | \
+      MH_DEBUG_REG00_WDB_EMPTY_MASK | \
+      MH_DEBUG_REG00_WDB_FULL_MASK | \
+      MH_DEBUG_REG00_AXI_AVALID_MASK | \
+      MH_DEBUG_REG00_AXI_AREADY_MASK | \
+      MH_DEBUG_REG00_AXI_ARVALID_MASK | \
+      MH_DEBUG_REG00_AXI_ARREADY_MASK | \
+      MH_DEBUG_REG00_AXI_WVALID_MASK | \
+      MH_DEBUG_REG00_AXI_WREADY_MASK | \
+      MH_DEBUG_REG00_AXI_RVALID_MASK | \
+      MH_DEBUG_REG00_AXI_RREADY_MASK | \
+      MH_DEBUG_REG00_AXI_BVALID_MASK | \
+      MH_DEBUG_REG00_AXI_BREADY_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \
+      MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \
+      MH_DEBUG_REG00_AXI_RDY_ENA_MASK)
+
+#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \
+     ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \
+      (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \
+      (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \
+      (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \
+      (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \
+      (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \
+      (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \
+      (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \
+      (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \
+      (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \
+      (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \
+      (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \
+      (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \
+      (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \
+      (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \
+      (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \
+      (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \
+      (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \
+      (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \
+      (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \
+      (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \
+      (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \
+      (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \
+      (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \
+      (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \
+      (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \
+      (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \
+      (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \
+      (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT))
+
+#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \
+     ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT)
+#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT)
+#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT)
+#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT)
+#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)
+#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \
+     mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg00_t {
+          unsigned int                                : 3;
+          unsigned int axi_rdy_ena                    : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE;
+          unsigned int axi_halt_ack                   : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE;
+          unsigned int axi_halt_req                   : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE;
+          unsigned int axi_bready                     : MH_DEBUG_REG00_AXI_BREADY_SIZE;
+          unsigned int axi_bvalid                     : MH_DEBUG_REG00_AXI_BVALID_SIZE;
+          unsigned int axi_rready                     : MH_DEBUG_REG00_AXI_RREADY_SIZE;
+          unsigned int axi_rvalid                     : MH_DEBUG_REG00_AXI_RVALID_SIZE;
+          unsigned int axi_wready                     : MH_DEBUG_REG00_AXI_WREADY_SIZE;
+          unsigned int axi_wvalid                     : MH_DEBUG_REG00_AXI_WVALID_SIZE;
+          unsigned int axi_arready                    : MH_DEBUG_REG00_AXI_ARREADY_SIZE;
+          unsigned int axi_arvalid                    : MH_DEBUG_REG00_AXI_ARVALID_SIZE;
+          unsigned int axi_aready                     : MH_DEBUG_REG00_AXI_AREADY_SIZE;
+          unsigned int axi_avalid                     : MH_DEBUG_REG00_AXI_AVALID_SIZE;
+          unsigned int wdb_full                       : MH_DEBUG_REG00_WDB_FULL_SIZE;
+          unsigned int wdb_empty                      : MH_DEBUG_REG00_WDB_EMPTY_SIZE;
+          unsigned int arq_full                       : MH_DEBUG_REG00_ARQ_FULL_SIZE;
+          unsigned int arq_empty                      : MH_DEBUG_REG00_ARQ_EMPTY_SIZE;
+          unsigned int mh_clk_en_state                : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE;
+          unsigned int pa_request                     : MH_DEBUG_REG00_PA_REQUEST_SIZE;
+          unsigned int rb_request                     : MH_DEBUG_REG00_RB_REQUEST_SIZE;
+          unsigned int tcd_full                       : MH_DEBUG_REG00_TCD_FULL_SIZE;
+          unsigned int tcd_empty                      : MH_DEBUG_REG00_TCD_EMPTY_SIZE;
+          unsigned int tc_cam_full                    : MH_DEBUG_REG00_TC_CAM_FULL_SIZE;
+          unsigned int tc_cam_empty                   : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE;
+          unsigned int tc_request                     : MH_DEBUG_REG00_TC_REQUEST_SIZE;
+          unsigned int vgt_request                    : MH_DEBUG_REG00_VGT_REQUEST_SIZE;
+          unsigned int cp_request                     : MH_DEBUG_REG00_CP_REQUEST_SIZE;
+          unsigned int trans_outstanding              : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE;
+          unsigned int mh_busy                        : MH_DEBUG_REG00_MH_BUSY_SIZE;
+     } mh_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg00_t f;
+} mh_debug_reg00_u;
+
+
+/*
+ * MH_DEBUG_REG01 struct
+ */
+
+#define MH_DEBUG_REG01_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1
+#define MH_DEBUG_REG01_CP_TAG_q_SIZE   3
+#define MH_DEBUG_REG01_CP_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG01_VGT_TAG_q_SIZE  1
+#define MH_DEBUG_REG01_TC_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_TC_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_TC_BLEN_q_SIZE  1
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG01_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG01_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG01_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG01_PA_RTR_q_SIZE   1
+
+#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0
+#define MH_DEBUG_REG01_CP_RTR_q_SHIFT  1
+#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2
+#define MH_DEBUG_REG01_CP_TAG_q_SHIFT  3
+#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6
+#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7
+#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8
+#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9
+#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10
+#define MH_DEBUG_REG01_TC_RTR_q_SHIFT  11
+#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14
+#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15
+#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16
+#define MH_DEBUG_REG01_RB_RTR_q_SHIFT  17
+#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18
+#define MH_DEBUG_REG01_PA_RTR_q_SHIFT  19
+
+#define MH_DEBUG_REG01_CP_SEND_q_MASK  0x00000001
+#define MH_DEBUG_REG01_CP_RTR_q_MASK   0x00000002
+#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004
+#define MH_DEBUG_REG01_CP_TAG_q_MASK   0x00000038
+#define MH_DEBUG_REG01_CP_BLEN_q_MASK  0x00000040
+#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080
+#define MH_DEBUG_REG01_VGT_RTR_q_MASK  0x00000100
+#define MH_DEBUG_REG01_VGT_TAG_q_MASK  0x00000200
+#define MH_DEBUG_REG01_TC_SEND_q_MASK  0x00000400
+#define MH_DEBUG_REG01_TC_RTR_q_MASK   0x00000800
+#define MH_DEBUG_REG01_TC_BLEN_q_MASK  0x00001000
+#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000
+#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000
+#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000
+#define MH_DEBUG_REG01_RB_SEND_q_MASK  0x00010000
+#define MH_DEBUG_REG01_RB_RTR_q_MASK   0x00020000
+#define MH_DEBUG_REG01_PA_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG01_PA_RTR_q_MASK   0x00080000
+
+#define MH_DEBUG_REG01_MASK \
+     (MH_DEBUG_REG01_CP_SEND_q_MASK | \
+      MH_DEBUG_REG01_CP_RTR_q_MASK | \
+      MH_DEBUG_REG01_CP_WRITE_q_MASK | \
+      MH_DEBUG_REG01_CP_TAG_q_MASK | \
+      MH_DEBUG_REG01_CP_BLEN_q_MASK | \
+      MH_DEBUG_REG01_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG01_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG01_VGT_TAG_q_MASK | \
+      MH_DEBUG_REG01_TC_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_BLEN_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG01_TC_MH_written_MASK | \
+      MH_DEBUG_REG01_RB_SEND_q_MASK | \
+      MH_DEBUG_REG01_RB_RTR_q_MASK | \
+      MH_DEBUG_REG01_PA_SEND_q_MASK | \
+      MH_DEBUG_REG01_PA_RTR_q_MASK)
+
+#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \
+     ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \
+      (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \
+      (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \
+      (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \
+      (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \
+      (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \
+      (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \
+      (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT))
+
+#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \
+     ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \
+     mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg01_t {
+          unsigned int                                : 12;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG01_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG01_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG01_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG01_RB_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG01_TC_MH_written_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_blen_q                      : MH_DEBUG_REG01_TC_BLEN_q_SIZE;
+          unsigned int tc_rtr_q                       : MH_DEBUG_REG01_TC_RTR_q_SIZE;
+          unsigned int tc_send_q                      : MH_DEBUG_REG01_TC_SEND_q_SIZE;
+          unsigned int vgt_tag_q                      : MH_DEBUG_REG01_VGT_TAG_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG01_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG01_VGT_SEND_q_SIZE;
+          unsigned int cp_blen_q                      : MH_DEBUG_REG01_CP_BLEN_q_SIZE;
+          unsigned int cp_tag_q                       : MH_DEBUG_REG01_CP_TAG_q_SIZE;
+          unsigned int cp_write_q                     : MH_DEBUG_REG01_CP_WRITE_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG01_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG01_CP_SEND_q_SIZE;
+     } mh_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg01_t f;
+} mh_debug_reg01_u;
+
+
+/*
+ * MH_DEBUG_REG02 struct
+ */
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1
+#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3
+#define MH_DEBUG_REG02_RDC_RID_SIZE    3
+#define MH_DEBUG_REG02_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1
+#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1
+#define MH_DEBUG_REG02_BRC_BID_SIZE    3
+#define MH_DEBUG_REG02_BRC_BRESP_SIZE  2
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3
+#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4
+#define MH_DEBUG_REG02_RDC_RID_SHIFT   7
+#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12
+#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13
+#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14
+#define MH_DEBUG_REG02_BRC_BID_SHIFT   15
+#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18
+
+#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008
+#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070
+#define MH_DEBUG_REG02_RDC_RID_MASK    0x00000380
+#define MH_DEBUG_REG02_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000
+#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000
+#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000
+#define MH_DEBUG_REG02_BRC_BID_MASK    0x00038000
+#define MH_DEBUG_REG02_BRC_BRESP_MASK  0x000c0000
+
+#define MH_DEBUG_REG02_MASK \
+     (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG02_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \
+      MH_DEBUG_REG02_MH_CLNT_tag_MASK | \
+      MH_DEBUG_REG02_RDC_RID_MASK | \
+      MH_DEBUG_REG02_RDC_RRESP_MASK | \
+      MH_DEBUG_REG02_MH_CP_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_RB_writeclean_MASK | \
+      MH_DEBUG_REG02_MH_PA_writeclean_MASK | \
+      MH_DEBUG_REG02_BRC_BID_MASK | \
+      MH_DEBUG_REG02_BRC_BRESP_MASK)
+
+#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \
+     ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \
+      (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \
+      (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \
+      (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \
+      (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \
+      (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \
+      (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \
+      (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT))
+
+#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \
+     ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT)
+#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT)
+#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \
+     mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg02_t {
+          unsigned int                                : 12;
+          unsigned int brc_bresp                      : MH_DEBUG_REG02_BRC_BRESP_SIZE;
+          unsigned int brc_bid                        : MH_DEBUG_REG02_BRC_BID_SIZE;
+          unsigned int mh_pa_writeclean               : MH_DEBUG_REG02_MH_PA_writeclean_SIZE;
+          unsigned int mh_rb_writeclean               : MH_DEBUG_REG02_MH_RB_writeclean_SIZE;
+          unsigned int mh_cp_writeclean               : MH_DEBUG_REG02_MH_CP_writeclean_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG02_RDC_RRESP_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG02_RDC_RID_SIZE;
+          unsigned int mh_clnt_tag                    : MH_DEBUG_REG02_MH_CLNT_tag_SIZE;
+          unsigned int mh_clnt_rlast                  : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG02_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG02_MH_CP_grb_send_SIZE;
+     } mh_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg02_t f;
+} mh_debug_reg02_u;
+
+
+/*
+ * MH_DEBUG_REG03 struct
+ */
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG03_MASK \
+     (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK)
+
+#define MH_DEBUG_REG03(mh_clnt_data_31_0) \
+     ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \
+     ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \
+     mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg03_t {
+          unsigned int mh_clnt_data_31_0              : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE;
+     } mh_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg03_t f;
+} mh_debug_reg03_u;
+
+
+/*
+ * MH_DEBUG_REG04 struct
+ */
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG04_MASK \
+     (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK)
+
+#define MH_DEBUG_REG04(mh_clnt_data_63_32) \
+     ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \
+     ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \
+     mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg04_t {
+          unsigned int mh_clnt_data_63_32             : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE;
+     } mh_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg04_t f;
+} mh_debug_reg04_u;
+
+
+/*
+ * MH_DEBUG_REG05 struct
+ */
+
+#define MH_DEBUG_REG05_CP_MH_send_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG05_CP_MH_tag_SIZE  3
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0
+#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1
+#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002
+#define MH_DEBUG_REG05_CP_MH_tag_MASK  0x0000001c
+#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG05_MASK \
+     (MH_DEBUG_REG05_CP_MH_send_MASK | \
+      MH_DEBUG_REG05_CP_MH_write_MASK | \
+      MH_DEBUG_REG05_CP_MH_tag_MASK | \
+      MH_DEBUG_REG05_CP_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \
+     ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \
+      (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \
+      (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \
+     ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT)
+#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \
+     mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+     } mh_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg05_t {
+          unsigned int cp_mh_ad_31_5                  : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE;
+          unsigned int cp_mh_tag                      : MH_DEBUG_REG05_CP_MH_tag_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG05_CP_MH_write_SIZE;
+          unsigned int cp_mh_send                     : MH_DEBUG_REG05_CP_MH_send_SIZE;
+     } mh_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg05_t f;
+} mh_debug_reg05_u;
+
+
+/*
+ * MH_DEBUG_REG06 struct
+ */
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG06_MASK \
+     (MH_DEBUG_REG06_CP_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG06(cp_mh_data_31_0) \
+     ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \
+     ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \
+     mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg06_t {
+          unsigned int cp_mh_data_31_0                : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE;
+     } mh_debug_reg06_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg06_t f;
+} mh_debug_reg06_u;
+
+
+/*
+ * MH_DEBUG_REG07 struct
+ */
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG07_MASK \
+     (MH_DEBUG_REG07_CP_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG07(cp_mh_data_63_32) \
+     ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \
+     ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \
+     mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg07_t {
+          unsigned int cp_mh_data_63_32               : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE;
+     } mh_debug_reg07_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg07_t f;
+} mh_debug_reg07_u;
+
+
+/*
+ * MH_DEBUG_REG08 struct
+ */
+
+#define MH_DEBUG_REG08_CP_MH_be_SIZE   8
+#define MH_DEBUG_REG08_RB_MH_be_SIZE   8
+#define MH_DEBUG_REG08_PA_MH_be_SIZE   8
+
+#define MH_DEBUG_REG08_CP_MH_be_SHIFT  0
+#define MH_DEBUG_REG08_RB_MH_be_SHIFT  8
+#define MH_DEBUG_REG08_PA_MH_be_SHIFT  16
+
+#define MH_DEBUG_REG08_CP_MH_be_MASK   0x000000ff
+#define MH_DEBUG_REG08_RB_MH_be_MASK   0x0000ff00
+#define MH_DEBUG_REG08_PA_MH_be_MASK   0x00ff0000
+
+#define MH_DEBUG_REG08_MASK \
+     (MH_DEBUG_REG08_CP_MH_be_MASK | \
+      MH_DEBUG_REG08_RB_MH_be_MASK | \
+      MH_DEBUG_REG08_PA_MH_be_MASK)
+
+#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \
+     ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \
+      (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \
+      (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT))
+
+#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \
+     ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT)
+#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \
+     mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int                                : 8;
+     } mh_debug_reg08_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg08_t {
+          unsigned int                                : 8;
+          unsigned int pa_mh_be                       : MH_DEBUG_REG08_PA_MH_be_SIZE;
+          unsigned int rb_mh_be                       : MH_DEBUG_REG08_RB_MH_be_SIZE;
+          unsigned int cp_mh_be                       : MH_DEBUG_REG08_CP_MH_be_SIZE;
+     } mh_debug_reg08_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg08_t f;
+} mh_debug_reg08_u;
+
+
+/*
+ * MH_DEBUG_REG09 struct
+ */
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3
+#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3
+#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5
+
+#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007
+#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008
+#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010
+#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG09_MASK \
+     (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG09_VGT_MH_send_MASK | \
+      MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \
+      MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK)
+
+#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \
+     ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \
+      (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \
+      (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \
+      (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT))
+
+#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \
+     ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT)
+#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \
+     mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+     } mh_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg09_t {
+          unsigned int vgt_mh_ad_31_5                 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE;
+          unsigned int vgt_mh_tagbe                   : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE;
+          unsigned int vgt_mh_send                    : MH_DEBUG_REG09_VGT_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg09_t f;
+} mh_debug_reg09_u;
+
+
+/*
+ * MH_DEBUG_REG10 struct
+ */
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2
+#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004
+#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018
+#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG10_MASK \
+     (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG10_TC_MH_send_MASK | \
+      MH_DEBUG_REG10_TC_MH_mask_MASK | \
+      MH_DEBUG_REG10_TC_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \
+      (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \
+      (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \
+     ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT)
+#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \
+     mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+     } mh_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg10_t {
+          unsigned int tc_mh_addr_31_5                : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE;
+          unsigned int tc_mh_mask                     : MH_DEBUG_REG10_TC_MH_mask_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG10_TC_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg10_t f;
+} mh_debug_reg10_u;
+
+
+/*
+ * MH_DEBUG_REG11 struct
+ */
+
+#define MH_DEBUG_REG11_TC_MH_info_SIZE 25
+#define MH_DEBUG_REG11_TC_MH_send_SIZE 1
+
+#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0
+#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25
+
+#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff
+#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000
+
+#define MH_DEBUG_REG11_MASK \
+     (MH_DEBUG_REG11_TC_MH_info_MASK | \
+      MH_DEBUG_REG11_TC_MH_send_MASK)
+
+#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \
+     ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT))
+
+#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \
+     ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT)
+#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \
+     mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg11_t {
+          unsigned int                                : 6;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG11_TC_MH_send_SIZE;
+          unsigned int tc_mh_info                     : MH_DEBUG_REG11_TC_MH_info_SIZE;
+     } mh_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg11_t f;
+} mh_debug_reg11_u;
+
+
+/*
+ * MH_DEBUG_REG12 struct
+ */
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1
+#define MH_DEBUG_REG12_TC_MH_written_SIZE 1
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25
+#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26
+
+#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff
+#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000
+#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000
+
+#define MH_DEBUG_REG12_MASK \
+     (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \
+      MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \
+      MH_DEBUG_REG12_TC_MH_written_MASK)
+
+#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \
+     ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \
+      (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT))
+
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \
+     ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT)
+#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT)
+#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \
+     mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int                                : 5;
+     } mh_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg12_t {
+          unsigned int                                : 5;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG12_TC_MH_written_SIZE;
+          unsigned int mh_tc_mcinfo_send              : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE;
+          unsigned int mh_tc_mcinfo                   : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE;
+     } mh_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg12_t f;
+} mh_debug_reg12_u;
+
+
+/*
+ * MH_DEBUG_REG13 struct
+ */
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2
+#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5
+
+#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004
+#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018
+#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG13_MASK \
+     (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \
+      MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK)
+
+#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \
+      (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \
+      (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT))
+
+#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \
+     ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT)
+#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \
+     mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+     } mh_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg13_t {
+          unsigned int tc_roq_addr_31_5               : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE;
+          unsigned int tc_roq_mask                    : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg13_t f;
+} mh_debug_reg13_u;
+
+
+/*
+ * MH_DEBUG_REG14 struct
+ */
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0
+#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25
+
+#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff
+#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000
+
+#define MH_DEBUG_REG14_MASK \
+     (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \
+      MH_DEBUG_REG14_TC_ROQ_SEND_MASK)
+
+#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \
+     ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \
+      (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT))
+
+#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \
+     ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT)
+#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \
+     mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int                                : 6;
+     } mh_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg14_t {
+          unsigned int                                : 6;
+          unsigned int tc_roq_send                    : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE;
+          unsigned int tc_roq_info                    : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE;
+     } mh_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg14_t f;
+} mh_debug_reg14_u;
+
+
+/*
+ * MH_DEBUG_REG15 struct
+ */
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG15_RB_MH_send_SIZE 1
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG15_MASK \
+     (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG15_RB_MH_send_MASK | \
+      MH_DEBUG_REG15_RB_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \
+      (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \
+      (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \
+     ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT)
+#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \
+     mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+     } mh_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg15_t {
+          unsigned int rb_mh_addr_31_5                : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE;
+          unsigned int rb_mh_send                     : MH_DEBUG_REG15_RB_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg15_t f;
+} mh_debug_reg15_u;
+
+
+/*
+ * MH_DEBUG_REG16 struct
+ */
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG16_MASK \
+     (MH_DEBUG_REG16_RB_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG16(rb_mh_data_31_0) \
+     ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \
+     ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \
+     mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg16_t {
+          unsigned int rb_mh_data_31_0                : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE;
+     } mh_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg16_t f;
+} mh_debug_reg16_u;
+
+
+/*
+ * MH_DEBUG_REG17 struct
+ */
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG17_MASK \
+     (MH_DEBUG_REG17_RB_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG17(rb_mh_data_63_32) \
+     ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \
+     ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \
+     mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg17_t {
+          unsigned int rb_mh_data_63_32               : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE;
+     } mh_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg17_t f;
+} mh_debug_reg17_u;
+
+
+/*
+ * MH_DEBUG_REG18 struct
+ */
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4
+#define MH_DEBUG_REG18_PA_MH_send_SIZE 1
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5
+
+#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f
+#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010
+#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG18_MASK \
+     (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG18_PA_MH_send_MASK | \
+      MH_DEBUG_REG18_PA_MH_addr_31_5_MASK)
+
+#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \
+     ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \
+      (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \
+      (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT))
+
+#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \
+     ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT)
+#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \
+     mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+     } mh_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg18_t {
+          unsigned int pa_mh_addr_31_5                : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE;
+          unsigned int pa_mh_send                     : MH_DEBUG_REG18_PA_MH_send_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg18_t f;
+} mh_debug_reg18_u;
+
+
+/*
+ * MH_DEBUG_REG19 struct
+ */
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0
+
+#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG19_MASK \
+     (MH_DEBUG_REG19_PA_MH_data_31_0_MASK)
+
+#define MH_DEBUG_REG19(pa_mh_data_31_0) \
+     ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT))
+
+#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \
+     ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \
+     mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg19_t {
+          unsigned int pa_mh_data_31_0                : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE;
+     } mh_debug_reg19_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg19_t f;
+} mh_debug_reg19_u;
+
+
+/*
+ * MH_DEBUG_REG20 struct
+ */
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0
+
+#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG20_MASK \
+     (MH_DEBUG_REG20_PA_MH_data_63_32_MASK)
+
+#define MH_DEBUG_REG20(pa_mh_data_63_32) \
+     ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT))
+
+#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \
+     ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \
+     mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg20_t {
+          unsigned int pa_mh_data_63_32               : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE;
+     } mh_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg20_t f;
+} mh_debug_reg20_u;
+
+
+/*
+ * MH_DEBUG_REG21 struct
+ */
+
+#define MH_DEBUG_REG21_AVALID_q_SIZE   1
+#define MH_DEBUG_REG21_AREADY_q_SIZE   1
+#define MH_DEBUG_REG21_AID_q_SIZE      3
+#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3
+#define MH_DEBUG_REG21_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG21_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG21_ARID_q_SIZE     3
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG21_RVALID_q_SIZE   1
+#define MH_DEBUG_REG21_RREADY_q_SIZE   1
+#define MH_DEBUG_REG21_RLAST_q_SIZE    1
+#define MH_DEBUG_REG21_RID_q_SIZE      3
+#define MH_DEBUG_REG21_WVALID_q_SIZE   1
+#define MH_DEBUG_REG21_WREADY_q_SIZE   1
+#define MH_DEBUG_REG21_WLAST_q_SIZE    1
+#define MH_DEBUG_REG21_WID_q_SIZE      3
+#define MH_DEBUG_REG21_BVALID_q_SIZE   1
+#define MH_DEBUG_REG21_BREADY_q_SIZE   1
+#define MH_DEBUG_REG21_BID_q_SIZE      3
+
+#define MH_DEBUG_REG21_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG21_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG21_AID_q_SHIFT     2
+#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5
+#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8
+#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9
+#define MH_DEBUG_REG21_ARID_q_SHIFT    10
+#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13
+#define MH_DEBUG_REG21_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG21_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG21_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG21_RID_q_SHIFT     18
+#define MH_DEBUG_REG21_WVALID_q_SHIFT  21
+#define MH_DEBUG_REG21_WREADY_q_SHIFT  22
+#define MH_DEBUG_REG21_WLAST_q_SHIFT   23
+#define MH_DEBUG_REG21_WID_q_SHIFT     24
+#define MH_DEBUG_REG21_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG21_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG21_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG21_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG21_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG21_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0
+#define MH_DEBUG_REG21_ARVALID_q_MASK  0x00000100
+#define MH_DEBUG_REG21_ARREADY_q_MASK  0x00000200
+#define MH_DEBUG_REG21_ARID_q_MASK     0x00001c00
+#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000
+#define MH_DEBUG_REG21_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG21_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG21_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG21_RID_q_MASK      0x001c0000
+#define MH_DEBUG_REG21_WVALID_q_MASK   0x00200000
+#define MH_DEBUG_REG21_WREADY_q_MASK   0x00400000
+#define MH_DEBUG_REG21_WLAST_q_MASK    0x00800000
+#define MH_DEBUG_REG21_WID_q_MASK      0x07000000
+#define MH_DEBUG_REG21_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG21_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG21_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG21_MASK \
+     (MH_DEBUG_REG21_AVALID_q_MASK | \
+      MH_DEBUG_REG21_AREADY_q_MASK | \
+      MH_DEBUG_REG21_AID_q_MASK | \
+      MH_DEBUG_REG21_ALEN_q_2_0_MASK | \
+      MH_DEBUG_REG21_ARVALID_q_MASK | \
+      MH_DEBUG_REG21_ARREADY_q_MASK | \
+      MH_DEBUG_REG21_ARID_q_MASK | \
+      MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \
+      MH_DEBUG_REG21_RVALID_q_MASK | \
+      MH_DEBUG_REG21_RREADY_q_MASK | \
+      MH_DEBUG_REG21_RLAST_q_MASK | \
+      MH_DEBUG_REG21_RID_q_MASK | \
+      MH_DEBUG_REG21_WVALID_q_MASK | \
+      MH_DEBUG_REG21_WREADY_q_MASK | \
+      MH_DEBUG_REG21_WLAST_q_MASK | \
+      MH_DEBUG_REG21_WID_q_MASK | \
+      MH_DEBUG_REG21_BVALID_q_MASK | \
+      MH_DEBUG_REG21_BREADY_q_MASK | \
+      MH_DEBUG_REG21_BID_q_MASK)
+
+#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \
+      (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \
+      (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \
+      (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG21_BID_q_SHIFT))
+
+#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \
+     ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT)
+
+#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT)
+#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT)
+#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT)
+#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \
+     mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg21_t {
+          unsigned int bid_q                          : MH_DEBUG_REG21_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG21_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG21_BVALID_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG21_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG21_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG21_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG21_WVALID_q_SIZE;
+          unsigned int rid_q                          : MH_DEBUG_REG21_RID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG21_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG21_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG21_RVALID_q_SIZE;
+          unsigned int arlen_q_1_0                    : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG21_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG21_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG21_ARVALID_q_SIZE;
+          unsigned int alen_q_2_0                     : MH_DEBUG_REG21_ALEN_q_2_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG21_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG21_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG21_AVALID_q_SIZE;
+     } mh_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg21_t f;
+} mh_debug_reg21_u;
+
+
+/*
+ * MH_DEBUG_REG22 struct
+ */
+
+#define MH_DEBUG_REG22_AVALID_q_SIZE   1
+#define MH_DEBUG_REG22_AREADY_q_SIZE   1
+#define MH_DEBUG_REG22_AID_q_SIZE      3
+#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2
+#define MH_DEBUG_REG22_ARVALID_q_SIZE  1
+#define MH_DEBUG_REG22_ARREADY_q_SIZE  1
+#define MH_DEBUG_REG22_ARID_q_SIZE     3
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1
+#define MH_DEBUG_REG22_WVALID_q_SIZE   1
+#define MH_DEBUG_REG22_WREADY_q_SIZE   1
+#define MH_DEBUG_REG22_WLAST_q_SIZE    1
+#define MH_DEBUG_REG22_WID_q_SIZE      3
+#define MH_DEBUG_REG22_WSTRB_q_SIZE    8
+#define MH_DEBUG_REG22_BVALID_q_SIZE   1
+#define MH_DEBUG_REG22_BREADY_q_SIZE   1
+#define MH_DEBUG_REG22_BID_q_SIZE      3
+
+#define MH_DEBUG_REG22_AVALID_q_SHIFT  0
+#define MH_DEBUG_REG22_AREADY_q_SHIFT  1
+#define MH_DEBUG_REG22_AID_q_SHIFT     2
+#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5
+#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7
+#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8
+#define MH_DEBUG_REG22_ARID_q_SHIFT    9
+#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12
+#define MH_DEBUG_REG22_WVALID_q_SHIFT  13
+#define MH_DEBUG_REG22_WREADY_q_SHIFT  14
+#define MH_DEBUG_REG22_WLAST_q_SHIFT   15
+#define MH_DEBUG_REG22_WID_q_SHIFT     16
+#define MH_DEBUG_REG22_WSTRB_q_SHIFT   19
+#define MH_DEBUG_REG22_BVALID_q_SHIFT  27
+#define MH_DEBUG_REG22_BREADY_q_SHIFT  28
+#define MH_DEBUG_REG22_BID_q_SHIFT     29
+
+#define MH_DEBUG_REG22_AVALID_q_MASK   0x00000001
+#define MH_DEBUG_REG22_AREADY_q_MASK   0x00000002
+#define MH_DEBUG_REG22_AID_q_MASK      0x0000001c
+#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060
+#define MH_DEBUG_REG22_ARVALID_q_MASK  0x00000080
+#define MH_DEBUG_REG22_ARREADY_q_MASK  0x00000100
+#define MH_DEBUG_REG22_ARID_q_MASK     0x00000e00
+#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000
+#define MH_DEBUG_REG22_WVALID_q_MASK   0x00002000
+#define MH_DEBUG_REG22_WREADY_q_MASK   0x00004000
+#define MH_DEBUG_REG22_WLAST_q_MASK    0x00008000
+#define MH_DEBUG_REG22_WID_q_MASK      0x00070000
+#define MH_DEBUG_REG22_WSTRB_q_MASK    0x07f80000
+#define MH_DEBUG_REG22_BVALID_q_MASK   0x08000000
+#define MH_DEBUG_REG22_BREADY_q_MASK   0x10000000
+#define MH_DEBUG_REG22_BID_q_MASK      0xe0000000
+
+#define MH_DEBUG_REG22_MASK \
+     (MH_DEBUG_REG22_AVALID_q_MASK | \
+      MH_DEBUG_REG22_AREADY_q_MASK | \
+      MH_DEBUG_REG22_AID_q_MASK | \
+      MH_DEBUG_REG22_ALEN_q_1_0_MASK | \
+      MH_DEBUG_REG22_ARVALID_q_MASK | \
+      MH_DEBUG_REG22_ARREADY_q_MASK | \
+      MH_DEBUG_REG22_ARID_q_MASK | \
+      MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \
+      MH_DEBUG_REG22_WVALID_q_MASK | \
+      MH_DEBUG_REG22_WREADY_q_MASK | \
+      MH_DEBUG_REG22_WLAST_q_MASK | \
+      MH_DEBUG_REG22_WID_q_MASK | \
+      MH_DEBUG_REG22_WSTRB_q_MASK | \
+      MH_DEBUG_REG22_BVALID_q_MASK | \
+      MH_DEBUG_REG22_BREADY_q_MASK | \
+      MH_DEBUG_REG22_BID_q_MASK)
+
+#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \
+     ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \
+      (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \
+      (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \
+      (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \
+      (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \
+      (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \
+      (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \
+      (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \
+      (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \
+      (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \
+      (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \
+      (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \
+      (bid_q << MH_DEBUG_REG22_BID_q_SHIFT))
+
+#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \
+     ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT)
+
+#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT)
+#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT)
+#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT)
+#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \
+     mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg22_t {
+          unsigned int bid_q                          : MH_DEBUG_REG22_BID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG22_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG22_BVALID_q_SIZE;
+          unsigned int wstrb_q                        : MH_DEBUG_REG22_WSTRB_q_SIZE;
+          unsigned int wid_q                          : MH_DEBUG_REG22_WID_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG22_WLAST_q_SIZE;
+          unsigned int wready_q                       : MH_DEBUG_REG22_WREADY_q_SIZE;
+          unsigned int wvalid_q                       : MH_DEBUG_REG22_WVALID_q_SIZE;
+          unsigned int arlen_q_1_1                    : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE;
+          unsigned int arid_q                         : MH_DEBUG_REG22_ARID_q_SIZE;
+          unsigned int arready_q                      : MH_DEBUG_REG22_ARREADY_q_SIZE;
+          unsigned int arvalid_q                      : MH_DEBUG_REG22_ARVALID_q_SIZE;
+          unsigned int alen_q_1_0                     : MH_DEBUG_REG22_ALEN_q_1_0_SIZE;
+          unsigned int aid_q                          : MH_DEBUG_REG22_AID_q_SIZE;
+          unsigned int aready_q                       : MH_DEBUG_REG22_AREADY_q_SIZE;
+          unsigned int avalid_q                       : MH_DEBUG_REG22_AVALID_q_SIZE;
+     } mh_debug_reg22_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg22_t f;
+} mh_debug_reg22_u;
+
+
+/*
+ * MH_DEBUG_REG23 struct
+ */
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0
+#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4
+
+#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001
+#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e
+#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0
+
+#define MH_DEBUG_REG23_MASK \
+     (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \
+      MH_DEBUG_REG23_CTRL_ARC_PAD_MASK)
+
+#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \
+     ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \
+      (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \
+      (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT))
+
+#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \
+     ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT)
+#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \
+     mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+     } mh_debug_reg23_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg23_t {
+          unsigned int ctrl_arc_pad                   : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE;
+          unsigned int ctrl_arc_id                    : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE;
+     } mh_debug_reg23_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg23_t f;
+} mh_debug_reg23_u;
+
+
+/*
+ * MH_DEBUG_REG24 struct
+ */
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG24_REG_A_SIZE      14
+#define MH_DEBUG_REG24_REG_RE_SIZE     1
+#define MH_DEBUG_REG24_REG_WE_SIZE     1
+#define MH_DEBUG_REG24_BLOCK_RS_SIZE   1
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0
+#define MH_DEBUG_REG24_REG_A_SHIFT     2
+#define MH_DEBUG_REG24_REG_RE_SHIFT    16
+#define MH_DEBUG_REG24_REG_WE_SHIFT    17
+#define MH_DEBUG_REG24_BLOCK_RS_SHIFT  18
+
+#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003
+#define MH_DEBUG_REG24_REG_A_MASK      0x0000fffc
+#define MH_DEBUG_REG24_REG_RE_MASK     0x00010000
+#define MH_DEBUG_REG24_REG_WE_MASK     0x00020000
+#define MH_DEBUG_REG24_BLOCK_RS_MASK   0x00040000
+
+#define MH_DEBUG_REG24_MASK \
+     (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG24_REG_A_MASK | \
+      MH_DEBUG_REG24_REG_RE_MASK | \
+      MH_DEBUG_REG24_REG_WE_MASK | \
+      MH_DEBUG_REG24_BLOCK_RS_MASK)
+
+#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \
+     ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \
+      (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \
+      (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \
+      (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \
+      (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT))
+
+#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \
+     ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT)
+#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT)
+#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \
+     mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int                                : 13;
+     } mh_debug_reg24_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg24_t {
+          unsigned int                                : 13;
+          unsigned int block_rs                       : MH_DEBUG_REG24_BLOCK_RS_SIZE;
+          unsigned int reg_we                         : MH_DEBUG_REG24_REG_WE_SIZE;
+          unsigned int reg_re                         : MH_DEBUG_REG24_REG_RE_SIZE;
+          unsigned int reg_a                          : MH_DEBUG_REG24_REG_A_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE;
+     } mh_debug_reg24_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg24_t f;
+} mh_debug_reg24_u;
+
+
+/*
+ * MH_DEBUG_REG25 struct
+ */
+
+#define MH_DEBUG_REG25_REG_WD_SIZE     32
+
+#define MH_DEBUG_REG25_REG_WD_SHIFT    0
+
+#define MH_DEBUG_REG25_REG_WD_MASK     0xffffffff
+
+#define MH_DEBUG_REG25_MASK \
+     (MH_DEBUG_REG25_REG_WD_MASK)
+
+#define MH_DEBUG_REG25(reg_wd) \
+     ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT))
+
+#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \
+     ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \
+     mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg25_t {
+          unsigned int reg_wd                         : MH_DEBUG_REG25_REG_WD_SIZE;
+     } mh_debug_reg25_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg25_t f;
+} mh_debug_reg25_u;
+
+
+/*
+ * MH_DEBUG_REG26 struct
+ */
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1
+#define MH_DEBUG_REG26_CNT_q_SIZE      6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG26_MH_BUSY_d_SIZE  1
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+#define MH_DEBUG_REG26_CP_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_CP_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_VGT_RTR_q_SIZE  1
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG26_RB_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_RB_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_PA_SEND_q_SIZE  1
+#define MH_DEBUG_REG26_PA_RTR_q_SIZE   1
+#define MH_DEBUG_REG26_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG26_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG26_BRC_VALID_SIZE  1
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3
+#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5
+#define MH_DEBUG_REG26_CNT_q_SHIFT     6
+#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13
+#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17
+#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18
+#define MH_DEBUG_REG26_CP_RTR_q_SHIFT  19
+#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20
+#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23
+#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24
+#define MH_DEBUG_REG26_RB_RTR_q_SHIFT  25
+#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26
+#define MH_DEBUG_REG26_PA_RTR_q_SHIFT  27
+#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28
+#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29
+#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30
+#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31
+
+#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001
+#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002
+#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004
+#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008
+#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010
+#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020
+#define MH_DEBUG_REG26_CNT_q_MASK      0x00000fc0
+#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000
+#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG26_MH_BUSY_d_MASK  0x00004000
+#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000
+#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000
+#define MH_DEBUG_REG26_CP_SEND_q_MASK  0x00040000
+#define MH_DEBUG_REG26_CP_RTR_q_MASK   0x00080000
+#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000
+#define MH_DEBUG_REG26_VGT_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000
+#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000
+#define MH_DEBUG_REG26_RB_SEND_q_MASK  0x01000000
+#define MH_DEBUG_REG26_RB_RTR_q_MASK   0x02000000
+#define MH_DEBUG_REG26_PA_SEND_q_MASK  0x04000000
+#define MH_DEBUG_REG26_PA_RTR_q_MASK   0x08000000
+#define MH_DEBUG_REG26_RDC_VALID_MASK  0x10000000
+#define MH_DEBUG_REG26_RDC_RLAST_MASK  0x20000000
+#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000
+#define MH_DEBUG_REG26_BRC_VALID_MASK  0x80000000
+
+#define MH_DEBUG_REG26_MASK \
+     (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \
+      MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \
+      MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \
+      MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \
+      MH_DEBUG_REG26_CNT_q_MASK | \
+      MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG26_MH_BUSY_d_MASK | \
+      MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \
+      MH_DEBUG_REG26_CP_SEND_q_MASK | \
+      MH_DEBUG_REG26_CP_RTR_q_MASK | \
+      MH_DEBUG_REG26_VGT_SEND_q_MASK | \
+      MH_DEBUG_REG26_VGT_RTR_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG26_RB_SEND_q_MASK | \
+      MH_DEBUG_REG26_RB_RTR_q_MASK | \
+      MH_DEBUG_REG26_PA_SEND_q_MASK | \
+      MH_DEBUG_REG26_PA_RTR_q_MASK | \
+      MH_DEBUG_REG26_RDC_VALID_MASK | \
+      MH_DEBUG_REG26_RDC_RLAST_MASK | \
+      MH_DEBUG_REG26_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG26_BRC_VALID_MASK)
+
+#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \
+     ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \
+      (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \
+      (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \
+      (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \
+      (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \
+      (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \
+      (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \
+      (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \
+      (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \
+      (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \
+      (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \
+      (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \
+      (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \
+      (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \
+      (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \
+      (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \
+      (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \
+      (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT))
+
+#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \
+     ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT)
+#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT)
+#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT)
+#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT)
+#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT)
+#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \
+     mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+     } mh_debug_reg26_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg26_t {
+          unsigned int brc_valid                      : MH_DEBUG_REG26_BRC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG26_TLBMISS_VALID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG26_RDC_RLAST_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG26_RDC_VALID_SIZE;
+          unsigned int pa_rtr_q                       : MH_DEBUG_REG26_PA_RTR_q_SIZE;
+          unsigned int pa_send_q                      : MH_DEBUG_REG26_PA_SEND_q_SIZE;
+          unsigned int rb_rtr_q                       : MH_DEBUG_REG26_RB_RTR_q_SIZE;
+          unsigned int rb_send_q                      : MH_DEBUG_REG26_RB_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE;
+          unsigned int vgt_rtr_q                      : MH_DEBUG_REG26_VGT_RTR_q_SIZE;
+          unsigned int vgt_send_q                     : MH_DEBUG_REG26_VGT_SEND_q_SIZE;
+          unsigned int cp_rtr_q                       : MH_DEBUG_REG26_CP_RTR_q_SIZE;
+          unsigned int cp_send_q                      : MH_DEBUG_REG26_CP_SEND_q_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int any_clnt_busy                  : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE;
+          unsigned int mh_busy_d                      : MH_DEBUG_REG26_MH_BUSY_d_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE;
+          unsigned int tcd_empty_q                    : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE;
+          unsigned int cnt_q                          : MH_DEBUG_REG26_CNT_q_SIZE;
+          unsigned int rbbm_mh_clk_en_override        : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE;
+          unsigned int gat_clk_ena                    : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE;
+          unsigned int mh_cib_tcroq_clk_en_int        : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE;
+          unsigned int mh_cib_mmu_clk_en_int          : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE;
+          unsigned int mh_cib_mh_clk_en_int           : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE;
+          unsigned int mh_rbbm_busy                   : MH_DEBUG_REG26_MH_RBBM_busy_SIZE;
+     } mh_debug_reg26_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg26_t f;
+} mh_debug_reg26_u;
+
+
+/*
+ * MH_DEBUG_REG27 struct
+ */
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3
+#define MH_DEBUG_REG27_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG27_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG27_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG27_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG27_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3
+#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6
+#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9
+#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12
+#define MH_DEBUG_REG27_EFF1_WIN_SHIFT  15
+#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16
+#define MH_DEBUG_REG27_ARB_HOLD_SHIFT  17
+#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18
+#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20
+#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22
+#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23
+#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24
+#define MH_DEBUG_REG27_ARB_QUAL_SHIFT  25
+#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27
+#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28
+#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30
+#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31
+
+#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038
+#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0
+#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00
+#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000
+#define MH_DEBUG_REG27_EFF1_WIN_MASK   0x00008000
+#define MH_DEBUG_REG27_KILL_EFF1_MASK  0x00010000
+#define MH_DEBUG_REG27_ARB_HOLD_MASK   0x00020000
+#define MH_DEBUG_REG27_ARB_RTR_q_MASK  0x00040000
+#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000
+#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000
+#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000
+#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000
+#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000
+#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000
+#define MH_DEBUG_REG27_ARB_QUAL_MASK   0x02000000
+#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000
+#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000
+#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000
+#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000
+#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000
+#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000
+
+#define MH_DEBUG_REG27_MASK \
+     (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \
+      MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG27_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_MASK | \
+      MH_DEBUG_REG27_ARB_WINNER_q_MASK | \
+      MH_DEBUG_REG27_EFF1_WIN_MASK | \
+      MH_DEBUG_REG27_KILL_EFF1_MASK | \
+      MH_DEBUG_REG27_ARB_HOLD_MASK | \
+      MH_DEBUG_REG27_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG27_ARB_QUAL_MASK | \
+      MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG27_TCHOLD_IP_q_MASK)
+
+#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \
+     ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \
+      (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \
+      (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \
+      (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT))
+
+#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \
+     ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT)
+#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \
+     mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+     } mh_debug_reg27_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg27_t {
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG27_ARB_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG27_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG27_ARB_HOLD_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG27_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG27_EFF1_WIN_SIZE;
+          unsigned int arb_winner_q                   : MH_DEBUG_REG27_ARB_WINNER_q_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG27_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG27_EFF1_WINNER_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int eff2_fp_winner                 : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE;
+     } mh_debug_reg27_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg27_t f;
+} mh_debug_reg27_u;
+
+
+/*
+ * MH_DEBUG_REG28 struct
+ */
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3
+#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG28_ARB_QUAL_SIZE   1
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1
+#define MH_DEBUG_REG28_EFF1_WIN_SIZE   1
+#define MH_DEBUG_REG28_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG28_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG28_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10
+
+#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0
+#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3
+#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7
+#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9
+#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10
+#define MH_DEBUG_REG28_ARB_QUAL_SHIFT  11
+#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13
+#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14
+#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15
+#define MH_DEBUG_REG28_EFF1_WIN_SHIFT  16
+#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18
+#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19
+#define MH_DEBUG_REG28_ARB_HOLD_SHIFT  20
+#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22
+
+#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007
+#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038
+#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040
+#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080
+#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100
+#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200
+#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400
+#define MH_DEBUG_REG28_ARB_QUAL_MASK   0x00000800
+#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000
+#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000
+#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000
+#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000
+#define MH_DEBUG_REG28_EFF1_WIN_MASK   0x00010000
+#define MH_DEBUG_REG28_KILL_EFF1_MASK  0x00020000
+#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000
+#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000
+#define MH_DEBUG_REG28_ARB_HOLD_MASK   0x00100000
+#define MH_DEBUG_REG28_ARB_RTR_q_MASK  0x00200000
+#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000
+
+#define MH_DEBUG_REG28_MASK \
+     (MH_DEBUG_REG28_EFF1_WINNER_MASK | \
+      MH_DEBUG_REG28_ARB_WINNER_MASK | \
+      MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG28_ARB_QUAL_MASK | \
+      MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \
+      MH_DEBUG_REG28_EFF1_WIN_MASK | \
+      MH_DEBUG_REG28_KILL_EFF1_MASK | \
+      MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_HOLD_MASK | \
+      MH_DEBUG_REG28_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK)
+
+#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \
+     ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \
+      (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \
+      (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \
+      (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \
+      (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \
+      (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \
+      (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \
+      (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \
+      (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \
+      (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \
+      (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \
+      (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT))
+
+#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \
+     ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT)
+#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT)
+#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT)
+#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \
+     mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+     } mh_debug_reg28_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg28_t {
+          unsigned int same_page_limit_count_q        : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG28_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG28_ARB_HOLD_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG28_KILL_EFF1_SIZE;
+          unsigned int eff1_win                       : MH_DEBUG_REG28_EFF1_WIN_SIZE;
+          unsigned int rb_eff1_req                    : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE;
+          unsigned int tc_eff1_req                    : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE;
+          unsigned int vgt_eff1_req                   : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE;
+          unsigned int cp_eff1_req                    : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE;
+          unsigned int arb_qual                       : MH_DEBUG_REG28_ARB_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE;
+          unsigned int tc_send_eff1_qual              : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE;
+          unsigned int tc_send_qual                   : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE;
+          unsigned int vgt_send_qual                  : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG28_ARB_WINNER_SIZE;
+          unsigned int eff1_winner                    : MH_DEBUG_REG28_EFF1_WINNER_SIZE;
+     } mh_debug_reg28_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg28_t f;
+} mh_debug_reg28_u;
+
+
+/*
+ * MH_DEBUG_REG29 struct
+ */
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1
+#define MH_DEBUG_REG29_ARB_HOLD_SIZE   1
+#define MH_DEBUG_REG29_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG29_CLNT_REQ_SIZE   5
+#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3
+#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3
+#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9
+#define MH_DEBUG_REG29_ARB_HOLD_SHIFT  10
+#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11
+#define MH_DEBUG_REG29_CLNT_REQ_SHIFT  12
+#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17
+#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20
+#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23
+#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26
+#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29
+
+#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007
+#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038
+#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0
+#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200
+#define MH_DEBUG_REG29_ARB_HOLD_MASK   0x00000400
+#define MH_DEBUG_REG29_ARB_RTR_q_MASK  0x00000800
+#define MH_DEBUG_REG29_CLNT_REQ_MASK   0x0001f000
+#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000
+#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000
+#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000
+#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000
+#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000
+
+#define MH_DEBUG_REG29_MASK \
+     (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \
+      MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \
+      MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \
+      MH_DEBUG_REG29_ARB_HOLD_MASK | \
+      MH_DEBUG_REG29_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG29_CLNT_REQ_MASK | \
+      MH_DEBUG_REG29_RECENT_d_0_MASK | \
+      MH_DEBUG_REG29_RECENT_d_1_MASK | \
+      MH_DEBUG_REG29_RECENT_d_2_MASK | \
+      MH_DEBUG_REG29_RECENT_d_3_MASK | \
+      MH_DEBUG_REG29_RECENT_d_4_MASK)
+
+#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \
+     ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \
+      (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \
+      (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \
+      (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \
+      (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \
+      (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \
+      (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \
+      (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \
+      (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \
+      (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \
+      (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT))
+
+#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \
+     ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT)
+#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT)
+#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT)
+#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \
+     mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+     } mh_debug_reg29_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg29_t {
+          unsigned int recent_d_4                     : MH_DEBUG_REG29_RECENT_d_4_SIZE;
+          unsigned int recent_d_3                     : MH_DEBUG_REG29_RECENT_d_3_SIZE;
+          unsigned int recent_d_2                     : MH_DEBUG_REG29_RECENT_d_2_SIZE;
+          unsigned int recent_d_1                     : MH_DEBUG_REG29_RECENT_d_1_SIZE;
+          unsigned int recent_d_0                     : MH_DEBUG_REG29_RECENT_d_0_SIZE;
+          unsigned int clnt_req                       : MH_DEBUG_REG29_CLNT_REQ_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG29_ARB_RTR_q_SIZE;
+          unsigned int arb_hold                       : MH_DEBUG_REG29_ARB_HOLD_SIZE;
+          unsigned int update_recent_stack_d          : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE;
+          unsigned int least_recent_d                 : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE;
+          unsigned int least_recent_index_d           : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE;
+          unsigned int eff2_lru_winner_out            : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE;
+     } mh_debug_reg29_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg29_t f;
+} mh_debug_reg29_u;
+
+
+/*
+ * MH_DEBUG_REG30 struct
+ */
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1
+#define MH_DEBUG_REG30_TC_MH_written_SIZE 1
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1
+#define MH_DEBUG_REG30_WLAST_q_SIZE    1
+#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_CP_MH_write_SIZE 1
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1
+#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3
+#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10
+#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12
+#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19
+#define MH_DEBUG_REG30_WLAST_q_SHIFT   20
+#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21
+#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22
+#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25
+#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26
+#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27
+#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28
+#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29
+
+#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001
+#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002
+#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004
+#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008
+#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010
+#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0
+#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100
+#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200
+#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400
+#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800
+#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000
+#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000
+#define MH_DEBUG_REG30_WLAST_q_MASK    0x00100000
+#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000
+#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000
+#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000
+#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000
+#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000
+#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000
+#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000
+
+#define MH_DEBUG_REG30_MASK \
+     (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \
+      MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \
+      MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \
+      MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \
+      MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \
+      MH_DEBUG_REG30_TC_MH_written_MASK | \
+      MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \
+      MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \
+      MH_DEBUG_REG30_WLAST_q_MASK | \
+      MH_DEBUG_REG30_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG30_WBURST_CNT_q_MASK | \
+      MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_CP_MH_write_MASK | \
+      MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \
+      MH_DEBUG_REG30_ARB_WINNER_MASK)
+
+#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \
+     ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \
+      (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \
+      (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \
+      (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \
+      (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \
+      (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \
+      (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \
+      (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \
+      (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \
+      (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \
+      (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \
+      (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \
+      (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \
+      (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \
+      (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \
+      (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \
+      (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \
+      (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \
+      (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT))
+
+#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \
+     ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT)
+#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT)
+#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT)
+#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT)
+#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT)
+#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \
+     mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+     } mh_debug_reg30_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg30_t {
+          unsigned int arb_winner                     : MH_DEBUG_REG30_ARB_WINNER_SIZE;
+          unsigned int pa_send_qual                   : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE;
+          unsigned int rb_send_qual                   : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE;
+          unsigned int cp_mh_write                    : MH_DEBUG_REG30_CP_MH_write_SIZE;
+          unsigned int cp_send_qual                   : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE;
+          unsigned int wburst_cnt_q                   : MH_DEBUG_REG30_WBURST_CNT_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG30_WBURST_IP_q_SIZE;
+          unsigned int wlast_q                        : MH_DEBUG_REG30_WLAST_q_SIZE;
+          unsigned int wburst_active                  : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE;
+          unsigned int tcd_fullness_cnt_q             : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE;
+          unsigned int tc_mh_written                  : MH_DEBUG_REG30_TC_MH_written_SIZE;
+          unsigned int tc_roq_send_q                  : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE;
+          unsigned int tc_roq_rtr_dbg_q               : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE;
+          unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE;
+          unsigned int tchold_cnt_q                   : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE;
+          unsigned int tchold_ip_q                    : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE;
+          unsigned int tcd_nearfull_q                 : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE;
+          unsigned int tc_roq_same_row_bank           : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_noroq_same_row_bank         : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE;
+          unsigned int tc_arb_hold                    : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE;
+     } mh_debug_reg30_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg30_t f;
+} mh_debug_reg30_u;
+
+
+/*
+ * MH_DEBUG_REG31 struct
+ */
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26
+
+#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff
+#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000
+
+#define MH_DEBUG_REG31_MASK \
+     (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \
+      MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \
+     ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \
+     ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT)
+#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int                                : 3;
+     } mh_debug_reg31_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg31_t {
+          unsigned int                                : 3;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int rf_arbiter_config_q            : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE;
+     } mh_debug_reg31_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg31_t f;
+} mh_debug_reg31_u;
+
+
+/*
+ * MH_DEBUG_REG32 struct
+ */
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8
+#define MH_DEBUG_REG32_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG32_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8
+#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16
+#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00
+#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000
+#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG32_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG32_MASK \
+     (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_MARK_q_MASK | \
+      MH_DEBUG_REG32_ROQ_VALID_q_MASK | \
+      MH_DEBUG_REG32_TC_MH_send_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG32_KILL_EFF1_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG32_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \
+      (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \
+     ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT)
+#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \
+     mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg32_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg32_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG32_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG32_TC_MH_send_SIZE;
+          unsigned int roq_valid_q                    : MH_DEBUG_REG32_ROQ_VALID_q_SIZE;
+          unsigned int roq_mark_q                     : MH_DEBUG_REG32_ROQ_MARK_q_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg32_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg32_t f;
+} mh_debug_reg32_u;
+
+
+/*
+ * MH_DEBUG_REG33 struct
+ */
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8
+#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8
+#define MH_DEBUG_REG33_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG33_KILL_EFF1_SIZE  1
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0
+#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8
+#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16
+#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25
+#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30
+#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31
+
+#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff
+#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00
+#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000
+#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000
+#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000
+#define MH_DEBUG_REG33_KILL_EFF1_MASK  0x04000000
+#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000
+#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000
+#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000
+#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000
+#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000
+
+#define MH_DEBUG_REG33_MASK \
+     (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \
+      MH_DEBUG_REG33_ROQ_MARK_d_MASK | \
+      MH_DEBUG_REG33_ROQ_VALID_d_MASK | \
+      MH_DEBUG_REG33_TC_MH_send_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG33_KILL_EFF1_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \
+      MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \
+      MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \
+      MH_DEBUG_REG33_TC_ROQ_FULL_MASK)
+
+#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \
+     ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \
+      (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \
+      (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \
+      (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \
+      (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \
+      (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \
+      (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \
+      (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \
+      (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \
+      (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT))
+
+#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \
+     ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT)
+#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT)
+#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT)
+#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \
+     mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+     } mh_debug_reg33_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg33_t {
+          unsigned int tc_roq_full                    : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE;
+          unsigned int tc_roq_empty                   : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE;
+          unsigned int tc_eff1_qual                   : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE;
+          unsigned int any_same_row_bank              : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE;
+          unsigned int tc_roq_same_row_bank_sel       : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE;
+          unsigned int kill_eff1                      : MH_DEBUG_REG33_KILL_EFF1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG33_TC_MH_send_SIZE;
+          unsigned int roq_valid_d                    : MH_DEBUG_REG33_ROQ_VALID_d_SIZE;
+          unsigned int roq_mark_d                     : MH_DEBUG_REG33_ROQ_MARK_d_SIZE;
+          unsigned int same_row_bank_q                : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE;
+     } mh_debug_reg33_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg33_t f;
+} mh_debug_reg33_u;
+
+
+/*
+ * MH_DEBUG_REG34 struct
+ */
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24
+
+#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff
+#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000
+#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000
+
+#define MH_DEBUG_REG34_MASK \
+     (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \
+      MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK)
+
+#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \
+     ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \
+      (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \
+      (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \
+      (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT))
+
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \
+     ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT)
+#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \
+     mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+     } mh_debug_reg34_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg34_t {
+          unsigned int non_same_row_bank_req          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int non_same_row_bank_win          : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE;
+          unsigned int same_row_bank_req              : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE;
+          unsigned int same_row_bank_win              : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE;
+     } mh_debug_reg34_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg34_t f;
+} mh_debug_reg34_u;
+
+
+/*
+ * MH_DEBUG_REG35 struct
+ */
+
+#define MH_DEBUG_REG35_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27
+
+#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4
+#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5
+
+#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004
+#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008
+#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010
+#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0
+
+#define MH_DEBUG_REG35_MASK \
+     (MH_DEBUG_REG35_TC_MH_send_MASK | \
+      MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \
+      MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \
+      MH_DEBUG_REG35_ROQ_ADDR_0_MASK)
+
+#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \
+     ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \
+      (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \
+      (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \
+      (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT))
+
+#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \
+     ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT)
+#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \
+     mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+     } mh_debug_reg35_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg35_t {
+          unsigned int roq_addr_0                     : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE;
+          unsigned int same_row_bank_q_0              : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE;
+          unsigned int roq_valid_q_0                  : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE;
+          unsigned int roq_mark_q_0                   : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG35_TC_MH_send_SIZE;
+     } mh_debug_reg35_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg35_t f;
+} mh_debug_reg35_u;
+
+
+/*
+ * MH_DEBUG_REG36 struct
+ */
+
+#define MH_DEBUG_REG36_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27
+
+#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4
+#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5
+
+#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004
+#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008
+#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010
+#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0
+
+#define MH_DEBUG_REG36_MASK \
+     (MH_DEBUG_REG36_TC_MH_send_MASK | \
+      MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \
+      MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \
+      MH_DEBUG_REG36_ROQ_ADDR_1_MASK)
+
+#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \
+     ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \
+      (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \
+      (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \
+      (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT))
+
+#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \
+     ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT)
+#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \
+     mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+     } mh_debug_reg36_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg36_t {
+          unsigned int roq_addr_1                     : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE;
+          unsigned int same_row_bank_q_1              : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE;
+          unsigned int roq_valid_q_1                  : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE;
+          unsigned int roq_mark_q_1                   : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG36_TC_MH_send_SIZE;
+     } mh_debug_reg36_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg36_t f;
+} mh_debug_reg36_u;
+
+
+/*
+ * MH_DEBUG_REG37 struct
+ */
+
+#define MH_DEBUG_REG37_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27
+
+#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4
+#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5
+
+#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004
+#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008
+#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010
+#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0
+
+#define MH_DEBUG_REG37_MASK \
+     (MH_DEBUG_REG37_TC_MH_send_MASK | \
+      MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \
+      MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \
+      MH_DEBUG_REG37_ROQ_ADDR_2_MASK)
+
+#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \
+     ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \
+      (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \
+      (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \
+      (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT))
+
+#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \
+     ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT)
+#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \
+     mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+     } mh_debug_reg37_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg37_t {
+          unsigned int roq_addr_2                     : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE;
+          unsigned int same_row_bank_q_2              : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE;
+          unsigned int roq_valid_q_2                  : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE;
+          unsigned int roq_mark_q_2                   : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG37_TC_MH_send_SIZE;
+     } mh_debug_reg37_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg37_t f;
+} mh_debug_reg37_u;
+
+
+/*
+ * MH_DEBUG_REG38 struct
+ */
+
+#define MH_DEBUG_REG38_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27
+
+#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4
+#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5
+
+#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004
+#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008
+#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010
+#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0
+
+#define MH_DEBUG_REG38_MASK \
+     (MH_DEBUG_REG38_TC_MH_send_MASK | \
+      MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \
+      MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \
+      MH_DEBUG_REG38_ROQ_ADDR_3_MASK)
+
+#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \
+     ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \
+      (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \
+      (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \
+      (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT))
+
+#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \
+     ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT)
+#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \
+     mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+     } mh_debug_reg38_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg38_t {
+          unsigned int roq_addr_3                     : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE;
+          unsigned int same_row_bank_q_3              : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE;
+          unsigned int roq_valid_q_3                  : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE;
+          unsigned int roq_mark_q_3                   : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG38_TC_MH_send_SIZE;
+     } mh_debug_reg38_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg38_t f;
+} mh_debug_reg38_u;
+
+
+/*
+ * MH_DEBUG_REG39 struct
+ */
+
+#define MH_DEBUG_REG39_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27
+
+#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4
+#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5
+
+#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004
+#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008
+#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010
+#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0
+
+#define MH_DEBUG_REG39_MASK \
+     (MH_DEBUG_REG39_TC_MH_send_MASK | \
+      MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \
+      MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \
+      MH_DEBUG_REG39_ROQ_ADDR_4_MASK)
+
+#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \
+     ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \
+      (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \
+      (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \
+      (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT))
+
+#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \
+     ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT)
+#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \
+     mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+     } mh_debug_reg39_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg39_t {
+          unsigned int roq_addr_4                     : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE;
+          unsigned int same_row_bank_q_4              : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE;
+          unsigned int roq_valid_q_4                  : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE;
+          unsigned int roq_mark_q_4                   : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG39_TC_MH_send_SIZE;
+     } mh_debug_reg39_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg39_t f;
+} mh_debug_reg39_u;
+
+
+/*
+ * MH_DEBUG_REG40 struct
+ */
+
+#define MH_DEBUG_REG40_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27
+
+#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4
+#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5
+
+#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004
+#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008
+#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010
+#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0
+
+#define MH_DEBUG_REG40_MASK \
+     (MH_DEBUG_REG40_TC_MH_send_MASK | \
+      MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \
+      MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \
+      MH_DEBUG_REG40_ROQ_ADDR_5_MASK)
+
+#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \
+     ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \
+      (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \
+      (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \
+      (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT))
+
+#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \
+     ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT)
+#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \
+     mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+     } mh_debug_reg40_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg40_t {
+          unsigned int roq_addr_5                     : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE;
+          unsigned int same_row_bank_q_5              : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE;
+          unsigned int roq_valid_q_5                  : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE;
+          unsigned int roq_mark_q_5                   : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG40_TC_MH_send_SIZE;
+     } mh_debug_reg40_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg40_t f;
+} mh_debug_reg40_u;
+
+
+/*
+ * MH_DEBUG_REG41 struct
+ */
+
+#define MH_DEBUG_REG41_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27
+
+#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4
+#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5
+
+#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004
+#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008
+#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010
+#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0
+
+#define MH_DEBUG_REG41_MASK \
+     (MH_DEBUG_REG41_TC_MH_send_MASK | \
+      MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \
+      MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \
+      MH_DEBUG_REG41_ROQ_ADDR_6_MASK)
+
+#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \
+     ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \
+      (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \
+      (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \
+      (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT))
+
+#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \
+     ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT)
+#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \
+     mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+     } mh_debug_reg41_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg41_t {
+          unsigned int roq_addr_6                     : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE;
+          unsigned int same_row_bank_q_6              : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE;
+          unsigned int roq_valid_q_6                  : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE;
+          unsigned int roq_mark_q_6                   : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG41_TC_MH_send_SIZE;
+     } mh_debug_reg41_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg41_t f;
+} mh_debug_reg41_u;
+
+
+/*
+ * MH_DEBUG_REG42 struct
+ */
+
+#define MH_DEBUG_REG42_TC_MH_send_SIZE 1
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27
+
+#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4
+#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5
+
+#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001
+#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002
+#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004
+#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008
+#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010
+#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0
+
+#define MH_DEBUG_REG42_MASK \
+     (MH_DEBUG_REG42_TC_MH_send_MASK | \
+      MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \
+      MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \
+      MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \
+      MH_DEBUG_REG42_ROQ_ADDR_7_MASK)
+
+#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \
+     ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \
+      (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \
+      (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \
+      (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \
+      (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \
+      (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT))
+
+#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \
+     ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT)
+#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT)
+#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \
+     mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+     } mh_debug_reg42_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg42_t {
+          unsigned int roq_addr_7                     : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE;
+          unsigned int same_row_bank_q_7              : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE;
+          unsigned int roq_valid_q_7                  : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE;
+          unsigned int roq_mark_q_7                   : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE;
+          unsigned int tc_roq_rtr_q                   : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE;
+          unsigned int tc_mh_send                     : MH_DEBUG_REG42_TC_MH_send_SIZE;
+     } mh_debug_reg42_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg42_t f;
+} mh_debug_reg42_u;
+
+
+/*
+ * MH_DEBUG_REG43 struct
+ */
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_WE_SIZE     1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_RTR_q_SIZE  1
+#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1
+#define MH_DEBUG_REG43_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG43_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3
+#define MH_DEBUG_REG43_MMU_WE_SIZE     1
+#define MH_DEBUG_REG43_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG43_MMU_ID_SIZE     3
+#define MH_DEBUG_REG43_MMU_WRITE_SIZE  1
+#define MH_DEBUG_REG43_MMU_BLEN_SIZE   1
+#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG43_WDB_WE_SIZE     1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG43_ARB_WE_SHIFT    1
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3
+#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5
+#define MH_DEBUG_REG43_MMU_RTR_SHIFT   6
+#define MH_DEBUG_REG43_ARB_ID_q_SHIFT  7
+#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10
+#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13
+#define MH_DEBUG_REG43_MMU_WE_SHIFT    16
+#define MH_DEBUG_REG43_ARQ_RTR_SHIFT   17
+#define MH_DEBUG_REG43_MMU_ID_SHIFT    18
+#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21
+#define MH_DEBUG_REG43_MMU_BLEN_SHIFT  22
+#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24
+#define MH_DEBUG_REG43_WDB_WE_SHIFT    25
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27
+
+#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG43_ARB_WE_MASK     0x00000002
+#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG43_ARB_RTR_q_MASK  0x00000008
+#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010
+#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020
+#define MH_DEBUG_REG43_MMU_RTR_MASK    0x00000040
+#define MH_DEBUG_REG43_ARB_ID_q_MASK   0x00000380
+#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400
+#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800
+#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000
+#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000
+#define MH_DEBUG_REG43_MMU_WE_MASK     0x00010000
+#define MH_DEBUG_REG43_ARQ_RTR_MASK    0x00020000
+#define MH_DEBUG_REG43_MMU_ID_MASK     0x001c0000
+#define MH_DEBUG_REG43_MMU_WRITE_MASK  0x00200000
+#define MH_DEBUG_REG43_MMU_BLEN_MASK   0x00400000
+#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000
+#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000
+#define MH_DEBUG_REG43_WDB_WE_MASK     0x02000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000
+#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000
+
+#define MH_DEBUG_REG43_MASK \
+     (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_ARB_WE_MASK | \
+      MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \
+      MH_DEBUG_REG43_ARB_RTR_q_MASK | \
+      MH_DEBUG_REG43_ARB_REG_RTR_MASK | \
+      MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_RTR_MASK | \
+      MH_DEBUG_REG43_ARB_ID_q_MASK | \
+      MH_DEBUG_REG43_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG43_ARB_BLEN_q_MASK | \
+      MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG43_MMU_WE_MASK | \
+      MH_DEBUG_REG43_ARQ_RTR_MASK | \
+      MH_DEBUG_REG43_MMU_ID_MASK | \
+      MH_DEBUG_REG43_MMU_WRITE_MASK | \
+      MH_DEBUG_REG43_MMU_BLEN_MASK | \
+      MH_DEBUG_REG43_WBURST_IP_q_MASK | \
+      MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG43_WDB_WE_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK)
+
+#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \
+     ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \
+      (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \
+      (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \
+      (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \
+      (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \
+      (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \
+      (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \
+      (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \
+      (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \
+      (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \
+      (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \
+      (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \
+      (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT))
+
+#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \
+     ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT)
+#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT)
+#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \
+     mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int                                : 4;
+     } mh_debug_reg43_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg43_t {
+          unsigned int                                : 4;
+          unsigned int wdb_rtr_skid_3                 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG43_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE;
+          unsigned int wburst_ip_q                    : MH_DEBUG_REG43_WBURST_IP_q_SIZE;
+          unsigned int mmu_blen                       : MH_DEBUG_REG43_MMU_BLEN_SIZE;
+          unsigned int mmu_write                      : MH_DEBUG_REG43_MMU_WRITE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG43_MMU_ID_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG43_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG43_MMU_WE_SIZE;
+          unsigned int arq_fifo_cnt_q                 : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arb_blen_q                     : MH_DEBUG_REG43_ARB_BLEN_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG43_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG43_ARB_ID_q_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG43_MMU_RTR_SIZE;
+          unsigned int wdat_burst_rtr                 : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE;
+          unsigned int arb_reg_rtr                    : MH_DEBUG_REG43_ARB_REG_RTR_SIZE;
+          unsigned int arb_rtr_q                      : MH_DEBUG_REG43_ARB_RTR_q_SIZE;
+          unsigned int arb_reg_valid_q                : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG43_ARB_WE_SIZE;
+          unsigned int arb_reg_we_q                   : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE;
+     } mh_debug_reg43_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg43_t f;
+} mh_debug_reg43_u;
+
+
+/*
+ * MH_DEBUG_REG44 struct
+ */
+
+#define MH_DEBUG_REG44_ARB_WE_SIZE     1
+#define MH_DEBUG_REG44_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG44_ARB_VAD_q_SIZE  28
+
+#define MH_DEBUG_REG44_ARB_WE_SHIFT    0
+#define MH_DEBUG_REG44_ARB_ID_q_SHIFT  1
+#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4
+
+#define MH_DEBUG_REG44_ARB_WE_MASK     0x00000001
+#define MH_DEBUG_REG44_ARB_ID_q_MASK   0x0000000e
+#define MH_DEBUG_REG44_ARB_VAD_q_MASK  0xfffffff0
+
+#define MH_DEBUG_REG44_MASK \
+     (MH_DEBUG_REG44_ARB_WE_MASK | \
+      MH_DEBUG_REG44_ARB_ID_q_MASK | \
+      MH_DEBUG_REG44_ARB_VAD_q_MASK)
+
+#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \
+     ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \
+      (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT))
+
+#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \
+     ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \
+     mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+     } mh_debug_reg44_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg44_t {
+          unsigned int arb_vad_q                      : MH_DEBUG_REG44_ARB_VAD_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG44_ARB_ID_q_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG44_ARB_WE_SIZE;
+     } mh_debug_reg44_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg44_t f;
+} mh_debug_reg44_u;
+
+
+/*
+ * MH_DEBUG_REG45 struct
+ */
+
+#define MH_DEBUG_REG45_MMU_WE_SIZE     1
+#define MH_DEBUG_REG45_MMU_ID_SIZE     3
+#define MH_DEBUG_REG45_MMU_PAD_SIZE    28
+
+#define MH_DEBUG_REG45_MMU_WE_SHIFT    0
+#define MH_DEBUG_REG45_MMU_ID_SHIFT    1
+#define MH_DEBUG_REG45_MMU_PAD_SHIFT   4
+
+#define MH_DEBUG_REG45_MMU_WE_MASK     0x00000001
+#define MH_DEBUG_REG45_MMU_ID_MASK     0x0000000e
+#define MH_DEBUG_REG45_MMU_PAD_MASK    0xfffffff0
+
+#define MH_DEBUG_REG45_MASK \
+     (MH_DEBUG_REG45_MMU_WE_MASK | \
+      MH_DEBUG_REG45_MMU_ID_MASK | \
+      MH_DEBUG_REG45_MMU_PAD_MASK)
+
+#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \
+     ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \
+      (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \
+      (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT))
+
+#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \
+     ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT)
+#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \
+     mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+     } mh_debug_reg45_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg45_t {
+          unsigned int mmu_pad                        : MH_DEBUG_REG45_MMU_PAD_SIZE;
+          unsigned int mmu_id                         : MH_DEBUG_REG45_MMU_ID_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG45_MMU_WE_SIZE;
+     } mh_debug_reg45_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg45_t f;
+} mh_debug_reg45_u;
+
+
+/*
+ * MH_DEBUG_REG46 struct
+ */
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WE_SIZE     1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8
+#define MH_DEBUG_REG46_ARB_WLAST_SIZE  1
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0
+#define MH_DEBUG_REG46_WDB_WE_SHIFT    1
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3
+#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4
+#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19
+#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24
+
+#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001
+#define MH_DEBUG_REG46_WDB_WE_MASK     0x00000002
+#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004
+#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008
+#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0
+#define MH_DEBUG_REG46_ARB_WLAST_MASK  0x00001000
+#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000
+#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000
+#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000
+#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000
+#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000
+#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000
+
+#define MH_DEBUG_REG46_MASK \
+     (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WE_MASK | \
+      MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \
+      MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \
+      MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \
+      MH_DEBUG_REG46_ARB_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \
+      MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WID_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \
+      MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK)
+
+#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \
+     ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \
+      (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \
+      (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \
+      (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \
+      (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \
+      (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \
+      (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \
+      (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \
+      (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \
+      (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \
+      (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \
+      (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT))
+
+#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \
+     ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT)
+#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT)
+#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT)
+#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \
+     mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+     } mh_debug_reg46_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg46_t {
+          unsigned int wdb_wdc_wstrb                  : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE;
+          unsigned int wdb_wdc_wlast                  : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE;
+          unsigned int wdb_wdc_wid                    : MH_DEBUG_REG46_WDB_WDC_WID_SIZE;
+          unsigned int wdc_wdb_re_q                   : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE;
+          unsigned int wdb_fifo_cnt_q                 : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE;
+          unsigned int wdb_ctrl_empty                 : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE;
+          unsigned int arb_wlast                      : MH_DEBUG_REG46_ARB_WLAST_SIZE;
+          unsigned int arb_wstrb_q                    : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE;
+          unsigned int wdb_rtr_skid_4                 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE;
+          unsigned int wdat_reg_valid_q               : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE;
+          unsigned int wdb_we                         : MH_DEBUG_REG46_WDB_WE_SIZE;
+          unsigned int wdat_reg_we_q                  : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE;
+     } mh_debug_reg46_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg46_t f;
+} mh_debug_reg46_u;
+
+
+/*
+ * MH_DEBUG_REG47 struct
+ */
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0
+
+#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff
+
+#define MH_DEBUG_REG47_MASK \
+     (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK)
+
+#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \
+     ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT))
+
+#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \
+     ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \
+     mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg47_t {
+          unsigned int wdb_wdc_wdata_31_0             : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE;
+     } mh_debug_reg47_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg47_t f;
+} mh_debug_reg47_u;
+
+
+/*
+ * MH_DEBUG_REG48 struct
+ */
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0
+
+#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff
+
+#define MH_DEBUG_REG48_MASK \
+     (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK)
+
+#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \
+     ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT))
+
+#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \
+     ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \
+     mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg48_t {
+          unsigned int wdb_wdc_wdata_63_32            : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE;
+     } mh_debug_reg48_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg48_t f;
+} mh_debug_reg48_u;
+
+
+/*
+ * MH_DEBUG_REG49 struct
+ */
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1
+#define MH_DEBUG_REG49_RVALID_q_SIZE   1
+#define MH_DEBUG_REG49_RREADY_q_SIZE   1
+#define MH_DEBUG_REG49_RLAST_q_SIZE    1
+#define MH_DEBUG_REG49_BVALID_q_SIZE   1
+#define MH_DEBUG_REG49_BREADY_q_SIZE   1
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14
+#define MH_DEBUG_REG49_RVALID_q_SHIFT  15
+#define MH_DEBUG_REG49_RREADY_q_SHIFT  16
+#define MH_DEBUG_REG49_RLAST_q_SHIFT   17
+#define MH_DEBUG_REG49_BVALID_q_SHIFT  18
+#define MH_DEBUG_REG49_BREADY_q_SHIFT  19
+
+#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001
+#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002
+#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004
+#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008
+#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010
+#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020
+#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040
+#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80
+#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000
+#define MH_DEBUG_REG49_RVALID_q_MASK   0x00008000
+#define MH_DEBUG_REG49_RREADY_q_MASK   0x00010000
+#define MH_DEBUG_REG49_RLAST_q_MASK    0x00020000
+#define MH_DEBUG_REG49_BVALID_q_MASK   0x00040000
+#define MH_DEBUG_REG49_BREADY_q_MASK   0x00080000
+
+#define MH_DEBUG_REG49_MASK \
+     (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \
+      MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \
+      MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \
+      MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \
+      MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \
+      MH_DEBUG_REG49_RVALID_q_MASK | \
+      MH_DEBUG_REG49_RREADY_q_MASK | \
+      MH_DEBUG_REG49_RLAST_q_MASK | \
+      MH_DEBUG_REG49_BVALID_q_MASK | \
+      MH_DEBUG_REG49_BREADY_q_MASK)
+
+#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \
+     ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \
+      (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \
+      (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \
+      (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \
+      (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \
+      (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \
+      (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \
+      (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \
+      (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \
+      (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \
+      (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \
+      (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT))
+
+#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \
+     ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT)
+#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT)
+#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT)
+#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT)
+#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT)
+#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \
+     mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int                                : 12;
+     } mh_debug_reg49_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg49_t {
+          unsigned int                                : 12;
+          unsigned int bready_q                       : MH_DEBUG_REG49_BREADY_q_SIZE;
+          unsigned int bvalid_q                       : MH_DEBUG_REG49_BVALID_q_SIZE;
+          unsigned int rlast_q                        : MH_DEBUG_REG49_RLAST_q_SIZE;
+          unsigned int rready_q                       : MH_DEBUG_REG49_RREADY_q_SIZE;
+          unsigned int rvalid_q                       : MH_DEBUG_REG49_RVALID_q_SIZE;
+          unsigned int rarc_ctrl_re_q                 : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE;
+          unsigned int arc_ctrl_re_q                  : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE;
+          unsigned int inflt_limit_cnt_q              : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE;
+          unsigned int inflt_limit_q                  : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int arq_ctrl_write                 : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE;
+          unsigned int arq_ctrl_empty                 : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE;
+          unsigned int ctrl_rarc_empty                : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE;
+          unsigned int ctrl_arc_empty                 : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE;
+     } mh_debug_reg49_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg49_t f;
+} mh_debug_reg49_u;
+
+
+/*
+ * MH_DEBUG_REG50 struct
+ */
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1
+#define MH_DEBUG_REG50_RDC_VALID_SIZE  1
+#define MH_DEBUG_REG50_RDC_RID_SIZE    3
+#define MH_DEBUG_REG50_RDC_RLAST_SIZE  1
+#define MH_DEBUG_REG50_RDC_RRESP_SIZE  2
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0
+#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1
+#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3
+#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4
+#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5
+#define MH_DEBUG_REG50_RDC_RID_SHIFT   6
+#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9
+#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22
+#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29
+
+#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001
+#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002
+#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004
+#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008
+#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010
+#define MH_DEBUG_REG50_RDC_VALID_MASK  0x00000020
+#define MH_DEBUG_REG50_RDC_RID_MASK    0x000001c0
+#define MH_DEBUG_REG50_RDC_RLAST_MASK  0x00000200
+#define MH_DEBUG_REG50_RDC_RRESP_MASK  0x00000c00
+#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000
+#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000
+#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000
+#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000
+#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000
+#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000
+#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000
+#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000
+
+#define MH_DEBUG_REG50_MASK \
+     (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \
+      MH_DEBUG_REG50_MH_TC_mcsend_MASK | \
+      MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG50_TLBMISS_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_VALID_MASK | \
+      MH_DEBUG_REG50_RDC_RID_MASK | \
+      MH_DEBUG_REG50_RDC_RLAST_MASK | \
+      MH_DEBUG_REG50_RDC_RRESP_MASK | \
+      MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \
+      MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \
+      MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \
+      MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \
+      MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \
+      MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK)
+
+#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \
+     ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \
+      (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \
+      (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \
+      (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \
+      (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \
+      (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \
+      (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \
+      (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \
+      (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \
+      (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \
+      (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \
+      (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \
+      (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT))
+
+#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \
+     ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT)
+#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT)
+#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT)
+#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT)
+#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT)
+#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \
+     mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+     } mh_debug_reg50_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg50_t {
+          unsigned int mh_clnt_axi_id_reuse_mmur_id   : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE;
+          unsigned int cnt_hold_q1                    : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE;
+          unsigned int tlbmiss_return_cnt_q           : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE;
+          unsigned int mmu_id_response                : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE;
+          unsigned int outstanding_mmuid_cnt_q        : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE;
+          unsigned int mmu_id_request_q               : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int rdc_rresp                      : MH_DEBUG_REG50_RDC_RRESP_SIZE;
+          unsigned int rdc_rlast                      : MH_DEBUG_REG50_RDC_RLAST_SIZE;
+          unsigned int rdc_rid                        : MH_DEBUG_REG50_RDC_RID_SIZE;
+          unsigned int rdc_valid                      : MH_DEBUG_REG50_RDC_VALID_SIZE;
+          unsigned int tlbmiss_valid                  : MH_DEBUG_REG50_TLBMISS_VALID_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE;
+          unsigned int mh_tc_mcsend                   : MH_DEBUG_REG50_MH_TC_mcsend_SIZE;
+          unsigned int mh_vgt_grb_send                : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE;
+          unsigned int mh_cp_grb_send                 : MH_DEBUG_REG50_MH_CP_grb_send_SIZE;
+     } mh_debug_reg50_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg50_t f;
+} mh_debug_reg50_u;
+
+
+/*
+ * MH_DEBUG_REG51 struct
+ */
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0
+
+#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG51_MASK \
+     (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK)
+
+#define MH_DEBUG_REG51(rf_mmu_page_fault) \
+     ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT))
+
+#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \
+     ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \
+     mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg51_t {
+          unsigned int rf_mmu_page_fault              : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE;
+     } mh_debug_reg51_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg51_t f;
+} mh_debug_reg51_u;
+
+
+/*
+ * MH_DEBUG_REG52 struct
+ */
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2
+#define MH_DEBUG_REG52_ARB_WE_SIZE     1
+#define MH_DEBUG_REG52_MMU_RTR_SIZE    1
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22
+#define MH_DEBUG_REG52_ARB_ID_q_SIZE   3
+#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1
+#define MH_DEBUG_REG52_client_behavior_q_SIZE 2
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0
+#define MH_DEBUG_REG52_ARB_WE_SHIFT    2
+#define MH_DEBUG_REG52_MMU_RTR_SHIFT   3
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4
+#define MH_DEBUG_REG52_ARB_ID_q_SHIFT  26
+#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29
+#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30
+
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003
+#define MH_DEBUG_REG52_ARB_WE_MASK     0x00000004
+#define MH_DEBUG_REG52_MMU_RTR_MASK    0x00000008
+#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0
+#define MH_DEBUG_REG52_ARB_ID_q_MASK   0x1c000000
+#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000
+#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000
+
+#define MH_DEBUG_REG52_MASK \
+     (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \
+      MH_DEBUG_REG52_ARB_WE_MASK | \
+      MH_DEBUG_REG52_MMU_RTR_MASK | \
+      MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \
+      MH_DEBUG_REG52_ARB_ID_q_MASK | \
+      MH_DEBUG_REG52_ARB_WRITE_q_MASK | \
+      MH_DEBUG_REG52_client_behavior_q_MASK)
+
+#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \
+     ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \
+      (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \
+      (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \
+      (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \
+      (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \
+      (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT))
+
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \
+     ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT)
+#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT)
+#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT)
+#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT)
+#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \
+     mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+     } mh_debug_reg52_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg52_t {
+          unsigned int client_behavior_q              : MH_DEBUG_REG52_client_behavior_q_SIZE;
+          unsigned int arb_write_q                    : MH_DEBUG_REG52_ARB_WRITE_q_SIZE;
+          unsigned int arb_id_q                       : MH_DEBUG_REG52_ARB_ID_q_SIZE;
+          unsigned int rf_mmu_config_q_25_to_4        : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE;
+          unsigned int mmu_rtr                        : MH_DEBUG_REG52_MMU_RTR_SIZE;
+          unsigned int arb_we                         : MH_DEBUG_REG52_ARB_WE_SIZE;
+          unsigned int rf_mmu_config_q_1_to_0         : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE;
+     } mh_debug_reg52_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg52_t f;
+} mh_debug_reg52_u;
+
+
+/*
+ * MH_DEBUG_REG53 struct
+ */
+
+#define MH_DEBUG_REG53_stage1_valid_SIZE 1
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG53_tag_match_q_SIZE 1
+#define MH_DEBUG_REG53_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG53_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG53_MMU_MISS_SIZE   1
+#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_HIT_SIZE    1
+#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16
+
+#define MH_DEBUG_REG53_stage1_valid_SHIFT 0
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1
+#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2
+#define MH_DEBUG_REG53_tag_match_q_SHIFT 3
+#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4
+#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5
+#define MH_DEBUG_REG53_MMU_MISS_SHIFT  6
+#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8
+#define MH_DEBUG_REG53_MMU_HIT_SHIFT   9
+#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16
+
+#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001
+#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002
+#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004
+#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008
+#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010
+#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020
+#define MH_DEBUG_REG53_MMU_MISS_MASK   0x00000040
+#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080
+#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100
+#define MH_DEBUG_REG53_MMU_HIT_MASK    0x00000200
+#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400
+#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000
+#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000
+#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG53_MASK \
+     (MH_DEBUG_REG53_stage1_valid_MASK | \
+      MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG53_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG53_tag_match_q_MASK | \
+      MH_DEBUG_REG53_tag_miss_q_MASK | \
+      MH_DEBUG_REG53_va_in_range_q_MASK | \
+      MH_DEBUG_REG53_MMU_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_READ_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_READ_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \
+      MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \
+      MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK)
+
+#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \
+     ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \
+      (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \
+      (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \
+      (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \
+      (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \
+      (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \
+      (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \
+      (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \
+      (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \
+      (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \
+      (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \
+      (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT))
+
+#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \
+     ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT)
+#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT)
+#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT)
+#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT)
+#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \
+     mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+     } mh_debug_reg53_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg53_t {
+          unsigned int req_va_offset_q                : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE;
+          unsigned int mmu_split_mode_nontc_hit       : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE;
+          unsigned int mmu_split_mode_nontc_miss      : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE;
+          unsigned int mmu_split_mode_tc_hit          : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE;
+          unsigned int mmu_split_mode_tc_miss         : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE;
+          unsigned int mmu_write_hit                  : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE;
+          unsigned int mmu_read_hit                   : MH_DEBUG_REG53_MMU_READ_HIT_SIZE;
+          unsigned int mmu_hit                        : MH_DEBUG_REG53_MMU_HIT_SIZE;
+          unsigned int mmu_write_miss                 : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE;
+          unsigned int mmu_read_miss                  : MH_DEBUG_REG53_MMU_READ_MISS_SIZE;
+          unsigned int mmu_miss                       : MH_DEBUG_REG53_MMU_MISS_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG53_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG53_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG53_tag_match_q_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG53_pa_in_mpu_range_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG53_stage1_valid_SIZE;
+     } mh_debug_reg53_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg53_t f;
+} mh_debug_reg53_u;
+
+
+/*
+ * MH_DEBUG_REG54 struct
+ */
+
+#define MH_DEBUG_REG54_ARQ_RTR_SIZE    1
+#define MH_DEBUG_REG54_MMU_WE_SIZE     1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1
+#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1
+#define MH_DEBUG_REG54_stage1_valid_SIZE 1
+#define MH_DEBUG_REG54_stage2_valid_SIZE 1
+#define MH_DEBUG_REG54_client_behavior_q_SIZE 2
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1
+#define MH_DEBUG_REG54_tag_match_q_SIZE 1
+#define MH_DEBUG_REG54_tag_miss_q_SIZE 1
+#define MH_DEBUG_REG54_va_in_range_q_SIZE 1
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1
+#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_SHIFT   0
+#define MH_DEBUG_REG54_MMU_WE_SHIFT    1
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5
+#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6
+#define MH_DEBUG_REG54_stage1_valid_SHIFT 7
+#define MH_DEBUG_REG54_stage2_valid_SHIFT 8
+#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11
+#define MH_DEBUG_REG54_tag_match_q_SHIFT 12
+#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13
+#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15
+#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16
+
+#define MH_DEBUG_REG54_ARQ_RTR_MASK    0x00000001
+#define MH_DEBUG_REG54_MMU_WE_MASK     0x00000002
+#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004
+#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008
+#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010
+#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020
+#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040
+#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080
+#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100
+#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600
+#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800
+#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000
+#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000
+#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000
+#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000
+#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000
+
+#define MH_DEBUG_REG54_MASK \
+     (MH_DEBUG_REG54_ARQ_RTR_MASK | \
+      MH_DEBUG_REG54_MMU_WE_MASK | \
+      MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \
+      MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \
+      MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \
+      MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \
+      MH_DEBUG_REG54_pa_in_mpu_range_MASK | \
+      MH_DEBUG_REG54_stage1_valid_MASK | \
+      MH_DEBUG_REG54_stage2_valid_MASK | \
+      MH_DEBUG_REG54_client_behavior_q_MASK | \
+      MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \
+      MH_DEBUG_REG54_tag_match_q_MASK | \
+      MH_DEBUG_REG54_tag_miss_q_MASK | \
+      MH_DEBUG_REG54_va_in_range_q_MASK | \
+      MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \
+      MH_DEBUG_REG54_TAG_valid_q_MASK)
+
+#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \
+     ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \
+      (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \
+      (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \
+      (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \
+      (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \
+      (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \
+      (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \
+      (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \
+      (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \
+      (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \
+      (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \
+      (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \
+      (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \
+      (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \
+      (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \
+      (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT))
+
+#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \
+     ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT)
+#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT)
+#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT)
+#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT)
+#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT)
+#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT)
+#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT)
+#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT)
+#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT)
+#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT)
+#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT)
+#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \
+     mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+     } mh_debug_reg54_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg54_t {
+          unsigned int tag_valid_q                    : MH_DEBUG_REG54_TAG_valid_q_SIZE;
+          unsigned int pte_fetch_complete_q           : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE;
+          unsigned int va_in_range_q                  : MH_DEBUG_REG54_va_in_range_q_SIZE;
+          unsigned int tag_miss_q                     : MH_DEBUG_REG54_tag_miss_q_SIZE;
+          unsigned int tag_match_q                    : MH_DEBUG_REG54_tag_match_q_SIZE;
+          unsigned int ignore_tag_miss_q              : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE;
+          unsigned int client_behavior_q              : MH_DEBUG_REG54_client_behavior_q_SIZE;
+          unsigned int stage2_valid                   : MH_DEBUG_REG54_stage2_valid_SIZE;
+          unsigned int stage1_valid                   : MH_DEBUG_REG54_stage1_valid_SIZE;
+          unsigned int pa_in_mpu_range                : MH_DEBUG_REG54_pa_in_mpu_range_SIZE;
+          unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE;
+          unsigned int mh_tlbmiss_send                : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE;
+          unsigned int tlbmiss_ctrl_rts               : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE;
+          unsigned int ctrl_tlbmiss_re_q              : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE;
+          unsigned int mmu_we                         : MH_DEBUG_REG54_MMU_WE_SIZE;
+          unsigned int arq_rtr                        : MH_DEBUG_REG54_ARQ_RTR_SIZE;
+     } mh_debug_reg54_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg54_t f;
+} mh_debug_reg54_u;
+
+
+/*
+ * MH_DEBUG_REG55 struct
+ */
+
+#define MH_DEBUG_REG55_TAG0_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG55_TAG1_VA_SIZE    13
+#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1
+
+#define MH_DEBUG_REG55_TAG0_VA_SHIFT   0
+#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13
+#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG55_TAG1_VA_SHIFT   16
+#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29
+
+#define MH_DEBUG_REG55_TAG0_VA_MASK    0x00001fff
+#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000
+#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG55_TAG1_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000
+
+#define MH_DEBUG_REG55_MASK \
+     (MH_DEBUG_REG55_TAG0_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_0_MASK | \
+      MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG55_TAG1_VA_MASK | \
+      MH_DEBUG_REG55_TAG_valid_q_1_MASK)
+
+#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \
+     ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \
+      (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \
+      (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \
+      (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \
+      (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT))
+
+#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \
+     ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT)
+#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT)
+#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \
+     mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg55_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg55_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_1                  : MH_DEBUG_REG55_TAG_valid_q_1_SIZE;
+          unsigned int tag1_va                        : MH_DEBUG_REG55_TAG1_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_0                  : MH_DEBUG_REG55_TAG_valid_q_0_SIZE;
+          unsigned int tag0_va                        : MH_DEBUG_REG55_TAG0_VA_SIZE;
+     } mh_debug_reg55_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg55_t f;
+} mh_debug_reg55_u;
+
+
+/*
+ * MH_DEBUG_REG56 struct
+ */
+
+#define MH_DEBUG_REG56_TAG2_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG56_TAG3_VA_SIZE    13
+#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1
+
+#define MH_DEBUG_REG56_TAG2_VA_SHIFT   0
+#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13
+#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG56_TAG3_VA_SHIFT   16
+#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29
+
+#define MH_DEBUG_REG56_TAG2_VA_MASK    0x00001fff
+#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000
+#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG56_TAG3_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000
+
+#define MH_DEBUG_REG56_MASK \
+     (MH_DEBUG_REG56_TAG2_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_2_MASK | \
+      MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG56_TAG3_VA_MASK | \
+      MH_DEBUG_REG56_TAG_valid_q_3_MASK)
+
+#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \
+     ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \
+      (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \
+      (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \
+      (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \
+      (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT))
+
+#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \
+     ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT)
+#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT)
+#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \
+     mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg56_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg56_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_3                  : MH_DEBUG_REG56_TAG_valid_q_3_SIZE;
+          unsigned int tag3_va                        : MH_DEBUG_REG56_TAG3_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_2                  : MH_DEBUG_REG56_TAG_valid_q_2_SIZE;
+          unsigned int tag2_va                        : MH_DEBUG_REG56_TAG2_VA_SIZE;
+     } mh_debug_reg56_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg56_t f;
+} mh_debug_reg56_u;
+
+
+/*
+ * MH_DEBUG_REG57 struct
+ */
+
+#define MH_DEBUG_REG57_TAG4_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG57_TAG5_VA_SIZE    13
+#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1
+
+#define MH_DEBUG_REG57_TAG4_VA_SHIFT   0
+#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13
+#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG57_TAG5_VA_SHIFT   16
+#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29
+
+#define MH_DEBUG_REG57_TAG4_VA_MASK    0x00001fff
+#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000
+#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG57_TAG5_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000
+
+#define MH_DEBUG_REG57_MASK \
+     (MH_DEBUG_REG57_TAG4_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_4_MASK | \
+      MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG57_TAG5_VA_MASK | \
+      MH_DEBUG_REG57_TAG_valid_q_5_MASK)
+
+#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \
+     ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \
+      (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \
+      (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \
+      (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \
+      (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT))
+
+#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \
+     ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT)
+#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT)
+#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \
+     mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg57_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg57_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_5                  : MH_DEBUG_REG57_TAG_valid_q_5_SIZE;
+          unsigned int tag5_va                        : MH_DEBUG_REG57_TAG5_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_4                  : MH_DEBUG_REG57_TAG_valid_q_4_SIZE;
+          unsigned int tag4_va                        : MH_DEBUG_REG57_TAG4_VA_SIZE;
+     } mh_debug_reg57_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg57_t f;
+} mh_debug_reg57_u;
+
+
+/*
+ * MH_DEBUG_REG58 struct
+ */
+
+#define MH_DEBUG_REG58_TAG6_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG58_TAG7_VA_SIZE    13
+#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1
+
+#define MH_DEBUG_REG58_TAG6_VA_SHIFT   0
+#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13
+#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG58_TAG7_VA_SHIFT   16
+#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29
+
+#define MH_DEBUG_REG58_TAG6_VA_MASK    0x00001fff
+#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000
+#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG58_TAG7_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000
+
+#define MH_DEBUG_REG58_MASK \
+     (MH_DEBUG_REG58_TAG6_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_6_MASK | \
+      MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG58_TAG7_VA_MASK | \
+      MH_DEBUG_REG58_TAG_valid_q_7_MASK)
+
+#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \
+     ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \
+      (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \
+      (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \
+      (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \
+      (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT))
+
+#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \
+     ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT)
+#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT)
+#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \
+     mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg58_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg58_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_7                  : MH_DEBUG_REG58_TAG_valid_q_7_SIZE;
+          unsigned int tag7_va                        : MH_DEBUG_REG58_TAG7_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_6                  : MH_DEBUG_REG58_TAG_valid_q_6_SIZE;
+          unsigned int tag6_va                        : MH_DEBUG_REG58_TAG6_VA_SIZE;
+     } mh_debug_reg58_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg58_t f;
+} mh_debug_reg58_u;
+
+
+/*
+ * MH_DEBUG_REG59 struct
+ */
+
+#define MH_DEBUG_REG59_TAG8_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG59_TAG9_VA_SIZE    13
+#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1
+
+#define MH_DEBUG_REG59_TAG8_VA_SHIFT   0
+#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13
+#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG59_TAG9_VA_SHIFT   16
+#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29
+
+#define MH_DEBUG_REG59_TAG8_VA_MASK    0x00001fff
+#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000
+#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG59_TAG9_VA_MASK    0x1fff0000
+#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000
+
+#define MH_DEBUG_REG59_MASK \
+     (MH_DEBUG_REG59_TAG8_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_8_MASK | \
+      MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG59_TAG9_VA_MASK | \
+      MH_DEBUG_REG59_TAG_valid_q_9_MASK)
+
+#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \
+     ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \
+      (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \
+      (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \
+      (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \
+      (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT))
+
+#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \
+     ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT)
+#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT)
+#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \
+     mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg59_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg59_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_9                  : MH_DEBUG_REG59_TAG_valid_q_9_SIZE;
+          unsigned int tag9_va                        : MH_DEBUG_REG59_TAG9_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_8                  : MH_DEBUG_REG59_TAG_valid_q_8_SIZE;
+          unsigned int tag8_va                        : MH_DEBUG_REG59_TAG8_VA_SIZE;
+     } mh_debug_reg59_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg59_t f;
+} mh_debug_reg59_u;
+
+
+/*
+ * MH_DEBUG_REG60 struct
+ */
+
+#define MH_DEBUG_REG60_TAG10_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG60_TAG11_VA_SIZE   13
+#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1
+
+#define MH_DEBUG_REG60_TAG10_VA_SHIFT  0
+#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13
+#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG60_TAG11_VA_SHIFT  16
+#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29
+
+#define MH_DEBUG_REG60_TAG10_VA_MASK   0x00001fff
+#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000
+#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG60_TAG11_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000
+
+#define MH_DEBUG_REG60_MASK \
+     (MH_DEBUG_REG60_TAG10_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_10_MASK | \
+      MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG60_TAG11_VA_MASK | \
+      MH_DEBUG_REG60_TAG_valid_q_11_MASK)
+
+#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \
+     ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \
+      (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \
+      (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \
+      (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \
+      (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT))
+
+#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \
+     ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT)
+#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT)
+#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \
+     mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg60_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg60_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_11                 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE;
+          unsigned int tag11_va                       : MH_DEBUG_REG60_TAG11_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_10                 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE;
+          unsigned int tag10_va                       : MH_DEBUG_REG60_TAG10_VA_SIZE;
+     } mh_debug_reg60_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg60_t f;
+} mh_debug_reg60_u;
+
+
+/*
+ * MH_DEBUG_REG61 struct
+ */
+
+#define MH_DEBUG_REG61_TAG12_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG61_TAG13_VA_SIZE   13
+#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1
+
+#define MH_DEBUG_REG61_TAG12_VA_SHIFT  0
+#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13
+#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG61_TAG13_VA_SHIFT  16
+#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29
+
+#define MH_DEBUG_REG61_TAG12_VA_MASK   0x00001fff
+#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000
+#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG61_TAG13_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000
+
+#define MH_DEBUG_REG61_MASK \
+     (MH_DEBUG_REG61_TAG12_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_12_MASK | \
+      MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG61_TAG13_VA_MASK | \
+      MH_DEBUG_REG61_TAG_valid_q_13_MASK)
+
+#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \
+     ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \
+      (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \
+      (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \
+      (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \
+      (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT))
+
+#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \
+     ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT)
+#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT)
+#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \
+     mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg61_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg61_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_13                 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE;
+          unsigned int tag13_va                       : MH_DEBUG_REG61_TAG13_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_12                 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE;
+          unsigned int tag12_va                       : MH_DEBUG_REG61_TAG12_VA_SIZE;
+     } mh_debug_reg61_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg61_t f;
+} mh_debug_reg61_u;
+
+
+/*
+ * MH_DEBUG_REG62 struct
+ */
+
+#define MH_DEBUG_REG62_TAG14_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2
+#define MH_DEBUG_REG62_TAG15_VA_SIZE   13
+#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1
+
+#define MH_DEBUG_REG62_TAG14_VA_SHIFT  0
+#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13
+#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14
+#define MH_DEBUG_REG62_TAG15_VA_SHIFT  16
+#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29
+
+#define MH_DEBUG_REG62_TAG14_VA_MASK   0x00001fff
+#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000
+#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000
+#define MH_DEBUG_REG62_TAG15_VA_MASK   0x1fff0000
+#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000
+
+#define MH_DEBUG_REG62_MASK \
+     (MH_DEBUG_REG62_TAG14_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_14_MASK | \
+      MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \
+      MH_DEBUG_REG62_TAG15_VA_MASK | \
+      MH_DEBUG_REG62_TAG_valid_q_15_MASK)
+
+#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \
+     ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \
+      (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \
+      (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \
+      (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \
+      (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT))
+
+#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \
+     ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT)
+#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT)
+#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \
+     mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int                                : 2;
+     } mh_debug_reg62_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg62_t {
+          unsigned int                                : 2;
+          unsigned int tag_valid_q_15                 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE;
+          unsigned int tag15_va                       : MH_DEBUG_REG62_TAG15_VA_SIZE;
+          unsigned int always_zero                    : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE;
+          unsigned int tag_valid_q_14                 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE;
+          unsigned int tag14_va                       : MH_DEBUG_REG62_TAG14_VA_SIZE;
+     } mh_debug_reg62_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg62_t f;
+} mh_debug_reg62_u;
+
+
+/*
+ * MH_DEBUG_REG63 struct
+ */
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0
+
+#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff
+
+#define MH_DEBUG_REG63_MASK \
+     (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK)
+
+#define MH_DEBUG_REG63(mh_dbg_default) \
+     ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT))
+
+#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \
+     ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \
+     mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_debug_reg63_t {
+          unsigned int mh_dbg_default                 : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE;
+     } mh_debug_reg63_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_debug_reg63_t f;
+} mh_debug_reg63_u;
+
+
+/*
+ * MH_MMU_CONFIG struct
+ */
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SIZE  1
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1
+#define MH_MMU_CONFIG_RESERVED1_SIZE   2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2
+
+#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1
+#define MH_MMU_CONFIG_RESERVED1_SHIFT  2
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24
+
+#define MH_MMU_CONFIG_MMU_ENABLE_MASK  0x00000001
+#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002
+#define MH_MMU_CONFIG_RESERVED1_MASK   0x0000000c
+#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030
+#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0
+#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300
+#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00
+#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000
+#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000
+#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000
+#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000
+#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000
+#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000
+#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000
+
+#define MH_MMU_CONFIG_MASK \
+     (MH_MMU_CONFIG_MMU_ENABLE_MASK | \
+      MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \
+      MH_MMU_CONFIG_RESERVED1_MASK | \
+      MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK)
+
+#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \
+     ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \
+      (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \
+      (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \
+      (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \
+      (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \
+      (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \
+      (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \
+      (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT))
+
+#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \
+     ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT)
+#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT)
+#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \
+     mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int                                : 6;
+     } mh_mmu_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_config_t {
+          unsigned int                                : 6;
+          unsigned int pa_w_clnt_behavior             : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int tc_r_clnt_behavior             : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r1_clnt_behavior           : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int vgt_r0_clnt_behavior           : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r4_clnt_behavior            : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r3_clnt_behavior            : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r2_clnt_behavior            : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r1_clnt_behavior            : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_r0_clnt_behavior            : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE;
+          unsigned int cp_w_clnt_behavior             : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int rb_w_clnt_behavior             : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE;
+          unsigned int reserved1                      : MH_MMU_CONFIG_RESERVED1_SIZE;
+          unsigned int split_mode_enable              : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE;
+          unsigned int mmu_enable                     : MH_MMU_CONFIG_MMU_ENABLE_SIZE;
+     } mh_mmu_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_config_t f;
+} mh_mmu_config_u;
+
+
+/*
+ * MH_MMU_VA_RANGE struct
+ */
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12
+#define MH_MMU_VA_RANGE_VA_BASE_SIZE   20
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0
+#define MH_MMU_VA_RANGE_VA_BASE_SHIFT  12
+
+#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff
+#define MH_MMU_VA_RANGE_VA_BASE_MASK   0xfffff000
+
+#define MH_MMU_VA_RANGE_MASK \
+     (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \
+      MH_MMU_VA_RANGE_VA_BASE_MASK)
+
+#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \
+     ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \
+      (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT))
+
+#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \
+     ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT)
+#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \
+     mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+     } mh_mmu_va_range_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_va_range_t {
+          unsigned int va_base                        : MH_MMU_VA_RANGE_VA_BASE_SIZE;
+          unsigned int num_64kb_regions               : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE;
+     } mh_mmu_va_range_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_va_range_t f;
+} mh_mmu_va_range_u;
+
+
+/*
+ * MH_MMU_PT_BASE struct
+ */
+
+#define MH_MMU_PT_BASE_PT_BASE_SIZE    20
+
+#define MH_MMU_PT_BASE_PT_BASE_SHIFT   12
+
+#define MH_MMU_PT_BASE_PT_BASE_MASK    0xfffff000
+
+#define MH_MMU_PT_BASE_MASK \
+     (MH_MMU_PT_BASE_PT_BASE_MASK)
+
+#define MH_MMU_PT_BASE(pt_base) \
+     ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT))
+
+#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \
+     ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \
+     mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int                                : 12;
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+     } mh_mmu_pt_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_pt_base_t {
+          unsigned int pt_base                        : MH_MMU_PT_BASE_PT_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_pt_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_pt_base_t f;
+} mh_mmu_pt_base_u;
+
+
+/*
+ * MH_MMU_PAGE_FAULT struct
+ */
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE  3
+#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1
+#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE  20
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0
+#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2
+#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4
+#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11
+#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12
+
+#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001
+#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002
+#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c
+#define MH_MMU_PAGE_FAULT_AXI_ID_MASK  0x00000070
+#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080
+#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100
+#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200
+#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400
+#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800
+#define MH_MMU_PAGE_FAULT_REQ_VA_MASK  0xfffff000
+
+#define MH_MMU_PAGE_FAULT_MASK \
+     (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \
+      MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \
+      MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \
+      MH_MMU_PAGE_FAULT_AXI_ID_MASK | \
+      MH_MMU_PAGE_FAULT_RESERVED1_MASK | \
+      MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \
+      MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \
+      MH_MMU_PAGE_FAULT_REQ_VA_MASK)
+
+#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \
+     ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \
+      (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \
+      (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \
+      (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \
+      (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \
+      (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \
+      (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \
+      (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \
+      (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT))
+
+#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \
+     ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT)
+#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \
+     mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+     } mh_mmu_page_fault_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_page_fault_t {
+          unsigned int req_va                         : MH_MMU_PAGE_FAULT_REQ_VA_SIZE;
+          unsigned int write_protection_error         : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE;
+          unsigned int read_protection_error          : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE;
+          unsigned int address_out_of_range           : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int mpu_address_out_of_range       : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE;
+          unsigned int reserved1                      : MH_MMU_PAGE_FAULT_RESERVED1_SIZE;
+          unsigned int axi_id                         : MH_MMU_PAGE_FAULT_AXI_ID_SIZE;
+          unsigned int clnt_behavior                  : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE;
+          unsigned int op_type                        : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE;
+          unsigned int page_fault                     : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE;
+     } mh_mmu_page_fault_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_page_fault_t f;
+} mh_mmu_page_fault_u;
+
+
+/*
+ * MH_MMU_TRAN_ERROR struct
+ */
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5
+
+#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0
+
+#define MH_MMU_TRAN_ERROR_MASK \
+     (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK)
+
+#define MH_MMU_TRAN_ERROR(tran_error) \
+     ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT))
+
+#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \
+     ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \
+     mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int                                : 5;
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+     } mh_mmu_tran_error_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_tran_error_t {
+          unsigned int tran_error                     : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE;
+          unsigned int                                : 5;
+     } mh_mmu_tran_error_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_tran_error_t f;
+} mh_mmu_tran_error_u;
+
+
+/*
+ * MH_MMU_INVALIDATE struct
+ */
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1
+
+#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001
+#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002
+
+#define MH_MMU_INVALIDATE_MASK \
+     (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \
+      MH_MMU_INVALIDATE_INVALIDATE_TC_MASK)
+
+#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \
+     ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \
+      (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT))
+
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \
+     ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT)
+#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \
+     mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int                                : 30;
+     } mh_mmu_invalidate_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_invalidate_t {
+          unsigned int                                : 30;
+          unsigned int invalidate_tc                  : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE;
+          unsigned int invalidate_all                 : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE;
+     } mh_mmu_invalidate_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_invalidate_t f;
+} mh_mmu_invalidate_u;
+
+
+/*
+ * MH_MMU_MPU_BASE struct
+ */
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SIZE  20
+
+#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12
+
+#define MH_MMU_MPU_BASE_MPU_BASE_MASK  0xfffff000
+
+#define MH_MMU_MPU_BASE_MASK \
+     (MH_MMU_MPU_BASE_MPU_BASE_MASK)
+
+#define MH_MMU_MPU_BASE(mpu_base) \
+     ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT))
+
+#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \
+     ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \
+     mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int                                : 12;
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+     } mh_mmu_mpu_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_base_t {
+          unsigned int mpu_base                       : MH_MMU_MPU_BASE_MPU_BASE_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_base_t f;
+} mh_mmu_mpu_base_u;
+
+
+/*
+ * MH_MMU_MPU_END struct
+ */
+
+#define MH_MMU_MPU_END_MPU_END_SIZE    20
+
+#define MH_MMU_MPU_END_MPU_END_SHIFT   12
+
+#define MH_MMU_MPU_END_MPU_END_MASK    0xfffff000
+
+#define MH_MMU_MPU_END_MASK \
+     (MH_MMU_MPU_END_MPU_END_MASK)
+
+#define MH_MMU_MPU_END(mpu_end) \
+     ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT))
+
+#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \
+     ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \
+     mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int                                : 12;
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+     } mh_mmu_mpu_end_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _mh_mmu_mpu_end_t {
+          unsigned int mpu_end                        : MH_MMU_MPU_END_MPU_END_SIZE;
+          unsigned int                                : 12;
+     } mh_mmu_mpu_end_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     mh_mmu_mpu_end_t f;
+} mh_mmu_mpu_end_u;
+
+
+#endif
+
+
+#if !defined (_PA_FIDDLE_H)
+#define _PA_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * PA_CL_VPORT_XSCALE struct
+ */
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0
+
+#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_XSCALE_MASK \
+     (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK)
+
+#define PA_CL_VPORT_XSCALE(vport_xscale) \
+     ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT))
+
+#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \
+     ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \
+     pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xscale_t {
+          unsigned int vport_xscale                   : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE;
+     } pa_cl_vport_xscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xscale_t f;
+} pa_cl_vport_xscale_u;
+
+
+/*
+ * PA_CL_VPORT_XOFFSET struct
+ */
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_XOFFSET_MASK \
+     (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK)
+
+#define PA_CL_VPORT_XOFFSET(vport_xoffset) \
+     ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT))
+
+#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \
+     ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \
+     pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_xoffset_t {
+          unsigned int vport_xoffset                  : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE;
+     } pa_cl_vport_xoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_xoffset_t f;
+} pa_cl_vport_xoffset_u;
+
+
+/*
+ * PA_CL_VPORT_YSCALE struct
+ */
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0
+
+#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_YSCALE_MASK \
+     (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK)
+
+#define PA_CL_VPORT_YSCALE(vport_yscale) \
+     ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT))
+
+#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \
+     ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \
+     pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yscale_t {
+          unsigned int vport_yscale                   : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE;
+     } pa_cl_vport_yscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yscale_t f;
+} pa_cl_vport_yscale_u;
+
+
+/*
+ * PA_CL_VPORT_YOFFSET struct
+ */
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_YOFFSET_MASK \
+     (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK)
+
+#define PA_CL_VPORT_YOFFSET(vport_yoffset) \
+     ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT))
+
+#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \
+     ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \
+     pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_yoffset_t {
+          unsigned int vport_yoffset                  : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE;
+     } pa_cl_vport_yoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_yoffset_t f;
+} pa_cl_vport_yoffset_u;
+
+
+/*
+ * PA_CL_VPORT_ZSCALE struct
+ */
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0
+
+#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZSCALE_MASK \
+     (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK)
+
+#define PA_CL_VPORT_ZSCALE(vport_zscale) \
+     ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT))
+
+#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \
+     ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \
+     pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zscale_t {
+          unsigned int vport_zscale                   : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE;
+     } pa_cl_vport_zscale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zscale_t f;
+} pa_cl_vport_zscale_u;
+
+
+/*
+ * PA_CL_VPORT_ZOFFSET struct
+ */
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0
+
+#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff
+
+#define PA_CL_VPORT_ZOFFSET_MASK \
+     (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK)
+
+#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \
+     ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT))
+
+#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \
+     ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \
+     pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vport_zoffset_t {
+          unsigned int vport_zoffset                  : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE;
+     } pa_cl_vport_zoffset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vport_zoffset_t f;
+} pa_cl_vport_zoffset_u;
+
+
+/*
+ * PA_CL_VTE_CNTL struct
+ */
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE  1
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11
+
+#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001
+#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002
+#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004
+#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008
+#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010
+#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020
+#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100
+#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK  0x00000200
+#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400
+#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800
+
+#define PA_CL_VTE_CNTL_MASK \
+     (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \
+      PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \
+      PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \
+      PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \
+      PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK)
+
+#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \
+     ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \
+      (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \
+      (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \
+      (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \
+      (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \
+      (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \
+      (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \
+      (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \
+      (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \
+      (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT))
+
+#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \
+     ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT)
+#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \
+     pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int                                : 2;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int                                : 20;
+     } pa_cl_vte_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_vte_cntl_t {
+          unsigned int                                : 20;
+          unsigned int perfcounter_ref                : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE;
+          unsigned int vtx_w0_fmt                     : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE;
+          unsigned int vtx_z_fmt                      : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE;
+          unsigned int vtx_xy_fmt                     : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE;
+          unsigned int                                : 2;
+          unsigned int vport_z_offset_ena             : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE;
+          unsigned int vport_z_scale_ena              : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE;
+          unsigned int vport_y_offset_ena             : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE;
+          unsigned int vport_y_scale_ena              : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE;
+          unsigned int vport_x_offset_ena             : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE;
+          unsigned int vport_x_scale_ena              : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE;
+     } pa_cl_vte_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_vte_cntl_t f;
+} pa_cl_vte_cntl_u;
+
+
+/*
+ * PA_CL_CLIP_CNTL struct
+ */
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24
+
+#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000
+#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000
+#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000
+#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000
+#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000
+#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000
+#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000
+#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000
+
+#define PA_CL_CLIP_CNTL_MASK \
+     (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \
+      PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \
+      PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \
+      PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \
+      PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \
+      PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \
+      PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK)
+
+#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \
+     ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \
+      (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \
+      (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \
+      (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \
+      (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \
+      (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \
+      (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \
+      (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT))
+
+#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \
+     ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT)
+#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \
+     pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 16;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int                                : 7;
+     } pa_cl_clip_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_clip_cntl_t {
+          unsigned int                                : 7;
+          unsigned int w_nan_retain                   : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE;
+          unsigned int z_nan_retain                   : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE;
+          unsigned int xy_nan_retain                  : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE;
+          unsigned int vtx_kill_or                    : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE;
+          unsigned int dis_clip_err_detect            : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE;
+          unsigned int dx_clip_space_def              : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE;
+          unsigned int boundary_edge_flag_ena         : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int clip_disable                   : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE;
+          unsigned int                                : 16;
+     } pa_cl_clip_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_clip_cntl_t f;
+} pa_cl_clip_cntl_u;
+
+
+/*
+ * PA_CL_GB_VERT_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_CLIP_ADJ_MASK \
+     (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \
+     ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \
+     pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_clip_adj_t f;
+} pa_cl_gb_vert_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_VERT_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_VERT_DISC_ADJ_MASK \
+     (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_VERT_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \
+     ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \
+     pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_vert_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_vert_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_vert_disc_adj_t f;
+} pa_cl_gb_vert_disc_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_CLIP_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \
+     (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \
+     ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \
+     pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_clip_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_clip_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_clip_adj_t f;
+} pa_cl_gb_horz_clip_adj_u;
+
+
+/*
+ * PA_CL_GB_HORZ_DISC_ADJ struct
+ */
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0
+
+#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff
+
+#define PA_CL_GB_HORZ_DISC_ADJ_MASK \
+     (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK)
+
+#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \
+     ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT))
+
+#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \
+     ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \
+     pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_gb_horz_disc_adj_t {
+          unsigned int data_register                  : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE;
+     } pa_cl_gb_horz_disc_adj_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_gb_horz_disc_adj_t f;
+} pa_cl_gb_horz_disc_adj_u;
+
+
+/*
+ * PA_CL_ENHANCE struct
+ */
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1
+#define PA_CL_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_CL_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0
+#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001
+#define PA_CL_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_CL_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_CL_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_CL_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_CL_ENHANCE_MASK \
+     (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE3_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE2_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE1_MASK | \
+      PA_CL_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \
+      (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \
+     ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \
+     pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+          unsigned int                                : 27;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_cl_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_enhance_t {
+          unsigned int eco_spare0                     : PA_CL_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_CL_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_CL_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_CL_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 27;
+          unsigned int clip_vtx_reorder_ena           : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE;
+     } pa_cl_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_enhance_t f;
+} pa_cl_enhance_u;
+
+
+/*
+ * PA_SC_ENHANCE struct
+ */
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE2_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE1_SIZE  1
+#define PA_SC_ENHANCE_ECO_SPARE0_SIZE  1
+
+#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28
+#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29
+#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30
+#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31
+
+#define PA_SC_ENHANCE_ECO_SPARE3_MASK  0x10000000
+#define PA_SC_ENHANCE_ECO_SPARE2_MASK  0x20000000
+#define PA_SC_ENHANCE_ECO_SPARE1_MASK  0x40000000
+#define PA_SC_ENHANCE_ECO_SPARE0_MASK  0x80000000
+
+#define PA_SC_ENHANCE_MASK \
+     (PA_SC_ENHANCE_ECO_SPARE3_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE2_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE1_MASK | \
+      PA_SC_ENHANCE_ECO_SPARE0_MASK)
+
+#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \
+     ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \
+      (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \
+      (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \
+      (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT))
+
+#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \
+     ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT)
+#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \
+     pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int                                : 28;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+     } pa_sc_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_enhance_t {
+          unsigned int eco_spare0                     : PA_SC_ENHANCE_ECO_SPARE0_SIZE;
+          unsigned int eco_spare1                     : PA_SC_ENHANCE_ECO_SPARE1_SIZE;
+          unsigned int eco_spare2                     : PA_SC_ENHANCE_ECO_SPARE2_SIZE;
+          unsigned int eco_spare3                     : PA_SC_ENHANCE_ECO_SPARE3_SIZE;
+          unsigned int                                : 28;
+     } pa_sc_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_enhance_t f;
+} pa_sc_enhance_u;
+
+
+/*
+ * PA_SU_VTX_CNTL struct
+ */
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1
+#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2
+#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0
+#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1
+#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3
+
+#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001
+#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006
+#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038
+
+#define PA_SU_VTX_CNTL_MASK \
+     (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \
+      PA_SU_VTX_CNTL_ROUND_MODE_MASK | \
+      PA_SU_VTX_CNTL_QUANT_MODE_MASK)
+
+#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \
+     ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \
+      (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \
+      (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT))
+
+#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \
+     ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT)
+#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT)
+#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \
+     pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int                                : 26;
+     } pa_su_vtx_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_vtx_cntl_t {
+          unsigned int                                : 26;
+          unsigned int quant_mode                     : PA_SU_VTX_CNTL_QUANT_MODE_SIZE;
+          unsigned int round_mode                     : PA_SU_VTX_CNTL_ROUND_MODE_SIZE;
+          unsigned int pix_center                     : PA_SU_VTX_CNTL_PIX_CENTER_SIZE;
+     } pa_su_vtx_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_vtx_cntl_t f;
+} pa_su_vtx_cntl_u;
+
+
+/*
+ * PA_SU_POINT_SIZE struct
+ */
+
+#define PA_SU_POINT_SIZE_HEIGHT_SIZE   16
+#define PA_SU_POINT_SIZE_WIDTH_SIZE    16
+
+#define PA_SU_POINT_SIZE_HEIGHT_SHIFT  0
+#define PA_SU_POINT_SIZE_WIDTH_SHIFT   16
+
+#define PA_SU_POINT_SIZE_HEIGHT_MASK   0x0000ffff
+#define PA_SU_POINT_SIZE_WIDTH_MASK    0xffff0000
+
+#define PA_SU_POINT_SIZE_MASK \
+     (PA_SU_POINT_SIZE_HEIGHT_MASK | \
+      PA_SU_POINT_SIZE_WIDTH_MASK)
+
+#define PA_SU_POINT_SIZE(height, width) \
+     ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \
+      (width << PA_SU_POINT_SIZE_WIDTH_SHIFT))
+
+#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \
+     ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT)
+#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \
+     pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+     } pa_su_point_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_size_t {
+          unsigned int width                          : PA_SU_POINT_SIZE_WIDTH_SIZE;
+          unsigned int height                         : PA_SU_POINT_SIZE_HEIGHT_SIZE;
+     } pa_su_point_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_size_t f;
+} pa_su_point_size_u;
+
+
+/*
+ * PA_SU_POINT_MINMAX struct
+ */
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0
+#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16
+
+#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff
+#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000
+
+#define PA_SU_POINT_MINMAX_MASK \
+     (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \
+      PA_SU_POINT_MINMAX_MAX_SIZE_MASK)
+
+#define PA_SU_POINT_MINMAX(min_size, max_size) \
+     ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \
+      (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT))
+
+#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \
+     ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT)
+#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \
+     pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_point_minmax_t {
+          unsigned int max_size                       : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE;
+          unsigned int min_size                       : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE;
+     } pa_su_point_minmax_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_point_minmax_t f;
+} pa_su_point_minmax_u;
+
+
+/*
+ * PA_SU_LINE_CNTL struct
+ */
+
+#define PA_SU_LINE_CNTL_WIDTH_SIZE     16
+
+#define PA_SU_LINE_CNTL_WIDTH_SHIFT    0
+
+#define PA_SU_LINE_CNTL_WIDTH_MASK     0x0000ffff
+
+#define PA_SU_LINE_CNTL_MASK \
+     (PA_SU_LINE_CNTL_WIDTH_MASK)
+
+#define PA_SU_LINE_CNTL(width) \
+     ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT))
+
+#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \
+     ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \
+     pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+          unsigned int                                : 16;
+     } pa_su_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_line_cntl_t {
+          unsigned int                                : 16;
+          unsigned int width                          : PA_SU_LINE_CNTL_WIDTH_SIZE;
+     } pa_su_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_line_cntl_t f;
+} pa_su_line_cntl_u;
+
+
+/*
+ * PA_SU_FACE_DATA struct
+ */
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27
+
+#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5
+
+#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0
+
+#define PA_SU_FACE_DATA_MASK \
+     (PA_SU_FACE_DATA_BASE_ADDR_MASK)
+
+#define PA_SU_FACE_DATA(base_addr) \
+     ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT))
+
+#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \
+     ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \
+     pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int                                : 5;
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+     } pa_su_face_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_face_data_t {
+          unsigned int base_addr                      : PA_SU_FACE_DATA_BASE_ADDR_SIZE;
+          unsigned int                                : 5;
+     } pa_su_face_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_face_data_t f;
+} pa_su_face_data_u;
+
+
+/*
+ * PA_SU_SC_MODE_CNTL struct
+ */
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_SIZE   1
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1
+#define PA_SU_SC_MODE_CNTL_FACE_SHIFT  2
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26
+#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT 28
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31
+
+#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001
+#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002
+#define PA_SU_SC_MODE_CNTL_FACE_MASK   0x00000004
+#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018
+#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0
+#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000
+#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000
+#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000
+#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000
+#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000
+#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000
+#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000
+#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000
+#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000
+#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000
+#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK 0x10000000
+#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000
+#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000
+#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000
+
+#define PA_SU_SC_MODE_CNTL_MASK \
+     (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \
+      PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \
+      PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \
+      PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \
+      PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \
+      PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \
+      PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK | \
+      PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \
+      PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK)
+
+#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, clamped_faceness, zero_area_faceness, face_kill_enable, face_write_enable) \
+     ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \
+      (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \
+      (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \
+      (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \
+      (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \
+      (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \
+      (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \
+      (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \
+      (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \
+      (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \
+      (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \
+      (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \
+      (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \
+      (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \
+      (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \
+      (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \
+      (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \
+      (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \
+      (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) | \
+      (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \
+      (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \
+      (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT))
+
+#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_CLAMPED_FACENESS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \
+     ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_CLAMPED_FACENESS(pa_su_sc_mode_cntl_reg, clamped_faceness) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) | (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT)
+#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \
+     pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int clamped_faceness               : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_sc_mode_cntl_t {
+          unsigned int face_write_enable              : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE;
+          unsigned int face_kill_enable               : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE;
+          unsigned int zero_area_faceness             : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE;
+          unsigned int clamped_faceness               : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE;
+          unsigned int                                : 1;
+          unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE;
+          unsigned int wait_rb_idle_all_tri           : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE;
+          unsigned int                                : 1;
+          unsigned int quad_order_enable              : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int multi_prim_ib_ena              : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE;
+          unsigned int persp_corr_dis                 : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE;
+          unsigned int provoking_vtx_last             : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE;
+          unsigned int line_stipple_enable            : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vtx_window_offset_enable       : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE;
+          unsigned int msaa_enable                    : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int poly_offset_para_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE;
+          unsigned int poly_offset_back_enable        : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE;
+          unsigned int poly_offset_front_enable       : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE;
+          unsigned int polymode_back_ptype            : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE;
+          unsigned int polymode_front_ptype           : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE;
+          unsigned int poly_mode                      : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE;
+          unsigned int face                           : PA_SU_SC_MODE_CNTL_FACE_SIZE;
+          unsigned int cull_back                      : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE;
+          unsigned int cull_front                     : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE;
+     } pa_su_sc_mode_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_sc_mode_cntl_t f;
+} pa_su_sc_mode_cntl_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \
+     ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \
+     pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_front_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_scale_t f;
+} pa_su_poly_offset_front_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_FRONT_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \
+     ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \
+     pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_front_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_front_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_front_offset_t f;
+} pa_su_poly_offset_front_offset_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_SCALE struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \
+     (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \
+     ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \
+     ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \
+     pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_scale_t {
+          unsigned int scale                          : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE;
+     } pa_su_poly_offset_back_scale_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_scale_t f;
+} pa_su_poly_offset_back_scale_u;
+
+
+/*
+ * PA_SU_POLY_OFFSET_BACK_OFFSET struct
+ */
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \
+     (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \
+     ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT))
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \
+     ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \
+     pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_poly_offset_back_offset_t {
+          unsigned int offset                         : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE;
+     } pa_su_poly_offset_back_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_poly_offset_back_offset_t f;
+} pa_su_poly_offset_back_offset_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER0_SELECT_MASK \
+     (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \
+     ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \
+     pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_select_t f;
+} pa_su_perfcounter0_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER1_SELECT_MASK \
+     (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \
+     ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \
+     pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_select_t f;
+} pa_su_perfcounter1_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER2_SELECT_MASK \
+     (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \
+     ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \
+     pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_select_t f;
+} pa_su_perfcounter2_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_SELECT struct
+ */
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SU_PERFCOUNTER3_SELECT_MASK \
+     (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \
+     ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \
+     pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_su_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } pa_su_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_select_t f;
+} pa_su_perfcounter3_select_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER0_LOW_MASK \
+     (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \
+     ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \
+     pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_low_t f;
+} pa_su_perfcounter0_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER0_HI_MASK \
+     (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \
+     ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \
+     pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter0_hi_t f;
+} pa_su_perfcounter0_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER1_LOW_MASK \
+     (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \
+     ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \
+     pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_low_t f;
+} pa_su_perfcounter1_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER1_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER1_HI_MASK \
+     (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \
+     ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \
+     pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter1_hi_t f;
+} pa_su_perfcounter1_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER2_LOW_MASK \
+     (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \
+     ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \
+     pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_low_t f;
+} pa_su_perfcounter2_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER2_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER2_HI_MASK \
+     (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \
+     ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \
+     pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter2_hi_t f;
+} pa_su_perfcounter2_hi_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_LOW struct
+ */
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SU_PERFCOUNTER3_LOW_MASK \
+     (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \
+     ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \
+     pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_low_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_low_t f;
+} pa_su_perfcounter3_low_u;
+
+
+/*
+ * PA_SU_PERFCOUNTER3_HI struct
+ */
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SU_PERFCOUNTER3_HI_MASK \
+     (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define PA_SU_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \
+     ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \
+     pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_su_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } pa_su_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_perfcounter3_hi_t f;
+} pa_su_perfcounter3_hi_u;
+
+
+/*
+ * PA_SC_WINDOW_OFFSET struct
+ */
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16
+
+#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff
+#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000
+
+#define PA_SC_WINDOW_OFFSET_MASK \
+     (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \
+      PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK)
+
+#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \
+     ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \
+      (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT))
+
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \
+     ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT)
+#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \
+     pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_window_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_offset_t {
+          unsigned int                                : 1;
+          unsigned int window_y_offset                : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_x_offset                : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE;
+     } pa_sc_window_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_offset_t f;
+} pa_sc_window_offset_u;
+
+
+/*
+ * PA_SC_AA_CONFIG struct
+ */
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13
+
+#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007
+#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000
+
+#define PA_SC_AA_CONFIG_MASK \
+     (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \
+      PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK)
+
+#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \
+     ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \
+      (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT))
+
+#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \
+     ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT)
+#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \
+     pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+          unsigned int                                : 10;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 15;
+     } pa_sc_aa_config_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_config_t {
+          unsigned int                                : 15;
+          unsigned int max_sample_dist                : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE;
+          unsigned int                                : 10;
+          unsigned int msaa_num_samples               : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE;
+     } pa_sc_aa_config_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_config_t f;
+} pa_sc_aa_config_u;
+
+
+/*
+ * PA_SC_AA_MASK struct
+ */
+
+#define PA_SC_AA_MASK_AA_MASK_SIZE     16
+
+#define PA_SC_AA_MASK_AA_MASK_SHIFT    0
+
+#define PA_SC_AA_MASK_AA_MASK_MASK     0x0000ffff
+
+#define PA_SC_AA_MASK_MASK \
+     (PA_SC_AA_MASK_AA_MASK_MASK)
+
+#define PA_SC_AA_MASK(aa_mask) \
+     ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT))
+
+#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \
+     ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \
+     pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_aa_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_aa_mask_t {
+          unsigned int                                : 16;
+          unsigned int aa_mask                        : PA_SC_AA_MASK_AA_MASK_SIZE;
+     } pa_sc_aa_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_aa_mask_t f;
+} pa_sc_aa_mask_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29
+
+#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff
+#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000
+#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000
+
+#define PA_SC_LINE_STIPPLE_MASK \
+     (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \
+      PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \
+      PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \
+      PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK)
+
+#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \
+     ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \
+      (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \
+      (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \
+      (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \
+     ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT)
+#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \
+     pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_line_stipple_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_t {
+          unsigned int                                : 1;
+          unsigned int auto_reset_cntl                : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE;
+          unsigned int pattern_bit_order              : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE;
+          unsigned int                                : 4;
+          unsigned int repeat_count                   : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE;
+          unsigned int line_pattern                   : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE;
+     } pa_sc_line_stipple_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_t f;
+} pa_sc_line_stipple_u;
+
+
+/*
+ * PA_SC_LINE_CNTL struct
+ */
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9
+#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10
+
+#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff
+#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100
+#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200
+#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400
+
+#define PA_SC_LINE_CNTL_MASK \
+     (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \
+      PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \
+      PA_SC_LINE_CNTL_LAST_PIXEL_MASK)
+
+#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \
+     ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \
+      (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \
+      (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \
+      (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT))
+
+#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \
+     ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT)
+#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT)
+#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \
+     pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int                                : 21;
+     } pa_sc_line_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_cntl_t {
+          unsigned int                                : 21;
+          unsigned int last_pixel                     : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE;
+          unsigned int expand_line_width              : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE;
+          unsigned int use_bres_cntl                  : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE;
+          unsigned int bres_cntl                      : PA_SC_LINE_CNTL_BRES_CNTL_SIZE;
+     } pa_sc_line_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_cntl_t f;
+} pa_sc_line_cntl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_TL struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31
+
+#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000
+#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000
+
+#define PA_SC_WINDOW_SCISSOR_TL_MASK \
+     (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \
+      PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \
+     ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \
+      (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \
+     ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \
+     pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_tl_t {
+          unsigned int window_offset_disable          : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int tl_x                           : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_window_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_tl_t f;
+} pa_sc_window_scissor_tl_u;
+
+
+/*
+ * PA_SC_WINDOW_SCISSOR_BR struct
+ */
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff
+#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000
+
+#define PA_SC_WINDOW_SCISSOR_BR_MASK \
+     (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \
+     ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \
+     pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+     } pa_sc_window_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_window_scissor_br_t {
+          unsigned int                                : 2;
+          unsigned int br_y                           : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 2;
+          unsigned int br_x                           : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_window_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_window_scissor_br_t f;
+} pa_sc_window_scissor_br_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_TL struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_TL_MASK \
+     (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \
+     ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \
+      (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \
+     ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \
+     pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_tl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_tl_t {
+          unsigned int                                : 1;
+          unsigned int tl_y                           : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int tl_x                           : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE;
+     } pa_sc_screen_scissor_tl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_tl_t f;
+} pa_sc_screen_scissor_tl_u;
+
+
+/*
+ * PA_SC_SCREEN_SCISSOR_BR struct
+ */
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16
+
+#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff
+#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000
+
+#define PA_SC_SCREEN_SCISSOR_BR_MASK \
+     (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \
+      PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK)
+
+#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \
+     ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \
+      (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT))
+
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \
+     ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT)
+#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \
+     pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+     } pa_sc_screen_scissor_br_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_screen_scissor_br_t {
+          unsigned int                                : 1;
+          unsigned int br_y                           : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE;
+          unsigned int                                : 1;
+          unsigned int br_x                           : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE;
+     } pa_sc_screen_scissor_br_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_screen_scissor_br_t f;
+} pa_sc_screen_scissor_br_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY struct
+ */
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7
+
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001
+#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e
+#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080
+
+#define PA_SC_VIZ_QUERY_MASK \
+     (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \
+      PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \
+      PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK)
+
+#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \
+     ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \
+      (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \
+      (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT))
+
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \
+     ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT)
+#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \
+     pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int                                : 1;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_viz_query_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_t {
+          unsigned int                                : 24;
+          unsigned int kill_pix_post_early_z          : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE;
+          unsigned int                                : 1;
+          unsigned int viz_query_id                   : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE;
+          unsigned int viz_query_ena                  : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE;
+     } pa_sc_viz_query_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_t f;
+} pa_sc_viz_query_u;
+
+
+/*
+ * PA_SC_VIZ_QUERY_STATUS struct
+ */
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0
+
+#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff
+
+#define PA_SC_VIZ_QUERY_STATUS_MASK \
+     (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK)
+
+#define PA_SC_VIZ_QUERY_STATUS(status_bits) \
+     ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT))
+
+#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \
+     ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \
+     pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_viz_query_status_t {
+          unsigned int status_bits                    : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE;
+     } pa_sc_viz_query_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_viz_query_status_t f;
+} pa_sc_viz_query_status_u;
+
+
+/*
+ * PA_SC_LINE_STIPPLE_STATE struct
+ */
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8
+
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f
+#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00
+
+#define PA_SC_LINE_STIPPLE_STATE_MASK \
+     (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \
+      PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK)
+
+#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \
+     ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \
+      (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT))
+
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \
+     ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT)
+#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \
+     pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_line_stipple_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_line_stipple_state_t {
+          unsigned int                                : 16;
+          unsigned int current_count                  : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE;
+          unsigned int                                : 4;
+          unsigned int current_ptr                    : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE;
+     } pa_sc_line_stipple_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_line_stipple_state_t f;
+} pa_sc_line_stipple_state_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_SELECT struct
+ */
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define PA_SC_PERFCOUNTER0_SELECT_MASK \
+     (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \
+     ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \
+     pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } pa_sc_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } pa_sc_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_select_t f;
+} pa_sc_perfcounter0_select_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_LOW struct
+ */
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define PA_SC_PERFCOUNTER0_LOW_MASK \
+     (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \
+     ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \
+     pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_low_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_low_t f;
+} pa_sc_perfcounter0_low_u;
+
+
+/*
+ * PA_SC_PERFCOUNTER0_HI struct
+ */
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define PA_SC_PERFCOUNTER0_HI_MASK \
+     (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define PA_SC_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \
+     ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \
+     pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } pa_sc_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } pa_sc_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_perfcounter0_hi_t f;
+} pa_sc_perfcounter0_hi_u;
+
+
+/*
+ * PA_CL_CNTL_STATUS struct
+ */
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31
+
+#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000
+
+#define PA_CL_CNTL_STATUS_MASK \
+     (PA_CL_CNTL_STATUS_CL_BUSY_MASK)
+
+#define PA_CL_CNTL_STATUS(cl_busy) \
+     ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT))
+
+#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \
+     ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \
+     pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+     } pa_cl_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_cl_cntl_status_t {
+          unsigned int cl_busy                        : PA_CL_CNTL_STATUS_CL_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_cl_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_cl_cntl_status_t f;
+} pa_cl_cntl_status_u;
+
+
+/*
+ * PA_SU_CNTL_STATUS struct
+ */
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31
+
+#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000
+
+#define PA_SU_CNTL_STATUS_MASK \
+     (PA_SU_CNTL_STATUS_SU_BUSY_MASK)
+
+#define PA_SU_CNTL_STATUS(su_busy) \
+     ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT))
+
+#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \
+     ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \
+     pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+     } pa_su_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_cntl_status_t {
+          unsigned int su_busy                        : PA_SU_CNTL_STATUS_SU_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_su_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_cntl_status_t f;
+} pa_su_cntl_status_u;
+
+
+/*
+ * PA_SC_CNTL_STATUS struct
+ */
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31
+
+#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000
+
+#define PA_SC_CNTL_STATUS_MASK \
+     (PA_SC_CNTL_STATUS_SC_BUSY_MASK)
+
+#define PA_SC_CNTL_STATUS(sc_busy) \
+     ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT))
+
+#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \
+     ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \
+     pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int                                : 31;
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+     } pa_sc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_cntl_status_t {
+          unsigned int sc_busy                        : PA_SC_CNTL_STATUS_SC_BUSY_SIZE;
+          unsigned int                                : 31;
+     } pa_sc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_cntl_status_t f;
+} pa_sc_cntl_status_u;
+
+
+/*
+ * PA_SU_DEBUG_CNTL struct
+ */
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0
+
+#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SU_DEBUG_CNTL_MASK \
+     (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK)
+
+#define PA_SU_DEBUG_CNTL(su_debug_indx) \
+     ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT))
+
+#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \
+     ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \
+     pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_su_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int su_debug_indx                  : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE;
+     } pa_su_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_cntl_t f;
+} pa_su_debug_cntl_u;
+
+
+/*
+ * PA_SU_DEBUG_DATA struct
+ */
+
+#define PA_SU_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SU_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SU_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SU_DEBUG_DATA_MASK \
+     (PA_SU_DEBUG_DATA_DATA_MASK)
+
+#define PA_SU_DEBUG_DATA(data) \
+     ((data << PA_SU_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \
+     ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \
+     pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_su_debug_data_t {
+          unsigned int data                           : PA_SU_DEBUG_DATA_DATA_SIZE;
+     } pa_su_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_su_debug_data_t f;
+} pa_su_debug_data_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG00 struct
+ */
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20
+
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001
+#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004
+#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010
+#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040
+#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100
+#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400
+#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000
+#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000
+#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000
+#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000
+#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000
+#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000
+
+#define CLIPPER_DEBUG_REG00_MASK \
+     (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \
+     ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \
+      (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \
+      (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \
+      (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \
+      (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \
+      (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \
+      (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \
+      (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \
+      (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \
+      (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \
+      (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \
+      (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \
+      (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \
+      (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \
+      (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \
+      (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \
+      (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \
+      (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \
+      (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \
+      (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \
+     ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \
+     clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg00_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg00_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_full      : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE;
+          unsigned int ccgen_to_clipcc_fifo_empty     : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE;
+          unsigned int vte_out_orig_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_full    : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE;
+          unsigned int vte_out_clip_fifo_fifo_empty   : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE;
+          unsigned int clipcode_fifo_full             : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE;
+          unsigned int clipcode_fifo_fifo_empty       : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE;
+          unsigned int vgt_to_clips_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE;
+          unsigned int vgt_to_clips_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE;
+          unsigned int vgt_to_clipp_fifo_full         : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE;
+          unsigned int vgt_to_clipp_fifo_empty        : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE;
+          unsigned int clip_to_outsm_fifo_full        : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE;
+          unsigned int clip_to_outsm_fifo_empty       : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE;
+          unsigned int primic_to_clprim_fifo_full     : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE;
+          unsigned int primic_to_clprim_fifo_empty    : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE;
+          unsigned int clip_to_ga_fifo_full           : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE;
+          unsigned int clip_to_ga_fifo_write          : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE;
+          unsigned int clip_ga_bc_fifo_full           : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE;
+          unsigned int clip_ga_bc_fifo_write          : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE;
+     } clipper_debug_reg00_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg00_t f;
+} clipper_debug_reg00_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG01 struct
+ */
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24
+
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000
+#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000
+#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000
+
+#define CLIPPER_DEBUG_REG01_MASK \
+     (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \
+      CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \
+     ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \
+      (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \
+      (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \
+      (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \
+      (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \
+      (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \
+      (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \
+      (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \
+     ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \
+     clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg01_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg01_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE;
+          unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE;
+          unsigned int clip_vert_vte_valid            : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE;
+          unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE;
+          unsigned int clip_to_outsm_null_primitive   : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE;
+          unsigned int clip_to_outsm_clipped_prim     : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE;
+          unsigned int clip_to_outsm_deallocate_slot  : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE;
+          unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE;
+          unsigned int clip_to_outsm_end_of_packet    : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE;
+     } clipper_debug_reg01_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg01_t f;
+} clipper_debug_reg01_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG02 struct
+ */
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31
+
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff
+#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000
+#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000
+#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+
+#define CLIPPER_DEBUG_REG02_MASK \
+     (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \
+      CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK)
+
+#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \
+     ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \
+      (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT))
+
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \
+     ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \
+     clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+     } clipper_debug_reg02_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg02_t {
+          unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE;
+     } clipper_debug_reg02_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg02_t f;
+} clipper_debug_reg02_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG03 struct
+ */
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26
+
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00
+#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000
+#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG03_MASK \
+     (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \
+      CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \
+     ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \
+     ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT)
+#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \
+     clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg03_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg03_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE;
+     } clipper_debug_reg03_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg03_t f;
+} clipper_debug_reg03_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG04 struct
+ */
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8
+
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070
+#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080
+#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00
+
+#define CLIPPER_DEBUG_REG04_MASK \
+     (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \
+      CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \
+     ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \
+     ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT)
+#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \
+     clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg04_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg04_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event   : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE;
+     } clipper_debug_reg04_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg04_t f;
+} clipper_debug_reg04_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG05 struct
+ */
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28
+
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000
+#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000
+#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000
+
+#define CLIPPER_DEBUG_REG05_MASK \
+     (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \
+     ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \
+      (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \
+      (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \
+      (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \
+     ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \
+     clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg05_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg05_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE;
+          unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE;
+          unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE;
+          unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE;
+     } clipper_debug_reg05_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg05_t f;
+} clipper_debug_reg05_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG09 struct
+ */
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18
+#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30
+
+#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001
+#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000
+#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000
+#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000
+
+#define CLIPPER_DEBUG_REG09_MASK \
+     (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \
+      CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \
+      CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK)
+
+#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \
+     ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \
+      (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \
+      (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \
+      (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \
+      (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \
+      (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \
+      (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \
+      (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \
+      (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT))
+
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \
+     ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT)
+#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \
+     clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+     } clipper_debug_reg09_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg09_t {
+          unsigned int clip_priority_seq_indx_load    : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE;
+          unsigned int outsm_clr_fifo_full            : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE;
+          unsigned int outsm_clr_fifo_empty           : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE;
+          unsigned int outsm_clr_rd_clipsm_wait       : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE;
+          unsigned int outsm_clr_rd_orig_vertices     : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE;
+          unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE;
+          unsigned int prim_back_valid                : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE;
+          unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE;
+          unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE;
+          unsigned int clprim_in_back_event           : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE;
+     } clipper_debug_reg09_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg09_t f;
+} clipper_debug_reg09_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG10 struct
+ */
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26
+
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00
+#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000
+#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000
+#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000
+
+#define CLIPPER_DEBUG_REG10_MASK \
+     (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \
+      CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \
+      CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK)
+
+#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \
+     ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \
+      (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \
+      (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \
+      (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \
+      (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \
+      (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \
+      (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \
+      (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT))
+
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \
+     ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT)
+#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \
+     clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+     } clipper_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg10_t {
+          unsigned int clprim_in_back_event_id        : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE;
+          unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE;
+          unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE;
+          unsigned int clprim_in_back_end_of_packet   : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE;
+          unsigned int clprim_in_back_state_var_indx  : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE;
+          unsigned int always_zero3                   : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE;
+          unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE;
+     } clipper_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg10_t f;
+} clipper_debug_reg10_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG11 struct
+ */
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4
+
+#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0
+
+#define CLIPPER_DEBUG_REG11_MASK \
+     (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \
+      CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK)
+
+#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \
+     ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \
+      (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT))
+
+#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \
+     ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT)
+#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \
+     clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+     } clipper_debug_reg11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg11_t {
+          unsigned int always_zero                    : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE;
+          unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE;
+     } clipper_debug_reg11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg11_t f;
+} clipper_debug_reg11_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG12 struct
+ */
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22
+
+#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c
+#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020
+#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800
+#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000
+#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000
+#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000
+#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define CLIPPER_DEBUG_REG12_MASK \
+     (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \
+      CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \
+      CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \
+      CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \
+      CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \
+      CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \
+     ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \
+      (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \
+      (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \
+      (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \
+      (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \
+      (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \
+      (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \
+     ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT)
+#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \
+     clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg12_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE;
+          unsigned int primic_to_clprim_valid         : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE;
+          unsigned int clipcc_vertex_store_indx       : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE;
+          unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE;
+          unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE;
+          unsigned int clip_vertex_fifo_empty         : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE;
+          unsigned int always_zero2                   : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE;
+          unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE;
+     } clipper_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg12_t f;
+} clipper_debug_reg12_u;
+
+
+/*
+ * CLIPPER_DEBUG_REG13 struct
+ */
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19
+#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27
+
+#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f
+#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800
+#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000
+#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000
+#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000
+#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000
+
+#define CLIPPER_DEBUG_REG13_MASK \
+     (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \
+      CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \
+      CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK)
+
+#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \
+     ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \
+      (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \
+      (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \
+      (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \
+      (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \
+      (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \
+      (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT))
+
+#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \
+     ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT)
+#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \
+     clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+     } clipper_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _clipper_debug_reg13_t {
+          unsigned int always_zero0                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE;
+          unsigned int sm0_current_state              : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_0   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE;
+          unsigned int sm0_inv_to_clip_data_valid_1   : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE;
+          unsigned int sm0_vertex_clip_cnt            : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE;
+          unsigned int always_zero1                   : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE;
+          unsigned int sm0_prim_end_state             : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE;
+          unsigned int sm0_clip_vert_cnt              : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE;
+     } clipper_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     clipper_debug_reg13_t f;
+} clipper_debug_reg13_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG0 struct
+ */
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4
+#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3
+#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0
+#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31
+
+#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380
+#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000
+
+#define SXIFCCG_DEBUG_REG0_MASK \
+     (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \
+      SXIFCCG_DEBUG_REG0_position_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG0_point_address_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \
+      SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK)
+
+#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \
+     ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \
+      (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \
+      (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \
+      (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \
+      (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \
+      (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \
+      (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \
+      (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT))
+
+#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \
+     ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT)
+#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \
+     sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg0_t {
+          unsigned int sx_pending_rd_aux_sel          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE;
+          unsigned int sx_pending_rd_aux_inc          : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE;
+          unsigned int sx_pending_rd_pci              : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE;
+          unsigned int sx_pending_rd_req_mask         : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE;
+          unsigned int sx_pending_rd_state_var_indx   : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE;
+          unsigned int point_address                  : SXIFCCG_DEBUG_REG0_point_address_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE;
+          unsigned int position_address               : SXIFCCG_DEBUG_REG0_position_address_SIZE;
+          unsigned int nan_kill_flag                  : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE;
+     } sxifccg_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg0_t f;
+} sxifccg_debug_reg0_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG1 struct
+ */
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4
+#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2
+#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23
+#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25
+
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003
+#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c
+#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780
+#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800
+#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000
+#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000
+#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000
+#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000
+#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000
+
+#define SXIFCCG_DEBUG_REG1_MASK \
+     (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \
+      SXIFCCG_DEBUG_REG1_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \
+      SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \
+      SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG1_aux_sel_MASK | \
+      SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \
+      SXIFCCG_DEBUG_REG1_param_cache_base_MASK)
+
+#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \
+     ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \
+      (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \
+      (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \
+      (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \
+      (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \
+      (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \
+      (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \
+      (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT))
+
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \
+     ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT)
+#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \
+     sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg1_t {
+          unsigned int param_cache_base               : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE;
+          unsigned int pasx_req_cnt                   : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE;
+          unsigned int aux_sel                        : SXIFCCG_DEBUG_REG1_aux_sel_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE;
+          unsigned int statevar_bits_sxpa_aux_vector  : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE;
+          unsigned int sx_receive_indx                : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE;
+          unsigned int sx_pending_advance             : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG1_available_positions_SIZE;
+          unsigned int sx_to_pa_empty                 : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE;
+     } sxifccg_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg1_t f;
+} sxifccg_debug_reg1_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG2 struct
+ */
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1
+#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3
+#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29
+
+#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002
+#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004
+#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8
+#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000
+#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000
+#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000
+#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000
+
+#define SXIFCCG_DEBUG_REG2_MASK \
+     (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_aux_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \
+      SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \
+      SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK)
+
+#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \
+     ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \
+      (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \
+      (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \
+      (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \
+      (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \
+      (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \
+      (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \
+      (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \
+      (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \
+      (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT))
+
+#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \
+     ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \
+     sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg2_t {
+          unsigned int sx_pending_fifo_contents       : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE;
+          unsigned int sx_pending_fifo_full           : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE;
+          unsigned int sx_pending_fifo_empty          : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE;
+          unsigned int req_active_verts_loaded        : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_active_verts      : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE;
+          unsigned int vgt_to_ccgen_state_var_indx    : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE;
+          unsigned int req_active_verts               : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE;
+          unsigned int sx_request_indx                : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE;
+          unsigned int sx_aux                         : SXIFCCG_DEBUG_REG2_sx_aux_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE;
+          unsigned int sx_sent                        : SXIFCCG_DEBUG_REG2_sx_sent_SIZE;
+     } sxifccg_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg2_t f;
+} sxifccg_debug_reg2_u;
+
+
+/*
+ * SXIFCCG_DEBUG_REG3 struct
+ */
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1
+#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4
+#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4
+#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8
+#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22
+
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010
+#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00
+#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000
+#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000
+#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000
+#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000
+#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000
+
+#define SXIFCCG_DEBUG_REG3_MASK \
+     (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \
+      SXIFCCG_DEBUG_REG3_available_positions_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \
+      SXIFCCG_DEBUG_REG3_current_state_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \
+      SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \
+      SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK)
+
+#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \
+     ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \
+      (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \
+      (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \
+      (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \
+      (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \
+      (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \
+      (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \
+      (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \
+      (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \
+      (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \
+      (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \
+      (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \
+      (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT))
+
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \
+     ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT)
+#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \
+     sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sxifccg_debug_reg3_t {
+          unsigned int always_zero0                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE;
+          unsigned int vgt_to_ccgen_fifo_full         : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE;
+          unsigned int vgt_to_ccgen_fifo_empty        : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE;
+          unsigned int sx0_receive_fifo_full          : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE;
+          unsigned int sx0_receive_fifo_empty         : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE;
+          unsigned int always_zero1                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE;
+          unsigned int vertex_fifo_full               : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE;
+          unsigned int vertex_fifo_empty              : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE;
+          unsigned int current_state                  : SXIFCCG_DEBUG_REG3_current_state_SIZE;
+          unsigned int always_zero2                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE;
+          unsigned int available_positions            : SXIFCCG_DEBUG_REG3_available_positions_SIZE;
+          unsigned int always_zero3                   : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE;
+          unsigned int vertex_fifo_entriesavailable   : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE;
+     } sxifccg_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sxifccg_debug_reg3_t f;
+} sxifccg_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG0 struct
+ */
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5
+#define SETUP_DEBUG_REG0_pmode_state_SIZE 6
+#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1
+#define SETUP_DEBUG_REG0_geom_enable_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1
+#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1
+#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1
+#define SETUP_DEBUG_REG0_geom_busy_SIZE 1
+
+#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0
+#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5
+#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11
+#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13
+#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14
+#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15
+#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16
+#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17
+
+#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f
+#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0
+#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800
+#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000
+#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000
+#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000
+#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000
+#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000
+#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000
+
+#define SETUP_DEBUG_REG0_MASK \
+     (SETUP_DEBUG_REG0_su_cntl_state_MASK | \
+      SETUP_DEBUG_REG0_pmode_state_MASK | \
+      SETUP_DEBUG_REG0_ge_stallb_MASK | \
+      SETUP_DEBUG_REG0_geom_enable_MASK | \
+      SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \
+      SETUP_DEBUG_REG0_su_clip_rtr_MASK | \
+      SETUP_DEBUG_REG0_pfifo_busy_MASK | \
+      SETUP_DEBUG_REG0_su_cntl_busy_MASK | \
+      SETUP_DEBUG_REG0_geom_busy_MASK)
+
+#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \
+     ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \
+      (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \
+      (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \
+      (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \
+      (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \
+      (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \
+      (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \
+      (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \
+      (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT))
+
+#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \
+     ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT)
+#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT)
+#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT)
+#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \
+     setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int                                : 14;
+     } setup_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg0_t {
+          unsigned int                                : 14;
+          unsigned int geom_busy                      : SETUP_DEBUG_REG0_geom_busy_SIZE;
+          unsigned int su_cntl_busy                   : SETUP_DEBUG_REG0_su_cntl_busy_SIZE;
+          unsigned int pfifo_busy                     : SETUP_DEBUG_REG0_pfifo_busy_SIZE;
+          unsigned int su_clip_rtr                    : SETUP_DEBUG_REG0_su_clip_rtr_SIZE;
+          unsigned int su_clip_baryc_rtr              : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE;
+          unsigned int geom_enable                    : SETUP_DEBUG_REG0_geom_enable_SIZE;
+          unsigned int ge_stallb                      : SETUP_DEBUG_REG0_ge_stallb_SIZE;
+          unsigned int pmode_state                    : SETUP_DEBUG_REG0_pmode_state_SIZE;
+          unsigned int su_cntl_state                  : SETUP_DEBUG_REG0_su_cntl_state_SIZE;
+     } setup_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg0_t f;
+} setup_debug_reg0_u;
+
+
+/*
+ * SETUP_DEBUG_REG1 struct
+ */
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG1_MASK \
+     (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \
+      SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \
+     ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \
+      (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \
+     ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \
+     setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg1_t {
+          unsigned int                                : 4;
+          unsigned int x_sort0_gated_17_4             : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE;
+          unsigned int y_sort0_gated_17_4             : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE;
+     } setup_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg1_t f;
+} setup_debug_reg1_u;
+
+
+/*
+ * SETUP_DEBUG_REG2 struct
+ */
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG2_MASK \
+     (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \
+      SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \
+     ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \
+      (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \
+     ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \
+     setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg2_t {
+          unsigned int                                : 4;
+          unsigned int x_sort1_gated_17_4             : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE;
+          unsigned int y_sort1_gated_17_4             : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE;
+     } setup_debug_reg2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg2_t f;
+} setup_debug_reg2_u;
+
+
+/*
+ * SETUP_DEBUG_REG3 struct
+ */
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14
+
+#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff
+#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000
+
+#define SETUP_DEBUG_REG3_MASK \
+     (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \
+      SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK)
+
+#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \
+     ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \
+      (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT))
+
+#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \
+     ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT)
+#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \
+     setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int                                : 4;
+     } setup_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg3_t {
+          unsigned int                                : 4;
+          unsigned int x_sort2_gated_17_4             : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE;
+          unsigned int y_sort2_gated_17_4             : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE;
+     } setup_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg3_t f;
+} setup_debug_reg3_u;
+
+
+/*
+ * SETUP_DEBUG_REG4 struct
+ */
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11
+#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1
+#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3
+#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3
+#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2
+#define SETUP_DEBUG_REG4_type_gated_SIZE 3
+#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1
+#define SETUP_DEBUG_REG4_event_gated_SIZE 1
+#define SETUP_DEBUG_REG4_eop_gated_SIZE 1
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0
+#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11
+#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12
+#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13
+#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17
+#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20
+#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21
+#define SETUP_DEBUG_REG4_type_gated_SHIFT 23
+#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26
+#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27
+#define SETUP_DEBUG_REG4_event_gated_SHIFT 28
+#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29
+
+#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800
+#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000
+#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000
+#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000
+#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000
+#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000
+#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000
+#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000
+#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000
+#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000
+#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000
+
+#define SETUP_DEBUG_REG4_MASK \
+     (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \
+      SETUP_DEBUG_REG4_null_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_backfacing_gated_MASK | \
+      SETUP_DEBUG_REG4_st_indx_gated_MASK | \
+      SETUP_DEBUG_REG4_clipped_gated_MASK | \
+      SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \
+      SETUP_DEBUG_REG4_xmajor_gated_MASK | \
+      SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \
+      SETUP_DEBUG_REG4_type_gated_MASK | \
+      SETUP_DEBUG_REG4_fpov_gated_MASK | \
+      SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \
+      SETUP_DEBUG_REG4_event_gated_MASK | \
+      SETUP_DEBUG_REG4_eop_gated_MASK)
+
+#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \
+     ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \
+      (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \
+      (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \
+      (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \
+      (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \
+      (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \
+      (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \
+      (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \
+      (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \
+      (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \
+      (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \
+      (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \
+      (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT))
+
+#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \
+     ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT)
+#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \
+     setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int                                : 2;
+     } setup_debug_reg4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg4_t {
+          unsigned int                                : 2;
+          unsigned int eop_gated                      : SETUP_DEBUG_REG4_eop_gated_SIZE;
+          unsigned int event_gated                    : SETUP_DEBUG_REG4_event_gated_SIZE;
+          unsigned int pmode_prim_gated               : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE;
+          unsigned int fpov_gated                     : SETUP_DEBUG_REG4_fpov_gated_SIZE;
+          unsigned int type_gated                     : SETUP_DEBUG_REG4_type_gated_SIZE;
+          unsigned int diamond_rule_gated             : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE;
+          unsigned int xmajor_gated                   : SETUP_DEBUG_REG4_xmajor_gated_SIZE;
+          unsigned int dealloc_slot_gated             : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE;
+          unsigned int clipped_gated                  : SETUP_DEBUG_REG4_clipped_gated_SIZE;
+          unsigned int st_indx_gated                  : SETUP_DEBUG_REG4_st_indx_gated_SIZE;
+          unsigned int backfacing_gated               : SETUP_DEBUG_REG4_backfacing_gated_SIZE;
+          unsigned int null_prim_gated                : SETUP_DEBUG_REG4_null_prim_gated_SIZE;
+          unsigned int attr_indx_sort0_gated          : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE;
+     } setup_debug_reg4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg4_t f;
+} setup_debug_reg4_u;
+
+
+/*
+ * SETUP_DEBUG_REG5 struct
+ */
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2
+#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22
+#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24
+
+#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff
+#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800
+#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000
+#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000
+
+#define SETUP_DEBUG_REG5_MASK \
+     (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \
+      SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \
+      SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \
+      SETUP_DEBUG_REG5_event_id_gated_MASK)
+
+#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \
+     ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \
+      (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \
+      (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \
+      (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT))
+
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \
+     ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT)
+#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \
+     setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int                                : 3;
+     } setup_debug_reg5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _setup_debug_reg5_t {
+          unsigned int                                : 3;
+          unsigned int event_id_gated                 : SETUP_DEBUG_REG5_event_id_gated_SIZE;
+          unsigned int provoking_vtx_gated            : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE;
+          unsigned int attr_indx_sort1_gated          : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE;
+          unsigned int attr_indx_sort2_gated          : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE;
+     } setup_debug_reg5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     setup_debug_reg5_t f;
+} setup_debug_reg5_u;
+
+
+/*
+ * PA_SC_DEBUG_CNTL struct
+ */
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0
+
+#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f
+
+#define PA_SC_DEBUG_CNTL_MASK \
+     (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK)
+
+#define PA_SC_DEBUG_CNTL(sc_debug_indx) \
+     ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT))
+
+#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \
+     ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \
+     pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } pa_sc_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int sc_debug_indx                  : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE;
+     } pa_sc_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_cntl_t f;
+} pa_sc_debug_cntl_u;
+
+
+/*
+ * PA_SC_DEBUG_DATA struct
+ */
+
+#define PA_SC_DEBUG_DATA_DATA_SIZE     32
+
+#define PA_SC_DEBUG_DATA_DATA_SHIFT    0
+
+#define PA_SC_DEBUG_DATA_DATA_MASK     0xffffffff
+
+#define PA_SC_DEBUG_DATA_MASK \
+     (PA_SC_DEBUG_DATA_DATA_MASK)
+
+#define PA_SC_DEBUG_DATA(data) \
+     ((data << PA_SC_DEBUG_DATA_DATA_SHIFT))
+
+#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \
+     ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \
+     pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _pa_sc_debug_data_t {
+          unsigned int data                           : PA_SC_DEBUG_DATA_DATA_SIZE;
+     } pa_sc_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     pa_sc_debug_data_t f;
+} pa_sc_debug_data_u;
+
+
+/*
+ * SC_DEBUG_0 struct
+ */
+
+#define SC_DEBUG_0_pa_freeze_b1_SIZE   1
+#define SC_DEBUG_0_pa_sc_valid_SIZE    1
+#define SC_DEBUG_0_pa_sc_phase_SIZE    3
+#define SC_DEBUG_0_cntx_cnt_SIZE       7
+#define SC_DEBUG_0_decr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_incr_cntx_cnt_SIZE  1
+#define SC_DEBUG_0_trigger_SIZE        1
+
+#define SC_DEBUG_0_pa_freeze_b1_SHIFT  0
+#define SC_DEBUG_0_pa_sc_valid_SHIFT   1
+#define SC_DEBUG_0_pa_sc_phase_SHIFT   2
+#define SC_DEBUG_0_cntx_cnt_SHIFT      5
+#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12
+#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13
+#define SC_DEBUG_0_trigger_SHIFT       31
+
+#define SC_DEBUG_0_pa_freeze_b1_MASK   0x00000001
+#define SC_DEBUG_0_pa_sc_valid_MASK    0x00000002
+#define SC_DEBUG_0_pa_sc_phase_MASK    0x0000001c
+#define SC_DEBUG_0_cntx_cnt_MASK       0x00000fe0
+#define SC_DEBUG_0_decr_cntx_cnt_MASK  0x00001000
+#define SC_DEBUG_0_incr_cntx_cnt_MASK  0x00002000
+#define SC_DEBUG_0_trigger_MASK        0x80000000
+
+#define SC_DEBUG_0_MASK \
+     (SC_DEBUG_0_pa_freeze_b1_MASK | \
+      SC_DEBUG_0_pa_sc_valid_MASK | \
+      SC_DEBUG_0_pa_sc_phase_MASK | \
+      SC_DEBUG_0_cntx_cnt_MASK | \
+      SC_DEBUG_0_decr_cntx_cnt_MASK | \
+      SC_DEBUG_0_incr_cntx_cnt_MASK | \
+      SC_DEBUG_0_trigger_MASK)
+
+#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \
+     ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \
+      (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \
+      (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \
+      (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \
+      (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \
+      (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \
+      (trigger << SC_DEBUG_0_trigger_SHIFT))
+
+#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_GET_trigger(sc_debug_0) \
+     ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT)
+
+#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT)
+#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT)
+#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT)
+#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \
+     sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int                                : 17;
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+     } sc_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_0_t {
+          unsigned int trigger                        : SC_DEBUG_0_trigger_SIZE;
+          unsigned int                                : 17;
+          unsigned int incr_cntx_cnt                  : SC_DEBUG_0_incr_cntx_cnt_SIZE;
+          unsigned int decr_cntx_cnt                  : SC_DEBUG_0_decr_cntx_cnt_SIZE;
+          unsigned int cntx_cnt                       : SC_DEBUG_0_cntx_cnt_SIZE;
+          unsigned int pa_sc_phase                    : SC_DEBUG_0_pa_sc_phase_SIZE;
+          unsigned int pa_sc_valid                    : SC_DEBUG_0_pa_sc_valid_SIZE;
+          unsigned int pa_freeze_b1                   : SC_DEBUG_0_pa_freeze_b1_SIZE;
+     } sc_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_0_t f;
+} sc_debug_0_u;
+
+
+/*
+ * SC_DEBUG_1 struct
+ */
+
+#define SC_DEBUG_1_em_state_SIZE       3
+#define SC_DEBUG_1_em1_data_ready_SIZE 1
+#define SC_DEBUG_1_em2_data_ready_SIZE 1
+#define SC_DEBUG_1_move_em1_to_em2_SIZE 1
+#define SC_DEBUG_1_ef_data_ready_SIZE  1
+#define SC_DEBUG_1_ef_state_SIZE       2
+#define SC_DEBUG_1_pipe_valid_SIZE     1
+#define SC_DEBUG_1_trigger_SIZE        1
+
+#define SC_DEBUG_1_em_state_SHIFT      0
+#define SC_DEBUG_1_em1_data_ready_SHIFT 3
+#define SC_DEBUG_1_em2_data_ready_SHIFT 4
+#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5
+#define SC_DEBUG_1_ef_data_ready_SHIFT 6
+#define SC_DEBUG_1_ef_state_SHIFT      7
+#define SC_DEBUG_1_pipe_valid_SHIFT    9
+#define SC_DEBUG_1_trigger_SHIFT       31
+
+#define SC_DEBUG_1_em_state_MASK       0x00000007
+#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008
+#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010
+#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020
+#define SC_DEBUG_1_ef_data_ready_MASK  0x00000040
+#define SC_DEBUG_1_ef_state_MASK       0x00000180
+#define SC_DEBUG_1_pipe_valid_MASK     0x00000200
+#define SC_DEBUG_1_trigger_MASK        0x80000000
+
+#define SC_DEBUG_1_MASK \
+     (SC_DEBUG_1_em_state_MASK | \
+      SC_DEBUG_1_em1_data_ready_MASK | \
+      SC_DEBUG_1_em2_data_ready_MASK | \
+      SC_DEBUG_1_move_em1_to_em2_MASK | \
+      SC_DEBUG_1_ef_data_ready_MASK | \
+      SC_DEBUG_1_ef_state_MASK | \
+      SC_DEBUG_1_pipe_valid_MASK | \
+      SC_DEBUG_1_trigger_MASK)
+
+#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \
+     ((em_state << SC_DEBUG_1_em_state_SHIFT) | \
+      (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \
+      (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \
+      (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \
+      (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \
+      (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \
+      (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \
+      (trigger << SC_DEBUG_1_trigger_SHIFT))
+
+#define SC_DEBUG_1_GET_em_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_GET_trigger(sc_debug_1) \
+     ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT)
+
+#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT)
+#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT)
+#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT)
+#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT)
+#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT)
+#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \
+     sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int                                : 21;
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+     } sc_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_1_t {
+          unsigned int trigger                        : SC_DEBUG_1_trigger_SIZE;
+          unsigned int                                : 21;
+          unsigned int pipe_valid                     : SC_DEBUG_1_pipe_valid_SIZE;
+          unsigned int ef_state                       : SC_DEBUG_1_ef_state_SIZE;
+          unsigned int ef_data_ready                  : SC_DEBUG_1_ef_data_ready_SIZE;
+          unsigned int move_em1_to_em2                : SC_DEBUG_1_move_em1_to_em2_SIZE;
+          unsigned int em2_data_ready                 : SC_DEBUG_1_em2_data_ready_SIZE;
+          unsigned int em1_data_ready                 : SC_DEBUG_1_em1_data_ready_SIZE;
+          unsigned int em_state                       : SC_DEBUG_1_em_state_SIZE;
+     } sc_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_1_t f;
+} sc_debug_1_u;
+
+
+/*
+ * SC_DEBUG_2 struct
+ */
+
+#define SC_DEBUG_2_rc_rtr_dly_SIZE     1
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1
+#define SC_DEBUG_2_pipe_freeze_b_SIZE  1
+#define SC_DEBUG_2_prim_rts_SIZE       1
+#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1
+#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1
+#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1
+#define SC_DEBUG_2_stage0_rts_SIZE     1
+#define SC_DEBUG_2_phase_rts_dly_SIZE  1
+#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1
+#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1
+#define SC_DEBUG_2_event_id_s1_SIZE    5
+#define SC_DEBUG_2_event_s1_SIZE       1
+#define SC_DEBUG_2_trigger_SIZE        1
+
+#define SC_DEBUG_2_rc_rtr_dly_SHIFT    0
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1
+#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3
+#define SC_DEBUG_2_prim_rts_SHIFT      4
+#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5
+#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6
+#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7
+#define SC_DEBUG_2_stage0_rts_SHIFT    8
+#define SC_DEBUG_2_phase_rts_dly_SHIFT 9
+#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15
+#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16
+#define SC_DEBUG_2_event_id_s1_SHIFT   17
+#define SC_DEBUG_2_event_s1_SHIFT      22
+#define SC_DEBUG_2_trigger_SHIFT       31
+
+#define SC_DEBUG_2_rc_rtr_dly_MASK     0x00000001
+#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002
+#define SC_DEBUG_2_pipe_freeze_b_MASK  0x00000008
+#define SC_DEBUG_2_prim_rts_MASK       0x00000010
+#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020
+#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040
+#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080
+#define SC_DEBUG_2_stage0_rts_MASK     0x00000100
+#define SC_DEBUG_2_phase_rts_dly_MASK  0x00000200
+#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000
+#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000
+#define SC_DEBUG_2_event_id_s1_MASK    0x003e0000
+#define SC_DEBUG_2_event_s1_MASK       0x00400000
+#define SC_DEBUG_2_trigger_MASK        0x80000000
+
+#define SC_DEBUG_2_MASK \
+     (SC_DEBUG_2_rc_rtr_dly_MASK | \
+      SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \
+      SC_DEBUG_2_pipe_freeze_b_MASK | \
+      SC_DEBUG_2_prim_rts_MASK | \
+      SC_DEBUG_2_next_prim_rts_dly_MASK | \
+      SC_DEBUG_2_next_prim_rtr_dly_MASK | \
+      SC_DEBUG_2_pre_stage1_rts_d1_MASK | \
+      SC_DEBUG_2_stage0_rts_MASK | \
+      SC_DEBUG_2_phase_rts_dly_MASK | \
+      SC_DEBUG_2_end_of_prim_s1_dly_MASK | \
+      SC_DEBUG_2_pass_empty_prim_s1_MASK | \
+      SC_DEBUG_2_event_id_s1_MASK | \
+      SC_DEBUG_2_event_s1_MASK | \
+      SC_DEBUG_2_trigger_MASK)
+
+#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \
+     ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \
+      (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \
+      (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \
+      (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \
+      (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \
+      (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \
+      (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \
+      (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \
+      (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \
+      (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \
+      (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \
+      (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \
+      (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \
+      (trigger << SC_DEBUG_2_trigger_SHIFT))
+
+#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_GET_trigger(sc_debug_2) \
+     ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT)
+
+#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT)
+#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT)
+#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT)
+#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT)
+#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT)
+#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT)
+#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT)
+#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT)
+#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT)
+#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \
+     sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int                                : 1;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int                                : 8;
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+     } sc_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_2_t {
+          unsigned int trigger                        : SC_DEBUG_2_trigger_SIZE;
+          unsigned int                                : 8;
+          unsigned int event_s1                       : SC_DEBUG_2_event_s1_SIZE;
+          unsigned int event_id_s1                    : SC_DEBUG_2_event_id_s1_SIZE;
+          unsigned int pass_empty_prim_s1             : SC_DEBUG_2_pass_empty_prim_s1_SIZE;
+          unsigned int end_of_prim_s1_dly             : SC_DEBUG_2_end_of_prim_s1_dly_SIZE;
+          unsigned int                                : 5;
+          unsigned int phase_rts_dly                  : SC_DEBUG_2_phase_rts_dly_SIZE;
+          unsigned int stage0_rts                     : SC_DEBUG_2_stage0_rts_SIZE;
+          unsigned int pre_stage1_rts_d1              : SC_DEBUG_2_pre_stage1_rts_d1_SIZE;
+          unsigned int next_prim_rtr_dly              : SC_DEBUG_2_next_prim_rtr_dly_SIZE;
+          unsigned int next_prim_rts_dly              : SC_DEBUG_2_next_prim_rts_dly_SIZE;
+          unsigned int prim_rts                       : SC_DEBUG_2_prim_rts_SIZE;
+          unsigned int pipe_freeze_b                  : SC_DEBUG_2_pipe_freeze_b_SIZE;
+          unsigned int                                : 1;
+          unsigned int qmask_ff_alm_full_d1           : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE;
+          unsigned int rc_rtr_dly                     : SC_DEBUG_2_rc_rtr_dly_SIZE;
+     } sc_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_2_t f;
+} sc_debug_2_u;
+
+
+/*
+ * SC_DEBUG_3 struct
+ */
+
+#define SC_DEBUG_3_x_curr_s1_SIZE      11
+#define SC_DEBUG_3_y_curr_s1_SIZE      11
+#define SC_DEBUG_3_trigger_SIZE        1
+
+#define SC_DEBUG_3_x_curr_s1_SHIFT     0
+#define SC_DEBUG_3_y_curr_s1_SHIFT     11
+#define SC_DEBUG_3_trigger_SHIFT       31
+
+#define SC_DEBUG_3_x_curr_s1_MASK      0x000007ff
+#define SC_DEBUG_3_y_curr_s1_MASK      0x003ff800
+#define SC_DEBUG_3_trigger_MASK        0x80000000
+
+#define SC_DEBUG_3_MASK \
+     (SC_DEBUG_3_x_curr_s1_MASK | \
+      SC_DEBUG_3_y_curr_s1_MASK | \
+      SC_DEBUG_3_trigger_MASK)
+
+#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \
+     ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \
+      (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \
+      (trigger << SC_DEBUG_3_trigger_SHIFT))
+
+#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_GET_trigger(sc_debug_3) \
+     ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT)
+
+#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT)
+#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \
+     sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int                                : 9;
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+     } sc_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_3_t {
+          unsigned int trigger                        : SC_DEBUG_3_trigger_SIZE;
+          unsigned int                                : 9;
+          unsigned int y_curr_s1                      : SC_DEBUG_3_y_curr_s1_SIZE;
+          unsigned int x_curr_s1                      : SC_DEBUG_3_x_curr_s1_SIZE;
+     } sc_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_3_t f;
+} sc_debug_3_u;
+
+
+/*
+ * SC_DEBUG_4 struct
+ */
+
+#define SC_DEBUG_4_y_end_s1_SIZE       14
+#define SC_DEBUG_4_y_start_s1_SIZE     14
+#define SC_DEBUG_4_y_dir_s1_SIZE       1
+#define SC_DEBUG_4_trigger_SIZE        1
+
+#define SC_DEBUG_4_y_end_s1_SHIFT      0
+#define SC_DEBUG_4_y_start_s1_SHIFT    14
+#define SC_DEBUG_4_y_dir_s1_SHIFT      28
+#define SC_DEBUG_4_trigger_SHIFT       31
+
+#define SC_DEBUG_4_y_end_s1_MASK       0x00003fff
+#define SC_DEBUG_4_y_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_4_y_dir_s1_MASK       0x10000000
+#define SC_DEBUG_4_trigger_MASK        0x80000000
+
+#define SC_DEBUG_4_MASK \
+     (SC_DEBUG_4_y_end_s1_MASK | \
+      SC_DEBUG_4_y_start_s1_MASK | \
+      SC_DEBUG_4_y_dir_s1_MASK | \
+      SC_DEBUG_4_trigger_MASK)
+
+#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \
+     ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \
+      (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \
+      (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_4_trigger_SHIFT))
+
+#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_GET_trigger(sc_debug_4) \
+     ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT)
+
+#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT)
+#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT)
+#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \
+     sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+     } sc_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_4_t {
+          unsigned int trigger                        : SC_DEBUG_4_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int y_dir_s1                       : SC_DEBUG_4_y_dir_s1_SIZE;
+          unsigned int y_start_s1                     : SC_DEBUG_4_y_start_s1_SIZE;
+          unsigned int y_end_s1                       : SC_DEBUG_4_y_end_s1_SIZE;
+     } sc_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_4_t f;
+} sc_debug_4_u;
+
+
+/*
+ * SC_DEBUG_5 struct
+ */
+
+#define SC_DEBUG_5_x_end_s1_SIZE       14
+#define SC_DEBUG_5_x_start_s1_SIZE     14
+#define SC_DEBUG_5_x_dir_s1_SIZE       1
+#define SC_DEBUG_5_trigger_SIZE        1
+
+#define SC_DEBUG_5_x_end_s1_SHIFT      0
+#define SC_DEBUG_5_x_start_s1_SHIFT    14
+#define SC_DEBUG_5_x_dir_s1_SHIFT      28
+#define SC_DEBUG_5_trigger_SHIFT       31
+
+#define SC_DEBUG_5_x_end_s1_MASK       0x00003fff
+#define SC_DEBUG_5_x_start_s1_MASK     0x0fffc000
+#define SC_DEBUG_5_x_dir_s1_MASK       0x10000000
+#define SC_DEBUG_5_trigger_MASK        0x80000000
+
+#define SC_DEBUG_5_MASK \
+     (SC_DEBUG_5_x_end_s1_MASK | \
+      SC_DEBUG_5_x_start_s1_MASK | \
+      SC_DEBUG_5_x_dir_s1_MASK | \
+      SC_DEBUG_5_trigger_MASK)
+
+#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \
+     ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \
+      (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \
+      (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \
+      (trigger << SC_DEBUG_5_trigger_SHIFT))
+
+#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_GET_trigger(sc_debug_5) \
+     ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT)
+
+#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT)
+#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT)
+#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \
+     sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int                                : 2;
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+     } sc_debug_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_5_t {
+          unsigned int trigger                        : SC_DEBUG_5_trigger_SIZE;
+          unsigned int                                : 2;
+          unsigned int x_dir_s1                       : SC_DEBUG_5_x_dir_s1_SIZE;
+          unsigned int x_start_s1                     : SC_DEBUG_5_x_start_s1_SIZE;
+          unsigned int x_end_s1                       : SC_DEBUG_5_x_end_s1_SIZE;
+     } sc_debug_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_5_t f;
+} sc_debug_5_u;
+
+
+/*
+ * SC_DEBUG_6 struct
+ */
+
+#define SC_DEBUG_6_z_ff_empty_SIZE     1
+#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1
+#define SC_DEBUG_6_xy_ff_empty_SIZE    1
+#define SC_DEBUG_6_event_flag_SIZE     1
+#define SC_DEBUG_6_z_mask_needed_SIZE  1
+#define SC_DEBUG_6_state_SIZE          3
+#define SC_DEBUG_6_state_delayed_SIZE  3
+#define SC_DEBUG_6_data_valid_SIZE     1
+#define SC_DEBUG_6_data_valid_d_SIZE   1
+#define SC_DEBUG_6_tilex_delayed_SIZE  9
+#define SC_DEBUG_6_tiley_delayed_SIZE  9
+#define SC_DEBUG_6_trigger_SIZE        1
+
+#define SC_DEBUG_6_z_ff_empty_SHIFT    0
+#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1
+#define SC_DEBUG_6_xy_ff_empty_SHIFT   2
+#define SC_DEBUG_6_event_flag_SHIFT    3
+#define SC_DEBUG_6_z_mask_needed_SHIFT 4
+#define SC_DEBUG_6_state_SHIFT         5
+#define SC_DEBUG_6_state_delayed_SHIFT 8
+#define SC_DEBUG_6_data_valid_SHIFT    11
+#define SC_DEBUG_6_data_valid_d_SHIFT  12
+#define SC_DEBUG_6_tilex_delayed_SHIFT 13
+#define SC_DEBUG_6_tiley_delayed_SHIFT 22
+#define SC_DEBUG_6_trigger_SHIFT       31
+
+#define SC_DEBUG_6_z_ff_empty_MASK     0x00000001
+#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002
+#define SC_DEBUG_6_xy_ff_empty_MASK    0x00000004
+#define SC_DEBUG_6_event_flag_MASK     0x00000008
+#define SC_DEBUG_6_z_mask_needed_MASK  0x00000010
+#define SC_DEBUG_6_state_MASK          0x000000e0
+#define SC_DEBUG_6_state_delayed_MASK  0x00000700
+#define SC_DEBUG_6_data_valid_MASK     0x00000800
+#define SC_DEBUG_6_data_valid_d_MASK   0x00001000
+#define SC_DEBUG_6_tilex_delayed_MASK  0x003fe000
+#define SC_DEBUG_6_tiley_delayed_MASK  0x7fc00000
+#define SC_DEBUG_6_trigger_MASK        0x80000000
+
+#define SC_DEBUG_6_MASK \
+     (SC_DEBUG_6_z_ff_empty_MASK | \
+      SC_DEBUG_6_qmcntl_ff_empty_MASK | \
+      SC_DEBUG_6_xy_ff_empty_MASK | \
+      SC_DEBUG_6_event_flag_MASK | \
+      SC_DEBUG_6_z_mask_needed_MASK | \
+      SC_DEBUG_6_state_MASK | \
+      SC_DEBUG_6_state_delayed_MASK | \
+      SC_DEBUG_6_data_valid_MASK | \
+      SC_DEBUG_6_data_valid_d_MASK | \
+      SC_DEBUG_6_tilex_delayed_MASK | \
+      SC_DEBUG_6_tiley_delayed_MASK | \
+      SC_DEBUG_6_trigger_MASK)
+
+#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \
+     ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \
+      (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \
+      (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \
+      (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \
+      (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \
+      (state << SC_DEBUG_6_state_SHIFT) | \
+      (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \
+      (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \
+      (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \
+      (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \
+      (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \
+      (trigger << SC_DEBUG_6_trigger_SHIFT))
+
+#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_GET_state(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_GET_trigger(sc_debug_6) \
+     ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT)
+
+#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT)
+#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT)
+#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT)
+#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT)
+#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT)
+#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT)
+#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT)
+#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT)
+#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT)
+#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \
+     sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+     } sc_debug_6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_6_t {
+          unsigned int trigger                        : SC_DEBUG_6_trigger_SIZE;
+          unsigned int tiley_delayed                  : SC_DEBUG_6_tiley_delayed_SIZE;
+          unsigned int tilex_delayed                  : SC_DEBUG_6_tilex_delayed_SIZE;
+          unsigned int data_valid_d                   : SC_DEBUG_6_data_valid_d_SIZE;
+          unsigned int data_valid                     : SC_DEBUG_6_data_valid_SIZE;
+          unsigned int state_delayed                  : SC_DEBUG_6_state_delayed_SIZE;
+          unsigned int state                          : SC_DEBUG_6_state_SIZE;
+          unsigned int z_mask_needed                  : SC_DEBUG_6_z_mask_needed_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_6_event_flag_SIZE;
+          unsigned int xy_ff_empty                    : SC_DEBUG_6_xy_ff_empty_SIZE;
+          unsigned int qmcntl_ff_empty                : SC_DEBUG_6_qmcntl_ff_empty_SIZE;
+          unsigned int z_ff_empty                     : SC_DEBUG_6_z_ff_empty_SIZE;
+     } sc_debug_6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_6_t f;
+} sc_debug_6_u;
+
+
+/*
+ * SC_DEBUG_7 struct
+ */
+
+#define SC_DEBUG_7_event_flag_SIZE     1
+#define SC_DEBUG_7_deallocate_SIZE     3
+#define SC_DEBUG_7_fposition_SIZE      1
+#define SC_DEBUG_7_sr_prim_we_SIZE     1
+#define SC_DEBUG_7_last_tile_SIZE      1
+#define SC_DEBUG_7_tile_ff_we_SIZE     1
+#define SC_DEBUG_7_qs_data_valid_SIZE  1
+#define SC_DEBUG_7_qs_q0_y_SIZE        2
+#define SC_DEBUG_7_qs_q0_x_SIZE        2
+#define SC_DEBUG_7_qs_q0_valid_SIZE    1
+#define SC_DEBUG_7_prim_ff_we_SIZE     1
+#define SC_DEBUG_7_tile_ff_re_SIZE     1
+#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_7_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_tile_SIZE 1
+#define SC_DEBUG_7_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_7_new_prim_SIZE       1
+#define SC_DEBUG_7_load_new_tile_data_SIZE 1
+#define SC_DEBUG_7_state_SIZE          2
+#define SC_DEBUG_7_fifos_ready_SIZE    1
+#define SC_DEBUG_7_trigger_SIZE        1
+
+#define SC_DEBUG_7_event_flag_SHIFT    0
+#define SC_DEBUG_7_deallocate_SHIFT    1
+#define SC_DEBUG_7_fposition_SHIFT     4
+#define SC_DEBUG_7_sr_prim_we_SHIFT    5
+#define SC_DEBUG_7_last_tile_SHIFT     6
+#define SC_DEBUG_7_tile_ff_we_SHIFT    7
+#define SC_DEBUG_7_qs_data_valid_SHIFT 8
+#define SC_DEBUG_7_qs_q0_y_SHIFT       9
+#define SC_DEBUG_7_qs_q0_x_SHIFT       11
+#define SC_DEBUG_7_qs_q0_valid_SHIFT   13
+#define SC_DEBUG_7_prim_ff_we_SHIFT    14
+#define SC_DEBUG_7_tile_ff_re_SHIFT    15
+#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16
+#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17
+#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18
+#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19
+#define SC_DEBUG_7_new_prim_SHIFT      20
+#define SC_DEBUG_7_load_new_tile_data_SHIFT 21
+#define SC_DEBUG_7_state_SHIFT         22
+#define SC_DEBUG_7_fifos_ready_SHIFT   24
+#define SC_DEBUG_7_trigger_SHIFT       31
+
+#define SC_DEBUG_7_event_flag_MASK     0x00000001
+#define SC_DEBUG_7_deallocate_MASK     0x0000000e
+#define SC_DEBUG_7_fposition_MASK      0x00000010
+#define SC_DEBUG_7_sr_prim_we_MASK     0x00000020
+#define SC_DEBUG_7_last_tile_MASK      0x00000040
+#define SC_DEBUG_7_tile_ff_we_MASK     0x00000080
+#define SC_DEBUG_7_qs_data_valid_MASK  0x00000100
+#define SC_DEBUG_7_qs_q0_y_MASK        0x00000600
+#define SC_DEBUG_7_qs_q0_x_MASK        0x00001800
+#define SC_DEBUG_7_qs_q0_valid_MASK    0x00002000
+#define SC_DEBUG_7_prim_ff_we_MASK     0x00004000
+#define SC_DEBUG_7_tile_ff_re_MASK     0x00008000
+#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000
+#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000
+#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000
+#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000
+#define SC_DEBUG_7_new_prim_MASK       0x00100000
+#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000
+#define SC_DEBUG_7_state_MASK          0x00c00000
+#define SC_DEBUG_7_fifos_ready_MASK    0x01000000
+#define SC_DEBUG_7_trigger_MASK        0x80000000
+
+#define SC_DEBUG_7_MASK \
+     (SC_DEBUG_7_event_flag_MASK | \
+      SC_DEBUG_7_deallocate_MASK | \
+      SC_DEBUG_7_fposition_MASK | \
+      SC_DEBUG_7_sr_prim_we_MASK | \
+      SC_DEBUG_7_last_tile_MASK | \
+      SC_DEBUG_7_tile_ff_we_MASK | \
+      SC_DEBUG_7_qs_data_valid_MASK | \
+      SC_DEBUG_7_qs_q0_y_MASK | \
+      SC_DEBUG_7_qs_q0_x_MASK | \
+      SC_DEBUG_7_qs_q0_valid_MASK | \
+      SC_DEBUG_7_prim_ff_we_MASK | \
+      SC_DEBUG_7_tile_ff_re_MASK | \
+      SC_DEBUG_7_fw_prim_data_valid_MASK | \
+      SC_DEBUG_7_last_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_tile_MASK | \
+      SC_DEBUG_7_first_quad_of_prim_MASK | \
+      SC_DEBUG_7_new_prim_MASK | \
+      SC_DEBUG_7_load_new_tile_data_MASK | \
+      SC_DEBUG_7_state_MASK | \
+      SC_DEBUG_7_fifos_ready_MASK | \
+      SC_DEBUG_7_trigger_MASK)
+
+#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \
+     ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \
+      (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \
+      (fposition << SC_DEBUG_7_fposition_SHIFT) | \
+      (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \
+      (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \
+      (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \
+      (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \
+      (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \
+      (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \
+      (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \
+      (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \
+      (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \
+      (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \
+      (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \
+      (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \
+      (state << SC_DEBUG_7_state_SHIFT) | \
+      (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \
+      (trigger << SC_DEBUG_7_trigger_SHIFT))
+
+#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_GET_fposition(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_GET_state(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_GET_trigger(sc_debug_7) \
+     ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT)
+
+#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT)
+#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT)
+#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT)
+#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT)
+#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT)
+#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT)
+#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT)
+#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT)
+#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT)
+#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT)
+#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT)
+#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT)
+#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT)
+#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \
+     sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int                                : 6;
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+     } sc_debug_7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_7_t {
+          unsigned int trigger                        : SC_DEBUG_7_trigger_SIZE;
+          unsigned int                                : 6;
+          unsigned int fifos_ready                    : SC_DEBUG_7_fifos_ready_SIZE;
+          unsigned int state                          : SC_DEBUG_7_state_SIZE;
+          unsigned int load_new_tile_data             : SC_DEBUG_7_load_new_tile_data_SIZE;
+          unsigned int new_prim                       : SC_DEBUG_7_new_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_7_first_quad_of_prim_SIZE;
+          unsigned int first_quad_of_tile             : SC_DEBUG_7_first_quad_of_tile_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_7_last_quad_of_tile_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_7_fw_prim_data_valid_SIZE;
+          unsigned int tile_ff_re                     : SC_DEBUG_7_tile_ff_re_SIZE;
+          unsigned int prim_ff_we                     : SC_DEBUG_7_prim_ff_we_SIZE;
+          unsigned int qs_q0_valid                    : SC_DEBUG_7_qs_q0_valid_SIZE;
+          unsigned int qs_q0_x                        : SC_DEBUG_7_qs_q0_x_SIZE;
+          unsigned int qs_q0_y                        : SC_DEBUG_7_qs_q0_y_SIZE;
+          unsigned int qs_data_valid                  : SC_DEBUG_7_qs_data_valid_SIZE;
+          unsigned int tile_ff_we                     : SC_DEBUG_7_tile_ff_we_SIZE;
+          unsigned int last_tile                      : SC_DEBUG_7_last_tile_SIZE;
+          unsigned int sr_prim_we                     : SC_DEBUG_7_sr_prim_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_7_fposition_SIZE;
+          unsigned int deallocate                     : SC_DEBUG_7_deallocate_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_7_event_flag_SIZE;
+     } sc_debug_7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_7_t f;
+} sc_debug_7_u;
+
+
+/*
+ * SC_DEBUG_8 struct
+ */
+
+#define SC_DEBUG_8_sample_last_SIZE    1
+#define SC_DEBUG_8_sample_mask_SIZE    4
+#define SC_DEBUG_8_sample_y_SIZE       2
+#define SC_DEBUG_8_sample_x_SIZE       2
+#define SC_DEBUG_8_sample_send_SIZE    1
+#define SC_DEBUG_8_next_cycle_SIZE     2
+#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1
+#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1
+#define SC_DEBUG_8_num_samples_SIZE    2
+#define SC_DEBUG_8_last_quad_of_tile_SIZE 1
+#define SC_DEBUG_8_last_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_first_quad_of_prim_SIZE 1
+#define SC_DEBUG_8_sample_we_SIZE      1
+#define SC_DEBUG_8_fposition_SIZE      1
+#define SC_DEBUG_8_event_id_SIZE       5
+#define SC_DEBUG_8_event_flag_SIZE     1
+#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1
+#define SC_DEBUG_8_trigger_SIZE        1
+
+#define SC_DEBUG_8_sample_last_SHIFT   0
+#define SC_DEBUG_8_sample_mask_SHIFT   1
+#define SC_DEBUG_8_sample_y_SHIFT      5
+#define SC_DEBUG_8_sample_x_SHIFT      7
+#define SC_DEBUG_8_sample_send_SHIFT   9
+#define SC_DEBUG_8_next_cycle_SHIFT    10
+#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12
+#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13
+#define SC_DEBUG_8_num_samples_SHIFT   14
+#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16
+#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17
+#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18
+#define SC_DEBUG_8_sample_we_SHIFT     19
+#define SC_DEBUG_8_fposition_SHIFT     20
+#define SC_DEBUG_8_event_id_SHIFT      21
+#define SC_DEBUG_8_event_flag_SHIFT    26
+#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27
+#define SC_DEBUG_8_trigger_SHIFT       31
+
+#define SC_DEBUG_8_sample_last_MASK    0x00000001
+#define SC_DEBUG_8_sample_mask_MASK    0x0000001e
+#define SC_DEBUG_8_sample_y_MASK       0x00000060
+#define SC_DEBUG_8_sample_x_MASK       0x00000180
+#define SC_DEBUG_8_sample_send_MASK    0x00000200
+#define SC_DEBUG_8_next_cycle_MASK     0x00000c00
+#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000
+#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000
+#define SC_DEBUG_8_num_samples_MASK    0x0000c000
+#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000
+#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000
+#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000
+#define SC_DEBUG_8_sample_we_MASK      0x00080000
+#define SC_DEBUG_8_fposition_MASK      0x00100000
+#define SC_DEBUG_8_event_id_MASK       0x03e00000
+#define SC_DEBUG_8_event_flag_MASK     0x04000000
+#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000
+#define SC_DEBUG_8_trigger_MASK        0x80000000
+
+#define SC_DEBUG_8_MASK \
+     (SC_DEBUG_8_sample_last_MASK | \
+      SC_DEBUG_8_sample_mask_MASK | \
+      SC_DEBUG_8_sample_y_MASK | \
+      SC_DEBUG_8_sample_x_MASK | \
+      SC_DEBUG_8_sample_send_MASK | \
+      SC_DEBUG_8_next_cycle_MASK | \
+      SC_DEBUG_8_ez_sample_ff_full_MASK | \
+      SC_DEBUG_8_rb_sc_samp_rtr_MASK | \
+      SC_DEBUG_8_num_samples_MASK | \
+      SC_DEBUG_8_last_quad_of_tile_MASK | \
+      SC_DEBUG_8_last_quad_of_prim_MASK | \
+      SC_DEBUG_8_first_quad_of_prim_MASK | \
+      SC_DEBUG_8_sample_we_MASK | \
+      SC_DEBUG_8_fposition_MASK | \
+      SC_DEBUG_8_event_id_MASK | \
+      SC_DEBUG_8_event_flag_MASK | \
+      SC_DEBUG_8_fw_prim_data_valid_MASK | \
+      SC_DEBUG_8_trigger_MASK)
+
+#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \
+     ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \
+      (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \
+      (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \
+      (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \
+      (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \
+      (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \
+      (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \
+      (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \
+      (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \
+      (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \
+      (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \
+      (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \
+      (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \
+      (fposition << SC_DEBUG_8_fposition_SHIFT) | \
+      (event_id << SC_DEBUG_8_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \
+      (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \
+      (trigger << SC_DEBUG_8_trigger_SHIFT))
+
+#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_GET_fposition(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_GET_event_id(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_GET_trigger(sc_debug_8) \
+     ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT)
+
+#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT)
+#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT)
+#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT)
+#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT)
+#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT)
+#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT)
+#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT)
+#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT)
+#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT)
+#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT)
+#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT)
+#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT)
+#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT)
+#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT)
+#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT)
+#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \
+     sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int                                : 3;
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+     } sc_debug_8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_8_t {
+          unsigned int trigger                        : SC_DEBUG_8_trigger_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_prim_data_valid             : SC_DEBUG_8_fw_prim_data_valid_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_8_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_8_event_id_SIZE;
+          unsigned int fposition                      : SC_DEBUG_8_fposition_SIZE;
+          unsigned int sample_we                      : SC_DEBUG_8_sample_we_SIZE;
+          unsigned int first_quad_of_prim             : SC_DEBUG_8_first_quad_of_prim_SIZE;
+          unsigned int last_quad_of_prim              : SC_DEBUG_8_last_quad_of_prim_SIZE;
+          unsigned int last_quad_of_tile              : SC_DEBUG_8_last_quad_of_tile_SIZE;
+          unsigned int num_samples                    : SC_DEBUG_8_num_samples_SIZE;
+          unsigned int rb_sc_samp_rtr                 : SC_DEBUG_8_rb_sc_samp_rtr_SIZE;
+          unsigned int ez_sample_ff_full              : SC_DEBUG_8_ez_sample_ff_full_SIZE;
+          unsigned int next_cycle                     : SC_DEBUG_8_next_cycle_SIZE;
+          unsigned int sample_send                    : SC_DEBUG_8_sample_send_SIZE;
+          unsigned int sample_x                       : SC_DEBUG_8_sample_x_SIZE;
+          unsigned int sample_y                       : SC_DEBUG_8_sample_y_SIZE;
+          unsigned int sample_mask                    : SC_DEBUG_8_sample_mask_SIZE;
+          unsigned int sample_last                    : SC_DEBUG_8_sample_last_SIZE;
+     } sc_debug_8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_8_t f;
+} sc_debug_8_u;
+
+
+/*
+ * SC_DEBUG_9 struct
+ */
+
+#define SC_DEBUG_9_rb_sc_send_SIZE     1
+#define SC_DEBUG_9_rb_sc_ez_mask_SIZE  4
+#define SC_DEBUG_9_fifo_data_ready_SIZE 1
+#define SC_DEBUG_9_early_z_enable_SIZE 1
+#define SC_DEBUG_9_mask_state_SIZE     2
+#define SC_DEBUG_9_next_ez_mask_SIZE   16
+#define SC_DEBUG_9_mask_ready_SIZE     1
+#define SC_DEBUG_9_drop_sample_SIZE    1
+#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_9_trigger_SIZE        1
+
+#define SC_DEBUG_9_rb_sc_send_SHIFT    0
+#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1
+#define SC_DEBUG_9_fifo_data_ready_SHIFT 5
+#define SC_DEBUG_9_early_z_enable_SHIFT 6
+#define SC_DEBUG_9_mask_state_SHIFT    7
+#define SC_DEBUG_9_next_ez_mask_SHIFT  9
+#define SC_DEBUG_9_mask_ready_SHIFT    25
+#define SC_DEBUG_9_drop_sample_SHIFT   26
+#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30
+#define SC_DEBUG_9_trigger_SHIFT       31
+
+#define SC_DEBUG_9_rb_sc_send_MASK     0x00000001
+#define SC_DEBUG_9_rb_sc_ez_mask_MASK  0x0000001e
+#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020
+#define SC_DEBUG_9_early_z_enable_MASK 0x00000040
+#define SC_DEBUG_9_mask_state_MASK     0x00000180
+#define SC_DEBUG_9_next_ez_mask_MASK   0x01fffe00
+#define SC_DEBUG_9_mask_ready_MASK     0x02000000
+#define SC_DEBUG_9_drop_sample_MASK    0x04000000
+#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000
+#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000
+#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000
+#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000
+#define SC_DEBUG_9_trigger_MASK        0x80000000
+
+#define SC_DEBUG_9_MASK \
+     (SC_DEBUG_9_rb_sc_send_MASK | \
+      SC_DEBUG_9_rb_sc_ez_mask_MASK | \
+      SC_DEBUG_9_fifo_data_ready_MASK | \
+      SC_DEBUG_9_early_z_enable_MASK | \
+      SC_DEBUG_9_mask_state_MASK | \
+      SC_DEBUG_9_next_ez_mask_MASK | \
+      SC_DEBUG_9_mask_ready_MASK | \
+      SC_DEBUG_9_drop_sample_MASK | \
+      SC_DEBUG_9_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_9_trigger_MASK)
+
+#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \
+     ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \
+      (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \
+      (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \
+      (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \
+      (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \
+      (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \
+      (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \
+      (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \
+      (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \
+      (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \
+      (trigger << SC_DEBUG_9_trigger_SHIFT))
+
+#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_GET_trigger(sc_debug_9) \
+     ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT)
+
+#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT)
+#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT)
+#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT)
+#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT)
+#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT)
+#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT)
+#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \
+     sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+     } sc_debug_9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_9_t {
+          unsigned int trigger                        : SC_DEBUG_9_trigger_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE;
+          unsigned int fetch_new_ez_sample_mask       : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE;
+          unsigned int fetch_new_sample_data          : SC_DEBUG_9_fetch_new_sample_data_SIZE;
+          unsigned int drop_sample                    : SC_DEBUG_9_drop_sample_SIZE;
+          unsigned int mask_ready                     : SC_DEBUG_9_mask_ready_SIZE;
+          unsigned int next_ez_mask                   : SC_DEBUG_9_next_ez_mask_SIZE;
+          unsigned int mask_state                     : SC_DEBUG_9_mask_state_SIZE;
+          unsigned int early_z_enable                 : SC_DEBUG_9_early_z_enable_SIZE;
+          unsigned int fifo_data_ready                : SC_DEBUG_9_fifo_data_ready_SIZE;
+          unsigned int rb_sc_ez_mask                  : SC_DEBUG_9_rb_sc_ez_mask_SIZE;
+          unsigned int rb_sc_send                     : SC_DEBUG_9_rb_sc_send_SIZE;
+     } sc_debug_9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_9_t f;
+} sc_debug_9_u;
+
+
+/*
+ * SC_DEBUG_10 struct
+ */
+
+#define SC_DEBUG_10_combined_sample_mask_SIZE 16
+#define SC_DEBUG_10_trigger_SIZE       1
+
+#define SC_DEBUG_10_combined_sample_mask_SHIFT 0
+#define SC_DEBUG_10_trigger_SHIFT      31
+
+#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff
+#define SC_DEBUG_10_trigger_MASK       0x80000000
+
+#define SC_DEBUG_10_MASK \
+     (SC_DEBUG_10_combined_sample_mask_MASK | \
+      SC_DEBUG_10_trigger_MASK)
+
+#define SC_DEBUG_10(combined_sample_mask, trigger) \
+     ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \
+      (trigger << SC_DEBUG_10_trigger_SHIFT))
+
+#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_GET_trigger(sc_debug_10) \
+     ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT)
+
+#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT)
+#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \
+     sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+          unsigned int                                : 15;
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+     } sc_debug_10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_10_t {
+          unsigned int trigger                        : SC_DEBUG_10_trigger_SIZE;
+          unsigned int                                : 15;
+          unsigned int combined_sample_mask           : SC_DEBUG_10_combined_sample_mask_SIZE;
+     } sc_debug_10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_10_t f;
+} sc_debug_10_u;
+
+
+/*
+ * SC_DEBUG_11 struct
+ */
+
+#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1
+#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1
+#define SC_DEBUG_11_iterator_input_fz_SIZE 1
+#define SC_DEBUG_11_packer_send_quads_SIZE 1
+#define SC_DEBUG_11_packer_send_cmd_SIZE 1
+#define SC_DEBUG_11_packer_send_event_SIZE 1
+#define SC_DEBUG_11_next_state_SIZE    3
+#define SC_DEBUG_11_state_SIZE         3
+#define SC_DEBUG_11_stall_SIZE         1
+#define SC_DEBUG_11_trigger_SIZE       1
+
+#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1
+#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3
+#define SC_DEBUG_11_iterator_input_fz_SHIFT 4
+#define SC_DEBUG_11_packer_send_quads_SHIFT 5
+#define SC_DEBUG_11_packer_send_cmd_SHIFT 6
+#define SC_DEBUG_11_packer_send_event_SHIFT 7
+#define SC_DEBUG_11_next_state_SHIFT   8
+#define SC_DEBUG_11_state_SHIFT        11
+#define SC_DEBUG_11_stall_SHIFT        14
+#define SC_DEBUG_11_trigger_SHIFT      31
+
+#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001
+#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002
+#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004
+#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008
+#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010
+#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020
+#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040
+#define SC_DEBUG_11_packer_send_event_MASK 0x00000080
+#define SC_DEBUG_11_next_state_MASK    0x00000700
+#define SC_DEBUG_11_state_MASK         0x00003800
+#define SC_DEBUG_11_stall_MASK         0x00004000
+#define SC_DEBUG_11_trigger_MASK       0x80000000
+
+#define SC_DEBUG_11_MASK \
+     (SC_DEBUG_11_ez_sample_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \
+      SC_DEBUG_11_ez_prim_data_ready_MASK | \
+      SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \
+      SC_DEBUG_11_iterator_input_fz_MASK | \
+      SC_DEBUG_11_packer_send_quads_MASK | \
+      SC_DEBUG_11_packer_send_cmd_MASK | \
+      SC_DEBUG_11_packer_send_event_MASK | \
+      SC_DEBUG_11_next_state_MASK | \
+      SC_DEBUG_11_state_MASK | \
+      SC_DEBUG_11_stall_MASK | \
+      SC_DEBUG_11_trigger_MASK)
+
+#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \
+     ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \
+      (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \
+      (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \
+      (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \
+      (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \
+      (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \
+      (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \
+      (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \
+      (next_state << SC_DEBUG_11_next_state_SHIFT) | \
+      (state << SC_DEBUG_11_state_SHIFT) | \
+      (stall << SC_DEBUG_11_stall_SHIFT) | \
+      (trigger << SC_DEBUG_11_trigger_SHIFT))
+
+#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_GET_next_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_GET_state(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_GET_stall(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_GET_trigger(sc_debug_11) \
+     ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT)
+
+#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT)
+#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT)
+#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT)
+#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT)
+#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT)
+#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT)
+#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT)
+#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT)
+#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \
+     sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int                                : 16;
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+     } sc_debug_11_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_11_t {
+          unsigned int trigger                        : SC_DEBUG_11_trigger_SIZE;
+          unsigned int                                : 16;
+          unsigned int stall                          : SC_DEBUG_11_stall_SIZE;
+          unsigned int state                          : SC_DEBUG_11_state_SIZE;
+          unsigned int next_state                     : SC_DEBUG_11_next_state_SIZE;
+          unsigned int packer_send_event              : SC_DEBUG_11_packer_send_event_SIZE;
+          unsigned int packer_send_cmd                : SC_DEBUG_11_packer_send_cmd_SIZE;
+          unsigned int packer_send_quads              : SC_DEBUG_11_packer_send_quads_SIZE;
+          unsigned int iterator_input_fz              : SC_DEBUG_11_iterator_input_fz_SIZE;
+          unsigned int pkr_fetch_new_prim_data        : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE;
+          unsigned int ez_prim_data_ready             : SC_DEBUG_11_ez_prim_data_ready_SIZE;
+          unsigned int pkr_fetch_new_sample_data      : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE;
+          unsigned int ez_sample_data_ready           : SC_DEBUG_11_ez_sample_data_ready_SIZE;
+     } sc_debug_11_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_11_t f;
+} sc_debug_11_u;
+
+
+/*
+ * SC_DEBUG_12 struct
+ */
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1
+#define SC_DEBUG_12_event_id_SIZE      5
+#define SC_DEBUG_12_event_flag_SIZE    1
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_full_SIZE 1
+#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1
+#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1
+#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1
+#define SC_DEBUG_12_iter_qdhit0_SIZE   1
+#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1
+#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1
+#define SC_DEBUG_12_iter_phase_out_SIZE 2
+#define SC_DEBUG_12_iter_phase_reg_SIZE 2
+#define SC_DEBUG_12_iterator_SP_valid_SIZE 1
+#define SC_DEBUG_12_eopv_reg_SIZE      1
+#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1
+#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1
+#define SC_DEBUG_12_trigger_SIZE       1
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0
+#define SC_DEBUG_12_event_id_SHIFT     1
+#define SC_DEBUG_12_event_flag_SHIFT   6
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7
+#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8
+#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9
+#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10
+#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11
+#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12
+#define SC_DEBUG_12_iter_qdhit0_SHIFT  13
+#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14
+#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15
+#define SC_DEBUG_12_iter_phase_out_SHIFT 16
+#define SC_DEBUG_12_iter_phase_reg_SHIFT 18
+#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20
+#define SC_DEBUG_12_eopv_reg_SHIFT     21
+#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22
+#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23
+#define SC_DEBUG_12_trigger_SHIFT      31
+
+#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001
+#define SC_DEBUG_12_event_id_MASK      0x0000003e
+#define SC_DEBUG_12_event_flag_MASK    0x00000040
+#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080
+#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100
+#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200
+#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400
+#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800
+#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000
+#define SC_DEBUG_12_iter_qdhit0_MASK   0x00002000
+#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000
+#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000
+#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000
+#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000
+#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000
+#define SC_DEBUG_12_eopv_reg_MASK      0x00200000
+#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000
+#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000
+#define SC_DEBUG_12_trigger_MASK       0x80000000
+
+#define SC_DEBUG_12_MASK \
+     (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \
+      SC_DEBUG_12_event_id_MASK | \
+      SC_DEBUG_12_event_flag_MASK | \
+      SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \
+      SC_DEBUG_12_itercmdfifo_full_MASK | \
+      SC_DEBUG_12_itercmdfifo_empty_MASK | \
+      SC_DEBUG_12_iter_ds_one_clk_command_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \
+      SC_DEBUG_12_iter_ds_end_of_vector_MASK | \
+      SC_DEBUG_12_iter_qdhit0_MASK | \
+      SC_DEBUG_12_bc_use_centers_reg_MASK | \
+      SC_DEBUG_12_bc_output_xy_reg_MASK | \
+      SC_DEBUG_12_iter_phase_out_MASK | \
+      SC_DEBUG_12_iter_phase_reg_MASK | \
+      SC_DEBUG_12_iterator_SP_valid_MASK | \
+      SC_DEBUG_12_eopv_reg_MASK | \
+      SC_DEBUG_12_one_clk_cmd_reg_MASK | \
+      SC_DEBUG_12_iter_dx_end_of_prim_MASK | \
+      SC_DEBUG_12_trigger_MASK)
+
+#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \
+     ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \
+      (event_id << SC_DEBUG_12_event_id_SHIFT) | \
+      (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \
+      (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \
+      (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \
+      (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \
+      (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \
+      (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \
+      (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \
+      (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \
+      (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \
+      (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \
+      (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \
+      (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \
+      (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \
+      (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \
+      (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \
+      (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \
+      (trigger << SC_DEBUG_12_trigger_SHIFT))
+
+#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_GET_event_id(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_GET_trigger(sc_debug_12) \
+     ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT)
+
+#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT)
+#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT)
+#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT)
+#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT)
+#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT)
+#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT)
+#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT)
+#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT)
+#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT)
+#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT)
+#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT)
+#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT)
+#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT)
+#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \
+     sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int                                : 7;
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+     } sc_debug_12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sc_debug_12_t {
+          unsigned int trigger                        : SC_DEBUG_12_trigger_SIZE;
+          unsigned int                                : 7;
+          unsigned int iter_dx_end_of_prim            : SC_DEBUG_12_iter_dx_end_of_prim_SIZE;
+          unsigned int one_clk_cmd_reg                : SC_DEBUG_12_one_clk_cmd_reg_SIZE;
+          unsigned int eopv_reg                       : SC_DEBUG_12_eopv_reg_SIZE;
+          unsigned int iterator_sp_valid              : SC_DEBUG_12_iterator_SP_valid_SIZE;
+          unsigned int iter_phase_reg                 : SC_DEBUG_12_iter_phase_reg_SIZE;
+          unsigned int iter_phase_out                 : SC_DEBUG_12_iter_phase_out_SIZE;
+          unsigned int bc_output_xy_reg               : SC_DEBUG_12_bc_output_xy_reg_SIZE;
+          unsigned int bc_use_centers_reg             : SC_DEBUG_12_bc_use_centers_reg_SIZE;
+          unsigned int iter_qdhit0                    : SC_DEBUG_12_iter_qdhit0_SIZE;
+          unsigned int iter_ds_end_of_vector          : SC_DEBUG_12_iter_ds_end_of_vector_SIZE;
+          unsigned int iter_ds_end_of_prim0           : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE;
+          unsigned int iter_ds_one_clk_command        : SC_DEBUG_12_iter_ds_one_clk_command_SIZE;
+          unsigned int itercmdfifo_empty              : SC_DEBUG_12_itercmdfifo_empty_SIZE;
+          unsigned int itercmdfifo_full               : SC_DEBUG_12_itercmdfifo_full_SIZE;
+          unsigned int itercmdfifo_busy_nc_dly        : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE;
+          unsigned int event_flag                     : SC_DEBUG_12_event_flag_SIZE;
+          unsigned int event_id                       : SC_DEBUG_12_event_id_SIZE;
+          unsigned int sq_iterator_free_buff          : SC_DEBUG_12_SQ_iterator_free_buff_SIZE;
+     } sc_debug_12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sc_debug_12_t f;
+} sc_debug_12_u;
+
+
+#endif
+
+
+#if !defined (_VGT_FIDDLE_H)
+#define _VGT_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+/*
+ * VGT_OUT_PRIM_TYPE enum
+ */
+
+#define VGT_OUT_POINT                  0x00000000
+#define VGT_OUT_LINE                   0x00000001
+#define VGT_OUT_TRI                    0x00000002
+#define VGT_OUT_RECT_V0                0x00000003
+#define VGT_OUT_RECT_V1                0x00000004
+#define VGT_OUT_RECT_V2                0x00000005
+#define VGT_OUT_RECT_V3                0x00000006
+#define VGT_OUT_RESERVED               0x00000007
+#define VGT_TE_QUAD                    0x00000008
+#define VGT_TE_PRIM_INDEX_LINE         0x00000009
+#define VGT_TE_PRIM_INDEX_TRI          0x0000000a
+#define VGT_TE_PRIM_INDEX_QUAD         0x0000000b
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * GFX_COPY_STATE struct
+ */
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1
+
+#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0
+
+#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+
+#define GFX_COPY_STATE_MASK \
+     (GFX_COPY_STATE_SRC_STATE_ID_MASK)
+
+#define GFX_COPY_STATE(src_state_id) \
+     ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT))
+
+#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \
+     ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \
+     gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 31;
+     } gfx_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _gfx_copy_state_t {
+          unsigned int                                : 31;
+          unsigned int src_state_id                   : GFX_COPY_STATE_SRC_STATE_ID_SIZE;
+     } gfx_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     gfx_copy_state_t f;
+} gfx_copy_state_u;
+
+
+/*
+ * VGT_DRAW_INITIATOR struct
+ */
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1
+#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11
+#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15
+#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16
+
+#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f
+#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0
+#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300
+#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800
+#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000
+#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000
+#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000
+#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000
+#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000
+
+#define VGT_DRAW_INITIATOR_MASK \
+     (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \
+      VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \
+      VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \
+      VGT_DRAW_INITIATOR_NOT_EOP_MASK | \
+      VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \
+      VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \
+      VGT_DRAW_INITIATOR_NUM_INDICES_MASK)
+
+#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \
+     ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \
+      (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \
+      (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \
+      (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \
+      (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \
+      (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \
+      (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \
+      (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \
+      (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT))
+
+#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \
+     ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT)
+#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \
+     vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+     } vgt_draw_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_draw_initiator_t {
+          unsigned int num_indices                    : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE;
+          unsigned int grp_cull_enable                : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE;
+          unsigned int pre_fetch_cull_enable          : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE;
+          unsigned int small_index                    : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE;
+          unsigned int not_eop                        : VGT_DRAW_INITIATOR_NOT_EOP_SIZE;
+          unsigned int index_size                     : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int faceness_cull_select           : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE;
+          unsigned int source_select                  : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE;
+          unsigned int prim_type                      : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE;
+     } vgt_draw_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_draw_initiator_t f;
+} vgt_draw_initiator_u;
+
+
+/*
+ * VGT_EVENT_INITIATOR struct
+ */
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0
+
+#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f
+
+#define VGT_EVENT_INITIATOR_MASK \
+     (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK)
+
+#define VGT_EVENT_INITIATOR(event_type) \
+     ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT))
+
+#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \
+     ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \
+     vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+          unsigned int                                : 26;
+     } vgt_event_initiator_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_event_initiator_t {
+          unsigned int                                : 26;
+          unsigned int event_type                     : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE;
+     } vgt_event_initiator_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_event_initiator_t f;
+} vgt_event_initiator_u;
+
+
+/*
+ * VGT_DMA_BASE struct
+ */
+
+#define VGT_DMA_BASE_BASE_ADDR_SIZE    32
+
+#define VGT_DMA_BASE_BASE_ADDR_SHIFT   0
+
+#define VGT_DMA_BASE_BASE_ADDR_MASK    0xffffffff
+
+#define VGT_DMA_BASE_MASK \
+     (VGT_DMA_BASE_BASE_ADDR_MASK)
+
+#define VGT_DMA_BASE(base_addr) \
+     ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT))
+
+#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \
+     ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \
+     vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_base_t {
+          unsigned int base_addr                      : VGT_DMA_BASE_BASE_ADDR_SIZE;
+     } vgt_dma_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_base_t f;
+} vgt_dma_base_u;
+
+
+/*
+ * VGT_DMA_SIZE struct
+ */
+
+#define VGT_DMA_SIZE_NUM_WORDS_SIZE    24
+#define VGT_DMA_SIZE_SWAP_MODE_SIZE    2
+
+#define VGT_DMA_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_DMA_SIZE_SWAP_MODE_SHIFT   30
+
+#define VGT_DMA_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_DMA_SIZE_SWAP_MODE_MASK    0xc0000000
+
+#define VGT_DMA_SIZE_MASK \
+     (VGT_DMA_SIZE_NUM_WORDS_MASK | \
+      VGT_DMA_SIZE_SWAP_MODE_MASK)
+
+#define VGT_DMA_SIZE(num_words, swap_mode) \
+     ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \
+      (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT))
+
+#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \
+     ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT)
+#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \
+     vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+     } vgt_dma_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_dma_size_t {
+          unsigned int swap_mode                      : VGT_DMA_SIZE_SWAP_MODE_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_DMA_SIZE_NUM_WORDS_SIZE;
+     } vgt_dma_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_dma_size_t f;
+} vgt_dma_size_u;
+
+
+/*
+ * VGT_BIN_BASE struct
+ */
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0
+
+#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff
+
+#define VGT_BIN_BASE_MASK \
+     (VGT_BIN_BASE_BIN_BASE_ADDR_MASK)
+
+#define VGT_BIN_BASE(bin_base_addr) \
+     ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT))
+
+#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \
+     ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \
+     vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_base_t {
+          unsigned int bin_base_addr                  : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE;
+     } vgt_bin_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_base_t f;
+} vgt_bin_base_u;
+
+
+/*
+ * VGT_BIN_SIZE struct
+ */
+
+#define VGT_BIN_SIZE_NUM_WORDS_SIZE    24
+#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1
+#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1
+
+#define VGT_BIN_SIZE_NUM_WORDS_SHIFT   0
+#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30
+#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31
+
+#define VGT_BIN_SIZE_NUM_WORDS_MASK    0x00ffffff
+#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000
+#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000
+
+#define VGT_BIN_SIZE_MASK \
+     (VGT_BIN_SIZE_NUM_WORDS_MASK | \
+      VGT_BIN_SIZE_FACENESS_FETCH_MASK | \
+      VGT_BIN_SIZE_FACENESS_RESET_MASK)
+
+#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \
+     ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \
+      (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \
+      (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT))
+
+#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \
+     ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT)
+#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \
+     vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+          unsigned int                                : 6;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+     } vgt_bin_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_bin_size_t {
+          unsigned int faceness_reset                 : VGT_BIN_SIZE_FACENESS_RESET_SIZE;
+          unsigned int faceness_fetch                 : VGT_BIN_SIZE_FACENESS_FETCH_SIZE;
+          unsigned int                                : 6;
+          unsigned int num_words                      : VGT_BIN_SIZE_NUM_WORDS_SIZE;
+     } vgt_bin_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_bin_size_t f;
+} vgt_bin_size_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MIN struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MIN_MASK \
+     (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \
+     ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \
+     vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_min_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_min_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE;
+     } vgt_current_bin_id_min_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_min_t f;
+} vgt_current_bin_id_min_u;
+
+
+/*
+ * VGT_CURRENT_BIN_ID_MAX struct
+ */
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0
+#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6
+
+#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007
+#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038
+#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0
+
+#define VGT_CURRENT_BIN_ID_MAX_MASK \
+     (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \
+      VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK)
+
+#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \
+     ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \
+      (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \
+      (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT))
+
+#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \
+     ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT)
+#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \
+     vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int                                : 23;
+     } vgt_current_bin_id_max_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_current_bin_id_max_t {
+          unsigned int                                : 23;
+          unsigned int guard_band                     : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE;
+          unsigned int row                            : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE;
+          unsigned int column                         : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE;
+     } vgt_current_bin_id_max_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_current_bin_id_max_t f;
+} vgt_current_bin_id_max_u;
+
+
+/*
+ * VGT_IMMED_DATA struct
+ */
+
+#define VGT_IMMED_DATA_DATA_SIZE       32
+
+#define VGT_IMMED_DATA_DATA_SHIFT      0
+
+#define VGT_IMMED_DATA_DATA_MASK       0xffffffff
+
+#define VGT_IMMED_DATA_MASK \
+     (VGT_IMMED_DATA_DATA_MASK)
+
+#define VGT_IMMED_DATA(data) \
+     ((data << VGT_IMMED_DATA_DATA_SHIFT))
+
+#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \
+     ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT)
+
+#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \
+     vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_immed_data_t {
+          unsigned int data                           : VGT_IMMED_DATA_DATA_SIZE;
+     } vgt_immed_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_immed_data_t f;
+} vgt_immed_data_u;
+
+
+/*
+ * VGT_MAX_VTX_INDX struct
+ */
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0
+
+#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff
+
+#define VGT_MAX_VTX_INDX_MASK \
+     (VGT_MAX_VTX_INDX_MAX_INDX_MASK)
+
+#define VGT_MAX_VTX_INDX(max_indx) \
+     ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT))
+
+#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \
+     ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \
+     vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_max_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_max_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int max_indx                       : VGT_MAX_VTX_INDX_MAX_INDX_SIZE;
+     } vgt_max_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_max_vtx_indx_t f;
+} vgt_max_vtx_indx_u;
+
+
+/*
+ * VGT_MIN_VTX_INDX struct
+ */
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0
+
+#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff
+
+#define VGT_MIN_VTX_INDX_MASK \
+     (VGT_MIN_VTX_INDX_MIN_INDX_MASK)
+
+#define VGT_MIN_VTX_INDX(min_indx) \
+     ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT))
+
+#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \
+     ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \
+     vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_min_vtx_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_min_vtx_indx_t {
+          unsigned int                                : 8;
+          unsigned int min_indx                       : VGT_MIN_VTX_INDX_MIN_INDX_SIZE;
+     } vgt_min_vtx_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_min_vtx_indx_t f;
+} vgt_min_vtx_indx_u;
+
+
+/*
+ * VGT_INDX_OFFSET struct
+ */
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0
+
+#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff
+
+#define VGT_INDX_OFFSET_MASK \
+     (VGT_INDX_OFFSET_INDX_OFFSET_MASK)
+
+#define VGT_INDX_OFFSET(indx_offset) \
+     ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT))
+
+#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \
+     ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \
+     vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+          unsigned int                                : 8;
+     } vgt_indx_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_indx_offset_t {
+          unsigned int                                : 8;
+          unsigned int indx_offset                    : VGT_INDX_OFFSET_INDX_OFFSET_SIZE;
+     } vgt_indx_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_indx_offset_t f;
+} vgt_indx_offset_u;
+
+
+/*
+ * VGT_VERTEX_REUSE_BLOCK_CNTL struct
+ */
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \
+     (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \
+     ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT))
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \
+     ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \
+     vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+          unsigned int                                : 29;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vertex_reuse_block_cntl_t {
+          unsigned int                                : 29;
+          unsigned int vtx_reuse_depth                : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE;
+     } vgt_vertex_reuse_block_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vertex_reuse_block_cntl_t f;
+} vgt_vertex_reuse_block_cntl_u;
+
+
+/*
+ * VGT_OUT_DEALLOC_CNTL struct
+ */
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0
+
+#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003
+
+#define VGT_OUT_DEALLOC_CNTL_MASK \
+     (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK)
+
+#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \
+     ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT))
+
+#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \
+     ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \
+     vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+          unsigned int                                : 30;
+     } vgt_out_dealloc_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_out_dealloc_cntl_t {
+          unsigned int                                : 30;
+          unsigned int dealloc_dist                   : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE;
+     } vgt_out_dealloc_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_out_dealloc_cntl_t f;
+} vgt_out_dealloc_cntl_u;
+
+
+/*
+ * VGT_MULTI_PRIM_IB_RESET_INDX struct
+ */
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \
+     (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \
+     ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT))
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \
+     ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \
+     vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+          unsigned int                                : 8;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_multi_prim_ib_reset_indx_t {
+          unsigned int                                : 8;
+          unsigned int reset_indx                     : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE;
+     } vgt_multi_prim_ib_reset_indx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_multi_prim_ib_reset_indx_t f;
+} vgt_multi_prim_ib_reset_indx_u;
+
+
+/*
+ * VGT_ENHANCE struct
+ */
+
+#define VGT_ENHANCE_MISC_SIZE          16
+
+#define VGT_ENHANCE_MISC_SHIFT         0
+
+#define VGT_ENHANCE_MISC_MASK          0x0000ffff
+
+#define VGT_ENHANCE_MASK \
+     (VGT_ENHANCE_MISC_MASK)
+
+#define VGT_ENHANCE(misc) \
+     ((misc << VGT_ENHANCE_MISC_SHIFT))
+
+#define VGT_ENHANCE_GET_MISC(vgt_enhance) \
+     ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT)
+
+#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \
+     vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+          unsigned int                                : 16;
+     } vgt_enhance_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_enhance_t {
+          unsigned int                                : 16;
+          unsigned int misc                           : VGT_ENHANCE_MISC_SIZE;
+     } vgt_enhance_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_enhance_t f;
+} vgt_enhance_u;
+
+
+/*
+ * VGT_VTX_VECT_EJECT_REG struct
+ */
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0
+
+#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f
+
+#define VGT_VTX_VECT_EJECT_REG_MASK \
+     (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK)
+
+#define VGT_VTX_VECT_EJECT_REG(prim_count) \
+     ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT))
+
+#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \
+     ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \
+     vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+          unsigned int                                : 27;
+     } vgt_vtx_vect_eject_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_vtx_vect_eject_reg_t {
+          unsigned int                                : 27;
+          unsigned int prim_count                     : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE;
+     } vgt_vtx_vect_eject_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_vtx_vect_eject_reg_t f;
+} vgt_vtx_vect_eject_reg_u;
+
+
+/*
+ * VGT_LAST_COPY_STATE struct
+ */
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16
+
+#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001
+#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000
+
+#define VGT_LAST_COPY_STATE_MASK \
+     (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \
+      VGT_LAST_COPY_STATE_DST_STATE_ID_MASK)
+
+#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \
+     ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \
+      (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT))
+
+#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \
+     ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT)
+#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \
+     vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+     } vgt_last_copy_state_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_last_copy_state_t {
+          unsigned int                                : 15;
+          unsigned int dst_state_id                   : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE;
+          unsigned int                                : 15;
+          unsigned int src_state_id                   : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE;
+     } vgt_last_copy_state_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_last_copy_state_t f;
+} vgt_last_copy_state_u;
+
+
+/*
+ * VGT_DEBUG_CNTL struct
+ */
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0
+
+#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f
+
+#define VGT_DEBUG_CNTL_MASK \
+     (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK)
+
+#define VGT_DEBUG_CNTL(vgt_debug_indx) \
+     ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT))
+
+#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \
+     ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \
+     vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+          unsigned int                                : 27;
+     } vgt_debug_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_cntl_t {
+          unsigned int                                : 27;
+          unsigned int vgt_debug_indx                 : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE;
+     } vgt_debug_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_cntl_t f;
+} vgt_debug_cntl_u;
+
+
+/*
+ * VGT_DEBUG_DATA struct
+ */
+
+#define VGT_DEBUG_DATA_DATA_SIZE       32
+
+#define VGT_DEBUG_DATA_DATA_SHIFT      0
+
+#define VGT_DEBUG_DATA_DATA_MASK       0xffffffff
+
+#define VGT_DEBUG_DATA_MASK \
+     (VGT_DEBUG_DATA_DATA_MASK)
+
+#define VGT_DEBUG_DATA(data) \
+     ((data << VGT_DEBUG_DATA_DATA_SHIFT))
+
+#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \
+     ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT)
+
+#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \
+     vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_data_t {
+          unsigned int data                           : VGT_DEBUG_DATA_DATA_SIZE;
+     } vgt_debug_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_data_t f;
+} vgt_debug_data_u;
+
+
+/*
+ * VGT_CNTL_STATUS struct
+ */
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SIZE  1
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1
+
+#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8
+
+#define VGT_CNTL_STATUS_VGT_BUSY_MASK  0x00000001
+#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002
+#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004
+#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008
+#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010
+#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020
+#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040
+#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080
+#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100
+
+#define VGT_CNTL_STATUS_MASK \
+     (VGT_CNTL_STATUS_VGT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \
+      VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK)
+
+#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \
+     ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \
+      (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \
+      (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \
+      (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \
+      (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \
+      (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \
+      (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \
+      (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \
+      (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT))
+
+#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \
+     ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT)
+#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \
+     vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int                                : 23;
+     } vgt_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_cntl_status_t {
+          unsigned int                                : 23;
+          unsigned int vgt_out_indx_busy              : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE;
+          unsigned int vgt_out_busy                   : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE;
+          unsigned int vgt_pt_busy                    : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE;
+          unsigned int vgt_bin_busy                   : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE;
+          unsigned int vgt_vr_busy                    : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE;
+          unsigned int vgt_grp_busy                   : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE;
+          unsigned int vgt_dma_req_busy               : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE;
+          unsigned int vgt_dma_busy                   : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE;
+          unsigned int vgt_busy                       : VGT_CNTL_STATUS_VGT_BUSY_SIZE;
+     } vgt_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_cntl_status_t f;
+} vgt_cntl_status_u;
+
+
+/*
+ * VGT_DEBUG_REG0 struct
+ */
+
+#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1
+#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_out_busy_SIZE   1
+#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1
+#define VGT_DEBUG_REG0_grp_busy_SIZE   1
+#define VGT_DEBUG_REG0_dma_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1
+#define VGT_DEBUG_REG0_rbiu_busy_SIZE  1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1
+#define VGT_DEBUG_REG0_vgt_busy_SIZE   1
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1
+
+#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0
+#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1
+#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2
+#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3
+#define VGT_DEBUG_REG0_out_busy_SHIFT  4
+#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5
+#define VGT_DEBUG_REG0_grp_busy_SHIFT  6
+#define VGT_DEBUG_REG0_dma_busy_SHIFT  7
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8
+#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11
+#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12
+#define VGT_DEBUG_REG0_vgt_busy_SHIFT  13
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16
+
+#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001
+#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002
+#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004
+#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008
+#define VGT_DEBUG_REG0_out_busy_MASK   0x00000010
+#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020
+#define VGT_DEBUG_REG0_grp_busy_MASK   0x00000040
+#define VGT_DEBUG_REG0_dma_busy_MASK   0x00000080
+#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100
+#define VGT_DEBUG_REG0_rbiu_busy_MASK  0x00000200
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400
+#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800
+#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000
+#define VGT_DEBUG_REG0_vgt_busy_MASK   0x00002000
+#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000
+#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000
+#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000
+
+#define VGT_DEBUG_REG0_MASK \
+     (VGT_DEBUG_REG0_te_grp_busy_MASK | \
+      VGT_DEBUG_REG0_pt_grp_busy_MASK | \
+      VGT_DEBUG_REG0_vr_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_out_busy_MASK | \
+      VGT_DEBUG_REG0_grp_backend_busy_MASK | \
+      VGT_DEBUG_REG0_grp_busy_MASK | \
+      VGT_DEBUG_REG0_dma_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \
+      VGT_DEBUG_REG0_rbiu_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_extended_MASK | \
+      VGT_DEBUG_REG0_vgt_busy_MASK | \
+      VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \
+      VGT_DEBUG_REG0_VGT_RBBM_busy_MASK)
+
+#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \
+     ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \
+      (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \
+      (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \
+      (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \
+      (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \
+      (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \
+      (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \
+      (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \
+      (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \
+      (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \
+      (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \
+      (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \
+      (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \
+      (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \
+      (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \
+      (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \
+      (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT))
+
+#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \
+     ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT)
+#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT)
+#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \
+     vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int                                : 15;
+     } vgt_debug_reg0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg0_t {
+          unsigned int                                : 15;
+          unsigned int vgt_rbbm_busy                  : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE;
+          unsigned int vgt_rbbm_no_dma_busy           : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE;
+          unsigned int rbbm_skid_fifo_busy_out        : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE;
+          unsigned int vgt_busy                       : VGT_DEBUG_REG0_vgt_busy_SIZE;
+          unsigned int vgt_busy_extended              : VGT_DEBUG_REG0_vgt_busy_extended_SIZE;
+          unsigned int vgt_no_dma_busy                : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE;
+          unsigned int vgt_no_dma_busy_extended       : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE;
+          unsigned int rbiu_busy                      : VGT_DEBUG_REG0_rbiu_busy_SIZE;
+          unsigned int rbiu_dma_request_busy          : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE;
+          unsigned int dma_busy                       : VGT_DEBUG_REG0_dma_busy_SIZE;
+          unsigned int grp_busy                       : VGT_DEBUG_REG0_grp_busy_SIZE;
+          unsigned int grp_backend_busy               : VGT_DEBUG_REG0_grp_backend_busy_SIZE;
+          unsigned int out_busy                       : VGT_DEBUG_REG0_out_busy_SIZE;
+          unsigned int dma_request_busy               : VGT_DEBUG_REG0_dma_request_busy_SIZE;
+          unsigned int vr_grp_busy                    : VGT_DEBUG_REG0_vr_grp_busy_SIZE;
+          unsigned int pt_grp_busy                    : VGT_DEBUG_REG0_pt_grp_busy_SIZE;
+          unsigned int te_grp_busy                    : VGT_DEBUG_REG0_te_grp_busy_SIZE;
+     } vgt_debug_reg0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg0_t f;
+} vgt_debug_reg0_u;
+
+
+/*
+ * VGT_DEBUG_REG1 struct
+ */
+
+#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1
+#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1
+#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1
+#define VGT_DEBUG_REG1_te_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1
+#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1
+#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1
+#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1
+#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1
+#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1
+
+#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0
+#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1
+#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2
+#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3
+#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4
+#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5
+#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6
+#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7
+#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8
+#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9
+#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10
+#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11
+#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12
+#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13
+#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14
+#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15
+#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16
+#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19
+#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20
+#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28
+#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30
+
+#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001
+#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002
+#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004
+#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008
+#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010
+#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020
+#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040
+#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080
+#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100
+#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200
+#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400
+#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800
+#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000
+#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000
+#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000
+#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000
+#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000
+#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000
+#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000
+#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000
+#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000
+#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000
+#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000
+#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000
+#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000
+#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000
+#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000
+#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000
+
+#define VGT_DEBUG_REG1_MASK \
+     (VGT_DEBUG_REG1_out_te_data_read_MASK | \
+      VGT_DEBUG_REG1_te_out_data_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_prim_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_pt_data_read_MASK | \
+      VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_prim_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \
+      VGT_DEBUG_REG1_out_vr_indx_read_MASK | \
+      VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \
+      VGT_DEBUG_REG1_te_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_te_valid_MASK | \
+      VGT_DEBUG_REG1_pt_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_pt_valid_MASK | \
+      VGT_DEBUG_REG1_vr_grp_read_MASK | \
+      VGT_DEBUG_REG1_grp_vr_valid_MASK | \
+      VGT_DEBUG_REG1_grp_dma_read_MASK | \
+      VGT_DEBUG_REG1_dma_grp_valid_MASK | \
+      VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \
+      VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \
+      VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_MH_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \
+      VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \
+      VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \
+      VGT_DEBUG_REG1_VGT_SQ_send_MASK | \
+      VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK)
+
+#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \
+     ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \
+      (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \
+      (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \
+      (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \
+      (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \
+      (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \
+      (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \
+      (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \
+      (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \
+      (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \
+      (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \
+      (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \
+      (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \
+      (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \
+      (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \
+      (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \
+      (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \
+      (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \
+      (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \
+      (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \
+      (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \
+      (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \
+      (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \
+      (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \
+      (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \
+      (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \
+      (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \
+      (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \
+      (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \
+      (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \
+      (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT))
+
+#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \
+     ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT)
+#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT)
+#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT)
+#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT)
+#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \
+     vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg1_t {
+          unsigned int                                : 1;
+          unsigned int mh_vgt_tag_7_q                 : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE;
+          unsigned int vgt_sq_send                    : VGT_DEBUG_REG1_VGT_SQ_send_SIZE;
+          unsigned int sq_vgt_rtr                     : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE;
+          unsigned int vgt_pa_clip_v_send             : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE;
+          unsigned int pa_vgt_clip_v_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE;
+          unsigned int vgt_pa_clip_p_send             : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE;
+          unsigned int pa_vgt_clip_p_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE;
+          unsigned int vgt_pa_clip_s_send             : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE;
+          unsigned int pa_vgt_clip_s_rtr              : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE;
+          unsigned int vgt_mh_send                    : VGT_DEBUG_REG1_VGT_MH_send_SIZE;
+          unsigned int mh_vgt_rtr                     : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE;
+          unsigned int rbiu_grp_di_valid              : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE;
+          unsigned int grp_rbiu_di_read               : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE;
+          unsigned int dma_grp_valid                  : VGT_DEBUG_REG1_dma_grp_valid_SIZE;
+          unsigned int grp_dma_read                   : VGT_DEBUG_REG1_grp_dma_read_SIZE;
+          unsigned int grp_vr_valid                   : VGT_DEBUG_REG1_grp_vr_valid_SIZE;
+          unsigned int vr_grp_read                    : VGT_DEBUG_REG1_vr_grp_read_SIZE;
+          unsigned int grp_pt_valid                   : VGT_DEBUG_REG1_grp_pt_valid_SIZE;
+          unsigned int pt_grp_read                    : VGT_DEBUG_REG1_pt_grp_read_SIZE;
+          unsigned int grp_te_valid                   : VGT_DEBUG_REG1_grp_te_valid_SIZE;
+          unsigned int te_grp_read                    : VGT_DEBUG_REG1_te_grp_read_SIZE;
+          unsigned int vr_out_indx_valid              : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE;
+          unsigned int out_vr_indx_read               : VGT_DEBUG_REG1_out_vr_indx_read_SIZE;
+          unsigned int vr_out_prim_valid              : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE;
+          unsigned int out_vr_prim_read               : VGT_DEBUG_REG1_out_vr_prim_read_SIZE;
+          unsigned int pt_out_indx_valid              : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE;
+          unsigned int out_pt_data_read               : VGT_DEBUG_REG1_out_pt_data_read_SIZE;
+          unsigned int pt_out_prim_valid              : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE;
+          unsigned int out_pt_prim_read               : VGT_DEBUG_REG1_out_pt_prim_read_SIZE;
+          unsigned int te_out_data_valid              : VGT_DEBUG_REG1_te_out_data_valid_SIZE;
+          unsigned int out_te_data_read               : VGT_DEBUG_REG1_out_te_data_read_SIZE;
+     } vgt_debug_reg1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg1_t f;
+} vgt_debug_reg1_u;
+
+
+/*
+ * VGT_DEBUG_REG3 struct
+ */
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1
+
+#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001
+#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002
+
+#define VGT_DEBUG_REG3_MASK \
+     (VGT_DEBUG_REG3_vgt_clk_en_MASK | \
+      VGT_DEBUG_REG3_reg_fifos_clk_en_MASK)
+
+#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \
+     ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \
+      (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT))
+
+#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \
+     ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT)
+#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \
+     vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int                                : 30;
+     } vgt_debug_reg3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg3_t {
+          unsigned int                                : 30;
+          unsigned int reg_fifos_clk_en               : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE;
+          unsigned int vgt_clk_en                     : VGT_DEBUG_REG3_vgt_clk_en_SIZE;
+     } vgt_debug_reg3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg3_t f;
+} vgt_debug_reg3_u;
+
+
+/*
+ * VGT_DEBUG_REG6 struct
+ */
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG6_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG6_extract_vector_SIZE 1
+#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG6_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG6_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG6_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG6_MASK \
+     (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG6_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG6_input_data_valid_MASK | \
+      VGT_DEBUG_REG6_input_data_xfer_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG6_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG6_shifter_first_load_MASK | \
+      VGT_DEBUG_REG6_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG6_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG6_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG6_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG6_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG6_extract_vector_MASK | \
+      VGT_DEBUG_REG6_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG6_destination_rtr_MASK | \
+      VGT_DEBUG_REG6_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \
+     ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT)
+#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \
+     vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg6_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg6_t {
+          unsigned int                                : 3;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG6_grp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG6_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG6_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG6_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG6_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG6_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG6_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG6_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG6_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG6_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG6_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG6_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG6_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG6_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg6_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg6_t f;
+} vgt_debug_reg6_u;
+
+
+/*
+ * VGT_DEBUG_REG7 struct
+ */
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG7_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG7_MASK \
+     (VGT_DEBUG_REG7_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG7_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG7_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG7_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \
+     ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \
+     vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+     } vgt_debug_reg7_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg7_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG7_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG7_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG7_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG7_di_index_counter_q_SIZE;
+     } vgt_debug_reg7_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg7_t f;
+} vgt_debug_reg7_u;
+
+
+/*
+ * VGT_DEBUG_REG8 struct
+ */
+
+#define VGT_DEBUG_REG8_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG8_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG8_MASK \
+     (VGT_DEBUG_REG8_current_source_sel_MASK | \
+      VGT_DEBUG_REG8_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG8_input_data_cnt_MASK | \
+      VGT_DEBUG_REG8_input_data_lsw_MASK | \
+      VGT_DEBUG_REG8_input_data_msw_MASK | \
+      VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \
+     ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg8_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg8_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG8_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG8_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG8_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG8_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG8_current_source_sel_SIZE;
+     } vgt_debug_reg8_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg8_t f;
+} vgt_debug_reg8_u;
+
+
+/*
+ * VGT_DEBUG_REG9 struct
+ */
+
+#define VGT_DEBUG_REG9_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG9_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG9_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG9_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG9_MASK \
+     (VGT_DEBUG_REG9_next_stride_q_MASK | \
+      VGT_DEBUG_REG9_next_stride_d_MASK | \
+      VGT_DEBUG_REG9_current_shift_q_MASK | \
+      VGT_DEBUG_REG9_current_shift_d_MASK | \
+      VGT_DEBUG_REG9_current_stride_q_MASK | \
+      VGT_DEBUG_REG9_current_stride_d_MASK | \
+      VGT_DEBUG_REG9_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \
+     ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \
+     vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg9_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg9_t {
+          unsigned int                                : 1;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG9_grp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG9_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG9_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG9_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG9_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG9_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG9_next_stride_q_SIZE;
+     } vgt_debug_reg9_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg9_t f;
+} vgt_debug_reg9_u;
+
+
+/*
+ * VGT_DEBUG_REG10 struct
+ */
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1
+#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG10_bin_valid_SIZE 1
+#define VGT_DEBUG_REG10_read_block_SIZE 1
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1
+#define VGT_DEBUG_REG10_selected_data_SIZE 8
+#define VGT_DEBUG_REG10_mask_input_data_SIZE 8
+#define VGT_DEBUG_REG10_gap_q_SIZE     1
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1
+#define VGT_DEBUG_REG10_grp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3
+#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4
+#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5
+#define VGT_DEBUG_REG10_bin_valid_SHIFT 6
+#define VGT_DEBUG_REG10_read_block_SHIFT 7
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8
+#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9
+#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10
+#define VGT_DEBUG_REG10_selected_data_SHIFT 11
+#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19
+#define VGT_DEBUG_REG10_gap_q_SHIFT    27
+#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28
+#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29
+#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30
+#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001
+#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002
+#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004
+#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008
+#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010
+#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020
+#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040
+#define VGT_DEBUG_REG10_read_block_MASK 0x00000080
+#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100
+#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200
+#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400
+#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800
+#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000
+#define VGT_DEBUG_REG10_gap_q_MASK     0x08000000
+#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000
+#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000
+#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000
+#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG10_MASK \
+     (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \
+      VGT_DEBUG_REG10_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG10_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG10_bin_valid_MASK | \
+      VGT_DEBUG_REG10_read_block_MASK | \
+      VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \
+      VGT_DEBUG_REG10_last_bit_enable_q_MASK | \
+      VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \
+      VGT_DEBUG_REG10_selected_data_MASK | \
+      VGT_DEBUG_REG10_mask_input_data_MASK | \
+      VGT_DEBUG_REG10_gap_q_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \
+      VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \
+      VGT_DEBUG_REG10_grp_trigger_MASK)
+
+#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \
+     ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \
+      (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \
+      (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \
+      (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \
+      (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \
+      (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \
+      (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \
+      (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \
+      (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \
+      (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \
+      (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \
+      (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \
+      (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \
+      (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \
+      (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \
+      (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \
+     ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT)
+#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT)
+#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT)
+#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT)
+#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT)
+#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \
+     vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+     } vgt_debug_reg10_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg10_t {
+          unsigned int grp_trigger                    : VGT_DEBUG_REG10_grp_trigger_SIZE;
+          unsigned int temp_mini_reset_x              : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE;
+          unsigned int temp_mini_reset_y              : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE;
+          unsigned int temp_mini_reset_z              : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE;
+          unsigned int gap_q                          : VGT_DEBUG_REG10_gap_q_SIZE;
+          unsigned int mask_input_data                : VGT_DEBUG_REG10_mask_input_data_SIZE;
+          unsigned int selected_data                  : VGT_DEBUG_REG10_selected_data_SIZE;
+          unsigned int last_bit_end_di_q              : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE;
+          unsigned int last_bit_enable_q              : VGT_DEBUG_REG10_last_bit_enable_q_SIZE;
+          unsigned int grp_bgrp_last_bit_read         : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE;
+          unsigned int read_block                     : VGT_DEBUG_REG10_read_block_SIZE;
+          unsigned int bin_valid                      : VGT_DEBUG_REG10_bin_valid_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG10_last_decr_of_packet_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG10_di_state_sel_q_SIZE;
+          unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE;
+          unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE;
+          unsigned int temp_derived_di_prim_type_t0   : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE;
+     } vgt_debug_reg10_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg10_t f;
+} vgt_debug_reg10_u;
+
+
+/*
+ * VGT_DEBUG_REG12 struct
+ */
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5
+#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG12_input_data_valid_SIZE 1
+#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1
+#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1
+#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1
+#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1
+#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1
+#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1
+#define VGT_DEBUG_REG12_extract_vector_SIZE 1
+#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1
+#define VGT_DEBUG_REG12_destination_rtr_SIZE 1
+#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0
+#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5
+#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10
+#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14
+#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15
+#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16
+#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18
+#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19
+#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20
+#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22
+#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23
+#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24
+#define VGT_DEBUG_REG12_extract_vector_SHIFT 25
+#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26
+#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27
+#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28
+
+#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f
+#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0
+#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400
+#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000
+#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000
+#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000
+#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000
+#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000
+#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000
+#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000
+#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000
+#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000
+#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000
+#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000
+#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000
+#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000
+#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000
+#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000
+#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000
+
+#define VGT_DEBUG_REG12_MASK \
+     (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \
+      VGT_DEBUG_REG12_right_word_indx_q_MASK | \
+      VGT_DEBUG_REG12_input_data_valid_MASK | \
+      VGT_DEBUG_REG12_input_data_xfer_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \
+      VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \
+      VGT_DEBUG_REG12_space_avail_from_shift_MASK | \
+      VGT_DEBUG_REG12_shifter_first_load_MASK | \
+      VGT_DEBUG_REG12_di_state_sel_q_MASK | \
+      VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \
+      VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \
+      VGT_DEBUG_REG12_di_event_flag_q_MASK | \
+      VGT_DEBUG_REG12_read_draw_initiator_MASK | \
+      VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \
+      VGT_DEBUG_REG12_last_shift_of_packet_MASK | \
+      VGT_DEBUG_REG12_last_decr_of_packet_MASK | \
+      VGT_DEBUG_REG12_extract_vector_MASK | \
+      VGT_DEBUG_REG12_shift_vect_rtr_MASK | \
+      VGT_DEBUG_REG12_destination_rtr_MASK | \
+      VGT_DEBUG_REG12_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \
+     ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \
+      (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \
+      (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \
+      (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \
+      (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \
+      (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \
+      (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \
+      (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \
+      (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \
+      (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \
+      (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \
+      (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \
+      (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \
+      (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \
+      (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \
+      (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \
+      (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \
+      (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \
+      (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \
+      (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \
+     ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT)
+#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT)
+#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT)
+#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT)
+#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT)
+#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT)
+#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT)
+#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \
+     vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int                                : 3;
+     } vgt_debug_reg12_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg12_t {
+          unsigned int                                : 3;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG12_bgrp_trigger_SIZE;
+          unsigned int destination_rtr                : VGT_DEBUG_REG12_destination_rtr_SIZE;
+          unsigned int shift_vect_rtr                 : VGT_DEBUG_REG12_shift_vect_rtr_SIZE;
+          unsigned int extract_vector                 : VGT_DEBUG_REG12_extract_vector_SIZE;
+          unsigned int last_decr_of_packet            : VGT_DEBUG_REG12_last_decr_of_packet_SIZE;
+          unsigned int last_shift_of_packet           : VGT_DEBUG_REG12_last_shift_of_packet_SIZE;
+          unsigned int loading_di_requires_shifter    : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE;
+          unsigned int read_draw_initiator            : VGT_DEBUG_REG12_read_draw_initiator_SIZE;
+          unsigned int di_event_flag_q                : VGT_DEBUG_REG12_di_event_flag_q_SIZE;
+          unsigned int di_first_group_flag_q          : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE;
+          unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE;
+          unsigned int di_state_sel_q                 : VGT_DEBUG_REG12_di_state_sel_q_SIZE;
+          unsigned int shifter_first_load             : VGT_DEBUG_REG12_shifter_first_load_SIZE;
+          unsigned int space_avail_from_shift         : VGT_DEBUG_REG12_space_avail_from_shift_SIZE;
+          unsigned int next_shift_is_vect_1_pre_d     : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE;
+          unsigned int next_shift_is_vect_1_d         : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE;
+          unsigned int next_shift_is_vect_1_q         : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE;
+          unsigned int input_data_xfer                : VGT_DEBUG_REG12_input_data_xfer_SIZE;
+          unsigned int input_data_valid               : VGT_DEBUG_REG12_input_data_valid_SIZE;
+          unsigned int right_word_indx_q              : VGT_DEBUG_REG12_right_word_indx_q_SIZE;
+          unsigned int shifter_byte_count_q           : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE;
+     } vgt_debug_reg12_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg12_t f;
+} vgt_debug_reg12_u;
+
+
+/*
+ * VGT_DEBUG_REG13 struct
+ */
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4
+#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4
+#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6
+#define VGT_DEBUG_REG13_current_source_sel_SIZE 2
+
+#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0
+#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16
+#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20
+#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24
+#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30
+
+#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff
+#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000
+#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000
+#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000
+#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000
+
+#define VGT_DEBUG_REG13_MASK \
+     (VGT_DEBUG_REG13_di_index_counter_q_MASK | \
+      VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \
+      VGT_DEBUG_REG13_shift_amount_extract_MASK | \
+      VGT_DEBUG_REG13_di_prim_type_q_MASK | \
+      VGT_DEBUG_REG13_current_source_sel_MASK)
+
+#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \
+     ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \
+      (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \
+      (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \
+      (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \
+      (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT))
+
+#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \
+     ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT)
+#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT)
+#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \
+     vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+     } vgt_debug_reg13_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg13_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG13_current_source_sel_SIZE;
+          unsigned int di_prim_type_q                 : VGT_DEBUG_REG13_di_prim_type_q_SIZE;
+          unsigned int shift_amount_extract           : VGT_DEBUG_REG13_shift_amount_extract_SIZE;
+          unsigned int shift_amount_no_extract        : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE;
+          unsigned int di_index_counter_q             : VGT_DEBUG_REG13_di_index_counter_q_SIZE;
+     } vgt_debug_reg13_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg13_t f;
+} vgt_debug_reg13_u;
+
+
+/*
+ * VGT_DEBUG_REG14 struct
+ */
+
+#define VGT_DEBUG_REG14_current_source_sel_SIZE 2
+#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5
+#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5
+#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5
+#define VGT_DEBUG_REG14_input_data_msw_SIZE 5
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5
+
+#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0
+#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2
+#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7
+#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12
+#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27
+
+#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003
+#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c
+#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80
+#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000
+#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000
+#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000
+#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000
+
+#define VGT_DEBUG_REG14_MASK \
+     (VGT_DEBUG_REG14_current_source_sel_MASK | \
+      VGT_DEBUG_REG14_left_word_indx_q_MASK | \
+      VGT_DEBUG_REG14_input_data_cnt_MASK | \
+      VGT_DEBUG_REG14_input_data_lsw_MASK | \
+      VGT_DEBUG_REG14_input_data_msw_MASK | \
+      VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \
+      VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK)
+
+#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \
+     ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \
+      (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \
+      (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \
+      (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \
+      (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \
+      (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \
+      (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT))
+
+#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \
+     ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT)
+#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT)
+#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT)
+#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT)
+#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \
+     vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+     } vgt_debug_reg14_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg14_t {
+          unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE;
+          unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE;
+          unsigned int input_data_msw                 : VGT_DEBUG_REG14_input_data_msw_SIZE;
+          unsigned int input_data_lsw                 : VGT_DEBUG_REG14_input_data_lsw_SIZE;
+          unsigned int input_data_cnt                 : VGT_DEBUG_REG14_input_data_cnt_SIZE;
+          unsigned int left_word_indx_q               : VGT_DEBUG_REG14_left_word_indx_q_SIZE;
+          unsigned int current_source_sel             : VGT_DEBUG_REG14_current_source_sel_SIZE;
+     } vgt_debug_reg14_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg14_t f;
+} vgt_debug_reg14_u;
+
+
+/*
+ * VGT_DEBUG_REG15 struct
+ */
+
+#define VGT_DEBUG_REG15_next_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_next_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_q_SIZE 5
+#define VGT_DEBUG_REG15_current_shift_d_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_q_SIZE 5
+#define VGT_DEBUG_REG15_current_stride_d_SIZE 5
+#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0
+#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5
+#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10
+#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15
+#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20
+#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25
+#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30
+
+#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f
+#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0
+#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00
+#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000
+#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000
+#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000
+#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000
+
+#define VGT_DEBUG_REG15_MASK \
+     (VGT_DEBUG_REG15_next_stride_q_MASK | \
+      VGT_DEBUG_REG15_next_stride_d_MASK | \
+      VGT_DEBUG_REG15_current_shift_q_MASK | \
+      VGT_DEBUG_REG15_current_shift_d_MASK | \
+      VGT_DEBUG_REG15_current_stride_q_MASK | \
+      VGT_DEBUG_REG15_current_stride_d_MASK | \
+      VGT_DEBUG_REG15_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \
+     ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \
+      (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \
+      (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \
+      (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \
+      (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \
+      (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \
+     ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT)
+#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT)
+#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \
+     vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int                                : 1;
+     } vgt_debug_reg15_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg15_t {
+          unsigned int                                : 1;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG15_bgrp_trigger_SIZE;
+          unsigned int current_stride_d               : VGT_DEBUG_REG15_current_stride_d_SIZE;
+          unsigned int current_stride_q               : VGT_DEBUG_REG15_current_stride_q_SIZE;
+          unsigned int current_shift_d                : VGT_DEBUG_REG15_current_shift_d_SIZE;
+          unsigned int current_shift_q                : VGT_DEBUG_REG15_current_shift_q_SIZE;
+          unsigned int next_stride_d                  : VGT_DEBUG_REG15_next_stride_d_SIZE;
+          unsigned int next_stride_q                  : VGT_DEBUG_REG15_next_stride_q_SIZE;
+     } vgt_debug_reg15_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg15_t f;
+} vgt_debug_reg15_u;
+
+
+/*
+ * VGT_DEBUG_REG16 struct
+ */
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1
+#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1
+#define VGT_DEBUG_REG16_current_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_q_SIZE 1
+#define VGT_DEBUG_REG16_old_state_en_SIZE 1
+#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1
+#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1
+#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1
+#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9
+#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10
+#define VGT_DEBUG_REG16_current_state_q_SHIFT 11
+#define VGT_DEBUG_REG16_old_state_q_SHIFT 12
+#define VGT_DEBUG_REG16_old_state_en_SHIFT 13
+#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14
+#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15
+#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16
+#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17
+#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30
+#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004
+#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040
+#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080
+#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100
+#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200
+#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400
+#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800
+#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000
+#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000
+#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000
+#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000
+#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000
+#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000
+#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000
+#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000
+#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000
+#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000
+#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000
+#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG16_MASK \
+     (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \
+      VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \
+      VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \
+      VGT_DEBUG_REG16_rst_last_bit_MASK | \
+      VGT_DEBUG_REG16_current_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_q_MASK | \
+      VGT_DEBUG_REG16_old_state_en_MASK | \
+      VGT_DEBUG_REG16_prev_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \
+      VGT_DEBUG_REG16_last_bit_block_q_MASK | \
+      VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \
+      VGT_DEBUG_REG16_load_empty_reg_MASK | \
+      VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \
+      VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \
+      VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \
+      VGT_DEBUG_REG16_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \
+     ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \
+      (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \
+      (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \
+      (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \
+      (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \
+      (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \
+      (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \
+      (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \
+      (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \
+      (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \
+      (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \
+      (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \
+      (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \
+      (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \
+      (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \
+      (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \
+      (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \
+      (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \
+      (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \
+      (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \
+      (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \
+     ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT)
+#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT)
+#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT)
+#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT)
+#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT)
+#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT)
+#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \
+     vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+     } vgt_debug_reg16_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg16_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG16_bgrp_trigger_SIZE;
+          unsigned int top_di_grp_cull_enable_q       : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE;
+          unsigned int top_di_pre_fetch_cull_enable   : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int bgrp_grp_byte_mask_rdata       : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE;
+          unsigned int load_empty_reg                 : VGT_DEBUG_REG16_load_empty_reg_SIZE;
+          unsigned int ast_bit_block2_q               : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE;
+          unsigned int last_bit_block_q               : VGT_DEBUG_REG16_last_bit_block_q_SIZE;
+          unsigned int dbl_last_bit_q                 : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE;
+          unsigned int prev_last_bit_q                : VGT_DEBUG_REG16_prev_last_bit_q_SIZE;
+          unsigned int old_state_en                   : VGT_DEBUG_REG16_old_state_en_SIZE;
+          unsigned int old_state_q                    : VGT_DEBUG_REG16_old_state_q_SIZE;
+          unsigned int current_state_q                : VGT_DEBUG_REG16_current_state_q_SIZE;
+          unsigned int rst_last_bit                   : VGT_DEBUG_REG16_rst_last_bit_SIZE;
+          unsigned int bgrp_grp_bin_valid             : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE;
+          unsigned int bgrp_dma_mask_kill             : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE;
+          unsigned int bgrp_byte_mask_fifo_we         : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE;
+          unsigned int bgrp_byte_mask_fifo_re_q       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE;
+          unsigned int bgrp_byte_mask_fifo_empty      : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE;
+          unsigned int bgrp_byte_mask_fifo_full       : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_we        : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE;
+          unsigned int dma_bgrp_cull_fetch_read       : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_empty     : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_full      : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE;
+     } vgt_debug_reg16_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg16_t f;
+} vgt_debug_reg16_u;
+
+
+/*
+ * VGT_DEBUG_REG17 struct
+ */
+
+#define VGT_DEBUG_REG17_save_read_q_SIZE 1
+#define VGT_DEBUG_REG17_extend_read_q_SIZE 1
+#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2
+#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1
+#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1
+#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1
+#define VGT_DEBUG_REG17_check_second_reg_SIZE 1
+#define VGT_DEBUG_REG17_check_first_reg_SIZE 1
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1
+#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1
+#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7
+#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1
+
+#define VGT_DEBUG_REG17_save_read_q_SHIFT 0
+#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1
+#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2
+#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4
+#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5
+#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6
+#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7
+#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8
+#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14
+#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15
+#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16
+#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17
+#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24
+#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001
+#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002
+#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c
+#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010
+#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020
+#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040
+#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080
+#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100
+#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200
+#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400
+#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800
+#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000
+#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000
+#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000
+#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000
+#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000
+#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000
+#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000
+#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG17_MASK \
+     (VGT_DEBUG_REG17_save_read_q_MASK | \
+      VGT_DEBUG_REG17_extend_read_q_MASK | \
+      VGT_DEBUG_REG17_grp_indx_size_MASK | \
+      VGT_DEBUG_REG17_cull_prim_true_MASK | \
+      VGT_DEBUG_REG17_reset_bit2_q_MASK | \
+      VGT_DEBUG_REG17_reset_bit1_q_MASK | \
+      VGT_DEBUG_REG17_first_reg_first_q_MASK | \
+      VGT_DEBUG_REG17_check_second_reg_MASK | \
+      VGT_DEBUG_REG17_check_first_reg_MASK | \
+      VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \
+      VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \
+      VGT_DEBUG_REG17_to_second_reg_q_MASK | \
+      VGT_DEBUG_REG17_roll_over_msk_q_MASK | \
+      VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \
+      VGT_DEBUG_REG17_bgrp_trigger_MASK)
+
+#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \
+     ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \
+      (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \
+      (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \
+      (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \
+      (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \
+      (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \
+      (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \
+      (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \
+      (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \
+      (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \
+      (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \
+      (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \
+      (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \
+      (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \
+      (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \
+      (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \
+      (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \
+      (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \
+      (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT))
+
+#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \
+     ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT)
+#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT)
+#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \
+     vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+     } vgt_debug_reg17_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg17_t {
+          unsigned int bgrp_trigger                   : VGT_DEBUG_REG17_bgrp_trigger_SIZE;
+          unsigned int min_msk_ptr_q                  : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE;
+          unsigned int max_msk_ptr_q                  : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE;
+          unsigned int roll_over_msk_q                : VGT_DEBUG_REG17_roll_over_msk_q_SIZE;
+          unsigned int to_second_reg_q                : VGT_DEBUG_REG17_to_second_reg_q_SIZE;
+          unsigned int save_byte_mask_data1_q         : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE;
+          unsigned int save_byte_mask_data2_q         : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE;
+          unsigned int save_cull_fetch_data1_q        : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE;
+          unsigned int save_cull_fetch_data2_q        : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE;
+          unsigned int bgrp_cull_fetch_fifo_wdata     : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE;
+          unsigned int check_first_reg                : VGT_DEBUG_REG17_check_first_reg_SIZE;
+          unsigned int check_second_reg               : VGT_DEBUG_REG17_check_second_reg_SIZE;
+          unsigned int first_reg_first_q              : VGT_DEBUG_REG17_first_reg_first_q_SIZE;
+          unsigned int reset_bit1_q                   : VGT_DEBUG_REG17_reset_bit1_q_SIZE;
+          unsigned int reset_bit2_q                   : VGT_DEBUG_REG17_reset_bit2_q_SIZE;
+          unsigned int cull_prim_true                 : VGT_DEBUG_REG17_cull_prim_true_SIZE;
+          unsigned int grp_indx_size                  : VGT_DEBUG_REG17_grp_indx_size_SIZE;
+          unsigned int extend_read_q                  : VGT_DEBUG_REG17_extend_read_q_SIZE;
+          unsigned int save_read_q                    : VGT_DEBUG_REG17_save_read_q_SIZE;
+     } vgt_debug_reg17_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg17_t f;
+} vgt_debug_reg17_u;
+
+
+/*
+ * VGT_DEBUG_REG18 struct
+ */
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2
+#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1
+#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1
+#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1
+#define VGT_DEBUG_REG18_start_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1
+#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1
+#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13
+#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15
+#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16
+#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17
+#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20
+#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21
+#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22
+#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23
+#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24
+#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25
+#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26
+#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27
+#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28
+#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31
+
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0
+#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000
+#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000
+#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000
+#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000
+#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000
+#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000
+#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000
+#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000
+#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000
+#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000
+#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000
+#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000
+#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000
+#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000
+#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000
+#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000
+#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000
+
+#define VGT_DEBUG_REG18_MASK \
+     (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \
+      VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \
+      VGT_DEBUG_REG18_dma_mem_full_MASK | \
+      VGT_DEBUG_REG18_dma_ram_re_MASK | \
+      VGT_DEBUG_REG18_dma_ram_we_MASK | \
+      VGT_DEBUG_REG18_dma_mem_empty_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \
+      VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \
+      VGT_DEBUG_REG18_bin_mem_full_MASK | \
+      VGT_DEBUG_REG18_bin_ram_we_MASK | \
+      VGT_DEBUG_REG18_bin_ram_re_MASK | \
+      VGT_DEBUG_REG18_bin_mem_empty_MASK | \
+      VGT_DEBUG_REG18_start_bin_req_MASK | \
+      VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \
+      VGT_DEBUG_REG18_dma_req_xfer_MASK | \
+      VGT_DEBUG_REG18_have_valid_bin_req_MASK | \
+      VGT_DEBUG_REG18_have_valid_dma_req_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \
+      VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK)
+
+#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \
+     ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \
+      (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \
+      (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \
+      (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \
+      (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \
+      (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \
+      (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \
+      (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \
+      (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \
+      (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \
+      (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \
+      (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \
+      (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \
+      (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \
+      (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \
+      (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \
+      (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \
+      (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \
+      (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \
+      (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \
+      (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT))
+
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \
+     ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT)
+#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT)
+#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT)
+#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT)
+#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \
+     vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+     } vgt_debug_reg18_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg18_t {
+          unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE;
+          unsigned int bgrp_dma_di_grp_cull_enable    : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE;
+          unsigned int have_valid_dma_req             : VGT_DEBUG_REG18_have_valid_dma_req_SIZE;
+          unsigned int have_valid_bin_req             : VGT_DEBUG_REG18_have_valid_bin_req_SIZE;
+          unsigned int dma_req_xfer                   : VGT_DEBUG_REG18_dma_req_xfer_SIZE;
+          unsigned int fetch_cull_not_used            : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE;
+          unsigned int start_bin_req                  : VGT_DEBUG_REG18_start_bin_req_SIZE;
+          unsigned int bin_mem_empty                  : VGT_DEBUG_REG18_bin_mem_empty_SIZE;
+          unsigned int bin_ram_re                     : VGT_DEBUG_REG18_bin_ram_re_SIZE;
+          unsigned int bin_ram_we                     : VGT_DEBUG_REG18_bin_ram_we_SIZE;
+          unsigned int bin_mem_full                   : VGT_DEBUG_REG18_bin_mem_full_SIZE;
+          unsigned int dma_data_fifo_mem_we           : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE;
+          unsigned int dma_data_fifo_mem_re           : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE;
+          unsigned int dma_mem_empty                  : VGT_DEBUG_REG18_dma_mem_empty_SIZE;
+          unsigned int dma_ram_we                     : VGT_DEBUG_REG18_dma_ram_we_SIZE;
+          unsigned int dma_ram_re                     : VGT_DEBUG_REG18_dma_ram_re_SIZE;
+          unsigned int dma_mem_full                   : VGT_DEBUG_REG18_dma_mem_full_SIZE;
+          unsigned int dma_bgrp_dma_data_fifo_rptr    : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE;
+          unsigned int dma_bgrp_byte_mask_fifo_re     : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE;
+          unsigned int dma_data_fifo_mem_waddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE;
+          unsigned int dma_data_fifo_mem_raddr        : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE;
+     } vgt_debug_reg18_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg18_t f;
+} vgt_debug_reg18_u;
+
+
+/*
+ * VGT_DEBUG_REG20 struct
+ */
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1
+#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1
+#define VGT_DEBUG_REG20_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_sent_cnt_SIZE  4
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5
+#define VGT_DEBUG_REG20_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1
+#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2
+#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3
+#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4
+#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5
+#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6
+#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7
+#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8
+#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9
+#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10
+#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11
+#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12
+#define VGT_DEBUG_REG20_hold_prim_SHIFT 13
+#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14
+#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20
+#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21
+#define VGT_DEBUG_REG20_out_trigger_SHIFT 26
+
+#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001
+#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002
+#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004
+#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008
+#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010
+#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020
+#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040
+#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080
+#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100
+#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200
+#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400
+#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800
+#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000
+#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000
+#define VGT_DEBUG_REG20_sent_cnt_MASK  0x0003c000
+#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000
+#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000
+#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000
+#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000
+#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000
+
+#define VGT_DEBUG_REG20_MASK \
+     (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \
+      VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_re_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_we_MASK | \
+      VGT_DEBUG_REG20_prim_buffer_full_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_empty_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_re_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_we_MASK | \
+      VGT_DEBUG_REG20_indx_buffer_full_MASK | \
+      VGT_DEBUG_REG20_hold_prim_MASK | \
+      VGT_DEBUG_REG20_sent_cnt_MASK | \
+      VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \
+      VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \
+      VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \
+      VGT_DEBUG_REG20_out_trigger_MASK)
+
+#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \
+     ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \
+      (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \
+      (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \
+      (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \
+      (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \
+      (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \
+      (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \
+      (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \
+      (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \
+      (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \
+      (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \
+      (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \
+      (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \
+      (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \
+      (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \
+      (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \
+      (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \
+      (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \
+      (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \
+     ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT)
+#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT)
+#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT)
+#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT)
+#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT)
+#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \
+     vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int                                : 5;
+     } vgt_debug_reg20_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg20_t {
+          unsigned int                                : 5;
+          unsigned int out_trigger                    : VGT_DEBUG_REG20_out_trigger_SIZE;
+          unsigned int buffered_prim_type_event       : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE;
+          unsigned int clip_p_pre_hold_prim           : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE;
+          unsigned int clip_s_pre_hold_prim           : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE;
+          unsigned int start_of_vtx_vector            : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE;
+          unsigned int sent_cnt                       : VGT_DEBUG_REG20_sent_cnt_SIZE;
+          unsigned int hold_prim                      : VGT_DEBUG_REG20_hold_prim_SIZE;
+          unsigned int indx_buffer_full               : VGT_DEBUG_REG20_indx_buffer_full_SIZE;
+          unsigned int indx_buffer_we                 : VGT_DEBUG_REG20_indx_buffer_we_SIZE;
+          unsigned int indx_buffer_re                 : VGT_DEBUG_REG20_indx_buffer_re_SIZE;
+          unsigned int indx_buffer_empty              : VGT_DEBUG_REG20_indx_buffer_empty_SIZE;
+          unsigned int prim_buffer_full               : VGT_DEBUG_REG20_prim_buffer_full_SIZE;
+          unsigned int prim_buffer_we                 : VGT_DEBUG_REG20_prim_buffer_we_SIZE;
+          unsigned int prim_buffer_re                 : VGT_DEBUG_REG20_prim_buffer_re_SIZE;
+          unsigned int prim_buffer_empty              : VGT_DEBUG_REG20_prim_buffer_empty_SIZE;
+          unsigned int indx_side_fifo_full            : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE;
+          unsigned int indx_side_fifo_we              : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE;
+          unsigned int indx_side_fifo_re              : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE;
+          unsigned int indx_side_fifo_empty           : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE;
+          unsigned int prim_side_indx_valid           : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE;
+     } vgt_debug_reg20_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg20_t f;
+} vgt_debug_reg20_u;
+
+
+/*
+ * VGT_DEBUG_REG21 struct
+ */
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3
+#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4
+#define VGT_DEBUG_REG21_new_packet_q_SIZE 1
+#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1
+#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1
+#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1
+#define VGT_DEBUG_REG21_out_trigger_SIZE 1
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1
+#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7
+#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14
+#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18
+#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20
+#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22
+#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25
+#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26
+#define VGT_DEBUG_REG21_out_trigger_SHIFT 31
+
+#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001
+#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e
+#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070
+#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380
+#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00
+#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000
+#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000
+#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000
+#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000
+#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000
+#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000
+#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000
+#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000
+#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000
+#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000
+
+#define VGT_DEBUG_REG21_MASK \
+     (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \
+      VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \
+      VGT_DEBUG_REG21_alloc_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \
+      VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \
+      VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \
+      VGT_DEBUG_REG21_new_packet_q_MASK | \
+      VGT_DEBUG_REG21_new_allocate_q_MASK | \
+      VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \
+      VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \
+      VGT_DEBUG_REG21_insert_null_prim_MASK | \
+      VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \
+      VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \
+      VGT_DEBUG_REG21_buffered_thread_size_MASK | \
+      VGT_DEBUG_REG21_out_trigger_MASK)
+
+#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \
+     ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \
+      (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \
+      (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \
+      (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \
+      (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \
+      (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \
+      (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \
+      (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \
+      (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \
+      (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \
+      (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \
+      (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \
+      (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \
+      (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \
+      (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT))
+
+#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \
+     ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT)
+#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT)
+#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT)
+#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT)
+#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT)
+#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \
+     vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int                                : 4;
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+     } vgt_debug_reg21_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_debug_reg21_t {
+          unsigned int out_trigger                    : VGT_DEBUG_REG21_out_trigger_SIZE;
+          unsigned int                                : 4;
+          unsigned int buffered_thread_size           : VGT_DEBUG_REG21_buffered_thread_size_SIZE;
+          unsigned int prim_buffer_empty_mux          : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE;
+          unsigned int buffered_prim_eop_mux          : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE;
+          unsigned int insert_null_prim               : VGT_DEBUG_REG21_insert_null_prim_SIZE;
+          unsigned int inserted_null_prim_q           : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE;
+          unsigned int num_new_unique_rel_indx        : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE;
+          unsigned int new_allocate_q                 : VGT_DEBUG_REG21_new_allocate_q_SIZE;
+          unsigned int new_packet_q                   : VGT_DEBUG_REG21_new_packet_q_SIZE;
+          unsigned int curr_dealloc_distance_q        : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE;
+          unsigned int int_vtx_counter_q              : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE;
+          unsigned int curr_slot_in_vtx_vect_q        : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE;
+          unsigned int alloc_counter_q                : VGT_DEBUG_REG21_alloc_counter_q_SIZE;
+          unsigned int prim_end_of_vtx_vect_flags     : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE;
+          unsigned int null_terminate_vtx_vector      : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE;
+     } vgt_debug_reg21_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_debug_reg21_t f;
+} vgt_debug_reg21_u;
+
+
+/*
+ * VGT_CRC_SQ_DATA struct
+ */
+
+#define VGT_CRC_SQ_DATA_CRC_SIZE       32
+
+#define VGT_CRC_SQ_DATA_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_DATA_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_DATA_MASK \
+     (VGT_CRC_SQ_DATA_CRC_MASK)
+
+#define VGT_CRC_SQ_DATA(crc) \
+     ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT))
+
+#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \
+     ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \
+     vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_data_t {
+          unsigned int crc                            : VGT_CRC_SQ_DATA_CRC_SIZE;
+     } vgt_crc_sq_data_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_data_t f;
+} vgt_crc_sq_data_u;
+
+
+/*
+ * VGT_CRC_SQ_CTRL struct
+ */
+
+#define VGT_CRC_SQ_CTRL_CRC_SIZE       32
+
+#define VGT_CRC_SQ_CTRL_CRC_SHIFT      0
+
+#define VGT_CRC_SQ_CTRL_CRC_MASK       0xffffffff
+
+#define VGT_CRC_SQ_CTRL_MASK \
+     (VGT_CRC_SQ_CTRL_CRC_MASK)
+
+#define VGT_CRC_SQ_CTRL(crc) \
+     ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT))
+
+#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \
+     ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \
+     vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_crc_sq_ctrl_t {
+          unsigned int crc                            : VGT_CRC_SQ_CTRL_CRC_SIZE;
+     } vgt_crc_sq_ctrl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_crc_sq_ctrl_t f;
+} vgt_crc_sq_ctrl_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER0_SELECT_MASK \
+     (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \
+     ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \
+     vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_select_t f;
+} vgt_perfcounter0_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER1_SELECT_MASK \
+     (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \
+     ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \
+     vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_select_t f;
+} vgt_perfcounter1_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER2_SELECT_MASK \
+     (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \
+     ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \
+     vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_select_t f;
+} vgt_perfcounter2_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_SELECT struct
+ */
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define VGT_PERFCOUNTER3_SELECT_MASK \
+     (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define VGT_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \
+     ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \
+     vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } vgt_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } vgt_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_select_t f;
+} vgt_perfcounter3_select_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_LOW struct
+ */
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER0_LOW_MASK \
+     (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \
+     ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \
+     vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_low_t f;
+} vgt_perfcounter0_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_LOW struct
+ */
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER1_LOW_MASK \
+     (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \
+     ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \
+     vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_low_t f;
+} vgt_perfcounter1_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_LOW struct
+ */
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER2_LOW_MASK \
+     (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \
+     ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \
+     vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_low_t f;
+} vgt_perfcounter2_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_LOW struct
+ */
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define VGT_PERFCOUNTER3_LOW_MASK \
+     (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \
+     ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \
+     vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_low_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_low_t f;
+} vgt_perfcounter3_low_u;
+
+
+/*
+ * VGT_PERFCOUNTER0_HI struct
+ */
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER0_HI_MASK \
+     (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \
+     ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \
+     vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter0_hi_t f;
+} vgt_perfcounter0_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER1_HI struct
+ */
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER1_HI_MASK \
+     (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \
+     ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \
+     vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter1_hi_t f;
+} vgt_perfcounter1_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER2_HI struct
+ */
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER2_HI_MASK \
+     (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \
+     ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \
+     vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter2_hi_t f;
+} vgt_perfcounter2_hi_u;
+
+
+/*
+ * VGT_PERFCOUNTER3_HI struct
+ */
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define VGT_PERFCOUNTER3_HI_MASK \
+     (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define VGT_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \
+     ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \
+     vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } vgt_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _vgt_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } vgt_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     vgt_perfcounter3_hi_t f;
+} vgt_perfcounter3_hi_u;
+
+
+#endif
+
+
+#if !defined (_SQ_FIDDLE_H)
+#define _SQ_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * SQ_GPR_MANAGEMENT struct
+ */
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12
+
+#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001
+#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0
+#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000
+
+#define SQ_GPR_MANAGEMENT_MASK \
+     (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \
+      SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK)
+
+#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \
+     ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \
+      (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \
+      (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT))
+
+#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \
+     ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT)
+#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \
+     sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 13;
+     } sq_gpr_management_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_gpr_management_t {
+          unsigned int                                : 13;
+          unsigned int reg_size_vtx                   : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_size_pix                   : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE;
+          unsigned int                                : 3;
+          unsigned int reg_dynamic                    : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE;
+     } sq_gpr_management_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_gpr_management_t f;
+} sq_gpr_management_u;
+
+
+/*
+ * SQ_FLOW_CONTROL struct
+ */
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1
+#define SQ_FLOW_CONTROL_ONE_ALU_SIZE   1
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4
+#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE  1
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0
+#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4
+#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT  8
+#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12
+#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27
+
+#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003
+#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010
+#define SQ_FLOW_CONTROL_ONE_ALU_MASK   0x00000100
+#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000
+#define SQ_FLOW_CONTROL_NO_PV_PS_MASK  0x00010000
+#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000
+#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000
+#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000
+#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000
+#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000
+#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000
+#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000
+#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000
+#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000
+#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000
+
+#define SQ_FLOW_CONTROL_MASK \
+     (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ONE_THREAD_MASK | \
+      SQ_FLOW_CONTROL_ONE_ALU_MASK | \
+      SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \
+      SQ_FLOW_CONTROL_NO_PV_PS_MASK | \
+      SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \
+      SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \
+      SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \
+      SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \
+      SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \
+      SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \
+      SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \
+      SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK)
+
+#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \
+     ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \
+      (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \
+      (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \
+      (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \
+      (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \
+      (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \
+      (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \
+      (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \
+      (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \
+      (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \
+      (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \
+      (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \
+      (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \
+      (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \
+      (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT))
+
+#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \
+     ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT)
+#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT)
+#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT)
+#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT)
+#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT)
+#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \
+     sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+          unsigned int                                : 2;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int                                : 4;
+     } sq_flow_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_flow_control_t {
+          unsigned int                                : 4;
+          unsigned int ps_prefetch_color_alloc        : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE;
+          unsigned int no_early_thread_termination    : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE;
+          unsigned int pos_exp_priority               : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE;
+          unsigned int no_cfs_eject                   : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE;
+          unsigned int no_arb_eject                   : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE;
+          unsigned int alu_arbitration_policy         : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE;
+          unsigned int vc_arbitration_policy          : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE;
+          unsigned int texture_arbitration_policy     : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE;
+          unsigned int no_cexec_optimize              : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE;
+          unsigned int no_loop_exit                   : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE;
+          unsigned int no_pv_ps                       : SQ_FLOW_CONTROL_NO_PV_PS_SIZE;
+          unsigned int cf_wr_base                     : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_alu                        : SQ_FLOW_CONTROL_ONE_ALU_SIZE;
+          unsigned int                                : 3;
+          unsigned int one_thread                     : SQ_FLOW_CONTROL_ONE_THREAD_SIZE;
+          unsigned int                                : 2;
+          unsigned int input_arbitration_policy       : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE;
+     } sq_flow_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_flow_control_t f;
+} sq_flow_control_u;
+
+
+/*
+ * SQ_INST_STORE_MANAGMENT struct
+ */
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16
+
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff
+#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000
+
+#define SQ_INST_STORE_MANAGMENT_MASK \
+     (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \
+      SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK)
+
+#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \
+     ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \
+      (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT))
+
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \
+     ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT)
+#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \
+     sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+     } sq_inst_store_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_inst_store_managment_t {
+          unsigned int                                : 4;
+          unsigned int inst_base_vtx                  : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE;
+          unsigned int                                : 4;
+          unsigned int inst_base_pix                  : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE;
+     } sq_inst_store_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_inst_store_managment_t f;
+} sq_inst_store_managment_u;
+
+
+/*
+ * SQ_RESOURCE_MANAGMENT struct
+ */
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16
+
+#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff
+#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00
+#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000
+
+#define SQ_RESOURCE_MANAGMENT_MASK \
+     (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \
+      SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK)
+
+#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \
+     ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \
+      (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT))
+
+#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \
+     ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT)
+#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \
+     sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int                                : 7;
+     } sq_resource_managment_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_resource_managment_t {
+          unsigned int                                : 7;
+          unsigned int export_buf_entries             : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE;
+          unsigned int pix_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE;
+          unsigned int vtx_thread_buf_entries         : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE;
+     } sq_resource_managment_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_resource_managment_t f;
+} sq_resource_managment_u;
+
+
+/*
+ * SQ_EO_RT struct
+ */
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE  8
+#define SQ_EO_RT_EO_TSTATE_RT_SIZE     8
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0
+#define SQ_EO_RT_EO_TSTATE_RT_SHIFT    16
+
+#define SQ_EO_RT_EO_CONSTANTS_RT_MASK  0x000000ff
+#define SQ_EO_RT_EO_TSTATE_RT_MASK     0x00ff0000
+
+#define SQ_EO_RT_MASK \
+     (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \
+      SQ_EO_RT_EO_TSTATE_RT_MASK)
+
+#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \
+     ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \
+      (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT))
+
+#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \
+     ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT)
+#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \
+     sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+     } sq_eo_rt_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_eo_rt_t {
+          unsigned int                                : 8;
+          unsigned int eo_tstate_rt                   : SQ_EO_RT_EO_TSTATE_RT_SIZE;
+          unsigned int                                : 8;
+          unsigned int eo_constants_rt                : SQ_EO_RT_EO_CONSTANTS_RT_SIZE;
+     } sq_eo_rt_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_eo_rt_t f;
+} sq_eo_rt_u;
+
+
+/*
+ * SQ_DEBUG_MISC struct
+ */
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8
+#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1
+#define SQ_DEBUG_MISC_RESERVED_SIZE    2
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12
+#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20
+#define SQ_DEBUG_MISC_RESERVED_SHIFT   21
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28
+
+#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff
+#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000
+#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000
+#define SQ_DEBUG_MISC_RESERVED_MASK    0x00600000
+#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000
+#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000
+
+#define SQ_DEBUG_MISC_MASK \
+     (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \
+      SQ_DEBUG_MISC_DB_READ_CTX_MASK | \
+      SQ_DEBUG_MISC_RESERVED_MASK | \
+      SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \
+      SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK)
+
+#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \
+     ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \
+      (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \
+      (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \
+      (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \
+      (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \
+      (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \
+      (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \
+      (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \
+      (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT))
+
+#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \
+     ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT)
+#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT)
+#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \
+     sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int                                : 3;
+     } sq_debug_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_t {
+          unsigned int                                : 3;
+          unsigned int db_wen_memory_3                : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE;
+          unsigned int db_wen_memory_2                : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE;
+          unsigned int db_wen_memory_1                : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE;
+          unsigned int db_wen_memory_0                : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE;
+          unsigned int db_read_memory                 : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_MISC_RESERVED_SIZE;
+          unsigned int db_read_ctx                    : SQ_DEBUG_MISC_DB_READ_CTX_SIZE;
+          unsigned int db_tstate_size                 : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int db_alucst_size                 : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE;
+     } sq_debug_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_t f;
+} sq_debug_misc_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_CNTL struct
+ */
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16
+#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24
+
+#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00
+#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000
+#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000
+
+#define SQ_ACTIVITY_METER_CNTL_MASK \
+     (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \
+      SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \
+      SQ_ACTIVITY_METER_CNTL_SPARE_MASK)
+
+#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \
+     ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \
+      (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \
+      (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \
+      (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT))
+
+#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \
+     ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT)
+#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \
+     sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_cntl_t {
+          unsigned int spare                          : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE;
+          unsigned int threshold_high                 : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE;
+          unsigned int threshold_low                  : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE;
+          unsigned int timebase                       : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE;
+     } sq_activity_meter_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_cntl_t f;
+} sq_activity_meter_cntl_u;
+
+
+/*
+ * SQ_ACTIVITY_METER_STATUS struct
+ */
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0
+
+#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff
+
+#define SQ_ACTIVITY_METER_STATUS_MASK \
+     (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK)
+
+#define SQ_ACTIVITY_METER_STATUS(percent_busy) \
+     ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT))
+
+#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \
+     ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \
+     sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+          unsigned int                                : 24;
+     } sq_activity_meter_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_activity_meter_status_t {
+          unsigned int                                : 24;
+          unsigned int percent_busy                   : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE;
+     } sq_activity_meter_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_activity_meter_status_t f;
+} sq_activity_meter_status_u;
+
+
+/*
+ * SQ_INPUT_ARB_PRIORITY struct
+ */
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8
+
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+
+#define SQ_INPUT_ARB_PRIORITY_MASK \
+     (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK)
+
+#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \
+     ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT))
+
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \
+     ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \
+     sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int                                : 14;
+     } sq_input_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_input_arb_priority_t {
+          unsigned int                                : 14;
+          unsigned int threshold                      : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_input_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_input_arb_priority_t f;
+} sq_input_arb_priority_u;
+
+
+/*
+ * SQ_THREAD_ARB_PRIORITY struct
+ */
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22
+
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007
+#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070
+#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080
+#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00
+#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000
+#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000
+#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000
+#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000
+
+#define SQ_THREAD_ARB_PRIORITY_MASK \
+     (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \
+      SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \
+      SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \
+      SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \
+      SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \
+      SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK)
+
+#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \
+     ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \
+      (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \
+      (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \
+      (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \
+      (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \
+      (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \
+      (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \
+      (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \
+      (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT))
+
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \
+     ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT)
+#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \
+     sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int                                : 9;
+     } sq_thread_arb_priority_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_thread_arb_priority_t {
+          unsigned int                                : 9;
+          unsigned int use_serial_count_threshold     : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE;
+          unsigned int ps_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int vs_prioritize_serial           : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE;
+          unsigned int threshold                      : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE;
+          unsigned int sx_avail_sign                  : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE;
+          unsigned int sx_avail_weight                : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE;
+          unsigned int pc_avail_sign                  : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE;
+          unsigned int pc_avail_weight                : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE;
+     } sq_thread_arb_priority_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_thread_arb_priority_t f;
+} sq_thread_arb_priority_u;
+
+
+/*
+ * SQ_VS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_VS_WATCHDOG_TIMER_MASK \
+     (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \
+     ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \
+     sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_vs_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_watchdog_timer_t f;
+} sq_vs_watchdog_timer_u;
+
+
+/*
+ * SQ_PS_WATCHDOG_TIMER struct
+ */
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1
+
+#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001
+#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe
+
+#define SQ_PS_WATCHDOG_TIMER_MASK \
+     (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \
+      SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK)
+
+#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \
+     ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \
+      (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT))
+
+#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \
+     ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT)
+#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \
+     sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_watchdog_timer_t {
+          unsigned int timeout_count                  : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE;
+          unsigned int enable                         : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE;
+     } sq_ps_watchdog_timer_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_watchdog_timer_t f;
+} sq_ps_watchdog_timer_u;
+
+
+/*
+ * SQ_INT_CNTL struct
+ */
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1
+
+#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001
+#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002
+
+#define SQ_INT_CNTL_MASK \
+     (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \
+      SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK)
+
+#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \
+     ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \
+      (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT))
+
+#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \
+     ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT)
+#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \
+     sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_cntl_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_mask               : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE;
+          unsigned int ps_watchdog_mask               : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE;
+     } sq_int_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_cntl_t f;
+} sq_int_cntl_u;
+
+
+/*
+ * SQ_INT_STATUS struct
+ */
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1
+
+#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001
+#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002
+
+#define SQ_INT_STATUS_MASK \
+     (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \
+      SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK)
+
+#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \
+     ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \
+      (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT))
+
+#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \
+     ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT)
+#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \
+     sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int                                : 30;
+     } sq_int_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_status_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_timeout            : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE;
+          unsigned int ps_watchdog_timeout            : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE;
+     } sq_int_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_status_t f;
+} sq_int_status_u;
+
+
+/*
+ * SQ_INT_ACK struct
+ */
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1
+
+#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001
+#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002
+
+#define SQ_INT_ACK_MASK \
+     (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \
+      SQ_INT_ACK_VS_WATCHDOG_ACK_MASK)
+
+#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \
+     ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \
+      (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT))
+
+#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \
+     ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT)
+#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \
+     sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int                                : 30;
+     } sq_int_ack_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_int_ack_t {
+          unsigned int                                : 30;
+          unsigned int vs_watchdog_ack                : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE;
+          unsigned int ps_watchdog_ack                : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE;
+     } sq_int_ack_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_int_ack_t f;
+} sq_int_ack_u;
+
+
+/*
+ * SQ_DEBUG_INPUT_FSM struct
+ */
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE  3
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0
+#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20
+
+#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007
+#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008
+#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0
+#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700
+#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK  0x00007000
+#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000
+#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000
+
+#define SQ_DEBUG_INPUT_FSM_MASK \
+     (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \
+      SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \
+      SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \
+      SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK)
+
+#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \
+     ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \
+      (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \
+      (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \
+      (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \
+      (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \
+      (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \
+      (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \
+      (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT))
+
+#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \
+     ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT)
+#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \
+     sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_input_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_input_fsm_t {
+          unsigned int                                : 4;
+          unsigned int pc_gpr_size                    : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE;
+          unsigned int pc_interp_cnt                  : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE;
+          unsigned int pc_as                          : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE;
+          unsigned int pc_pism                        : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE;
+          unsigned int vc_gpr_ld                      : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE;
+          unsigned int vc_vsr_ld                      : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE;
+     } sq_debug_input_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_input_fsm_t f;
+} sq_debug_input_fsm_u;
+
+
+/*
+ * SQ_DEBUG_CONST_MGR_FSM struct
+ */
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23
+
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00
+#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000
+#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000
+#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000
+#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000
+
+#define SQ_DEBUG_CONST_MGR_FSM_MASK \
+     (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \
+      SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK)
+
+#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \
+     ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \
+      (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \
+      (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \
+      (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \
+      (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \
+      (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \
+      (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \
+      (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \
+      (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \
+      (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT))
+
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \
+     ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT)
+#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \
+     sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int                                : 8;
+     } sq_debug_const_mgr_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_const_mgr_fsm_t {
+          unsigned int                                : 8;
+          unsigned int cntx1_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx1_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE;
+          unsigned int cntx0_pix_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE;
+          unsigned int cntx0_vtx_event_done           : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE;
+          unsigned int tex_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE;
+          unsigned int alu_const_cntx_valid           : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE;
+          unsigned int alu_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE;
+          unsigned int tex_const_event_state          : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE;
+     } sq_debug_const_mgr_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_const_mgr_fsm_t f;
+} sq_debug_const_mgr_fsm_u;
+
+
+/*
+ * SQ_DEBUG_TP_FSM struct
+ */
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1
+#define SQ_DEBUG_TP_FSM_CF_TP_SIZE     4
+#define SQ_DEBUG_TP_FSM_IF_TP_SIZE     3
+#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1
+#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2
+#define SQ_DEBUG_TP_FSM_GS_TP_SIZE     2
+#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2
+#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE    2
+#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3
+
+#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT    0
+#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3
+#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT    4
+#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT    8
+#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11
+#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT   12
+#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14
+#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT    16
+#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18
+#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT   20
+#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22
+#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT   24
+#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28
+
+#define SQ_DEBUG_TP_FSM_EX_TP_MASK     0x00000007
+#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_TP_FSM_CF_TP_MASK     0x000000f0
+#define SQ_DEBUG_TP_FSM_IF_TP_MASK     0x00000700
+#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_TP_FSM_TIS_TP_MASK    0x00003000
+#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000
+#define SQ_DEBUG_TP_FSM_GS_TP_MASK     0x00030000
+#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000
+#define SQ_DEBUG_TP_FSM_FCR_TP_MASK    0x00300000
+#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000
+#define SQ_DEBUG_TP_FSM_FCS_TP_MASK    0x03000000
+#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000
+#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000
+
+#define SQ_DEBUG_TP_FSM_MASK \
+     (SQ_DEBUG_TP_FSM_EX_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED0_MASK | \
+      SQ_DEBUG_TP_FSM_CF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_IF_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED1_MASK | \
+      SQ_DEBUG_TP_FSM_TIS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED2_MASK | \
+      SQ_DEBUG_TP_FSM_GS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED3_MASK | \
+      SQ_DEBUG_TP_FSM_FCR_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED4_MASK | \
+      SQ_DEBUG_TP_FSM_FCS_TP_MASK | \
+      SQ_DEBUG_TP_FSM_RESERVED5_MASK | \
+      SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK)
+
+#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \
+     ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \
+      (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \
+      (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \
+      (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \
+      (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \
+      (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \
+      (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \
+      (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \
+      (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \
+      (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \
+      (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \
+      (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \
+      (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \
+      (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT))
+
+#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \
+     ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT)
+#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \
+     sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_tp_fsm_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tp_fsm_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_tp                      : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_TP_FSM_RESERVED5_SIZE;
+          unsigned int fcs_tp                         : SQ_DEBUG_TP_FSM_FCS_TP_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_TP_FSM_RESERVED4_SIZE;
+          unsigned int fcr_tp                         : SQ_DEBUG_TP_FSM_FCR_TP_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_TP_FSM_RESERVED3_SIZE;
+          unsigned int gs_tp                          : SQ_DEBUG_TP_FSM_GS_TP_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_TP_FSM_RESERVED2_SIZE;
+          unsigned int tis_tp                         : SQ_DEBUG_TP_FSM_TIS_TP_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_TP_FSM_RESERVED1_SIZE;
+          unsigned int if_tp                          : SQ_DEBUG_TP_FSM_IF_TP_SIZE;
+          unsigned int cf_tp                          : SQ_DEBUG_TP_FSM_CF_TP_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_TP_FSM_RESERVED0_SIZE;
+          unsigned int ex_tp                          : SQ_DEBUG_TP_FSM_EX_TP_SIZE;
+     } sq_debug_tp_fsm_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tp_fsm_t f;
+} sq_debug_tp_fsm_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_0 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_0_MASK \
+     (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \
+     ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_0_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_0_t f;
+} sq_debug_fsm_alu_0_u;
+
+
+/*
+ * SQ_DEBUG_FSM_ALU_1 struct
+ */
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28
+
+#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007
+#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008
+#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0
+#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700
+#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800
+#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000
+#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000
+#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000
+#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000
+#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000
+#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000
+
+#define SQ_DEBUG_FSM_ALU_1_MASK \
+     (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \
+      SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \
+      SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \
+      SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \
+      SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK)
+
+#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \
+     ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \
+      (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \
+      (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \
+      (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \
+      (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \
+      (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \
+      (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \
+      (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \
+      (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \
+      (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \
+      (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \
+      (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \
+      (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \
+      (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT))
+
+#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \
+     ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT)
+#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \
+     sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_fsm_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_fsm_alu_1_t {
+          unsigned int                                : 1;
+          unsigned int arb_tr_alu                     : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE;
+          unsigned int reserved5                      : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE;
+          unsigned int acs_alu_0                      : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE;
+          unsigned int reserved4                      : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE;
+          unsigned int ais_alu_0                      : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE;
+          unsigned int reserved3                      : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE;
+          unsigned int du0_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE;
+          unsigned int du1_alu_0                      : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE;
+          unsigned int if_alu_0                       : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE;
+          unsigned int cf_alu_0                       : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE;
+          unsigned int reserved0                      : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE;
+          unsigned int ex_alu_0                       : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE;
+     } sq_debug_fsm_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_fsm_alu_1_t f;
+} sq_debug_fsm_alu_1_u;
+
+
+/*
+ * SQ_DEBUG_EXP_ALLOC struct
+ */
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16
+
+#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f
+#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0
+#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000
+#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000
+#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000
+
+#define SQ_DEBUG_EXP_ALLOC_MASK \
+     (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \
+      SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \
+      SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK)
+
+#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \
+     ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \
+      (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \
+      (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \
+      (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \
+      (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT))
+
+#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \
+     ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT)
+#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \
+     sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_exp_alloc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_exp_alloc_t {
+          unsigned int                                : 10;
+          unsigned int alloc_tbl_buf_avail            : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE;
+          unsigned int ea_buf_avail                   : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE;
+          unsigned int color_buf_avail                : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE;
+          unsigned int pos_buf_avail                  : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE;
+     } sq_debug_exp_alloc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_exp_alloc_t f;
+} sq_debug_exp_alloc_u;
+
+
+/*
+ * SQ_DEBUG_PTR_BUFF struct
+ */
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17
+
+#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001
+#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e
+#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020
+#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0
+#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00
+#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000
+#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000
+#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000
+#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000
+
+#define SQ_DEBUG_PTR_BUFF_MASK \
+     (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \
+      SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \
+      SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \
+      SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \
+      SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \
+      SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \
+      SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK)
+
+#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \
+     ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \
+      (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \
+      (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \
+      (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \
+      (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \
+      (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \
+      (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \
+      (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \
+      (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT))
+
+#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \
+     ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT)
+#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \
+     sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int                                : 4;
+     } sq_debug_ptr_buff_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_ptr_buff_t {
+          unsigned int                                : 4;
+          unsigned int vtx_sync_cnt                   : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE;
+          unsigned int ef_empty                       : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE;
+          unsigned int prim_type_polygon              : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE;
+          unsigned int qual_event                     : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE;
+          unsigned int sc_event_id                    : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE;
+          unsigned int event_context_id               : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE;
+          unsigned int qual_new_vector                : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE;
+          unsigned int dealloc_cnt                    : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE;
+          unsigned int end_of_buffer                  : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE;
+     } sq_debug_ptr_buff_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_ptr_buff_t f;
+} sq_debug_ptr_buff_u;
+
+
+/*
+ * SQ_DEBUG_GPR_VTX struct
+ */
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_VTX_MASK \
+     (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \
+      SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_VTX_VTX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \
+     ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \
+      (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \
+      (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \
+      (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \
+     ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \
+     sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_vtx_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_vtx_t {
+          unsigned int                                : 1;
+          unsigned int vtx_free                       : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE;
+          unsigned int vtx_max                        : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE;
+          unsigned int vtx_head_ptr                   : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_VTX_RESERVED_SIZE;
+          unsigned int vtx_tail_ptr                   : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_vtx_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_vtx_t f;
+} sq_debug_gpr_vtx_u;
+
+
+/*
+ * SQ_DEBUG_GPR_PIX struct
+ */
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE  7
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0
+#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8
+#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16
+#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24
+
+#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f
+#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080
+#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00
+#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000
+#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK  0x007f0000
+#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000
+#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000
+
+#define SQ_DEBUG_GPR_PIX_MASK \
+     (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \
+      SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \
+      SQ_DEBUG_GPR_PIX_PIX_FREE_MASK)
+
+#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \
+     ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \
+      (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \
+      (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \
+      (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \
+      (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \
+      (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \
+      (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT))
+
+#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \
+     ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT)
+#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \
+     sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int                                : 1;
+     } sq_debug_gpr_pix_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_gpr_pix_t {
+          unsigned int                                : 1;
+          unsigned int pix_free                       : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE;
+          unsigned int reserved2                      : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE;
+          unsigned int pix_max                        : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE;
+          unsigned int reserved1                      : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE;
+          unsigned int reserved                       : SQ_DEBUG_GPR_PIX_RESERVED_SIZE;
+          unsigned int pix_tail_ptr                   : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE;
+     } sq_debug_gpr_pix_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_gpr_pix_t f;
+} sq_debug_gpr_pix_u;
+
+
+/*
+ * SQ_DEBUG_TB_STATUS_SEL struct
+ */
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31
+
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780
+#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000
+#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000
+#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000
+#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000
+#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000
+
+#define SQ_DEBUG_TB_STATUS_SEL_MASK \
+     (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \
+      SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK)
+
+#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \
+     ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \
+      (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \
+      (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \
+      (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \
+      (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \
+      (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \
+      (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \
+      (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT))
+
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \
+     ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT)
+#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \
+     sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_tb_status_sel_t {
+          unsigned int disable_strict_ctx_sync        : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE;
+          unsigned int vc_thread_buf_dly              : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE;
+          unsigned int pix_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int pix_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int pix_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE;
+          unsigned int debug_bus_trigger_sel          : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pix_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_en         : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE;
+          unsigned int vtx_tb_state_mem_rd_addr       : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE;
+          unsigned int vtx_tb_state_mem_dw_sel        : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE;
+          unsigned int vtx_tb_status_reg_sel          : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE;
+     } sq_debug_tb_status_sel_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_tb_status_sel_t f;
+} sq_debug_tb_status_sel_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_0 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE  1
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21
+
+#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f
+#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0
+#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00
+#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000
+#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000
+#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000
+#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK  0x00200000
+
+#define SQ_DEBUG_VTX_TB_0_MASK \
+     (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \
+      SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \
+      SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK)
+
+#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \
+     ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \
+      (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \
+      (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \
+      (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \
+      (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \
+      (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \
+      (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \
+     ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT)
+#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \
+     sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int                                : 10;
+     } sq_debug_vtx_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_0_t {
+          unsigned int                                : 10;
+          unsigned int busy_q                         : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE;
+          unsigned int sx_event_full                  : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE;
+          unsigned int nxt_pc_alloc_cnt               : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE;
+          unsigned int nxt_pos_alloc_cnt              : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE;
+          unsigned int full_cnt_q                     : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE;
+          unsigned int tail_ptr_q                     : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE;
+          unsigned int vtx_head_ptr_q                 : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE;
+     } sq_debug_vtx_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_0_t f;
+} sq_debug_vtx_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_1 struct
+ */
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff
+
+#define SQ_DEBUG_VTX_TB_1_MASK \
+     (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK)
+
+#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \
+     ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \
+     ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \
+     sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+          unsigned int                                : 16;
+     } sq_debug_vtx_tb_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_1_t {
+          unsigned int                                : 16;
+          unsigned int vs_done_ptr                    : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE;
+     } sq_debug_vtx_tb_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_1_t f;
+} sq_debug_vtx_tb_1_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATUS_REG struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \
+     (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \
+     ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \
+     ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \
+     sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_status_reg_t {
+          unsigned int vs_status_reg                  : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE;
+     } sq_debug_vtx_tb_status_reg_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_status_reg_t f;
+} sq_debug_vtx_tb_status_reg_u;
+
+
+/*
+ * SQ_DEBUG_VTX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \
+     ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \
+     ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \
+     sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_vtx_tb_state_mem_t {
+          unsigned int vs_state_mem                   : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE;
+     } sq_debug_vtx_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_vtx_tb_state_mem_t f;
+} sq_debug_vtx_tb_state_mem_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6
+#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE    1
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25
+#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT   31
+
+#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f
+#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0
+#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000
+#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000
+#define SQ_DEBUG_PIX_TB_0_BUSY_MASK    0x80000000
+
+#define SQ_DEBUG_PIX_TB_0_MASK \
+     (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \
+      SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \
+      SQ_DEBUG_PIX_TB_0_BUSY_MASK)
+
+#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \
+     ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \
+      (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \
+      (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \
+      (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \
+      (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \
+      (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \
+     ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT)
+#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \
+     sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_0_t {
+          unsigned int busy                           : SQ_DEBUG_PIX_TB_0_BUSY_SIZE;
+          unsigned int nxt_pix_exp_cnt                : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE;
+          unsigned int nxt_pix_alloc_cnt              : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE;
+          unsigned int full_cnt                       : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE;
+          unsigned int tail_ptr                       : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE;
+          unsigned int pix_head_ptr                   : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE;
+     } sq_debug_pix_tb_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_0_t f;
+} sq_debug_pix_tb_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \
+     ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \
+     ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \
+     sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_0_t {
+          unsigned int pix_tb_status_reg_0            : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE;
+     } sq_debug_pix_tb_status_reg_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_0_t f;
+} sq_debug_pix_tb_status_reg_0_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \
+     ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \
+     ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \
+     sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_1_t {
+          unsigned int pix_tb_status_reg_1            : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE;
+     } sq_debug_pix_tb_status_reg_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_1_t f;
+} sq_debug_pix_tb_status_reg_1_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \
+     ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \
+     ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \
+     sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_2_t {
+          unsigned int pix_tb_status_reg_2            : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE;
+     } sq_debug_pix_tb_status_reg_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_2_t f;
+} sq_debug_pix_tb_status_reg_2_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \
+     (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \
+     ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \
+     ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \
+     sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_status_reg_3_t {
+          unsigned int pix_tb_status_reg_3            : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE;
+     } sq_debug_pix_tb_status_reg_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_status_reg_3_t f;
+} sq_debug_pix_tb_status_reg_3_u;
+
+
+/*
+ * SQ_DEBUG_PIX_TB_STATE_MEM struct
+ */
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \
+     (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \
+     ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT))
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \
+     ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \
+     sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_pix_tb_state_mem_t {
+          unsigned int pix_tb_state_mem               : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE;
+     } sq_debug_pix_tb_state_mem_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_pix_tb_state_mem_t f;
+} sq_debug_pix_tb_state_mem_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER0_SELECT_MASK \
+     (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \
+     ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \
+     sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_select_t f;
+} sq_perfcounter0_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER1_SELECT_MASK \
+     (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER1_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \
+     ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \
+     sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_select_t f;
+} sq_perfcounter1_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER2_SELECT_MASK \
+     (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER2_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \
+     ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \
+     sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_select_t f;
+} sq_perfcounter2_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_SELECT struct
+ */
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0
+
+#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SQ_PERFCOUNTER3_SELECT_MASK \
+     (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK)
+
+#define SQ_PERFCOUNTER3_SELECT(perf_sel) \
+     ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT))
+
+#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \
+     ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \
+     sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sq_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE;
+     } sq_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_select_t f;
+} sq_perfcounter3_select_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_LOW struct
+ */
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER0_LOW_MASK \
+     (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \
+     ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \
+     sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_low_t f;
+} sq_perfcounter0_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER0_HI struct
+ */
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER0_HI_MASK \
+     (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \
+     ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \
+     sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter0_hi_t f;
+} sq_perfcounter0_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_LOW struct
+ */
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER1_LOW_MASK \
+     (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \
+     ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \
+     sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_low_t f;
+} sq_perfcounter1_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER1_HI struct
+ */
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER1_HI_MASK \
+     (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER1_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \
+     ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \
+     sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter1_hi_t f;
+} sq_perfcounter1_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_LOW struct
+ */
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER2_LOW_MASK \
+     (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \
+     ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \
+     sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_low_t f;
+} sq_perfcounter2_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER2_HI struct
+ */
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER2_HI_MASK \
+     (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER2_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \
+     ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \
+     sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter2_hi_t f;
+} sq_perfcounter2_hi_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_LOW struct
+ */
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SQ_PERFCOUNTER3_LOW_MASK \
+     (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_LOW(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \
+     ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \
+     sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_low_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE;
+     } sq_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_low_t f;
+} sq_perfcounter3_low_u;
+
+
+/*
+ * SQ_PERFCOUNTER3_HI struct
+ */
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0
+
+#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SQ_PERFCOUNTER3_HI_MASK \
+     (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK)
+
+#define SQ_PERFCOUNTER3_HI(perf_count) \
+     ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT))
+
+#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \
+     ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \
+     sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sq_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE;
+     } sq_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_perfcounter3_hi_t f;
+} sq_perfcounter3_hi_u;
+
+
+/*
+ * SX_PERFCOUNTER0_SELECT struct
+ */
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define SX_PERFCOUNTER0_SELECT_MASK \
+     (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define SX_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \
+     ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \
+     sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } sx_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } sx_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_select_t f;
+} sx_perfcounter0_select_u;
+
+
+/*
+ * SX_PERFCOUNTER0_LOW struct
+ */
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define SX_PERFCOUNTER0_LOW_MASK \
+     (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \
+     ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \
+     sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_low_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } sx_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_low_t f;
+} sx_perfcounter0_low_u;
+
+
+/*
+ * SX_PERFCOUNTER0_HI struct
+ */
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define SX_PERFCOUNTER0_HI_MASK \
+     (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define SX_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \
+     ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \
+     sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } sx_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sx_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } sx_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sx_perfcounter0_hi_t f;
+} sx_perfcounter0_hi_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_0 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26
+
+#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000
+#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_ALU_0_MASK \
+     (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \
+      SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \
+      SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \
+      SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \
+     ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \
+      (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \
+      (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \
+      (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \
+      (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \
+      (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \
+      (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \
+      (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \
+      (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \
+      (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \
+      (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \
+     ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT)
+#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \
+     sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+     } sq_instruction_alu_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_0_t {
+          unsigned int scalar_opcode                  : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE;
+          unsigned int scalar_clamp                   : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE;
+          unsigned int vector_clamp                   : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE;
+          unsigned int scalar_wrt_msk                 : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE;
+          unsigned int vector_wrt_msk                 : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE;
+          unsigned int export_data                    : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE;
+          unsigned int scalar_dst_rel                 : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE;
+          unsigned int scalar_result                  : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE;
+          unsigned int low_precision_16b_fp           : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE;
+          unsigned int vector_dst_rel                 : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE;
+          unsigned int vector_result                  : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE;
+     } sq_instruction_alu_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_0_t f;
+} sq_instruction_alu_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_1 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030
+#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000
+#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000
+#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000
+#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000
+#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000
+#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_1_MASK \
+     (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \
+      SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \
+      SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \
+      SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK)
+
+#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \
+     ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \
+      (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \
+      (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \
+      (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \
+      (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \
+      (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \
+      (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \
+      (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \
+      (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \
+      (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \
+      (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \
+      (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \
+      (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \
+      (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \
+      (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \
+      (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \
+      (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \
+      (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \
+     ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT)
+#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \
+     sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+     } sq_instruction_alu_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_1_t {
+          unsigned int const_0_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE;
+          unsigned int const_1_rel_abs                : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE;
+          unsigned int relative_addr                  : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE;
+          unsigned int src_a_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE;
+          unsigned int src_b_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE;
+          unsigned int src_c_arg_mod                  : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE;
+          unsigned int src_a_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE;
+          unsigned int src_a_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE;
+          unsigned int src_a_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE;
+          unsigned int src_a_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE;
+          unsigned int src_b_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE;
+          unsigned int src_b_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE;
+          unsigned int src_b_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE;
+          unsigned int src_b_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE;
+          unsigned int src_c_swizzle_a                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE;
+          unsigned int src_c_swizzle_b                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE;
+          unsigned int src_c_swizzle_g                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE;
+          unsigned int src_c_swizzle_r                : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE;
+     } sq_instruction_alu_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_1_t f;
+} sq_instruction_alu_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_ALU_2 struct
+ */
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31
+
+#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080
+#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000
+#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000
+#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000
+#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000
+#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000
+#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000
+#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000
+
+#define SQ_INSTRUCTION_ALU_2_MASK \
+     (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \
+      SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \
+      SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK)
+
+#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \
+     ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \
+      (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \
+      (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \
+      (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \
+      (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \
+      (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \
+      (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \
+      (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \
+      (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \
+      (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \
+      (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \
+      (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \
+      (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \
+     ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT)
+#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \
+     sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+     } sq_instruction_alu_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_alu_2_t {
+          unsigned int src_a_sel                      : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE;
+          unsigned int src_b_sel                      : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE;
+          unsigned int src_c_sel                      : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE;
+          unsigned int vector_opcode                  : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE;
+          unsigned int reg_abs_mod_a                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE;
+          unsigned int reg_select_a                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE;
+          unsigned int src_a_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_b                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE;
+          unsigned int reg_select_b                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE;
+          unsigned int src_b_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE;
+          unsigned int reg_abs_mod_c                  : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE;
+          unsigned int reg_select_c                   : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE;
+          unsigned int src_c_reg_ptr                  : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE;
+     } sq_instruction_alu_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_alu_2_t f;
+} sq_instruction_alu_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff
+#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00
+#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000
+#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000
+#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_0_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \
+     ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \
+      (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \
+     ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \
+     sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_0_t {
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE;
+     } sq_instruction_cf_exec_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_0_t f;
+} sq_instruction_cf_exec_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31
+
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000
+#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000
+#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000
+#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000
+
+#define SQ_INSTRUCTION_CF_EXEC_1_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \
+     ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \
+      (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \
+      (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \
+     ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \
+     sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_1_t {
+          unsigned int yield                          : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE;
+          unsigned int count                          : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE;
+     } sq_instruction_cf_exec_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_1_t f;
+} sq_instruction_cf_exec_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_EXEC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000
+#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_EXEC_2_MASK \
+     (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \
+     ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \
+      (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \
+      (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \
+      (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \
+      (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \
+      (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \
+      (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \
+      (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \
+      (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \
+      (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \
+      (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \
+      (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \
+      (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \
+      (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \
+      (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \
+      (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \
+      (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \
+      (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \
+     ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \
+     sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_exec_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE;
+          unsigned int inst_vc_5                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE;
+          unsigned int inst_vc_4                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE;
+          unsigned int inst_vc_3                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE;
+          unsigned int inst_vc_2                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE;
+          unsigned int inst_vc_1                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE;
+          unsigned int inst_vc_0                      : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE;
+          unsigned int inst_serial_5                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE;
+          unsigned int inst_type_5                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE;
+          unsigned int inst_serial_4                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE;
+          unsigned int inst_type_4                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE;
+          unsigned int inst_serial_3                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE;
+          unsigned int inst_type_3                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE;
+          unsigned int inst_serial_2                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE;
+          unsigned int inst_type_2                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE;
+          unsigned int inst_serial_1                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE;
+          unsigned int inst_type_1                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE;
+          unsigned int inst_serial_0                  : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE;
+          unsigned int inst_type_0                    : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE;
+     } sq_instruction_cf_exec_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_exec_2_t f;
+} sq_instruction_cf_exec_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21
+
+#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00
+#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000
+#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000
+
+#define SQ_INSTRUCTION_CF_LOOP_0_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \
+      (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \
+     ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \
+     sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE;
+     } sq_instruction_cf_loop_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_0_t f;
+} sq_instruction_cf_loop_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26
+
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000
+
+#define SQ_INSTRUCTION_CF_LOOP_1_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \
+     ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \
+     sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_loop_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_1_t f;
+} sq_instruction_cf_loop_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_LOOP_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f
+#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0
+#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_LOOP_2_MASK \
+     (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \
+     ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \
+     ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \
+     sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_loop_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE;
+          unsigned int loop_id                        : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE;
+     } sq_instruction_cf_loop_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_loop_2_t f;
+} sq_instruction_cf_loop_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \
+     ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \
+      (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \
+      (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \
+     ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_0_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE;
+          unsigned int predicated_jmp                 : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE;
+     } sq_instruction_cf_jmp_call_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_0_t f;
+} sq_instruction_cf_jmp_call_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \
+      (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \
+      (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \
+      (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \
+     ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \
+     sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_1_t {
+          unsigned int reserved_2                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE;
+          unsigned int force_call                     : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE;
+          unsigned int address                        : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_jmp_call_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_1_t f;
+} sq_instruction_cf_jmp_call_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_JMP_CALL_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \
+     (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \
+      SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \
+      (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \
+      (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \
+      (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \
+      (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \
+     ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \
+     sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_jmp_call_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE;
+          unsigned int address_mode                   : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE;
+          unsigned int condition                      : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE;
+          unsigned int bool_addr                      : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE;
+          unsigned int direction                      : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE;
+     } sq_instruction_cf_jmp_call_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_jmp_call_2_t f;
+} sq_instruction_cf_jmp_call_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_0 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f
+#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \
+     ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \
+      (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \
+     ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \
+     sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_0_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE;
+     } sq_instruction_cf_alloc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_0_t f;
+} sq_instruction_cf_alloc_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_1 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff
+#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100
+#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600
+#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800
+#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000
+#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000
+#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \
+     ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \
+      (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \
+      (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \
+     ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \
+     sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_1_t {
+          unsigned int reserved_1                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE;
+          unsigned int size                           : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE;
+          unsigned int reserved_0                     : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE;
+     } sq_instruction_cf_alloc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_1_t f;
+} sq_instruction_cf_alloc_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_CF_ALLOC_2 struct
+ */
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff
+#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000
+#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \
+     (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \
+      SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \
+     ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \
+      (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \
+      (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \
+      (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \
+      (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT))
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \
+     ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT)
+#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \
+     sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_cf_alloc_2_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE;
+          unsigned int alloc_mode                     : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE;
+          unsigned int buffer_select                  : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE;
+          unsigned int no_serial                      : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE;
+          unsigned int reserved                       : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE;
+     } sq_instruction_cf_alloc_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_cf_alloc_2_t f;
+} sq_instruction_cf_alloc_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30
+
+#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000
+#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000
+#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_TFETCH_0_MASK \
+     (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \
+     ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \
+      (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \
+      (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \
+      (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \
+      (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \
+      (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \
+     ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \
+     sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_0_t {
+          unsigned int src_sel_z                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE;
+          unsigned int src_sel_y                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE;
+          unsigned int src_sel_x                      : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE;
+          unsigned int tx_coord_denorm                : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE;
+          unsigned int fetch_valid_only               : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE;
+     } sq_instruction_tfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_0_t f;
+} sq_instruction_tfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000
+#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000
+#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000
+#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000
+#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000
+#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000
+#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000
+#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_1_MASK \
+     (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \
+      SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \
+      (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \
+      (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \
+      (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \
+      (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \
+      (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \
+      (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \
+      (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \
+      (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \
+      (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \
+     ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \
+     sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE;
+          unsigned int use_reg_lod                    : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE;
+          unsigned int use_comp_lod                   : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE;
+          unsigned int vol_min_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE;
+          unsigned int vol_mag_filter                 : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE;
+          unsigned int arbitrary_filter               : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE;
+          unsigned int aniso_filter                   : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE;
+          unsigned int mip_filter                     : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE;
+          unsigned int min_filter                     : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE;
+          unsigned int mag_filter                     : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_tfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_1_t f;
+} sq_instruction_tfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_TFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001
+#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002
+#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc
+#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000
+#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000
+#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_TFETCH_2_MASK \
+     (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \
+      SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \
+     ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \
+      (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \
+      (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \
+      (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \
+      (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \
+      (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \
+      (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \
+     ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT)
+#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \
+     sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_tfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int offset_z                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE;
+          unsigned int offset_y                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE;
+          unsigned int unused                         : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE;
+          unsigned int lod_bias                       : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE;
+          unsigned int sample_location                : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE;
+          unsigned int use_reg_gradients              : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE;
+     } sq_instruction_tfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_tfetch_2_t f;
+} sq_instruction_tfetch_2_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_0 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30
+
+#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0
+#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000
+#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000
+#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000
+#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000
+#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000
+
+#define SQ_INSTRUCTION_VFETCH_0_MASK \
+     (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \
+      SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \
+     ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \
+      (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \
+      (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \
+      (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \
+      (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \
+      (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \
+      (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \
+      (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \
+      (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \
+     ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \
+     sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_0_t {
+          unsigned int src_sel                        : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE;
+          unsigned int                                : 3;
+          unsigned int const_index_sel                : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE;
+          unsigned int const_index                    : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE;
+          unsigned int must_be_one                    : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE;
+          unsigned int dst_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE;
+          unsigned int dst_gpr                        : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE;
+          unsigned int src_gpr_am                     : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE;
+          unsigned int src_gpr                        : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE;
+          unsigned int opcode                         : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE;
+     } sq_instruction_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_0_t f;
+} sq_instruction_vfetch_0_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_1 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0
+#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00
+#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000
+#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000
+#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000
+#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000
+#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000
+#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_1_MASK \
+     (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \
+      SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \
+     ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \
+      (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \
+      (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \
+      (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \
+      (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \
+      (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \
+      (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \
+      (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \
+      (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \
+      (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \
+     ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \
+     sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_1_t {
+          unsigned int pred_select                    : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE;
+          unsigned int                                : 1;
+          unsigned int exp_adjust_all                 : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE;
+          unsigned int                                : 1;
+          unsigned int data_format                    : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE;
+          unsigned int                                : 1;
+          unsigned int signed_rf_mode_all             : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE;
+          unsigned int num_format_all                 : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE;
+          unsigned int format_comp_all                : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE;
+          unsigned int dst_sel_w                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE;
+          unsigned int dst_sel_z                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE;
+          unsigned int dst_sel_y                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE;
+          unsigned int dst_sel_x                      : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE;
+     } sq_instruction_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_1_t f;
+} sq_instruction_vfetch_1_u;
+
+
+/*
+ * SQ_INSTRUCTION_VFETCH_2 struct
+ */
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31
+
+#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff
+#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000
+#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000
+
+#define SQ_INSTRUCTION_VFETCH_2_MASK \
+     (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \
+      SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK)
+
+#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \
+     ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \
+      (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \
+      (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT))
+
+#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \
+     ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT)
+#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \
+     sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+          unsigned int                                : 8;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 7;
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_instruction_vfetch_2_t {
+          unsigned int pred_condition                 : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE;
+          unsigned int                                : 7;
+          unsigned int offset                         : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE;
+          unsigned int                                : 8;
+          unsigned int stride                         : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE;
+     } sq_instruction_vfetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_instruction_vfetch_2_t f;
+} sq_instruction_vfetch_2_u;
+
+
+/*
+ * SQ_CONSTANT_0 struct
+ */
+
+#define SQ_CONSTANT_0_RED_SIZE         32
+
+#define SQ_CONSTANT_0_RED_SHIFT        0
+
+#define SQ_CONSTANT_0_RED_MASK         0xffffffff
+
+#define SQ_CONSTANT_0_MASK \
+     (SQ_CONSTANT_0_RED_MASK)
+
+#define SQ_CONSTANT_0(red) \
+     ((red << SQ_CONSTANT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \
+     ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \
+     sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_0_t {
+          unsigned int red                            : SQ_CONSTANT_0_RED_SIZE;
+     } sq_constant_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_0_t f;
+} sq_constant_0_u;
+
+
+/*
+ * SQ_CONSTANT_1 struct
+ */
+
+#define SQ_CONSTANT_1_GREEN_SIZE       32
+
+#define SQ_CONSTANT_1_GREEN_SHIFT      0
+
+#define SQ_CONSTANT_1_GREEN_MASK       0xffffffff
+
+#define SQ_CONSTANT_1_MASK \
+     (SQ_CONSTANT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_1(green) \
+     ((green << SQ_CONSTANT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \
+     ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \
+     sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_1_t {
+          unsigned int green                          : SQ_CONSTANT_1_GREEN_SIZE;
+     } sq_constant_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_1_t f;
+} sq_constant_1_u;
+
+
+/*
+ * SQ_CONSTANT_2 struct
+ */
+
+#define SQ_CONSTANT_2_BLUE_SIZE        32
+
+#define SQ_CONSTANT_2_BLUE_SHIFT       0
+
+#define SQ_CONSTANT_2_BLUE_MASK        0xffffffff
+
+#define SQ_CONSTANT_2_MASK \
+     (SQ_CONSTANT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_2(blue) \
+     ((blue << SQ_CONSTANT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \
+     ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \
+     sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_2_t {
+          unsigned int blue                           : SQ_CONSTANT_2_BLUE_SIZE;
+     } sq_constant_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_2_t f;
+} sq_constant_2_u;
+
+
+/*
+ * SQ_CONSTANT_3 struct
+ */
+
+#define SQ_CONSTANT_3_ALPHA_SIZE       32
+
+#define SQ_CONSTANT_3_ALPHA_SHIFT      0
+
+#define SQ_CONSTANT_3_ALPHA_MASK       0xffffffff
+
+#define SQ_CONSTANT_3_MASK \
+     (SQ_CONSTANT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_3(alpha) \
+     ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \
+     ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \
+     sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_3_ALPHA_SIZE;
+     } sq_constant_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_3_t f;
+} sq_constant_3_u;
+
+
+/*
+ * SQ_FETCH_0 struct
+ */
+
+#define SQ_FETCH_0_VALUE_SIZE          32
+
+#define SQ_FETCH_0_VALUE_SHIFT         0
+
+#define SQ_FETCH_0_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_0_MASK \
+     (SQ_FETCH_0_VALUE_MASK)
+
+#define SQ_FETCH_0(value) \
+     ((value << SQ_FETCH_0_VALUE_SHIFT))
+
+#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \
+     ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT)
+
+#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \
+     sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_0_t {
+          unsigned int value                          : SQ_FETCH_0_VALUE_SIZE;
+     } sq_fetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_0_t f;
+} sq_fetch_0_u;
+
+
+/*
+ * SQ_FETCH_1 struct
+ */
+
+#define SQ_FETCH_1_VALUE_SIZE          32
+
+#define SQ_FETCH_1_VALUE_SHIFT         0
+
+#define SQ_FETCH_1_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_1_MASK \
+     (SQ_FETCH_1_VALUE_MASK)
+
+#define SQ_FETCH_1(value) \
+     ((value << SQ_FETCH_1_VALUE_SHIFT))
+
+#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \
+     ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT)
+
+#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \
+     sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_1_t {
+          unsigned int value                          : SQ_FETCH_1_VALUE_SIZE;
+     } sq_fetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_1_t f;
+} sq_fetch_1_u;
+
+
+/*
+ * SQ_FETCH_2 struct
+ */
+
+#define SQ_FETCH_2_VALUE_SIZE          32
+
+#define SQ_FETCH_2_VALUE_SHIFT         0
+
+#define SQ_FETCH_2_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_2_MASK \
+     (SQ_FETCH_2_VALUE_MASK)
+
+#define SQ_FETCH_2(value) \
+     ((value << SQ_FETCH_2_VALUE_SHIFT))
+
+#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \
+     ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT)
+
+#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \
+     sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_2_t {
+          unsigned int value                          : SQ_FETCH_2_VALUE_SIZE;
+     } sq_fetch_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_2_t f;
+} sq_fetch_2_u;
+
+
+/*
+ * SQ_FETCH_3 struct
+ */
+
+#define SQ_FETCH_3_VALUE_SIZE          32
+
+#define SQ_FETCH_3_VALUE_SHIFT         0
+
+#define SQ_FETCH_3_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_3_MASK \
+     (SQ_FETCH_3_VALUE_MASK)
+
+#define SQ_FETCH_3(value) \
+     ((value << SQ_FETCH_3_VALUE_SHIFT))
+
+#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \
+     ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT)
+
+#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \
+     sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_3_t {
+          unsigned int value                          : SQ_FETCH_3_VALUE_SIZE;
+     } sq_fetch_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_3_t f;
+} sq_fetch_3_u;
+
+
+/*
+ * SQ_FETCH_4 struct
+ */
+
+#define SQ_FETCH_4_VALUE_SIZE          32
+
+#define SQ_FETCH_4_VALUE_SHIFT         0
+
+#define SQ_FETCH_4_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_4_MASK \
+     (SQ_FETCH_4_VALUE_MASK)
+
+#define SQ_FETCH_4(value) \
+     ((value << SQ_FETCH_4_VALUE_SHIFT))
+
+#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \
+     ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT)
+
+#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \
+     sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_4_t {
+          unsigned int value                          : SQ_FETCH_4_VALUE_SIZE;
+     } sq_fetch_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_4_t f;
+} sq_fetch_4_u;
+
+
+/*
+ * SQ_FETCH_5 struct
+ */
+
+#define SQ_FETCH_5_VALUE_SIZE          32
+
+#define SQ_FETCH_5_VALUE_SHIFT         0
+
+#define SQ_FETCH_5_VALUE_MASK          0xffffffff
+
+#define SQ_FETCH_5_MASK \
+     (SQ_FETCH_5_VALUE_MASK)
+
+#define SQ_FETCH_5(value) \
+     ((value << SQ_FETCH_5_VALUE_SHIFT))
+
+#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \
+     ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT)
+
+#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \
+     sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_5_t {
+          unsigned int value                          : SQ_FETCH_5_VALUE_SIZE;
+     } sq_fetch_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_5_t f;
+} sq_fetch_5_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_0 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0
+#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001
+#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002
+#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_0_MASK \
+     (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \
+      SQ_CONSTANT_VFETCH_0_STATE_MASK | \
+      SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \
+     ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \
+      (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \
+      (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \
+     ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT)
+#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \
+     sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_0_t {
+          unsigned int base_address                   : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE;
+          unsigned int state                          : SQ_CONSTANT_VFETCH_0_STATE_SIZE;
+          unsigned int type                           : SQ_CONSTANT_VFETCH_0_TYPE_SIZE;
+     } sq_constant_vfetch_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_0_t f;
+} sq_constant_vfetch_0_u;
+
+
+/*
+ * SQ_CONSTANT_VFETCH_1 struct
+ */
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2
+
+#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003
+#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc
+
+#define SQ_CONSTANT_VFETCH_1_MASK \
+     (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \
+      SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK)
+
+#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \
+     ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \
+      (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT))
+
+#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \
+     ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT)
+#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \
+     sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_vfetch_1_t {
+          unsigned int limit_address                  : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE;
+          unsigned int endian_swap                    : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE;
+     } sq_constant_vfetch_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_vfetch_1_t f;
+} sq_constant_vfetch_1_u;
+
+
+/*
+ * SQ_CONSTANT_T2 struct
+ */
+
+#define SQ_CONSTANT_T2_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T2_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T2_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T2_MASK \
+     (SQ_CONSTANT_T2_VALUE_MASK)
+
+#define SQ_CONSTANT_T2(value) \
+     ((value << SQ_CONSTANT_T2_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \
+     ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \
+     sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t2_t {
+          unsigned int value                          : SQ_CONSTANT_T2_VALUE_SIZE;
+     } sq_constant_t2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t2_t f;
+} sq_constant_t2_u;
+
+
+/*
+ * SQ_CONSTANT_T3 struct
+ */
+
+#define SQ_CONSTANT_T3_VALUE_SIZE      32
+
+#define SQ_CONSTANT_T3_VALUE_SHIFT     0
+
+#define SQ_CONSTANT_T3_VALUE_MASK      0xffffffff
+
+#define SQ_CONSTANT_T3_MASK \
+     (SQ_CONSTANT_T3_VALUE_MASK)
+
+#define SQ_CONSTANT_T3(value) \
+     ((value << SQ_CONSTANT_T3_VALUE_SHIFT))
+
+#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \
+     ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \
+     sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_t3_t {
+          unsigned int value                          : SQ_CONSTANT_T3_VALUE_SIZE;
+     } sq_constant_t3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_t3_t f;
+} sq_constant_t3_u;
+
+
+/*
+ * SQ_CF_BOOLEANS struct
+ */
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_BOOLEANS_MASK \
+     (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \
+     ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \
+     sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_booleans_t f;
+} sq_cf_booleans_u;
+
+
+/*
+ * SQ_CF_LOOP struct
+ */
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_START_SIZE  8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE   8
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT  16
+
+#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK  0x000000ff
+#define SQ_CF_LOOP_CF_LOOP_START_MASK  0x0000ff00
+#define SQ_CF_LOOP_CF_LOOP_STEP_MASK   0x00ff0000
+
+#define SQ_CF_LOOP_MASK \
+     (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \
+     ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \
+     sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_loop_t f;
+} sq_cf_loop_u;
+
+
+/*
+ * SQ_CONSTANT_RT_0 struct
+ */
+
+#define SQ_CONSTANT_RT_0_RED_SIZE      32
+
+#define SQ_CONSTANT_RT_0_RED_SHIFT     0
+
+#define SQ_CONSTANT_RT_0_RED_MASK      0xffffffff
+
+#define SQ_CONSTANT_RT_0_MASK \
+     (SQ_CONSTANT_RT_0_RED_MASK)
+
+#define SQ_CONSTANT_RT_0(red) \
+     ((red << SQ_CONSTANT_RT_0_RED_SHIFT))
+
+#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \
+     ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \
+     sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_0_t {
+          unsigned int red                            : SQ_CONSTANT_RT_0_RED_SIZE;
+     } sq_constant_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_0_t f;
+} sq_constant_rt_0_u;
+
+
+/*
+ * SQ_CONSTANT_RT_1 struct
+ */
+
+#define SQ_CONSTANT_RT_1_GREEN_SIZE    32
+
+#define SQ_CONSTANT_RT_1_GREEN_SHIFT   0
+
+#define SQ_CONSTANT_RT_1_GREEN_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_1_MASK \
+     (SQ_CONSTANT_RT_1_GREEN_MASK)
+
+#define SQ_CONSTANT_RT_1(green) \
+     ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT))
+
+#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \
+     ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \
+     sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_1_t {
+          unsigned int green                          : SQ_CONSTANT_RT_1_GREEN_SIZE;
+     } sq_constant_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_1_t f;
+} sq_constant_rt_1_u;
+
+
+/*
+ * SQ_CONSTANT_RT_2 struct
+ */
+
+#define SQ_CONSTANT_RT_2_BLUE_SIZE     32
+
+#define SQ_CONSTANT_RT_2_BLUE_SHIFT    0
+
+#define SQ_CONSTANT_RT_2_BLUE_MASK     0xffffffff
+
+#define SQ_CONSTANT_RT_2_MASK \
+     (SQ_CONSTANT_RT_2_BLUE_MASK)
+
+#define SQ_CONSTANT_RT_2(blue) \
+     ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT))
+
+#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \
+     ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \
+     sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_2_t {
+          unsigned int blue                           : SQ_CONSTANT_RT_2_BLUE_SIZE;
+     } sq_constant_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_2_t f;
+} sq_constant_rt_2_u;
+
+
+/*
+ * SQ_CONSTANT_RT_3 struct
+ */
+
+#define SQ_CONSTANT_RT_3_ALPHA_SIZE    32
+
+#define SQ_CONSTANT_RT_3_ALPHA_SHIFT   0
+
+#define SQ_CONSTANT_RT_3_ALPHA_MASK    0xffffffff
+
+#define SQ_CONSTANT_RT_3_MASK \
+     (SQ_CONSTANT_RT_3_ALPHA_MASK)
+
+#define SQ_CONSTANT_RT_3(alpha) \
+     ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT))
+
+#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \
+     ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \
+     sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_constant_rt_3_t {
+          unsigned int alpha                          : SQ_CONSTANT_RT_3_ALPHA_SIZE;
+     } sq_constant_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_constant_rt_3_t f;
+} sq_constant_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_0 struct
+ */
+
+#define SQ_FETCH_RT_0_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_0_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_0_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_0_MASK \
+     (SQ_FETCH_RT_0_VALUE_MASK)
+
+#define SQ_FETCH_RT_0(value) \
+     ((value << SQ_FETCH_RT_0_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \
+     ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \
+     sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_0_t {
+          unsigned int value                          : SQ_FETCH_RT_0_VALUE_SIZE;
+     } sq_fetch_rt_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_0_t f;
+} sq_fetch_rt_0_u;
+
+
+/*
+ * SQ_FETCH_RT_1 struct
+ */
+
+#define SQ_FETCH_RT_1_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_1_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_1_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_1_MASK \
+     (SQ_FETCH_RT_1_VALUE_MASK)
+
+#define SQ_FETCH_RT_1(value) \
+     ((value << SQ_FETCH_RT_1_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \
+     ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \
+     sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_1_t {
+          unsigned int value                          : SQ_FETCH_RT_1_VALUE_SIZE;
+     } sq_fetch_rt_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_1_t f;
+} sq_fetch_rt_1_u;
+
+
+/*
+ * SQ_FETCH_RT_2 struct
+ */
+
+#define SQ_FETCH_RT_2_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_2_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_2_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_2_MASK \
+     (SQ_FETCH_RT_2_VALUE_MASK)
+
+#define SQ_FETCH_RT_2(value) \
+     ((value << SQ_FETCH_RT_2_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \
+     ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \
+     sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_2_t {
+          unsigned int value                          : SQ_FETCH_RT_2_VALUE_SIZE;
+     } sq_fetch_rt_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_2_t f;
+} sq_fetch_rt_2_u;
+
+
+/*
+ * SQ_FETCH_RT_3 struct
+ */
+
+#define SQ_FETCH_RT_3_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_3_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_3_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_3_MASK \
+     (SQ_FETCH_RT_3_VALUE_MASK)
+
+#define SQ_FETCH_RT_3(value) \
+     ((value << SQ_FETCH_RT_3_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \
+     ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \
+     sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_3_t {
+          unsigned int value                          : SQ_FETCH_RT_3_VALUE_SIZE;
+     } sq_fetch_rt_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_3_t f;
+} sq_fetch_rt_3_u;
+
+
+/*
+ * SQ_FETCH_RT_4 struct
+ */
+
+#define SQ_FETCH_RT_4_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_4_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_4_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_4_MASK \
+     (SQ_FETCH_RT_4_VALUE_MASK)
+
+#define SQ_FETCH_RT_4(value) \
+     ((value << SQ_FETCH_RT_4_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \
+     ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \
+     sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_4_t {
+          unsigned int value                          : SQ_FETCH_RT_4_VALUE_SIZE;
+     } sq_fetch_rt_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_4_t f;
+} sq_fetch_rt_4_u;
+
+
+/*
+ * SQ_FETCH_RT_5 struct
+ */
+
+#define SQ_FETCH_RT_5_VALUE_SIZE       32
+
+#define SQ_FETCH_RT_5_VALUE_SHIFT      0
+
+#define SQ_FETCH_RT_5_VALUE_MASK       0xffffffff
+
+#define SQ_FETCH_RT_5_MASK \
+     (SQ_FETCH_RT_5_VALUE_MASK)
+
+#define SQ_FETCH_RT_5(value) \
+     ((value << SQ_FETCH_RT_5_VALUE_SHIFT))
+
+#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \
+     ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \
+     sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_fetch_rt_5_t {
+          unsigned int value                          : SQ_FETCH_RT_5_VALUE_SIZE;
+     } sq_fetch_rt_5_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_fetch_rt_5_t f;
+} sq_fetch_rt_5_u;
+
+
+/*
+ * SQ_CF_RT_BOOLEANS struct
+ */
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24
+
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000
+#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000
+
+#define SQ_CF_RT_BOOLEANS_MASK \
+     (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \
+      SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK)
+
+#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \
+     ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \
+      (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \
+      (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \
+      (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT))
+
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \
+     ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT)
+#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \
+     sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_booleans_t {
+          unsigned int cf_booleans_3                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE;
+          unsigned int cf_booleans_2                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE;
+          unsigned int cf_booleans_1                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE;
+          unsigned int cf_booleans_0                  : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE;
+     } sq_cf_rt_booleans_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_booleans_t f;
+} sq_cf_rt_booleans_u;
+
+
+/*
+ * SQ_CF_RT_LOOP struct
+ */
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0
+#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16
+
+#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff
+#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00
+#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000
+
+#define SQ_CF_RT_LOOP_MASK \
+     (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \
+      SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK)
+
+#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \
+     ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \
+      (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \
+      (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT))
+
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \
+     ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT)
+#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \
+     sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int                                : 8;
+     } sq_cf_rt_loop_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rt_loop_t {
+          unsigned int                                : 8;
+          unsigned int cf_loop_step                   : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE;
+          unsigned int cf_loop_start                  : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE;
+          unsigned int cf_loop_count                  : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE;
+     } sq_cf_rt_loop_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rt_loop_t f;
+} sq_cf_rt_loop_u;
+
+
+/*
+ * SQ_VS_PROGRAM struct
+ */
+
+#define SQ_VS_PROGRAM_BASE_SIZE        12
+#define SQ_VS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_VS_PROGRAM_BASE_SHIFT       0
+#define SQ_VS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_VS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_VS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_VS_PROGRAM_MASK \
+     (SQ_VS_PROGRAM_BASE_MASK | \
+      SQ_VS_PROGRAM_SIZE_MASK)
+
+#define SQ_VS_PROGRAM(base, size) \
+     ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_VS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \
+     ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT)
+#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \
+     sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_vs_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_VS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_VS_PROGRAM_BASE_SIZE;
+     } sq_vs_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_program_t f;
+} sq_vs_program_u;
+
+
+/*
+ * SQ_PS_PROGRAM struct
+ */
+
+#define SQ_PS_PROGRAM_BASE_SIZE        12
+#define SQ_PS_PROGRAM_SIZE_SIZE        12
+
+#define SQ_PS_PROGRAM_BASE_SHIFT       0
+#define SQ_PS_PROGRAM_SIZE_SHIFT       12
+
+#define SQ_PS_PROGRAM_BASE_MASK        0x00000fff
+#define SQ_PS_PROGRAM_SIZE_MASK        0x00fff000
+
+#define SQ_PS_PROGRAM_MASK \
+     (SQ_PS_PROGRAM_BASE_MASK | \
+      SQ_PS_PROGRAM_SIZE_MASK)
+
+#define SQ_PS_PROGRAM(base, size) \
+     ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \
+      (size << SQ_PS_PROGRAM_SIZE_SHIFT))
+
+#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \
+     ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT)
+#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \
+     sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int                                : 8;
+     } sq_ps_program_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_program_t {
+          unsigned int                                : 8;
+          unsigned int size                           : SQ_PS_PROGRAM_SIZE_SIZE;
+          unsigned int base                           : SQ_PS_PROGRAM_BASE_SIZE;
+     } sq_ps_program_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_program_t f;
+} sq_ps_program_u;
+
+
+/*
+ * SQ_CF_PROGRAM_SIZE struct
+ */
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12
+
+#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff
+#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000
+
+#define SQ_CF_PROGRAM_SIZE_MASK \
+     (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \
+      SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK)
+
+#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \
+     ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \
+      (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT))
+
+#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \
+     ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT)
+#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \
+     sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 9;
+     } sq_cf_program_size_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_program_size_t {
+          unsigned int                                : 9;
+          unsigned int ps_cf_size                     : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE;
+          unsigned int                                : 1;
+          unsigned int vs_cf_size                     : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE;
+     } sq_cf_program_size_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_program_size_t f;
+} sq_cf_program_size_u;
+
+
+/*
+ * SQ_INTERPOLATOR_CNTL struct
+ */
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16
+
+#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff
+#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000
+
+#define SQ_INTERPOLATOR_CNTL_MASK \
+     (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \
+      SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK)
+
+#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \
+     ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \
+      (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT))
+
+#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \
+     ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT)
+#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \
+     sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+     } sq_interpolator_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_interpolator_cntl_t {
+          unsigned int sampling_pattern               : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE;
+          unsigned int param_shade                    : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE;
+     } sq_interpolator_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_interpolator_cntl_t f;
+} sq_interpolator_cntl_u;
+
+
+/*
+ * SQ_PROGRAM_CNTL struct
+ */
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17
+#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31
+
+#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f
+#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00
+#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000
+#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000
+#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000
+#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000
+#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000
+#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000
+
+#define SQ_PROGRAM_CNTL_MASK \
+     (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \
+      SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \
+      SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \
+      SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \
+      SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK)
+
+#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \
+     ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \
+      (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \
+      (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \
+      (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \
+      (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \
+      (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \
+      (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \
+      (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \
+      (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \
+      (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT))
+
+#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \
+     ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT)
+#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \
+     sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+     } sq_program_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_program_cntl_t {
+          unsigned int gen_index_vtx                  : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE;
+          unsigned int ps_export_mode                 : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_mode                 : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE;
+          unsigned int vs_export_count                : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE;
+          unsigned int gen_index_pix                  : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE;
+          unsigned int param_gen                      : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE;
+          unsigned int ps_resource                    : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE;
+          unsigned int vs_resource                    : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE;
+          unsigned int                                : 2;
+          unsigned int ps_num_reg                     : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE;
+          unsigned int                                : 2;
+          unsigned int vs_num_reg                     : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE;
+     } sq_program_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_program_cntl_t f;
+} sq_program_cntl_u;
+
+
+/*
+ * SQ_WRAPPING_0 struct
+ */
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0
+#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4
+#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8
+#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12
+#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16
+#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20
+#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24
+#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28
+
+#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f
+#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0
+#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00
+#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000
+#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000
+#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000
+#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000
+#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000
+
+#define SQ_WRAPPING_0_MASK \
+     (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \
+      SQ_WRAPPING_0_PARAM_WRAP_7_MASK)
+
+#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \
+     ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \
+      (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \
+      (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \
+      (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \
+      (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \
+      (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \
+      (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \
+      (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT))
+
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \
+     ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT)
+#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \
+     sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+     } sq_wrapping_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_0_t {
+          unsigned int param_wrap_7                   : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE;
+          unsigned int param_wrap_6                   : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE;
+          unsigned int param_wrap_5                   : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE;
+          unsigned int param_wrap_4                   : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE;
+          unsigned int param_wrap_3                   : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE;
+          unsigned int param_wrap_2                   : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE;
+          unsigned int param_wrap_1                   : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE;
+          unsigned int param_wrap_0                   : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE;
+     } sq_wrapping_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_0_t f;
+} sq_wrapping_0_u;
+
+
+/*
+ * SQ_WRAPPING_1 struct
+ */
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0
+#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4
+#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8
+#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12
+#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16
+#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20
+#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24
+#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28
+
+#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f
+#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0
+#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00
+#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000
+#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000
+#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000
+#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000
+#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000
+
+#define SQ_WRAPPING_1_MASK \
+     (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \
+      SQ_WRAPPING_1_PARAM_WRAP_15_MASK)
+
+#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \
+     ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \
+      (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \
+      (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \
+      (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \
+      (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \
+      (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \
+      (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \
+      (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT))
+
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \
+     ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT)
+#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \
+     sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+     } sq_wrapping_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_wrapping_1_t {
+          unsigned int param_wrap_15                  : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE;
+          unsigned int param_wrap_14                  : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE;
+          unsigned int param_wrap_13                  : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE;
+          unsigned int param_wrap_12                  : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE;
+          unsigned int param_wrap_11                  : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE;
+          unsigned int param_wrap_10                  : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE;
+          unsigned int param_wrap_9                   : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE;
+          unsigned int param_wrap_8                   : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE;
+     } sq_wrapping_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_wrapping_1_t f;
+} sq_wrapping_1_u;
+
+
+/*
+ * SQ_VS_CONST struct
+ */
+
+#define SQ_VS_CONST_BASE_SIZE          9
+#define SQ_VS_CONST_SIZE_SIZE          9
+
+#define SQ_VS_CONST_BASE_SHIFT         0
+#define SQ_VS_CONST_SIZE_SHIFT         12
+
+#define SQ_VS_CONST_BASE_MASK          0x000001ff
+#define SQ_VS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_VS_CONST_MASK \
+     (SQ_VS_CONST_BASE_MASK | \
+      SQ_VS_CONST_SIZE_MASK)
+
+#define SQ_VS_CONST(base, size) \
+     ((base << SQ_VS_CONST_BASE_SHIFT) | \
+      (size << SQ_VS_CONST_SIZE_SHIFT))
+
+#define SQ_VS_CONST_GET_BASE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \
+     ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT)
+
+#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT)
+#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \
+     sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_vs_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_vs_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_VS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_VS_CONST_BASE_SIZE;
+     } sq_vs_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_vs_const_t f;
+} sq_vs_const_u;
+
+
+/*
+ * SQ_PS_CONST struct
+ */
+
+#define SQ_PS_CONST_BASE_SIZE          9
+#define SQ_PS_CONST_SIZE_SIZE          9
+
+#define SQ_PS_CONST_BASE_SHIFT         0
+#define SQ_PS_CONST_SIZE_SHIFT         12
+
+#define SQ_PS_CONST_BASE_MASK          0x000001ff
+#define SQ_PS_CONST_SIZE_MASK          0x001ff000
+
+#define SQ_PS_CONST_MASK \
+     (SQ_PS_CONST_BASE_MASK | \
+      SQ_PS_CONST_SIZE_MASK)
+
+#define SQ_PS_CONST(base, size) \
+     ((base << SQ_PS_CONST_BASE_SHIFT) | \
+      (size << SQ_PS_CONST_SIZE_SHIFT))
+
+#define SQ_PS_CONST_GET_BASE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \
+     ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT)
+
+#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT)
+#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \
+     sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+          unsigned int                                : 3;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 11;
+     } sq_ps_const_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_ps_const_t {
+          unsigned int                                : 11;
+          unsigned int size                           : SQ_PS_CONST_SIZE_SIZE;
+          unsigned int                                : 3;
+          unsigned int base                           : SQ_PS_CONST_BASE_SIZE;
+     } sq_ps_const_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_ps_const_t f;
+} sq_ps_const_u;
+
+
+/*
+ * SQ_CONTEXT_MISC struct
+ */
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18
+
+#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001
+#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002
+#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c
+#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00
+#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000
+#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000
+#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000
+
+#define SQ_CONTEXT_MISC_MASK \
+     (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \
+      SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \
+      SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \
+      SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \
+      SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \
+      SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK)
+
+#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \
+     ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \
+      (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \
+      (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \
+      (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \
+      (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \
+      (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \
+      (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT))
+
+#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \
+     ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT)
+#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT)
+#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT)
+#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT)
+#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \
+     sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int                                : 4;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int                                : 13;
+     } sq_context_misc_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_context_misc_t {
+          unsigned int                                : 13;
+          unsigned int tx_cache_sel                   : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE;
+          unsigned int yeild_optimize                 : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE;
+          unsigned int perfcounter_ref                : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE;
+          unsigned int param_gen_pos                  : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE;
+          unsigned int                                : 4;
+          unsigned int sc_sample_cntl                 : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE;
+          unsigned int sc_output_screen_xy            : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE;
+          unsigned int inst_pred_optimize             : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE;
+     } sq_context_misc_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_context_misc_t f;
+} sq_context_misc_u;
+
+
+/*
+ * SQ_CF_RD_BASE struct
+ */
+
+#define SQ_CF_RD_BASE_RD_BASE_SIZE     3
+
+#define SQ_CF_RD_BASE_RD_BASE_SHIFT    0
+
+#define SQ_CF_RD_BASE_RD_BASE_MASK     0x00000007
+
+#define SQ_CF_RD_BASE_MASK \
+     (SQ_CF_RD_BASE_RD_BASE_MASK)
+
+#define SQ_CF_RD_BASE(rd_base) \
+     ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT))
+
+#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \
+     ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \
+     sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+          unsigned int                                : 29;
+     } sq_cf_rd_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_cf_rd_base_t {
+          unsigned int                                : 29;
+          unsigned int rd_base                        : SQ_CF_RD_BASE_RD_BASE_SIZE;
+     } sq_cf_rd_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_cf_rd_base_t f;
+} sq_cf_rd_base_u;
+
+
+/*
+ * SQ_DEBUG_MISC_0 struct
+ */
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24
+
+#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001
+#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010
+#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00
+#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000
+
+#define SQ_DEBUG_MISC_0_MASK \
+     (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \
+      SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK)
+
+#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \
+     ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \
+      (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \
+      (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \
+      (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT))
+
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \
+     ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT)
+#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \
+     sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+     } sq_debug_misc_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_0_t {
+          unsigned int db_prob_count                  : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE;
+          unsigned int                                : 5;
+          unsigned int db_prob_addr                   : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_break                  : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE;
+          unsigned int                                : 3;
+          unsigned int db_prob_on                     : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE;
+     } sq_debug_misc_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_0_t f;
+} sq_debug_misc_0_u;
+
+
+/*
+ * SQ_DEBUG_MISC_1 struct
+ */
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16
+
+#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001
+#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002
+#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00
+#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000
+
+#define SQ_DEBUG_MISC_1_MASK \
+     (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \
+      SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \
+      SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \
+      SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK)
+
+#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \
+     ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \
+      (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \
+      (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \
+      (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT))
+
+#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \
+     ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT)
+#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \
+     sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int                                : 5;
+     } sq_debug_misc_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _sq_debug_misc_1_t {
+          unsigned int                                : 5;
+          unsigned int db_break_addr                  : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE;
+          unsigned int db_inst_count                  : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE;
+          unsigned int                                : 6;
+          unsigned int db_on_vtx                      : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE;
+          unsigned int db_on_pix                      : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE;
+     } sq_debug_misc_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     sq_debug_misc_1_t f;
+} sq_debug_misc_1_u;
+
+
+#endif
+
+
+#if !defined (_SX_FIDDLE_H)
+#define _SX_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_TP_FIDDLE_H)
+#define _TP_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * TC_CNTL_STATUS struct
+ */
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2
+#define TC_CNTL_STATUS_TC_BUSY_SIZE    1
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18
+#define TC_CNTL_STATUS_TC_BUSY_SHIFT   31
+
+#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001
+#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000
+#define TC_CNTL_STATUS_TC_BUSY_MASK    0x80000000
+
+#define TC_CNTL_STATUS_MASK \
+     (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \
+      TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \
+      TC_CNTL_STATUS_TC_BUSY_MASK)
+
+#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \
+     ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \
+      (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \
+      (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT))
+
+#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \
+     ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT)
+#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \
+     tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+          unsigned int                                : 17;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+     } tc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tc_cntl_status_t {
+          unsigned int tc_busy                        : TC_CNTL_STATUS_TC_BUSY_SIZE;
+          unsigned int                                : 11;
+          unsigned int tc_l2_hit_miss                 : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE;
+          unsigned int                                : 17;
+          unsigned int l2_invalidate                  : TC_CNTL_STATUS_L2_INVALIDATE_SIZE;
+     } tc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tc_cntl_status_t f;
+} tc_cntl_status_u;
+
+
+/*
+ * TCR_CHICKEN struct
+ */
+
+#define TCR_CHICKEN_SPARE_SIZE         32
+
+#define TCR_CHICKEN_SPARE_SHIFT        0
+
+#define TCR_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCR_CHICKEN_MASK \
+     (TCR_CHICKEN_SPARE_MASK)
+
+#define TCR_CHICKEN(spare) \
+     ((spare << TCR_CHICKEN_SPARE_SHIFT))
+
+#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \
+     ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT)
+
+#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \
+     tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_chicken_t {
+          unsigned int spare                          : TCR_CHICKEN_SPARE_SIZE;
+     } tcr_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_chicken_t f;
+} tcr_chicken_u;
+
+
+/*
+ * TCF_CHICKEN struct
+ */
+
+#define TCF_CHICKEN_SPARE_SIZE         32
+
+#define TCF_CHICKEN_SPARE_SHIFT        0
+
+#define TCF_CHICKEN_SPARE_MASK         0xffffffff
+
+#define TCF_CHICKEN_MASK \
+     (TCF_CHICKEN_SPARE_MASK)
+
+#define TCF_CHICKEN(spare) \
+     ((spare << TCF_CHICKEN_SPARE_SHIFT))
+
+#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \
+     ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT)
+
+#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \
+     tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_chicken_t {
+          unsigned int spare                          : TCF_CHICKEN_SPARE_SIZE;
+     } tcf_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_chicken_t f;
+} tcf_chicken_u;
+
+
+/*
+ * TCM_CHICKEN struct
+ */
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1
+#define TCM_CHICKEN_SPARE_SIZE         23
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8
+#define TCM_CHICKEN_SPARE_SHIFT        9
+
+#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff
+#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100
+#define TCM_CHICKEN_SPARE_MASK         0xfffffe00
+
+#define TCM_CHICKEN_MASK \
+     (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \
+      TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \
+      TCM_CHICKEN_SPARE_MASK)
+
+#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \
+     ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \
+      (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \
+      (spare << TCM_CHICKEN_SPARE_SHIFT))
+
+#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \
+     ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT)
+
+#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT)
+#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT)
+#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \
+     tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+     } tcm_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_chicken_t {
+          unsigned int spare                          : TCM_CHICKEN_SPARE_SIZE;
+          unsigned int etc_color_endian               : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE;
+          unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE;
+     } tcm_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_chicken_t f;
+} tcm_chicken_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER0_SELECT_MASK \
+     (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \
+     ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \
+     tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_select_t f;
+} tcr_perfcounter0_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCR_PERFCOUNTER1_SELECT_MASK \
+     (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \
+     ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \
+     tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcr_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcr_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_select_t f;
+} tcr_perfcounter1_select_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_HI struct
+ */
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER0_HI_MASK \
+     (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \
+     ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \
+     tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_hi_t f;
+} tcr_perfcounter0_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_HI struct
+ */
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCR_PERFCOUNTER1_HI_MASK \
+     (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \
+     ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \
+     tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcr_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcr_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_hi_t f;
+} tcr_perfcounter1_hi_u;
+
+
+/*
+ * TCR_PERFCOUNTER0_LOW struct
+ */
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER0_LOW_MASK \
+     (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \
+     ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \
+     tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter0_low_t f;
+} tcr_perfcounter0_low_u;
+
+
+/*
+ * TCR_PERFCOUNTER1_LOW struct
+ */
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCR_PERFCOUNTER1_LOW_MASK \
+     (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \
+     ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \
+     tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcr_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcr_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcr_perfcounter1_low_t f;
+} tcr_perfcounter1_low_u;
+
+
+/*
+ * TP_TC_CLKGATE_CNTL struct
+ */
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3
+
+#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007
+#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038
+
+#define TP_TC_CLKGATE_CNTL_MASK \
+     (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \
+      TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK)
+
+#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \
+     ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \
+      (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT))
+
+#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \
+     ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT)
+#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \
+     tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int                                : 26;
+     } tp_tc_clkgate_cntl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp_tc_clkgate_cntl_t {
+          unsigned int                                : 26;
+          unsigned int tc_busy_extend                 : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE;
+          unsigned int tp_busy_extend                 : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE;
+     } tp_tc_clkgate_cntl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp_tc_clkgate_cntl_t f;
+} tp_tc_clkgate_cntl_u;
+
+
+/*
+ * TPC_CNTL_STATUS struct
+ */
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1
+#define TPC_CNTL_STATUS_TPC_BUSY_SIZE  1
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15
+#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17
+#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19
+#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22
+#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23
+#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25
+#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27
+#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29
+#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30
+#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31
+
+#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001
+#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002
+#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004
+#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008
+#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010
+#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020
+#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040
+#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100
+#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200
+#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400
+#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000
+#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000
+#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000
+#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000
+#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000
+#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000
+#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000
+#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000
+#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000
+#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000
+#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000
+#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000
+#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000
+#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000
+#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000
+#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000
+#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000
+#define TPC_CNTL_STATUS_TPC_BUSY_MASK  0x80000000
+
+#define TPC_CNTL_STATUS_MASK \
+     (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \
+      TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \
+      TPC_CNTL_STATUS_TF_TW_RTR_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \
+      TPC_CNTL_STATUS_TW_TA_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TB_RTR_MASK | \
+      TPC_CNTL_STATUS_TA_TF_RTS_MASK | \
+      TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \
+      TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \
+      TPC_CNTL_STATUS_TPC_BUSY_MASK)
+
+#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \
+     ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \
+      (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \
+      (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \
+      (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \
+      (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \
+      (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \
+      (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \
+      (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \
+      (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \
+      (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \
+      (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \
+      (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \
+      (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \
+      (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \
+      (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \
+      (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \
+      (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \
+      (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \
+      (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \
+      (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \
+      (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \
+      (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \
+      (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \
+      (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \
+      (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT))
+
+#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \
+     ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT)
+#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT)
+#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT)
+#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \
+     tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_cntl_status_t {
+          unsigned int tpc_busy                       : TPC_CNTL_STATUS_TPC_BUSY_SIZE;
+          unsigned int tp_sq_dec                      : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE;
+          unsigned int ta_tf_tc_fifo_ren              : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE;
+          unsigned int ta_tf_rts                      : TPC_CNTL_STATUS_TA_TF_RTS_SIZE;
+          unsigned int ta_tb_rtr                      : TPC_CNTL_STATUS_TA_TB_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int ta_tb_tt_rts                   : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE;
+          unsigned int ta_tb_rts                      : TPC_CNTL_STATUS_TA_TB_RTS_SIZE;
+          unsigned int tw_ta_rtr                      : TPC_CNTL_STATUS_TW_TA_RTR_SIZE;
+          unsigned int tw_ta_last_rts                 : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE;
+          unsigned int tw_ta_tt_rts                   : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE;
+          unsigned int tw_ta_rts                      : TPC_CNTL_STATUS_TW_TA_RTS_SIZE;
+          unsigned int tf_tw_rtr                      : TPC_CNTL_STATUS_TF_TW_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int tf_tw_state_rts                : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE;
+          unsigned int tf_tw_rts                      : TPC_CNTL_STATUS_TF_TW_RTS_SIZE;
+          unsigned int tpc_blend_busy                 : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE;
+          unsigned int tpc_out_fifo_busy              : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE;
+          unsigned int tpc_blend_pipe_busy            : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE;
+          unsigned int tpc_rr_fifo_busy               : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_aligner_busy               : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE;
+          unsigned int tpc_align_fifo_busy            : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tpc_aligner_pipe_busy          : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int tpc_walker_busy                : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE;
+          unsigned int tpc_walk_fifo_busy             : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE;
+          unsigned int tpc_walker_pipe_busy           : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE;
+          unsigned int tpc_fetch_fifo_busy            : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE;
+          unsigned int tpc_state_fifo_busy            : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE;
+          unsigned int tpc_tc_fifo_busy               : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE;
+          unsigned int tpc_input_busy                 : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE;
+     } tpc_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_cntl_status_t f;
+} tpc_cntl_status_u;
+
+
+/*
+ * TPC_DEBUG0 struct
+ */
+
+#define TPC_DEBUG0_LOD_CNTL_SIZE       2
+#define TPC_DEBUG0_IC_CTR_SIZE         2
+#define TPC_DEBUG0_WALKER_CNTL_SIZE    4
+#define TPC_DEBUG0_ALIGNER_CNTL_SIZE   3
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1
+#define TPC_DEBUG0_WALKER_STATE_SIZE   10
+#define TPC_DEBUG0_ALIGNER_STATE_SIZE  2
+#define TPC_DEBUG0_REG_CLK_EN_SIZE     1
+#define TPC_DEBUG0_TPC_CLK_EN_SIZE     1
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE   1
+
+#define TPC_DEBUG0_LOD_CNTL_SHIFT      0
+#define TPC_DEBUG0_IC_CTR_SHIFT        2
+#define TPC_DEBUG0_WALKER_CNTL_SHIFT   4
+#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT  8
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12
+#define TPC_DEBUG0_WALKER_STATE_SHIFT  16
+#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26
+#define TPC_DEBUG0_REG_CLK_EN_SHIFT    29
+#define TPC_DEBUG0_TPC_CLK_EN_SHIFT    30
+#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT  31
+
+#define TPC_DEBUG0_LOD_CNTL_MASK       0x00000003
+#define TPC_DEBUG0_IC_CTR_MASK         0x0000000c
+#define TPC_DEBUG0_WALKER_CNTL_MASK    0x000000f0
+#define TPC_DEBUG0_ALIGNER_CNTL_MASK   0x00000700
+#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000
+#define TPC_DEBUG0_WALKER_STATE_MASK   0x03ff0000
+#define TPC_DEBUG0_ALIGNER_STATE_MASK  0x0c000000
+#define TPC_DEBUG0_REG_CLK_EN_MASK     0x20000000
+#define TPC_DEBUG0_TPC_CLK_EN_MASK     0x40000000
+#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK   0x80000000
+
+#define TPC_DEBUG0_MASK \
+     (TPC_DEBUG0_LOD_CNTL_MASK | \
+      TPC_DEBUG0_IC_CTR_MASK | \
+      TPC_DEBUG0_WALKER_CNTL_MASK | \
+      TPC_DEBUG0_ALIGNER_CNTL_MASK | \
+      TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \
+      TPC_DEBUG0_WALKER_STATE_MASK | \
+      TPC_DEBUG0_ALIGNER_STATE_MASK | \
+      TPC_DEBUG0_REG_CLK_EN_MASK | \
+      TPC_DEBUG0_TPC_CLK_EN_MASK | \
+      TPC_DEBUG0_SQ_TP_WAKEUP_MASK)
+
+#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \
+     ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \
+      (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \
+      (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \
+      (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \
+      (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \
+      (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \
+      (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \
+      (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \
+      (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \
+      (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT))
+
+#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \
+     ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT)
+#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT)
+#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT)
+#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT)
+#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \
+     tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 3;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+     } tpc_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug0_t {
+          unsigned int sq_tp_wakeup                   : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE;
+          unsigned int tpc_clk_en                     : TPC_DEBUG0_TPC_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TPC_DEBUG0_REG_CLK_EN_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_state                  : TPC_DEBUG0_ALIGNER_STATE_SIZE;
+          unsigned int walker_state                   : TPC_DEBUG0_WALKER_STATE_SIZE;
+          unsigned int                                : 3;
+          unsigned int prev_tc_state_valid            : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE;
+          unsigned int                                : 1;
+          unsigned int aligner_cntl                   : TPC_DEBUG0_ALIGNER_CNTL_SIZE;
+          unsigned int walker_cntl                    : TPC_DEBUG0_WALKER_CNTL_SIZE;
+          unsigned int ic_ctr                         : TPC_DEBUG0_IC_CTR_SIZE;
+          unsigned int lod_cntl                       : TPC_DEBUG0_LOD_CNTL_SIZE;
+     } tpc_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug0_t f;
+} tpc_debug0_u;
+
+
+/*
+ * TPC_DEBUG1 struct
+ */
+
+#define TPC_DEBUG1_UNUSED_SIZE         1
+
+#define TPC_DEBUG1_UNUSED_SHIFT        0
+
+#define TPC_DEBUG1_UNUSED_MASK         0x00000001
+
+#define TPC_DEBUG1_MASK \
+     (TPC_DEBUG1_UNUSED_MASK)
+
+#define TPC_DEBUG1(unused) \
+     ((unused << TPC_DEBUG1_UNUSED_SHIFT))
+
+#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \
+     ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT)
+
+#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \
+     tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+          unsigned int                                : 31;
+     } tpc_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_debug1_t {
+          unsigned int                                : 31;
+          unsigned int unused                         : TPC_DEBUG1_UNUSED_SIZE;
+     } tpc_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_debug1_t f;
+} tpc_debug1_u;
+
+
+/*
+ * TPC_CHICKEN struct
+ */
+
+#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1
+#define TPC_CHICKEN_SPARE_SIZE         31
+
+#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0
+#define TPC_CHICKEN_SPARE_SHIFT        1
+
+#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001
+#define TPC_CHICKEN_SPARE_MASK         0xfffffffe
+
+#define TPC_CHICKEN_MASK \
+     (TPC_CHICKEN_BLEND_PRECISION_MASK | \
+      TPC_CHICKEN_SPARE_MASK)
+
+#define TPC_CHICKEN(blend_precision, spare) \
+     ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \
+      (spare << TPC_CHICKEN_SPARE_SHIFT))
+
+#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \
+     ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT)
+
+#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT)
+#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \
+     tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+     } tpc_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tpc_chicken_t {
+          unsigned int spare                          : TPC_CHICKEN_SPARE_SIZE;
+          unsigned int blend_precision                : TPC_CHICKEN_BLEND_PRECISION_SIZE;
+     } tpc_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tpc_chicken_t f;
+} tpc_chicken_u;
+
+
+/*
+ * TP0_CNTL_STATUS struct
+ */
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1
+#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1
+#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1
+#define TP0_CNTL_STATUS_TP_BUSY_SIZE   1
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9
+#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14
+#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16
+#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17
+#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18
+#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19
+#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21
+#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23
+#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25
+#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27
+#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29
+#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30
+#define TP0_CNTL_STATUS_TP_BUSY_SHIFT  31
+
+#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001
+#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002
+#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004
+#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008
+#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010
+#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020
+#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040
+#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080
+#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100
+#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200
+#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400
+#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800
+#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000
+#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000
+#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000
+#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000
+#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000
+#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000
+#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000
+#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000
+#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000
+#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000
+#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000
+#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000
+#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000
+#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000
+#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000
+#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000
+#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000
+#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000
+#define TP0_CNTL_STATUS_TP_BUSY_MASK   0x80000000
+
+#define TP0_CNTL_STATUS_MASK \
+     (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \
+      TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \
+      TP0_CNTL_STATUS_IN_LC_RTS_MASK | \
+      TP0_CNTL_STATUS_LC_LA_RTS_MASK | \
+      TP0_CNTL_STATUS_LA_FL_RTS_MASK | \
+      TP0_CNTL_STATUS_FL_TA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_RTS_MASK | \
+      TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_RTS_MASK | \
+      TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_RTS_MASK | \
+      TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_RTS_MASK | \
+      TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_RTS_MASK | \
+      TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \
+      TP0_CNTL_STATUS_TB_TO_RTS_MASK | \
+      TP0_CNTL_STATUS_TP_BUSY_MASK)
+
+#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \
+     ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \
+      (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \
+      (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \
+      (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \
+      (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \
+      (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \
+      (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \
+      (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \
+      (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \
+      (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \
+      (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \
+      (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \
+      (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \
+      (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \
+      (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \
+      (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \
+      (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \
+      (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \
+      (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \
+      (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \
+      (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \
+      (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \
+      (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \
+      (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \
+      (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \
+      (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \
+      (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \
+      (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \
+      (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \
+      (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \
+      (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT))
+
+#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \
+     ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT)
+#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT)
+#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT)
+#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \
+     tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int                                : 1;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_cntl_status_t {
+          unsigned int tp_busy                        : TP0_CNTL_STATUS_TP_BUSY_SIZE;
+          unsigned int tb_to_rts                      : TP0_CNTL_STATUS_TB_TO_RTS_SIZE;
+          unsigned int tb_tt_tt_reset                 : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE;
+          unsigned int tb_tt_rts                      : TP0_CNTL_STATUS_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_tt_rts                   : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE;
+          unsigned int tf_tb_rts                      : TP0_CNTL_STATUS_TF_TB_RTS_SIZE;
+          unsigned int al_tf_tt_rts                   : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE;
+          unsigned int al_tf_rts                      : TP0_CNTL_STATUS_AL_TF_RTS_SIZE;
+          unsigned int fa_al_tt_rts                   : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE;
+          unsigned int fa_al_rts                      : TP0_CNTL_STATUS_FA_AL_RTS_SIZE;
+          unsigned int ta_fa_tt_rts                   : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE;
+          unsigned int ta_fa_rts                      : TP0_CNTL_STATUS_TA_FA_RTS_SIZE;
+          unsigned int fl_ta_rts                      : TP0_CNTL_STATUS_FL_TA_RTS_SIZE;
+          unsigned int la_fl_rts                      : TP0_CNTL_STATUS_LA_FL_RTS_SIZE;
+          unsigned int lc_la_rts                      : TP0_CNTL_STATUS_LC_LA_RTS_SIZE;
+          unsigned int in_lc_rts                      : TP0_CNTL_STATUS_IN_LC_RTS_SIZE;
+          unsigned int                                : 1;
+          unsigned int tp_output_busy                 : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE;
+          unsigned int tp_out_fifo_busy               : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE;
+          unsigned int tp_blend_busy                  : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE;
+          unsigned int tp_hicolor_busy                : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE;
+          unsigned int tp_tt_busy                     : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE;
+          unsigned int tp_ch_blend_busy               : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE;
+          unsigned int tp_fetch_busy                  : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE;
+          unsigned int tp_rr_fifo_busy                : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE;
+          unsigned int tp_tc_fifo_busy                : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE;
+          unsigned int tp_aligner_busy                : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE;
+          unsigned int tp_align_fifo_busy             : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE;
+          unsigned int tp_addr_busy                   : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE;
+          unsigned int tp_lod_fifo_busy               : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE;
+          unsigned int tp_lod_busy                    : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE;
+          unsigned int tp_input_busy                  : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE;
+     } tp0_cntl_status_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_cntl_status_t f;
+} tp0_cntl_status_u;
+
+
+/*
+ * TP0_DEBUG struct
+ */
+
+#define TP0_DEBUG_Q_LOD_CNTL_SIZE      2
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE  1
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17
+#define TP0_DEBUG_REG_CLK_EN_SIZE      1
+#define TP0_DEBUG_PERF_CLK_EN_SIZE     1
+#define TP0_DEBUG_TP_CLK_EN_SIZE       1
+#define TP0_DEBUG_Q_WALKER_CNTL_SIZE   4
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE  3
+
+#define TP0_DEBUG_Q_LOD_CNTL_SHIFT     0
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4
+#define TP0_DEBUG_REG_CLK_EN_SHIFT     21
+#define TP0_DEBUG_PERF_CLK_EN_SHIFT    22
+#define TP0_DEBUG_TP_CLK_EN_SHIFT      23
+#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT  24
+#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28
+
+#define TP0_DEBUG_Q_LOD_CNTL_MASK      0x00000003
+#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK  0x00000008
+#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0
+#define TP0_DEBUG_REG_CLK_EN_MASK      0x00200000
+#define TP0_DEBUG_PERF_CLK_EN_MASK     0x00400000
+#define TP0_DEBUG_TP_CLK_EN_MASK       0x00800000
+#define TP0_DEBUG_Q_WALKER_CNTL_MASK   0x0f000000
+#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK  0x70000000
+
+#define TP0_DEBUG_MASK \
+     (TP0_DEBUG_Q_LOD_CNTL_MASK | \
+      TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \
+      TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \
+      TP0_DEBUG_REG_CLK_EN_MASK | \
+      TP0_DEBUG_PERF_CLK_EN_MASK | \
+      TP0_DEBUG_TP_CLK_EN_MASK | \
+      TP0_DEBUG_Q_WALKER_CNTL_MASK | \
+      TP0_DEBUG_Q_ALIGNER_CNTL_MASK)
+
+#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \
+     ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \
+      (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \
+      (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \
+      (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \
+      (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \
+      (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \
+      (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \
+      (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT))
+
+#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \
+     ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT)
+#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT)
+#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT)
+#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \
+     tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int                                : 1;
+     } tp0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_debug_t {
+          unsigned int                                : 1;
+          unsigned int q_aligner_cntl                 : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE;
+          unsigned int q_walker_cntl                  : TP0_DEBUG_Q_WALKER_CNTL_SIZE;
+          unsigned int tp_clk_en                      : TP0_DEBUG_TP_CLK_EN_SIZE;
+          unsigned int perf_clk_en                    : TP0_DEBUG_PERF_CLK_EN_SIZE;
+          unsigned int reg_clk_en                     : TP0_DEBUG_REG_CLK_EN_SIZE;
+          unsigned int fl_ta_addresser_cntl           : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE;
+          unsigned int q_sq_tp_wakeup                 : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE;
+          unsigned int                                : 1;
+          unsigned int q_lod_cntl                     : TP0_DEBUG_Q_LOD_CNTL_SIZE;
+     } tp0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_debug_t f;
+} tp0_debug_u;
+
+
+/*
+ * TP0_CHICKEN struct
+ */
+
+#define TP0_CHICKEN_TT_MODE_SIZE       1
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1
+#define TP0_CHICKEN_SPARE_SIZE         30
+
+#define TP0_CHICKEN_TT_MODE_SHIFT      0
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1
+#define TP0_CHICKEN_SPARE_SHIFT        2
+
+#define TP0_CHICKEN_TT_MODE_MASK       0x00000001
+#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002
+#define TP0_CHICKEN_SPARE_MASK         0xfffffffc
+
+#define TP0_CHICKEN_MASK \
+     (TP0_CHICKEN_TT_MODE_MASK | \
+      TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \
+      TP0_CHICKEN_SPARE_MASK)
+
+#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \
+     ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \
+      (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \
+      (spare << TP0_CHICKEN_SPARE_SHIFT))
+
+#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \
+     ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT)
+
+#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT)
+#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT)
+#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \
+     tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+     } tp0_chicken_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_chicken_t {
+          unsigned int spare                          : TP0_CHICKEN_SPARE_SIZE;
+          unsigned int vfetch_address_mode            : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE;
+          unsigned int tt_mode                        : TP0_CHICKEN_TT_MODE_SIZE;
+     } tp0_chicken_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_chicken_t f;
+} tp0_chicken_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER0_SELECT_MASK \
+     (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \
+     ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \
+     tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_select_t f;
+} tp0_perfcounter0_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_HI struct
+ */
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER0_HI_MASK \
+     (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \
+     ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \
+     tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_hi_t f;
+} tp0_perfcounter0_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER0_LOW struct
+ */
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER0_LOW_MASK \
+     (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \
+     ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \
+     tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter0_low_t f;
+} tp0_perfcounter0_low_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_SELECT struct
+ */
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TP0_PERFCOUNTER1_SELECT_MASK \
+     (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \
+     ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \
+     tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tp0_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tp0_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_select_t f;
+} tp0_perfcounter1_select_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_HI struct
+ */
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TP0_PERFCOUNTER1_HI_MASK \
+     (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \
+     ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \
+     tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tp0_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tp0_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_hi_t f;
+} tp0_perfcounter1_hi_u;
+
+
+/*
+ * TP0_PERFCOUNTER1_LOW struct
+ */
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TP0_PERFCOUNTER1_LOW_MASK \
+     (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \
+     ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \
+     tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tp0_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tp0_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tp0_perfcounter1_low_t f;
+} tp0_perfcounter1_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER0_SELECT_MASK \
+     (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \
+     ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \
+     tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_select_t f;
+} tcm_perfcounter0_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCM_PERFCOUNTER1_SELECT_MASK \
+     (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \
+     ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \
+     tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcm_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcm_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_select_t f;
+} tcm_perfcounter1_select_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_HI struct
+ */
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER0_HI_MASK \
+     (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \
+     ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \
+     tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_hi_t f;
+} tcm_perfcounter0_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_HI struct
+ */
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCM_PERFCOUNTER1_HI_MASK \
+     (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \
+     ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \
+     tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcm_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcm_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_hi_t f;
+} tcm_perfcounter1_hi_u;
+
+
+/*
+ * TCM_PERFCOUNTER0_LOW struct
+ */
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER0_LOW_MASK \
+     (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \
+     ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \
+     tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter0_low_t f;
+} tcm_perfcounter0_low_u;
+
+
+/*
+ * TCM_PERFCOUNTER1_LOW struct
+ */
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCM_PERFCOUNTER1_LOW_MASK \
+     (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \
+     ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \
+     tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcm_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcm_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcm_perfcounter1_low_t f;
+} tcm_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER0_SELECT_MASK \
+     (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \
+     ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \
+     tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_select_t f;
+} tcf_perfcounter0_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER1_SELECT_MASK \
+     (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \
+     ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \
+     tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter1_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter1_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_select_t f;
+} tcf_perfcounter1_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER2_SELECT_MASK \
+     (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \
+     ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \
+     tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter2_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter2_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_select_t f;
+} tcf_perfcounter2_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER3_SELECT_MASK \
+     (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \
+     ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \
+     tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter3_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter3_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_select_t f;
+} tcf_perfcounter3_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER4_SELECT_MASK \
+     (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \
+     ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \
+     tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter4_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter4_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_select_t f;
+} tcf_perfcounter4_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER5_SELECT_MASK \
+     (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \
+     ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \
+     tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter5_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter5_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_select_t f;
+} tcf_perfcounter5_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER6_SELECT_MASK \
+     (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \
+     ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \
+     tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter6_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter6_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_select_t f;
+} tcf_perfcounter6_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER7_SELECT_MASK \
+     (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \
+     ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \
+     tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter7_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter7_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_select_t f;
+} tcf_perfcounter7_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER8_SELECT_MASK \
+     (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \
+     ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \
+     tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter8_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter8_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_select_t f;
+} tcf_perfcounter8_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER9_SELECT_MASK \
+     (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \
+     ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \
+     tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter9_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter9_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_select_t f;
+} tcf_perfcounter9_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER10_SELECT_MASK \
+     (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \
+     ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \
+     tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter10_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter10_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_select_t f;
+} tcf_perfcounter10_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_SELECT struct
+ */
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0
+
+#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff
+
+#define TCF_PERFCOUNTER11_SELECT_MASK \
+     (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK)
+
+#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \
+     ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT))
+
+#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \
+     ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \
+     tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+          unsigned int                                : 24;
+     } tcf_perfcounter11_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_select_t {
+          unsigned int                                : 24;
+          unsigned int perfcounter_select             : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE;
+     } tcf_perfcounter11_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_select_t f;
+} tcf_perfcounter11_select_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_HI struct
+ */
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER0_HI_MASK \
+     (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \
+     ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \
+     tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_hi_t f;
+} tcf_perfcounter0_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_HI struct
+ */
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER1_HI_MASK \
+     (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \
+     ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \
+     tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter1_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter1_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_hi_t f;
+} tcf_perfcounter1_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_HI struct
+ */
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER2_HI_MASK \
+     (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \
+     ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \
+     tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter2_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter2_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_hi_t f;
+} tcf_perfcounter2_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_HI struct
+ */
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER3_HI_MASK \
+     (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \
+     ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \
+     tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter3_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter3_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_hi_t f;
+} tcf_perfcounter3_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_HI struct
+ */
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER4_HI_MASK \
+     (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \
+     ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \
+     tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter4_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter4_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_hi_t f;
+} tcf_perfcounter4_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_HI struct
+ */
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER5_HI_MASK \
+     (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \
+     ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \
+     tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter5_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter5_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_hi_t f;
+} tcf_perfcounter5_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_HI struct
+ */
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER6_HI_MASK \
+     (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \
+     ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \
+     tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter6_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter6_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_hi_t f;
+} tcf_perfcounter6_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_HI struct
+ */
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER7_HI_MASK \
+     (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \
+     ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \
+     tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter7_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter7_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_hi_t f;
+} tcf_perfcounter7_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_HI struct
+ */
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER8_HI_MASK \
+     (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \
+     ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \
+     tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter8_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter8_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_hi_t f;
+} tcf_perfcounter8_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_HI struct
+ */
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER9_HI_MASK \
+     (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \
+     ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \
+     tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter9_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter9_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_hi_t f;
+} tcf_perfcounter9_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_HI struct
+ */
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER10_HI_MASK \
+     (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \
+     ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \
+     tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter10_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter10_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_hi_t f;
+} tcf_perfcounter10_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_HI struct
+ */
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0
+
+#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff
+
+#define TCF_PERFCOUNTER11_HI_MASK \
+     (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK)
+
+#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \
+     ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT))
+
+#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \
+     ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \
+     tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+          unsigned int                                : 16;
+     } tcf_perfcounter11_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_hi_t {
+          unsigned int                                : 16;
+          unsigned int perfcounter_hi                 : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE;
+     } tcf_perfcounter11_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_hi_t f;
+} tcf_perfcounter11_hi_u;
+
+
+/*
+ * TCF_PERFCOUNTER0_LOW struct
+ */
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER0_LOW_MASK \
+     (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \
+     ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \
+     tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter0_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter0_low_t f;
+} tcf_perfcounter0_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER1_LOW struct
+ */
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER1_LOW_MASK \
+     (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \
+     ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \
+     tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter1_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter1_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter1_low_t f;
+} tcf_perfcounter1_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER2_LOW struct
+ */
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER2_LOW_MASK \
+     (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \
+     ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \
+     tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter2_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter2_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter2_low_t f;
+} tcf_perfcounter2_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER3_LOW struct
+ */
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER3_LOW_MASK \
+     (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \
+     ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \
+     tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter3_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter3_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter3_low_t f;
+} tcf_perfcounter3_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER4_LOW struct
+ */
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER4_LOW_MASK \
+     (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \
+     ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \
+     tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter4_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter4_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter4_low_t f;
+} tcf_perfcounter4_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER5_LOW struct
+ */
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER5_LOW_MASK \
+     (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \
+     ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \
+     tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter5_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter5_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter5_low_t f;
+} tcf_perfcounter5_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER6_LOW struct
+ */
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER6_LOW_MASK \
+     (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \
+     ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \
+     tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter6_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter6_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter6_low_t f;
+} tcf_perfcounter6_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER7_LOW struct
+ */
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER7_LOW_MASK \
+     (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \
+     ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \
+     tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter7_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter7_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter7_low_t f;
+} tcf_perfcounter7_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER8_LOW struct
+ */
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER8_LOW_MASK \
+     (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \
+     ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \
+     tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter8_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter8_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter8_low_t f;
+} tcf_perfcounter8_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER9_LOW struct
+ */
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER9_LOW_MASK \
+     (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \
+     ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \
+     tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter9_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter9_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter9_low_t f;
+} tcf_perfcounter9_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER10_LOW struct
+ */
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER10_LOW_MASK \
+     (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \
+     ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \
+     tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter10_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter10_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter10_low_t f;
+} tcf_perfcounter10_low_u;
+
+
+/*
+ * TCF_PERFCOUNTER11_LOW struct
+ */
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0
+
+#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff
+
+#define TCF_PERFCOUNTER11_LOW_MASK \
+     (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK)
+
+#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \
+     ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT))
+
+#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \
+     ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \
+     tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_perfcounter11_low_t {
+          unsigned int perfcounter_low                : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE;
+     } tcf_perfcounter11_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_perfcounter11_low_t f;
+} tcf_perfcounter11_low_u;
+
+
+/*
+ * TCF_DEBUG struct
+ */
+
+#define TCF_DEBUG_not_MH_TC_rtr_SIZE   1
+#define TCF_DEBUG_TC_MH_send_SIZE      1
+#define TCF_DEBUG_not_FG0_rtr_SIZE     1
+#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1
+#define TCF_DEBUG_TCB_ff_stall_SIZE    1
+#define TCF_DEBUG_TCB_miss_stall_SIZE  1
+#define TCF_DEBUG_TCA_TCB_stall_SIZE   1
+#define TCF_DEBUG_PF0_stall_SIZE       1
+#define TCF_DEBUG_TP0_full_SIZE        1
+#define TCF_DEBUG_TPC_full_SIZE        1
+#define TCF_DEBUG_not_TPC_rtr_SIZE     1
+#define TCF_DEBUG_tca_state_rts_SIZE   1
+#define TCF_DEBUG_tca_rts_SIZE         1
+
+#define TCF_DEBUG_not_MH_TC_rtr_SHIFT  6
+#define TCF_DEBUG_TC_MH_send_SHIFT     7
+#define TCF_DEBUG_not_FG0_rtr_SHIFT    8
+#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12
+#define TCF_DEBUG_TCB_ff_stall_SHIFT   13
+#define TCF_DEBUG_TCB_miss_stall_SHIFT 14
+#define TCF_DEBUG_TCA_TCB_stall_SHIFT  15
+#define TCF_DEBUG_PF0_stall_SHIFT      16
+#define TCF_DEBUG_TP0_full_SHIFT       20
+#define TCF_DEBUG_TPC_full_SHIFT       24
+#define TCF_DEBUG_not_TPC_rtr_SHIFT    25
+#define TCF_DEBUG_tca_state_rts_SHIFT  26
+#define TCF_DEBUG_tca_rts_SHIFT        27
+
+#define TCF_DEBUG_not_MH_TC_rtr_MASK   0x00000040
+#define TCF_DEBUG_TC_MH_send_MASK      0x00000080
+#define TCF_DEBUG_not_FG0_rtr_MASK     0x00000100
+#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000
+#define TCF_DEBUG_TCB_ff_stall_MASK    0x00002000
+#define TCF_DEBUG_TCB_miss_stall_MASK  0x00004000
+#define TCF_DEBUG_TCA_TCB_stall_MASK   0x00008000
+#define TCF_DEBUG_PF0_stall_MASK       0x00010000
+#define TCF_DEBUG_TP0_full_MASK        0x00100000
+#define TCF_DEBUG_TPC_full_MASK        0x01000000
+#define TCF_DEBUG_not_TPC_rtr_MASK     0x02000000
+#define TCF_DEBUG_tca_state_rts_MASK   0x04000000
+#define TCF_DEBUG_tca_rts_MASK         0x08000000
+
+#define TCF_DEBUG_MASK \
+     (TCF_DEBUG_not_MH_TC_rtr_MASK | \
+      TCF_DEBUG_TC_MH_send_MASK | \
+      TCF_DEBUG_not_FG0_rtr_MASK | \
+      TCF_DEBUG_not_TCB_TCO_rtr_MASK | \
+      TCF_DEBUG_TCB_ff_stall_MASK | \
+      TCF_DEBUG_TCB_miss_stall_MASK | \
+      TCF_DEBUG_TCA_TCB_stall_MASK | \
+      TCF_DEBUG_PF0_stall_MASK | \
+      TCF_DEBUG_TP0_full_MASK | \
+      TCF_DEBUG_TPC_full_MASK | \
+      TCF_DEBUG_not_TPC_rtr_MASK | \
+      TCF_DEBUG_tca_state_rts_MASK | \
+      TCF_DEBUG_tca_rts_MASK)
+
+#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \
+     ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \
+      (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \
+      (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \
+      (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \
+      (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \
+      (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \
+      (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \
+      (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \
+      (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \
+      (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \
+      (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \
+      (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \
+      (tca_rts << TCF_DEBUG_tca_rts_SHIFT))
+
+#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_GET_TP0_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_GET_TPC_full(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_GET_tca_rts(tcf_debug) \
+     ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT)
+
+#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT)
+#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT)
+#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT)
+#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT)
+#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT)
+#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT)
+#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT)
+#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT)
+#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT)
+#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT)
+#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT)
+#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT)
+#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \
+     tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 6;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int                                : 4;
+     } tcf_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcf_debug_t {
+          unsigned int                                : 4;
+          unsigned int tca_rts                        : TCF_DEBUG_tca_rts_SIZE;
+          unsigned int tca_state_rts                  : TCF_DEBUG_tca_state_rts_SIZE;
+          unsigned int not_tpc_rtr                    : TCF_DEBUG_not_TPC_rtr_SIZE;
+          unsigned int tpc_full                       : TCF_DEBUG_TPC_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCF_DEBUG_TP0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int pf0_stall                      : TCF_DEBUG_PF0_stall_SIZE;
+          unsigned int tca_tcb_stall                  : TCF_DEBUG_TCA_TCB_stall_SIZE;
+          unsigned int tcb_miss_stall                 : TCF_DEBUG_TCB_miss_stall_SIZE;
+          unsigned int tcb_ff_stall                   : TCF_DEBUG_TCB_ff_stall_SIZE;
+          unsigned int not_tcb_tco_rtr                : TCF_DEBUG_not_TCB_TCO_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fg0_rtr                    : TCF_DEBUG_not_FG0_rtr_SIZE;
+          unsigned int tc_mh_send                     : TCF_DEBUG_TC_MH_send_SIZE;
+          unsigned int not_mh_tc_rtr                  : TCF_DEBUG_not_MH_TC_rtr_SIZE;
+          unsigned int                                : 6;
+     } tcf_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcf_debug_t f;
+} tcf_debug_u;
+
+
+/*
+ * TCA_FIFO_DEBUG struct
+ */
+
+#define TCA_FIFO_DEBUG_tp0_full_SIZE   1
+#define TCA_FIFO_DEBUG_tpc_full_SIZE   1
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1
+#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1
+#define TCA_FIFO_DEBUG_FW_full_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1
+#define TCA_FIFO_DEBUG_FW_rts0_SIZE    1
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1
+
+#define TCA_FIFO_DEBUG_tp0_full_SHIFT  0
+#define TCA_FIFO_DEBUG_tpc_full_SHIFT  4
+#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5
+#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6
+#define TCA_FIFO_DEBUG_FW_full_SHIFT   7
+#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8
+#define TCA_FIFO_DEBUG_FW_rts0_SHIFT   12
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16
+#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17
+
+#define TCA_FIFO_DEBUG_tp0_full_MASK   0x00000001
+#define TCA_FIFO_DEBUG_tpc_full_MASK   0x00000010
+#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020
+#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040
+#define TCA_FIFO_DEBUG_FW_full_MASK    0x00000080
+#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100
+#define TCA_FIFO_DEBUG_FW_rts0_MASK    0x00001000
+#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000
+#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000
+
+#define TCA_FIFO_DEBUG_MASK \
+     (TCA_FIFO_DEBUG_tp0_full_MASK | \
+      TCA_FIFO_DEBUG_tpc_full_MASK | \
+      TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \
+      TCA_FIFO_DEBUG_load_tp_fifos_MASK | \
+      TCA_FIFO_DEBUG_FW_full_MASK | \
+      TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \
+      TCA_FIFO_DEBUG_FW_rts0_MASK | \
+      TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \
+      TCA_FIFO_DEBUG_FW_tpc_rts_MASK)
+
+#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \
+     ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \
+      (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \
+      (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \
+      (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \
+      (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \
+      (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \
+      (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \
+      (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \
+      (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT))
+
+#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \
+     ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT)
+#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT)
+#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT)
+#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \
+     tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int                                : 14;
+     } tca_fifo_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_fifo_debug_t {
+          unsigned int                                : 14;
+          unsigned int fw_tpc_rts                     : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE;
+          unsigned int not_fw_tpc_rtr                 : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int fw_rts0                        : TCA_FIFO_DEBUG_FW_rts0_SIZE;
+          unsigned int                                : 3;
+          unsigned int not_fw_rtr0                    : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE;
+          unsigned int fw_full                        : TCA_FIFO_DEBUG_FW_full_SIZE;
+          unsigned int load_tp_fifos                  : TCA_FIFO_DEBUG_load_tp_fifos_SIZE;
+          unsigned int load_tpc_fifo                  : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE;
+          unsigned int tpc_full                       : TCA_FIFO_DEBUG_tpc_full_SIZE;
+          unsigned int                                : 3;
+          unsigned int tp0_full                       : TCA_FIFO_DEBUG_tp0_full_SIZE;
+     } tca_fifo_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_fifo_debug_t f;
+} tca_fifo_debug_u;
+
+
+/*
+ * TCA_PROBE_DEBUG struct
+ */
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0
+
+#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001
+
+#define TCA_PROBE_DEBUG_MASK \
+     (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK)
+
+#define TCA_PROBE_DEBUG(probefilter_stall) \
+     ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT))
+
+#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \
+     ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \
+     tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+          unsigned int                                : 31;
+     } tca_probe_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_probe_debug_t {
+          unsigned int                                : 31;
+          unsigned int probefilter_stall              : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE;
+     } tca_probe_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_probe_debug_t f;
+} tca_probe_debug_u;
+
+
+/*
+ * TCA_TPC_DEBUG struct
+ */
+
+#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1
+#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1
+
+#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12
+#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13
+
+#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000
+#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000
+
+#define TCA_TPC_DEBUG_MASK \
+     (TCA_TPC_DEBUG_captue_state_rts_MASK | \
+      TCA_TPC_DEBUG_capture_tca_rts_MASK)
+
+#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \
+     ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \
+      (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT))
+
+#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \
+     ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT)
+#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \
+     tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 12;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int                                : 18;
+     } tca_tpc_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tca_tpc_debug_t {
+          unsigned int                                : 18;
+          unsigned int capture_tca_rts                : TCA_TPC_DEBUG_capture_tca_rts_SIZE;
+          unsigned int captue_state_rts               : TCA_TPC_DEBUG_captue_state_rts_SIZE;
+          unsigned int                                : 12;
+     } tca_tpc_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tca_tpc_debug_t f;
+} tca_tpc_debug_u;
+
+
+/*
+ * TCB_CORE_DEBUG struct
+ */
+
+#define TCB_CORE_DEBUG_access512_SIZE  1
+#define TCB_CORE_DEBUG_tiled_SIZE      1
+#define TCB_CORE_DEBUG_opcode_SIZE     3
+#define TCB_CORE_DEBUG_format_SIZE     6
+#define TCB_CORE_DEBUG_sector_format_SIZE 5
+#define TCB_CORE_DEBUG_sector_format512_SIZE 3
+
+#define TCB_CORE_DEBUG_access512_SHIFT 0
+#define TCB_CORE_DEBUG_tiled_SHIFT     1
+#define TCB_CORE_DEBUG_opcode_SHIFT    4
+#define TCB_CORE_DEBUG_format_SHIFT    8
+#define TCB_CORE_DEBUG_sector_format_SHIFT 16
+#define TCB_CORE_DEBUG_sector_format512_SHIFT 24
+
+#define TCB_CORE_DEBUG_access512_MASK  0x00000001
+#define TCB_CORE_DEBUG_tiled_MASK      0x00000002
+#define TCB_CORE_DEBUG_opcode_MASK     0x00000070
+#define TCB_CORE_DEBUG_format_MASK     0x00003f00
+#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000
+#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000
+
+#define TCB_CORE_DEBUG_MASK \
+     (TCB_CORE_DEBUG_access512_MASK | \
+      TCB_CORE_DEBUG_tiled_MASK | \
+      TCB_CORE_DEBUG_opcode_MASK | \
+      TCB_CORE_DEBUG_format_MASK | \
+      TCB_CORE_DEBUG_sector_format_MASK | \
+      TCB_CORE_DEBUG_sector_format512_MASK)
+
+#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \
+     ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \
+      (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \
+      (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \
+      (format << TCB_CORE_DEBUG_format_SHIFT) | \
+      (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \
+      (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT))
+
+#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \
+     ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT)
+#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT)
+#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT)
+#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT)
+#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \
+     tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int                                : 2;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 1;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 5;
+     } tcb_core_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_core_debug_t {
+          unsigned int                                : 5;
+          unsigned int sector_format512               : TCB_CORE_DEBUG_sector_format512_SIZE;
+          unsigned int                                : 3;
+          unsigned int sector_format                  : TCB_CORE_DEBUG_sector_format_SIZE;
+          unsigned int                                : 2;
+          unsigned int format                         : TCB_CORE_DEBUG_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int opcode                         : TCB_CORE_DEBUG_opcode_SIZE;
+          unsigned int                                : 2;
+          unsigned int tiled                          : TCB_CORE_DEBUG_tiled_SIZE;
+          unsigned int access512                      : TCB_CORE_DEBUG_access512_SIZE;
+     } tcb_core_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_core_debug_t f;
+} tcb_core_debug_u;
+
+
+/*
+ * TCB_TAG0_DEBUG struct
+ */
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG0_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG0_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG0_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG0_DEBUG_MASK \
+     (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG0_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG0_DEBUG_miss_stall_MASK | \
+      TCB_TAG0_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG0_DEBUG_max_misses_MASK)
+
+#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \
+     ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \
+     tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+     } tcb_tag0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag0_debug_t {
+          unsigned int max_misses                     : TCB_TAG0_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG0_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG0_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG0_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG0_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag0_debug_t f;
+} tcb_tag0_debug_u;
+
+
+/*
+ * TCB_TAG1_DEBUG struct
+ */
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG1_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG1_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG1_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG1_DEBUG_MASK \
+     (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG1_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG1_DEBUG_miss_stall_MASK | \
+      TCB_TAG1_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG1_DEBUG_max_misses_MASK)
+
+#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \
+     ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \
+     tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+     } tcb_tag1_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag1_debug_t {
+          unsigned int max_misses                     : TCB_TAG1_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG1_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG1_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG1_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG1_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag1_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag1_debug_t f;
+} tcb_tag1_debug_u;
+
+
+/*
+ * TCB_TAG2_DEBUG struct
+ */
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG2_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG2_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG2_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG2_DEBUG_MASK \
+     (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG2_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG2_DEBUG_miss_stall_MASK | \
+      TCB_TAG2_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG2_DEBUG_max_misses_MASK)
+
+#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \
+     ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \
+     tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+     } tcb_tag2_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag2_debug_t {
+          unsigned int max_misses                     : TCB_TAG2_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG2_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG2_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG2_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG2_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag2_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag2_debug_t f;
+} tcb_tag2_debug_u;
+
+
+/*
+ * TCB_TAG3_DEBUG struct
+ */
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10
+#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9
+#define TCB_TAG3_DEBUG_miss_stall_SIZE 1
+#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5
+#define TCB_TAG3_DEBUG_max_misses_SIZE 3
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0
+#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12
+#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23
+#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24
+#define TCB_TAG3_DEBUG_max_misses_SHIFT 29
+
+#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff
+#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000
+#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000
+#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000
+#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000
+
+#define TCB_TAG3_DEBUG_MASK \
+     (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \
+      TCB_TAG3_DEBUG_tag_access_cycle_MASK | \
+      TCB_TAG3_DEBUG_miss_stall_MASK | \
+      TCB_TAG3_DEBUG_num_feee_lines_MASK | \
+      TCB_TAG3_DEBUG_max_misses_MASK)
+
+#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \
+     ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \
+      (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \
+      (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \
+      (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \
+      (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT))
+
+#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \
+     ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT)
+#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT)
+#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT)
+#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \
+     tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+     } tcb_tag3_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_tag3_debug_t {
+          unsigned int max_misses                     : TCB_TAG3_DEBUG_max_misses_SIZE;
+          unsigned int num_feee_lines                 : TCB_TAG3_DEBUG_num_feee_lines_SIZE;
+          unsigned int miss_stall                     : TCB_TAG3_DEBUG_miss_stall_SIZE;
+          unsigned int                                : 2;
+          unsigned int tag_access_cycle               : TCB_TAG3_DEBUG_tag_access_cycle_SIZE;
+          unsigned int                                : 2;
+          unsigned int mem_read_cycle                 : TCB_TAG3_DEBUG_mem_read_cycle_SIZE;
+     } tcb_tag3_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_tag3_debug_t f;
+} tcb_tag3_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \
+     (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \
+      TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \
+     ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \
+      (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \
+      (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \
+      (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \
+      (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \
+      (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \
+      (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \
+      (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT))
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \
+     ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT)
+#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \
+     tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int                                : 3;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_sector_walker0_debug_t {
+          unsigned int                                : 3;
+          unsigned int valid_left_q                   : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE;
+          unsigned int sector_mask_left_q             : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE;
+          unsigned int sector_mask_left_count_q       : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE;
+          unsigned int update_left                    : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE;
+          unsigned int no_sectors_to_go               : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE;
+          unsigned int one_sector_to_go_left_q        : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int fg0_sends_left                 : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE;
+          unsigned int                                : 1;
+          unsigned int left_done                      : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE;
+     } tcb_fetch_gen_sector_walker0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_sector_walker0_debug_t f;
+} tcb_fetch_gen_sector_walker0_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_WALKER_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030
+#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0
+#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800
+#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000
+#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000
+#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \
+     (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \
+     ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \
+      (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \
+      (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \
+      (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \
+      (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \
+      (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT))
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \
+     ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \
+     tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 4;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int                                : 12;
+     } tcb_fetch_gen_walker_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_walker_debug_t {
+          unsigned int                                : 12;
+          unsigned int setquads_to_send               : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE;
+          unsigned int ff_fg_type512                  : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE;
+          unsigned int right_eq_left                  : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE;
+          unsigned int                                : 3;
+          unsigned int set_sel_left                   : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE;
+          unsigned int quad_sel_left                  : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE;
+          unsigned int                                : 4;
+     } tcb_fetch_gen_walker_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_walker_debug_t f;
+} tcb_fetch_gen_walker_debug_u;
+
+
+/*
+ * TCB_FETCH_GEN_PIPE0_DEBUG struct
+ */
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000
+#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \
+     (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \
+      TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \
+     ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \
+      (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \
+      (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \
+      (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \
+      (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \
+      (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \
+      (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \
+      (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \
+      (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \
+      (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \
+      (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT))
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \
+     ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT)
+#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \
+     tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcb_fetch_gen_pipe0_debug_t {
+          unsigned int                                : 1;
+          unsigned int arb_rtr                        : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE;
+          unsigned int                                : 1;
+          unsigned int valid_q                        : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE;
+          unsigned int mc_sel_q                       : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE;
+          unsigned int ga_busy                        : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE;
+          unsigned int fgo_busy                       : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE;
+          unsigned int busy                           : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE;
+          unsigned int tc_arb_request_type            : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE;
+          unsigned int tc_arb_fmsopcode               : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE;
+          unsigned int tc_arb_format                  : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE;
+          unsigned int                                : 1;
+          unsigned int ga_out_rts                     : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE;
+          unsigned int                                : 1;
+          unsigned int tc0_arb_rts                    : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE;
+     } tcb_fetch_gen_pipe0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcb_fetch_gen_pipe0_debug_t f;
+} tcb_fetch_gen_pipe0_debug_u;
+
+
+/*
+ * TCD_INPUT0_DEBUG struct
+ */
+
+#define TCD_INPUT0_DEBUG_empty_SIZE    1
+#define TCD_INPUT0_DEBUG_full_SIZE     1
+#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_cnt_q1_SIZE   2
+#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1
+#define TCD_INPUT0_DEBUG_ip_send_SIZE  1
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1
+
+#define TCD_INPUT0_DEBUG_empty_SHIFT   16
+#define TCD_INPUT0_DEBUG_full_SHIFT    17
+#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20
+#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT  21
+#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23
+#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25
+#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26
+
+#define TCD_INPUT0_DEBUG_empty_MASK    0x00010000
+#define TCD_INPUT0_DEBUG_full_MASK     0x00020000
+#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000
+#define TCD_INPUT0_DEBUG_cnt_q1_MASK   0x00600000
+#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000
+#define TCD_INPUT0_DEBUG_ip_send_MASK  0x01000000
+#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000
+#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000
+
+#define TCD_INPUT0_DEBUG_MASK \
+     (TCD_INPUT0_DEBUG_empty_MASK | \
+      TCD_INPUT0_DEBUG_full_MASK | \
+      TCD_INPUT0_DEBUG_valid_q1_MASK | \
+      TCD_INPUT0_DEBUG_cnt_q1_MASK | \
+      TCD_INPUT0_DEBUG_last_send_q1_MASK | \
+      TCD_INPUT0_DEBUG_ip_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \
+      TCD_INPUT0_DEBUG_ipbuf_busy_MASK)
+
+#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \
+     ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \
+      (full << TCD_INPUT0_DEBUG_full_SHIFT) | \
+      (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \
+      (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \
+      (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \
+      (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \
+      (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \
+      (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT))
+
+#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \
+     ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT)
+#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \
+     tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 16;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int                                : 2;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int                                : 5;
+     } tcd_input0_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_input0_debug_t {
+          unsigned int                                : 5;
+          unsigned int ipbuf_busy                     : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE;
+          unsigned int ipbuf_dxt_send                 : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE;
+          unsigned int ip_send                        : TCD_INPUT0_DEBUG_ip_send_SIZE;
+          unsigned int last_send_q1                   : TCD_INPUT0_DEBUG_last_send_q1_SIZE;
+          unsigned int cnt_q1                         : TCD_INPUT0_DEBUG_cnt_q1_SIZE;
+          unsigned int valid_q1                       : TCD_INPUT0_DEBUG_valid_q1_SIZE;
+          unsigned int                                : 2;
+          unsigned int full                           : TCD_INPUT0_DEBUG_full_SIZE;
+          unsigned int empty                          : TCD_INPUT0_DEBUG_empty_SIZE;
+          unsigned int                                : 16;
+     } tcd_input0_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_input0_debug_t f;
+} tcd_input0_debug_u;
+
+
+/*
+ * TCD_DEGAMMA_DEBUG struct
+ */
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6
+
+#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008
+#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010
+#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020
+#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040
+
+#define TCD_DEGAMMA_DEBUG_MASK \
+     (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \
+      TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK)
+
+#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \
+     ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \
+      (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \
+      (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \
+      (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \
+      (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \
+      (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT))
+
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \
+     ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT)
+#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \
+     tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int                                : 25;
+     } tcd_degamma_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_degamma_debug_t {
+          unsigned int                                : 25;
+          unsigned int dgmm_pstate                    : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE;
+          unsigned int dgmm_stall                     : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE;
+          unsigned int dgmm_ctrl_send                 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE;
+          unsigned int dgmm_ctrl_last_send            : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE;
+          unsigned int dgmm_ctrl_dgmm8                : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE;
+          unsigned int dgmm_ftfconv_dgmmen            : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE;
+     } tcd_degamma_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_degamma_debug_t f;
+} tcd_degamma_debug_u;
+
+
+/*
+ * TCD_DXTMUX_SCTARB_DEBUG struct
+ */
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29
+
+#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000
+#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000
+#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000
+
+#define TCD_DXTMUX_SCTARB_DEBUG_MASK \
+     (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \
+      TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK)
+
+#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \
+     ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \
+      (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \
+      (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \
+      (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \
+      (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \
+      (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \
+      (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \
+      (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \
+      (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT))
+
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \
+     ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT)
+#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \
+     tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 9;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int                                : 2;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtmux_sctarb_debug_t {
+          unsigned int                                : 2;
+          unsigned int dcmp_mux_send                  : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE;
+          unsigned int dxtc_dgmmpd_send               : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE;
+          unsigned int dxtc_dgmmpd_last_send          : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE;
+          unsigned int                                : 6;
+          unsigned int dxtc_sctrarb_send              : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int sctrmx0_sctrarb_rts            : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE;
+          unsigned int sctrarb_multcyl_send           : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE;
+          unsigned int                                : 3;
+          unsigned int dxtc_rtr                       : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE;
+          unsigned int sctrmx_rtr                     : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE;
+          unsigned int pstate                         : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE;
+          unsigned int                                : 9;
+     } tcd_dxtmux_sctarb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtmux_sctarb_debug_t f;
+} tcd_dxtmux_sctarb_debug_u;
+
+
+/*
+ * TCD_DXTC_ARB_DEBUG struct
+ */
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4
+#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31
+
+#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010
+#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000
+#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000
+#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000
+
+#define TCD_DXTC_ARB_DEBUG_MASK \
+     (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \
+      TCD_DXTC_ARB_DEBUG_pstate_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \
+      TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \
+      TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK)
+
+#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \
+     ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \
+      (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \
+      (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \
+      (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \
+      (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \
+      (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \
+      (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \
+      (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \
+      (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT))
+
+#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \
+     ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT)
+#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \
+     tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int                                : 4;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+     } tcd_dxtc_arb_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_dxtc_arb_debug_t {
+          unsigned int n0_dxt2_4_types                : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE;
+          unsigned int arb_dcmp01_send                : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE;
+          unsigned int arb_dcmp01_format              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE;
+          unsigned int arb_dcmp01_cacheline           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE;
+          unsigned int arb_dcmp01_sector              : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE;
+          unsigned int arb_dcmp01_cnt                 : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE;
+          unsigned int arb_dcmp01_last_send           : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE;
+          unsigned int pstate                         : TCD_DXTC_ARB_DEBUG_pstate_SIZE;
+          unsigned int n0_stall                       : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE;
+          unsigned int                                : 4;
+     } tcd_dxtc_arb_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_dxtc_arb_debug_t f;
+} tcd_dxtc_arb_debug_u;
+
+
+/*
+ * TCD_STALLS_DEBUG struct
+ */
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19
+#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31
+
+#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400
+#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800
+#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000
+#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000
+#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000
+#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000
+
+#define TCD_STALLS_DEBUG_MASK \
+     (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \
+      TCD_STALLS_DEBUG_not_incoming_rtr_MASK)
+
+#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \
+     ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \
+      (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \
+      (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \
+      (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \
+      (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \
+      (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT))
+
+#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \
+     ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT)
+#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \
+     tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int                                : 10;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+     } tcd_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tcd_stalls_debug_t {
+          unsigned int not_incoming_rtr               : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE;
+          unsigned int                                : 11;
+          unsigned int not_mux_dcmp_rtr               : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE;
+          unsigned int not_dgmmpd_dxtc_rtr            : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE;
+          unsigned int not_dcmp0_arb_rtr              : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE;
+          unsigned int                                : 5;
+          unsigned int not_sctrmx0_sctrarb_rtr        : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE;
+          unsigned int not_multcyl_sctrarb_rtr        : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE;
+          unsigned int                                : 10;
+     } tcd_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tcd_stalls_debug_t f;
+} tcd_stalls_debug_u;
+
+
+/*
+ * TCO_STALLS_DEBUG struct
+ */
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7
+
+#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020
+#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040
+#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080
+
+#define TCO_STALLS_DEBUG_MASK \
+     (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \
+      TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK)
+
+#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \
+     ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \
+      (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \
+      (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT))
+
+#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \
+     ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT)
+#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \
+     tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 5;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int                                : 24;
+     } tco_stalls_debug_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_stalls_debug_t {
+          unsigned int                                : 24;
+          unsigned int quad0_tco_tcb_rtr_d            : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE;
+          unsigned int quad0_rl_sg_rtr                : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE;
+          unsigned int quad0_sg_crd_rtr               : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE;
+          unsigned int                                : 5;
+     } tco_stalls_debug_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_stalls_debug_t f;
+} tco_stalls_debug_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG0 struct
+ */
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1
+#define TCO_QUAD0_DEBUG0_busy_SIZE     1
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16
+#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29
+#define TCO_QUAD0_DEBUG0_busy_SHIFT    30
+
+#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff
+#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100
+#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200
+#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400
+#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800
+#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000
+#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000
+#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000
+#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000
+#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000
+#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000
+#define TCO_QUAD0_DEBUG0_busy_MASK     0x40000000
+
+#define TCO_QUAD0_DEBUG0_MASK \
+     (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \
+      TCO_QUAD0_DEBUG0_read_cache_q_MASK | \
+      TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \
+      TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \
+      TCO_QUAD0_DEBUG0_busy_MASK)
+
+#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \
+     ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \
+      (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \
+      (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \
+      (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \
+      (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \
+      (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \
+      (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \
+      (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \
+      (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \
+      (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \
+      (busy << TCO_QUAD0_DEBUG0_busy_SHIFT))
+
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \
+     ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT)
+#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \
+     tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int                                : 2;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug0_t {
+          unsigned int                                : 1;
+          unsigned int busy                           : TCO_QUAD0_DEBUG0_busy_SIZE;
+          unsigned int all_sectors_written_set0       : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE;
+          unsigned int all_sectors_written_set1       : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE;
+          unsigned int all_sectors_written_set2       : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE;
+          unsigned int all_sectors_written_set3       : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE;
+          unsigned int cache_read_rtr                 : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE;
+          unsigned int read_cache_q                   : TCO_QUAD0_DEBUG0_read_cache_q_SIZE;
+          unsigned int                                : 7;
+          unsigned int stagen1_valid_q                : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE;
+          unsigned int                                : 2;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_end_of_sample           : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_end_of_sample            : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE;
+          unsigned int rl_sg_sector_format            : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE;
+     } tco_quad0_debug0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug0_t f;
+} tco_quad0_debug0_u;
+
+
+/*
+ * TCO_QUAD0_DEBUG1 struct
+ */
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_empty_SIZE    1
+#define TCO_QUAD0_DEBUG1_full_SIZE     1
+#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0
+#define TCO_QUAD0_DEBUG1_empty_SHIFT   1
+#define TCO_QUAD0_DEBUG1_full_SHIFT    2
+#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11
+#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21
+#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30
+
+#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001
+#define TCO_QUAD0_DEBUG1_empty_MASK    0x00000002
+#define TCO_QUAD0_DEBUG1_full_MASK     0x00000004
+#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008
+#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0
+#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800
+#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000
+#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000
+#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000
+#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000
+#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000
+#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000
+#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000
+#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000
+
+#define TCO_QUAD0_DEBUG1_MASK \
+     (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_empty_MASK | \
+      TCO_QUAD0_DEBUG1_full_MASK | \
+      TCO_QUAD0_DEBUG1_write_enable_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \
+      TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \
+      TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \
+      TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \
+      TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \
+      TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \
+      TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \
+      TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK)
+
+#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \
+     ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \
+      (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \
+      (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \
+      (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \
+      (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \
+      (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \
+      (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \
+      (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \
+      (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \
+      (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \
+      (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \
+      (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \
+      (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \
+      (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \
+      (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \
+      (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \
+      (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT))
+
+#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \
+     ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT)
+#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \
+     tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int                                : 2;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int                                : 1;
+     } tco_quad0_debug1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _tco_quad0_debug1_t {
+          unsigned int                                : 1;
+          unsigned int tco_tcb_read_xfc               : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE;
+          unsigned int sg_crd_rts                     : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE;
+          unsigned int sg_crd_rtr                     : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE;
+          unsigned int rl_sg_rts                      : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE;
+          unsigned int rl_sg_rtr                      : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE;
+          unsigned int tcb_tco_xfc_q                  : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE;
+          unsigned int tcb_tco_rtr_d                  : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE;
+          unsigned int tco_quad_pipe_busy             : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE;
+          unsigned int input_quad_busy                : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE;
+          unsigned int latency_fifo_busy              : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE;
+          unsigned int cache_read_busy                : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE;
+          unsigned int                                : 2;
+          unsigned int fifo_read_ptr                  : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE;
+          unsigned int fifo_write_ptr                 : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE;
+          unsigned int write_enable                   : TCO_QUAD0_DEBUG1_write_enable_SIZE;
+          unsigned int full                           : TCO_QUAD0_DEBUG1_full_SIZE;
+          unsigned int empty                          : TCO_QUAD0_DEBUG1_empty_SIZE;
+          unsigned int fifo_busy                      : TCO_QUAD0_DEBUG1_fifo_busy_SIZE;
+     } tco_quad0_debug1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     tco_quad0_debug1_t f;
+} tco_quad0_debug1_u;
+
+
+#endif
+
+
+#if !defined (_TC_FIDDLE_H)
+#define _TC_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_SC_FIDDLE_H)
+#define _SC_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+#endif
+
+
+#if !defined (_BC_FIDDLE_H)
+#define _BC_FIDDLE_H
+
+/*******************************************************
+ * Enums
+ *******************************************************/
+
+
+/*******************************************************
+ * Values
+ *******************************************************/
+
+
+/*******************************************************
+ * Structures
+ *******************************************************/
+
+/*
+ * RB_SURFACE_INFO struct
+ */
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0
+#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14
+
+#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff
+#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000
+
+#define RB_SURFACE_INFO_MASK \
+     (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \
+      RB_SURFACE_INFO_MSAA_SAMPLES_MASK)
+
+#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \
+     ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \
+      (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT))
+
+#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \
+     ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT)
+#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \
+     rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int                                : 16;
+     } rb_surface_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_surface_info_t {
+          unsigned int                                : 16;
+          unsigned int msaa_samples                   : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE;
+          unsigned int surface_pitch                  : RB_SURFACE_INFO_SURFACE_PITCH_SIZE;
+     } rb_surface_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_surface_info_t f;
+} rb_surface_info_u;
+
+
+/*
+ * RB_COLOR_INFO struct
+ */
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2
+#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1
+#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2
+#define RB_COLOR_INFO_COLOR_SWAP_SIZE  2
+#define RB_COLOR_INFO_COLOR_BASE_SIZE  20
+
+#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4
+#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6
+#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7
+#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9
+#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12
+
+#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f
+#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030
+#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040
+#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180
+#define RB_COLOR_INFO_COLOR_SWAP_MASK  0x00000600
+#define RB_COLOR_INFO_COLOR_BASE_MASK  0xfffff000
+
+#define RB_COLOR_INFO_MASK \
+     (RB_COLOR_INFO_COLOR_FORMAT_MASK | \
+      RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \
+      RB_COLOR_INFO_COLOR_LINEAR_MASK | \
+      RB_COLOR_INFO_COLOR_ENDIAN_MASK | \
+      RB_COLOR_INFO_COLOR_SWAP_MASK | \
+      RB_COLOR_INFO_COLOR_BASE_MASK)
+
+#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \
+     ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \
+      (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \
+      (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \
+      (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \
+      (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \
+      (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT))
+
+#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \
+     ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT)
+#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \
+     rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+     } rb_color_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_info_t {
+          unsigned int color_base                     : RB_COLOR_INFO_COLOR_BASE_SIZE;
+          unsigned int                                : 1;
+          unsigned int color_swap                     : RB_COLOR_INFO_COLOR_SWAP_SIZE;
+          unsigned int color_endian                   : RB_COLOR_INFO_COLOR_ENDIAN_SIZE;
+          unsigned int color_linear                   : RB_COLOR_INFO_COLOR_LINEAR_SIZE;
+          unsigned int color_round_mode               : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE;
+          unsigned int color_format                   : RB_COLOR_INFO_COLOR_FORMAT_SIZE;
+     } rb_color_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_info_t f;
+} rb_color_info_u;
+
+
+/*
+ * RB_DEPTH_INFO struct
+ */
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1
+#define RB_DEPTH_INFO_DEPTH_BASE_SIZE  20
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0
+#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12
+
+#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001
+#define RB_DEPTH_INFO_DEPTH_BASE_MASK  0xfffff000
+
+#define RB_DEPTH_INFO_MASK \
+     (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \
+      RB_DEPTH_INFO_DEPTH_BASE_MASK)
+
+#define RB_DEPTH_INFO(depth_format, depth_base) \
+     ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \
+      (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT))
+
+#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \
+     ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT)
+#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \
+     rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+     } rb_depth_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_info_t {
+          unsigned int depth_base                     : RB_DEPTH_INFO_DEPTH_BASE_SIZE;
+          unsigned int                                : 11;
+          unsigned int depth_format                   : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE;
+     } rb_depth_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_info_t f;
+} rb_depth_info_u;
+
+
+/*
+ * RB_STENCILREFMASK struct
+ */
+
+#define RB_STENCILREFMASK_STENCILREF_SIZE 8
+#define RB_STENCILREFMASK_STENCILMASK_SIZE 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8
+#define RB_STENCILREFMASK_RESERVED0_SIZE 1
+#define RB_STENCILREFMASK_RESERVED1_SIZE 1
+
+#define RB_STENCILREFMASK_STENCILREF_SHIFT 0
+#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8
+#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
+#define RB_STENCILREFMASK_RESERVED0_SHIFT 24
+#define RB_STENCILREFMASK_RESERVED1_SHIFT 25
+
+#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
+#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
+#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000
+#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000
+#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000
+
+#define RB_STENCILREFMASK_MASK \
+     (RB_STENCILREFMASK_STENCILREF_MASK | \
+      RB_STENCILREFMASK_STENCILMASK_MASK | \
+      RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \
+      RB_STENCILREFMASK_RESERVED0_MASK | \
+      RB_STENCILREFMASK_RESERVED1_MASK)
+
+#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \
+     ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \
+      (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \
+      (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \
+      (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \
+      (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT))
+
+#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \
+     ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT)
+#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \
+     rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_t {
+          unsigned int                                : 6;
+          unsigned int reserved1                      : RB_STENCILREFMASK_RESERVED1_SIZE;
+          unsigned int reserved0                      : RB_STENCILREFMASK_RESERVED0_SIZE;
+          unsigned int stencilwritemask               : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE;
+          unsigned int stencilmask                    : RB_STENCILREFMASK_STENCILMASK_SIZE;
+          unsigned int stencilref                     : RB_STENCILREFMASK_STENCILREF_SIZE;
+     } rb_stencilrefmask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_t f;
+} rb_stencilrefmask_u;
+
+
+/*
+ * RB_ALPHA_REF struct
+ */
+
+#define RB_ALPHA_REF_ALPHA_REF_SIZE    32
+
+#define RB_ALPHA_REF_ALPHA_REF_SHIFT   0
+
+#define RB_ALPHA_REF_ALPHA_REF_MASK    0xffffffff
+
+#define RB_ALPHA_REF_MASK \
+     (RB_ALPHA_REF_ALPHA_REF_MASK)
+
+#define RB_ALPHA_REF(alpha_ref) \
+     ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT))
+
+#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \
+     ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \
+     rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_alpha_ref_t {
+          unsigned int alpha_ref                      : RB_ALPHA_REF_ALPHA_REF_SIZE;
+     } rb_alpha_ref_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_alpha_ref_t f;
+} rb_alpha_ref_u;
+
+
+/*
+ * RB_COLOR_MASK struct
+ */
+
+#define RB_COLOR_MASK_WRITE_RED_SIZE   1
+#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1
+#define RB_COLOR_MASK_WRITE_BLUE_SIZE  1
+#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1
+#define RB_COLOR_MASK_RESERVED2_SIZE   1
+#define RB_COLOR_MASK_RESERVED3_SIZE   1
+
+#define RB_COLOR_MASK_WRITE_RED_SHIFT  0
+#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1
+#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2
+#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3
+#define RB_COLOR_MASK_RESERVED2_SHIFT  4
+#define RB_COLOR_MASK_RESERVED3_SHIFT  5
+
+#define RB_COLOR_MASK_WRITE_RED_MASK   0x00000001
+#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002
+#define RB_COLOR_MASK_WRITE_BLUE_MASK  0x00000004
+#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008
+#define RB_COLOR_MASK_RESERVED2_MASK   0x00000010
+#define RB_COLOR_MASK_RESERVED3_MASK   0x00000020
+
+#define RB_COLOR_MASK_MASK \
+     (RB_COLOR_MASK_WRITE_RED_MASK | \
+      RB_COLOR_MASK_WRITE_GREEN_MASK | \
+      RB_COLOR_MASK_WRITE_BLUE_MASK | \
+      RB_COLOR_MASK_WRITE_ALPHA_MASK | \
+      RB_COLOR_MASK_RESERVED2_MASK | \
+      RB_COLOR_MASK_RESERVED3_MASK)
+
+#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \
+     ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \
+      (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \
+      (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \
+      (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \
+      (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \
+      (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT))
+
+#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \
+     ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT)
+#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT)
+#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \
+     rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int                                : 26;
+     } rb_color_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_mask_t {
+          unsigned int                                : 26;
+          unsigned int reserved3                      : RB_COLOR_MASK_RESERVED3_SIZE;
+          unsigned int reserved2                      : RB_COLOR_MASK_RESERVED2_SIZE;
+          unsigned int write_alpha                    : RB_COLOR_MASK_WRITE_ALPHA_SIZE;
+          unsigned int write_blue                     : RB_COLOR_MASK_WRITE_BLUE_SIZE;
+          unsigned int write_green                    : RB_COLOR_MASK_WRITE_GREEN_SIZE;
+          unsigned int write_red                      : RB_COLOR_MASK_WRITE_RED_SIZE;
+     } rb_color_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_mask_t f;
+} rb_color_mask_u;
+
+
+/*
+ * RB_BLEND_RED struct
+ */
+
+#define RB_BLEND_RED_BLEND_RED_SIZE    8
+
+#define RB_BLEND_RED_BLEND_RED_SHIFT   0
+
+#define RB_BLEND_RED_BLEND_RED_MASK    0x000000ff
+
+#define RB_BLEND_RED_MASK \
+     (RB_BLEND_RED_BLEND_RED_MASK)
+
+#define RB_BLEND_RED(blend_red) \
+     ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT))
+
+#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \
+     ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \
+     rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_red_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_red_t {
+          unsigned int                                : 24;
+          unsigned int blend_red                      : RB_BLEND_RED_BLEND_RED_SIZE;
+     } rb_blend_red_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_red_t f;
+} rb_blend_red_u;
+
+
+/*
+ * RB_BLEND_GREEN struct
+ */
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8
+
+#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0
+
+#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff
+
+#define RB_BLEND_GREEN_MASK \
+     (RB_BLEND_GREEN_BLEND_GREEN_MASK)
+
+#define RB_BLEND_GREEN(blend_green) \
+     ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT))
+
+#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \
+     ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \
+     rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_green_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_green_t {
+          unsigned int                                : 24;
+          unsigned int blend_green                    : RB_BLEND_GREEN_BLEND_GREEN_SIZE;
+     } rb_blend_green_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_green_t f;
+} rb_blend_green_u;
+
+
+/*
+ * RB_BLEND_BLUE struct
+ */
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SIZE  8
+
+#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0
+
+#define RB_BLEND_BLUE_BLEND_BLUE_MASK  0x000000ff
+
+#define RB_BLEND_BLUE_MASK \
+     (RB_BLEND_BLUE_BLEND_BLUE_MASK)
+
+#define RB_BLEND_BLUE(blend_blue) \
+     ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT))
+
+#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \
+     ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \
+     rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_blue_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_blue_t {
+          unsigned int                                : 24;
+          unsigned int blend_blue                     : RB_BLEND_BLUE_BLEND_BLUE_SIZE;
+     } rb_blend_blue_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_blue_t f;
+} rb_blend_blue_u;
+
+
+/*
+ * RB_BLEND_ALPHA struct
+ */
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0
+
+#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff
+
+#define RB_BLEND_ALPHA_MASK \
+     (RB_BLEND_ALPHA_BLEND_ALPHA_MASK)
+
+#define RB_BLEND_ALPHA(blend_alpha) \
+     ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT))
+
+#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \
+     ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \
+     rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+          unsigned int                                : 24;
+     } rb_blend_alpha_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blend_alpha_t {
+          unsigned int                                : 24;
+          unsigned int blend_alpha                    : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE;
+     } rb_blend_alpha_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blend_alpha_t f;
+} rb_blend_alpha_u;
+
+
+/*
+ * RB_FOG_COLOR struct
+ */
+
+#define RB_FOG_COLOR_FOG_RED_SIZE      8
+#define RB_FOG_COLOR_FOG_GREEN_SIZE    8
+#define RB_FOG_COLOR_FOG_BLUE_SIZE     8
+
+#define RB_FOG_COLOR_FOG_RED_SHIFT     0
+#define RB_FOG_COLOR_FOG_GREEN_SHIFT   8
+#define RB_FOG_COLOR_FOG_BLUE_SHIFT    16
+
+#define RB_FOG_COLOR_FOG_RED_MASK      0x000000ff
+#define RB_FOG_COLOR_FOG_GREEN_MASK    0x0000ff00
+#define RB_FOG_COLOR_FOG_BLUE_MASK     0x00ff0000
+
+#define RB_FOG_COLOR_MASK \
+     (RB_FOG_COLOR_FOG_RED_MASK | \
+      RB_FOG_COLOR_FOG_GREEN_MASK | \
+      RB_FOG_COLOR_FOG_BLUE_MASK)
+
+#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \
+     ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \
+      (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \
+      (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT))
+
+#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \
+     ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT)
+#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \
+     rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int                                : 8;
+     } rb_fog_color_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_fog_color_t {
+          unsigned int                                : 8;
+          unsigned int fog_blue                       : RB_FOG_COLOR_FOG_BLUE_SIZE;
+          unsigned int fog_green                      : RB_FOG_COLOR_FOG_GREEN_SIZE;
+          unsigned int fog_red                        : RB_FOG_COLOR_FOG_RED_SIZE;
+     } rb_fog_color_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_fog_color_t f;
+} rb_fog_color_u;
+
+
+/*
+ * RB_STENCILREFMASK_BF struct
+ */
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8
+#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1
+#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16
+#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24
+#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25
+
+#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff
+#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00
+#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000
+#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000
+#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000
+
+#define RB_STENCILREFMASK_BF_MASK \
+     (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED4_MASK | \
+      RB_STENCILREFMASK_BF_RESERVED5_MASK)
+
+#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \
+     ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \
+      (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \
+      (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \
+      (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \
+      (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT))
+
+#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \
+     ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT)
+#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \
+     rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int                                : 6;
+     } rb_stencilrefmask_bf_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_stencilrefmask_bf_t {
+          unsigned int                                : 6;
+          unsigned int reserved5                      : RB_STENCILREFMASK_BF_RESERVED5_SIZE;
+          unsigned int reserved4                      : RB_STENCILREFMASK_BF_RESERVED4_SIZE;
+          unsigned int stencilwritemask_bf            : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE;
+          unsigned int stencilmask_bf                 : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE;
+          unsigned int stencilref_bf                  : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE;
+     } rb_stencilrefmask_bf_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_stencilrefmask_bf_t f;
+} rb_stencilrefmask_bf_u;
+
+
+/*
+ * RB_DEPTHCONTROL struct
+ */
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_Z_ENABLE_SIZE  1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_ZFUNC_SIZE     3
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1
+#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0
+#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3
+#define RB_DEPTHCONTROL_ZFUNC_SHIFT    4
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7
+#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8
+#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11
+#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14
+#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29
+
+#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001
+#define RB_DEPTHCONTROL_Z_ENABLE_MASK  0x00000002
+#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004
+#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008
+#define RB_DEPTHCONTROL_ZFUNC_MASK     0x00000070
+#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080
+#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700
+#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800
+#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000
+#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000
+#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000
+#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000
+#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000
+#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000
+
+#define RB_DEPTHCONTROL_MASK \
+     (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \
+      RB_DEPTHCONTROL_ZFUNC_MASK | \
+      RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_MASK | \
+      RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \
+      RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK)
+
+#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \
+     ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \
+      (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \
+      (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \
+      (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \
+      (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \
+      (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \
+      (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \
+      (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \
+      (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \
+      (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \
+      (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \
+      (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \
+      (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \
+      (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT))
+
+#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \
+     ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT)
+#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \
+     rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+     } rb_depthcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depthcontrol_t {
+          unsigned int stencilzfail_bf                : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE;
+          unsigned int stencilzpass_bf                : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE;
+          unsigned int stencilfail_bf                 : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE;
+          unsigned int stencilfunc_bf                 : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE;
+          unsigned int stencilzfail                   : RB_DEPTHCONTROL_STENCILZFAIL_SIZE;
+          unsigned int stencilzpass                   : RB_DEPTHCONTROL_STENCILZPASS_SIZE;
+          unsigned int stencilfail                    : RB_DEPTHCONTROL_STENCILFAIL_SIZE;
+          unsigned int stencilfunc                    : RB_DEPTHCONTROL_STENCILFUNC_SIZE;
+          unsigned int backface_enable                : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE;
+          unsigned int zfunc                          : RB_DEPTHCONTROL_ZFUNC_SIZE;
+          unsigned int early_z_enable                 : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE;
+          unsigned int z_write_enable                 : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE;
+          unsigned int z_enable                       : RB_DEPTHCONTROL_Z_ENABLE_SIZE;
+          unsigned int stencil_enable                 : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE;
+     } rb_depthcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depthcontrol_t f;
+} rb_depthcontrol_u;
+
+
+/*
+ * RB_BLENDCONTROL struct
+ */
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1
+#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29
+#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30
+
+#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f
+#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0
+#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00
+#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000
+#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000
+#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000
+#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000
+#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000
+
+#define RB_BLENDCONTROL_MASK \
+     (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \
+      RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \
+      RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \
+      RB_BLENDCONTROL_BLEND_FORCE_MASK)
+
+#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \
+     ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \
+      (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \
+      (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \
+      (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \
+      (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \
+      (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \
+      (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \
+      (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT))
+
+#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \
+     ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT)
+#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT)
+#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \
+     rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int                                : 1;
+     } rb_blendcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_blendcontrol_t {
+          unsigned int                                : 1;
+          unsigned int blend_force                    : RB_BLENDCONTROL_BLEND_FORCE_SIZE;
+          unsigned int blend_force_enable             : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE;
+          unsigned int alpha_destblend                : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE;
+          unsigned int alpha_comb_fcn                 : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE;
+          unsigned int alpha_srcblend                 : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE;
+          unsigned int                                : 3;
+          unsigned int color_destblend                : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE;
+          unsigned int color_comb_fcn                 : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE;
+          unsigned int color_srcblend                 : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE;
+     } rb_blendcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_blendcontrol_t f;
+} rb_blendcontrol_u;
+
+
+/*
+ * RB_COLORCONTROL struct
+ */
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1
+#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1
+#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1
+#define RB_COLORCONTROL_ROP_CODE_SIZE  4
+#define RB_COLORCONTROL_DITHER_MODE_SIZE 2
+#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2
+#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2
+
+#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4
+#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5
+#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7
+#define RB_COLORCONTROL_ROP_CODE_SHIFT 8
+#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12
+#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14
+#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30
+
+#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007
+#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008
+#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010
+#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020
+#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040
+#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080
+#define RB_COLORCONTROL_ROP_CODE_MASK  0x00000f00
+#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000
+#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000
+#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000
+#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000
+
+#define RB_COLORCONTROL_MASK \
+     (RB_COLORCONTROL_ALPHA_FUNC_MASK | \
+      RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \
+      RB_COLORCONTROL_BLEND_DISABLE_MASK | \
+      RB_COLORCONTROL_FOG_ENABLE_MASK | \
+      RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \
+      RB_COLORCONTROL_ROP_CODE_MASK | \
+      RB_COLORCONTROL_DITHER_MODE_MASK | \
+      RB_COLORCONTROL_DITHER_TYPE_MASK | \
+      RB_COLORCONTROL_PIXEL_FOG_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \
+      RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK)
+
+#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \
+     ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \
+      (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \
+      (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \
+      (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \
+      (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \
+      (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \
+      (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \
+      (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \
+      (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \
+      (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \
+      (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \
+      (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \
+      (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \
+      (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT))
+
+#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \
+     ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT)
+#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT)
+#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT)
+#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT)
+#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT)
+#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \
+     rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int                                : 7;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+     } rb_colorcontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_colorcontrol_t {
+          unsigned int alpha_to_mask_offset3          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE;
+          unsigned int alpha_to_mask_offset2          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE;
+          unsigned int alpha_to_mask_offset1          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE;
+          unsigned int alpha_to_mask_offset0          : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE;
+          unsigned int                                : 7;
+          unsigned int pixel_fog                      : RB_COLORCONTROL_PIXEL_FOG_SIZE;
+          unsigned int dither_type                    : RB_COLORCONTROL_DITHER_TYPE_SIZE;
+          unsigned int dither_mode                    : RB_COLORCONTROL_DITHER_MODE_SIZE;
+          unsigned int rop_code                       : RB_COLORCONTROL_ROP_CODE_SIZE;
+          unsigned int vs_exports_fog                 : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE;
+          unsigned int fog_enable                     : RB_COLORCONTROL_FOG_ENABLE_SIZE;
+          unsigned int blend_disable                  : RB_COLORCONTROL_BLEND_DISABLE_SIZE;
+          unsigned int alpha_to_mask_enable           : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE;
+          unsigned int alpha_test_enable              : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE;
+          unsigned int alpha_func                     : RB_COLORCONTROL_ALPHA_FUNC_SIZE;
+     } rb_colorcontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_colorcontrol_t f;
+} rb_colorcontrol_u;
+
+
+/*
+ * RB_MODECONTROL struct
+ */
+
+#define RB_MODECONTROL_EDRAM_MODE_SIZE 3
+
+#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0
+
+#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007
+
+#define RB_MODECONTROL_MASK \
+     (RB_MODECONTROL_EDRAM_MODE_MASK)
+
+#define RB_MODECONTROL(edram_mode) \
+     ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT))
+
+#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \
+     ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \
+     rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+          unsigned int                                : 29;
+     } rb_modecontrol_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_modecontrol_t {
+          unsigned int                                : 29;
+          unsigned int edram_mode                     : RB_MODECONTROL_EDRAM_MODE_SIZE;
+     } rb_modecontrol_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_modecontrol_t f;
+} rb_modecontrol_u;
+
+
+/*
+ * RB_COLOR_DEST_MASK struct
+ */
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0
+
+#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff
+
+#define RB_COLOR_DEST_MASK_MASK \
+     (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK)
+
+#define RB_COLOR_DEST_MASK(color_dest_mask) \
+     ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT))
+
+#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \
+     ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \
+     rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_color_dest_mask_t {
+          unsigned int color_dest_mask                : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE;
+     } rb_color_dest_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_color_dest_mask_t f;
+} rb_color_dest_mask_u;
+
+
+/*
+ * RB_COPY_CONTROL struct
+ */
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1
+#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3
+#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4
+
+#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007
+#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008
+#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0
+
+#define RB_COPY_CONTROL_MASK \
+     (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \
+      RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \
+      RB_COPY_CONTROL_CLEAR_MASK_MASK)
+
+#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \
+     ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \
+      (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \
+      (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT))
+
+#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \
+     ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT)
+#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT)
+#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \
+     rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int                                : 24;
+     } rb_copy_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_control_t {
+          unsigned int                                : 24;
+          unsigned int clear_mask                     : RB_COPY_CONTROL_CLEAR_MASK_SIZE;
+          unsigned int depth_clear_enable             : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE;
+          unsigned int copy_sample_select             : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE;
+     } rb_copy_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_control_t f;
+} rb_copy_control_u;
+
+
+/*
+ * RB_COPY_DEST_BASE struct
+ */
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12
+
+#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000
+
+#define RB_COPY_DEST_BASE_MASK \
+     (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK)
+
+#define RB_COPY_DEST_BASE(copy_dest_base) \
+     ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT))
+
+#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \
+     ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \
+     rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int                                : 12;
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+     } rb_copy_dest_base_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_base_t {
+          unsigned int copy_dest_base                 : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE;
+          unsigned int                                : 12;
+     } rb_copy_dest_base_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_base_t f;
+} rb_copy_dest_base_u;
+
+
+/*
+ * RB_COPY_DEST_PITCH struct
+ */
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0
+
+#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff
+
+#define RB_COPY_DEST_PITCH_MASK \
+     (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK)
+
+#define RB_COPY_DEST_PITCH(copy_dest_pitch) \
+     ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT))
+
+#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \
+     ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \
+     rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+          unsigned int                                : 23;
+     } rb_copy_dest_pitch_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pitch_t {
+          unsigned int                                : 23;
+          unsigned int copy_dest_pitch                : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE;
+     } rb_copy_dest_pitch_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pitch_t f;
+} rb_copy_dest_pitch_u;
+
+
+/*
+ * RB_COPY_DEST_INFO struct
+ */
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17
+
+#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007
+#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008
+#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0
+#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00
+#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000
+#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000
+
+#define RB_COPY_DEST_INFO_MASK \
+     (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \
+      RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \
+      RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK)
+
+#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \
+     ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \
+      (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \
+      (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \
+      (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \
+      (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \
+      (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \
+      (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \
+      (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \
+      (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \
+      (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT))
+
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \
+     ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT)
+#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \
+     rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int                                : 14;
+     } rb_copy_dest_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_info_t {
+          unsigned int                                : 14;
+          unsigned int copy_mask_write_alpha          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE;
+          unsigned int copy_mask_write_blue           : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE;
+          unsigned int copy_mask_write_green          : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE;
+          unsigned int copy_mask_write_red            : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE;
+          unsigned int copy_dest_dither_type          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE;
+          unsigned int copy_dest_dither_mode          : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE;
+          unsigned int copy_dest_swap                 : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE;
+          unsigned int copy_dest_format               : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE;
+          unsigned int copy_dest_linear               : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE;
+          unsigned int copy_dest_endian               : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE;
+     } rb_copy_dest_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_info_t f;
+} rb_copy_dest_info_u;
+
+
+/*
+ * RB_COPY_DEST_PIXEL_OFFSET struct
+ */
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13
+
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff
+#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000
+
+#define RB_COPY_DEST_PIXEL_OFFSET_MASK \
+     (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \
+      RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK)
+
+#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \
+     ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \
+      (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT))
+
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \
+     ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT)
+#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \
+     rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int                                : 6;
+     } rb_copy_dest_pixel_offset_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_copy_dest_pixel_offset_t {
+          unsigned int                                : 6;
+          unsigned int offset_y                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE;
+          unsigned int offset_x                       : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE;
+     } rb_copy_dest_pixel_offset_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_copy_dest_pixel_offset_t f;
+} rb_copy_dest_pixel_offset_u;
+
+
+/*
+ * RB_DEPTH_CLEAR struct
+ */
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0
+
+#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff
+
+#define RB_DEPTH_CLEAR_MASK \
+     (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK)
+
+#define RB_DEPTH_CLEAR(depth_clear) \
+     ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT))
+
+#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \
+     ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \
+     rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_depth_clear_t {
+          unsigned int depth_clear                    : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE;
+     } rb_depth_clear_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_depth_clear_t f;
+} rb_depth_clear_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_CTL struct
+ */
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1
+
+#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001
+#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002
+
+#define RB_SAMPLE_COUNT_CTL_MASK \
+     (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \
+      RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK)
+
+#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \
+     ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \
+      (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT))
+
+#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \
+     ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT)
+#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \
+     rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int                                : 30;
+     } rb_sample_count_ctl_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_ctl_t {
+          unsigned int                                : 30;
+          unsigned int copy_sample_count              : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE;
+          unsigned int reset_sample_count             : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE;
+     } rb_sample_count_ctl_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_ctl_t f;
+} rb_sample_count_ctl_u;
+
+
+/*
+ * RB_SAMPLE_COUNT_ADDR struct
+ */
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0
+
+#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff
+
+#define RB_SAMPLE_COUNT_ADDR_MASK \
+     (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK)
+
+#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \
+     ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT))
+
+#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \
+     ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \
+     rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sample_count_addr_t {
+          unsigned int sample_count_addr              : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE;
+     } rb_sample_count_addr_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sample_count_addr_t f;
+} rb_sample_count_addr_u;
+
+
+/*
+ * RB_BC_CONTROL struct
+ */
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1
+#define RB_BC_CONTROL_CRC_MODE_SIZE    1
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1
+#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1
+#define RB_BC_CONTROL_CRC_SYSTEM_SIZE  1
+#define RB_BC_CONTROL_RESERVED6_SIZE   1
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14
+#define RB_BC_CONTROL_CRC_MODE_SHIFT   15
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16
+#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29
+#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30
+#define RB_BC_CONTROL_RESERVED6_SHIFT  31
+
+#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001
+#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006
+#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008
+#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010
+#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020
+#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040
+#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080
+#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00
+#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000
+#define RB_BC_CONTROL_CRC_MODE_MASK    0x00008000
+#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000
+#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000
+#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000
+#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000
+#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000
+#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000
+#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000
+#define RB_BC_CONTROL_CRC_SYSTEM_MASK  0x40000000
+#define RB_BC_CONTROL_RESERVED6_MASK   0x80000000
+
+#define RB_BC_CONTROL_MASK \
+     (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \
+      RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \
+      RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \
+      RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \
+      RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \
+      RB_BC_CONTROL_CRC_MODE_MASK | \
+      RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \
+      RB_BC_CONTROL_DISABLE_ACCUM_MASK | \
+      RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \
+      RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \
+      RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \
+      RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \
+      RB_BC_CONTROL_CRC_SYSTEM_MASK | \
+      RB_BC_CONTROL_RESERVED6_MASK)
+
+#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \
+     ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \
+      (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \
+      (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \
+      (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \
+      (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \
+      (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \
+      (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \
+      (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \
+      (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \
+      (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \
+      (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \
+      (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \
+      (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \
+      (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \
+      (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \
+      (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \
+      (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \
+      (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \
+      (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT))
+
+#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \
+     ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT)
+#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT)
+#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT)
+#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT)
+#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT)
+#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT)
+#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT)
+#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \
+     rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int                                : 1;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+     } rb_bc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_control_t {
+          unsigned int reserved6                      : RB_BC_CONTROL_RESERVED6_SIZE;
+          unsigned int crc_system                     : RB_BC_CONTROL_CRC_SYSTEM_SIZE;
+          unsigned int mem_export_linear_mode_enable  : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE;
+          unsigned int mem_export_timeout_select      : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_data_fifo_limit          : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE;
+          unsigned int linear_performance_enable      : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE;
+          unsigned int accum_alloc_mask               : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE;
+          unsigned int disable_accum                  : RB_BC_CONTROL_DISABLE_ACCUM_SIZE;
+          unsigned int disable_sample_counters        : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE;
+          unsigned int crc_mode                       : RB_BC_CONTROL_CRC_MODE_SIZE;
+          unsigned int enable_crc_update              : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE;
+          unsigned int                                : 1;
+          unsigned int az_throttle_count              : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE;
+          unsigned int enable_az_throttle             : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE;
+          unsigned int disable_lz_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_null_zcmd_drop      : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE;
+          unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE;
+          unsigned int disable_edram_cam              : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE;
+          unsigned int accum_timeout_select           : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE;
+          unsigned int accum_linear_mode_enable       : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE;
+     } rb_bc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_control_t f;
+} rb_bc_control_u;
+
+
+/*
+ * RB_EDRAM_INFO struct
+ */
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE  4
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
+#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4
+#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14
+
+#define RB_EDRAM_INFO_EDRAM_SIZE_MASK  0x0000000f
+#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030
+#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000
+
+#define RB_EDRAM_INFO_MASK \
+     (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \
+      RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \
+      RB_EDRAM_INFO_EDRAM_RANGE_MASK)
+
+#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \
+     ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \
+      (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \
+      (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT))
+
+#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \
+     ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT)
+#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \
+     rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+     } rb_edram_info_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_edram_info_t {
+          unsigned int edram_range                    : RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
+          unsigned int                                : 8;
+          unsigned int edram_mapping_mode             : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
+          unsigned int edram_size                     : RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
+     } rb_edram_info_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_edram_info_t f;
+} rb_edram_info_u;
+
+
+/*
+ * RB_CRC_RD_PORT struct
+ */
+
+#define RB_CRC_RD_PORT_CRC_DATA_SIZE   32
+
+#define RB_CRC_RD_PORT_CRC_DATA_SHIFT  0
+
+#define RB_CRC_RD_PORT_CRC_DATA_MASK   0xffffffff
+
+#define RB_CRC_RD_PORT_MASK \
+     (RB_CRC_RD_PORT_CRC_DATA_MASK)
+
+#define RB_CRC_RD_PORT(crc_data) \
+     ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT))
+
+#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \
+     ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \
+     rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_rd_port_t {
+          unsigned int crc_data                       : RB_CRC_RD_PORT_CRC_DATA_SIZE;
+     } rb_crc_rd_port_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_rd_port_t f;
+} rb_crc_rd_port_u;
+
+
+/*
+ * RB_CRC_CONTROL struct
+ */
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0
+
+#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001
+
+#define RB_CRC_CONTROL_MASK \
+     (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK)
+
+#define RB_CRC_CONTROL(crc_rd_advance) \
+     ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT))
+
+#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \
+     ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \
+     rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+          unsigned int                                : 31;
+     } rb_crc_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_control_t {
+          unsigned int                                : 31;
+          unsigned int crc_rd_advance                 : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE;
+     } rb_crc_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_control_t f;
+} rb_crc_control_u;
+
+
+/*
+ * RB_CRC_MASK struct
+ */
+
+#define RB_CRC_MASK_CRC_MASK_SIZE      32
+
+#define RB_CRC_MASK_CRC_MASK_SHIFT     0
+
+#define RB_CRC_MASK_CRC_MASK_MASK      0xffffffff
+
+#define RB_CRC_MASK_MASK \
+     (RB_CRC_MASK_CRC_MASK_MASK)
+
+#define RB_CRC_MASK(crc_mask) \
+     ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT))
+
+#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \
+     ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \
+     rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_crc_mask_t {
+          unsigned int crc_mask                       : RB_CRC_MASK_CRC_MASK_SIZE;
+     } rb_crc_mask_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_crc_mask_t f;
+} rb_crc_mask_u;
+
+
+/*
+ * RB_PERFCOUNTER0_SELECT struct
+ */
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0
+
+#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff
+
+#define RB_PERFCOUNTER0_SELECT_MASK \
+     (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK)
+
+#define RB_PERFCOUNTER0_SELECT(perf_sel) \
+     ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT))
+
+#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \
+     ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \
+     rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+          unsigned int                                : 24;
+     } rb_perfcounter0_select_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_select_t {
+          unsigned int                                : 24;
+          unsigned int perf_sel                       : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE;
+     } rb_perfcounter0_select_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_select_t f;
+} rb_perfcounter0_select_u;
+
+
+/*
+ * RB_PERFCOUNTER0_LOW struct
+ */
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff
+
+#define RB_PERFCOUNTER0_LOW_MASK \
+     (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_LOW(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \
+     ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \
+     rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_low_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE;
+     } rb_perfcounter0_low_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_low_t f;
+} rb_perfcounter0_low_u;
+
+
+/*
+ * RB_PERFCOUNTER0_HI struct
+ */
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0
+
+#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff
+
+#define RB_PERFCOUNTER0_HI_MASK \
+     (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK)
+
+#define RB_PERFCOUNTER0_HI(perf_count) \
+     ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT))
+
+#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \
+     ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \
+     rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+          unsigned int                                : 16;
+     } rb_perfcounter0_hi_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_perfcounter0_hi_t {
+          unsigned int                                : 16;
+          unsigned int perf_count                     : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE;
+     } rb_perfcounter0_hi_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_perfcounter0_hi_t f;
+} rb_perfcounter0_hi_u;
+
+
+/*
+ * RB_TOTAL_SAMPLES struct
+ */
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0
+
+#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff
+
+#define RB_TOTAL_SAMPLES_MASK \
+     (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK)
+
+#define RB_TOTAL_SAMPLES(total_samples) \
+     ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT))
+
+#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \
+     ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \
+     rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_total_samples_t {
+          unsigned int total_samples                  : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE;
+     } rb_total_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_total_samples_t f;
+} rb_total_samples_u;
+
+
+/*
+ * RB_ZPASS_SAMPLES struct
+ */
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0
+
+#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff
+
+#define RB_ZPASS_SAMPLES_MASK \
+     (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK)
+
+#define RB_ZPASS_SAMPLES(zpass_samples) \
+     ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT))
+
+#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \
+     ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \
+     rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zpass_samples_t {
+          unsigned int zpass_samples                  : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE;
+     } rb_zpass_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zpass_samples_t f;
+} rb_zpass_samples_u;
+
+
+/*
+ * RB_ZFAIL_SAMPLES struct
+ */
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0
+
+#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_ZFAIL_SAMPLES_MASK \
+     (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK)
+
+#define RB_ZFAIL_SAMPLES(zfail_samples) \
+     ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT))
+
+#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \
+     ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \
+     rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_zfail_samples_t {
+          unsigned int zfail_samples                  : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE;
+     } rb_zfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_zfail_samples_t f;
+} rb_zfail_samples_u;
+
+
+/*
+ * RB_SFAIL_SAMPLES struct
+ */
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0
+
+#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff
+
+#define RB_SFAIL_SAMPLES_MASK \
+     (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK)
+
+#define RB_SFAIL_SAMPLES(sfail_samples) \
+     ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT))
+
+#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \
+     ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \
+     rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_sfail_samples_t {
+          unsigned int sfail_samples                  : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE;
+     } rb_sfail_samples_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_sfail_samples_t f;
+} rb_sfail_samples_u;
+
+
+/*
+ * RB_DEBUG_0 struct
+ */
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE  1
+#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE  1
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1
+#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE  1
+#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE  1
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1
+#define RB_DEBUG_0_C_REQ_FULL_SIZE     1
+#define RB_DEBUG_0_C_MASK_FULL_SIZE    1
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5
+#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6
+#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7
+#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8
+#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15
+#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16
+#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17
+#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18
+#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25
+#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26
+#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27
+#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28
+#define RB_DEBUG_0_C_REQ_FULL_SHIFT    29
+#define RB_DEBUG_0_C_MASK_FULL_SHIFT   30
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31
+
+#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001
+#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002
+#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004
+#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008
+#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010
+#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020
+#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK  0x00000040
+#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK  0x00000080
+#define RB_DEBUG_0_RDREQ_C1_FULL_MASK  0x00000100
+#define RB_DEBUG_0_RDREQ_C0_FULL_MASK  0x00000200
+#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400
+#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800
+#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000
+#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000
+#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000
+#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000
+#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK  0x00010000
+#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK  0x00020000
+#define RB_DEBUG_0_WRREQ_C1_FULL_MASK  0x00040000
+#define RB_DEBUG_0_WRREQ_C0_FULL_MASK  0x00080000
+#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000
+#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000
+#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000
+#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000
+#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000
+#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000
+#define RB_DEBUG_0_C_SX_LAT_FULL_MASK  0x04000000
+#define RB_DEBUG_0_C_SX_CMD_FULL_MASK  0x08000000
+#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000
+#define RB_DEBUG_0_C_REQ_FULL_MASK     0x20000000
+#define RB_DEBUG_0_C_MASK_FULL_MASK    0x40000000
+#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000
+
+#define RB_DEBUG_0_MASK \
+     (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_RDREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C1_FULL_MASK | \
+      RB_DEBUG_0_WRREQ_C0_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \
+      RB_DEBUG_0_C_SX_LAT_FULL_MASK | \
+      RB_DEBUG_0_C_SX_CMD_FULL_MASK | \
+      RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \
+      RB_DEBUG_0_C_REQ_FULL_MASK | \
+      RB_DEBUG_0_C_MASK_FULL_MASK | \
+      RB_DEBUG_0_EZ_INFSAMP_FULL_MASK)
+
+#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \
+     ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \
+      (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \
+      (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \
+      (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \
+      (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \
+      (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \
+      (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \
+      (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \
+      (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \
+      (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \
+      (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \
+      (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \
+      (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \
+      (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \
+      (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \
+      (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \
+      (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \
+      (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \
+      (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \
+      (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \
+      (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \
+      (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \
+      (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \
+      (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \
+      (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \
+      (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT))
+
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \
+     ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT)
+#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT)
+#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT)
+#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \
+     rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+     } rb_debug_0_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_0_t {
+          unsigned int ez_infsamp_full                : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE;
+          unsigned int c_mask_full                    : RB_DEBUG_0_C_MASK_FULL_SIZE;
+          unsigned int c_req_full                     : RB_DEBUG_0_C_REQ_FULL_SIZE;
+          unsigned int c_ez_tile_full                 : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE;
+          unsigned int c_sx_cmd_full                  : RB_DEBUG_0_C_SX_CMD_FULL_SIZE;
+          unsigned int c_sx_lat_full                  : RB_DEBUG_0_C_SX_LAT_FULL_SIZE;
+          unsigned int cmdfifo_c_ordering_full        : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_z_ordering_full        : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE;
+          unsigned int cmdfifo_c0_hold_full           : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_c1_hold_full           : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z0_hold_full           : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE;
+          unsigned int cmdfifo_z1_hold_full           : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE;
+          unsigned int wrreq_c0_full                  : RB_DEBUG_0_WRREQ_C0_FULL_SIZE;
+          unsigned int wrreq_c1_full                  : RB_DEBUG_0_WRREQ_C1_FULL_SIZE;
+          unsigned int wrreq_z0_full                  : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE;
+          unsigned int wrreq_z1_full                  : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE;
+          unsigned int wrreq_c_we_lo_full             : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE;
+          unsigned int wrreq_c_we_hi_full             : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE;
+          unsigned int wrreq_e0_macro_lo_full         : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e0_macro_hi_full         : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE;
+          unsigned int wrreq_e1_macro_lo_full         : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE;
+          unsigned int wrreq_e1_macro_hi_full         : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE;
+          unsigned int rdreq_c0_full                  : RB_DEBUG_0_RDREQ_C0_FULL_SIZE;
+          unsigned int rdreq_c1_full                  : RB_DEBUG_0_RDREQ_C1_FULL_SIZE;
+          unsigned int rdreq_z0_full                  : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE;
+          unsigned int rdreq_z1_full                  : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE;
+          unsigned int rdreq_e0_ordering_full         : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE;
+          unsigned int rdreq_e1_ordering_full         : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE;
+          unsigned int rdreq_ctl_c0_pre_full          : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_c1_pre_full          : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z0_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE;
+          unsigned int rdreq_ctl_z1_pre_full          : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE;
+     } rb_debug_0_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_0_t f;
+} rb_debug_0_u;
+
+
+/*
+ * RB_DEBUG_1 struct
+ */
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1
+#define RB_DEBUG_1_C_REQ_EMPTY_SIZE    1
+#define RB_DEBUG_1_C_MASK_EMPTY_SIZE   1
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28
+#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT   29
+#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT  30
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31
+
+#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001
+#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002
+#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004
+#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008
+#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010
+#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020
+#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040
+#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080
+#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100
+#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200
+#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400
+#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800
+#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000
+#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000
+#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000
+#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000
+#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000
+#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000
+#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000
+#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000
+#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000
+#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000
+#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000
+#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000
+#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000
+#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000
+#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000
+#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000
+#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000
+#define RB_DEBUG_1_C_REQ_EMPTY_MASK    0x20000000
+#define RB_DEBUG_1_C_MASK_EMPTY_MASK   0x40000000
+#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000
+
+#define RB_DEBUG_1_MASK \
+     (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \
+      RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \
+      RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \
+      RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \
+      RB_DEBUG_1_C_REQ_EMPTY_MASK | \
+      RB_DEBUG_1_C_MASK_EMPTY_MASK | \
+      RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK)
+
+#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \
+     ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \
+      (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \
+      (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \
+      (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \
+      (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \
+      (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \
+      (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \
+      (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \
+      (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \
+      (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \
+      (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \
+      (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \
+      (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \
+      (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \
+      (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \
+      (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \
+      (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \
+      (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \
+      (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \
+      (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \
+      (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \
+      (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \
+      (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \
+      (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \
+      (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT))
+
+#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \
+     ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \
+     rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_1_t {
+          unsigned int ez_infsamp_empty               : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE;
+          unsigned int c_mask_empty                   : RB_DEBUG_1_C_MASK_EMPTY_SIZE;
+          unsigned int c_req_empty                    : RB_DEBUG_1_C_REQ_EMPTY_SIZE;
+          unsigned int c_ez_tile_empty                : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE;
+          unsigned int c_sx_cmd_empty                 : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE;
+          unsigned int c_sx_lat_empty                 : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE;
+          unsigned int cmdfifo_c_ordering_empty       : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_z_ordering_empty       : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE;
+          unsigned int cmdfifo_c0_hold_empty          : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_c1_hold_empty          : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z0_hold_empty          : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE;
+          unsigned int cmdfifo_z1_hold_empty          : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE;
+          unsigned int wrreq_c0_pre_empty             : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE;
+          unsigned int wrreq_c1_pre_empty             : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE;
+          unsigned int wrreq_z0_empty                 : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE;
+          unsigned int wrreq_z1_empty                 : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE;
+          unsigned int wrreq_c_we_lo_empty            : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE;
+          unsigned int wrreq_c_we_hi_empty            : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_lo_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e0_macro_hi_empty        : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_lo_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE;
+          unsigned int wrreq_e1_macro_hi_empty        : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE;
+          unsigned int rdreq_c0_empty                 : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE;
+          unsigned int rdreq_c1_empty                 : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE;
+          unsigned int rdreq_z0_empty                 : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE;
+          unsigned int rdreq_z1_empty                 : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE;
+          unsigned int rdreq_e0_ordering_empty        : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_e1_ordering_empty        : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE;
+          unsigned int rdreq_c0_cmd_empty             : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_c1_cmd_empty             : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z0_cmd_empty             : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE;
+          unsigned int rdreq_z1_cmd_empty             : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE;
+     } rb_debug_1_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_1_t f;
+} rb_debug_1_u;
+
+
+/*
+ * RB_DEBUG_2 struct
+ */
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z1_MASK_FULL_SIZE   1
+#define RB_DEBUG_2_Z0_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z1_REQ_FULL_SIZE    1
+#define RB_DEBUG_2_Z_SAMP_FULL_SIZE    1
+#define RB_DEBUG_2_Z_TILE_FULL_SIZE    1
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE  1
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE   1
+#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE   1
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13
+#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16
+#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT  17
+#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT  18
+#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT   19
+#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT   20
+#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT   21
+#define RB_DEBUG_2_Z_TILE_FULL_SHIFT   22
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25
+#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26
+#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27
+#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT  28
+#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT  29
+#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT  30
+#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT  31
+
+#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f
+#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0
+#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800
+#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000
+#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000
+#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000
+#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000
+#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000
+#define RB_DEBUG_2_Z0_MASK_FULL_MASK   0x00020000
+#define RB_DEBUG_2_Z1_MASK_FULL_MASK   0x00040000
+#define RB_DEBUG_2_Z0_REQ_FULL_MASK    0x00080000
+#define RB_DEBUG_2_Z1_REQ_FULL_MASK    0x00100000
+#define RB_DEBUG_2_Z_SAMP_FULL_MASK    0x00200000
+#define RB_DEBUG_2_Z_TILE_FULL_MASK    0x00400000
+#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000
+#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000
+#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK  0x04000000
+#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK  0x08000000
+#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK   0x10000000
+#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK   0x20000000
+#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK   0x40000000
+#define RB_DEBUG_2_Z_TILE_EMPTY_MASK   0x80000000
+
+#define RB_DEBUG_2_MASK \
+     (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \
+      RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \
+      RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \
+      RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \
+      RB_DEBUG_2_Z0_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z1_MASK_FULL_MASK | \
+      RB_DEBUG_2_Z0_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z1_REQ_FULL_MASK | \
+      RB_DEBUG_2_Z_SAMP_FULL_MASK | \
+      RB_DEBUG_2_Z_TILE_FULL_MASK | \
+      RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \
+      RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \
+      RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \
+      RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \
+      RB_DEBUG_2_Z_TILE_EMPTY_MASK)
+
+#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \
+     ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \
+      (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \
+      (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \
+      (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \
+      (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \
+      (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \
+      (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \
+      (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \
+      (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \
+      (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \
+      (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \
+      (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \
+      (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \
+      (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \
+      (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \
+      (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \
+      (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \
+      (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \
+      (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \
+      (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \
+      (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \
+      (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \
+      (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT))
+
+#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \
+     ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT)
+#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT)
+#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT)
+#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT)
+#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \
+     rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+     } rb_debug_2_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_2_t {
+          unsigned int z_tile_empty                   : RB_DEBUG_2_Z_TILE_EMPTY_SIZE;
+          unsigned int z_samp_empty                   : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE;
+          unsigned int z1_req_empty                   : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE;
+          unsigned int z0_req_empty                   : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE;
+          unsigned int z1_mask_empty                  : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE;
+          unsigned int z0_mask_empty                  : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE;
+          unsigned int ez_mask_upper_empty            : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE;
+          unsigned int ez_mask_lower_empty            : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE;
+          unsigned int ez_inftile_empty               : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE;
+          unsigned int z_tile_full                    : RB_DEBUG_2_Z_TILE_FULL_SIZE;
+          unsigned int z_samp_full                    : RB_DEBUG_2_Z_SAMP_FULL_SIZE;
+          unsigned int z1_req_full                    : RB_DEBUG_2_Z1_REQ_FULL_SIZE;
+          unsigned int z0_req_full                    : RB_DEBUG_2_Z0_REQ_FULL_SIZE;
+          unsigned int z1_mask_full                   : RB_DEBUG_2_Z1_MASK_FULL_SIZE;
+          unsigned int z0_mask_full                   : RB_DEBUG_2_Z0_MASK_FULL_SIZE;
+          unsigned int ez_mask_upper_full             : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE;
+          unsigned int ez_mask_lower_full             : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE;
+          unsigned int ez_inftile_full                : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE;
+          unsigned int current_tile_event             : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE;
+          unsigned int sysmem_blend_flag              : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE;
+          unsigned int mem_export_flag                : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE;
+          unsigned int sx_lat_fifo_count              : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE;
+          unsigned int tile_fifo_count                : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE;
+     } rb_debug_2_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_2_t f;
+} rb_debug_2_u;
+
+
+/*
+ * RB_DEBUG_3 struct
+ */
+
+#define RB_DEBUG_3_ACCUM_VALID_SIZE    4
+#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4
+#define RB_DEBUG_3_SHD_FULL_SIZE       1
+#define RB_DEBUG_3_SHD_EMPTY_SIZE      1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1
+
+#define RB_DEBUG_3_ACCUM_VALID_SHIFT   0
+#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15
+#define RB_DEBUG_3_SHD_FULL_SHIFT      19
+#define RB_DEBUG_3_SHD_EMPTY_SHIFT     20
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28
+
+#define RB_DEBUG_3_ACCUM_VALID_MASK    0x0000000f
+#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0
+#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00
+#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000
+#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000
+#define RB_DEBUG_3_SHD_FULL_MASK       0x00080000
+#define RB_DEBUG_3_SHD_EMPTY_MASK      0x00100000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000
+#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000
+#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000
+#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000
+#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000
+#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000
+#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000
+
+#define RB_DEBUG_3_MASK \
+     (RB_DEBUG_3_ACCUM_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_FLUSHING_MASK | \
+      RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \
+      RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \
+      RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \
+      RB_DEBUG_3_SHD_FULL_MASK | \
+      RB_DEBUG_3_SHD_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \
+      RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \
+      RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \
+      RB_DEBUG_3_ZEXP_UPPER_FULL_MASK)
+
+#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \
+     ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \
+      (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \
+      (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \
+      (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \
+      (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \
+      (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \
+      (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \
+      (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \
+      (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \
+      (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \
+      (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \
+      (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \
+      (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \
+      (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \
+      (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT))
+
+#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \
+     ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT)
+#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT)
+#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT)
+#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT)
+#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \
+     rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int                                : 3;
+     } rb_debug_3_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_3_t {
+          unsigned int                                : 3;
+          unsigned int zexp_upper_full                : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE;
+          unsigned int zexp_lower_full                : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE;
+          unsigned int zexp_upper_empty               : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE;
+          unsigned int zexp_lower_empty               : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE;
+          unsigned int ez_return_upper_full           : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE;
+          unsigned int ez_return_lower_full           : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE;
+          unsigned int ez_return_upper_empty          : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE;
+          unsigned int ez_return_lower_empty          : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE;
+          unsigned int shd_empty                      : RB_DEBUG_3_SHD_EMPTY_SIZE;
+          unsigned int shd_full                       : RB_DEBUG_3_SHD_FULL_SIZE;
+          unsigned int accum_data_fifo_cnt            : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE;
+          unsigned int accum_input_reg_valid          : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE;
+          unsigned int accum_write_clean_count        : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE;
+          unsigned int accum_flushing                 : RB_DEBUG_3_ACCUM_FLUSHING_SIZE;
+          unsigned int accum_valid                    : RB_DEBUG_3_ACCUM_VALID_SIZE;
+     } rb_debug_3_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_3_t f;
+} rb_debug_3_u;
+
+
+/*
+ * RB_DEBUG_4 struct
+ */
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9
+
+#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001
+#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002
+#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004
+#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020
+#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040
+#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080
+#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100
+#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00
+
+#define RB_DEBUG_4_MASK \
+     (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \
+      RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \
+      RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \
+      RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \
+      RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK)
+
+#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \
+     ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \
+      (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \
+      (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \
+      (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \
+      (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \
+      (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \
+      (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \
+      (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT))
+
+#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \
+     ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT)
+#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT)
+#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \
+     rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int                                : 19;
+     } rb_debug_4_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_debug_4_t {
+          unsigned int                                : 19;
+          unsigned int context_count_debug            : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE;
+          unsigned int sysmem_write_count_overflow    : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE;
+          unsigned int accum_order_fifo_full          : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE;
+          unsigned int accum_data_fifo_full           : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE;
+          unsigned int accum_order_fifo_empty         : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE;
+          unsigned int accum_data_fifo_empty          : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE;
+          unsigned int sysmem_wr_access_flag          : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int sysmem_rd_access_flag          : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE;
+          unsigned int gmem_wr_access_flag            : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE;
+          unsigned int gmem_rd_access_flag            : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE;
+     } rb_debug_4_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_debug_4_t f;
+} rb_debug_4_u;
+
+
+/*
+ * RB_FLAG_CONTROL struct
+ */
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0
+
+#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001
+
+#define RB_FLAG_CONTROL_MASK \
+     (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK)
+
+#define RB_FLAG_CONTROL(debug_flag_clear) \
+     ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT))
+
+#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \
+     ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \
+     rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+          unsigned int                                : 31;
+     } rb_flag_control_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_flag_control_t {
+          unsigned int                                : 31;
+          unsigned int debug_flag_clear               : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE;
+     } rb_flag_control_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_flag_control_t f;
+} rb_flag_control_u;
+
+
+/*
+ * RB_BC_SPARES struct
+ */
+
+#define RB_BC_SPARES_RESERVED_SIZE     32
+
+#define RB_BC_SPARES_RESERVED_SHIFT    0
+
+#define RB_BC_SPARES_RESERVED_MASK     0xffffffff
+
+#define RB_BC_SPARES_MASK \
+     (RB_BC_SPARES_RESERVED_MASK)
+
+#define RB_BC_SPARES(reserved) \
+     ((reserved << RB_BC_SPARES_RESERVED_SHIFT))
+
+#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \
+     ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT)
+
+#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \
+     rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _rb_bc_spares_t {
+          unsigned int reserved                       : RB_BC_SPARES_RESERVED_SIZE;
+     } rb_bc_spares_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     rb_bc_spares_t f;
+} rb_bc_spares_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_ENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29
+
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000
+#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000
+
+#define BC_DUMMY_CRAYRB_ENUMS_MASK \
+     (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \
+      BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK)
+
+#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \
+     ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \
+      (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \
+      (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \
+      (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \
+      (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \
+      (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \
+      (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \
+      (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT))
+
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \
+     ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT)
+#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \
+     bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_enums_t {
+          unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE;
+          unsigned int dummy_crayrb_surface_array     : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_tiling    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE;
+          unsigned int dummy_crayrb_surface_format    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE;
+          unsigned int dummy_crayrb_surface_number    : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE;
+          unsigned int dummy_crayrb_color_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE;
+          unsigned int dummy_crayrb_array             : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE;
+          unsigned int dummy_crayrb_depth_array       : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE;
+          unsigned int dummy_crayrb_surface_swap      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE;
+          unsigned int dummy_crayrb_depth_format      : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE;
+     } bc_dummy_crayrb_enums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_enums_t f;
+} bc_dummy_crayrb_enums_u;
+
+
+/*
+ * BC_DUMMY_CRAYRB_MOREENUMS struct
+ */
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \
+     (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \
+     ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT))
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \
+     ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \
+     bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)
+
+#ifndef BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+          unsigned int                                : 30;
+     } bc_dummy_crayrb_moreenums_t;
+
+#else   // !BIGENDIAN_OS
+
+     typedef struct _bc_dummy_crayrb_moreenums_t {
+          unsigned int                                : 30;
+          unsigned int dummy_crayrb_colorarrayx       : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE;
+     } bc_dummy_crayrb_moreenums_t;
+
+#endif
+
+typedef union {
+     unsigned int val : 32;
+     bc_dummy_crayrb_moreenums_t f;
+} bc_dummy_crayrb_moreenums_u;
+
+
+#endif
+
+
diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h
new file mode 100644
index 00000000000..6968abb48bd
--- /dev/null
+++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h
@@ -0,0 +1,550 @@
+/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined (_yamato_TYPEDEF_HEADER)
+#define _yamato_TYPEDEF_HEADER
+
+#include "yamato_registers.h"
+
+typedef union PA_CL_VPORT_XSCALE                regPA_CL_VPORT_XSCALE;
+typedef union PA_CL_VPORT_XOFFSET               regPA_CL_VPORT_XOFFSET;
+typedef union PA_CL_VPORT_YSCALE                regPA_CL_VPORT_YSCALE;
+typedef union PA_CL_VPORT_YOFFSET               regPA_CL_VPORT_YOFFSET;
+typedef union PA_CL_VPORT_ZSCALE                regPA_CL_VPORT_ZSCALE;
+typedef union PA_CL_VPORT_ZOFFSET               regPA_CL_VPORT_ZOFFSET;
+typedef union PA_CL_VTE_CNTL                    regPA_CL_VTE_CNTL;
+typedef union PA_CL_CLIP_CNTL                   regPA_CL_CLIP_CNTL;
+typedef union PA_CL_GB_VERT_CLIP_ADJ            regPA_CL_GB_VERT_CLIP_ADJ;
+typedef union PA_CL_GB_VERT_DISC_ADJ            regPA_CL_GB_VERT_DISC_ADJ;
+typedef union PA_CL_GB_HORZ_CLIP_ADJ            regPA_CL_GB_HORZ_CLIP_ADJ;
+typedef union PA_CL_GB_HORZ_DISC_ADJ            regPA_CL_GB_HORZ_DISC_ADJ;
+typedef union PA_CL_ENHANCE                     regPA_CL_ENHANCE;
+typedef union PA_SC_ENHANCE                     regPA_SC_ENHANCE;
+typedef union PA_SU_VTX_CNTL                    regPA_SU_VTX_CNTL;
+typedef union PA_SU_POINT_SIZE                  regPA_SU_POINT_SIZE;
+typedef union PA_SU_POINT_MINMAX                regPA_SU_POINT_MINMAX;
+typedef union PA_SU_LINE_CNTL                   regPA_SU_LINE_CNTL;
+typedef union PA_SU_FACE_DATA                   regPA_SU_FACE_DATA;
+typedef union PA_SU_SC_MODE_CNTL                regPA_SU_SC_MODE_CNTL;
+typedef union PA_SU_POLY_OFFSET_FRONT_SCALE     regPA_SU_POLY_OFFSET_FRONT_SCALE;
+typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET    regPA_SU_POLY_OFFSET_FRONT_OFFSET;
+typedef union PA_SU_POLY_OFFSET_BACK_SCALE      regPA_SU_POLY_OFFSET_BACK_SCALE;
+typedef union PA_SU_POLY_OFFSET_BACK_OFFSET     regPA_SU_POLY_OFFSET_BACK_OFFSET;
+typedef union PA_SU_PERFCOUNTER0_SELECT         regPA_SU_PERFCOUNTER0_SELECT;
+typedef union PA_SU_PERFCOUNTER1_SELECT         regPA_SU_PERFCOUNTER1_SELECT;
+typedef union PA_SU_PERFCOUNTER2_SELECT         regPA_SU_PERFCOUNTER2_SELECT;
+typedef union PA_SU_PERFCOUNTER3_SELECT         regPA_SU_PERFCOUNTER3_SELECT;
+typedef union PA_SU_PERFCOUNTER0_LOW            regPA_SU_PERFCOUNTER0_LOW;
+typedef union PA_SU_PERFCOUNTER0_HI             regPA_SU_PERFCOUNTER0_HI;
+typedef union PA_SU_PERFCOUNTER1_LOW            regPA_SU_PERFCOUNTER1_LOW;
+typedef union PA_SU_PERFCOUNTER1_HI             regPA_SU_PERFCOUNTER1_HI;
+typedef union PA_SU_PERFCOUNTER2_LOW            regPA_SU_PERFCOUNTER2_LOW;
+typedef union PA_SU_PERFCOUNTER2_HI             regPA_SU_PERFCOUNTER2_HI;
+typedef union PA_SU_PERFCOUNTER3_LOW            regPA_SU_PERFCOUNTER3_LOW;
+typedef union PA_SU_PERFCOUNTER3_HI             regPA_SU_PERFCOUNTER3_HI;
+typedef union PA_SC_WINDOW_OFFSET               regPA_SC_WINDOW_OFFSET;
+typedef union PA_SC_AA_CONFIG                   regPA_SC_AA_CONFIG;
+typedef union PA_SC_AA_MASK                     regPA_SC_AA_MASK;
+typedef union PA_SC_LINE_STIPPLE                regPA_SC_LINE_STIPPLE;
+typedef union PA_SC_LINE_CNTL                   regPA_SC_LINE_CNTL;
+typedef union PA_SC_WINDOW_SCISSOR_TL           regPA_SC_WINDOW_SCISSOR_TL;
+typedef union PA_SC_WINDOW_SCISSOR_BR           regPA_SC_WINDOW_SCISSOR_BR;
+typedef union PA_SC_SCREEN_SCISSOR_TL           regPA_SC_SCREEN_SCISSOR_TL;
+typedef union PA_SC_SCREEN_SCISSOR_BR           regPA_SC_SCREEN_SCISSOR_BR;
+typedef union PA_SC_VIZ_QUERY                   regPA_SC_VIZ_QUERY;
+typedef union PA_SC_VIZ_QUERY_STATUS            regPA_SC_VIZ_QUERY_STATUS;
+typedef union PA_SC_LINE_STIPPLE_STATE          regPA_SC_LINE_STIPPLE_STATE;
+typedef union PA_SC_PERFCOUNTER0_SELECT         regPA_SC_PERFCOUNTER0_SELECT;
+typedef union PA_SC_PERFCOUNTER0_LOW            regPA_SC_PERFCOUNTER0_LOW;
+typedef union PA_SC_PERFCOUNTER0_HI             regPA_SC_PERFCOUNTER0_HI;
+typedef union PA_CL_CNTL_STATUS                 regPA_CL_CNTL_STATUS;
+typedef union PA_SU_CNTL_STATUS                 regPA_SU_CNTL_STATUS;
+typedef union PA_SC_CNTL_STATUS                 regPA_SC_CNTL_STATUS;
+typedef union PA_SU_DEBUG_CNTL                  regPA_SU_DEBUG_CNTL;
+typedef union PA_SU_DEBUG_DATA                  regPA_SU_DEBUG_DATA;
+typedef union PA_SC_DEBUG_CNTL                  regPA_SC_DEBUG_CNTL;
+typedef union PA_SC_DEBUG_DATA                  regPA_SC_DEBUG_DATA;
+typedef union GFX_COPY_STATE                    regGFX_COPY_STATE;
+typedef union VGT_DRAW_INITIATOR                regVGT_DRAW_INITIATOR;
+typedef union VGT_EVENT_INITIATOR               regVGT_EVENT_INITIATOR;
+typedef union VGT_DMA_BASE                      regVGT_DMA_BASE;
+typedef union VGT_DMA_SIZE                      regVGT_DMA_SIZE;
+typedef union VGT_BIN_BASE                      regVGT_BIN_BASE;
+typedef union VGT_BIN_SIZE                      regVGT_BIN_SIZE;
+typedef union VGT_CURRENT_BIN_ID_MIN            regVGT_CURRENT_BIN_ID_MIN;
+typedef union VGT_CURRENT_BIN_ID_MAX            regVGT_CURRENT_BIN_ID_MAX;
+typedef union VGT_IMMED_DATA                    regVGT_IMMED_DATA;
+typedef union VGT_MAX_VTX_INDX                  regVGT_MAX_VTX_INDX;
+typedef union VGT_MIN_VTX_INDX                  regVGT_MIN_VTX_INDX;
+typedef union VGT_INDX_OFFSET                   regVGT_INDX_OFFSET;
+typedef union VGT_VERTEX_REUSE_BLOCK_CNTL       regVGT_VERTEX_REUSE_BLOCK_CNTL;
+typedef union VGT_OUT_DEALLOC_CNTL              regVGT_OUT_DEALLOC_CNTL;
+typedef union VGT_MULTI_PRIM_IB_RESET_INDX      regVGT_MULTI_PRIM_IB_RESET_INDX;
+typedef union VGT_ENHANCE                       regVGT_ENHANCE;
+typedef union VGT_VTX_VECT_EJECT_REG            regVGT_VTX_VECT_EJECT_REG;
+typedef union VGT_LAST_COPY_STATE               regVGT_LAST_COPY_STATE;
+typedef union VGT_DEBUG_CNTL                    regVGT_DEBUG_CNTL;
+typedef union VGT_DEBUG_DATA                    regVGT_DEBUG_DATA;
+typedef union VGT_CNTL_STATUS                   regVGT_CNTL_STATUS;
+typedef union VGT_CRC_SQ_DATA                   regVGT_CRC_SQ_DATA;
+typedef union VGT_CRC_SQ_CTRL                   regVGT_CRC_SQ_CTRL;
+typedef union VGT_PERFCOUNTER0_SELECT           regVGT_PERFCOUNTER0_SELECT;
+typedef union VGT_PERFCOUNTER1_SELECT           regVGT_PERFCOUNTER1_SELECT;
+typedef union VGT_PERFCOUNTER2_SELECT           regVGT_PERFCOUNTER2_SELECT;
+typedef union VGT_PERFCOUNTER3_SELECT           regVGT_PERFCOUNTER3_SELECT;
+typedef union VGT_PERFCOUNTER0_LOW              regVGT_PERFCOUNTER0_LOW;
+typedef union VGT_PERFCOUNTER1_LOW              regVGT_PERFCOUNTER1_LOW;
+typedef union VGT_PERFCOUNTER2_LOW              regVGT_PERFCOUNTER2_LOW;
+typedef union VGT_PERFCOUNTER3_LOW              regVGT_PERFCOUNTER3_LOW;
+typedef union VGT_PERFCOUNTER0_HI               regVGT_PERFCOUNTER0_HI;
+typedef union VGT_PERFCOUNTER1_HI               regVGT_PERFCOUNTER1_HI;
+typedef union VGT_PERFCOUNTER2_HI               regVGT_PERFCOUNTER2_HI;
+typedef union VGT_PERFCOUNTER3_HI               regVGT_PERFCOUNTER3_HI;
+typedef union TC_CNTL_STATUS                    regTC_CNTL_STATUS;
+typedef union TCR_CHICKEN                       regTCR_CHICKEN;
+typedef union TCF_CHICKEN                       regTCF_CHICKEN;
+typedef union TCM_CHICKEN                       regTCM_CHICKEN;
+typedef union TCR_PERFCOUNTER0_SELECT           regTCR_PERFCOUNTER0_SELECT;
+typedef union TCR_PERFCOUNTER1_SELECT           regTCR_PERFCOUNTER1_SELECT;
+typedef union TCR_PERFCOUNTER0_HI               regTCR_PERFCOUNTER0_HI;
+typedef union TCR_PERFCOUNTER1_HI               regTCR_PERFCOUNTER1_HI;
+typedef union TCR_PERFCOUNTER0_LOW              regTCR_PERFCOUNTER0_LOW;
+typedef union TCR_PERFCOUNTER1_LOW              regTCR_PERFCOUNTER1_LOW;
+typedef union TP_TC_CLKGATE_CNTL                regTP_TC_CLKGATE_CNTL;
+typedef union TPC_CNTL_STATUS                   regTPC_CNTL_STATUS;
+typedef union TPC_DEBUG0                        regTPC_DEBUG0;
+typedef union TPC_DEBUG1                        regTPC_DEBUG1;
+typedef union TPC_CHICKEN                       regTPC_CHICKEN;
+typedef union TP0_CNTL_STATUS                   regTP0_CNTL_STATUS;
+typedef union TP0_DEBUG                         regTP0_DEBUG;
+typedef union TP0_CHICKEN                       regTP0_CHICKEN;
+typedef union TP0_PERFCOUNTER0_SELECT           regTP0_PERFCOUNTER0_SELECT;
+typedef union TP0_PERFCOUNTER0_HI               regTP0_PERFCOUNTER0_HI;
+typedef union TP0_PERFCOUNTER0_LOW              regTP0_PERFCOUNTER0_LOW;
+typedef union TP0_PERFCOUNTER1_SELECT           regTP0_PERFCOUNTER1_SELECT;
+typedef union TP0_PERFCOUNTER1_HI               regTP0_PERFCOUNTER1_HI;
+typedef union TP0_PERFCOUNTER1_LOW              regTP0_PERFCOUNTER1_LOW;
+typedef union TCM_PERFCOUNTER0_SELECT           regTCM_PERFCOUNTER0_SELECT;
+typedef union TCM_PERFCOUNTER1_SELECT           regTCM_PERFCOUNTER1_SELECT;
+typedef union TCM_PERFCOUNTER0_HI               regTCM_PERFCOUNTER0_HI;
+typedef union TCM_PERFCOUNTER1_HI               regTCM_PERFCOUNTER1_HI;
+typedef union TCM_PERFCOUNTER0_LOW              regTCM_PERFCOUNTER0_LOW;
+typedef union TCM_PERFCOUNTER1_LOW              regTCM_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER0_SELECT           regTCF_PERFCOUNTER0_SELECT;
+typedef union TCF_PERFCOUNTER1_SELECT           regTCF_PERFCOUNTER1_SELECT;
+typedef union TCF_PERFCOUNTER2_SELECT           regTCF_PERFCOUNTER2_SELECT;
+typedef union TCF_PERFCOUNTER3_SELECT           regTCF_PERFCOUNTER3_SELECT;
+typedef union TCF_PERFCOUNTER4_SELECT           regTCF_PERFCOUNTER4_SELECT;
+typedef union TCF_PERFCOUNTER5_SELECT           regTCF_PERFCOUNTER5_SELECT;
+typedef union TCF_PERFCOUNTER6_SELECT           regTCF_PERFCOUNTER6_SELECT;
+typedef union TCF_PERFCOUNTER7_SELECT           regTCF_PERFCOUNTER7_SELECT;
+typedef union TCF_PERFCOUNTER8_SELECT           regTCF_PERFCOUNTER8_SELECT;
+typedef union TCF_PERFCOUNTER9_SELECT           regTCF_PERFCOUNTER9_SELECT;
+typedef union TCF_PERFCOUNTER10_SELECT          regTCF_PERFCOUNTER10_SELECT;
+typedef union TCF_PERFCOUNTER11_SELECT          regTCF_PERFCOUNTER11_SELECT;
+typedef union TCF_PERFCOUNTER0_HI               regTCF_PERFCOUNTER0_HI;
+typedef union TCF_PERFCOUNTER1_HI               regTCF_PERFCOUNTER1_HI;
+typedef union TCF_PERFCOUNTER2_HI               regTCF_PERFCOUNTER2_HI;
+typedef union TCF_PERFCOUNTER3_HI               regTCF_PERFCOUNTER3_HI;
+typedef union TCF_PERFCOUNTER4_HI               regTCF_PERFCOUNTER4_HI;
+typedef union TCF_PERFCOUNTER5_HI               regTCF_PERFCOUNTER5_HI;
+typedef union TCF_PERFCOUNTER6_HI               regTCF_PERFCOUNTER6_HI;
+typedef union TCF_PERFCOUNTER7_HI               regTCF_PERFCOUNTER7_HI;
+typedef union TCF_PERFCOUNTER8_HI               regTCF_PERFCOUNTER8_HI;
+typedef union TCF_PERFCOUNTER9_HI               regTCF_PERFCOUNTER9_HI;
+typedef union TCF_PERFCOUNTER10_HI              regTCF_PERFCOUNTER10_HI;
+typedef union TCF_PERFCOUNTER11_HI              regTCF_PERFCOUNTER11_HI;
+typedef union TCF_PERFCOUNTER0_LOW              regTCF_PERFCOUNTER0_LOW;
+typedef union TCF_PERFCOUNTER1_LOW              regTCF_PERFCOUNTER1_LOW;
+typedef union TCF_PERFCOUNTER2_LOW              regTCF_PERFCOUNTER2_LOW;
+typedef union TCF_PERFCOUNTER3_LOW              regTCF_PERFCOUNTER3_LOW;
+typedef union TCF_PERFCOUNTER4_LOW              regTCF_PERFCOUNTER4_LOW;
+typedef union TCF_PERFCOUNTER5_LOW              regTCF_PERFCOUNTER5_LOW;
+typedef union TCF_PERFCOUNTER6_LOW              regTCF_PERFCOUNTER6_LOW;
+typedef union TCF_PERFCOUNTER7_LOW              regTCF_PERFCOUNTER7_LOW;
+typedef union TCF_PERFCOUNTER8_LOW              regTCF_PERFCOUNTER8_LOW;
+typedef union TCF_PERFCOUNTER9_LOW              regTCF_PERFCOUNTER9_LOW;
+typedef union TCF_PERFCOUNTER10_LOW             regTCF_PERFCOUNTER10_LOW;
+typedef union TCF_PERFCOUNTER11_LOW             regTCF_PERFCOUNTER11_LOW;
+typedef union TCF_DEBUG                         regTCF_DEBUG;
+typedef union TCA_FIFO_DEBUG                    regTCA_FIFO_DEBUG;
+typedef union TCA_PROBE_DEBUG                   regTCA_PROBE_DEBUG;
+typedef union TCA_TPC_DEBUG                     regTCA_TPC_DEBUG;
+typedef union TCB_CORE_DEBUG                    regTCB_CORE_DEBUG;
+typedef union TCB_TAG0_DEBUG                    regTCB_TAG0_DEBUG;
+typedef union TCB_TAG1_DEBUG                    regTCB_TAG1_DEBUG;
+typedef union TCB_TAG2_DEBUG                    regTCB_TAG2_DEBUG;
+typedef union TCB_TAG3_DEBUG                    regTCB_TAG3_DEBUG;
+typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG;
+typedef union TCB_FETCH_GEN_WALKER_DEBUG        regTCB_FETCH_GEN_WALKER_DEBUG;
+typedef union TCB_FETCH_GEN_PIPE0_DEBUG         regTCB_FETCH_GEN_PIPE0_DEBUG;
+typedef union TCD_INPUT0_DEBUG                  regTCD_INPUT0_DEBUG;
+typedef union TCD_DEGAMMA_DEBUG                 regTCD_DEGAMMA_DEBUG;
+typedef union TCD_DXTMUX_SCTARB_DEBUG           regTCD_DXTMUX_SCTARB_DEBUG;
+typedef union TCD_DXTC_ARB_DEBUG                regTCD_DXTC_ARB_DEBUG;
+typedef union TCD_STALLS_DEBUG                  regTCD_STALLS_DEBUG;
+typedef union TCO_STALLS_DEBUG                  regTCO_STALLS_DEBUG;
+typedef union TCO_QUAD0_DEBUG0                  regTCO_QUAD0_DEBUG0;
+typedef union TCO_QUAD0_DEBUG1                  regTCO_QUAD0_DEBUG1;
+typedef union SQ_GPR_MANAGEMENT                 regSQ_GPR_MANAGEMENT;
+typedef union SQ_FLOW_CONTROL                   regSQ_FLOW_CONTROL;
+typedef union SQ_INST_STORE_MANAGMENT           regSQ_INST_STORE_MANAGMENT;
+typedef union SQ_RESOURCE_MANAGMENT             regSQ_RESOURCE_MANAGMENT;
+typedef union SQ_EO_RT                          regSQ_EO_RT;
+typedef union SQ_DEBUG_MISC                     regSQ_DEBUG_MISC;
+typedef union SQ_ACTIVITY_METER_CNTL            regSQ_ACTIVITY_METER_CNTL;
+typedef union SQ_ACTIVITY_METER_STATUS          regSQ_ACTIVITY_METER_STATUS;
+typedef union SQ_INPUT_ARB_PRIORITY             regSQ_INPUT_ARB_PRIORITY;
+typedef union SQ_THREAD_ARB_PRIORITY            regSQ_THREAD_ARB_PRIORITY;
+typedef union SQ_VS_WATCHDOG_TIMER              regSQ_VS_WATCHDOG_TIMER;
+typedef union SQ_PS_WATCHDOG_TIMER              regSQ_PS_WATCHDOG_TIMER;
+typedef union SQ_INT_CNTL                       regSQ_INT_CNTL;
+typedef union SQ_INT_STATUS                     regSQ_INT_STATUS;
+typedef union SQ_INT_ACK                        regSQ_INT_ACK;
+typedef union SQ_DEBUG_INPUT_FSM                regSQ_DEBUG_INPUT_FSM;
+typedef union SQ_DEBUG_CONST_MGR_FSM            regSQ_DEBUG_CONST_MGR_FSM;
+typedef union SQ_DEBUG_TP_FSM                   regSQ_DEBUG_TP_FSM;
+typedef union SQ_DEBUG_FSM_ALU_0                regSQ_DEBUG_FSM_ALU_0;
+typedef union SQ_DEBUG_FSM_ALU_1                regSQ_DEBUG_FSM_ALU_1;
+typedef union SQ_DEBUG_EXP_ALLOC                regSQ_DEBUG_EXP_ALLOC;
+typedef union SQ_DEBUG_PTR_BUFF                 regSQ_DEBUG_PTR_BUFF;
+typedef union SQ_DEBUG_GPR_VTX                  regSQ_DEBUG_GPR_VTX;
+typedef union SQ_DEBUG_GPR_PIX                  regSQ_DEBUG_GPR_PIX;
+typedef union SQ_DEBUG_TB_STATUS_SEL            regSQ_DEBUG_TB_STATUS_SEL;
+typedef union SQ_DEBUG_VTX_TB_0                 regSQ_DEBUG_VTX_TB_0;
+typedef union SQ_DEBUG_VTX_TB_1                 regSQ_DEBUG_VTX_TB_1;
+typedef union SQ_DEBUG_VTX_TB_STATUS_REG        regSQ_DEBUG_VTX_TB_STATUS_REG;
+typedef union SQ_DEBUG_VTX_TB_STATE_MEM         regSQ_DEBUG_VTX_TB_STATE_MEM;
+typedef union SQ_DEBUG_PIX_TB_0                 regSQ_DEBUG_PIX_TB_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0      regSQ_DEBUG_PIX_TB_STATUS_REG_0;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1      regSQ_DEBUG_PIX_TB_STATUS_REG_1;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2      regSQ_DEBUG_PIX_TB_STATUS_REG_2;
+typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3      regSQ_DEBUG_PIX_TB_STATUS_REG_3;
+typedef union SQ_DEBUG_PIX_TB_STATE_MEM         regSQ_DEBUG_PIX_TB_STATE_MEM;
+typedef union SQ_PERFCOUNTER0_SELECT            regSQ_PERFCOUNTER0_SELECT;
+typedef union SQ_PERFCOUNTER1_SELECT            regSQ_PERFCOUNTER1_SELECT;
+typedef union SQ_PERFCOUNTER2_SELECT            regSQ_PERFCOUNTER2_SELECT;
+typedef union SQ_PERFCOUNTER3_SELECT            regSQ_PERFCOUNTER3_SELECT;
+typedef union SQ_PERFCOUNTER0_LOW               regSQ_PERFCOUNTER0_LOW;
+typedef union SQ_PERFCOUNTER0_HI                regSQ_PERFCOUNTER0_HI;
+typedef union SQ_PERFCOUNTER1_LOW               regSQ_PERFCOUNTER1_LOW;
+typedef union SQ_PERFCOUNTER1_HI                regSQ_PERFCOUNTER1_HI;
+typedef union SQ_PERFCOUNTER2_LOW               regSQ_PERFCOUNTER2_LOW;
+typedef union SQ_PERFCOUNTER2_HI                regSQ_PERFCOUNTER2_HI;
+typedef union SQ_PERFCOUNTER3_LOW               regSQ_PERFCOUNTER3_LOW;
+typedef union SQ_PERFCOUNTER3_HI                regSQ_PERFCOUNTER3_HI;
+typedef union SX_PERFCOUNTER0_SELECT            regSX_PERFCOUNTER0_SELECT;
+typedef union SX_PERFCOUNTER0_LOW               regSX_PERFCOUNTER0_LOW;
+typedef union SX_PERFCOUNTER0_HI                regSX_PERFCOUNTER0_HI;
+typedef union SQ_INSTRUCTION_ALU_0              regSQ_INSTRUCTION_ALU_0;
+typedef union SQ_INSTRUCTION_ALU_1              regSQ_INSTRUCTION_ALU_1;
+typedef union SQ_INSTRUCTION_ALU_2              regSQ_INSTRUCTION_ALU_2;
+typedef union SQ_INSTRUCTION_CF_EXEC_0          regSQ_INSTRUCTION_CF_EXEC_0;
+typedef union SQ_INSTRUCTION_CF_EXEC_1          regSQ_INSTRUCTION_CF_EXEC_1;
+typedef union SQ_INSTRUCTION_CF_EXEC_2          regSQ_INSTRUCTION_CF_EXEC_2;
+typedef union SQ_INSTRUCTION_CF_LOOP_0          regSQ_INSTRUCTION_CF_LOOP_0;
+typedef union SQ_INSTRUCTION_CF_LOOP_1          regSQ_INSTRUCTION_CF_LOOP_1;
+typedef union SQ_INSTRUCTION_CF_LOOP_2          regSQ_INSTRUCTION_CF_LOOP_2;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_0      regSQ_INSTRUCTION_CF_JMP_CALL_0;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_1      regSQ_INSTRUCTION_CF_JMP_CALL_1;
+typedef union SQ_INSTRUCTION_CF_JMP_CALL_2      regSQ_INSTRUCTION_CF_JMP_CALL_2;
+typedef union SQ_INSTRUCTION_CF_ALLOC_0         regSQ_INSTRUCTION_CF_ALLOC_0;
+typedef union SQ_INSTRUCTION_CF_ALLOC_1         regSQ_INSTRUCTION_CF_ALLOC_1;
+typedef union SQ_INSTRUCTION_CF_ALLOC_2         regSQ_INSTRUCTION_CF_ALLOC_2;
+typedef union SQ_INSTRUCTION_TFETCH_0           regSQ_INSTRUCTION_TFETCH_0;
+typedef union SQ_INSTRUCTION_TFETCH_1           regSQ_INSTRUCTION_TFETCH_1;
+typedef union SQ_INSTRUCTION_TFETCH_2           regSQ_INSTRUCTION_TFETCH_2;
+typedef union SQ_INSTRUCTION_VFETCH_0           regSQ_INSTRUCTION_VFETCH_0;
+typedef union SQ_INSTRUCTION_VFETCH_1           regSQ_INSTRUCTION_VFETCH_1;
+typedef union SQ_INSTRUCTION_VFETCH_2           regSQ_INSTRUCTION_VFETCH_2;
+typedef union SQ_CONSTANT_0                     regSQ_CONSTANT_0;
+typedef union SQ_CONSTANT_1                     regSQ_CONSTANT_1;
+typedef union SQ_CONSTANT_2                     regSQ_CONSTANT_2;
+typedef union SQ_CONSTANT_3                     regSQ_CONSTANT_3;
+typedef union SQ_FETCH_0                        regSQ_FETCH_0;
+typedef union SQ_FETCH_1                        regSQ_FETCH_1;
+typedef union SQ_FETCH_2                        regSQ_FETCH_2;
+typedef union SQ_FETCH_3                        regSQ_FETCH_3;
+typedef union SQ_FETCH_4                        regSQ_FETCH_4;
+typedef union SQ_FETCH_5                        regSQ_FETCH_5;
+typedef union SQ_CONSTANT_VFETCH_0              regSQ_CONSTANT_VFETCH_0;
+typedef union SQ_CONSTANT_VFETCH_1              regSQ_CONSTANT_VFETCH_1;
+typedef union SQ_CONSTANT_T2                    regSQ_CONSTANT_T2;
+typedef union SQ_CONSTANT_T3                    regSQ_CONSTANT_T3;
+typedef union SQ_CF_BOOLEANS                    regSQ_CF_BOOLEANS;
+typedef union SQ_CF_LOOP                        regSQ_CF_LOOP;
+typedef union SQ_CONSTANT_RT_0                  regSQ_CONSTANT_RT_0;
+typedef union SQ_CONSTANT_RT_1                  regSQ_CONSTANT_RT_1;
+typedef union SQ_CONSTANT_RT_2                  regSQ_CONSTANT_RT_2;
+typedef union SQ_CONSTANT_RT_3                  regSQ_CONSTANT_RT_3;
+typedef union SQ_FETCH_RT_0                     regSQ_FETCH_RT_0;
+typedef union SQ_FETCH_RT_1                     regSQ_FETCH_RT_1;
+typedef union SQ_FETCH_RT_2                     regSQ_FETCH_RT_2;
+typedef union SQ_FETCH_RT_3                     regSQ_FETCH_RT_3;
+typedef union SQ_FETCH_RT_4                     regSQ_FETCH_RT_4;
+typedef union SQ_FETCH_RT_5                     regSQ_FETCH_RT_5;
+typedef union SQ_CF_RT_BOOLEANS                 regSQ_CF_RT_BOOLEANS;
+typedef union SQ_CF_RT_LOOP                     regSQ_CF_RT_LOOP;
+typedef union SQ_VS_PROGRAM                     regSQ_VS_PROGRAM;
+typedef union SQ_PS_PROGRAM                     regSQ_PS_PROGRAM;
+typedef union SQ_CF_PROGRAM_SIZE                regSQ_CF_PROGRAM_SIZE;
+typedef union SQ_INTERPOLATOR_CNTL              regSQ_INTERPOLATOR_CNTL;
+typedef union SQ_PROGRAM_CNTL                   regSQ_PROGRAM_CNTL;
+typedef union SQ_WRAPPING_0                     regSQ_WRAPPING_0;
+typedef union SQ_WRAPPING_1                     regSQ_WRAPPING_1;
+typedef union SQ_VS_CONST                       regSQ_VS_CONST;
+typedef union SQ_PS_CONST                       regSQ_PS_CONST;
+typedef union SQ_CONTEXT_MISC                   regSQ_CONTEXT_MISC;
+typedef union SQ_CF_RD_BASE                     regSQ_CF_RD_BASE;
+typedef union SQ_DEBUG_MISC_0                   regSQ_DEBUG_MISC_0;
+typedef union SQ_DEBUG_MISC_1                   regSQ_DEBUG_MISC_1;
+typedef union MH_ARBITER_CONFIG                 regMH_ARBITER_CONFIG;
+typedef union MH_CLNT_AXI_ID_REUSE              regMH_CLNT_AXI_ID_REUSE;
+typedef union MH_INTERRUPT_MASK                 regMH_INTERRUPT_MASK;
+typedef union MH_INTERRUPT_STATUS               regMH_INTERRUPT_STATUS;
+typedef union MH_INTERRUPT_CLEAR                regMH_INTERRUPT_CLEAR;
+typedef union MH_AXI_ERROR                      regMH_AXI_ERROR;
+typedef union MH_PERFCOUNTER0_SELECT            regMH_PERFCOUNTER0_SELECT;
+typedef union MH_PERFCOUNTER1_SELECT            regMH_PERFCOUNTER1_SELECT;
+typedef union MH_PERFCOUNTER0_CONFIG            regMH_PERFCOUNTER0_CONFIG;
+typedef union MH_PERFCOUNTER1_CONFIG            regMH_PERFCOUNTER1_CONFIG;
+typedef union MH_PERFCOUNTER0_LOW               regMH_PERFCOUNTER0_LOW;
+typedef union MH_PERFCOUNTER1_LOW               regMH_PERFCOUNTER1_LOW;
+typedef union MH_PERFCOUNTER0_HI                regMH_PERFCOUNTER0_HI;
+typedef union MH_PERFCOUNTER1_HI                regMH_PERFCOUNTER1_HI;
+typedef union MH_DEBUG_CTRL                     regMH_DEBUG_CTRL;
+typedef union MH_DEBUG_DATA                     regMH_DEBUG_DATA;
+typedef union MH_AXI_HALT_CONTROL               regMH_AXI_HALT_CONTROL;
+typedef union MH_MMU_CONFIG                     regMH_MMU_CONFIG;
+typedef union MH_MMU_VA_RANGE                   regMH_MMU_VA_RANGE;
+typedef union MH_MMU_PT_BASE                    regMH_MMU_PT_BASE;
+typedef union MH_MMU_PAGE_FAULT                 regMH_MMU_PAGE_FAULT;
+typedef union MH_MMU_TRAN_ERROR                 regMH_MMU_TRAN_ERROR;
+typedef union MH_MMU_INVALIDATE                 regMH_MMU_INVALIDATE;
+typedef union MH_MMU_MPU_BASE                   regMH_MMU_MPU_BASE;
+typedef union MH_MMU_MPU_END                    regMH_MMU_MPU_END;
+typedef union WAIT_UNTIL                        regWAIT_UNTIL;
+typedef union RBBM_ISYNC_CNTL                   regRBBM_ISYNC_CNTL;
+typedef union RBBM_STATUS                       regRBBM_STATUS;
+typedef union RBBM_DSPLY                        regRBBM_DSPLY;
+typedef union RBBM_RENDER_LATEST                regRBBM_RENDER_LATEST;
+typedef union RBBM_RTL_RELEASE                  regRBBM_RTL_RELEASE;
+typedef union RBBM_PATCH_RELEASE                regRBBM_PATCH_RELEASE;
+typedef union RBBM_AUXILIARY_CONFIG             regRBBM_AUXILIARY_CONFIG;
+typedef union RBBM_PERIPHID0                    regRBBM_PERIPHID0;
+typedef union RBBM_PERIPHID1                    regRBBM_PERIPHID1;
+typedef union RBBM_PERIPHID2                    regRBBM_PERIPHID2;
+typedef union RBBM_PERIPHID3                    regRBBM_PERIPHID3;
+typedef union RBBM_CNTL                         regRBBM_CNTL;
+typedef union RBBM_SKEW_CNTL                    regRBBM_SKEW_CNTL;
+typedef union RBBM_SOFT_RESET                   regRBBM_SOFT_RESET;
+typedef union RBBM_PM_OVERRIDE1                 regRBBM_PM_OVERRIDE1;
+typedef union RBBM_PM_OVERRIDE2                 regRBBM_PM_OVERRIDE2;
+typedef union GC_SYS_IDLE                       regGC_SYS_IDLE;
+typedef union NQWAIT_UNTIL                      regNQWAIT_UNTIL;
+typedef union RBBM_DEBUG_OUT                    regRBBM_DEBUG_OUT;
+typedef union RBBM_DEBUG_CNTL                   regRBBM_DEBUG_CNTL;
+typedef union RBBM_DEBUG                        regRBBM_DEBUG;
+typedef union RBBM_READ_ERROR                   regRBBM_READ_ERROR;
+typedef union RBBM_WAIT_IDLE_CLOCKS             regRBBM_WAIT_IDLE_CLOCKS;
+typedef union RBBM_INT_CNTL                     regRBBM_INT_CNTL;
+typedef union RBBM_INT_STATUS                   regRBBM_INT_STATUS;
+typedef union RBBM_INT_ACK                      regRBBM_INT_ACK;
+typedef union MASTER_INT_SIGNAL                 regMASTER_INT_SIGNAL;
+typedef union RBBM_PERFCOUNTER1_SELECT          regRBBM_PERFCOUNTER1_SELECT;
+typedef union RBBM_PERFCOUNTER1_LO              regRBBM_PERFCOUNTER1_LO;
+typedef union RBBM_PERFCOUNTER1_HI              regRBBM_PERFCOUNTER1_HI;
+typedef union CP_RB_BASE                        regCP_RB_BASE;
+typedef union CP_RB_CNTL                        regCP_RB_CNTL;
+typedef union CP_RB_RPTR_ADDR                   regCP_RB_RPTR_ADDR;
+typedef union CP_RB_RPTR                        regCP_RB_RPTR;
+typedef union CP_RB_RPTR_WR                     regCP_RB_RPTR_WR;
+typedef union CP_RB_WPTR                        regCP_RB_WPTR;
+typedef union CP_RB_WPTR_DELAY                  regCP_RB_WPTR_DELAY;
+typedef union CP_RB_WPTR_BASE                   regCP_RB_WPTR_BASE;
+typedef union CP_IB1_BASE                       regCP_IB1_BASE;
+typedef union CP_IB1_BUFSZ                      regCP_IB1_BUFSZ;
+typedef union CP_IB2_BASE                       regCP_IB2_BASE;
+typedef union CP_IB2_BUFSZ                      regCP_IB2_BUFSZ;
+typedef union CP_ST_BASE                        regCP_ST_BASE;
+typedef union CP_ST_BUFSZ                       regCP_ST_BUFSZ;
+typedef union CP_QUEUE_THRESHOLDS               regCP_QUEUE_THRESHOLDS;
+typedef union CP_MEQ_THRESHOLDS                 regCP_MEQ_THRESHOLDS;
+typedef union CP_CSQ_AVAIL                      regCP_CSQ_AVAIL;
+typedef union CP_STQ_AVAIL                      regCP_STQ_AVAIL;
+typedef union CP_MEQ_AVAIL                      regCP_MEQ_AVAIL;
+typedef union CP_CSQ_RB_STAT                    regCP_CSQ_RB_STAT;
+typedef union CP_CSQ_IB1_STAT                   regCP_CSQ_IB1_STAT;
+typedef union CP_CSQ_IB2_STAT                   regCP_CSQ_IB2_STAT;
+typedef union CP_NON_PREFETCH_CNTRS             regCP_NON_PREFETCH_CNTRS;
+typedef union CP_STQ_ST_STAT                    regCP_STQ_ST_STAT;
+typedef union CP_MEQ_STAT                       regCP_MEQ_STAT;
+typedef union CP_MIU_TAG_STAT                   regCP_MIU_TAG_STAT;
+typedef union CP_CMD_INDEX                      regCP_CMD_INDEX;
+typedef union CP_CMD_DATA                       regCP_CMD_DATA;
+typedef union CP_ME_CNTL                        regCP_ME_CNTL;
+typedef union CP_ME_STATUS                      regCP_ME_STATUS;
+typedef union CP_ME_RAM_WADDR                   regCP_ME_RAM_WADDR;
+typedef union CP_ME_RAM_RADDR                   regCP_ME_RAM_RADDR;
+typedef union CP_ME_RAM_DATA                    regCP_ME_RAM_DATA;
+typedef union CP_ME_RDADDR                      regCP_ME_RDADDR;
+typedef union CP_DEBUG                          regCP_DEBUG;
+typedef union SCRATCH_REG0                      regSCRATCH_REG0;
+typedef union GUI_SCRATCH_REG0                  regGUI_SCRATCH_REG0;
+typedef union SCRATCH_REG1                      regSCRATCH_REG1;
+typedef union GUI_SCRATCH_REG1                  regGUI_SCRATCH_REG1;
+typedef union SCRATCH_REG2                      regSCRATCH_REG2;
+typedef union GUI_SCRATCH_REG2                  regGUI_SCRATCH_REG2;
+typedef union SCRATCH_REG3                      regSCRATCH_REG3;
+typedef union GUI_SCRATCH_REG3                  regGUI_SCRATCH_REG3;
+typedef union SCRATCH_REG4                      regSCRATCH_REG4;
+typedef union GUI_SCRATCH_REG4                  regGUI_SCRATCH_REG4;
+typedef union SCRATCH_REG5                      regSCRATCH_REG5;
+typedef union GUI_SCRATCH_REG5                  regGUI_SCRATCH_REG5;
+typedef union SCRATCH_REG6                      regSCRATCH_REG6;
+typedef union GUI_SCRATCH_REG6                  regGUI_SCRATCH_REG6;
+typedef union SCRATCH_REG7                      regSCRATCH_REG7;
+typedef union GUI_SCRATCH_REG7                  regGUI_SCRATCH_REG7;
+typedef union SCRATCH_UMSK                      regSCRATCH_UMSK;
+typedef union SCRATCH_ADDR                      regSCRATCH_ADDR;
+typedef union CP_ME_VS_EVENT_SRC                regCP_ME_VS_EVENT_SRC;
+typedef union CP_ME_VS_EVENT_ADDR               regCP_ME_VS_EVENT_ADDR;
+typedef union CP_ME_VS_EVENT_DATA               regCP_ME_VS_EVENT_DATA;
+typedef union CP_ME_VS_EVENT_ADDR_SWM           regCP_ME_VS_EVENT_ADDR_SWM;
+typedef union CP_ME_VS_EVENT_DATA_SWM           regCP_ME_VS_EVENT_DATA_SWM;
+typedef union CP_ME_PS_EVENT_SRC                regCP_ME_PS_EVENT_SRC;
+typedef union CP_ME_PS_EVENT_ADDR               regCP_ME_PS_EVENT_ADDR;
+typedef union CP_ME_PS_EVENT_DATA               regCP_ME_PS_EVENT_DATA;
+typedef union CP_ME_PS_EVENT_ADDR_SWM           regCP_ME_PS_EVENT_ADDR_SWM;
+typedef union CP_ME_PS_EVENT_DATA_SWM           regCP_ME_PS_EVENT_DATA_SWM;
+typedef union CP_ME_CF_EVENT_SRC                regCP_ME_CF_EVENT_SRC;
+typedef union CP_ME_CF_EVENT_ADDR               regCP_ME_CF_EVENT_ADDR;
+typedef union CP_ME_CF_EVENT_DATA               regCP_ME_CF_EVENT_DATA;
+typedef union CP_ME_NRT_ADDR                    regCP_ME_NRT_ADDR;
+typedef union CP_ME_NRT_DATA                    regCP_ME_NRT_DATA;
+typedef union CP_ME_VS_FETCH_DONE_SRC           regCP_ME_VS_FETCH_DONE_SRC;
+typedef union CP_ME_VS_FETCH_DONE_ADDR          regCP_ME_VS_FETCH_DONE_ADDR;
+typedef union CP_ME_VS_FETCH_DONE_DATA          regCP_ME_VS_FETCH_DONE_DATA;
+typedef union CP_INT_CNTL                       regCP_INT_CNTL;
+typedef union CP_INT_STATUS                     regCP_INT_STATUS;
+typedef union CP_INT_ACK                        regCP_INT_ACK;
+typedef union CP_PFP_UCODE_ADDR                 regCP_PFP_UCODE_ADDR;
+typedef union CP_PFP_UCODE_DATA                 regCP_PFP_UCODE_DATA;
+typedef union CP_PERFMON_CNTL                   regCP_PERFMON_CNTL;
+typedef union CP_PERFCOUNTER_SELECT             regCP_PERFCOUNTER_SELECT;
+typedef union CP_PERFCOUNTER_LO                 regCP_PERFCOUNTER_LO;
+typedef union CP_PERFCOUNTER_HI                 regCP_PERFCOUNTER_HI;
+typedef union CP_BIN_MASK_LO                    regCP_BIN_MASK_LO;
+typedef union CP_BIN_MASK_HI                    regCP_BIN_MASK_HI;
+typedef union CP_BIN_SELECT_LO                  regCP_BIN_SELECT_LO;
+typedef union CP_BIN_SELECT_HI                  regCP_BIN_SELECT_HI;
+typedef union CP_NV_FLAGS_0                     regCP_NV_FLAGS_0;
+typedef union CP_NV_FLAGS_1                     regCP_NV_FLAGS_1;
+typedef union CP_NV_FLAGS_2                     regCP_NV_FLAGS_2;
+typedef union CP_NV_FLAGS_3                     regCP_NV_FLAGS_3;
+typedef union CP_STATE_DEBUG_INDEX              regCP_STATE_DEBUG_INDEX;
+typedef union CP_STATE_DEBUG_DATA               regCP_STATE_DEBUG_DATA;
+typedef union CP_PROG_COUNTER                   regCP_PROG_COUNTER;
+typedef union CP_STAT                           regCP_STAT;
+typedef union BIOS_0_SCRATCH                    regBIOS_0_SCRATCH;
+typedef union BIOS_1_SCRATCH                    regBIOS_1_SCRATCH;
+typedef union BIOS_2_SCRATCH                    regBIOS_2_SCRATCH;
+typedef union BIOS_3_SCRATCH                    regBIOS_3_SCRATCH;
+typedef union BIOS_4_SCRATCH                    regBIOS_4_SCRATCH;
+typedef union BIOS_5_SCRATCH                    regBIOS_5_SCRATCH;
+typedef union BIOS_6_SCRATCH                    regBIOS_6_SCRATCH;
+typedef union BIOS_7_SCRATCH                    regBIOS_7_SCRATCH;
+typedef union BIOS_8_SCRATCH                    regBIOS_8_SCRATCH;
+typedef union BIOS_9_SCRATCH                    regBIOS_9_SCRATCH;
+typedef union BIOS_10_SCRATCH                   regBIOS_10_SCRATCH;
+typedef union BIOS_11_SCRATCH                   regBIOS_11_SCRATCH;
+typedef union BIOS_12_SCRATCH                   regBIOS_12_SCRATCH;
+typedef union BIOS_13_SCRATCH                   regBIOS_13_SCRATCH;
+typedef union BIOS_14_SCRATCH                   regBIOS_14_SCRATCH;
+typedef union BIOS_15_SCRATCH                   regBIOS_15_SCRATCH;
+typedef union COHER_SIZE_PM4                    regCOHER_SIZE_PM4;
+typedef union COHER_BASE_PM4                    regCOHER_BASE_PM4;
+typedef union COHER_STATUS_PM4                  regCOHER_STATUS_PM4;
+typedef union COHER_SIZE_HOST                   regCOHER_SIZE_HOST;
+typedef union COHER_BASE_HOST                   regCOHER_BASE_HOST;
+typedef union COHER_STATUS_HOST                 regCOHER_STATUS_HOST;
+typedef union COHER_DEST_BASE_0                 regCOHER_DEST_BASE_0;
+typedef union COHER_DEST_BASE_1                 regCOHER_DEST_BASE_1;
+typedef union COHER_DEST_BASE_2                 regCOHER_DEST_BASE_2;
+typedef union COHER_DEST_BASE_3                 regCOHER_DEST_BASE_3;
+typedef union COHER_DEST_BASE_4                 regCOHER_DEST_BASE_4;
+typedef union COHER_DEST_BASE_5                 regCOHER_DEST_BASE_5;
+typedef union COHER_DEST_BASE_6                 regCOHER_DEST_BASE_6;
+typedef union COHER_DEST_BASE_7                 regCOHER_DEST_BASE_7;
+typedef union RB_SURFACE_INFO                   regRB_SURFACE_INFO;
+typedef union RB_COLOR_INFO                     regRB_COLOR_INFO;
+typedef union RB_DEPTH_INFO                     regRB_DEPTH_INFO;
+typedef union RB_STENCILREFMASK                 regRB_STENCILREFMASK;
+typedef union RB_ALPHA_REF                      regRB_ALPHA_REF;
+typedef union RB_COLOR_MASK                     regRB_COLOR_MASK;
+typedef union RB_BLEND_RED                      regRB_BLEND_RED;
+typedef union RB_BLEND_GREEN                    regRB_BLEND_GREEN;
+typedef union RB_BLEND_BLUE                     regRB_BLEND_BLUE;
+typedef union RB_BLEND_ALPHA                    regRB_BLEND_ALPHA;
+typedef union RB_FOG_COLOR                      regRB_FOG_COLOR;
+typedef union RB_STENCILREFMASK_BF              regRB_STENCILREFMASK_BF;
+typedef union RB_DEPTHCONTROL                   regRB_DEPTHCONTROL;
+typedef union RB_BLENDCONTROL                   regRB_BLENDCONTROL;
+typedef union RB_COLORCONTROL                   regRB_COLORCONTROL;
+typedef union RB_MODECONTROL                    regRB_MODECONTROL;
+typedef union RB_COLOR_DEST_MASK                regRB_COLOR_DEST_MASK;
+typedef union RB_COPY_CONTROL                   regRB_COPY_CONTROL;
+typedef union RB_COPY_DEST_BASE                 regRB_COPY_DEST_BASE;
+typedef union RB_COPY_DEST_PITCH                regRB_COPY_DEST_PITCH;
+typedef union RB_COPY_DEST_INFO                 regRB_COPY_DEST_INFO;
+typedef union RB_COPY_DEST_PIXEL_OFFSET         regRB_COPY_DEST_PIXEL_OFFSET;
+typedef union RB_DEPTH_CLEAR                    regRB_DEPTH_CLEAR;
+typedef union RB_SAMPLE_COUNT_CTL               regRB_SAMPLE_COUNT_CTL;
+typedef union RB_SAMPLE_COUNT_ADDR              regRB_SAMPLE_COUNT_ADDR;
+typedef union RB_BC_CONTROL                     regRB_BC_CONTROL;
+typedef union RB_EDRAM_INFO                     regRB_EDRAM_INFO;
+typedef union RB_CRC_RD_PORT                    regRB_CRC_RD_PORT;
+typedef union RB_CRC_CONTROL                    regRB_CRC_CONTROL;
+typedef union RB_CRC_MASK                       regRB_CRC_MASK;
+typedef union RB_PERFCOUNTER0_SELECT            regRB_PERFCOUNTER0_SELECT;
+typedef union RB_PERFCOUNTER0_LOW               regRB_PERFCOUNTER0_LOW;
+typedef union RB_PERFCOUNTER0_HI                regRB_PERFCOUNTER0_HI;
+typedef union RB_TOTAL_SAMPLES                  regRB_TOTAL_SAMPLES;
+typedef union RB_ZPASS_SAMPLES                  regRB_ZPASS_SAMPLES;
+typedef union RB_ZFAIL_SAMPLES                  regRB_ZFAIL_SAMPLES;
+typedef union RB_SFAIL_SAMPLES                  regRB_SFAIL_SAMPLES;
+typedef union RB_DEBUG_0                        regRB_DEBUG_0;
+typedef union RB_DEBUG_1                        regRB_DEBUG_1;
+typedef union RB_DEBUG_2                        regRB_DEBUG_2;
+typedef union RB_DEBUG_3                        regRB_DEBUG_3;
+typedef union RB_DEBUG_4                        regRB_DEBUG_4;
+typedef union RB_FLAG_CONTROL                   regRB_FLAG_CONTROL;
+typedef union RB_BC_SPARES                      regRB_BC_SPARES;
+typedef union BC_DUMMY_CRAYRB_ENUMS             regBC_DUMMY_CRAYRB_ENUMS;
+typedef union BC_DUMMY_CRAYRB_MOREENUMS         regBC_DUMMY_CRAYRB_MOREENUMS;
+#endif
diff --git a/drivers/mxc/amd-gpu/os/include/os_types.h b/drivers/mxc/amd-gpu/os/include/os_types.h
new file mode 100644
index 00000000000..e7ecd90f895
--- /dev/null
+++ b/drivers/mxc/amd-gpu/os/include/os_types.h
@@ -0,0 +1,138 @@
+ /* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of QUALCOMM Incorporated nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __OSTYPES_H
+#define __OSTYPES_H
+
+//////////////////////////////////////////////////////////////////////////////
+//   status
+//////////////////////////////////////////////////////////////////////////////
+#define OS_SUCCESS                       0
+#define OS_FAILURE                      -1
+#define OS_FAILURE_SYSTEMERROR          -2
+#define OS_FAILURE_DEVICEERROR          -3
+#define OS_FAILURE_OUTOFMEM             -4
+#define OS_FAILURE_BADPARAM             -5
+#define OS_FAILURE_NOTSUPPORTED         -6
+#define OS_FAILURE_NOMOREAVAILABLE      -7
+#define OS_FAILURE_NOTINITIALIZED       -8
+#define OS_FAILURE_ALREADYINITIALIZED   -9
+#define OS_FAILURE_TIMEOUT              -10
+
+
+//////////////////////////////////////////////////////////////////////////////
+// inline
+//////////////////////////////////////////////////////////////////////////////
+#ifndef OSINLINE
+#ifdef _LINUX
+#define OSINLINE    static __inline
+#else
+#define OSINLINE    __inline
+#endif
+#endif // OSINLINE
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  values
+//////////////////////////////////////////////////////////////////////////////
+#define OS_INFINITE             0xFFFFFFFF
+#define OS_TLS_OUTOFINDEXES     0xFFFFFFFF
+#define OS_TRUE                         1
+#define OS_FALSE                        0
+
+#ifndef NULL
+#define NULL                    (void *)0x0
+#endif  // !NULL
+
+//////////////////////////////////////////////////////////////////////////////
+// types
+//////////////////////////////////////////////////////////////////////////////
+
+
+//
+// oshandle_t
+//
+typedef void *          oshandle_t;
+#define OS_HANDLE_NULL  (oshandle_t)0x0
+
+//
+// os_sysinfo_t
+//
+typedef struct _os_sysinfo_t {
+    int     cpu_mhz;
+    int     cpu_type;
+    int     cpu_version;
+    int     os_type;
+    int     os_version;
+    int     sysmem_size;
+    int     page_size;
+    int     max_path;
+    int     tls_slots;
+    int     endianness;     // 0 == little_endian, 1 == big_endian
+} os_sysinfo_t;
+
+
+//
+// os_stats_t
+//
+#ifdef _LINUX
+typedef long long __int64;
+typedef unsigned long long __uint64;
+#else
+typedef unsigned __int64 __uint64;
+#endif
+
+typedef struct _os_stats_t {
+    __int64     heap_allocs;
+    __int64     heap_frees;
+    __int64     heap_alloc_bytes;
+    __int64     shared_heap_allocs;
+    __int64     shared_heap_frees;
+    __int64     shared_heap_alloc_bytes;
+    __int64     objects_alloc;
+    __int64     objects_free;
+} os_stats_t;
+
+
+typedef enum {
+    OS_PROTECTION_GLOBAL,   // inter process
+    OS_PROTECTION_LOCAL,    // process local
+    OS_PROTECTION_NONE,     // none
+} os_protection_t;
+
+typedef struct _os_cputimer_t {
+    int refcount;                   // Reference count
+    int enabled;                    // Counter is enabled
+    int size;                       // Number of counters
+    __int64  start_time;            // start time in cpu ticks
+    __int64  end_time;              // end time in cpu ticks
+    __int64  timer_frequency;       // cpu ticks per second
+    __int64  *counter_array;        // number of ticks for each counter
+} os_cputimer_t;
+
+#endif  // __OSTYPES_H
diff --git a/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h
new file mode 100644
index 00000000000..a02c396c22a
--- /dev/null
+++ b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h
@@ -0,0 +1,813 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __KOSAPI_H
+#define __KOSAPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "os_types.h"
+
+
+//////////////////////////////////////////////////////////////////////////////
+//   entrypoint abstraction
+//////////////////////////////////////////////////////////////////////////////
+
+
+#if defined(_WIN32) && !defined (_WIN32_WCE) && !defined(__SYMBIAN32__)
+#define KOS_DLLEXPORT   __declspec(dllexport)
+#define KOS_DLLIMPORT   __declspec(dllimport)
+#elif defined(_WIN32) && defined (_WIN32_WCE)
+#define KOS_DLLEXPORT   __declspec(dllexport)   
+#define KOS_DLLIMPORT
+#else
+#define KOS_DLLEXPORT   extern
+#define KOS_DLLIMPORT   
+#endif // _WIN32
+
+
+//////////////////////////////////////////////////////////////////////////////
+//   KOS lib entrypoints
+//////////////////////////////////////////////////////////////////////////////
+#ifdef __KOSLIB_EXPORTS
+#define KOS_API         KOS_DLLEXPORT
+#else
+#define KOS_API         KOS_DLLIMPORT
+#endif // __KOSLIB_EXPORTS
+
+//////////////////////////////////////////////////////////////////////////////
+//                             assert API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void                    kos_assert_hook(const char* file, int line, int expression);
+
+#if defined(DEBUG) || defined(DBG) || defined (_DBG) || defined (_DEBUG)
+
+#if defined(_WIN32) && !defined(__SYMBIAN32__) || defined(_WIN32_WCE)
+#include <assert.h>
+#define KOS_ASSERT(expression)  assert(expression)
+#elif defined(_BREW)
+#include <assert.h>
+#define KOS_ASSERT(expression)  kos_assert_hook(__FILE__, __LINE__, expression)
+#elif defined(__SYMBIAN32__)
+//#include <assert.h>
+//#define   KOS_ASSERT(expression)  assert(expression)
+#define KOS_ASSERT(expression)  /**/
+#elif defined(__ARM__)
+#define KOS_ASSERT(expression)
+#elif defined(_LINUX)
+#define KOS_ASSERT(expression) //kos_assert_hook(__FILE__, __LINE__, (int)(expression))
+#endif
+
+#else
+
+#define KOS_ASSERT(expression)
+
+#endif // DEBUG || DBG || _DBG
+
+#if defined(_WIN32) && defined(_DEBUG) && !defined(_WIN32_WCE) && !defined(__SYMBIAN32__)
+#pragma warning ( push, 3 )
+#include <crtdbg.h>
+#pragma warning  (pop)
+#define KOS_MALLOC_DBG(size)    _malloc_dbg(size, _NORMAL_BLOCK, __FILE__, __LINE__)
+#else
+#define KOS_MALLOC_DBG(size)    kos_malloc(int size)
+#endif // _WIN32 _DEBUG
+
+#define kos_assert(expression)  KOS_ASSERT(expression)
+#define kos_malloc_dbg(size)    KOS_MALLOC_DBG(size)
+
+#ifdef UNDER_CE
+#define KOS_PAGE_SIZE 0x1000
+#endif
+
+typedef enum mutexIndex mutexIndex_t;
+//////////////////////////////////////////////////////////////////////////////
+//  Interprocess shared memory initialization 
+//////////////////////////////////////////////////////////////////////////////
+// TODO: still valid?
+KOS_API int             kos_sharedmem_create(unsigned int map_addr, unsigned int size);
+KOS_API int             kos_sharedmem_destroy(void);
+
+//////////////////////////////////////////////////////////////////////////////
+//  heap API (per process)
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory for a kernel side process.
+ *
+ *
+ * \param   int size    Amount of bytes to be allocated.
+ * \return  Pointer to the reserved memory, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_malloc(int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory for a kernel side process. Clears the reserved memory.
+ *
+ *
+ * \param   int num     Number of elements to allocate.
+ * \param   int size    Element size in bytes.
+ * \return  Pointer to the reserved memory, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_calloc(int num, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Re-allocate an existing memory for a kernel side process.
+ *          Contents of the old block will be copied to the new block
+ *          taking the sizes of both blocks into account.
+ *
+ *
+ * \param   void* memblock  Pointer to the old memory block.
+ * \param   int size        Size of the new block in bytes.
+ * \return  Pointer to the new memory block, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_realloc(void* memblock, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free a reserved memory block from the kernel side process.
+ *
+ *
+ * \param   void* memblock  Pointer to the memory block.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void            kos_free(void* memblock);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Enable automatic memory leak checking performed at program exit.
+ *
+ *
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void            kos_enable_memoryleakcheck(void);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  shared heap API (cross process)
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory that can be shared between user and kernel
+ *          side processes.
+ *
+ *
+ * \param   int size    Amount of bytes to be allocated.
+ * \return  Pointer to the new memory block, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_shared_malloc(int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate memory that can be shared between user and kernel
+ *          side processes. Clears the reserved memory.
+ *
+ *
+ * \param   int num Number of elements to allocate.
+ * \param   int size    Element size in bytes.
+ * \return  Pointer to the reserved memory, NULL if any error.
+ *//*-------------------------------------------------------------------*/ 
+KOS_API void*           kos_shared_calloc(int num, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Re-allocate an existing user/kernel shared memory block.
+ *          Contents of the old block will be copied to the new block
+ *          taking the sizes of both blocks into account.
+ *
+ *
+ * \param   void* ptr   Pointer to the old memory block.
+ * \param   int size    Size of the new block in bytes.
+ * \return  Pointer to the new memory block, NULL if any error.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_shared_realloc(void* ptr, int size);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free a reserved shared memory block.
+ *
+ *
+ * \param   void* ptr   Pointer to the memory block.
+ *//*-------------------------------------------------------------------*/
+ KOS_API void           kos_shared_free(void* ptr);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  memory API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Copies the values of num bytes from the location pointed by src
+ *          directly to the memory block pointed by dst.
+ *
+ *
+ * \param   void* dst   Pointer to the destination memory block.
+ * \param   void* src   Pointer to the source memory block.
+ * \param   void* count Amount of bytes to copy.
+ * \return  Returns the dst pointer, NULL if any error.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_memcpy(void* dst, const void* src, int count);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Fills the destination memory block with the given value.
+ *
+ *
+ * \param   void* dst   Pointer to the destination memory block.
+ * \param   int value   Value to be written to each destination address.
+ * \param   void* count Number of bytes to be set to the value.
+ * \return  Returns the dst pointer, NULL if any error.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_memset(void* dst, int value, int count);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Compares two memory blocks.
+ *
+ *
+ * \param   void* dst   Pointer to the destination memory block.
+ * \param   void* src   Pointer to the source memory block.
+ * \param   void* count Number of bytes to compare.
+ * \return  Zero if identical, >0 if first nonmatching byte is greater in dst.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_memcmp(void* dst, void* src, int count);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  physical memory API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocates a physically contiguous memory block.
+ *
+ *
+ * \param   void** virt_addr    Pointer where to store the virtual address of the reserved block.
+ * \param   void** phys_addr    Pointer where to store the physical address of the reserved block.
+ * \param   int pages           Number of pages to reserve (default page size = 4096 bytes).
+ * \return  Zero if ok, othervise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_alloc_physical(void** virt_addr, void** phys_addr, int pages);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free a physically contiguous allocated memory block.
+ *
+ *
+ * \param   void* virt_addr     Virtual address of the memory block.
+ * \param   int pages           Number of pages.
+ * \return  Zero if ok, othervise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_free_physical(void* virt_addr, int pages);
+
+KOS_API void            kos_memoryfence(void);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  string API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Perform a string copy.
+ *
+ *
+ * \param   void* strdestination    Pointer to destination memory.
+ * \param   void* strsource     Pointer to the source string.
+ * \return  Zero if ok, othervise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API char*           kos_strcpy(char* strdestination, const char* strsource);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Perform a string copy with given length.
+ *
+ *
+ * \param   void* destination   Pointer to destination memory.
+ * \param   void* source        Pointer to the source string.
+ * \param   int length          Amount of bytes to copy.
+ * \return  Returns the destination pointer.
+ *//*-------------------------------------------------------------------*/
+KOS_API char*           kos_strncpy(char* destination, const char* source, int length);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Append source string to destination string.
+ *
+ *
+ * \param   void* strdestination    Pointer to destination string.
+ * \param   void* strsource         Pointer to the source string.
+ * \return  Returns the destination pointer.
+ *//*-------------------------------------------------------------------*/
+KOS_API char*           kos_strcat(char* strdestination, const char* strsource);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Compare two strings.
+ *
+ *
+ * \param   void* string1   Pointer to first string.
+ * \param   void* string2   Pointer to second string.
+ * \param   void* length    Number of bytes to compare.
+ * \return  Zero if identical, >0 if first string is lexically greater <0 if not.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_strcmp(const char* string1, const char* string2);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Compares two strings of given length.
+ *
+ *
+ * \param   void* string1   Pointer to first string.
+ * \param   void* string2   Pointer to second string.
+ * \param   void* length    Number of bytes to compare.
+ * \return  Zero if identical, >0 if first string is lexically greater <0 if not.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_strncmp(const char* string1, const char* string2, int length);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Calculates the length of a string..
+ *
+ *
+ * \param   void* string    Pointer to the string.
+ * \return  Lenght of the string in bytes.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_strlen(const char* string);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Convert an numeric ascii string to integer value.
+ *
+ *
+ * \param   void* string    Pointer to the string.
+ * \return  Integer value extracted from the string.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_atoi(const char* string);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Convert string to unsigned long integer.
+ *
+ *
+ * \param   void* nptr      Pointer to the string.
+ * \param   char** endptr   If not null, will be set to point to the next character after the number.
+ * \param   int base        Base defining the type of the numeric string.
+ * \return  Unsigned integer value extracted from the string.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_strtoul(const char* nptr, char** endptr, int base);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  sync API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Create a mutex instance.
+ *
+ *
+ * \param   void* name      Name string for the new mutex.
+ * \return  Returns a handle to the mutex.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_mutex_create(const char* name);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get a handle to an already existing mutex.
+ *
+ *
+ * \param   void* name      Name string for the new mutex.
+ * \return  Returns a handle to the mutex.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_mutex_open(const char* name);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free the given mutex.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_free(oshandle_t mutexhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Lock the given mutex.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_lock(oshandle_t mutexhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Try to lock the given mutex, if already locked returns immediately.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_locktry(oshandle_t mutexhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Try to lock the given mutex by waiting for its release. Returns without locking if the
+ * mutex is already locked and cannot be acquired within the given period.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \param   int millisecondstowait  Time to wait for the mutex to be available.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_lockwait(oshandle_t mutexhandle, int millisecondstowait);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Unlock the given mutex.
+ *
+ *
+ * \param   oshandle_t mutexhandle  Handle to the mutex.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_mutex_unlock(oshandle_t mutexhandle);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Increments (increases by one) the value of the specified 32-bit variable as an atomic operation.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be incremented.
+ * \return  Returns the new incremented value.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_incr(int* ptr);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Decrements (decreases by one) the value of the specified 32-bit variable as an atomic operation.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be decremented.
+ * \return  Returns the new decremented value.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_decr(int* ptr);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Atomic replacement of a value.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be replaced.
+ * \param   int value The new value.
+ * \return  Returns the old value.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_xchg(int* ptr, int value);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Perform an atomic compare-and-exchange operation on the specified values. Compares the two specified 32-bit values and exchanges
+* with another 32-bit value based on the outcome of the comparison.
+ *
+ *
+ * \param   int* ptr Pointer to the value to be replaced.
+ * \param   int value The new value.
+ * \param   int compvalue Value to be compared with.
+ * \return  Returns the initial value of the first given parameter.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_compxchg(int* ptr, int value, int compvalue);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Atomic addition of two 32-bit values.
+ *
+ *
+ * \param   int* ptr Pointer to the target value.
+ * \param   int value Value to be added to the target.
+ * \return  Returns the initial value of the target.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interlock_xchgadd(int* ptr, int value);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Create an event semaphore.
+ *
+ *
+ * \param   int a_manualReset Selection for performing reset manually (or by the system).
+ * \return  Returns an handle to the created semaphore.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_event_create(int a_manualReset);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Destroy an event semaphore.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_destroy(oshandle_t a_event);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Signal an event semaphore.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_signal(oshandle_t a_event);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Reset an event semaphore.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_reset(oshandle_t a_event);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Wait for an event semaphore to be freed and acquire it.
+ *
+ *
+ * \param   oshandle_t a_event Handle to the semaphore.
+ * \param   int a_milliSeconds Time to wait.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_event_wait(oshandle_t a_event, int a_milliSeconds);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  interrupt handler API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Enable an interrupt with specified id.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_enable(int interrupt);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Disable an interrupt with specified id.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_disable(int interrupt);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Set the callback function for an interrupt.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \param   void* handler   Pointer to the callback function.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_setcallback(int interrupt, void* handler);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Remove a callback function from an interrupt.
+ *
+ *
+ * \param   int interrupt   Identification number for the interrupt.
+ * \param   void* handler   Pointer to the callback function.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_interrupt_clearcallback(int interrupt, void* handler);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  thread and process API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Allocate an entry from the thread local storage table.
+ *
+ *
+ * \return  Index of the reserved entry.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_tls_alloc(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Free an entry from the thread local storage table.
+ *
+ *
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_tls_free(unsigned int tlsindex);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Read the value of an entry in the thread local storage table.
+ *
+ *
+ * \param   unsigned int tlsindex   Index of the entry.
+ * \return  Returns the value of the entry.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_tls_read(unsigned int tlsindex);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Write a value to an entry in the thread local storage table.
+ *
+ *
+ * \param   unsigned int tlsindex   Index of the entry.
+ * \param   void* tlsvalue          Value to be written.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_tls_write(unsigned int tlsindex, void* tlsvalue);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Put the thread to sleep for the given time period.
+ *
+ *
+ * \param   unsigned int milliseconds   Time in milliseconds.
+ *//*-------------------------------------------------------------------*/
+KOS_API void            kos_sleep(unsigned int milliseconds);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the id of the current process.
+ *
+ *
+ * \return  Returns the process id.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_process_getid(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the id of the current caller process.
+ *
+ *
+ * \return  Returns the caller process id.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_callerprocess_getid(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the id of the current thread.
+ *
+ *
+ * \return  Returns the thread id.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_thread_getid(void);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Create a new thread.
+ *
+ *
+ * \param   oshandle_t a_function Handle to the function to be executed in the thread.
+ * \param   unsigned int* a_threadId Pointer to a value where to store the ID of the new thread.
+ * \return  Returns an handle to the created thread.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_thread_create(oshandle_t a_function, unsigned int* a_threadId);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Destroy the given thread.
+ *
+ *
+ * \param   oshandle_t a_task Handle to the thread to be destroyed.
+ *//*-------------------------------------------------------------------*/
+KOS_API void            kos_thread_destroy( oshandle_t a_task );
+
+//////////////////////////////////////////////////////////////////////////////
+//  timing API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the current time as a timestamp.
+ *
+ *
+ * \return  Returns the timestamp.
+ *//*-------------------------------------------------------------------*/
+KOS_API unsigned int    kos_timestamp(void);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  libary API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Map the given library (not required an all OS'es).
+ *
+ *
+ * \param   char* libraryname   The name string of the lib.
+ * \return  Returns a handle for the lib.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_lib_map(char* libraryname);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Unmap the given library.
+ *
+ * \param   oshandle_t libhandle Handle to the lib.
+ * \return  Returns an error code incase of an error.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_lib_unmap(oshandle_t libhandle);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get the address of a lib.
+ *
+ * \param   oshandle_t libhandle Handle to the lib.
+ * \return  Returns a pointer to the lib.
+ *//*-------------------------------------------------------------------*/
+KOS_API void*           kos_lib_getaddr(oshandle_t libhandle, char* procname);
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  query API
+//////////////////////////////////////////////////////////////////////////////
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get device system info.
+ *
+ * \param   os_sysinfo_t* sysinfo   Pointer to the destination sysinfo structure.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_get_sysinfo(os_sysinfo_t* sysinfo);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Get system status info.
+ *
+ * \param   os_stats_t* stats   Pointer to the destination stats structure.
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_get_stats(os_stats_t* stats);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_syncblock_start(void);
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block end
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_syncblock_end(void);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start with argument
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int kos_syncblock_start_ex( mutexIndex_t a_index );
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start with argument
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int kos_syncblock_end_ex( mutexIndex_t a_index );
+
+//////////////////////////////////////////////////////////////////////////////
+//  file API
+//////////////////////////////////////////////////////////////////////////////
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Opens a file
+ *
+ * \param   const char* filename    Name of the file to open.
+ * \param   const char* mode        Mode used for file opening. See fopen.
+ * \return  Returns file handle or NULL if error.
+ *//*-------------------------------------------------------------------*/
+KOS_API oshandle_t      kos_fopen(const char* filename, const char* mode);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Writes to a file
+ *
+ * \param   oshandle_t file     Handle of the file to write to.
+ * \param   const char* format  Format string. See fprintf.
+ * \return  Returns the number of bytes written
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_fprintf(oshandle_t file, const char* format, ...);
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Closes a file
+ *
+ * \param   oshandle_t file     Handle of the file to close.
+ * \return  Returns zero if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int             kos_fclose(oshandle_t file);
+
+#ifdef  __SYMBIAN32__
+KOS_API void kos_create_dfc(void);
+KOS_API void kos_signal_dfc(void);
+KOS_API void kos_enter_critical_section();
+KOS_API void kos_leave_critical_section();
+#endif  // __SYMBIAN32__
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif  // __KOSAPI_H
diff --git a/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c
new file mode 100644
index 00000000000..4ead84ffe0d
--- /dev/null
+++ b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c
@@ -0,0 +1,661 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/limits.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/mutex.h>
+#include <asm/atomic.h>
+#include <asm/current.h>
+#include <linux/sched.h>
+#include <linux/jiffies.h>
+#include <linux/kthread.h>
+#include "kos_libapi.h"
+
+//////////////////////////////////////////////////////////////////////////////
+//  defines
+//////////////////////////////////////////////////////////////////////////////
+//#define KOS_STATS_ENABLE
+
+//////////////////////////////////////////////////////////////////////////////
+//  macros
+//////////////////////////////////////////////////////////////////////////////
+#define KOS_MALLOC(s)               kmalloc(s, GFP_KERNEL)
+#define KOS_CALLOC(num, size)       kcalloc(num, size, GFP_KERNEL)
+#define KOS_REALLOC(p, s)           krealloc(p, s, GFP_KERNEL)
+#define KOS_FREE(p)                 kfree(p); p = 0
+#define KOS_DBGFLAGS_SET(flag)
+
+//////////////////////////////////////////////////////////////////////////////
+// stats
+//////////////////////////////////////////////////////////////////////////////
+#ifdef KOS_STATS_ENABLE
+os_stats_t kos_stats = {0, 0, 0, 0, 0, 0, 0, 0};
+#define KOS_STATS(x) x
+#else
+#define KOS_STATS(x)
+#endif
+
+//////////////////////////////////////////////////////////////////////////////
+//  assert API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void
+kos_assert_hook(const char* file, int line, int expression)
+{
+    if (expression)
+    {
+        return;
+    }
+    else
+    {
+        printk(KERN_ERR "Assertion failed at %s:%d!\n", file, line);
+        //BUG();
+    }
+
+    // put breakpoint here
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  heap API (per process)
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void*
+kos_malloc(int size)
+{
+    void* ptr = KOS_MALLOC(size);
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.heap_allocs++);
+    KOS_STATS(kos_stats.heap_alloc_bytes += size);
+
+    return (ptr);
+}
+
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_calloc(int num, int size)
+{
+    void* ptr = KOS_CALLOC(num, size);
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.heap_allocs++);
+    KOS_STATS(kos_stats.heap_alloc_bytes += (size * num));
+
+    return (ptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_realloc(void* ptr, int size)
+{
+    void* newptr;
+
+    KOS_ASSERT(ptr);
+    newptr = KOS_REALLOC(ptr, size);
+
+    KOS_ASSERT(newptr);
+
+    return (newptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_free(void* ptr)
+{
+    KOS_STATS(kos_stats.heap_frees++);
+
+    KOS_FREE(ptr);
+}
+
+
+//////////////////////////////////////////////////////////////////////////////
+//  shared heap API (cross process)
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void*
+kos_shared_malloc(int size)
+{
+    void* ptr;
+
+    ptr = NULL; // shared alloc
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.shared_heap_allocs++);
+    KOS_STATS(kos_stats.shared_heap_alloc_bytes += size);
+
+    return (ptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_shared_calloc(int num, int size)
+{
+    void* ptr;
+
+    ptr = NULL; // shared calloc
+
+    KOS_ASSERT(ptr);
+    KOS_STATS(kos_stats.shared_heap_allocs++);
+    KOS_STATS(kos_stats.shared_heap_alloc_bytes += (size * num));
+    return (ptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_shared_realloc(void* ptr, int size)
+{
+    void* newptr;
+    (void) ptr;      // unreferenced formal parameter
+    (void) size;     // unreferenced formal parameter
+
+    newptr = NULL; // shared realloc
+
+    KOS_ASSERT(newptr);
+
+    return (newptr);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_shared_free(void* ptr)
+{
+    (void) ptr;      // unreferenced formal parameter
+    KOS_ASSERT(0);   // not implemented
+
+    KOS_STATS(kos_stats.shared_heap_frees++);
+
+    // shared free
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  memory access API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API void*
+kos_memcpy(void* dst, const void* src, int count)
+{
+    KOS_ASSERT(src);
+    KOS_ASSERT(dst);
+    return memcpy(dst, src, count);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void*
+kos_memset(void* dst, int value, int count)
+{
+    KOS_ASSERT(dst);
+    return memset(dst, value, count);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_memcmp(void* dst, void* src, int count)
+{
+    KOS_ASSERT(src);
+    KOS_ASSERT(dst);
+    return memcmp(dst, src, count);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  physical memory API
+//////////////////////////////////////////////////////////////////////////////
+KOS_API int
+kos_alloc_physical(void** virt_addr, void** phys_addr, int pages)
+{
+    *virt_addr = dma_alloc_coherent(NULL, pages*PAGE_SIZE, (dma_addr_t*)*phys_addr, GFP_DMA | GFP_KERNEL);
+    return *virt_addr ? OS_SUCCESS : OS_FAILURE;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_free_physical(void* virt_addr, int pages)
+{
+    (void) virt_addr;      // unreferenced formal parameter
+    (void) pages;         // unreferenced formal parameter
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_map_physical(void** virt_addr, void** phys_addr, int pages)
+{
+    (void) virt_addr;      // unreferenced formal parameter
+    (void) phys_addr;     // unreferenced formal parameter
+    (void) pages;         // unreferenced formal parameter
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_unmap_physical(void* virt_addr, int pages)
+{
+    (void) virt_addr;      // unreferenced formal parameter
+    (void) pages;         // unreferenced formal parameter
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_memoryfence(void)
+{
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_enable_memoryleakcheck(void)
+{
+    // perform automatic leak checking at program exit
+    KOS_DBGFLAGS_SET(_CRTDBG_ALLOC_MEM_DF | _CRTDBG_LEAK_CHECK_DF);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  string API
+//////////////////////////////////////////////////////////////////////////////
+
+KOS_API char*
+kos_strcpy(char* strdestination, const char* strsource)
+{
+    KOS_ASSERT(strdestination);
+    KOS_ASSERT(strsource);
+    return strcpy(strdestination, strsource);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API char*
+kos_strncpy(char* destination, const char* source, int length)
+{
+    KOS_ASSERT(destination);
+    KOS_ASSERT(source);
+    return strncpy(destination, source, length);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API char*
+kos_strcat(char* strdestination, const char* strsource)
+{
+    KOS_ASSERT(strdestination);
+    KOS_ASSERT(strsource);
+    return strcat(strdestination, strsource);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_strcmp(const char* string1, const char* string2)
+{
+    KOS_ASSERT(string1);
+    KOS_ASSERT(string2);
+    return strcmp(string1, string2);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_strncmp(const char* string1, const char* string2, int length)
+{
+    KOS_ASSERT(string1);
+    KOS_ASSERT(string2);
+    return strncmp(string1, string2, length);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_strlen(const char* string)
+{
+    KOS_ASSERT(string);
+    return strlen(string);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  sync API
+//////////////////////////////////////////////////////////////////////////////
+
+KOS_API oshandle_t
+kos_mutex_create(const char *name)
+{
+	struct mutex *mutex = KOS_MALLOC(sizeof(struct mutex));
+	if (!mutex)
+		return 0;
+	mutex_init(mutex);
+	return mutex;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API oshandle_t
+kos_mutex_open(const char *name)
+{
+	// not implemented
+	return 0;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_free(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	KOS_FREE(mutex);
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_lock(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	if (mutex_lock_interruptible(mutex) == -EINTR)
+		return OS_FAILURE;
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_locktry(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	if (!mutex_trylock(mutex))
+		return OS_FAILURE;
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_mutex_unlock(oshandle_t mutexhandle)
+{
+	struct mutex *mutex = (struct mutex *)mutexhandle;
+	if (!mutex)
+		return OS_FAILURE;
+	KOS_ASSERT(mutex_is_locked(mutex));
+	mutex_unlock(mutex);
+	return OS_SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API unsigned int
+kos_process_getid(void)
+{
+	return current->tgid;
+}
+
+//----------------------------------------------------------------------------
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Creates new event semaphore
+ * \param           uint32 a_manualReset
+ *                  When this param is zero, system automatically resets the
+ *                  event state to nonsignaled after waiting thread has been
+ *                  released
+ * \return          oshandle_t
+*//* ------------------------------------------------------------------- */
+KOS_API oshandle_t
+kos_event_create(int a_manualReset)
+{
+    struct completion *comp = KOS_MALLOC(sizeof(struct completion));
+
+    KOS_ASSERT(comp);
+    if(!comp)
+    {
+        return (oshandle_t)NULL;
+    }
+
+    init_completion(comp);
+
+    return (oshandle_t)comp;
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Frees event semaphore
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_destroy(oshandle_t a_event)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+//  KOS_ASSERT(completion_done(comp));
+
+    KOS_FREE(comp);
+    return (OS_SUCCESS);
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Signals event semaphore
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_signal(oshandle_t a_event)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+    complete_all(comp);     // perhaps complete_all?
+    return (OS_SUCCESS);
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Resets event semaphore state to nonsignaled
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_reset(oshandle_t a_event)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+    INIT_COMPLETION(*comp);
+    return (OS_SUCCESS);
+}
+
+/* ------------------------------------------------------------------- *//*
+ * \brief           Waits event semaphore to be signaled
+ * \param           oshandle_t a_event, event semaphore
+ * \return          int
+*//* ------------------------------------------------------------------- */
+KOS_API int
+kos_event_wait(oshandle_t a_event, int a_milliSeconds)
+{
+    struct completion *comp = (struct completion *)a_event;
+
+    KOS_ASSERT(comp);
+    if(a_milliSeconds == OS_INFINITE)
+    {
+        wait_for_completion_killable(comp);
+    }
+    else
+    {
+        // should interpret milliseconds really to jiffies?
+        if(!wait_for_completion_timeout(comp, msecs_to_jiffies(a_milliSeconds)))
+        {
+            return (OS_FAILURE);
+        }
+    }
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API void
+kos_sleep(unsigned int milliseconds)
+{
+    msleep(milliseconds);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//  query API
+//////////////////////////////////////////////////////////////////////////////
+
+static int
+kos_get_endianness(void)
+{
+    int  value;
+    char* ptr;
+
+    value = 0x01FFFF00;
+
+    ptr = (char*)&value;
+
+    KOS_ASSERT((*ptr == 0x00) || (*ptr == 0x01));
+
+    return (int)*ptr;
+}
+
+//----------------------------------------------------------------------------
+
+KOS_API int
+kos_get_sysinfo(os_sysinfo_t* sysinfo)
+{
+    KOS_ASSERT(sysinfo);
+    if (!sysinfo) return (OS_FAILURE);
+
+    sysinfo->cpu_mhz            = 0;
+    sysinfo->cpu_type           = 0;
+    sysinfo->cpu_version        = 0;
+    sysinfo->os_type            = 0;
+    sysinfo->os_version         = 0;
+    sysinfo->sysmem_size        = 0;
+    sysinfo->page_size          = 0x1000;
+    sysinfo->max_path           = PATH_MAX;
+//  sysinfo->tls_slots          = TLS_MINIMUM_AVAILABLE - 1;
+    sysinfo->endianness         = kos_get_endianness();
+
+    return (OS_SUCCESS);
+}
+
+//----------------------------------------------------------------------------
+
+#ifdef KOS_STATS_ENABLE
+KOS_API int
+kos_get_stats(os_stats_t* stats)
+{
+    kos_memcpy(stats, &kos_stats, sizeof(os_stats_t));
+    return (OS_SUCCESS);
+}
+#else
+KOS_API int
+kos_get_stats(os_stats_t* stats)
+{
+    return (OS_FAILURE);
+}
+#endif // KOS_STATS
+
+/*-------------------------------------------------------------------*//*!
+ * \brief Sync block API
+ *        Same mutex needed from different blocks of driver
+ *//*-------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block start
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+
+static struct mutex* syncblock_mutex = 0;
+
+KOS_API int kos_syncblock_start(void)
+{
+    int return_value;
+
+    if(!syncblock_mutex)
+    {
+        syncblock_mutex = kos_mutex_create("syncblock");
+    }
+
+    if(syncblock_mutex)
+    {
+        return_value = kos_mutex_lock(syncblock_mutex);
+    }
+    else
+    {
+        return_value = -1;
+    }
+
+    return return_value;
+}
+/*-------------------------------------------------------------------*//*!
+ * \external
+ * \brief   Sync block end
+ *
+ * \param   void
+ * \return  Returns NULL if no error, otherwise an error code.
+ *//*-------------------------------------------------------------------*/
+KOS_API int kos_syncblock_end(void)
+{
+    int return_value;
+
+    if(syncblock_mutex)
+    {
+        return_value = kos_mutex_unlock(syncblock_mutex);
+    }
+    else
+    {
+        return_value = -1;
+    }
+
+    return return_value;
+}
+
+KOS_API oshandle_t kos_thread_create(oshandle_t a_function, unsigned int* a_threadId)
+{
+	struct task_struct *task = kthread_run(a_function, 0, "kos_thread_%p", a_threadId);
+	*a_threadId = (unsigned int)task;
+	return (oshandle_t)task;
+}
+
+KOS_API void kos_thread_destroy( oshandle_t a_task )
+{
+	kthread_stop((struct task_struct *)a_task);
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c
new file mode 100644
index 00000000000..51270ada4d3
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c
@@ -0,0 +1,590 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#include "gsl_hal.h"
+#include "gsl_halconfig.h"
+#include "gsl_linux_map.h"
+
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/vmalloc.h>
+
+#include <asm/atomic.h>
+#include <linux/uaccess.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+
+#define GSL_HAL_MEM1                        0
+#define GSL_HAL_MEM2                        1
+#define GSL_HAL_MEM3                        2
+
+/* #define GSL_HAL_DEBUG */
+
+extern phys_addr_t gpu_2d_regbase;
+extern int gpu_2d_regsize;
+extern phys_addr_t gpu_3d_regbase;
+extern int gpu_3d_regsize;
+extern int gmem_size;
+extern phys_addr_t gpu_reserved_mem;
+extern int gpu_reserved_mem_size;
+extern int gpu_2d_irq, gpu_3d_irq;
+
+
+KGSLHAL_API int
+kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[])
+{
+    /* allocate physically contiguous memory */
+
+	int i;
+	void *va;
+
+	va = gsl_linux_map_alloc(virtaddr, numpages*PAGE_SIZE);
+
+	if (!va)
+		return GSL_FAILURE_OUTOFMEM;
+
+	for (i = 0; i < numpages; i++) {
+		scattergatterlist[i] = page_to_phys(vmalloc_to_page(va));
+		va += PAGE_SIZE;
+	}
+
+	return GSL_SUCCESS;
+}
+
+/* --------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[])
+{
+    /* free physical memory */
+
+	gsl_linux_map_free(virtaddr);
+
+    return GSL_SUCCESS;
+}
+
+/* ---------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_init(void)
+{
+    gsl_hal_t *hal;
+    unsigned long totalsize, mem1size;
+    unsigned int va, pa;
+
+    if (gsl_driver.hal) {
+	return GSL_FAILURE_ALREADYINITIALIZED;
+    }
+
+    gsl_driver.hal = (void *)kos_malloc(sizeof(gsl_hal_t));
+
+    if (!gsl_driver.hal) {
+	return GSL_FAILURE_OUTOFMEM;
+    }
+
+    kos_memset(gsl_driver.hal, 0, sizeof(gsl_hal_t));
+
+
+    /* overlay structure on hal memory */
+    hal = (gsl_hal_t *) gsl_driver.hal;
+
+    if (gpu_3d_regbase && gpu_3d_regsize && gpu_3d_irq) {
+	hal->has_z430 = 1;
+    } else {
+	hal->has_z430 = 0;
+    }
+
+    if (gpu_2d_regbase && gpu_2d_regsize && gpu_2d_irq) {
+	hal->has_z160 = 1;
+    } else {
+	hal->has_z160 = 0;
+    }
+
+    /* there is still some problem to enable mmu currently */
+    gsl_driver.enable_mmu = 0;
+
+    /* setup register space */
+    if (hal->has_z430) {
+	hal->z430_regspace.mmio_phys_base = gpu_3d_regbase;
+	hal->z430_regspace.sizebytes = gpu_3d_regsize;
+	hal->z430_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z430_regspace.mmio_phys_base, hal->z430_regspace.sizebytes);
+
+	if (hal->z430_regspace.mmio_virt_base == NULL) {
+	    printk(KERN_ERR "GPU: %s:%d ioremap failed!\n", __func__, __LINE__);
+	    return GSL_FAILURE_SYSTEMERROR;
+	}
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->z430_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_phys_base);
+	printk(KERN_INFO "%s: hal->z430_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_virt_base);
+	printk(KERN_INFO "%s: hal->z430_regspace.sizebytes      = 0x%08x\n", __func__, hal->z430_regspace.sizebytes);
+#endif
+    }
+
+    if (hal->has_z160) {
+	hal->z160_regspace.mmio_phys_base = gpu_2d_regbase;
+	hal->z160_regspace.sizebytes = gpu_2d_regsize;
+	hal->z160_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z160_regspace.mmio_phys_base, hal->z160_regspace.sizebytes);
+
+	if (hal->z160_regspace.mmio_virt_base == NULL) {
+	    printk(KERN_ERR "GPU: %s:%d ioremap failed!\n", __func__, __LINE__);
+	    return GSL_FAILURE_SYSTEMERROR;
+	}
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->z160_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_phys_base);
+	printk(KERN_INFO "%s: hal->z160_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_virt_base);
+	printk(KERN_INFO "%s: hal->z160_regspace.sizebytes      = 0x%08x\n", __func__, hal->z160_regspace.sizebytes);
+#endif
+    }
+
+    if (gsl_driver.enable_mmu) {
+	totalsize = GSL_HAL_SHMEM_SIZE_EMEM2_MMU + GSL_HAL_SHMEM_SIZE_PHYS_MMU;
+	mem1size = GSL_HAL_SHMEM_SIZE_EMEM1_MMU;
+	if (gpu_reserved_mem && gpu_reserved_mem_size >= totalsize) {
+	    pa = gpu_reserved_mem;
+	    va = (unsigned int)ioremap(gpu_reserved_mem, totalsize);
+	    if (!va) {
+		    printk(KERN_ERR "GPU: %s:%d ioremap failed!\n", __func__, __LINE__);
+		    return GSL_FAILURE_SYSTEMERROR;
+	   }
+	} else {
+	    va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
+	}
+    } else {
+	if (gpu_reserved_mem && gpu_reserved_mem_size >= SZ_8M) {
+	    totalsize = gpu_reserved_mem_size;
+	    pa = gpu_reserved_mem;
+	    va = (unsigned int)ioremap(gpu_reserved_mem, gpu_reserved_mem_size);
+	    if (!va) {
+		    printk(KERN_ERR "GPU: %s:%d ioremap failed!\n", __func__, __LINE__);
+		    return GSL_FAILURE_SYSTEMERROR;
+	   }
+	} else {
+	    gpu_reserved_mem = 0;
+	    totalsize = GSL_HAL_SHMEM_SIZE_EMEM1_NOMMU + GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU + GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
+	    va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL);
+	}
+	mem1size = totalsize - (GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU + GSL_HAL_SHMEM_SIZE_PHYS_NOMMU);
+    }
+
+    if (va) {
+	kos_memset((void *)va, 0, totalsize);
+
+	hal->memchunk.mmio_virt_base = (void *)va;
+	hal->memchunk.mmio_phys_base = pa;
+	hal->memchunk.sizebytes      = totalsize;
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_phys_base);
+	printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_virt_base);
+	printk(KERN_INFO "%s: hal->memchunk.sizebytes      = 0x%08x\n", __func__, hal->memchunk.sizebytes);
+#endif
+
+	hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va;
+	hal->memspace[GSL_HAL_MEM2].gpu_base       = pa;
+	if (gsl_driver.enable_mmu) {
+	    hal->memspace[GSL_HAL_MEM2].sizebytes  = GSL_HAL_SHMEM_SIZE_EMEM2_MMU;
+	    va += GSL_HAL_SHMEM_SIZE_EMEM2_MMU;
+	    pa += GSL_HAL_SHMEM_SIZE_EMEM2_MMU;
+	} else {
+	    hal->memspace[GSL_HAL_MEM2].sizebytes  = GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU;
+	    va += GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU;
+	    pa += GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU;
+	}
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base       = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].gpu_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].mmio_virt_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes);
+#endif
+
+	hal->memspace[GSL_HAL_MEM3].mmio_virt_base  = (void *) va;
+	hal->memspace[GSL_HAL_MEM3].gpu_base        = pa;
+	if (gsl_driver.enable_mmu) {
+	    hal->memspace[GSL_HAL_MEM3].sizebytes   = GSL_HAL_SHMEM_SIZE_PHYS_MMU;
+	    va += GSL_HAL_SHMEM_SIZE_PHYS_MMU;
+	    pa += GSL_HAL_SHMEM_SIZE_PHYS_MMU;
+	} else {
+	    hal->memspace[GSL_HAL_MEM3].sizebytes   = GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
+	    va += GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
+	    pa += GSL_HAL_SHMEM_SIZE_PHYS_NOMMU;
+	}
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base       = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].gpu_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].mmio_virt_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes);
+#endif
+
+	if (gsl_driver.enable_mmu) {
+	    gsl_linux_map_init();
+	    hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START;
+	    hal->memspace[GSL_HAL_MEM1].gpu_base       = GSL_LINUX_MAP_RANGE_START;
+	    hal->memspace[GSL_HAL_MEM1].sizebytes      = mem1size;
+	} else {
+	    hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va;
+	    hal->memspace[GSL_HAL_MEM1].gpu_base       = pa;
+	    hal->memspace[GSL_HAL_MEM1].sizebytes      = mem1size;
+	}
+
+#ifdef GSL_HAL_DEBUG
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base       = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].gpu_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].mmio_virt_base);
+	printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes      = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes);
+#endif
+    } else {
+	kgsl_hal_close();
+	return GSL_FAILURE_SYSTEMERROR;
+    }
+
+    return GSL_SUCCESS;
+}
+
+/* ---------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_close(void)
+{
+    gsl_hal_t  *hal;
+
+    if (gsl_driver.hal) {
+	/* overlay structure on hal memory */
+	hal = (gsl_hal_t *) gsl_driver.hal;
+
+	/* unmap registers */
+	if (hal->has_z430 && hal->z430_regspace.mmio_virt_base) {
+	    iounmap(hal->z430_regspace.mmio_virt_base);
+	}
+
+	if (hal->has_z160 && hal->z160_regspace.mmio_virt_base) {
+	    iounmap(hal->z160_regspace.mmio_virt_base);
+	}
+
+	/* free physical block */
+	if (hal->memchunk.mmio_virt_base && gpu_reserved_mem) {
+	    iounmap(hal->memchunk.mmio_virt_base);
+	} else {
+	    dma_free_coherent(0, hal->memchunk.sizebytes, hal->memchunk.mmio_virt_base, hal->memchunk.mmio_phys_base);
+	}
+
+	if (gsl_driver.enable_mmu) {
+	    gsl_linux_map_destroy();
+	}
+
+	/* release hal struct */
+	kos_memset(hal, 0, sizeof(gsl_hal_t));
+	kos_free(gsl_driver.hal);
+	gsl_driver.hal = NULL;
+    }
+
+    return GSL_SUCCESS;
+}
+
+/* ---------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config)
+{
+    int        status = GSL_FAILURE_DEVICEERROR;
+    gsl_hal_t  *hal   = (gsl_hal_t *) gsl_driver.hal;
+
+    kos_memset(config, 0, sizeof(gsl_shmemconfig_t));
+
+    if (hal) {
+	config->numapertures = GSL_SHMEM_MAX_APERTURES;
+
+	if (gsl_driver.enable_mmu) {
+	    config->apertures[0].id    = GSL_APERTURE_MMU;
+	} else {
+	    config->apertures[0].id    = GSL_APERTURE_EMEM;
+	}
+	config->apertures[0].channel   = GSL_CHANNEL_1;
+	config->apertures[0].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM1].mmio_virt_base;
+	config->apertures[0].gpubase   = hal->memspace[GSL_HAL_MEM1].gpu_base;
+	config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes;
+
+	config->apertures[1].id        = GSL_APERTURE_EMEM;
+	config->apertures[1].channel   = GSL_CHANNEL_2;
+	config->apertures[1].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base;
+	config->apertures[1].gpubase   = hal->memspace[GSL_HAL_MEM2].gpu_base;
+	config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes;
+
+	config->apertures[2].id        = GSL_APERTURE_PHYS;
+	config->apertures[2].channel   = GSL_CHANNEL_1;
+	config->apertures[2].hostbase  = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base;
+	config->apertures[2].gpubase   = hal->memspace[GSL_HAL_MEM3].gpu_base;
+	config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes;
+
+	status = GSL_SUCCESS;
+    }
+
+    return status;
+}
+
+/* ---------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config)
+{
+    int        status = GSL_FAILURE_DEVICEERROR;
+    gsl_hal_t  *hal   = (gsl_hal_t *) gsl_driver.hal;
+
+    kos_memset(config, 0, sizeof(gsl_devconfig_t));
+
+    if (hal) {
+	switch (device_id) {
+	case GSL_DEVICE_YAMATO:
+	{
+	    if (hal->has_z430) {
+		mh_mmu_config_u      mmu_config   = {0};
+
+		config->gmemspace.gpu_base        = 0;
+		config->gmemspace.mmio_virt_base  = 0;
+		config->gmemspace.mmio_phys_base  = 0;
+		if (gmem_size) {
+		    config->gmemspace.sizebytes = gmem_size;
+		} else {
+		    config->gmemspace.sizebytes = 0;
+		}
+
+		config->regspace.gpu_base         = 0;
+		config->regspace.mmio_virt_base   = (unsigned char *)hal->z430_regspace.mmio_virt_base;
+		config->regspace.mmio_phys_base   = (unsigned int) hal->z430_regspace.mmio_phys_base;
+		config->regspace.sizebytes        = GSL_HAL_SIZE_REG_YDX;
+
+		mmu_config.f.mmu_enable           = 1;
+
+		if (gsl_driver.enable_mmu) {
+		    mmu_config.f.split_mode_enable    = 0;
+		    mmu_config.f.rb_w_clnt_behavior   = 1;
+		    mmu_config.f.cp_w_clnt_behavior   = 1;
+		    mmu_config.f.cp_r0_clnt_behavior  = 1;
+		    mmu_config.f.cp_r1_clnt_behavior  = 1;
+		    mmu_config.f.cp_r2_clnt_behavior  = 1;
+		    mmu_config.f.cp_r3_clnt_behavior  = 1;
+		    mmu_config.f.cp_r4_clnt_behavior  = 1;
+		    mmu_config.f.vgt_r0_clnt_behavior = 1;
+		    mmu_config.f.vgt_r1_clnt_behavior = 1;
+		    mmu_config.f.tc_r_clnt_behavior   = 1;
+		    mmu_config.f.pa_w_clnt_behavior   = 1;
+		}
+
+		config->mmu_config                = mmu_config.val;
+
+		if (gsl_driver.enable_mmu) {
+		    config->va_base               = hal->memspace[GSL_HAL_MEM1].gpu_base;
+		    config->va_range              = hal->memspace[GSL_HAL_MEM1].sizebytes;
+		} else {
+		    config->va_base               = 0x00000000;
+		    config->va_range              = 0x00000000;
+		}
+
+		/* turn off memory protection unit by setting acceptable physical address range to include all pages */
+		config->mpu_base                  = 0x00000000; /* hal->memchunk.mmio_virt_base; */
+		config->mpu_range                 = 0xFFFFF000; /* hal->memchunk.sizebytes; */
+		status = GSL_SUCCESS;
+	    }
+	    break;
+	}
+
+	case GSL_DEVICE_G12:
+	{
+		mh_mmu_config_u      mmu_config   = {0};
+
+		config->regspace.gpu_base       = 0;
+		config->regspace.mmio_virt_base = (unsigned char *)hal->z160_regspace.mmio_virt_base;
+		config->regspace.mmio_phys_base = (unsigned int) hal->z160_regspace.mmio_phys_base;
+		config->regspace.sizebytes      = GSL_HAL_SIZE_REG_G12;
+
+		mmu_config.f.mmu_enable           = 1;
+
+		if (gsl_driver.enable_mmu) {
+		    config->mmu_config              = 0x00555551;
+		    config->va_base                 = hal->memspace[GSL_HAL_MEM1].gpu_base;
+		    config->va_range                = hal->memspace[GSL_HAL_MEM1].sizebytes;
+		} else {
+		    config->mmu_config              = mmu_config.val;
+		    config->va_base                 = 0x00000000;
+		    config->va_range                = 0x00000000;
+		}
+
+		config->mpu_base                = 0x00000000; /* (unsigned int) hal->memchunk.mmio_virt_base; */
+		config->mpu_range               = 0xFFFFF000; /* hal->memchunk.sizebytes; */
+
+		status = GSL_SUCCESS;
+		break;
+	}
+
+	default:
+		break;
+	}
+    }
+
+    return status;
+}
+
+/*----------------------------------------------------------------------------
+ * kgsl_hal_getchipid
+ *
+ * The proper platform method, build from RBBM_PERIPHIDx and RBBM_PATCH_RELEASE
+ *----------------------------------------------------------------------------
+ */
+KGSLHAL_API gsl_chipid_t
+kgsl_hal_getchipid(gsl_deviceid_t device_id)
+{
+    gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal;
+    gsl_device_t *device = &gsl_driver.device[device_id-1];
+    gsl_chipid_t chipid = 0;
+    unsigned int coreid, majorid, minorid, patchid, revid;
+
+    if (hal->has_z430 && (device_id == GSL_DEVICE_YAMATO)) {
+	device->ftbl.device_regread(device, mmRBBM_PERIPHID1, &coreid);
+	coreid &= 0xF;
+
+	device->ftbl.device_regread(device, mmRBBM_PERIPHID2, &majorid);
+	majorid = (majorid >> 4) & 0xF;
+
+	device->ftbl.device_regread(device, mmRBBM_PATCH_RELEASE, &revid);
+
+	minorid = ((revid >> 0) & 0xFF); /* this is a 16bit field, but extremely unlikely it would ever get this high */
+
+	patchid = ((revid >> 16) & 0xFF);
+
+	chipid = ((coreid << 24) | (majorid << 16) | (minorid << 8) | (patchid << 0));
+    }
+
+    return chipid;
+}
+
+/* --------------------------------------------------------------------------- */
+
+KGSLHAL_API int
+kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value)
+{
+	gsl_device_t *device = &gsl_driver.device[device_id-1];
+	struct clk *gpu_clk = NULL;
+	struct clk *garb_clk = NULL;
+	struct clk *emi_garb_clk = NULL;
+
+	/* unreferenced formal parameters */
+	(void) value;
+
+	switch (device_id) {
+	case GSL_DEVICE_G12:
+		gpu_clk = clk_get(0, "gpu2d_clk");
+		break;
+	case GSL_DEVICE_YAMATO:
+		gpu_clk = clk_get(0, "gpu3d_clk");
+		garb_clk = clk_get(0, "garb_clk");
+		emi_garb_clk = clk_get(0, "emi_garb_clk");
+		break;
+	default:
+		return GSL_FAILURE_DEVICEERROR;
+	}
+
+	if (!gpu_clk) {
+		return GSL_FAILURE_DEVICEERROR;
+	}
+
+	switch (state) {
+	case GSL_PWRFLAGS_CLK_ON:
+		break;
+	case GSL_PWRFLAGS_POWER_ON:
+		clk_enable(gpu_clk);
+		if (garb_clk) {
+			clk_enable(garb_clk);
+		}
+		if (emi_garb_clk) {
+			clk_enable(emi_garb_clk);
+		}
+		kgsl_device_autogate_init(&gsl_driver.device[device_id-1]);
+		break;
+	case GSL_PWRFLAGS_CLK_OFF:
+		break;
+	case GSL_PWRFLAGS_POWER_OFF:
+		if (device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT) != GSL_SUCCESS) {
+			return GSL_FAILURE_DEVICEERROR;
+		}
+		kgsl_device_autogate_exit(&gsl_driver.device[device_id-1]);
+		clk_disable(gpu_clk);
+		if (garb_clk) {
+			clk_disable(garb_clk);
+		}
+		if (emi_garb_clk) {
+			clk_disable(emi_garb_clk);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return GSL_SUCCESS;
+}
+
+KGSLHAL_API int kgsl_clock(gsl_deviceid_t dev, int enable)
+{
+	struct clk *gpu_clk = NULL;
+	struct clk *garb_clk = NULL;
+	struct clk *emi_garb_clk = NULL;
+
+	switch (dev) {
+	case GSL_DEVICE_G12:
+		gpu_clk = clk_get(0, "gpu2d_clk");
+		break;
+	case GSL_DEVICE_YAMATO:
+		gpu_clk = clk_get(0, "gpu3d_clk");
+		garb_clk = clk_get(0, "garb_clk");
+		emi_garb_clk = clk_get(0, "emi_garb_clk");
+		break;
+	default:
+		printk(KERN_ERR "GPU device %d is invalid!\n", dev);
+		return GSL_FAILURE_DEVICEERROR;
+	}
+
+	if (IS_ERR(gpu_clk)) {
+		printk(KERN_ERR "%s: GPU clock get failed!\n", __func__);
+		return GSL_FAILURE_DEVICEERROR;
+	}
+
+	if (enable) {
+		clk_enable(gpu_clk);
+		if (garb_clk) {
+		    clk_enable(garb_clk);
+		}
+		if (emi_garb_clk) {
+		    clk_enable(emi_garb_clk);
+		}
+	} else {
+		clk_disable(gpu_clk);
+		if (garb_clk) {
+		    clk_disable(garb_clk);
+		}
+		if (emi_garb_clk) {
+		    clk_disable(emi_garb_clk);
+		}
+	}
+
+	return GSL_SUCCESS;
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h
new file mode 100644
index 00000000000..305b2ee9066
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h
@@ -0,0 +1,142 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_HWACCESS_LINUX_H
+#define __GSL_HWACCESS_LINUX_H
+
+#ifdef _LINUX
+#include "gsl_linux_map.h"
+#endif
+
+#include <linux/io.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+
+OSINLINE void
+kgsl_hwaccess_memread(void *dst, unsigned int gpubase, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace)
+{
+    if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) {
+        gsl_linux_map_read(dst, gpubase+gpuoffset, sizebytes, touserspace);
+    } else {
+        mb();
+        dsb();
+        if (touserspace)
+        {
+            if (copy_to_user(dst, (void *)(gpubase + gpuoffset), sizebytes))
+            {
+                return;
+            }
+        }
+        else
+        {
+            kos_memcpy(dst, (void *) (gpubase + gpuoffset), sizebytes);
+        }
+        mb();
+        dsb();
+    }
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_memwrite(unsigned int gpubase, unsigned int gpuoffset, void *src, unsigned int sizebytes, unsigned int fromuserspace)
+{
+    if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) {
+        gsl_linux_map_write(src, gpubase+gpuoffset, sizebytes, fromuserspace);
+    } else {
+        mb();
+        dsb();
+        if (fromuserspace)
+        {
+            if (copy_from_user((void *)(gpubase + gpuoffset), src, sizebytes))
+            {
+                return;
+            }
+        }
+        else
+        {
+            kos_memcpy((void *)(gpubase + gpuoffset), src, sizebytes);
+        }
+        mb();
+        dsb();
+    }
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_memset(unsigned int gpubase, unsigned int gpuoffset, unsigned int value, unsigned int sizebytes)
+{
+    if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) {
+	gsl_linux_map_set(gpuoffset+gpubase, value, sizebytes);
+    } else {
+        mb();
+        dsb();
+        kos_memset((void *)(gpubase + gpuoffset), value, sizebytes);
+        mb();
+        dsb();
+    }
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_regread(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int *data)
+{
+    unsigned int *reg;
+
+    // unreferenced formal parameter
+    (void) device_id;
+
+    reg = (unsigned int *)(gpubase + (offsetwords << 2));
+    
+    mb();
+    dsb();
+    *data = __raw_readl(reg);
+    mb();
+    dsb();
+}
+
+//----------------------------------------------------------------------------
+
+OSINLINE void
+kgsl_hwaccess_regwrite(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int data)
+{
+    unsigned int *reg;
+
+    // unreferenced formal parameter
+    (void) device_id;
+
+    reg = (unsigned int *)(gpubase + (offsetwords << 2));
+    mb();
+    dsb();
+    __raw_writel(data, reg);
+    mb();
+    dsb();
+}
+#endif  // __GSL_HWACCESS_WINCE_MX51_H
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c
new file mode 100644
index 00000000000..b67404150e1
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c
@@ -0,0 +1,980 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl_types.h"
+#include "gsl.h"
+#include "gsl_buildconfig.h"
+#include "gsl_halconfig.h"
+#include "gsl_ioctl.h"
+#include "gsl_kmod_cleanup.h"
+#include "gsl_linux_map.h"
+
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/cdev.h>
+#include <linux/platform_device.h>
+#include <linux/vmalloc.h>
+#include <linux/uaccess.h>
+
+#include <mach/mxc_gpu.h>
+
+int gpu_2d_irq, gpu_3d_irq;
+
+phys_addr_t gpu_2d_regbase;
+int gpu_2d_regsize;
+phys_addr_t gpu_3d_regbase;
+int gpu_3d_regsize;
+int gmem_size;
+phys_addr_t gpu_reserved_mem;
+int gpu_reserved_mem_size;
+int z160_version;
+
+static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr);
+static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr);
+static long gsl_kmod_ioctl(struct file *fd, unsigned int cmd, unsigned long arg);
+static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma);
+static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
+static int gsl_kmod_open(struct inode *inode, struct file *fd);
+static int gsl_kmod_release(struct inode *inode, struct file *fd);
+static irqreturn_t z160_irq_handler(int irq, void *dev_id);
+static irqreturn_t z430_irq_handler(int irq, void *dev_id);
+
+static int gsl_kmod_major;
+static struct class *gsl_kmod_class;
+DEFINE_MUTEX(gsl_mutex);
+
+static const struct file_operations gsl_kmod_fops =
+{
+    .owner = THIS_MODULE,
+    .read = gsl_kmod_read,
+    .write = gsl_kmod_write,
+    .unlocked_ioctl = gsl_kmod_ioctl,
+    .mmap = gsl_kmod_mmap,
+    .open = gsl_kmod_open,
+    .release = gsl_kmod_release
+};
+
+static struct vm_operations_struct gsl_kmod_vmops =
+{
+	.fault = gsl_kmod_fault,
+};
+
+static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr)
+{
+    return 0;
+}
+
+static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
+{
+    return 0;
+}
+
+static long gsl_kmod_ioctl(struct file *fd, unsigned int cmd, unsigned long arg)
+{
+    int kgslStatus = GSL_FAILURE;
+
+    switch (cmd) {
+    case IOCTL_KGSL_DEVICE_START:
+        {
+            kgsl_device_start_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_start_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_start(param.device_id, param.flags);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_STOP:
+        {
+            kgsl_device_stop_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_stop_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_stop(param.device_id);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_IDLE:
+        {
+            kgsl_device_idle_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_idle_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_idle(param.device_id, param.timeout);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_ISIDLE:
+        {
+            kgsl_device_isidle_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_isidle_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_isidle(param.device_id);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_GETPROPERTY:
+        {
+            kgsl_device_getproperty_t param;
+            void *tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_getproperty_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            tmp = kmalloc(param.sizebytes, GFP_KERNEL);
+            if (!tmp)
+            {
+                printk(KERN_ERR "%s:kmalloc error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_getproperty(param.device_id, param.type, tmp, param.sizebytes);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.value, tmp, param.sizebytes))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    kfree(tmp);
+                    break;
+                }
+            }
+            else
+            {
+                printk(KERN_ERR "%s: kgsl_device_getproperty error\n", __func__);
+            }
+            kfree(tmp);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_SETPROPERTY:
+        {
+            kgsl_device_setproperty_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_setproperty_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_setproperty(param.device_id, param.type, param.value, param.sizebytes);
+            if (kgslStatus != GSL_SUCCESS)
+            {
+                printk(KERN_ERR "%s: kgsl_device_setproperty error\n", __func__);
+            }
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_REGREAD:
+        {
+            kgsl_device_regread_t param;
+            unsigned int tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_regread_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_regread(param.device_id, param.offsetwords, &tmp);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.value, &tmp, sizeof(unsigned int)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_REGWRITE:
+        {
+            kgsl_device_regwrite_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_regwrite_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_regwrite(param.device_id, param.offsetwords, param.value);
+            break;
+        }
+    case IOCTL_KGSL_DEVICE_WAITIRQ:
+        {
+            kgsl_device_waitirq_t param;
+            unsigned int count;
+
+            printk(KERN_ERR "IOCTL_KGSL_DEVICE_WAITIRQ obsoleted!\n");
+//          kgslStatus = -ENOTTY; break;
+
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_waitirq_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_waitirq(param.device_id, param.intr_id, &count, param.timeout);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.count, &count, sizeof(unsigned int)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS:
+        {
+            kgsl_cmdstream_issueibcmds_t param;
+            gsl_timestamp_t tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_issueibcmds_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_cmdstream_issueibcmds(param.device_id, param.drawctxt_index, param.ibaddr, param.sizedwords, &tmp, param.flags);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_READTIMESTAMP:
+        {
+            kgsl_cmdstream_readtimestamp_t param;
+            gsl_timestamp_t tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_readtimestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            tmp = kgsl_cmdstream_readtimestamp(param.device_id, param.type);
+            if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t)))
+            {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+            }
+            kgslStatus = GSL_SUCCESS;
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP:
+        {
+            int err;
+            kgsl_cmdstream_freememontimestamp_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_freememontimestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            err = del_memblock_from_allocated_list(fd, param.memdesc);
+            if(err)
+            {
+                /* tried to remove a block of memory that is not allocated! 
+                 * NOTE that -EINVAL is Linux kernel's error codes! 
+                 * the drivers error codes COULD mix up with kernel's. */
+                kgslStatus = -EINVAL;
+            }
+            else
+            {
+                kgslStatus = kgsl_cmdstream_freememontimestamp(param.device_id,
+                                                               param.memdesc,
+                                                               param.timestamp,
+                                                               param.type);
+            }
+            break;
+        }
+    case IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP:
+        {
+            kgsl_cmdstream_waittimestamp_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdstream_waittimestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_cmdstream_waittimestamp(param.device_id, param.timestamp, param.timeout);
+            break;
+        }
+    case IOCTL_KGSL_CMDWINDOW_WRITE:
+        {
+            kgsl_cmdwindow_write_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_cmdwindow_write_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_cmdwindow_write(param.device_id, param.target, param.addr, param.data);
+            break;
+        }
+    case IOCTL_KGSL_CONTEXT_CREATE:
+        {
+            kgsl_context_create_t param;
+            unsigned int tmp;
+            int tmpStatus;
+
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_context_create_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_context_create(param.device_id, param.type, &tmp, param.flags);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.drawctxt_id, &tmp, sizeof(unsigned int)))
+                {
+                    tmpStatus = kgsl_context_destroy(param.device_id, tmp);
+                    /* is asserting ok? Basicly we should return the error from copy_to_user
+                     * but will the user space interpret it correctly? Will the user space 
+                     * always check against GSL_SUCCESS  or GSL_FAILURE as they are not the only
+                     * return values.
+                     */
+                    KOS_ASSERT(tmpStatus == GSL_SUCCESS);
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+                else
+                {
+                    add_device_context_to_array(fd, param.device_id, tmp);
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_CONTEXT_DESTROY:
+        {
+            kgsl_context_destroy_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_context_destroy_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_context_destroy(param.device_id, param.drawctxt_id);
+            del_device_context_from_array(fd, param.device_id, param.drawctxt_id);
+            break;
+        }
+    case IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW:
+        {
+            kgsl_drawctxt_bind_gmem_shadow_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_drawctxt_bind_gmem_shadow_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_drawctxt_bind_gmem_shadow(param.device_id, param.drawctxt_id, param.gmem_rect, param.shadow_x, param.shadow_y, param.shadow_buffer, param.buffer_id);
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_ALLOC:
+        {
+            kgsl_sharedmem_alloc_t param;
+            gsl_memdesc_t tmp;
+            int tmpStatus;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_alloc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_alloc(param.device_id, param.flags, param.sizebytes, &tmp);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t)))
+                {
+                    tmpStatus = kgsl_sharedmem_free(&tmp);
+                    KOS_ASSERT(tmpStatus == GSL_SUCCESS);
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+                else
+                {
+                    add_memblock_to_allocated_list(fd, &tmp);
+                }
+	    } else {
+		    printk(KERN_ERR "GPU %s:%d kgsl_sharedmem_alloc failed!\n", __func__, __LINE__);
+	    }
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_FREE:
+        {
+            kgsl_sharedmem_free_t param;
+            gsl_memdesc_t tmp;
+            int err;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_free_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&tmp, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            err = del_memblock_from_allocated_list(fd, &tmp);
+            if(err)
+            {
+                printk(KERN_ERR "%s: tried to free memdesc that was not allocated!\n", __func__);
+                kgslStatus = err;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_free(&tmp);
+            if (kgslStatus == GSL_SUCCESS)
+            {
+                if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t)))
+                {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+                }
+            }
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_READ:
+        {
+            kgsl_sharedmem_read_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_read_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_read(&memdesc, param.dst, param.offsetbytes, param.sizebytes, true);
+            if (kgslStatus != GSL_SUCCESS)
+            {
+                printk(KERN_ERR "%s: kgsl_sharedmem_read failed\n", __func__);
+            }
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_WRITE:
+        {
+            kgsl_sharedmem_write_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_write_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_write(&memdesc, param.offsetbytes, param.src, param.sizebytes, true);
+            if (kgslStatus != GSL_SUCCESS)
+            {
+                printk(KERN_ERR "%s: kgsl_sharedmem_write failed\n", __func__);
+            }
+            
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_SET:
+        {
+            kgsl_sharedmem_set_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_set_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_set(&memdesc, param.offsetbytes, param.value, param.sizebytes);
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK:
+        {
+            kgsl_sharedmem_largestfreeblock_t param;
+            unsigned int largestfreeblock;
+
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_largestfreeblock_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            largestfreeblock = kgsl_sharedmem_largestfreeblock(param.device_id, param.flags);
+            if (copy_to_user(param.largestfreeblock, &largestfreeblock, sizeof(unsigned int)))
+            {
+                printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = GSL_SUCCESS;
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_CACHEOPERATION:
+        {
+            kgsl_sharedmem_cacheoperation_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_cacheoperation_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_cacheoperation(&memdesc, param.offsetbytes, param.sizebytes, param.operation);
+            break;
+        }
+    case IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER:
+        {
+            kgsl_sharedmem_fromhostpointer_t param;
+            gsl_memdesc_t memdesc;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_sharedmem_fromhostpointer_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_sharedmem_fromhostpointer(param.device_id, &memdesc, param.hostptr);
+            break;
+        }
+    case IOCTL_KGSL_ADD_TIMESTAMP:
+        {
+            kgsl_add_timestamp_t param;
+            gsl_timestamp_t tmp;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_add_timestamp_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            tmp = kgsl_add_timestamp(param.device_id, &tmp);
+            if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t)))
+            {
+                    printk(KERN_ERR "%s: copy_to_user error\n", __func__);
+                    kgslStatus = GSL_FAILURE;
+                    break;
+            }
+            kgslStatus = GSL_SUCCESS;
+            break;
+        }
+    
+    case IOCTL_KGSL_DEVICE_CLOCK:
+        {
+            kgsl_device_clock_t param;
+            if (copy_from_user(&param, (void __user *)arg, sizeof(kgsl_device_clock_t)))
+            {
+                printk(KERN_ERR "%s: copy_from_user error\n", __func__);
+                kgslStatus = GSL_FAILURE;
+                break;
+            }
+            kgslStatus = kgsl_device_clock(param.device, param.enable);
+            break;
+        }
+    default:
+        kgslStatus = -ENOTTY;
+        break;
+    }
+
+    return kgslStatus;
+}
+
+static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma)
+{
+    int status = 0;
+    unsigned long start = vma->vm_start;
+    unsigned long pfn = vma->vm_pgoff;
+    unsigned long size = vma->vm_end - vma->vm_start;
+    unsigned long prot = pgprot_writecombine(vma->vm_page_prot);
+    unsigned long addr = vma->vm_pgoff << PAGE_SHIFT;
+    void *va = NULL;
+
+    if (gsl_driver.enable_mmu && (addr < GSL_LINUX_MAP_RANGE_END) && (addr >= GSL_LINUX_MAP_RANGE_START)) {
+	va = gsl_linux_map_find(addr);
+	while (size > 0) {
+	    if (remap_pfn_range(vma, start, vmalloc_to_pfn(va), PAGE_SIZE, prot)) {
+		return -EAGAIN;
+	    }
+	    start += PAGE_SIZE;
+	    va += PAGE_SIZE;
+	    size -= PAGE_SIZE;
+	}
+    } else {
+	if (remap_pfn_range(vma, start, pfn, size, prot)) {
+	    status = -EAGAIN;
+	}
+    }
+
+    vma->vm_ops = &gsl_kmod_vmops;
+
+    return status;
+}
+
+static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+    return VM_FAULT_SIGBUS;
+}
+
+static int gsl_kmod_open(struct inode *inode, struct file *fd)
+{
+    gsl_flags_t flags = 0;
+    struct gsl_kmod_per_fd_data *datp;
+    int err = 0;
+
+    if(mutex_lock_interruptible(&gsl_mutex))
+    {
+        return -EINTR;
+    }
+
+    if (kgsl_driver_entry(flags) != GSL_SUCCESS)
+    {
+        printk(KERN_INFO "%s: kgsl_driver_entry error\n", __func__);
+        err = -EIO;  // TODO: not sure why did it fail?
+    }
+    else
+    {
+        /* allocate per file descriptor data structure */
+        datp = (struct gsl_kmod_per_fd_data *)kzalloc(
+                                             sizeof(struct gsl_kmod_per_fd_data),
+                                             GFP_KERNEL);
+        if(datp)
+        {
+            init_created_contexts_array(datp->created_contexts_array[0]);
+            INIT_LIST_HEAD(&datp->allocated_blocks_head);
+
+            fd->private_data = (void *)datp;
+        }
+        else
+        {
+            err = -ENOMEM;
+        }
+    }
+
+    mutex_unlock(&gsl_mutex);
+
+    return err;
+}
+
+static int gsl_kmod_release(struct inode *inode, struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    int err = 0;
+
+    if(mutex_lock_interruptible(&gsl_mutex))
+    {
+        return -EINTR;
+    }
+
+    /* make sure contexts are destroyed */
+    del_all_devices_contexts(fd);
+
+    if (kgsl_driver_exit() != GSL_SUCCESS)
+    {
+        printk(KERN_INFO "%s: kgsl_driver_exit error\n", __func__);
+        err = -EIO; // TODO: find better error code
+    }
+    else
+    {
+        /* release per file descriptor data structure */
+        datp = (struct gsl_kmod_per_fd_data *)fd->private_data;
+        del_all_memblocks_from_allocated_list(fd);
+        kfree(datp);
+        fd->private_data = 0;
+    }
+
+    mutex_unlock(&gsl_mutex);
+
+    return err;
+}
+
+static struct class *gsl_kmod_class;
+
+static irqreturn_t z160_irq_handler(int irq, void *dev_id)
+{
+    kgsl_intr_isr(&gsl_driver.device[GSL_DEVICE_G12-1]);
+    return IRQ_HANDLED;
+}
+
+static irqreturn_t z430_irq_handler(int irq, void *dev_id)
+{
+    kgsl_intr_isr(&gsl_driver.device[GSL_DEVICE_YAMATO-1]);
+    return IRQ_HANDLED;
+}
+
+static int gpu_probe(struct platform_device *pdev)
+{
+    int i;
+    struct resource *res;
+    struct device *dev;
+    struct mxc_gpu_platform_data *pdata;
+
+    pdata = pdev->dev.platform_data;
+    if (pdata) {
+	z160_version = pdata->z160_revision;
+	gpu_reserved_mem = pdata->reserved_mem_base;
+	gpu_reserved_mem_size = pdata->reserved_mem_size;
+    }
+
+    for(i = 0; i < 2; i++){
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+        if (!res) {
+            if (i == 0) {
+                printk(KERN_ERR "gpu: unable to get gpu irq\n");
+                return -ENODEV;
+            } else {
+                break;
+            }
+        }
+        if(strcmp(res->name, "gpu_2d_irq") == 0){
+            gpu_2d_irq = res->start;
+        }else if(strcmp(res->name, "gpu_3d_irq") == 0){
+            gpu_3d_irq = res->start;
+        }
+    }
+
+    for (i = 0; i < 3; i++) {
+        res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+        if (!res) {
+            gpu_2d_regbase = 0;
+            gpu_2d_regsize = 0;
+            gpu_3d_regbase = 0;
+            gpu_2d_regsize = 0;
+            gmem_size = 0;
+            gpu_reserved_mem = 0;
+            gpu_reserved_mem_size = 0;
+            break;
+        }else{
+            if(strcmp(res->name, "gpu_2d_registers") == 0){
+                gpu_2d_regbase = res->start;
+                gpu_2d_regsize = res->end - res->start + 1;
+            }else if(strcmp(res->name, "gpu_3d_registers") == 0){
+                gpu_3d_regbase = res->start;
+                gpu_3d_regsize = res->end - res->start + 1;
+            }else if(strcmp(res->name, "gpu_graphics_mem") == 0){
+                gmem_size = res->end - res->start + 1;
+            }
+        }
+    }
+
+    if (gpu_3d_irq > 0)
+    {
+	if (request_irq(gpu_3d_irq, z430_irq_handler, 0, "ydx", NULL) < 0) {
+	    printk(KERN_ERR "%s: request_irq error\n", __func__);
+	    gpu_3d_irq = 0;
+	    goto request_irq_error;
+	}
+    }
+
+    if (gpu_2d_irq > 0)
+    {
+	if (request_irq(gpu_2d_irq, z160_irq_handler, 0, "g12", NULL) < 0) {
+	    printk(KERN_ERR "DO NOT use uio_pdrv_genirq kernel module for X acceleration!\n");
+	    gpu_2d_irq = 0;
+	}
+    }
+
+    if (kgsl_driver_init() != GSL_SUCCESS) {
+	printk(KERN_ERR "%s: kgsl_driver_init error\n", __func__);
+	goto kgsl_driver_init_error;
+    }
+
+    gsl_kmod_major = register_chrdev(0, "gsl_kmod", &gsl_kmod_fops);
+    gsl_kmod_vmops.fault = gsl_kmod_fault;
+
+    if (gsl_kmod_major <= 0)
+    {
+        pr_err("%s: register_chrdev error\n", __func__);
+        goto register_chrdev_error;
+    }
+
+    gsl_kmod_class = class_create(THIS_MODULE, "gsl_kmod");
+
+    if (IS_ERR(gsl_kmod_class))
+    {
+        pr_err("%s: class_create error\n", __func__);
+        goto class_create_error;
+    }
+
+    #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28))
+        dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), "gsl_kmod");
+    #else
+        dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), NULL,"gsl_kmod");
+    #endif
+
+    if (!IS_ERR(dev))
+    {
+    //    gsl_kmod_data.device = dev;
+        return 0;
+    }
+
+    pr_err("%s: device_create error\n", __func__);
+
+class_create_error:
+    class_destroy(gsl_kmod_class);
+
+register_chrdev_error:
+    unregister_chrdev(gsl_kmod_major, "gsl_kmod");
+
+kgsl_driver_init_error:
+    kgsl_driver_close();
+    if (gpu_2d_irq > 0) {
+	free_irq(gpu_2d_irq, NULL);
+    }
+    if (gpu_3d_irq > 0) {
+	free_irq(gpu_3d_irq, NULL);
+    }
+request_irq_error:
+    return 0;   // TODO: return proper error code
+}
+
+static int gpu_remove(struct platform_device *pdev)
+{
+    device_destroy(gsl_kmod_class, MKDEV(gsl_kmod_major, 0));
+    class_destroy(gsl_kmod_class);
+    unregister_chrdev(gsl_kmod_major, "gsl_kmod");
+
+    if (gpu_3d_irq)
+    {
+        free_irq(gpu_3d_irq, NULL);
+    }
+
+    if (gpu_2d_irq)
+    {
+        free_irq(gpu_2d_irq, NULL);
+    }
+
+    kgsl_driver_close();
+    return 0;
+}
+
+#ifdef CONFIG_PM
+static int gpu_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    int              i;
+    gsl_powerprop_t  power;
+
+    power.flags = GSL_PWRFLAGS_POWER_OFF;
+    for (i = 0; i < GSL_DEVICE_MAX; i++)
+    {
+        kgsl_device_setproperty(
+                        (gsl_deviceid_t) (i+1),
+                        GSL_PROP_DEVICE_POWER,
+                        &power,
+                        sizeof(gsl_powerprop_t));
+    }   
+
+    return 0;
+}
+
+static int gpu_resume(struct platform_device *pdev)
+{
+    int              i;
+    gsl_powerprop_t  power;
+
+    power.flags = GSL_PWRFLAGS_POWER_ON;
+    for (i = 0; i < GSL_DEVICE_MAX; i++)
+    {
+        kgsl_device_setproperty(
+                        (gsl_deviceid_t) (i+1),
+                        GSL_PROP_DEVICE_POWER,
+                        &power,
+                        sizeof(gsl_powerprop_t));
+    }   
+
+    return 0;
+}
+#else
+#define	gpu_suspend	NULL
+#define	gpu_resume	NULL
+#endif /* !CONFIG_PM */
+
+/*! Driver definition
+ */
+static struct platform_driver gpu_driver = {
+    .driver = {
+        .name = "mxc_gpu",
+        },
+    .probe = gpu_probe,
+    .remove = gpu_remove,
+    .suspend = gpu_suspend,
+    .resume = gpu_resume,
+};
+
+static int __init gsl_kmod_init(void)
+{
+     return platform_driver_register(&gpu_driver);
+}
+
+static void __exit gsl_kmod_exit(void)
+{
+     platform_driver_unregister(&gpu_driver);
+}
+
+module_init(gsl_kmod_init);
+module_exit(gsl_kmod_exit);
+MODULE_AUTHOR("Advanced Micro Devices");
+MODULE_DESCRIPTION("AMD graphics core driver for i.MX");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c
new file mode 100644
index 00000000000..3685a5756ba
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c
@@ -0,0 +1,269 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+ 
+#include "gsl.h"
+#include "gsl_kmod_cleanup.h"
+
+#include <linux/kernel.h>
+#include <linux/fs.h>
+
+/*
+ * Local helper functions to check and convert device/context id's (1 based)
+ * to index (0 based).
+ */
+static u32 device_id_to_device_index(gsl_deviceid_t device_id)
+{
+    KOS_ASSERT((GSL_DEVICE_ANY < device_id) && 
+               (device_id <= GSL_DEVICE_MAX));
+    return (u32)(device_id - 1);
+}
+
+/* 
+ * Local helper function to check and get pointer to per file descriptor data 
+ */
+static struct gsl_kmod_per_fd_data *get_fd_private_data(struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp; 
+
+    KOS_ASSERT(fd);
+    datp = (struct gsl_kmod_per_fd_data *)fd->private_data;
+    KOS_ASSERT(datp);
+    return datp;
+}
+
+static s8 *find_first_entry_with(s8 *subarray, s8 context_id)
+{
+    s8 *entry = NULL;
+    int i;
+
+//printk(KERN_DEBUG "At %s, ctx_id = %d\n", __func__, context_id);
+
+    KOS_ASSERT(context_id >= EMPTY_ENTRY);    
+    KOS_ASSERT(context_id <= GSL_CONTEXT_MAX);  // TODO: check the bound.
+
+    for(i = 0; i < GSL_CONTEXT_MAX; i++)        // TODO: check the bound.
+    {
+        if(subarray[i] == (s8)context_id)
+        {
+            entry = &subarray[i];
+            break;
+        }
+    }
+
+    return entry;
+}
+
+
+/*
+ * Add a memdesc into a list of allocated memory blocks for this file 
+ * descriptor. The list is build in such a way that it implements FIFO (i.e.
+ * list). Traces of tiger, tiger_ri and VG11 CTs should be analysed to make
+ * informed choice.
+ *
+ * NOTE! gsl_memdesc_ts are COPIED so user space should NOT change them.
+ */
+int add_memblock_to_allocated_list(struct file *fd,
+                                   gsl_memdesc_t *allocated_block)
+{
+    int err = 0;
+    struct gsl_kmod_per_fd_data *datp;
+    struct gsl_kmod_alloc_list *lisp;
+    struct list_head *head;
+
+    KOS_ASSERT(allocated_block);
+
+    datp = get_fd_private_data(fd);
+
+    head = &datp->allocated_blocks_head;
+    KOS_ASSERT(head);
+
+    /* allocate and put new entry in the list of allocated memory descriptors */
+    lisp = (struct gsl_kmod_alloc_list *)kzalloc(sizeof(struct gsl_kmod_alloc_list), GFP_KERNEL);
+    if(lisp)
+    {
+        INIT_LIST_HEAD(&lisp->node);
+
+        /* builds FIFO (list_add() would build LIFO) */
+        list_add_tail(&lisp->node, head);
+        memcpy(&lisp->allocated_block, allocated_block, sizeof(gsl_memdesc_t));
+        lisp->allocation_number = datp->maximum_number_of_blocks;
+//        printk(KERN_DEBUG "List entry #%u allocated\n", lisp->allocation_number);
+
+        datp->maximum_number_of_blocks++;
+        datp->number_of_allocated_blocks++;
+
+        err = 0;
+    }
+    else
+    {
+        printk(KERN_ERR "%s: Could not allocate new list element\n", __func__);
+        err = -ENOMEM;
+    }
+
+    return err;
+}
+
+/* Delete a previously allocated memdesc from a list of allocated memory blocks */
+int del_memblock_from_allocated_list(struct file *fd,
+                                     gsl_memdesc_t *freed_block)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    struct gsl_kmod_alloc_list *cursor, *next;
+    struct list_head *head;
+//    int is_different;
+
+    KOS_ASSERT(freed_block);
+
+    datp = get_fd_private_data(fd);
+
+    head = &datp->allocated_blocks_head;
+    KOS_ASSERT(head);
+
+    KOS_ASSERT(datp->number_of_allocated_blocks > 0);
+
+    if(!list_empty(head))
+    {
+        list_for_each_entry_safe(cursor, next, head, node)
+        {
+            if(cursor->allocated_block.gpuaddr == freed_block->gpuaddr)
+            {
+//                is_different = memcmp(&cursor->allocated_block, freed_block, sizeof(gsl_memdesc_t));
+//                KOS_ASSERT(!is_different);
+
+                list_del(&cursor->node);
+//                printk(KERN_DEBUG "List entry #%u freed\n", cursor->allocation_number);
+                kfree(cursor);
+                datp->number_of_allocated_blocks--;
+                return 0;
+            }
+        }
+    }
+    return -EINVAL; // tried to free entry not existing or from empty list.
+}
+
+/* Delete all previously allocated memdescs from a list */
+int del_all_memblocks_from_allocated_list(struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    struct gsl_kmod_alloc_list *cursor, *next;
+    struct list_head *head;
+
+    datp = get_fd_private_data(fd);
+
+    head = &datp->allocated_blocks_head;
+    KOS_ASSERT(head);
+
+    if(!list_empty(head))
+    {
+        printk(KERN_INFO "Not all allocated memory blocks were freed. Doing it now.\n");
+        list_for_each_entry_safe(cursor, next, head, node)
+        {
+            printk(KERN_INFO "Freeing list entry #%u, gpuaddr=%x\n", (u32)cursor->allocation_number, cursor->allocated_block.gpuaddr);
+            kgsl_sharedmem_free(&cursor->allocated_block);
+            list_del(&cursor->node);
+            kfree(cursor);
+        }
+    }
+
+    KOS_ASSERT(list_empty(head));
+    datp->number_of_allocated_blocks = 0;
+
+    return 0;
+}
+
+void init_created_contexts_array(s8 *array)
+{
+    memset((void*)array, EMPTY_ENTRY, GSL_DEVICE_MAX * GSL_CONTEXT_MAX);
+}
+
+
+void add_device_context_to_array(struct file *fd,
+                                 gsl_deviceid_t device_id,
+                                 unsigned int context_id)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    s8 *entry;
+    s8 *subarray;
+    u32 device_index = device_id_to_device_index(device_id);
+
+    datp = get_fd_private_data(fd);
+
+    subarray = datp->created_contexts_array[device_index];
+    entry = find_first_entry_with(subarray, EMPTY_ENTRY);
+
+    KOS_ASSERT(entry);
+    KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) &&
+               (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX));
+    KOS_ASSERT(context_id < 127);
+    *entry = (s8)context_id;
+}
+
+void del_device_context_from_array(struct file *fd, 
+                                   gsl_deviceid_t device_id,
+                                   unsigned int context_id)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    u32 device_index = device_id_to_device_index(device_id);
+    s8 *entry;
+    s8 *subarray;
+
+    datp = get_fd_private_data(fd);
+
+    KOS_ASSERT(context_id < 127);
+    subarray = &(datp->created_contexts_array[device_index][0]);
+    entry = find_first_entry_with(subarray, context_id);
+    KOS_ASSERT(entry);
+    KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) &&
+               (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX));
+    *entry = EMPTY_ENTRY;
+}
+
+void del_all_devices_contexts(struct file *fd)
+{
+    struct gsl_kmod_per_fd_data *datp;
+    gsl_deviceid_t id;
+    u32 device_index;
+    u32 ctx_array_index;
+    s8 ctx;
+    int err;
+    
+    datp = get_fd_private_data(fd);
+
+    /* device_id is 1 based */
+    for(id = GSL_DEVICE_ANY + 1; id <= GSL_DEVICE_MAX; id++)
+    {
+        device_index = device_id_to_device_index(id);
+        for(ctx_array_index = 0; ctx_array_index < GSL_CONTEXT_MAX; ctx_array_index++)
+        {
+            ctx = datp->created_contexts_array[device_index][ctx_array_index];
+            if(ctx != EMPTY_ENTRY)
+            {
+                err = kgsl_context_destroy(id, ctx);
+                if(err != GSL_SUCCESS)
+                {
+                    printk(KERN_ERR "%s: could not destroy context %d on device id = %u\n", __func__, ctx, id);
+                }
+                else
+                {
+                    printk(KERN_DEBUG "%s: Destroyed context %d on device id = %u\n", __func__, ctx, id);
+                }
+            }
+        }
+    }
+}
+
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h
new file mode 100644
index 00000000000..475ee3be2e5
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h
@@ -0,0 +1,90 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_KMOD_CLEANUP_H
+#define __GSL_KMOD_CLEANUP_H
+#include "gsl_types.h"
+
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/list.h>
+
+#if (GSL_CONTEXT_MAX > 127)
+    #error created_contexts_array supports context numbers only 127 or less.
+#endif
+
+static const s8 EMPTY_ENTRY = -1;
+
+/* A structure to make list of allocated memory blocks. List per fd. */
+/* should probably be allocated from slab cache to minimise fragmentation */
+struct gsl_kmod_alloc_list
+{
+    struct list_head node;
+    gsl_memdesc_t allocated_block;
+    u32 allocation_number;
+};
+
+/* A structure to hold abovementioned list of blocks. Contain per fd data. */
+struct gsl_kmod_per_fd_data
+{
+    struct list_head allocated_blocks_head; // list head
+    u32 maximum_number_of_blocks;
+    u32 number_of_allocated_blocks;
+    s8 created_contexts_array[GSL_DEVICE_MAX][GSL_CONTEXT_MAX];
+};
+
+
+/* 
+ * prototypes 
+ */
+
+/* allocated memory block tracking */
+int add_memblock_to_allocated_list(struct file *fd,
+                                   gsl_memdesc_t *allocated_block);
+
+int del_memblock_from_allocated_list(struct file *fd,
+                                     gsl_memdesc_t *freed_block);
+
+int del_all_memblocks_from_allocated_list(struct file *fd);
+
+/* created contexts tracking */
+void init_created_contexts_array(s8 *array);
+
+void add_device_context_to_array(struct file *fd,
+                                 gsl_deviceid_t device_id,
+                                 unsigned int context_id);
+
+void del_device_context_from_array(struct file *fd, 
+                                   gsl_deviceid_t device_id,
+                                   unsigned int context_id);
+
+void del_all_devices_contexts(struct file *fd);
+
+#endif  // __GSL_KMOD_CLEANUP_H
+
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c
new file mode 100644
index 00000000000..7fee7b81441
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c
@@ -0,0 +1,221 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/vmalloc.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+
+#include "gsl_linux_map.h"
+
+struct gsl_linux_map
+{
+	struct list_head list;
+	unsigned int gpu_addr;
+	void *kernel_virtual_addr;
+	unsigned int size;
+};
+
+static LIST_HEAD(gsl_linux_map_list);
+static DEFINE_MUTEX(gsl_linux_map_mutex);
+
+int gsl_linux_map_init()
+{
+	mutex_lock(&gsl_linux_map_mutex);
+	INIT_LIST_HEAD(&gsl_linux_map_list);
+	mutex_unlock(&gsl_linux_map_mutex);
+
+	return 0;
+}
+
+void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+	void *va;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr == gpu_addr){
+			mutex_unlock(&gsl_linux_map_mutex);
+			return map->kernel_virtual_addr;
+		}
+	}
+
+	va = __vmalloc(size, GFP_KERNEL, pgprot_noncached(pgprot_kernel));
+	if(va == NULL){
+		mutex_unlock(&gsl_linux_map_mutex);
+		return NULL;
+	}
+
+	map = (struct gsl_linux_map *)kmalloc(sizeof(*map), GFP_KERNEL);
+	map->gpu_addr = gpu_addr;
+	map->kernel_virtual_addr = va;
+	map->size = size;
+
+	INIT_LIST_HEAD(&map->list);
+	list_add_tail(&map->list, &gsl_linux_map_list);
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return va;
+}
+
+void gsl_linux_map_free(unsigned int gpu_addr)
+{
+	int found = 0;
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr == gpu_addr){
+			found = 1;
+			break;
+		}
+	}
+
+	if(found){
+		vfree(map->kernel_virtual_addr);
+		list_del(&map->list);
+		kfree(map);
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+}
+
+void *gsl_linux_map_find(unsigned int gpu_addr)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr == gpu_addr){
+			mutex_unlock(&gsl_linux_map_mutex);
+			return map->kernel_virtual_addr;
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr <= gpuoffset && 
+			(map->gpu_addr +  map->size) > gpuoffset){
+			void *src = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr);
+			mutex_unlock(&gsl_linux_map_mutex);
+                        if (touserspace)
+                        {
+                            return (void *)copy_to_user(dst, map->kernel_virtual_addr + gpuoffset - map->gpu_addr, sizebytes);
+                        }
+                        else
+                        {
+	                    return memcpy(dst, src, sizebytes);
+                        }
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr <= gpuoffset && 
+			(map->gpu_addr +  map->size) > gpuoffset){
+			void *dst = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr);
+			mutex_unlock(&gsl_linux_map_mutex);
+                        if (fromuserspace)
+                        {
+                            return (void *)copy_from_user(map->kernel_virtual_addr + gpuoffset - map->gpu_addr, src, sizebytes);
+                        }
+                        else
+                        {
+                            return memcpy(dst, src, sizebytes);
+                        }
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes)
+{
+	struct gsl_linux_map * map;
+	struct list_head *p;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each(p, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		if(map->gpu_addr <= gpuoffset && 
+			(map->gpu_addr +  map->size) > gpuoffset){
+			void *ptr = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr);
+			mutex_unlock(&gsl_linux_map_mutex);
+			return memset(ptr, value, sizebytes);
+		}
+	}
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return NULL;
+}
+
+int gsl_linux_map_destroy()
+{
+	struct gsl_linux_map * map;
+	struct list_head *p, *tmp;
+
+	mutex_lock(&gsl_linux_map_mutex);
+	
+	list_for_each_safe(p, tmp, &gsl_linux_map_list){
+		map = list_entry(p, struct gsl_linux_map, list);
+		vfree(map->kernel_virtual_addr);
+		list_del(&map->list);
+		kfree(map);
+	}
+
+	INIT_LIST_HEAD(&gsl_linux_map_list);
+
+	mutex_unlock(&gsl_linux_map_mutex);
+	return 0;
+}
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h
new file mode 100644
index 00000000000..ebbe94a75e1
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h
@@ -0,0 +1,46 @@
+/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __GSL_LINUX_MAP_H__
+#define __GSL_LINUX_MAP_H__
+
+#include "gsl_halconfig.h"
+
+#define GSL_LINUX_MAP_RANGE_START (1024*1024)
+#define GSL_LINUX_MAP_RANGE_END (GSL_LINUX_MAP_RANGE_START+GSL_HAL_SHMEM_SIZE_EMEM1_MMU)
+
+int gsl_linux_map_init(void);
+void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size);
+void gsl_linux_map_free(unsigned int gpu_addr);
+void *gsl_linux_map_find(unsigned int gpu_addr);
+void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace);
+void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace);
+void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes);
+int gsl_linux_map_destroy(void);
+
+#endif
diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/misc.c b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c
new file mode 100644
index 00000000000..b3a4582bb15
--- /dev/null
+++ b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <gsl.h>
+
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/hardirq.h>
+#include <linux/semaphore.h>
+
+typedef struct _gsl_autogate_t {
+    struct timer_list timer;	
+    spinlock_t lock;
+    int active;
+    /* pending indicate the timer has been fired but clock not yet disabled. */
+    int pending;
+    int timeout;
+    gsl_device_t *dev;
+    struct work_struct dis_task;
+} gsl_autogate_t;
+
+static gsl_autogate_t *g_autogate[2];
+static DEFINE_SEMAPHORE(sem_dev);
+
+#define KGSL_DEVICE_IDLE_TIMEOUT 5000	/* unit ms */
+
+static void clk_disable_task(struct work_struct *work)
+{
+	gsl_autogate_t *autogate;
+	autogate = container_of(work, gsl_autogate_t, dis_task);
+	if (autogate->dev->ftbl.device_idle)
+		autogate->dev->ftbl.device_idle(autogate->dev, GSL_TIMEOUT_DEFAULT);
+	kgsl_clock(autogate->dev->id, 0);
+	autogate->pending = 0;
+}
+
+static int _kgsl_device_active(gsl_device_t *dev, int all)
+{
+	unsigned long flags;
+	int to_active = 0;
+	gsl_autogate_t *autogate = dev->autogate;
+	if (!autogate) {
+		printk(KERN_ERR "%s: autogate has exited!\n", __func__);
+		return 0;
+	}
+//	printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id, autogate->active);
+
+	spin_lock_irqsave(&autogate->lock, flags);
+	if (in_interrupt()) {
+		if (!autogate->active && !autogate->pending)
+			BUG();
+	} else {
+		to_active = !autogate->active;
+		autogate->active = 1;
+	}
+	mod_timer(&autogate->timer, jiffies + msecs_to_jiffies(autogate->timeout));
+	spin_unlock_irqrestore(&autogate->lock, flags);
+	if (to_active)
+		kgsl_clock(autogate->dev->id, 1);
+	if (to_active && all) {
+		int index;
+		index = autogate->dev->id == GSL_DEVICE_G12 ? GSL_DEVICE_YAMATO - 1 :
+			GSL_DEVICE_G12 - 1;
+		down(&sem_dev);
+		if (g_autogate[index])
+			_kgsl_device_active(g_autogate[index]->dev, 0);
+		up(&sem_dev);
+	}
+	return 0;
+}
+int kgsl_device_active(gsl_device_t *dev)
+{
+	return _kgsl_device_active(dev, 0);
+}
+
+static void kgsl_device_inactive(unsigned long data)
+{
+	gsl_autogate_t *autogate = (gsl_autogate_t *)data;
+	unsigned long flags;
+
+//	printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, autogate->dev->id, autogate->active);
+	del_timer(&autogate->timer);
+	spin_lock_irqsave(&autogate->lock, flags);
+	WARN(!autogate->active, "GPU Device %d is already inactive\n", autogate->dev->id);
+	if (autogate->active) {
+		autogate->active = 0;
+		autogate->pending = 1;
+		schedule_work(&autogate->dis_task);
+	}
+	spin_unlock_irqrestore(&autogate->lock, flags);
+}
+
+int kgsl_device_clock(gsl_deviceid_t id, int enable)
+{
+	int ret = GSL_SUCCESS;
+	gsl_device_t *device;
+
+	device = &gsl_driver.device[id-1];       // device_id is 1 based
+	if (device->flags & GSL_FLAGS_INITIALIZED) {
+		if (enable)
+			kgsl_device_active(device);
+		else
+			kgsl_device_inactive((unsigned long)device);
+	} else {
+		printk(KERN_ERR "%s: Dev %d clock is already off!\n", __func__, id);
+		ret = GSL_FAILURE;
+	}
+	
+	return ret;
+}
+
+int kgsl_device_autogate_init(gsl_device_t *dev)
+{
+	gsl_autogate_t *autogate;
+
+//	printk(KERN_ERR "%s:%d id %d\n", __func__, __LINE__, dev->id);
+	autogate = kzalloc(sizeof(gsl_autogate_t), GFP_KERNEL);
+	if (!autogate) {
+		printk(KERN_ERR "%s: out of memory!\n", __func__);
+		return -ENOMEM;
+	}
+	down(&sem_dev);
+	autogate->dev = dev;
+	autogate->active = 1;
+	spin_lock_init(&autogate->lock);
+	autogate->timeout = KGSL_DEVICE_IDLE_TIMEOUT;
+	init_timer(&autogate->timer);
+	autogate->timer.expires = jiffies + msecs_to_jiffies(autogate->timeout);
+	autogate->timer.function = kgsl_device_inactive;
+	autogate->timer.data = (unsigned long)autogate;
+	add_timer(&autogate->timer);
+	INIT_WORK(&autogate->dis_task, clk_disable_task);
+	dev->autogate = autogate;
+	g_autogate[dev->id - 1] = autogate;
+	up(&sem_dev);
+	return 0;
+}
+
+void kgsl_device_autogate_exit(gsl_device_t *dev)
+{
+	gsl_autogate_t *autogate = dev->autogate;
+
+//	printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id,  autogate->active);
+	down(&sem_dev);
+	del_timer_sync(&autogate->timer);
+	if (!autogate->active)
+		kgsl_clock(autogate->dev->id, 1);
+	flush_work(&autogate->dis_task);
+	g_autogate[dev->id - 1] = NULL;
+	up(&sem_dev);
+	kfree(autogate);
+	dev->autogate = NULL;
+}
diff --git a/drivers/mxc/ipu3/Kconfig b/drivers/mxc/ipu3/Kconfig
new file mode 100644
index 00000000000..b1461ce4624
--- /dev/null
+++ b/drivers/mxc/ipu3/Kconfig
@@ -0,0 +1,11 @@
+config MXC_IPU_V3
+	bool
+
+config MXC_IPU_V3D
+	bool
+
+config MXC_IPU_V3EX
+	bool
+
+config MXC_IPU_V3H
+	bool
diff --git a/drivers/mxc/ipu3/Makefile b/drivers/mxc/ipu3/Makefile
new file mode 100644
index 00000000000..8be29736b80
--- /dev/null
+++ b/drivers/mxc/ipu3/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_MXC_IPU_V3) = mxc_ipu.o
+
+mxc_ipu-objs := ipu_common.o ipu_ic.o ipu_disp.o ipu_capture.o ipu_device.o ipu_calc_stripes_sizes.o
diff --git a/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
new file mode 100644
index 00000000000..1e05cc5808b
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
@@ -0,0 +1,376 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_calc_stripes_sizes.c
+ *
+ * @brief IPU IC functions
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/module.h>
+#include <mach/ipu-v3.h>
+#include <asm/div64.h>
+
+#define BPP_32 0
+#define BPP_16 3
+#define BPP_8 5
+#define BPP_24 1
+#define BPP_12 4
+#define BPP_18 2
+
+static u64 _do_div(u64 a, u32 b)
+{
+	u64 div;
+	div = a;
+	do_div(div, b);
+	return div;
+}
+
+static u32 truncate(u32 up, /* 0: down; else: up */
+					u64 a, /* must be non-negative */
+					u32 b)
+{
+	u32 d;
+	u64 div;
+	div = _do_div(a, b);
+	d = b * (div >> 32);
+	if (up && (a > (((u64)d) << 32)))
+		return d+b;
+	else
+		return d;
+}
+
+/*static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
+{[> return input_f <]
+	unsigned int f_calculated = 0;
+	switch (pfs) {
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YVU420P:
+		f_calculated = 16;
+		break;
+
+	case IPU_PIX_FMT_NV12:
+		f_calculated = 8;
+		break;
+
+	default:
+		f_calculated = 0;
+		break;
+
+	}
+	if (!f_calculated) {
+		switch (bpp) {
+		case BPP_32:
+			f_calculated = 2;
+			break;
+
+		case BPP_16:
+			f_calculated = 4;
+			break;
+
+		case BPP_8:
+		case BPP_24:
+			f_calculated = 8;
+			break;
+
+		case BPP_12:
+			f_calculated = 16;
+			break;
+
+		case BPP_18:
+			f_calculated = 32;
+			break;
+
+		default:
+			f_calculated = 0;
+			break;
+			}
+		}
+	return f_calculated;
+}
+
+
+static unsigned int m_calc(unsigned int pfs)
+{
+	unsigned int m_calculated = 0;
+	switch (pfs) {
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_NV12:
+		m_calculated = 8;
+		break;
+
+	case IPU_PIX_FMT_YUYV:
+	case IPU_PIX_FMT_UYVY:
+		m_calculated = 2;
+		break;
+
+	default:
+		m_calculated = 1;
+		break;
+
+	}
+	return m_calculated;
+}*/
+
+
+/* Stripe parameters calculator */
+/**************************************************************************
+Notes:
+MSW = the maximal width allowed for a stripe
+	i.MX31: 720, i.MX35: 800, i.MX37/51/53: 1024
+cirr = the maximal inverse resizing ratio for which overlap in the input
+	is requested; typically cirr~2
+equal_stripes:
+	0: each stripe is allowed to have independent parameters
+		for maximal image quality
+	1: the stripes are requested to have identical parameters
+	(except the base address), for maximal performance
+If performance is the top priority (above image quality)
+	Avoid overlap, by setting CIRR = 0
+		This will also force effectively identical_stripes = 1
+	Choose IF & OF that corresponds to the same IOX/SX for both stripes
+	Choose IFW & OFW such that
+	IFW/IM, IFW/IF, OFW/OM, OFW/OF are even integers
+	The function returns an error status:
+	0: no error
+	1: invalid input parameters -> aborted without result
+		Valid parameters should satisfy the following conditions
+		IFW <= OFW, otherwise downsizing is required
+					 - which is not supported yet
+		4 <= IFW,OFW, so some interpolation may be needed even without overlap
+		IM, OM, IF, OF should not vanish
+		2*IF <= IFW
+		so the frame can be split to two equal stripes, even without overlap
+		2*(OF+IF/irr_opt) <= OFW
+		so a valid positive INW exists even for equal stripes
+		OF <= MSW, otherwise, the left stripe cannot be sufficiently large
+		MSW < OFW, so splitting to stripes is required
+		OFW <= 2*MSW, so two stripes are sufficient
+		(this also implies that 2<=MSW)
+	2: OF is not a multiple of OM - not fully-supported yet
+	Output is produced but OW is not guaranited to be a multiple of OM
+	4: OFW reduced to be a multiple of OM
+	8: CIRR > 1: truncated to 1
+	Overlap is not supported (and not needed) y for upsizing)
+**************************************************************************/
+int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
+			   /* input frame width;>1 */
+			   unsigned int output_frame_width, /* output frame width; >1 */
+			   const unsigned int maximal_stripe_width,
+			   /* the maximal width allowed for a stripe */
+			   const unsigned long long cirr, /* see above */
+			   const unsigned int equal_stripes, /* see above */
+			   u32 input_pixelformat,/* pixel format after of read channel*/
+			   u32 output_pixelformat,/* pixel format after of write channel*/
+			   struct stripe_param *left,
+			   struct stripe_param *right)
+{
+	const unsigned int irr_frac_bits = 13;
+	const unsigned long irr_steps = 1 << irr_frac_bits;
+	const u64 dirr = ((u64)1) << (32 - 2);
+	/* The maximum relative difference allowed between the irrs */
+	const u64 cr = ((u64)4) << 32;
+	/* The importance ratio between the two terms in the cost function below */
+
+	unsigned int status;
+	unsigned int temp;
+	unsigned int onw_min;
+	unsigned int inw, onw, inw_best = 0;
+	/* number of pixels in the left stripe NOT hidden by the right stripe */
+	u64 irr_opt; /* the optimal inverse resizing ratio */
+	u64 rr_opt; /* the optimal resizing ratio = 1/irr_opt*/
+	u64 dinw; /* the misalignment between the stripes */
+	/* (measured in units of input columns) */
+	u64 difwl, difwr;
+	/* The number of input columns not reflected in the output */
+	/* the resizing ratio used for the right stripe is */
+	/*   left->irr and right->irr respectively */
+	u64 cost, cost_min;
+	u64 div; /* result of division */
+
+	unsigned int input_m, input_f, output_m, output_f; /* parameters for upsizing by stripes */
+
+	status = 0;
+
+	/* M, F calculations */
+	/* read back pfs from params */
+
+	input_f = 16;
+	input_m = 16;
+	/* BPP should be used in the out_F calc */
+	/* Temporarily not used */
+	/* out_F = F_calc(idmac->pfs, idmac->bpp, NULL); */
+
+	output_f = 16;
+	output_m = 16;
+
+
+	if ((input_frame_width < 4) || (output_frame_width < 4))
+		return 1;
+
+	irr_opt = _do_div((((u64)(input_frame_width - 1)) << 32),
+			  (output_frame_width - 1));
+	rr_opt = _do_div((((u64)(output_frame_width - 1)) << 32),
+			 (input_frame_width - 1));
+
+	if ((input_m == 0) || (output_m == 0) || (input_f == 0) || (output_f == 0)
+	    || (input_frame_width < (2 * input_f))
+	    || ((((u64)output_frame_width) << 32) <
+		(2 * ((((u64)output_f) << 32) + (input_f * rr_opt))))
+	    || (maximal_stripe_width < output_f)
+	    || (output_frame_width <= maximal_stripe_width)
+	    || ((2 * maximal_stripe_width) < output_frame_width))
+		return 1;
+
+	if (output_f % output_m)
+		status += 2;
+
+	temp = truncate(0, (((u64)output_frame_width) << 32), output_m);
+	if (temp < output_frame_width) {
+		output_frame_width = temp;
+		status += 4;
+	}
+
+	if (equal_stripes) {
+		if ((irr_opt > cirr) /* overlap in the input is not requested */
+		    && ((input_frame_width % (input_m << 1)) == 0)
+		    && ((input_frame_width % (input_f << 1)) == 0)
+		    && ((output_frame_width % (output_m << 1)) == 0)
+		    && ((output_frame_width % (output_f << 1)) == 0)) {
+			/* without overlap */
+			left->input_width = right->input_width = right->input_column =
+				input_frame_width >> 1;
+			left->output_width = right->output_width = right->output_column =
+				output_frame_width >> 1;
+			left->input_column = 0;
+			left->output_column = 0;
+			div = _do_div(((((u64)irr_steps) << 32) *
+				       (right->input_width - 1)), (right->output_width - 1));
+			left->irr = right->irr = truncate(0, div, 1);
+		} else { /* with overlap */
+			onw = truncate(0, (((u64)output_frame_width - 1) << 32) >> 1,
+				       output_f);
+			inw = truncate(0, onw * irr_opt, input_f);
+			/* this is the maximal inw which allows the same resizing ratio */
+			/* in both stripes */
+			onw = truncate(1, (inw * rr_opt), output_f);
+			div = _do_div((((u64)(irr_steps * inw)) <<
+				       32), onw);
+			left->irr = right->irr = truncate(0, div, 1);
+			left->output_width = right->output_width =
+				output_frame_width - onw;
+			/* These are valid assignments for output_width, */
+			/* assuming output_f is a multiple of output_m */
+			div = (((u64)(left->output_width-1) * (left->irr)) << 32);
+			div = (((u64)1) << 32) + _do_div(div, irr_steps);
+
+			left->input_width = right->input_width = truncate(1, div, input_m);
+
+			div = _do_div((((u64)((right->output_width - 1) * right->irr)) <<
+				       32), irr_steps);
+			difwr = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
+			div = _do_div((difwr + (((u64)input_f) << 32)), 2);
+			left->input_column = truncate(0, div, input_f);
+
+
+			/* This splits the truncated input columns evenly */
+			/*    between the left and right margins */
+			right->input_column = left->input_column + inw;
+			left->output_column = 0;
+			right->output_column = onw;
+		}
+	} else { /* independent stripes */
+		onw_min = output_frame_width - maximal_stripe_width;
+		/* onw is a multiple of output_f, in the range */
+		/* [max(output_f,output_frame_width-maximal_stripe_width),*/
+		/*min(output_frame_width-2,maximal_stripe_width)] */
+		/* definitely beyond the cost of any valid setting */
+		cost_min = (((u64)input_frame_width) << 32) + cr;
+		onw = truncate(0, ((u64)maximal_stripe_width), output_f);
+		if (output_frame_width - onw == 1)
+			onw -= output_f; /*  => onw and output_frame_width-1-onw are positive */
+		inw = truncate(0, onw * irr_opt, input_f);
+		/* this is the maximal inw which allows the same resizing ratio */
+		/* in both stripes */
+		onw = truncate(1, inw * rr_opt, output_f);
+		do {
+			div = _do_div((((u64)(irr_steps * inw)) << 32), onw);
+			left->irr = truncate(0, div, 1);
+			div = _do_div((((u64)(onw * left->irr)) << 32),
+				      irr_steps);
+			dinw = (((u64)inw) << 32) - div;
+
+			div = _do_div((((u64)((output_frame_width - 1 - onw) * left->irr)) <<
+				       32), irr_steps);
+
+			difwl = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
+
+			cost = difwl + (((u64)(cr * dinw)) >> 32);
+
+			if (cost < cost_min) {
+				inw_best = inw;
+				cost_min = cost;
+			}
+
+			inw -= input_f;
+			onw = truncate(1, inw * rr_opt, output_f);
+			/* This is the minimal onw which allows the same resizing ratio */
+			/*     in both stripes */
+		} while (onw >= onw_min);
+
+		inw = inw_best;
+		onw = truncate(1, inw * rr_opt, output_f);
+		div = _do_div((((u64)(irr_steps * inw)) << 32), onw);
+		left->irr = truncate(0, div, 1);
+
+		left->output_width = onw;
+		right->output_width = output_frame_width - onw;
+		/* These are valid assignments for output_width, */
+		/* assuming output_f is a multiple of output_m */
+		left->input_width = truncate(1, ((u64)(inw + 1)) << 32, input_m);
+		right->input_width = truncate(1, ((u64)(input_frame_width - inw)) <<
+					      32, input_m);
+
+		div = _do_div((((u64)(irr_steps * (input_frame_width - 1 - inw))) <<
+			       32), (right->output_width - 1));
+		right->irr = truncate(0, div, 1);
+		temp = truncate(0, ((u64)left->irr) * ((((u64)1) << 32) + dirr), 1);
+		if (temp < right->irr)
+			right->irr = temp;
+		div = _do_div(((u64)((right->output_width - 1) * right->irr) <<
+			       32), irr_steps);
+		difwr = (u64)(input_frame_width - 1 - inw) - div;
+
+
+		div = _do_div((difwr + (((u64)input_f) << 32)), 2);
+		left->input_column = truncate(0, div, input_f);
+
+		/* This splits the truncated input columns evenly */
+		/*    between the left and right margins */
+		right->input_column = left->input_column + inw;
+		left->output_column = 0;
+		right->output_column = onw;
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(ipu_calc_stripes_sizes);
diff --git a/drivers/mxc/ipu3/ipu_capture.c b/drivers/mxc/ipu3/ipu_capture.c
new file mode 100644
index 00000000000..816e6ebf6c4
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_capture.c
@@ -0,0 +1,747 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_capture.c
+ *
+ * @brief IPU capture dase functions
+ *
+ * @ingroup IPU
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <mach/ipu-v3.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+
+/*!
+ * ipu_csi_init_interface
+ *	Sets initial values for the CSI registers.
+ *	The width and height of the sensor and the actual frame size will be
+ *	set to the same values.
+ * @param	ipu		ipu handler
+ * @param	width		Sensor width
+ * @param       height		Sensor height
+ * @param       pixel_fmt	pixel format
+ * @param       cfg_param	ipu_csi_signal_cfg_t structure
+ * @param       csi             csi 0 or csi 1
+ *
+ * @return      0 for success, -EINVAL for error
+ */
+int32_t
+ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
+	uint32_t pixel_fmt, ipu_csi_signal_cfg_t cfg_param)
+{
+	uint32_t data = 0;
+	uint32_t csi = cfg_param.csi;
+
+	/* Set SENS_DATA_FORMAT bits (8, 9 and 10)
+	   RGB or YUV444 is 0 which is current value in data so not set
+	   explicitly
+	   This is also the default value if attempts are made to set it to
+	   something invalid. */
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_YUYV:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
+		break;
+	case IPU_PIX_FMT_UYVY:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
+		break;
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_BGR24:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
+		break;
+	case IPU_PIX_FMT_GENERIC:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
+		break;
+	case IPU_PIX_FMT_RGB565:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
+		break;
+	case IPU_PIX_FMT_RGB555:
+		cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set the CSI_SENS_CONF register remaining fields */
+	data |= cfg_param.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
+		cfg_param.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
+		cfg_param.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
+		cfg_param.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
+		cfg_param.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
+		cfg_param.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
+		cfg_param.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
+		cfg_param.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
+		cfg_param.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
+		cfg_param.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
+		cfg_param.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
+
+	_ipu_get(ipu);
+
+	_ipu_lock(ipu);
+
+	ipu_csi_write(ipu, csi, data, CSI_SENS_CONF);
+
+	/* Setup sensor frame size */
+	ipu_csi_write(ipu, csi, (width - 1) | (height - 1) << 16, CSI_SENS_FRM_SIZE);
+
+	/* Set CCIR registers */
+	if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) {
+		ipu_csi_write(ipu, csi, 0x40030, CSI_CCIR_CODE_1);
+		ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
+	} else if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) {
+		if (width == 720 && height == 625) {
+			/* PAL case */
+			/*
+			 * Field0BlankEnd = 0x6, Field0BlankStart = 0x2,
+			 * Field0ActiveEnd = 0x4, Field0ActiveStart = 0
+			 */
+			ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_1);
+			/*
+			 * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,
+			 * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1
+			 */
+			ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_2);
+			ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
+		} else if (width == 720 && height == 525) {
+			/* NTSC case */
+			/*
+			 * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
+			 * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1
+			 */
+			ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_1);
+			/*
+			 * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
+			 * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
+			 */
+			ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_2);
+			ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
+		} else {
+			dev_err(ipu->dev, "Unsupported CCIR656 interlaced "
+					"video mode\n");
+			_ipu_unlock(ipu);
+			_ipu_put(ipu);
+			return -EINVAL;
+		}
+		_ipu_csi_ccir_err_detection_enable(ipu, csi);
+	} else if ((cfg_param.clk_mode ==
+			IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR) ||
+		(cfg_param.clk_mode ==
+			IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR) ||
+		(cfg_param.clk_mode ==
+			IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR) ||
+		(cfg_param.clk_mode ==
+			IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR)) {
+		ipu_csi_write(ipu, csi, 0x40030, CSI_CCIR_CODE_1);
+		ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
+		_ipu_csi_ccir_err_detection_enable(ipu, csi);
+	} else if ((cfg_param.clk_mode == IPU_CSI_CLK_MODE_GATED_CLK) ||
+		   (cfg_param.clk_mode == IPU_CSI_CLK_MODE_NONGATED_CLK)) {
+		_ipu_csi_ccir_err_detection_disable(ipu, csi);
+	}
+
+	dev_dbg(ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
+		ipu_csi_read(ipu, csi, CSI_SENS_CONF));
+	dev_dbg(ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
+		ipu_csi_read(ipu, csi, CSI_ACT_FRM_SIZE));
+
+	_ipu_unlock(ipu);
+
+	_ipu_put(ipu);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_csi_init_interface);
+
+/*!
+ * ipu_csi_get_sensor_protocol
+ *
+ * @param	ipu		ipu handler
+ * @param	csi         csi 0 or csi 1
+ *
+ * @return	Returns sensor protocol
+ */
+int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi)
+{
+	return (ipu_csi_read(ipu, csi, CSI_SENS_CONF) &
+		CSI_SENS_CONF_SENS_PRTCL_MASK) >>
+		CSI_SENS_CONF_SENS_PRTCL_SHIFT;
+}
+EXPORT_SYMBOL(ipu_csi_get_sensor_protocol);
+
+/*!
+ * _ipu_csi_mclk_set
+ *
+ * @param	ipu		ipu handler
+ * @param	pixel_clk   desired pixel clock frequency in Hz
+ * @param	csi         csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_mclk_set(struct ipu_soc *ipu, uint32_t pixel_clk, uint32_t csi)
+{
+	uint32_t temp;
+	uint32_t div_ratio;
+
+	div_ratio = (clk_get_rate(ipu->ipu_clk) / pixel_clk) - 1;
+
+	if (div_ratio > 0xFF || div_ratio < 0) {
+		dev_dbg(ipu->dev, "The value of pixel_clk extends normal range\n");
+		return -EINVAL;
+	}
+
+	temp = ipu_csi_read(ipu, csi, CSI_SENS_CONF);
+	temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
+	ipu_csi_write(ipu, csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
+			CSI_SENS_CONF);
+
+	return 0;
+}
+
+/*!
+ * ipu_csi_enable_mclk
+ *
+ * @param	ipu		ipu handler
+ * @param	csi         csi 0 or csi 1
+ * @param       flag        true to enable mclk, false to disable mclk
+ * @param       wait        true to wait 100ms make clock stable, false not wait
+ *
+ * @return      Returns 0 on success
+ */
+int ipu_csi_enable_mclk(struct ipu_soc *ipu, int csi, bool flag, bool wait)
+{
+	if (flag) {
+		clk_enable(ipu->csi_clk[csi]);
+		if (wait == true)
+			msleep(10);
+	} else {
+		clk_disable(ipu->csi_clk[csi]);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_csi_enable_mclk);
+
+/*!
+ * ipu_csi_get_window_size
+ *
+ * @param	ipu		ipu handler
+ * @param	width	pointer to window width
+ * @param	height	pointer to window height
+ * @param	csi	csi 0 or csi 1
+ */
+void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi)
+{
+	uint32_t reg;
+
+	_ipu_get(ipu);
+
+	_ipu_lock(ipu);
+
+	reg = ipu_csi_read(ipu, csi, CSI_ACT_FRM_SIZE);
+	*width = (reg & 0xFFFF) + 1;
+	*height = (reg >> 16 & 0xFFFF) + 1;
+
+	_ipu_unlock(ipu);
+
+	_ipu_put(ipu);
+}
+EXPORT_SYMBOL(ipu_csi_get_window_size);
+
+/*!
+ * ipu_csi_set_window_size
+ *
+ * @param	ipu		ipu handler
+ * @param	width	window width
+ * @param       height	window height
+ * @param       csi	csi 0 or csi 1
+ */
+void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi)
+{
+	_ipu_get(ipu);
+
+	_ipu_lock(ipu);
+
+	ipu_csi_write(ipu, csi, (width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE);
+
+	_ipu_unlock(ipu);
+
+	_ipu_put(ipu);
+}
+EXPORT_SYMBOL(ipu_csi_set_window_size);
+
+/*!
+ * ipu_csi_set_window_pos
+ *
+ * @param	ipu		ipu handler
+ * @param       left	uint32 window x start
+ * @param       top	uint32 window y start
+ * @param       csi	csi 0 or csi 1
+ */
+void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi)
+{
+	uint32_t temp;
+
+	_ipu_get(ipu);
+
+	_ipu_lock(ipu);
+
+	temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
+	temp &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
+	temp |= ((top << CSI_VSC_SHIFT) | (left << CSI_HSC_SHIFT));
+	ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
+
+	_ipu_unlock(ipu);
+
+	_ipu_put(ipu);
+}
+EXPORT_SYMBOL(ipu_csi_set_window_pos);
+
+/*!
+ * _ipu_csi_horizontal_downsize_enable
+ *	Enable horizontal downsizing(decimation) by 2.
+ *
+ * @param	ipu		ipu handler
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_horizontal_downsize_enable(struct ipu_soc *ipu, uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
+	temp |= CSI_HORI_DOWNSIZE_EN;
+	ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
+}
+
+/*!
+ * _ipu_csi_horizontal_downsize_disable
+ *	Disable horizontal downsizing(decimation) by 2.
+ *
+ * @param	ipu		ipu handler
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_horizontal_downsize_disable(struct ipu_soc *ipu, uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
+	temp &= ~CSI_HORI_DOWNSIZE_EN;
+	ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
+}
+
+/*!
+ * _ipu_csi_vertical_downsize_enable
+ *	Enable vertical downsizing(decimation) by 2.
+ *
+ * @param	ipu		ipu handler
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_vertical_downsize_enable(struct ipu_soc *ipu, uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
+	temp |= CSI_VERT_DOWNSIZE_EN;
+	ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
+}
+
+/*!
+ * _ipu_csi_vertical_downsize_disable
+ *	Disable vertical downsizing(decimation) by 2.
+ *
+ * @param	ipu		ipu handler
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_vertical_downsize_disable(struct ipu_soc *ipu, uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
+	temp &= ~CSI_VERT_DOWNSIZE_EN;
+	ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
+}
+
+/*!
+ * _ipu_csi_set_test_generator
+ *
+ * @param	ipu		ipu handler
+ * @param	active       1 for active and 0 for inactive
+ * @param       r_value	     red value for the generated pattern of even pixel
+ * @param       g_value      green value for the generated pattern of even
+ *			     pixel
+ * @param       b_value      blue value for the generated pattern of even pixel
+ * @param	pixel_clk   desired pixel clock frequency in Hz
+ * @param       csi          csi 0 or csi 1
+ */
+void _ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
+	uint32_t g_value, uint32_t b_value, uint32_t pix_clk, uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = ipu_csi_read(ipu, csi, CSI_TST_CTRL);
+
+	if (active == false) {
+		temp &= ~CSI_TEST_GEN_MODE_EN;
+		ipu_csi_write(ipu, csi, temp, CSI_TST_CTRL);
+	} else {
+		/* Set sensb_mclk div_ratio*/
+		_ipu_csi_mclk_set(ipu, pix_clk, csi);
+
+		temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
+			CSI_TEST_GEN_B_MASK);
+		temp |= CSI_TEST_GEN_MODE_EN;
+		temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
+			(g_value << CSI_TEST_GEN_G_SHIFT) |
+			(b_value << CSI_TEST_GEN_B_SHIFT);
+		ipu_csi_write(ipu, csi, temp, CSI_TST_CTRL);
+	}
+}
+
+/*!
+ * _ipu_csi_ccir_err_detection_en
+ *	Enable error detection and correction for
+ *	CCIR interlaced mode with protection bit.
+ *
+ * @param	ipu		ipu handler
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_ccir_err_detection_enable(struct ipu_soc *ipu, uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = ipu_csi_read(ipu, csi, CSI_CCIR_CODE_1);
+	temp |= CSI_CCIR_ERR_DET_EN;
+	ipu_csi_write(ipu, csi, temp, CSI_CCIR_CODE_1);
+
+}
+
+/*!
+ * _ipu_csi_ccir_err_detection_disable
+ *	Disable error detection and correction for
+ *	CCIR interlaced mode with protection bit.
+ *
+ * @param	ipu		ipu handler
+ * @param	csi	csi 0 or csi 1
+ */
+void _ipu_csi_ccir_err_detection_disable(struct ipu_soc *ipu, uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = ipu_csi_read(ipu, csi, CSI_CCIR_CODE_1);
+	temp &= ~CSI_CCIR_ERR_DET_EN;
+	ipu_csi_write(ipu, csi, temp, CSI_CCIR_CODE_1);
+
+}
+
+/*!
+ * _ipu_csi_set_mipi_di
+ *
+ * @param	ipu		ipu handler
+ * @param	num	MIPI data identifier 0-3 handled by CSI
+ * @param	di_val	data identifier value
+ * @param	csi	csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_set_mipi_di(struct ipu_soc *ipu, uint32_t num, uint32_t di_val, uint32_t csi)
+{
+	uint32_t temp;
+	int retval = 0;
+
+	if (di_val > 0xFFL) {
+		retval = -EINVAL;
+		goto err;
+	}
+
+	temp = ipu_csi_read(ipu, csi, CSI_MIPI_DI);
+
+	switch (num) {
+	case IPU_CSI_MIPI_DI0:
+		temp &= ~CSI_MIPI_DI0_MASK;
+		temp |= (di_val << CSI_MIPI_DI0_SHIFT);
+		ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
+		break;
+	case IPU_CSI_MIPI_DI1:
+		temp &= ~CSI_MIPI_DI1_MASK;
+		temp |= (di_val << CSI_MIPI_DI1_SHIFT);
+		ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
+		break;
+	case IPU_CSI_MIPI_DI2:
+		temp &= ~CSI_MIPI_DI2_MASK;
+		temp |= (di_val << CSI_MIPI_DI2_SHIFT);
+		ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
+		break;
+	case IPU_CSI_MIPI_DI3:
+		temp &= ~CSI_MIPI_DI3_MASK;
+		temp |= (di_val << CSI_MIPI_DI3_SHIFT);
+		ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
+		break;
+	default:
+		retval = -EINVAL;
+	}
+
+err:
+	return retval;
+}
+
+/*!
+ * _ipu_csi_set_skip_isp
+ *
+ * @param	ipu		ipu handler
+ * @param	skip		select frames to be skipped and set the
+ *				correspond bits to 1
+ * @param	max_ratio	number of frames in a skipping set and the
+ * 				maximum value of max_ratio is 5
+ * @param	csi		csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_set_skip_isp(struct ipu_soc *ipu, uint32_t skip, uint32_t max_ratio, uint32_t csi)
+{
+	uint32_t temp;
+	int retval = 0;
+
+	if (max_ratio > 5) {
+		retval = -EINVAL;
+		goto err;
+	}
+
+	temp = ipu_csi_read(ipu, csi, CSI_SKIP);
+	temp &= ~(CSI_MAX_RATIO_SKIP_ISP_MASK | CSI_SKIP_ISP_MASK);
+	temp |= (max_ratio << CSI_MAX_RATIO_SKIP_ISP_SHIFT) |
+		(skip << CSI_SKIP_ISP_SHIFT);
+	ipu_csi_write(ipu, csi, temp, CSI_SKIP);
+
+err:
+	return retval;
+}
+
+/*!
+ * _ipu_csi_set_skip_smfc
+ *
+ * @param	ipu		ipu handler
+ * @param	skip		select frames to be skipped and set the
+ *				correspond bits to 1
+ * @param	max_ratio	number of frames in a skipping set and the
+ *				maximum value of max_ratio is 5
+ * @param	id		csi to smfc skipping id
+ * @param	csi		csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_set_skip_smfc(struct ipu_soc *ipu, uint32_t skip,
+	uint32_t max_ratio, uint32_t id, uint32_t csi)
+{
+	uint32_t temp;
+	int retval = 0;
+
+	if (max_ratio > 5 || id > 3) {
+		retval = -EINVAL;
+		goto err;
+	}
+
+	temp = ipu_csi_read(ipu, csi, CSI_SKIP);
+	temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
+			CSI_SKIP_SMFC_MASK);
+	temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
+			(id << CSI_ID_2_SKIP_SHIFT) |
+			(skip << CSI_SKIP_SMFC_SHIFT);
+	ipu_csi_write(ipu, csi, temp, CSI_SKIP);
+
+err:
+	return retval;
+}
+
+/*!
+ * _ipu_smfc_init
+ *	Map CSI frames to IDMAC channels.
+ *
+ * @param	ipu		ipu handler
+ * @param	channel		IDMAC channel 0-3
+ * @param	mipi_id		mipi id number 0-3
+ * @param	csi		csi0 or csi1
+ */
+void _ipu_smfc_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t mipi_id, uint32_t csi)
+{
+	uint32_t temp;
+
+	temp = ipu_smfc_read(ipu, SMFC_MAP);
+
+	switch (channel) {
+	case CSI_MEM0:
+		temp &= ~SMFC_MAP_CH0_MASK;
+		temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH0_SHIFT;
+		break;
+	case CSI_MEM1:
+		temp &= ~SMFC_MAP_CH1_MASK;
+		temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH1_SHIFT;
+		break;
+	case CSI_MEM2:
+		temp &= ~SMFC_MAP_CH2_MASK;
+		temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH2_SHIFT;
+		break;
+	case CSI_MEM3:
+		temp &= ~SMFC_MAP_CH3_MASK;
+		temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH3_SHIFT;
+		break;
+	default:
+		return;
+	}
+
+	ipu_smfc_write(ipu, temp, SMFC_MAP);
+}
+
+/*!
+ * _ipu_smfc_set_wmc
+ *	Caution: The number of required channels,  the enabled channels
+ *	and the FIFO size per channel are configured restrictedly.
+ *
+ * @param	ipu		ipu handler
+ * @param	channel		IDMAC channel 0-3
+ * @param	set		set 1 or clear 0
+ * @param	level		water mark level when FIFO is on the
+ *				relative size
+ */
+void _ipu_smfc_set_wmc(struct ipu_soc *ipu, ipu_channel_t channel, bool set, uint32_t level)
+{
+	uint32_t temp;
+
+	temp = ipu_smfc_read(ipu, SMFC_WMC);
+
+	switch (channel) {
+	case CSI_MEM0:
+		if (set == true) {
+			temp &= ~SMFC_WM0_SET_MASK;
+			temp |= level << SMFC_WM0_SET_SHIFT;
+		} else {
+			temp &= ~SMFC_WM0_CLR_MASK;
+			temp |= level << SMFC_WM0_CLR_SHIFT;
+		}
+		break;
+	case CSI_MEM1:
+		if (set == true) {
+			temp &= ~SMFC_WM1_SET_MASK;
+			temp |= level << SMFC_WM1_SET_SHIFT;
+		} else {
+			temp &= ~SMFC_WM1_CLR_MASK;
+			temp |= level << SMFC_WM1_CLR_SHIFT;
+		}
+		break;
+	case CSI_MEM2:
+		if (set == true) {
+			temp &= ~SMFC_WM2_SET_MASK;
+			temp |= level << SMFC_WM2_SET_SHIFT;
+		} else {
+			temp &= ~SMFC_WM2_CLR_MASK;
+			temp |= level << SMFC_WM2_CLR_SHIFT;
+		}
+		break;
+	case CSI_MEM3:
+		if (set == true) {
+			temp &= ~SMFC_WM3_SET_MASK;
+			temp |= level << SMFC_WM3_SET_SHIFT;
+		} else {
+			temp &= ~SMFC_WM3_CLR_MASK;
+			temp |= level << SMFC_WM3_CLR_SHIFT;
+		}
+		break;
+	default:
+		return;
+	}
+
+	ipu_smfc_write(ipu, temp, SMFC_WMC);
+}
+
+/*!
+ * _ipu_smfc_set_burst_size
+ *
+ * @param	ipu		ipu handler
+ * @param	channel		IDMAC channel 0-3
+ * @param	bs		burst size of IDMAC channel,
+ *				the value programmed here shoud be BURST_SIZE-1
+ */
+void _ipu_smfc_set_burst_size(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t bs)
+{
+	uint32_t temp;
+
+	temp = ipu_smfc_read(ipu, SMFC_BS);
+
+	switch (channel) {
+	case CSI_MEM0:
+		temp &= ~SMFC_BS0_MASK;
+		temp |= bs << SMFC_BS0_SHIFT;
+		break;
+	case CSI_MEM1:
+		temp &= ~SMFC_BS1_MASK;
+		temp |= bs << SMFC_BS1_SHIFT;
+		break;
+	case CSI_MEM2:
+		temp &= ~SMFC_BS2_MASK;
+		temp |= bs << SMFC_BS2_SHIFT;
+		break;
+	case CSI_MEM3:
+		temp &= ~SMFC_BS3_MASK;
+		temp |= bs << SMFC_BS3_SHIFT;
+		break;
+	default:
+		return;
+	}
+
+	ipu_smfc_write(ipu, temp, SMFC_BS);
+}
+
+/*!
+ * _ipu_csi_init
+ *
+ * @param	ipu		ipu handler
+ * @param	channel      IDMAC channel
+ * @param	csi	     csi 0 or csi 1
+ *
+ * @return	Returns 0 on success or negative error code on fail
+ */
+int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi)
+{
+	uint32_t csi_sens_conf, csi_dest;
+	int retval = 0;
+
+	switch (channel) {
+	case CSI_MEM0:
+	case CSI_MEM1:
+	case CSI_MEM2:
+	case CSI_MEM3:
+		csi_dest = CSI_DATA_DEST_IDMAC;
+		break;
+	case CSI_PRP_ENC_MEM:
+	case CSI_PRP_VF_MEM:
+		csi_dest = CSI_DATA_DEST_IC;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	csi_sens_conf = ipu_csi_read(ipu, csi, CSI_SENS_CONF);
+	csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
+	ipu_csi_write(ipu, csi, csi_sens_conf | (csi_dest <<
+		CSI_SENS_CONF_DATA_DEST_SHIFT), CSI_SENS_CONF);
+err:
+	return retval;
+}
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
new file mode 100644
index 00000000000..014125921c8
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -0,0 +1,2958 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_common.c
+ *
+ * @brief This file contains the IPU driver common API functions.
+ *
+ * @ingroup IPU
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
+#include <linux/clk.h>
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/ipu-v3.h>
+#include <mach/devices-common.h>
+#include <asm/cacheflush.h>
+#include <linux/delay.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+static struct ipu_soc ipu_array[MXC_IPU_MAX_NUM];
+int g_ipu_hw_rev;
+
+/* Static functions */
+static irqreturn_t ipu_irq_handler(int irq, void *desc);
+
+static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
+{
+	return ((uint32_t) ch >> (6 * type)) & 0x3F;
+};
+
+static inline int _ipu_is_ic_chan(uint32_t dma_chan)
+{
+	return ((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) && (dma_chan != 18));
+}
+
+static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan)
+{
+	return (dma_chan == 14 || dma_chan == 15);
+}
+
+/* Either DP BG or DP FG can be graphic window */
+static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan)
+{
+	return (dma_chan == 23 || dma_chan == 27);
+}
+
+static inline int _ipu_is_irt_chan(uint32_t dma_chan)
+{
+	return ((dma_chan >= 45) && (dma_chan <= 50));
+}
+
+static inline int _ipu_is_dmfc_chan(uint32_t dma_chan)
+{
+	return ((dma_chan >= 23) && (dma_chan <= 29));
+}
+
+static inline int _ipu_is_smfc_chan(uint32_t dma_chan)
+{
+	return ((dma_chan >= 0) && (dma_chan <= 3));
+}
+
+static inline int _ipu_is_trb_chan(uint32_t dma_chan)
+{
+	return (((dma_chan == 8) || (dma_chan == 9) ||
+		 (dma_chan == 10) || (dma_chan == 13) ||
+		 (dma_chan == 21) || (dma_chan == 23) ||
+		 (dma_chan == 27) || (dma_chan == 28)) &&
+		(g_ipu_hw_rev >= 2));
+}
+
+#define idma_is_valid(ch)	(ch != NO_DMA)
+#define idma_mask(ch)		(idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
+#define idma_is_set(ipu, reg, dma)	(ipu_idmac_read(ipu, reg(dma)) & idma_mask(dma))
+#define tri_cur_buf_mask(ch)	(idma_mask(ch*2) * 3)
+#define tri_cur_buf_shift(ch)	(ffs(idma_mask(ch*2)) - 1)
+
+static int ipu_reset(struct ipu_soc *ipu)
+{
+	int timeout = 1000;
+
+	ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
+
+	while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
+		if (!timeout--)
+			return -ETIME;
+		msleep(1);
+	}
+
+	return 0;
+}
+
+static int __devinit ipu_clk_setup_enable(struct ipu_soc *ipu,
+		struct platform_device *pdev)
+{
+	struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
+	char ipu_clk[] = "ipu1_clk";
+	char di0_clk[] = "ipu1_di0_clk";
+	char di1_clk[] = "ipu1_di1_clk";
+
+	ipu_clk[3] += pdev->id;
+	di0_clk[3] += pdev->id;
+	di1_clk[3] += pdev->id;
+
+	ipu->ipu_clk = clk_get(ipu->dev, ipu_clk);
+	if (IS_ERR(ipu->ipu_clk)) {
+		dev_err(ipu->dev, "clk_get failed");
+		return PTR_ERR(ipu->ipu_clk);
+	}
+	dev_dbg(ipu->dev, "ipu_clk = %lu\n", clk_get_rate(ipu->ipu_clk));
+
+	ipu->pixel_clk[0] = ipu_pixel_clk[0];
+	ipu->pixel_clk[1] = ipu_pixel_clk[1];
+
+	ipu_lookups[pdev->id][0].clk = &ipu->pixel_clk[0];
+	ipu_lookups[pdev->id][1].clk = &ipu->pixel_clk[1];
+	ipu_lookups[pdev->id][0].dev_id = dev_name(ipu->dev);
+	ipu_lookups[pdev->id][1].dev_id = dev_name(ipu->dev);
+	clkdev_add(&ipu_lookups[pdev->id][0]);
+	clkdev_add(&ipu_lookups[pdev->id][1]);
+
+	clk_debug_register(&ipu->pixel_clk[0]);
+	clk_debug_register(&ipu->pixel_clk[1]);
+
+	clk_enable(ipu->ipu_clk);
+
+	clk_set_parent(&ipu->pixel_clk[0], ipu->ipu_clk);
+	clk_set_parent(&ipu->pixel_clk[1], ipu->ipu_clk);
+
+	ipu->di_clk[0] = clk_get(ipu->dev, di0_clk);
+	ipu->di_clk[1] = clk_get(ipu->dev, di1_clk);
+
+	ipu->csi_clk[0] = clk_get(ipu->dev, plat_data->csi_clk[0]);
+	ipu->csi_clk[1] = clk_get(ipu->dev, plat_data->csi_clk[1]);
+
+	return 0;
+}
+
+#if 0
+static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
+	const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
+	u32 status;
+	int i, line;
+
+	for (i = 0;; i++) {
+		if (int_reg[i] == 0)
+			break;
+
+		status = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
+		status &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
+
+		while ((line = ffs(status))) {
+			line--;
+			status &= ~(1UL << line);
+			line += ipu->irq_start + (int_reg[i] - 1) * 32;
+			generic_handle_irq(line);
+		}
+
+	}
+}
+
+static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
+	const int int_reg[] = { 5, 6, 9, 10, 0 };
+	u32 status;
+	int i, line;
+
+	for (i = 0;; i++) {
+		if (int_reg[i] == 0)
+			break;
+
+		status = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
+		status &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
+
+		while ((line = ffs(status))) {
+			line--;
+			status &= ~(1UL << line);
+			line += ipu->irq_start + (int_reg[i] - 1) * 32;
+			generic_handle_irq(line);
+		}
+
+	}
+}
+
+static void ipu_ack_irq(struct irq_data *d)
+{
+	struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
+	unsigned int irq = d->irq - ipu->irq_start;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ipu->ipu_lock, flags);
+	ipu_cm_write(ipu, 1 << (irq % 32), IPU_INT_STAT(irq / 32 + 1));
+	spin_unlock_irqrestore(&ipu->ipu_lock, flags);
+}
+
+static void ipu_unmask_irq(struct irq_data *d)
+{
+	struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
+	unsigned int irq = d->irq - ipu->irq_start;
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&ipu->ipu_lock, flags);
+	reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32 + 1));
+	reg |= 1 << (irq % 32);
+	ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32 + 1));
+	spin_unlock_irqrestore(&ipu->ipu_lock, flags);
+}
+
+static void ipu_mask_irq(struct irq_data *d)
+{
+	struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
+	unsigned int irq = d->irq - ipu->irq_start;
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&ipu->ipu_lock, flags);
+	reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32 + 1));
+	reg &= ~(1 << (irq % 32));
+	ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32 + 1));
+	spin_unlock_irqrestore(&ipu->ipu_lock, flags);
+}
+
+static struct irq_chip ipu_irq_chip = {
+	.name = "IPU",
+	.irq_ack = ipu_ack_irq,
+	.irq_mask = ipu_mask_irq,
+	.irq_unmask = ipu_unmask_irq,
+};
+
+static void __devinit ipu_irq_setup(struct ipu_soc *ipu)
+{
+	int i;
+
+	for (i = ipu->irq_start; i < ipu->irq_start + MX5_IPU_IRQS; i++) {
+		irq_set_chip_and_handler(i, &ipu_irq_chip, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+		irq_set_chip_data(i, ipu);
+	}
+
+	irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
+	irq_set_handler_data(ipu->irq_sync, ipu);
+	irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
+	irq_set_handler_data(ipu->irq_err, ipu);
+}
+
+int ipu_request_irq(struct ipu_soc *ipu, unsigned int irq,
+		irq_handler_t handler, unsigned long flags,
+		const char *name, void *dev)
+{
+	return request_irq(ipu->irq_start + irq, handler, flags, name, dev);
+}
+EXPORT_SYMBOL_GPL(ipu_request_irq);
+
+void ipu_enable_irq(struct ipu_soc *ipu, unsigned int irq)
+{
+	return enable_irq(ipu->irq_start + irq);
+}
+EXPORT_SYMBOL_GPL(ipu_disable_irq);
+
+void ipu_disable_irq(struct ipu_soc *ipu, unsigned int irq)
+{
+	return disable_irq(ipu->irq_start + irq);
+}
+EXPORT_SYMBOL_GPL(ipu_disable_irq);
+
+void ipu_free_irq(struct ipu_soc *ipu, unsigned int irq, void *dev_id)
+{
+	free_irq(ipu->irq_start + irq, dev_id);
+}
+EXPORT_SYMBOL_GPL(ipu_free_irq);
+
+static irqreturn_t ipu_completion_handler(int irq, void *dev)
+{
+	struct completion *completion = dev;
+
+	complete(completion);
+	return IRQ_HANDLED;
+}
+
+int ipu_wait_for_interrupt(struct ipu_soc *ipu, int interrupt, int timeout_ms)
+{
+	DECLARE_COMPLETION_ONSTACK(completion);
+	int ret;
+
+	ret = ipu_request_irq(ipu, interrupt, ipu_completion_handler,
+			0, NULL, &completion);
+	if (ret) {
+		dev_err(ipu->dev,
+			"ipu request irq %d fail\n", interrupt);
+		return ret;
+	}
+
+	ret = wait_for_completion_timeout(&completion,
+			msecs_to_jiffies(timeout_ms));
+
+	ipu_free_irq(ipu, interrupt, &completion);
+
+	return ret > 0 ? 0 : -ETIMEDOUT;
+}
+EXPORT_SYMBOL_GPL(ipu_wait_for_interrupt);
+#endif
+
+struct ipu_soc *ipu_get_soc(int id)
+{
+	if (id >= MXC_IPU_MAX_NUM)
+		return ERR_PTR(-ENODEV);
+	else if (!ipu_array[id].online)
+		return ERR_PTR(-ENODEV);
+	else
+		return &(ipu_array[id]);
+}
+EXPORT_SYMBOL_GPL(ipu_get_soc);
+
+void _ipu_lock(struct ipu_soc *ipu)
+{
+	/*TODO:remove in_irq() condition after v4l2 driver rewrite*/
+	if (!in_irq() && !in_softirq())
+		mutex_lock(&ipu->mutex_lock);
+}
+
+void _ipu_unlock(struct ipu_soc *ipu)
+{
+	/*TODO:remove in_irq() condition after v4l2 driver rewrite*/
+	if (!in_irq() && !in_softirq())
+		mutex_unlock(&ipu->mutex_lock);
+}
+
+void _ipu_get(struct ipu_soc *ipu)
+{
+	if (atomic_inc_return(&ipu->ipu_use_count) == 1)
+		clk_enable(ipu->ipu_clk);
+}
+
+void _ipu_put(struct ipu_soc *ipu)
+{
+	if (atomic_dec_return(&ipu->ipu_use_count) == 0)
+		clk_disable(ipu->ipu_clk);
+}
+
+/*!
+ * This function is called by the driver framework to initialize the IPU
+ * hardware.
+ *
+ * @param	dev	The device structure for the IPU passed in by the
+ *			driver framework.
+ *
+ * @return      Returns 0 on success or negative error code on error
+ */
+static int __devinit ipu_probe(struct platform_device *pdev)
+{
+	struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
+	struct ipu_soc *ipu;
+	struct resource *res;
+	unsigned long ipu_base;
+	int ret = 0;
+
+	if (pdev->id >= MXC_IPU_MAX_NUM)
+		return -ENODEV;
+
+	ipu = &ipu_array[pdev->id];
+	memset(ipu, 0, sizeof(struct ipu_soc));
+
+	spin_lock_init(&ipu->spin_lock);
+	mutex_init(&ipu->mutex_lock);
+	atomic_set(&ipu->ipu_use_count, 0);
+
+	g_ipu_hw_rev = plat_data->rev;
+
+	ipu->dev = &pdev->dev;
+
+	if (plat_data->init)
+		plat_data->init(pdev->id);
+
+	ipu->irq_sync = platform_get_irq(pdev, 0);
+	ipu->irq_err = platform_get_irq(pdev, 1);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (!res || ipu->irq_sync < 0 || ipu->irq_err < 0) {
+		ret = -ENODEV;
+		goto failed_get_res;
+	}
+
+	if (request_irq(ipu->irq_sync, ipu_irq_handler, 0, pdev->name, ipu) != 0) {
+		dev_err(ipu->dev, "request SYNC interrupt failed\n");
+		ret = -EBUSY;
+		goto failed_req_irq_sync;
+	}
+	/* Some platforms have 2 IPU interrupts */
+	if (ipu->irq_err >= 0) {
+		if (request_irq
+		    (ipu->irq_err, ipu_irq_handler, 0, pdev->name, ipu) != 0) {
+			dev_err(ipu->dev, "request ERR interrupt failed\n");
+			ret = -EBUSY;
+			goto failed_req_irq_err;
+		}
+	}
+
+	ipu_base = res->start;
+	/* base fixup */
+	if (g_ipu_hw_rev == 4)	/* IPUv3H */
+		ipu_base += IPUV3H_REG_BASE;
+	else if (g_ipu_hw_rev == 3)	/* IPUv3M */
+		ipu_base += IPUV3M_REG_BASE;
+	else			/* IPUv3D, v3E, v3EX */
+		ipu_base += IPUV3DEX_REG_BASE;
+
+	ipu->cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
+	ipu->ic_reg = ioremap(ipu_base + IPU_IC_REG_BASE, PAGE_SIZE);
+	ipu->idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
+	/* DP Registers are accessed thru the SRM */
+	ipu->dp_reg = ioremap(ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE);
+	ipu->dc_reg = ioremap(ipu_base + IPU_DC_REG_BASE, PAGE_SIZE);
+	ipu->dmfc_reg = ioremap(ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE);
+	ipu->di_reg[0] = ioremap(ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE);
+	ipu->di_reg[1] = ioremap(ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE);
+	ipu->smfc_reg = ioremap(ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE);
+	ipu->csi_reg[0] = ioremap(ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE);
+	ipu->csi_reg[1] = ioremap(ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE);
+	ipu->cpmem_base = ioremap(ipu_base + IPU_CPMEM_REG_BASE, SZ_128K);
+	ipu->tpmem_base = ioremap(ipu_base + IPU_TPM_REG_BASE, SZ_64K);
+	ipu->dc_tmpl_reg = ioremap(ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
+	ipu->vdi_reg = ioremap(ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
+	ipu->disp_base[1] = ioremap(ipu_base + IPU_DISP1_BASE, SZ_4K);
+
+	if (!ipu->cm_reg || !ipu->ic_reg || !ipu->idmac_reg ||
+		!ipu->dp_reg || !ipu->dc_reg || !ipu->dmfc_reg ||
+		!ipu->di_reg[0] || !ipu->di_reg[1] || !ipu->smfc_reg ||
+		!ipu->csi_reg[0] || !ipu->csi_reg[1] || !ipu->cpmem_base ||
+		!ipu->tpmem_base || !ipu->dc_tmpl_reg || !ipu->disp_base[1]
+		|| !ipu->vdi_reg) {
+		ret = -ENOMEM;
+		goto failed_ioremap;
+	}
+
+	dev_dbg(ipu->dev, "IPU CM Regs = %p\n", ipu->cm_reg);
+	dev_dbg(ipu->dev, "IPU IC Regs = %p\n", ipu->ic_reg);
+	dev_dbg(ipu->dev, "IPU IDMAC Regs = %p\n", ipu->idmac_reg);
+	dev_dbg(ipu->dev, "IPU DP Regs = %p\n", ipu->dp_reg);
+	dev_dbg(ipu->dev, "IPU DC Regs = %p\n", ipu->dc_reg);
+	dev_dbg(ipu->dev, "IPU DMFC Regs = %p\n", ipu->dmfc_reg);
+	dev_dbg(ipu->dev, "IPU DI0 Regs = %p\n", ipu->di_reg[0]);
+	dev_dbg(ipu->dev, "IPU DI1 Regs = %p\n", ipu->di_reg[1]);
+	dev_dbg(ipu->dev, "IPU SMFC Regs = %p\n", ipu->smfc_reg);
+	dev_dbg(ipu->dev, "IPU CSI0 Regs = %p\n", ipu->csi_reg[0]);
+	dev_dbg(ipu->dev, "IPU CSI1 Regs = %p\n", ipu->csi_reg[1]);
+	dev_dbg(ipu->dev, "IPU CPMem = %p\n", ipu->cpmem_base);
+	dev_dbg(ipu->dev, "IPU TPMem = %p\n", ipu->tpmem_base);
+	dev_dbg(ipu->dev, "IPU DC Template Mem = %p\n", ipu->dc_tmpl_reg);
+	dev_dbg(ipu->dev, "IPU Display Region 1 Mem = %p\n", ipu->disp_base[1]);
+	dev_dbg(ipu->dev, "IPU VDI Regs = %p\n", ipu->vdi_reg);
+
+	ret = ipu_clk_setup_enable(ipu, pdev);
+	if (ret < 0) {
+		dev_err(ipu->dev, "ipu clk setup failed\n");
+		goto failed_clk_setup;
+	}
+
+	platform_set_drvdata(pdev, ipu);
+
+	ipu_reset(ipu);
+
+	ipu_disp_init(ipu);
+
+	/* Set sync refresh channels and CSI->mem channel as high priority */
+	ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
+
+	/* Set MCU_T to divide MCU access window into 2 */
+	ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
+
+	clk_disable(ipu->ipu_clk);
+
+	register_ipu_device(ipu, pdev->id);
+
+	ipu->online = true;
+
+	return ret;
+
+failed_clk_setup:
+	iounmap(ipu->cm_reg);
+	iounmap(ipu->ic_reg);
+	iounmap(ipu->idmac_reg);
+	iounmap(ipu->dc_reg);
+	iounmap(ipu->dp_reg);
+	iounmap(ipu->dmfc_reg);
+	iounmap(ipu->di_reg[0]);
+	iounmap(ipu->di_reg[1]);
+	iounmap(ipu->smfc_reg);
+	iounmap(ipu->csi_reg[0]);
+	iounmap(ipu->csi_reg[1]);
+	iounmap(ipu->cpmem_base);
+	iounmap(ipu->tpmem_base);
+	iounmap(ipu->dc_tmpl_reg);
+	iounmap(ipu->disp_base[1]);
+	iounmap(ipu->vdi_reg);
+failed_ioremap:
+	if (ipu->irq_sync)
+		free_irq(ipu->irq_err, ipu);
+failed_req_irq_err:
+	free_irq(ipu->irq_sync, ipu);
+failed_req_irq_sync:
+failed_get_res:
+	return ret;
+}
+
+int __devexit ipu_remove(struct platform_device *pdev)
+{
+	struct ipu_soc *ipu = platform_get_drvdata(pdev);
+
+	unregister_ipu_device(ipu, pdev->id);
+
+	if (ipu->irq_sync)
+		free_irq(ipu->irq_sync, ipu);
+	if (ipu->irq_err)
+		free_irq(ipu->irq_err, ipu);
+
+	clk_put(ipu->ipu_clk);
+
+	iounmap(ipu->cm_reg);
+	iounmap(ipu->ic_reg);
+	iounmap(ipu->idmac_reg);
+	iounmap(ipu->dc_reg);
+	iounmap(ipu->dp_reg);
+	iounmap(ipu->dmfc_reg);
+	iounmap(ipu->di_reg[0]);
+	iounmap(ipu->di_reg[1]);
+	iounmap(ipu->smfc_reg);
+	iounmap(ipu->csi_reg[0]);
+	iounmap(ipu->csi_reg[1]);
+	iounmap(ipu->cpmem_base);
+	iounmap(ipu->tpmem_base);
+	iounmap(ipu->dc_tmpl_reg);
+	iounmap(ipu->disp_base[1]);
+	iounmap(ipu->vdi_reg);
+
+	return 0;
+}
+
+void ipu_dump_registers(struct ipu_soc *ipu)
+{
+	dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", ipu_cm_read(ipu, IPU_CONF));
+	dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", ipu_idmac_read(ipu, IDMAC_CONF));
+	dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
+	       ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
+	dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
+	       ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
+	dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
+	       ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
+	dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
+	       ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
+	dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
+	       ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
+	dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
+	       ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
+	dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
+	       ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
+	dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
+	       ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
+	if (g_ipu_hw_rev >= 2) {
+		dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL0 = \t0x%08X\n",
+		       ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(0)));
+		dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL1 = \t0x%08X\n",
+		       ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(32)));
+	}
+	dev_dbg(ipu->dev, "DMFC_WR_CHAN = \t0x%08X\n",
+	       ipu_dmfc_read(ipu, DMFC_WR_CHAN));
+	dev_dbg(ipu->dev, "DMFC_WR_CHAN_DEF = \t0x%08X\n",
+	       ipu_dmfc_read(ipu, DMFC_WR_CHAN_DEF));
+	dev_dbg(ipu->dev, "DMFC_DP_CHAN = \t0x%08X\n",
+	       ipu_dmfc_read(ipu, DMFC_DP_CHAN));
+	dev_dbg(ipu->dev, "DMFC_DP_CHAN_DEF = \t0x%08X\n",
+	       ipu_dmfc_read(ipu, DMFC_DP_CHAN_DEF));
+	dev_dbg(ipu->dev, "DMFC_IC_CTRL = \t0x%08X\n",
+	       ipu_dmfc_read(ipu, DMFC_IC_CTRL));
+	dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
+	       ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
+	dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
+	       ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
+	dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
+	       ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
+	dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
+	       ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
+}
+
+/*!
+ * This function is called to initialize a logical IPU channel.
+ *
+ * @param	ipu	ipu handler
+ * @param       channel Input parameter for the logical channel ID to init.
+ *
+ * @param       params  Input parameter containing union of channel
+ *                      initialization parameters.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
+{
+	int ret = 0;
+	uint32_t ipu_conf;
+	uint32_t reg;
+
+	dev_dbg(ipu->dev, "init channel = %d\n", IPU_CHAN_ID(channel));
+
+	_ipu_get(ipu);
+
+	_ipu_lock(ipu);
+
+	if (ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
+		dev_warn(ipu->dev, "Warning: channel already initialized %d\n",
+			IPU_CHAN_ID(channel));
+	}
+
+	ipu_conf = ipu_cm_read(ipu, IPU_CONF);
+
+	switch (channel) {
+	case CSI_MEM0:
+	case CSI_MEM1:
+	case CSI_MEM2:
+	case CSI_MEM3:
+		if (params->csi_mem.csi > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		if (params->csi_mem.interlaced)
+			ipu->chan_is_interlaced[channel_2_dma(channel,
+				IPU_OUTPUT_BUFFER)] = true;
+		else
+			ipu->chan_is_interlaced[channel_2_dma(channel,
+				IPU_OUTPUT_BUFFER)] = false;
+
+		ipu->smfc_use_count++;
+		ipu->csi_channel[params->csi_mem.csi] = channel;
+
+		/*SMFC setting*/
+		if (params->csi_mem.mipi_en) {
+			ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
+				params->csi_mem.csi));
+			_ipu_smfc_init(ipu, channel, params->csi_mem.mipi_id,
+				params->csi_mem.csi);
+		} else {
+			ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
+				params->csi_mem.csi));
+			_ipu_smfc_init(ipu, channel, 0, params->csi_mem.csi);
+		}
+
+		/*CSI data (include compander) dest*/
+		_ipu_csi_init(ipu, channel, params->csi_mem.csi);
+		break;
+	case CSI_PRP_ENC_MEM:
+		if (params->csi_prp_enc_mem.csi > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+		if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
+			ret = -EINVAL;
+			goto err;
+		}
+		ipu->using_ic_dirct_ch = CSI_PRP_ENC_MEM;
+
+		ipu->ic_use_count++;
+		ipu->csi_channel[params->csi_prp_enc_mem.csi] = channel;
+
+		/*Without SMFC, CSI only support parallel data source*/
+		ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
+			params->csi_prp_enc_mem.csi));
+
+		/*CSI0/1 feed into IC*/
+		ipu_conf &= ~IPU_CONF_IC_INPUT;
+		if (params->csi_prp_enc_mem.csi)
+			ipu_conf |= IPU_CONF_CSI_SEL;
+		else
+			ipu_conf &= ~IPU_CONF_CSI_SEL;
+
+		/*PRP skip buffer in memory, only valid when RWS_EN is true*/
+		reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+		ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
+
+		/*CSI data (include compander) dest*/
+		_ipu_csi_init(ipu, channel, params->csi_prp_enc_mem.csi);
+		_ipu_ic_init_prpenc(ipu, params, true);
+		break;
+	case CSI_PRP_VF_MEM:
+		if (params->csi_prp_vf_mem.csi > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+		if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
+			ret = -EINVAL;
+			goto err;
+		}
+		ipu->using_ic_dirct_ch = CSI_PRP_VF_MEM;
+
+		ipu->ic_use_count++;
+		ipu->csi_channel[params->csi_prp_vf_mem.csi] = channel;
+
+		/*Without SMFC, CSI only support parallel data source*/
+		ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
+			params->csi_prp_vf_mem.csi));
+
+		/*CSI0/1 feed into IC*/
+		ipu_conf &= ~IPU_CONF_IC_INPUT;
+		if (params->csi_prp_vf_mem.csi)
+			ipu_conf |= IPU_CONF_CSI_SEL;
+		else
+			ipu_conf &= ~IPU_CONF_CSI_SEL;
+
+		/*PRP skip buffer in memory, only valid when RWS_EN is true*/
+		reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+		ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
+
+		/*CSI data (include compander) dest*/
+		_ipu_csi_init(ipu, channel, params->csi_prp_vf_mem.csi);
+		_ipu_ic_init_prpvf(ipu, params, true);
+		break;
+	case MEM_PRP_VF_MEM:
+		ipu->ic_use_count++;
+		reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+		ipu_cm_write(ipu, reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
+
+		if (params->mem_prp_vf_mem.graphics_combine_en)
+			ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
+		if (params->mem_prp_vf_mem.alpha_chan_en)
+			ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		_ipu_ic_init_prpvf(ipu, params, false);
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		if ((ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
+		     (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
+			ret = -EINVAL;
+			goto err;
+		}
+		ipu->using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM;
+		ipu->ic_use_count++;
+		ipu->vdi_use_count++;
+		reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+		reg &= ~FS_VDI_SRC_SEL_MASK;
+		ipu_cm_write(ipu, reg , IPU_FS_PROC_FLOW1);
+
+		if (params->mem_prp_vf_mem.graphics_combine_en)
+			ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
+		_ipu_ic_init_prpvf(ipu, params, false);
+		_ipu_vdi_init(ipu, channel, params);
+		break;
+	case MEM_VDI_PRP_VF_MEM_P:
+		_ipu_vdi_init(ipu, channel, params);
+		break;
+	case MEM_VDI_PRP_VF_MEM_N:
+		_ipu_vdi_init(ipu, channel, params);
+		break;
+	case MEM_ROT_VF_MEM:
+		ipu->ic_use_count++;
+		ipu->rot_use_count++;
+		_ipu_ic_init_rotate_vf(ipu, params);
+		break;
+	case MEM_PRP_ENC_MEM:
+		ipu->ic_use_count++;
+		reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+		ipu_cm_write(ipu, reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
+		_ipu_ic_init_prpenc(ipu, params, false);
+		break;
+	case MEM_ROT_ENC_MEM:
+		ipu->ic_use_count++;
+		ipu->rot_use_count++;
+		_ipu_ic_init_rotate_enc(ipu, params);
+		break;
+	case MEM_PP_MEM:
+		if (params->mem_pp_mem.graphics_combine_en)
+			ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
+		if (params->mem_pp_mem.alpha_chan_en)
+			ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+		_ipu_ic_init_pp(ipu, params);
+		ipu->ic_use_count++;
+		break;
+	case MEM_ROT_PP_MEM:
+		_ipu_ic_init_rotate_pp(ipu, params);
+		ipu->ic_use_count++;
+		ipu->rot_use_count++;
+		break;
+	case MEM_DC_SYNC:
+		if (params->mem_dc_sync.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		ipu->dc_di_assignment[1] = params->mem_dc_sync.di;
+		_ipu_dc_init(ipu, 1, params->mem_dc_sync.di,
+			     params->mem_dc_sync.interlaced,
+			     params->mem_dc_sync.out_pixel_fmt);
+		ipu->di_use_count[params->mem_dc_sync.di]++;
+		ipu->dc_use_count++;
+		ipu->dmfc_use_count++;
+		break;
+	case MEM_BG_SYNC:
+		if (params->mem_dp_bg_sync.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		if (params->mem_dp_bg_sync.alpha_chan_en)
+			ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		ipu->dc_di_assignment[5] = params->mem_dp_bg_sync.di;
+		_ipu_dp_init(ipu, channel, params->mem_dp_bg_sync.in_pixel_fmt,
+			     params->mem_dp_bg_sync.out_pixel_fmt);
+		_ipu_dc_init(ipu, 5, params->mem_dp_bg_sync.di,
+			     params->mem_dp_bg_sync.interlaced,
+			     params->mem_dp_bg_sync.out_pixel_fmt);
+		ipu->di_use_count[params->mem_dp_bg_sync.di]++;
+		ipu->dc_use_count++;
+		ipu->dp_use_count++;
+		ipu->dmfc_use_count++;
+		break;
+	case MEM_FG_SYNC:
+		_ipu_dp_init(ipu, channel, params->mem_dp_fg_sync.in_pixel_fmt,
+			     params->mem_dp_fg_sync.out_pixel_fmt);
+
+		if (params->mem_dp_fg_sync.alpha_chan_en)
+			ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
+
+		ipu->dc_use_count++;
+		ipu->dp_use_count++;
+		ipu->dmfc_use_count++;
+		break;
+	case DIRECT_ASYNC0:
+		if (params->direct_async.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		ipu->dc_di_assignment[8] = params->direct_async.di;
+		_ipu_dc_init(ipu, 8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
+		ipu->di_use_count[params->direct_async.di]++;
+		ipu->dc_use_count++;
+		break;
+	case DIRECT_ASYNC1:
+		if (params->direct_async.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		ipu->dc_di_assignment[9] = params->direct_async.di;
+		_ipu_dc_init(ipu, 9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
+		ipu->di_use_count[params->direct_async.di]++;
+		ipu->dc_use_count++;
+		break;
+	default:
+		dev_err(ipu->dev, "Missing channel initialization\n");
+		break;
+	}
+
+	ipu->channel_init_mask |= 1L << IPU_CHAN_ID(channel);
+
+	ipu_cm_write(ipu, ipu_conf, IPU_CONF);
+
+err:
+	_ipu_unlock(ipu);
+	return ret;
+}
+EXPORT_SYMBOL(ipu_init_channel);
+
+/*!
+ * This function is called to uninitialize a logical IPU channel.
+ *
+ * @param	ipu	ipu handler
+ * @param       channel Input parameter for the logical channel ID to uninit.
+ */
+void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel)
+{
+	uint32_t reg;
+	uint32_t in_dma, out_dma = 0;
+	uint32_t ipu_conf;
+
+	_ipu_lock(ipu);
+
+	if ((ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
+		dev_err(ipu->dev, "Channel already uninitialized %d\n",
+			IPU_CHAN_ID(channel));
+		_ipu_unlock(ipu);
+		return;
+	}
+
+	/* Make sure channel is disabled */
+	/* Get input and output dma channels */
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+
+	if (idma_is_set(ipu, IDMAC_CHA_EN, in_dma) ||
+	    idma_is_set(ipu, IDMAC_CHA_EN, out_dma)) {
+		dev_err(ipu->dev,
+			"Channel %d is not disabled, disable first\n",
+			IPU_CHAN_ID(channel));
+		_ipu_unlock(ipu);
+		return;
+	}
+
+	ipu_conf = ipu_cm_read(ipu, IPU_CONF);
+
+	/* Reset the double buffer */
+	reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(in_dma));
+	ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
+	reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(out_dma));
+	ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
+
+	/* Reset the triple buffer */
+	reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(in_dma));
+	ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_TRB_MODE_SEL(in_dma));
+	reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(out_dma));
+	ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_TRB_MODE_SEL(out_dma));
+
+	if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
+		ipu->sec_chan_en[IPU_CHAN_ID(channel)] = false;
+		ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = false;
+	}
+
+	switch (channel) {
+	case CSI_MEM0:
+	case CSI_MEM1:
+	case CSI_MEM2:
+	case CSI_MEM3:
+		ipu->smfc_use_count--;
+		if (ipu->csi_channel[0] == channel) {
+			ipu->csi_channel[0] = CHAN_NONE;
+		} else if (ipu->csi_channel[1] == channel) {
+			ipu->csi_channel[1] = CHAN_NONE;
+		}
+		break;
+	case CSI_PRP_ENC_MEM:
+		ipu->ic_use_count--;
+		if (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)
+			ipu->using_ic_dirct_ch = 0;
+		_ipu_ic_uninit_prpenc(ipu);
+		if (ipu->csi_channel[0] == channel) {
+			ipu->csi_channel[0] = CHAN_NONE;
+		} else if (ipu->csi_channel[1] == channel) {
+			ipu->csi_channel[1] = CHAN_NONE;
+		}
+		break;
+	case CSI_PRP_VF_MEM:
+		ipu->ic_use_count--;
+		if (ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM)
+			ipu->using_ic_dirct_ch = 0;
+		_ipu_ic_uninit_prpvf(ipu);
+		if (ipu->csi_channel[0] == channel) {
+			ipu->csi_channel[0] = CHAN_NONE;
+		} else if (ipu->csi_channel[1] == channel) {
+			ipu->csi_channel[1] = CHAN_NONE;
+		}
+		break;
+	case MEM_PRP_VF_MEM:
+		ipu->ic_use_count--;
+		_ipu_ic_uninit_prpvf(ipu);
+		reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+		ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		ipu->ic_use_count--;
+		ipu->vdi_use_count--;
+		if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM)
+			ipu->using_ic_dirct_ch = 0;
+		_ipu_ic_uninit_prpvf(ipu);
+		_ipu_vdi_uninit(ipu);
+		reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+		ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
+		break;
+	case MEM_VDI_PRP_VF_MEM_P:
+	case MEM_VDI_PRP_VF_MEM_N:
+		break;
+	case MEM_ROT_VF_MEM:
+		ipu->rot_use_count--;
+		ipu->ic_use_count--;
+		_ipu_ic_uninit_rotate_vf(ipu);
+		break;
+	case MEM_PRP_ENC_MEM:
+		ipu->ic_use_count--;
+		_ipu_ic_uninit_prpenc(ipu);
+		reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+		ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
+		break;
+	case MEM_ROT_ENC_MEM:
+		ipu->rot_use_count--;
+		ipu->ic_use_count--;
+		_ipu_ic_uninit_rotate_enc(ipu);
+		break;
+	case MEM_PP_MEM:
+		ipu->ic_use_count--;
+		_ipu_ic_uninit_pp(ipu);
+		break;
+	case MEM_ROT_PP_MEM:
+		ipu->rot_use_count--;
+		ipu->ic_use_count--;
+		_ipu_ic_uninit_rotate_pp(ipu);
+		break;
+	case MEM_DC_SYNC:
+		_ipu_dc_uninit(ipu, 1);
+		ipu->di_use_count[ipu->dc_di_assignment[1]]--;
+		ipu->dc_use_count--;
+		ipu->dmfc_use_count--;
+		break;
+	case MEM_BG_SYNC:
+		_ipu_dp_uninit(ipu, channel);
+		_ipu_dc_uninit(ipu, 5);
+		ipu->di_use_count[ipu->dc_di_assignment[5]]--;
+		ipu->dc_use_count--;
+		ipu->dp_use_count--;
+		ipu->dmfc_use_count--;
+		break;
+	case MEM_FG_SYNC:
+		_ipu_dp_uninit(ipu, channel);
+		ipu->dc_use_count--;
+		ipu->dp_use_count--;
+		ipu->dmfc_use_count--;
+		break;
+	case DIRECT_ASYNC0:
+		_ipu_dc_uninit(ipu, 8);
+		ipu->di_use_count[ipu->dc_di_assignment[8]]--;
+		ipu->dc_use_count--;
+		break;
+	case DIRECT_ASYNC1:
+		_ipu_dc_uninit(ipu, 9);
+		ipu->di_use_count[ipu->dc_di_assignment[9]]--;
+		ipu->dc_use_count--;
+		break;
+	default:
+		break;
+	}
+
+	if (ipu->ic_use_count == 0)
+		ipu_conf &= ~IPU_CONF_IC_EN;
+	if (ipu->vdi_use_count == 0) {
+		ipu_conf &= ~IPU_CONF_ISP_EN;
+		ipu_conf &= ~IPU_CONF_VDI_EN;
+		ipu_conf &= ~IPU_CONF_IC_INPUT;
+	}
+	if (ipu->rot_use_count == 0)
+		ipu_conf &= ~IPU_CONF_ROT_EN;
+	if (ipu->dc_use_count == 0)
+		ipu_conf &= ~IPU_CONF_DC_EN;
+	if (ipu->dp_use_count == 0)
+		ipu_conf &= ~IPU_CONF_DP_EN;
+	if (ipu->dmfc_use_count == 0)
+		ipu_conf &= ~IPU_CONF_DMFC_EN;
+	if (ipu->di_use_count[0] == 0) {
+		ipu_conf &= ~IPU_CONF_DI0_EN;
+	}
+	if (ipu->di_use_count[1] == 0) {
+		ipu_conf &= ~IPU_CONF_DI1_EN;
+	}
+	if (ipu->smfc_use_count == 0)
+		ipu_conf &= ~IPU_CONF_SMFC_EN;
+
+	ipu_cm_write(ipu, ipu_conf, IPU_CONF);
+
+	ipu->channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
+
+	_ipu_unlock(ipu);
+
+	_ipu_put(ipu);
+
+	WARN_ON(ipu->ic_use_count < 0);
+	WARN_ON(ipu->vdi_use_count < 0);
+	WARN_ON(ipu->rot_use_count < 0);
+	WARN_ON(ipu->dc_use_count < 0);
+	WARN_ON(ipu->dp_use_count < 0);
+	WARN_ON(ipu->dmfc_use_count < 0);
+	WARN_ON(ipu->smfc_use_count < 0);
+}
+EXPORT_SYMBOL(ipu_uninit_channel);
+
+/*!
+ * This function is called to initialize buffer(s) for logical IPU channel.
+ *
+ * @param	ipu		ipu handler
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer.
+ *                              Pixel format is a FOURCC ASCII code.
+ *
+ * @param       width           Input parameter for width of buffer in pixels.
+ *
+ * @param       height          Input parameter for height of buffer in pixels.
+ *
+ * @param       stride          Input parameter for stride length of buffer
+ *                              in pixels.
+ *
+ * @param       rot_mode        Input parameter for rotation setting of buffer.
+ *                              A rotation setting other than
+ *                              IPU_ROTATE_VERT_FLIP
+ *                              should only be used for input buffers of
+ *                              rotation channels.
+ *
+ * @param       phyaddr_0       Input parameter buffer 0 physical address.
+ *
+ * @param       phyaddr_1       Input parameter buffer 1 physical address.
+ *                              Setting this to a value other than NULL enables
+ *                              double buffering mode.
+ *
+ * @param       phyaddr_2       Input parameter buffer 2 physical address.
+ *                              Setting this to a value other than NULL enables
+ *                              triple buffering mode, phyaddr_1 should not be
+ *                              NULL then.
+ *
+ * @param       u		private u offset for additional cropping,
+ *				zero if not used.
+ *
+ * @param       v		private v offset for additional cropping,
+ *				zero if not used.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
+				ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				ipu_rotate_mode_t rot_mode,
+				dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+				dma_addr_t phyaddr_2,
+				uint32_t u, uint32_t v)
+{
+	uint32_t reg;
+	uint32_t dma_chan;
+	uint32_t burst_size;
+
+	dma_chan = channel_2_dma(channel, type);
+	if (!idma_is_valid(dma_chan))
+		return -EINVAL;
+
+	if (stride < width * bytes_per_pixel(pixel_fmt))
+		stride = width * bytes_per_pixel(pixel_fmt);
+
+	if (stride % 4) {
+		dev_err(ipu->dev,
+			"Stride not 32-bit aligned, stride = %d\n", stride);
+		return -EINVAL;
+	}
+	/* IC & IRT channels' width must be multiple of 8 pixels */
+	if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
+		&& (width % 8)) {
+		dev_err(ipu->dev, "Width must be 8 pixel multiple\n");
+		return -EINVAL;
+	}
+
+	/* IPUv3EX and IPUv3M support triple buffer */
+	if ((!_ipu_is_trb_chan(dma_chan)) && phyaddr_2) {
+		dev_err(ipu->dev, "Chan%d doesn't support triple buffer "
+				   "mode\n", dma_chan);
+		return -EINVAL;
+	}
+	if (!phyaddr_1 && phyaddr_2) {
+		dev_err(ipu->dev, "Chan%d's buf1 physical addr is NULL for "
+				   "triple buffer mode\n", dma_chan);
+		return -EINVAL;
+	}
+
+	_ipu_lock(ipu);
+
+	/* Build parameter memory data for DMA channel */
+	_ipu_ch_param_init(ipu, dma_chan, pixel_fmt, width, height, stride, u, v, 0,
+			   phyaddr_0, phyaddr_1, phyaddr_2);
+
+	/* Set correlative channel parameter of local alpha channel */
+	if ((_ipu_is_ic_graphic_chan(dma_chan) ||
+	     _ipu_is_dp_graphic_chan(dma_chan)) &&
+	    (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
+		_ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, true);
+		_ipu_ch_param_set_alpha_buffer_memory(ipu, dma_chan);
+		_ipu_ch_param_set_alpha_condition_read(ipu, dma_chan);
+		/* fix alpha width as 8 and burst size as 16*/
+		_ipu_ch_params_set_alpha_width(ipu, dma_chan, 8);
+		_ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
+	} else if (_ipu_is_ic_graphic_chan(dma_chan) &&
+		   ipu_pixel_format_has_alpha(pixel_fmt))
+		_ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, false);
+
+	if (rot_mode)
+		_ipu_ch_param_set_rotation(ipu, dma_chan, rot_mode);
+
+	/* IC and ROT channels have restriction of 8 or 16 pix burst length */
+	if (_ipu_is_ic_chan(dma_chan)) {
+		if ((width % 16) == 0)
+			_ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
+		else
+			_ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
+	} else if (_ipu_is_irt_chan(dma_chan)) {
+		_ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
+		_ipu_ch_param_set_block_mode(ipu, dma_chan);
+	} else if (_ipu_is_dmfc_chan(dma_chan)) {
+		burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
+		_ipu_dmfc_set_wait4eot(ipu, dma_chan, width);
+		_ipu_dmfc_set_burst_size(ipu, dma_chan, burst_size);
+	}
+
+	if (_ipu_disp_chan_is_interlaced(ipu, channel) ||
+		ipu->chan_is_interlaced[dma_chan])
+		_ipu_ch_param_set_interlaced_scan(ipu, dma_chan);
+
+	if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) {
+		burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
+		_ipu_ic_idma_init(ipu, dma_chan, width, height, burst_size,
+			rot_mode);
+	} else if (_ipu_is_smfc_chan(dma_chan)) {
+		burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
+		if ((pixel_fmt == IPU_PIX_FMT_GENERIC) &&
+			((_ipu_ch_param_get_bpp(ipu, dma_chan) == 5) ||
+			(_ipu_ch_param_get_bpp(ipu, dma_chan) == 3)))
+			burst_size = burst_size >> 4;
+		else
+			burst_size = burst_size >> 2;
+		_ipu_smfc_set_burst_size(ipu, channel, burst_size-1);
+	}
+
+	/* AXI-id */
+	if (idma_is_set(ipu, IDMAC_CHA_PRI, dma_chan)) {
+		unsigned reg = IDMAC_CH_LOCK_EN_1;
+		uint32_t value = 0;
+		if (cpu_is_mx53() || cpu_is_mx6q()) {
+			_ipu_ch_param_set_axi_id(ipu, dma_chan, 0);
+			switch (dma_chan) {
+			case 5:
+				value = 0x3;
+				break;
+			case 11:
+				value = 0x3 << 2;
+				break;
+			case 12:
+				value = 0x3 << 4;
+				break;
+			case 14:
+				value = 0x3 << 6;
+				break;
+			case 15:
+				value = 0x3 << 8;
+				break;
+			case 20:
+				value = 0x3 << 10;
+				break;
+			case 21:
+				value = 0x3 << 12;
+				break;
+			case 22:
+				value = 0x3 << 14;
+				break;
+			case 23:
+				value = 0x3 << 16;
+				break;
+			case 27:
+				value = 0x3 << 18;
+				break;
+			case 28:
+				value = 0x3 << 20;
+				break;
+			case 45:
+				reg = IDMAC_CH_LOCK_EN_2;
+				value = 0x3 << 0;
+				break;
+			case 46:
+				reg = IDMAC_CH_LOCK_EN_2;
+				value = 0x3 << 2;
+				break;
+			case 47:
+				reg = IDMAC_CH_LOCK_EN_2;
+				value = 0x3 << 4;
+				break;
+			case 48:
+				reg = IDMAC_CH_LOCK_EN_2;
+				value = 0x3 << 6;
+				break;
+			case 49:
+				reg = IDMAC_CH_LOCK_EN_2;
+				value = 0x3 << 8;
+				break;
+			case 50:
+				reg = IDMAC_CH_LOCK_EN_2;
+				value = 0x3 << 10;
+				break;
+			default:
+				break;
+			}
+			value |= ipu_idmac_read(ipu, reg);
+			ipu_idmac_write(ipu, value, reg);
+		} else
+			_ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
+	} else {
+		if (cpu_is_mx6q())
+			_ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
+	}
+
+	_ipu_ch_param_dump(ipu, dma_chan);
+
+	if (phyaddr_2 && g_ipu_hw_rev >= 2) {
+		reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
+		reg &= ~idma_mask(dma_chan);
+		ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
+
+		reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
+		reg |= idma_mask(dma_chan);
+		ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
+
+		/* Set IDMAC third buffer's cpmem number */
+		/* See __ipu_ch_get_third_buf_cpmem_num() for mapping */
+		ipu_idmac_write(ipu, 0x00444047L, IDMAC_SUB_ADDR_4);
+		ipu_idmac_write(ipu, 0x46004241L, IDMAC_SUB_ADDR_3);
+		ipu_idmac_write(ipu, 0x00000045L, IDMAC_SUB_ADDR_1);
+
+		/* Reset to buffer 0 */
+		ipu_cm_write(ipu, tri_cur_buf_mask(dma_chan),
+				IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
+	} else {
+		reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
+		reg &= ~idma_mask(dma_chan);
+		ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
+
+		reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
+		if (phyaddr_1)
+			reg |= idma_mask(dma_chan);
+		else
+			reg &= ~idma_mask(dma_chan);
+		ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
+
+		/* Reset to buffer 0 */
+		ipu_cm_write(ipu, idma_mask(dma_chan),
+				IPU_CHA_CUR_BUF(dma_chan));
+
+	}
+
+	_ipu_unlock(ipu);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_init_channel_buffer);
+
+/*!
+ * This function is called to update the physical address of a buffer for
+ * a logical IPU channel.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       bufNum          Input parameter for buffer number to update.
+ *                              0 or 1 are the only valid values.
+ *
+ * @param       phyaddr         Input parameter buffer physical address.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail. This function will fail if the buffer is set to ready.
+ */
+int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
+				ipu_buffer_t type, uint32_t bufNum, dma_addr_t phyaddr)
+{
+	uint32_t reg;
+	int ret = 0;
+	uint32_t dma_chan = channel_2_dma(channel, type);
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	_ipu_lock(ipu);
+
+	if (bufNum == 0)
+		reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
+	else if (bufNum == 1)
+		reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
+	else
+		reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
+
+	if ((reg & idma_mask(dma_chan)) == 0)
+		_ipu_ch_param_set_buffer(ipu, dma_chan, bufNum, phyaddr);
+	else
+		ret = -EACCES;
+
+	_ipu_unlock(ipu);
+
+	return ret;
+}
+EXPORT_SYMBOL(ipu_update_channel_buffer);
+
+
+/*!
+ * This function is called to initialize a buffer for logical IPU channel.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer.
+ *                              Pixel format is a FOURCC ASCII code.
+ *
+ * @param       width           Input parameter for width of buffer in pixels.
+ *
+ * @param       height          Input parameter for height of buffer in pixels.
+ *
+ * @param       stride          Input parameter for stride length of buffer
+ *                              in pixels.
+ *
+ * @param       u		predefined private u offset for additional cropping,
+ *								zero if not used.
+ *
+ * @param       v		predefined private v offset for additional cropping,
+ *								zero if not used.
+ *
+ * @param			vertical_offset vertical offset for Y coordinate
+ * 								in the existed frame
+ *
+ *
+ * @param			horizontal_offset horizontal offset for X coordinate
+ * 								in the existed frame
+ *
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ *              This function will fail if any buffer is set to ready.
+ */
+
+int32_t ipu_update_channel_offset(struct ipu_soc *ipu,
+				ipu_channel_t channel, ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				uint32_t u, uint32_t v,
+				uint32_t vertical_offset, uint32_t horizontal_offset)
+{
+	int ret = 0;
+	uint32_t dma_chan = channel_2_dma(channel, type);
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	_ipu_lock(ipu);
+
+	if ((ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) ||
+	    (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan)) & idma_mask(dma_chan)) ||
+	    ((ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan)) & idma_mask(dma_chan)) &&
+	     (ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan)) & idma_mask(dma_chan)) &&
+	     _ipu_is_trb_chan(dma_chan)))
+		ret = -EACCES;
+	else
+		_ipu_ch_offset_update(ipu, dma_chan, pixel_fmt, width, height, stride,
+				      u, v, 0, vertical_offset, horizontal_offset);
+
+	_ipu_unlock(ipu);
+	return ret;
+}
+EXPORT_SYMBOL(ipu_update_channel_offset);
+
+
+/*!
+ * This function is called to set a channel's buffer as ready.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       bufNum          Input parameter for which buffer number set to
+ *                              ready state.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
+			ipu_buffer_t type, uint32_t bufNum)
+{
+	uint32_t dma_chan = channel_2_dma(channel, type);
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	/* Mark buffer to be ready. */
+	_ipu_lock(ipu);
+	if (bufNum == 0)
+		ipu_cm_write(ipu, idma_mask(dma_chan),
+			     IPU_CHA_BUF0_RDY(dma_chan));
+	else if (bufNum == 1)
+		ipu_cm_write(ipu, idma_mask(dma_chan),
+			     IPU_CHA_BUF1_RDY(dma_chan));
+	else
+		ipu_cm_write(ipu, idma_mask(dma_chan),
+			     IPU_CHA_BUF2_RDY(dma_chan));
+	_ipu_unlock(ipu);
+	return 0;
+}
+EXPORT_SYMBOL(ipu_select_buffer);
+
+/*!
+ * This function is called to set a channel's buffer as ready.
+ *
+ * @param	ipu		ipu handler
+ * @param       bufNum          Input parameter for which buffer number set to
+ *                              ready state.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum)
+{
+
+	uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER);
+	uint32_t mask_bit =
+		idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))|
+		idma_mask(dma_chan)|
+		idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER));
+
+	/* Mark buffers to be ready. */
+	_ipu_lock(ipu);
+	if (bufNum == 0)
+		ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF0_RDY(dma_chan));
+	else
+		ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF1_RDY(dma_chan));
+	_ipu_unlock(ipu);
+	return 0;
+}
+EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
+
+#define NA	-1
+static int proc_dest_sel[] = {
+	0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
+	0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
+static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
+  NA, NA, NA, NA, NA,  1,  2,  3,  4,  7,  8, NA, 8, NA };
+static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
+  NA, NA, NA, NA, NA,  1, NA,  2, NA,  3,  4,  4,  4,  4 };
+
+
+/*!
+ * This function links 2 channels together for automatic frame
+ * synchronization. The output of the source channel is linked to the input of
+ * the destination channel.
+ *
+ * @param	ipu		ipu handler
+ * @param       src_ch          Input parameter for the logical channel ID of
+ *                              the source channel.
+ *
+ * @param       dest_ch         Input parameter for the logical channel ID of
+ *                              the destination channel.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
+{
+	int retval = 0;
+	uint32_t fs_proc_flow1;
+	uint32_t fs_proc_flow2;
+	uint32_t fs_proc_flow3;
+	uint32_t fs_disp_flow1;
+
+	_ipu_lock(ipu);
+
+	fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+	fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
+	fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
+	fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
+
+	switch (src_ch) {
+	case CSI_MEM0:
+		fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
+		fs_proc_flow3 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_SMFC0_DEST_SEL_OFFSET;
+		break;
+	case CSI_MEM1:
+		fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
+		fs_proc_flow3 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_SMFC1_DEST_SEL_OFFSET;
+		break;
+	case CSI_MEM2:
+		fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
+		fs_proc_flow3 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_SMFC2_DEST_SEL_OFFSET;
+		break;
+	case CSI_MEM3:
+		fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
+		fs_proc_flow3 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_SMFC3_DEST_SEL_OFFSET;
+		break;
+	case CSI_PRP_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_PRPENC_DEST_SEL_OFFSET;
+		break;
+	case CSI_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+			proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+			FS_PRPVF_DEST_SEL_OFFSET;
+		break;
+	case MEM_PP_MEM:
+		fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PP_DEST_SEL_OFFSET;
+		break;
+	case MEM_ROT_PP_MEM:
+		fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PP_ROT_DEST_SEL_OFFSET;
+		break;
+	case MEM_PRP_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPENC_DEST_SEL_OFFSET;
+		break;
+	case MEM_ROT_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPENC_ROT_DEST_SEL_OFFSET;
+		break;
+	case MEM_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPVF_DEST_SEL_OFFSET;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPVF_DEST_SEL_OFFSET;
+		break;
+	case MEM_ROT_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
+		fs_proc_flow2 |=
+		    proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
+		    FS_PRPVF_ROT_DEST_SEL_OFFSET;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	switch (dest_ch) {
+	case MEM_PP_MEM:
+		fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PP_SRC_SEL_OFFSET;
+		break;
+	case MEM_ROT_PP_MEM:
+		fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_PP_ROT_SRC_SEL_OFFSET;
+		break;
+	case MEM_PRP_ENC_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
+		break;
+	case MEM_ROT_ENC_MEM:
+		fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_PRPENC_ROT_SRC_SEL_OFFSET;
+		break;
+	case MEM_PRP_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
+		break;
+	case MEM_ROT_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
+		fs_proc_flow1 |=
+		    proc_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_PRPVF_ROT_SRC_SEL_OFFSET;
+		break;
+	case MEM_DC_SYNC:
+		fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET;
+		break;
+	case MEM_BG_SYNC:
+		fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_DP_SYNC0_SRC_SEL_OFFSET;
+		break;
+	case MEM_FG_SYNC:
+		fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_DP_SYNC1_SRC_SEL_OFFSET;
+		break;
+	case MEM_DC_ASYNC:
+		fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET;
+		break;
+	case MEM_BG_ASYNC0:
+		fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_DP_ASYNC0_SRC_SEL_OFFSET;
+		break;
+	case MEM_FG_ASYNC0:
+		fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
+		fs_disp_flow1 |=
+		    disp_src_sel[IPU_CHAN_ID(src_ch)] <<
+		    FS_DP_ASYNC1_SRC_SEL_OFFSET;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
+	ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
+	ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
+	ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
+
+err:
+	_ipu_unlock(ipu);
+	return retval;
+}
+EXPORT_SYMBOL(ipu_link_channels);
+
+/*!
+ * This function unlinks 2 channels and disables automatic frame
+ * synchronization.
+ *
+ * @param	ipu		ipu handler
+ * @param       src_ch          Input parameter for the logical channel ID of
+ *                              the source channel.
+ *
+ * @param       dest_ch         Input parameter for the logical channel ID of
+ *                              the destination channel.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
+{
+	int retval = 0;
+	uint32_t fs_proc_flow1;
+	uint32_t fs_proc_flow2;
+	uint32_t fs_proc_flow3;
+	uint32_t fs_disp_flow1;
+
+	_ipu_lock(ipu);
+
+	fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
+	fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
+	fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
+	fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
+
+	switch (src_ch) {
+	case CSI_MEM0:
+		fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
+		break;
+	case CSI_MEM1:
+		fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
+		break;
+	case CSI_MEM2:
+		fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
+		break;
+	case CSI_MEM3:
+		fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
+		break;
+	case CSI_PRP_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
+		break;
+	case CSI_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		break;
+	case MEM_PP_MEM:
+		fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
+		break;
+	case MEM_ROT_PP_MEM:
+		fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
+		break;
+	case MEM_PRP_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
+		break;
+	case MEM_ROT_ENC_MEM:
+		fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
+		break;
+	case MEM_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
+		break;
+	case MEM_ROT_VF_MEM:
+		fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	switch (dest_ch) {
+	case MEM_PP_MEM:
+		fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
+		break;
+	case MEM_ROT_PP_MEM:
+		fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
+		break;
+	case MEM_PRP_ENC_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		break;
+	case MEM_ROT_ENC_MEM:
+		fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
+		break;
+	case MEM_PRP_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
+		break;
+	case MEM_ROT_VF_MEM:
+		fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
+		break;
+	case MEM_DC_SYNC:
+		fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
+		break;
+	case MEM_BG_SYNC:
+		fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
+		break;
+	case MEM_FG_SYNC:
+		fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
+		break;
+	case MEM_DC_ASYNC:
+		fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
+		break;
+	case MEM_BG_ASYNC0:
+		fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
+		break;
+	case MEM_FG_ASYNC0:
+		fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
+		break;
+	default:
+		retval = -EINVAL;
+		goto err;
+	}
+
+	ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
+	ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
+	ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
+	ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
+
+err:
+	_ipu_unlock(ipu);
+	return retval;
+}
+EXPORT_SYMBOL(ipu_unlink_channels);
+
+/*!
+ * This function check whether a logical channel was enabled.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @return      This function returns 1 while request channel is enabled or
+ *              0 for not enabled.
+ */
+int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel)
+{
+	uint32_t reg;
+	uint32_t in_dma;
+	uint32_t out_dma;
+
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+	reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
+	if (reg & idma_mask(in_dma))
+		return 1;
+	reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
+	if (reg & idma_mask(out_dma))
+		return 1;
+	return 0;
+}
+EXPORT_SYMBOL(ipu_is_channel_busy);
+
+/*!
+ * This function enables a logical channel.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel)
+{
+	uint32_t reg;
+	uint32_t ipu_conf;
+	uint32_t in_dma;
+	uint32_t out_dma;
+	uint32_t sec_dma;
+	uint32_t thrd_dma;
+
+	_ipu_lock(ipu);
+
+	if (ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
+		dev_err(ipu->dev, "Warning: channel already enabled %d\n",
+			IPU_CHAN_ID(channel));
+		_ipu_unlock(ipu);
+		return -EACCES;
+	}
+
+	/* Get input and output dma channels */
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+	ipu_conf = ipu_cm_read(ipu, IPU_CONF);
+	if (ipu->di_use_count[0] > 0) {
+		ipu_conf |= IPU_CONF_DI0_EN;
+	}
+	if (ipu->di_use_count[1] > 0) {
+		ipu_conf |= IPU_CONF_DI1_EN;
+	}
+	if (ipu->dp_use_count > 0)
+		ipu_conf |= IPU_CONF_DP_EN;
+	if (ipu->dc_use_count > 0)
+		ipu_conf |= IPU_CONF_DC_EN;
+	if (ipu->dmfc_use_count > 0)
+		ipu_conf |= IPU_CONF_DMFC_EN;
+	if (ipu->ic_use_count > 0)
+		ipu_conf |= IPU_CONF_IC_EN;
+	if (ipu->vdi_use_count > 0) {
+		ipu_conf |= IPU_CONF_ISP_EN;
+		ipu_conf |= IPU_CONF_VDI_EN;
+		ipu_conf |= IPU_CONF_IC_INPUT;
+	}
+	if (ipu->rot_use_count > 0)
+		ipu_conf |= IPU_CONF_ROT_EN;
+	if (ipu->smfc_use_count > 0)
+		ipu_conf |= IPU_CONF_SMFC_EN;
+	ipu_cm_write(ipu, ipu_conf, IPU_CONF);
+
+	if (idma_is_valid(in_dma)) {
+		reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
+		ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
+	}
+	if (idma_is_valid(out_dma)) {
+		reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
+		ipu_idmac_write(ipu, reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
+	}
+
+	if ((ipu->sec_chan_en[IPU_CHAN_ID(channel)]) &&
+		((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
+		 (channel == MEM_VDI_PRP_VF_MEM))) {
+		sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
+		reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
+		ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
+	}
+	if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
+		((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
+		thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
+		reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
+		ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
+
+		sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
+		reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
+		ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA);
+	} else if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
+		   ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) {
+		thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
+		reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
+		ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
+		reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
+		ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_SEP_ALPHA);
+	}
+
+	if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
+	    (channel == MEM_FG_SYNC)) {
+		reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
+		ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
+
+		_ipu_dp_dc_enable(ipu, channel);
+	}
+
+	if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
+		_ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
+		_ipu_ic_enable_task(ipu, channel);
+
+	ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
+
+	_ipu_unlock(ipu);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_enable_channel);
+
+/*!
+ * This function check buffer ready for a logical channel.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to clear.
+ *
+ * @param       bufNum          Input parameter for which buffer number clear
+ * 				ready state.
+ *
+ */
+int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	uint32_t dma_chan = channel_2_dma(channel, type);
+	uint32_t reg;
+
+	if (dma_chan == IDMA_CHAN_INVALID)
+		return -EINVAL;
+
+	if (bufNum == 0)
+		reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
+	else if (bufNum == 1)
+		reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
+	else
+		reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
+
+	if (reg & idma_mask(dma_chan))
+		return 1;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(ipu_check_buffer_ready);
+
+/*!
+ * This function clear buffer ready for a logical channel.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to clear.
+ *
+ * @param       bufNum          Input parameter for which buffer number clear
+ * 				ready state.
+ *
+ */
+void _ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	uint32_t dma_ch = channel_2_dma(channel, type);
+
+	if (!idma_is_valid(dma_ch))
+		return;
+
+	ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
+	if (bufNum == 0)
+		ipu_cm_write(ipu, idma_mask(dma_ch),
+				IPU_CHA_BUF0_RDY(dma_ch));
+	else if (bufNum == 1)
+		ipu_cm_write(ipu, idma_mask(dma_ch),
+				IPU_CHA_BUF1_RDY(dma_ch));
+	else
+		ipu_cm_write(ipu, idma_mask(dma_ch),
+				IPU_CHA_BUF2_RDY(dma_ch));
+	ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
+}
+
+void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	_ipu_lock(ipu);
+	_ipu_clear_buffer_ready(ipu, channel, type, bufNum);
+	_ipu_unlock(ipu);
+}
+EXPORT_SYMBOL(ipu_clear_buffer_ready);
+
+/*!
+ * This function disables a logical channel.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       wait_for_stop   Flag to set whether to wait for channel end
+ *                              of frame or return immediately.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop)
+{
+	uint32_t reg;
+	uint32_t in_dma;
+	uint32_t out_dma;
+	uint32_t sec_dma = NO_DMA;
+	uint32_t thrd_dma = NO_DMA;
+	uint16_t fg_pos_x, fg_pos_y;
+
+	_ipu_lock(ipu);
+
+	if ((ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
+		dev_err(ipu->dev, "Channel already disabled %d\n",
+			IPU_CHAN_ID(channel));
+		_ipu_unlock(ipu);
+		return -EACCES;
+	}
+
+	/* Get input and output dma channels */
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+	if ((idma_is_valid(in_dma) &&
+		!idma_is_set(ipu, IDMAC_CHA_EN, in_dma))
+		&& (idma_is_valid(out_dma) &&
+		!idma_is_set(ipu, IDMAC_CHA_EN, out_dma))) {
+		_ipu_unlock(ipu);
+		return -EINVAL;
+	}
+
+	if (ipu->sec_chan_en[IPU_CHAN_ID(channel)])
+		sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
+	if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) {
+		sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
+		thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
+	}
+
+	if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
+	    (channel == MEM_DC_SYNC)) {
+		if (channel == MEM_FG_SYNC) {
+			_ipu_disp_get_window_pos(ipu, channel, &fg_pos_x, &fg_pos_y);
+			_ipu_disp_set_window_pos(ipu, channel, 0, 0);
+		}
+
+		_ipu_dp_dc_disable(ipu, channel, false);
+
+		/*
+		 * wait for BG channel EOF then disable FG-IDMAC,
+		 * it avoid FG NFB4EOF error.
+		 */
+		if ((channel == MEM_FG_SYNC) && (ipu_is_channel_busy(ipu, MEM_BG_SYNC))) {
+			int timeout = 50;
+
+			ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF),
+					IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF));
+			while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)) &
+						IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF)) == 0) {
+				msleep(10);
+				timeout -= 10;
+				if (timeout <= 0) {
+					dev_err(ipu->dev, "warning: wait for bg sync eof timeout\n");
+					break;
+				}
+			}
+		}
+	} else if (wait_for_stop) {
+		while (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma) ||
+		       idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma) ||
+			(ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
+			idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma)) ||
+			(ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
+			idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))) {
+			uint32_t irq = 0xffffffff;
+			int timeout = 50;
+
+			if (idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma))
+				irq = out_dma;
+			if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
+				idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma))
+				irq = sec_dma;
+			if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
+				idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))
+				irq = thrd_dma;
+			if (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma))
+				irq = in_dma;
+
+			if (irq == 0xffffffff) {
+				dev_dbg(ipu->dev, "warning: no channel busy, break\n");
+				break;
+			}
+
+			ipu_cm_write(ipu, IPUIRQ_2_MASK(irq),
+					IPUIRQ_2_STATREG(irq));
+
+			dev_dbg(ipu->dev, "warning: channel %d busy, need wait\n", irq);
+
+			while (((ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq))
+				& IPUIRQ_2_MASK(irq)) == 0) &&
+				(idma_is_set(ipu, IDMAC_CHA_BUSY, irq))) {
+				msleep(10);
+				timeout -= 10;
+				if (timeout <= 0) {
+					ipu_dump_registers(ipu);
+					dev_err(ipu->dev, "warning: disable ipu dma channel %d during its busy state\n", irq);
+					break;
+				}
+			}
+
+		}
+	}
+
+	if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
+	    (channel == MEM_DC_SYNC)) {
+		reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
+		ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
+	}
+
+	/* Disable IC task */
+	if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
+		_ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
+		_ipu_ic_disable_task(ipu, channel);
+
+	/* Disable DMA channel(s) */
+	if (idma_is_valid(in_dma)) {
+		reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
+		ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
+		ipu_cm_write(ipu, idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
+		ipu_cm_write(ipu, tri_cur_buf_mask(in_dma),
+					IPU_CHA_TRIPLE_CUR_BUF(in_dma));
+	}
+	if (idma_is_valid(out_dma)) {
+		reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
+		ipu_idmac_write(ipu, reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
+		ipu_cm_write(ipu, idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
+		ipu_cm_write(ipu, tri_cur_buf_mask(out_dma),
+					IPU_CHA_TRIPLE_CUR_BUF(out_dma));
+	}
+	if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
+		reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
+		ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
+		ipu_cm_write(ipu, idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma));
+	}
+	if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
+		reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
+		ipu_idmac_write(ipu, reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
+		if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) {
+			reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
+			ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA);
+		} else {
+			reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
+			ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA);
+		}
+		ipu_cm_write(ipu, idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma));
+	}
+
+	if (channel == MEM_FG_SYNC)
+		_ipu_disp_set_window_pos(ipu, channel, fg_pos_x, fg_pos_y);
+
+	/* Set channel buffers NOT to be ready */
+	if (idma_is_valid(in_dma)) {
+		_ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 0);
+		_ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 1);
+		_ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 2);
+	}
+	if (idma_is_valid(out_dma)) {
+		_ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 0);
+		_ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 1);
+	}
+	if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
+		_ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 0);
+		_ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 1);
+	}
+	if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
+		_ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 0);
+		_ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 1);
+	}
+
+	ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
+
+	_ipu_unlock(ipu);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disable_channel);
+
+/*!
+ * This function enables CSI.
+ *
+ * @param	ipu		ipu handler
+ * @param       csi	csi num 0 or 1
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi)
+{
+	uint32_t reg;
+
+	if (csi > 1) {
+		dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
+		return -EINVAL;
+	}
+
+	_ipu_lock(ipu);
+	ipu->csi_use_count[csi]++;
+
+	if (ipu->csi_use_count[csi] == 1) {
+		reg = ipu_cm_read(ipu, IPU_CONF);
+		if (csi == 0)
+			ipu_cm_write(ipu, reg | IPU_CONF_CSI0_EN, IPU_CONF);
+		else
+			ipu_cm_write(ipu, reg | IPU_CONF_CSI1_EN, IPU_CONF);
+	}
+	_ipu_unlock(ipu);
+	return 0;
+}
+EXPORT_SYMBOL(ipu_enable_csi);
+
+/*!
+ * This function disables CSI.
+ *
+ * @param	ipu		ipu handler
+ * @param       csi	csi num 0 or 1
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi)
+{
+	uint32_t reg;
+
+	if (csi > 1) {
+		dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
+		return -EINVAL;
+	}
+
+	_ipu_lock(ipu);
+	ipu->csi_use_count[csi]--;
+	if (ipu->csi_use_count[csi] == 0) {
+		reg = ipu_cm_read(ipu, IPU_CONF);
+		if (csi == 0)
+			ipu_cm_write(ipu, reg & ~IPU_CONF_CSI0_EN, IPU_CONF);
+		else
+			ipu_cm_write(ipu, reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
+	}
+	_ipu_unlock(ipu);
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disable_csi);
+
+static irqreturn_t ipu_irq_handler(int irq, void *desc)
+{
+	struct ipu_soc *ipu = desc;
+	int i;
+	uint32_t line;
+	irqreturn_t result = IRQ_NONE;
+	uint32_t int_stat;
+	const int err_reg[] = { 5, 6, 9, 10, 0 };
+	const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
+	unsigned long lock_flags;
+
+	for (i = 0;; i++) {
+		if (err_reg[i] == 0)
+			break;
+
+		spin_lock_irqsave(&ipu->spin_lock, lock_flags);
+
+		int_stat = ipu_cm_read(ipu, IPU_INT_STAT(err_reg[i]));
+		int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i]));
+		if (int_stat) {
+			ipu_cm_write(ipu, int_stat, IPU_INT_STAT(err_reg[i]));
+			dev_err(ipu->dev,
+				"IPU Error - IPU_INT_STAT_%d = 0x%08X\n",
+				err_reg[i], int_stat);
+			/* Disable interrupts so we only get error once */
+			int_stat =
+			    ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i])) & ~int_stat;
+			ipu_cm_write(ipu, int_stat, IPU_INT_CTRL(err_reg[i]));
+		}
+
+		spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+	}
+
+	for (i = 0;; i++) {
+		if (int_reg[i] == 0)
+			break;
+		spin_lock_irqsave(&ipu->spin_lock, lock_flags);
+		int_stat = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
+		int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
+		ipu_cm_write(ipu, int_stat, IPU_INT_STAT(int_reg[i]));
+		spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+		while ((line = ffs(int_stat)) != 0) {
+			line--;
+			int_stat &= ~(1UL << line);
+			line += (int_reg[i] - 1) * 32;
+			result |=
+			    ipu->irq_list[line].handler(line,
+						       ipu->irq_list[line].
+						       dev_id);
+		}
+	}
+
+	return result;
+}
+
+/*!
+ * This function enables the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param	ipu		ipu handler
+ * @param       irq             Interrupt line to enable interrupt for.
+ *
+ */
+void ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	_ipu_get(ipu);
+
+	spin_lock_irqsave(&ipu->spin_lock, lock_flags);
+
+	reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
+	reg |= IPUIRQ_2_MASK(irq);
+	ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
+
+	spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+
+	_ipu_put(ipu);
+}
+EXPORT_SYMBOL(ipu_enable_irq);
+
+/*!
+ * This function disables the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param	ipu		ipu handler
+ * @param       irq             Interrupt line to disable interrupt for.
+ *
+ */
+void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq)
+{
+	uint32_t reg;
+	unsigned long lock_flags;
+
+	_ipu_get(ipu);
+
+	spin_lock_irqsave(&ipu->spin_lock, lock_flags);
+
+	reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
+	reg &= ~IPUIRQ_2_MASK(irq);
+	ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
+
+	spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+
+	_ipu_put(ipu);
+}
+EXPORT_SYMBOL(ipu_disable_irq);
+
+/*!
+ * This function clears the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param	ipu		ipu handler
+ * @param       irq             Interrupt line to clear interrupt for.
+ *
+ */
+void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq)
+{
+	unsigned long lock_flags;
+
+	_ipu_get(ipu);
+
+	spin_lock_irqsave(&ipu->spin_lock, lock_flags);
+
+	ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
+
+	spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+
+	_ipu_put(ipu);
+}
+EXPORT_SYMBOL(ipu_clear_irq);
+
+/*!
+ * This function returns the current interrupt status for the specified
+ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param	ipu		ipu handler
+ * @param       irq             Interrupt line to get status for.
+ *
+ * @return      Returns true if the interrupt is pending/asserted or false if
+ *              the interrupt is not pending.
+ */
+bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq)
+{
+	uint32_t reg;
+
+	_ipu_get(ipu);
+
+	reg = ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq));
+
+	_ipu_put(ipu);
+
+	if (reg & IPUIRQ_2_MASK(irq))
+		return true;
+	else
+		return false;
+}
+EXPORT_SYMBOL(ipu_get_irq_status);
+
+/*!
+ * This function registers an interrupt handler function for the specified
+ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param	ipu		ipu handler
+ * @param       irq             Interrupt line to get status for.
+ *
+ * @param       handler         Input parameter for address of the handler
+ *                              function.
+ *
+ * @param       irq_flags       Flags for interrupt mode. Currently not used.
+ *
+ * @param       devname         Input parameter for string name of driver
+ *                              registering the handler.
+ *
+ * @param       dev_id          Input parameter for pointer of data to be
+ *                              passed to the handler.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
+		    irqreturn_t(*handler) (int, void *),
+		    uint32_t irq_flags, const char *devname, void *dev_id)
+{
+	unsigned long lock_flags;
+
+	BUG_ON(irq >= IPU_IRQ_COUNT);
+
+	_ipu_get(ipu);
+
+	spin_lock_irqsave(&ipu->spin_lock, lock_flags);
+
+	if (ipu->irq_list[irq].handler != NULL) {
+		dev_err(ipu->dev,
+			"handler already installed on irq %d\n", irq);
+		spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+		return -EINVAL;
+	}
+
+	ipu->irq_list[irq].handler = handler;
+	ipu->irq_list[irq].flags = irq_flags;
+	ipu->irq_list[irq].dev_id = dev_id;
+	ipu->irq_list[irq].name = devname;
+
+	/* clear irq stat for previous use */
+	ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
+
+	spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+
+	_ipu_put(ipu);
+
+	ipu_enable_irq(ipu, irq);	/* enable the interrupt */
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_request_irq);
+
+/*!
+ * This function unregisters an interrupt handler for the specified interrupt
+ * line. The interrupt lines are defined in \b ipu_irq_line enum.
+ *
+ * @param	ipu		ipu handler
+ * @param       irq             Interrupt line to get status for.
+ *
+ * @param       dev_id          Input parameter for pointer of data to be passed
+ *                              to the handler. This must match value passed to
+ *                              ipu_request_irq().
+ *
+ */
+void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id)
+{
+	unsigned long lock_flags;
+
+	ipu_disable_irq(ipu, irq);	/* disable the interrupt */
+
+	spin_lock_irqsave(&ipu->spin_lock, lock_flags);
+	if (ipu->irq_list[irq].dev_id == dev_id)
+		ipu->irq_list[irq].handler = NULL;
+	spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
+}
+EXPORT_SYMBOL(ipu_free_irq);
+
+uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type)
+{
+	uint32_t reg, dma_chan;
+
+	dma_chan = channel_2_dma(channel, type);
+	if (!idma_is_valid(dma_chan))
+		return -EINVAL;
+
+	reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
+	if ((reg & idma_mask(dma_chan)) && _ipu_is_trb_chan(dma_chan)) {
+		reg = ipu_cm_read(ipu, IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
+		return (reg & tri_cur_buf_mask(dma_chan)) >>
+				tri_cur_buf_shift(dma_chan);
+	} else {
+		reg = ipu_cm_read(ipu, IPU_CHA_CUR_BUF(dma_chan));
+		if (reg & idma_mask(dma_chan))
+			return 1;
+		else
+			return 0;
+	}
+}
+EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
+
+uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel)
+{
+	uint32_t stat = 0;
+	uint32_t task_stat_reg = ipu_cm_read(ipu, IPU_PROC_TASK_STAT);
+
+	switch (channel) {
+	case MEM_PRP_VF_MEM:
+		stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
+		break;
+	case MEM_ROT_VF_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
+		break;
+	case MEM_PRP_ENC_MEM:
+		stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
+		break;
+	case MEM_ROT_ENC_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
+		    TSTAT_ENC_ROT_OFFSET;
+		break;
+	case MEM_PP_MEM:
+		stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
+		break;
+	case MEM_ROT_PP_MEM:
+		stat =
+		    (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
+		break;
+
+	default:
+		stat = TASK_STAT_IDLE;
+		break;
+	}
+	return stat;
+}
+
+int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch)
+{
+	uint32_t reg;
+
+	int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER);
+	int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER);
+
+	_ipu_lock(ipu);
+
+	/* enable target channel */
+	reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(to_dma));
+	ipu_idmac_write(ipu, reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma));
+
+	ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch);
+
+	/* switch dp dc */
+	_ipu_dp_dc_disable(ipu, from_ch, true);
+
+	/* disable source channel */
+	reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(from_dma));
+	ipu_idmac_write(ipu, reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma));
+	ipu_cm_write(ipu, idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma));
+	ipu_cm_write(ipu, tri_cur_buf_mask(from_dma),
+				IPU_CHA_TRIPLE_CUR_BUF(from_dma));
+
+	ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch));
+
+	_ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 0);
+	_ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 1);
+	_ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 2);
+
+	_ipu_unlock(ipu);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_swap_channel);
+
+uint32_t bytes_per_pixel(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_GENERIC:	/*generic data */
+	case IPU_PIX_FMT_RGB332:
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_YUV422P:
+		return 1;
+		break;
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_YUYV:
+	case IPU_PIX_FMT_UYVY:
+		return 2;
+		break;
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+		return 3;
+		break;
+	case IPU_PIX_FMT_GENERIC_32:	/*generic data */
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_ABGR32:
+		return 4;
+		break;
+	default:
+		return 1;
+		break;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(bytes_per_pixel);
+
+ipu_color_space_t format_to_colorspace(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_RGB666:
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_GBR24:
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_ABGR32:
+	case IPU_PIX_FMT_LVDS666:
+	case IPU_PIX_FMT_LVDS888:
+		return RGB;
+		break;
+
+	default:
+		return YCbCr;
+		break;
+	}
+	return RGB;
+}
+
+bool ipu_pixel_format_has_alpha(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_ABGR32:
+		return true;
+		break;
+	default:
+		return false;
+		break;
+	}
+	return false;
+}
+
+static int ipu_suspend_noirq(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
+	struct ipu_soc *ipu = platform_get_drvdata(pdev);
+
+	if (atomic_read(&ipu->ipu_use_count)) {
+		/* save and disable enabled channels*/
+		ipu->idma_enable_reg[0] = ipu_idmac_read(ipu, IDMAC_CHA_EN(0));
+		ipu->idma_enable_reg[1] = ipu_idmac_read(ipu, IDMAC_CHA_EN(32));
+		while ((ipu_idmac_read(ipu, IDMAC_CHA_BUSY(0))
+			& ipu->idma_enable_reg[0])
+			|| (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(32))
+			& ipu->idma_enable_reg[1])) {
+			/* disable channel not busy already */
+			uint32_t chan_should_disable, timeout = 1000, time = 0;
+
+			chan_should_disable =
+				ipu_idmac_read(ipu, IDMAC_CHA_BUSY(0))
+					^ ipu->idma_enable_reg[0];
+			ipu_idmac_write(ipu, (~chan_should_disable) &
+					ipu->idma_enable_reg[0], IDMAC_CHA_EN(0));
+			chan_should_disable =
+				ipu_idmac_read(ipu, IDMAC_CHA_BUSY(1))
+					^ ipu->idma_enable_reg[1];
+			ipu_idmac_write(ipu, (~chan_should_disable) &
+					ipu->idma_enable_reg[1], IDMAC_CHA_EN(32));
+			msleep(2);
+			time += 2;
+			if (time >= timeout)
+				return -1;
+		}
+		ipu_idmac_write(ipu, 0, IDMAC_CHA_EN(0));
+		ipu_idmac_write(ipu, 0, IDMAC_CHA_EN(32));
+
+		/* save double buffer select regs */
+		ipu->cha_db_mode_reg[0] = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0));
+		ipu->cha_db_mode_reg[1] = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32));
+		ipu->cha_db_mode_reg[2] =
+			ipu_cm_read(ipu, IPU_ALT_CHA_DB_MODE_SEL(0));
+		ipu->cha_db_mode_reg[3] =
+			ipu_cm_read(ipu, IPU_ALT_CHA_DB_MODE_SEL(32));
+
+		/* save triple buffer select regs */
+		ipu->cha_trb_mode_reg[0] = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(0));
+		ipu->cha_trb_mode_reg[1] = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(32));
+
+		/* save idamc sub addr regs */
+		ipu->idma_sub_addr_reg[0] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_0);
+		ipu->idma_sub_addr_reg[1] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_1);
+		ipu->idma_sub_addr_reg[2] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_2);
+		ipu->idma_sub_addr_reg[3] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_3);
+		ipu->idma_sub_addr_reg[4] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_4);
+
+		/* save sub-modules status and disable all */
+		ipu->ic_conf_reg = ipu_ic_read(ipu, IC_CONF);
+		ipu_ic_write(ipu, 0, IC_CONF);
+		ipu->ipu_conf_reg = ipu_cm_read(ipu, IPU_CONF);
+		ipu_cm_write(ipu, 0, IPU_CONF);
+
+		/* save buf ready regs */
+		ipu->buf_ready_reg[0] = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(0));
+		ipu->buf_ready_reg[1] = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(32));
+		ipu->buf_ready_reg[2] = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(0));
+		ipu->buf_ready_reg[3] = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(32));
+		ipu->buf_ready_reg[4] = ipu_cm_read(ipu, IPU_ALT_CHA_BUF0_RDY(0));
+		ipu->buf_ready_reg[5] = ipu_cm_read(ipu, IPU_ALT_CHA_BUF0_RDY(32));
+		ipu->buf_ready_reg[6] = ipu_cm_read(ipu, IPU_ALT_CHA_BUF1_RDY(0));
+		ipu->buf_ready_reg[7] = ipu_cm_read(ipu, IPU_ALT_CHA_BUF1_RDY(32));
+		ipu->buf_ready_reg[8] = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(0));
+		ipu->buf_ready_reg[9] = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(32));
+
+		clk_disable(ipu->ipu_clk);
+	}
+
+	if (plat_data->pg)
+		plat_data->pg(1);
+
+	return 0;
+}
+
+static int ipu_resume_noirq(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
+	struct ipu_soc *ipu = platform_get_drvdata(pdev);
+
+	if (plat_data->pg)
+		plat_data->pg(0);
+
+	if (atomic_read(&ipu->ipu_use_count)) {
+		clk_enable(ipu->ipu_clk);
+
+		/* restore buf ready regs */
+		ipu_cm_write(ipu, ipu->buf_ready_reg[0], IPU_CHA_BUF0_RDY(0));
+		ipu_cm_write(ipu, ipu->buf_ready_reg[1], IPU_CHA_BUF0_RDY(32));
+		ipu_cm_write(ipu, ipu->buf_ready_reg[2], IPU_CHA_BUF1_RDY(0));
+		ipu_cm_write(ipu, ipu->buf_ready_reg[3], IPU_CHA_BUF1_RDY(32));
+		ipu_cm_write(ipu, ipu->buf_ready_reg[4], IPU_ALT_CHA_BUF0_RDY(0));
+		ipu_cm_write(ipu, ipu->buf_ready_reg[5], IPU_ALT_CHA_BUF0_RDY(32));
+		ipu_cm_write(ipu, ipu->buf_ready_reg[6], IPU_ALT_CHA_BUF1_RDY(0));
+		ipu_cm_write(ipu, ipu->buf_ready_reg[7], IPU_ALT_CHA_BUF1_RDY(32));
+		ipu_cm_write(ipu, ipu->buf_ready_reg[8], IPU_CHA_BUF2_RDY(0));
+		ipu_cm_write(ipu, ipu->buf_ready_reg[9], IPU_CHA_BUF2_RDY(32));
+
+		/* re-enable sub-modules*/
+		ipu_cm_write(ipu, ipu->ipu_conf_reg, IPU_CONF);
+		ipu_ic_write(ipu, ipu->ic_conf_reg, IC_CONF);
+
+		/* restore double buffer select regs */
+		ipu_cm_write(ipu, ipu->cha_db_mode_reg[0], IPU_CHA_DB_MODE_SEL(0));
+		ipu_cm_write(ipu, ipu->cha_db_mode_reg[1], IPU_CHA_DB_MODE_SEL(32));
+		ipu_cm_write(ipu, ipu->cha_db_mode_reg[2],
+				IPU_ALT_CHA_DB_MODE_SEL(0));
+		ipu_cm_write(ipu, ipu->cha_db_mode_reg[3],
+				IPU_ALT_CHA_DB_MODE_SEL(32));
+
+		/* restore triple buffer select regs */
+		ipu_cm_write(ipu, ipu->cha_trb_mode_reg[0], IPU_CHA_TRB_MODE_SEL(0));
+		ipu_cm_write(ipu, ipu->cha_trb_mode_reg[1], IPU_CHA_TRB_MODE_SEL(32));
+
+		/* restore idamc sub addr regs */
+		ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[0], IDMAC_SUB_ADDR_0);
+		ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[1], IDMAC_SUB_ADDR_1);
+		ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[2], IDMAC_SUB_ADDR_2);
+		ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[3], IDMAC_SUB_ADDR_3);
+		ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[4], IDMAC_SUB_ADDR_4);
+
+		/* restart idma channel*/
+		ipu_idmac_write(ipu, ipu->idma_enable_reg[0], IDMAC_CHA_EN(0));
+		ipu_idmac_write(ipu, ipu->idma_enable_reg[1], IDMAC_CHA_EN(32));
+	} else {
+		_ipu_get(ipu);
+		_ipu_dmfc_init(ipu, dmfc_type_setup, 1);
+		_ipu_init_dc_mappings(ipu);
+		/* Set sync refresh channels as high priority */
+		ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
+		_ipu_put(ipu);
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops mxcipu_pm_ops = {
+	.suspend_noirq = ipu_suspend_noirq,
+	.resume_noirq = ipu_resume_noirq,
+};
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcipu_driver = {
+	.driver = {
+		   .name = "imx-ipuv3",
+		   .pm = &mxcipu_pm_ops,
+		   },
+	.probe = ipu_probe,
+	.remove = ipu_remove,
+};
+
+int32_t __init ipu_gen_init(void)
+{
+	int32_t ret;
+
+	ret = platform_driver_register(&mxcipu_driver);
+	return 0;
+}
+
+subsys_initcall(ipu_gen_init);
+
+static void __exit ipu_gen_uninit(void)
+{
+	platform_driver_unregister(&mxcipu_driver);
+}
+
+module_exit(ipu_gen_uninit);
diff --git a/drivers/mxc/ipu3/ipu_device.c b/drivers/mxc/ipu3/ipu_device.c
new file mode 100644
index 00000000000..e9c55abcfc8
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_device.c
@@ -0,0 +1,2326 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_device.c
+ *
+ * @brief This file contains the IPUv3 driver device interface and fops functions.
+ *
+ * @ingroup IPU
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/kthread.h>
+#include <linux/vmalloc.h>
+#include <mach/ipu-v3.h>
+#include <asm/outercache.h>
+#include <asm/cacheflush.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+/* Strucutures and variables for exporting MXC IPU as device*/
+typedef enum {
+	STATE_OK = 0,
+	STATE_NO_IPU,
+	STATE_NO_IRQ,
+	STATE_IRQ_FAIL,
+	STATE_IRQ_TIMEOUT,
+	STATE_INIT_CHAN_FAIL,
+	STATE_LINK_CHAN_FAIL,
+	STATE_INIT_CHAN_BUF_FAIL,
+} ipu_state_t;
+
+struct ipu_state_msg {
+	int state;
+	char *msg;
+} state_msg[] = {
+	{STATE_OK, "ok"},
+	{STATE_NO_IPU, "no ipu found"},
+	{STATE_NO_IRQ, "no irq found for task"},
+	{STATE_IRQ_FAIL, "request irq failed"},
+	{STATE_IRQ_TIMEOUT, "wait for irq timeout"},
+	{STATE_INIT_CHAN_FAIL, "ipu init channel fail"},
+	{STATE_LINK_CHAN_FAIL, "ipu link channel fail"},
+	{STATE_INIT_CHAN_BUF_FAIL, "ipu init channel buffer fail"},
+};
+
+struct stripe_setting {
+	u32 iw;
+	u32 ih;
+	u32 ow;
+	u32 oh;
+	u32 outh_resize_ratio;
+	u32 outv_resize_ratio;
+	u32 i_left_pos;
+	u32 i_right_pos;
+	u32 i_top_pos;
+	u32 i_bottom_pos;
+	u32 o_left_pos;
+	u32 o_right_pos;
+	u32 o_top_pos;
+	u32 o_bottom_pos;
+	u32 rl_split_line;
+	u32 ud_split_line;
+};
+
+struct task_set {
+#define	NULL_MODE	0x0
+#define	IC_MODE		0x1
+#define	ROT_MODE	0x2
+#define	VDI_MODE	0x4
+	u8	mode;
+#define IC_VF	0x1
+#define IC_PP	0x2
+#define ROT_VF	0x4
+#define ROT_PP	0x8
+#define VDI_VF	0x10
+	u8	task;
+
+	ipu_channel_t ic_chan;
+	ipu_channel_t rot_chan;
+	ipu_channel_t vdi_ic_p_chan;
+	ipu_channel_t vdi_ic_n_chan;
+
+	u32 i_off;
+	u32 i_uoff;
+	u32 i_voff;
+	u32 istride;
+
+	u32 ov_off;
+	u32 ov_uoff;
+	u32 ov_voff;
+	u32 ovstride;
+
+	u32 ov_alpha_off;
+	u32 ov_alpha_stride;
+
+	u32 o_off;
+	u32 o_uoff;
+	u32 o_voff;
+	u32 ostride;
+
+	u32 r_fmt;
+	u32 r_width;
+	u32 r_height;
+	u32 r_stride;
+	dma_addr_t r_paddr;
+
+#define NO_SPLIT	0x0
+#define RL_SPLIT	0x1
+#define UD_SPLIT	0x2
+#define LEFT_STRIPE	0x1
+#define RIGHT_STRIPE	0x2
+#define UP_STRIPE	0x4
+#define DOWN_STRIPE	0x8
+	u8 split_mode;
+	struct stripe_setting sp_setting;
+};
+
+struct ipu_split_task {
+	struct ipu_task task;
+	struct ipu_task_entry *parent_task;
+	struct task_struct *thread;
+	volatile bool could_finish;
+	wait_queue_head_t waitq;
+	int ret;
+
+	u32 task_no;
+};
+
+struct ipu_task_entry {
+	struct ipu_input input;
+	struct ipu_output output;
+
+	bool overlay_en;
+	struct ipu_overlay overlay;
+
+	u8	priority;
+	u8	task_id;
+#define DEF_TIMEOUT_MS	1000
+	int	timeout;
+
+	struct list_head node;
+	struct device *dev;
+	struct task_set set;
+	struct completion comp;
+	ipu_state_t state;
+
+	u32 task_no;
+};
+struct ipu_alloc_list {
+	struct list_head list;
+	dma_addr_t phy_addr;
+	void *cpu_addr;
+	u32 size;
+};
+LIST_HEAD(ipu_alloc_list);
+
+static int major;
+static u32 frame_no;
+static struct class *ipu_class;
+static struct device *ipu_dev;
+static char *vditmpbuf[2];
+static bool buf1filled, buf0filled;
+static u32 old_save_lines, old_size;
+int ipu_queue_sp_task(struct ipu_split_task *sp_task);
+
+static bool deinterlace_3_field(struct ipu_task_entry *t)
+{
+	return ((t->set.mode & VDI_MODE) &&
+		(t->input.deinterlace.motion != HIGH_MOTION));
+}
+
+unsigned int fmt_to_bpp(unsigned int pixelformat)
+{
+	u32 bpp;
+
+	switch (pixelformat) {
+	case IPU_PIX_FMT_RGB565:
+	/*interleaved 422*/
+	case IPU_PIX_FMT_YUYV:
+	case IPU_PIX_FMT_UYVY:
+	/*non-interleaved 422*/
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YVU422P:
+		bpp = 16;
+		break;
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_YUV444:
+		bpp = 24;
+		break;
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_ABGR32:
+		bpp = 32;
+		break;
+	/*non-interleaved 420*/
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_NV12:
+		bpp = 12;
+		break;
+	default:
+		bpp = 8;
+		break;
+	}
+	return bpp;
+}
+EXPORT_SYMBOL_GPL(fmt_to_bpp);
+
+cs_t colorspaceofpixel(int fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_ABGR32:
+		return RGB_CS;
+		break;
+	case IPU_PIX_FMT_UYVY:
+	case IPU_PIX_FMT_YUYV:
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YUV444:
+	case IPU_PIX_FMT_NV12:
+		return YUV_CS;
+		break;
+	default:
+		return NULL_CS;
+	}
+}
+EXPORT_SYMBOL_GPL(colorspaceofpixel);
+
+int need_csc(int ifmt, int ofmt)
+{
+	cs_t ics, ocs;
+
+	ics = colorspaceofpixel(ifmt);
+	ocs = colorspaceofpixel(ofmt);
+
+	if ((ics == NULL_CS) || (ocs == NULL_CS))
+		return -1;
+	else if (ics != ocs)
+		return 1;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(need_csc);
+
+static int soc_max_in_width(void)
+{
+	return 4096;
+}
+
+static int soc_max_in_height(void)
+{
+	return 4096;
+}
+
+static int soc_max_out_width(void)
+{
+	/* mx51/mx53/mx6q is 1024*/
+	return 1024;
+}
+
+static int soc_max_out_height(void)
+{
+	/* mx51/mx53/mx6q is 1024*/
+	return 1024;
+}
+
+static int list_size(struct list_head *head)
+{
+	struct list_head *p, *n;
+	int size = 0;
+
+	list_for_each_safe(p, n, head)
+		size++;
+
+	return size;
+}
+
+static int get_task_size(struct ipu_soc *ipu, int id)
+{
+	struct list_head *task_list;
+
+	if (id == IPU_TASK_ID_VF)
+		task_list = &ipu->task_list[0];
+	else if (id == IPU_TASK_ID_PP)
+		task_list = &ipu->task_list[1];
+	else {
+		printk(KERN_ERR "query error task id\n");
+		return -EINVAL;
+	}
+
+	return list_size(task_list);
+}
+
+static struct ipu_soc *most_free_ipu_task(struct ipu_task_entry *t)
+{
+	unsigned int task_num[2][2] = {
+		{0xffffffff, 0xffffffff},
+		{0xffffffff, 0xffffffff} };
+	struct ipu_soc *ipu;
+	int ipu_idx, task_id;
+	int i;
+
+	/* decide task_id */
+	if (t->task_id >= IPU_TASK_ID_MAX)
+		t->task_id %= IPU_TASK_ID_MAX;
+	/* must use task_id VF for VDI task*/
+	if ((t->set.mode & VDI_MODE) &&
+		(t->task_id != IPU_TASK_ID_VF))
+		t->task_id = IPU_TASK_ID_VF;
+
+	for (i = 0; i < MXC_IPU_MAX_NUM; i++) {
+		ipu = ipu_get_soc(i);
+		if (!IS_ERR(ipu)) {
+			task_num[i][0] = get_task_size(ipu, IPU_TASK_ID_VF);
+			task_num[i][1] = get_task_size(ipu, IPU_TASK_ID_PP);
+		}
+	}
+
+	task_id = t->task_id;
+	if (t->task_id == IPU_TASK_ID_VF) {
+		if (task_num[0][0] < task_num[1][0])
+			ipu_idx = 0;
+		else
+			ipu_idx = 1;
+	} else if (t->task_id == IPU_TASK_ID_PP) {
+		if (task_num[0][1] < task_num[1][1])
+			ipu_idx = 0;
+		else
+			ipu_idx = 1;
+	} else {
+		unsigned int min;
+		ipu_idx = 0;
+		task_id = IPU_TASK_ID_VF;
+		min = task_num[0][0];
+		if (task_num[0][1] < min) {
+			min = task_num[0][1];
+			task_id = IPU_TASK_ID_PP;
+		}
+		if (task_num[1][0] < min) {
+			min = task_num[1][0];
+			ipu_idx = 1;
+			task_id = IPU_TASK_ID_VF;
+		}
+		if (task_num[1][1] < min) {
+			ipu_idx = 1;
+			task_id = IPU_TASK_ID_PP;
+		}
+	}
+
+	t->task_id = task_id;
+	ipu = ipu_get_soc(ipu_idx);
+
+	return ipu;
+}
+
+static void dump_task_info(struct ipu_task_entry *t)
+{
+	dev_dbg(t->dev, "[0x%p]input:\n", (void *)t);
+	dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->input.format);
+	dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->input.width);
+	dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->input.height);
+	dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n", (void *)t, t->input.crop.w);
+	dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n", (void *)t, t->input.crop.h);
+	dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
+			(void *)t, t->input.crop.pos.x);
+	dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
+			(void *)t, t->input.crop.pos.y);
+	dev_dbg(t->dev, "[0x%p]input buffer:\n", (void *)t);
+	dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->input.paddr);
+	dev_dbg(t->dev, "[0x%p]\ti_off = 0x%x\n", (void *)t, t->set.i_off);
+	dev_dbg(t->dev, "[0x%p]\ti_uoff = 0x%x\n", (void *)t, t->set.i_uoff);
+	dev_dbg(t->dev, "[0x%p]\ti_voff = 0x%x\n", (void *)t, t->set.i_voff);
+	dev_dbg(t->dev, "[0x%p]\tistride = %d\n", (void *)t, t->set.istride);
+	if (t->input.deinterlace.enable) {
+		dev_dbg(t->dev, "[0x%p]deinterlace enabled with:\n", (void *)t);
+		if (t->input.deinterlace.motion != HIGH_MOTION) {
+			dev_dbg(t->dev, "[0x%p]\tlow/medium motion\n", (void *)t);
+			dev_dbg(t->dev, "[0x%p]\tpaddr_n = 0x%x\n",
+				(void *)t, t->input.paddr_n);
+		} else
+			dev_dbg(t->dev, "[0x%p]\thigh motion\n", (void *)t);
+	}
+
+	dev_dbg(t->dev, "[0x%p]output:\n", (void *)t);
+	dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->output.format);
+	dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->output.width);
+	dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->output.height);
+	dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n", (void *)t, t->output.crop.w);
+	dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n", (void *)t, t->output.crop.h);
+	dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
+			(void *)t, t->output.crop.pos.x);
+	dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
+			(void *)t, t->output.crop.pos.y);
+	dev_dbg(t->dev, "[0x%p]\trotate = %d\n", (void *)t, t->output.rotate);
+	dev_dbg(t->dev, "[0x%p]output buffer:\n", (void *)t);
+	dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->output.paddr);
+	dev_dbg(t->dev, "[0x%p]\to_off = 0x%x\n", (void *)t, t->set.o_off);
+	dev_dbg(t->dev, "[0x%p]\to_uoff = 0x%x\n", (void *)t, t->set.o_uoff);
+	dev_dbg(t->dev, "[0x%p]\to_voff = 0x%x\n", (void *)t, t->set.o_voff);
+	dev_dbg(t->dev, "[0x%p]\tostride = %d\n", (void *)t, t->set.ostride);
+
+	if (t->overlay_en) {
+		dev_dbg(t->dev, "[0x%p]overlay:\n", (void *)t);
+		dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n",
+				(void *)t, t->overlay.format);
+		dev_dbg(t->dev, "[0x%p]\twidth = %d\n",
+				(void *)t, t->overlay.width);
+		dev_dbg(t->dev, "[0x%p]\theight = %d\n",
+				(void *)t, t->overlay.height);
+		dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n",
+				(void *)t, t->overlay.crop.w);
+		dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n",
+				(void *)t, t->overlay.crop.h);
+		dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
+				(void *)t, t->overlay.crop.pos.x);
+		dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
+				(void *)t, t->overlay.crop.pos.y);
+		dev_dbg(t->dev, "[0x%p]overlay buffer:\n", (void *)t);
+		dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n",
+				(void *)t, t->overlay.paddr);
+		dev_dbg(t->dev, "[0x%p]\tov_off = 0x%x\n",
+				(void *)t, t->set.ov_off);
+		dev_dbg(t->dev, "[0x%p]\tov_uoff = 0x%x\n",
+				(void *)t, t->set.ov_uoff);
+		dev_dbg(t->dev, "[0x%p]\tov_voff = 0x%x\n",
+				(void *)t, t->set.ov_voff);
+		dev_dbg(t->dev, "[0x%p]\tovstride = %d\n",
+				(void *)t, t->set.ovstride);
+		if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
+			dev_dbg(t->dev, "[0x%p]local alpha enabled with:\n",
+					(void *)t);
+			dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n",
+					(void *)t, t->overlay.alpha.loc_alp_paddr);
+			dev_dbg(t->dev, "[0x%p]\tov_alpha_off = 0x%x\n",
+					(void *)t, t->set.ov_alpha_off);
+			dev_dbg(t->dev, "[0x%p]\tov_alpha_stride = %d\n",
+					(void *)t, t->set.ov_alpha_stride);
+		} else
+			dev_dbg(t->dev, "[0x%p]globle alpha enabled with value 0x%x\n",
+					(void *)t, t->overlay.alpha.gvalue);
+		if (t->overlay.colorkey.enable)
+			dev_dbg(t->dev, "[0x%p]colorkey enabled with value 0x%x\n",
+					(void *)t, t->overlay.colorkey.value);
+	}
+
+	dev_dbg(t->dev, "[0x%p]want task_id = %d\n", (void *)t, t->task_id);
+	dev_dbg(t->dev, "[0x%p]want task mode is 0x%x\n",
+				(void *)t, t->set.mode);
+	dev_dbg(t->dev, "[0x%p]\tIC_MODE = 0x%x\n", (void *)t, IC_MODE);
+	dev_dbg(t->dev, "[0x%p]\tROT_MODE = 0x%x\n", (void *)t, ROT_MODE);
+	dev_dbg(t->dev, "[0x%p]\tVDI_MODE = 0x%x\n", (void *)t, VDI_MODE);
+	dev_dbg(t->dev, "[0x%p]\tTask_no = 0x%x\n\n\n", (void *)t, t->task_no);
+}
+
+static void dump_check_err(struct device *dev, int err)
+{
+	switch (err) {
+	case IPU_CHECK_ERR_INPUT_CROP:
+		dev_err(dev, "input crop setting error\n");
+		break;
+	case IPU_CHECK_ERR_OUTPUT_CROP:
+		dev_err(dev, "output crop setting error\n");
+		break;
+	case IPU_CHECK_ERR_OVERLAY_CROP:
+		dev_err(dev, "overlay crop setting error\n");
+		break;
+	case IPU_CHECK_ERR_INPUT_OVER_LIMIT:
+		dev_err(dev, "input over limitation\n");
+		break;
+	case IPU_CHECK_ERR_OVERLAY_WITH_VDI:
+		dev_err(dev, "do not support overlay with deinterlace\n");
+		break;
+	case IPU_CHECK_ERR_OV_OUT_NO_FIT:
+		dev_err(dev,
+			"width/height of overlay and ic output should be same\n");
+		break;
+	case IPU_CHECK_ERR_PROC_NO_NEED:
+		dev_err(dev, "no ipu processing need\n");
+		break;
+	case IPU_CHECK_ERR_SPLIT_INPUTW_OVER:
+		dev_err(dev, "split mode input width overflow\n");
+		break;
+	case IPU_CHECK_ERR_SPLIT_INPUTH_OVER:
+		dev_err(dev, "split mode input height overflow\n");
+		break;
+	case IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER:
+		dev_err(dev, "split mode output width overflow\n");
+		break;
+	case IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER:
+		dev_err(dev, "split mode output height overflow\n");
+		break;
+	case IPU_CHECK_ERR_SPLIT_WITH_ROT:
+		dev_err(dev, "not support split mode with rotation\n");
+		break;
+	default:
+		break;
+	}
+}
+
+static void dump_check_warn(struct device *dev, int warn)
+{
+	if (warn & IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN)
+		dev_warn(dev, "input u/v offset not 8 align\n");
+	if (warn & IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN)
+		dev_warn(dev, "output u/v offset not 8 align\n");
+	if (warn & IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN)
+		dev_warn(dev, "overlay u/v offset not 8 align\n");
+}
+
+static int set_crop(struct ipu_crop *crop, int width, int height)
+{
+	if (crop->w || crop->h) {
+		if (((crop->w + crop->pos.x) > width)
+		|| ((crop->h + crop->pos.y) > height))
+			return -EINVAL;
+	} else {
+		crop->pos.x = 0;
+		crop->pos.y = 0;
+		crop->w = width;
+		crop->h = height;
+	}
+	crop->w -= crop->w%8;
+	crop->h -= crop->h%8;
+
+	return 0;
+}
+
+static void update_offset(unsigned int fmt,
+				unsigned int width, unsigned int height,
+				unsigned int pos_x, unsigned int pos_y,
+				int *off, int *uoff, int *voff, int *stride)
+{
+	/* NOTE: u v offset should based on start point of off*/
+	switch (fmt) {
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+		*off = pos_y * width + pos_x;
+		*uoff = (width * (height - pos_y) - pos_x)
+			+ ((width/2 * pos_y/2) + pos_x/2);
+		*voff = *uoff + (width/2 * height/2);
+		break;
+	case IPU_PIX_FMT_YVU420P:
+		*off = pos_y * width + pos_x;
+		*voff = (width * (height - pos_y) - pos_x)
+			+ ((width/2 * pos_y/2) + pos_x/2);
+		*uoff = *voff + (width/2 * height/2);
+		break;
+	case IPU_PIX_FMT_YVU422P:
+		*off = pos_y * width + pos_x;
+		*voff = (width * (height - pos_y) - pos_x)
+			+ ((width * pos_y)/2 + pos_x/2);
+		*uoff = *voff + (width * height)/2;
+		break;
+	case IPU_PIX_FMT_YUV422P:
+		*off = pos_y * width + pos_x;
+		*uoff = (width * (height - pos_y) - pos_x)
+			+ (width * pos_y)/2 + pos_x/2;
+		*voff = *uoff + (width * height)/2;
+		break;
+	case IPU_PIX_FMT_NV12:
+		*off = pos_y * width + pos_x;
+		*uoff = (width * (height - pos_y) - pos_x)
+			+ width * pos_y/2 + pos_x;
+		break;
+	default:
+		*off = (pos_y * width + pos_x) * fmt_to_bpp(fmt)/8;
+		break;
+	}
+	*stride = width * bytes_per_pixel(fmt);
+}
+
+static int update_split_setting(struct ipu_task_entry *t)
+{
+	struct stripe_param left_stripe;
+	struct stripe_param right_stripe;
+	struct stripe_param up_stripe;
+	struct stripe_param down_stripe;
+	u32 iw, ih, ow, oh;
+
+	if (t->output.rotate >= IPU_ROTATE_90_RIGHT)
+		return IPU_CHECK_ERR_SPLIT_WITH_ROT;
+
+	iw = t->input.crop.w;
+	ih = t->input.crop.h;
+
+	ow = t->output.crop.w;
+	oh = t->output.crop.h;
+
+	if (t->set.split_mode & RL_SPLIT) {
+		ipu_calc_stripes_sizes(iw,
+				ow,
+				soc_max_out_width(),
+				(((unsigned long long)1) << 32), /* 32bit for fractional*/
+				1, /* equal stripes */
+				t->input.format,
+				t->output.format,
+				&left_stripe,
+				&right_stripe);
+		t->set.sp_setting.iw = left_stripe.input_width;
+		t->set.sp_setting.ow = left_stripe.output_width;
+		t->set.sp_setting.outh_resize_ratio = left_stripe.irr;
+		t->set.sp_setting.i_left_pos = left_stripe.input_column;
+		t->set.sp_setting.o_left_pos = left_stripe.output_column;
+		t->set.sp_setting.i_right_pos = right_stripe.input_column;
+		t->set.sp_setting.o_right_pos = right_stripe.output_column;
+	} else {
+		t->set.sp_setting.iw = iw;
+		t->set.sp_setting.ow = ow;
+		t->set.sp_setting.outh_resize_ratio = 0;
+		t->set.sp_setting.i_left_pos = 0;
+		t->set.sp_setting.o_left_pos = 0;
+		t->set.sp_setting.i_right_pos = 0;
+		t->set.sp_setting.o_right_pos = 0;
+	}
+	if ((t->set.sp_setting.iw + t->set.sp_setting.i_right_pos) > iw)
+		return IPU_CHECK_ERR_SPLIT_INPUTW_OVER;
+	if (((t->set.sp_setting.ow + t->set.sp_setting.o_right_pos) > ow)
+		|| (t->set.sp_setting.ow > soc_max_out_width()))
+		return IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER;
+
+	if (t->set.split_mode & UD_SPLIT) {
+		ipu_calc_stripes_sizes(ih,
+				oh,
+				soc_max_out_height(),
+				(((unsigned long long)1) << 32), /* 32bit for fractional*/
+				1, /* equal stripes */
+				t->input.format,
+				t->output.format,
+				&up_stripe,
+				&down_stripe);
+		t->set.sp_setting.ih = up_stripe.input_width;
+		t->set.sp_setting.oh = up_stripe.output_width;
+		t->set.sp_setting.outv_resize_ratio = up_stripe.irr;
+		t->set.sp_setting.i_top_pos = up_stripe.input_column;
+		t->set.sp_setting.o_top_pos = up_stripe.output_column;
+		t->set.sp_setting.i_bottom_pos = down_stripe.input_column;
+		t->set.sp_setting.o_bottom_pos = down_stripe.output_column;
+	} else {
+		t->set.sp_setting.ih = ih;
+		t->set.sp_setting.oh = oh;
+		t->set.sp_setting.outv_resize_ratio = 0;
+		t->set.sp_setting.i_top_pos = 0;
+		t->set.sp_setting.o_top_pos = 0;
+		t->set.sp_setting.i_bottom_pos = 0;
+		t->set.sp_setting.o_bottom_pos = 0;
+	}
+	if ((t->set.sp_setting.ih + t->set.sp_setting.i_bottom_pos) > ih)
+		return IPU_CHECK_ERR_SPLIT_INPUTH_OVER;
+	if (((t->set.sp_setting.oh + t->set.sp_setting.o_bottom_pos) > oh)
+		|| (t->set.sp_setting.oh > soc_max_out_height()))
+		return IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER;
+
+	return IPU_CHECK_OK;
+}
+
+static int check_task(struct ipu_task_entry *t)
+{
+	int tmp;
+	int ret = IPU_CHECK_OK;
+
+	/* check input */
+	ret = set_crop(&t->input.crop, t->input.width, t->input.height);
+	if (ret < 0) {
+		ret = IPU_CHECK_ERR_INPUT_CROP;
+		goto done;
+	} else
+		update_offset(t->input.format, t->input.width, t->input.height,
+				t->input.crop.pos.x, t->input.crop.pos.y,
+				&t->set.i_off, &t->set.i_uoff,
+				&t->set.i_voff, &t->set.istride);
+
+	/* check output */
+	ret = set_crop(&t->output.crop, t->output.width, t->output.height);
+	if (ret < 0) {
+		ret = IPU_CHECK_ERR_OUTPUT_CROP;
+		goto done;
+	} else
+		update_offset(t->output.format,
+				t->output.width, t->output.height,
+				t->output.crop.pos.x, t->output.crop.pos.y,
+				&t->set.o_off, &t->set.o_uoff,
+				&t->set.o_voff, &t->set.ostride);
+
+	/* check overlay if there is */
+	if (t->overlay_en) {
+		if (t->input.deinterlace.enable) {
+			ret = IPU_CHECK_ERR_OVERLAY_WITH_VDI;
+			goto done;
+		}
+		ret = set_crop(&t->overlay.crop, t->overlay.width, t->overlay.height);
+		if (ret < 0) {
+			ret = IPU_CHECK_ERR_OVERLAY_CROP;
+			goto done;
+		} else {
+			int ow = t->output.crop.w;
+			int oh = t->output.crop.h;
+
+			if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
+				ow = t->output.crop.h;
+				oh = t->output.crop.w;
+			}
+			if ((t->overlay.crop.w != ow) || (t->overlay.crop.h != oh)) {
+				ret = IPU_CHECK_ERR_OV_OUT_NO_FIT;
+				goto done;
+			}
+
+			update_offset(t->overlay.format,
+					t->overlay.width, t->overlay.height,
+					t->overlay.crop.pos.x, t->overlay.crop.pos.y,
+					&t->set.ov_off, &t->set.ov_uoff,
+					&t->set.ov_voff, &t->set.ovstride);
+			if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
+				t->set.ov_alpha_stride = t->overlay.width;
+				t->set.ov_alpha_off = t->overlay.crop.pos.y *
+					t->overlay.width + t->overlay.crop.pos.x;
+			}
+		}
+	}
+
+	/* input overflow? */
+	if ((t->input.crop.w > soc_max_in_width()) ||
+		(t->input.crop.h > soc_max_in_height())) {
+		ret = IPU_CHECK_ERR_INPUT_OVER_LIMIT;
+		goto done;
+	}
+
+	/* check task mode */
+	t->set.mode = NULL_MODE;
+	t->set.split_mode = NO_SPLIT;
+
+	if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
+		/*output swap*/
+		tmp = t->output.crop.w;
+		t->output.crop.w = t->output.crop.h;
+		t->output.crop.h = tmp;
+	}
+
+	if (t->output.rotate >= IPU_ROTATE_90_RIGHT)
+		t->set.mode |= ROT_MODE;
+
+	/*need resize or CSC?*/
+	if ((t->input.crop.w != t->output.crop.w) ||
+			(t->input.crop.h != t->output.crop.h) ||
+			need_csc(t->input.format, t->output.format))
+		t->set.mode |= IC_MODE;
+
+	/*need flip?*/
+	if ((t->set.mode == NULL_MODE) && (t->output.rotate > IPU_ROTATE_NONE))
+		t->set.mode |= IC_MODE;
+
+	/*need IDMAC do format(same color space)?*/
+	if ((t->set.mode == NULL_MODE) && (t->input.format != t->output.format))
+		t->set.mode |= IC_MODE;
+
+	/*overlay support*/
+	if (t->overlay_en)
+		t->set.mode |= IC_MODE;
+
+	/*deinterlace*/
+	if (t->input.deinterlace.enable) {
+		t->set.mode &= ~IC_MODE;
+		t->set.mode |= VDI_MODE;
+	}
+
+	if (t->set.mode & (IC_MODE | VDI_MODE)) {
+		if (t->output.crop.w > soc_max_out_width())
+			t->set.split_mode |= RL_SPLIT;
+		if (t->output.crop.h > soc_max_out_height())
+			t->set.split_mode |= UD_SPLIT;
+		if (t->set.split_mode) {
+			ret = update_split_setting(t);
+			if (ret > IPU_CHECK_ERR_MIN)
+				goto done;
+		}
+	}
+
+	if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
+		/*output swap*/
+		tmp = t->output.crop.w;
+		t->output.crop.w = t->output.crop.h;
+		t->output.crop.h = tmp;
+	}
+
+	if (t->set.mode == NULL_MODE) {
+		ret = IPU_CHECK_ERR_PROC_NO_NEED;
+		goto done;
+	}
+
+	if ((t->set.i_uoff % 8) || (t->set.i_voff % 8))
+		ret |= IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN;
+	if ((t->set.o_uoff % 8) || (t->set.o_voff % 8))
+		ret |= IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN;
+	if (t->overlay_en && ((t->set.ov_uoff % 8) || (t->set.ov_voff % 8)))
+		ret |= IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN;
+
+done:
+	/* dump msg */
+	if (ret > IPU_CHECK_ERR_MIN)
+		dump_check_err(t->dev, ret);
+	else if (ret != IPU_CHECK_OK)
+		dump_check_warn(t->dev, ret);
+
+	return ret;
+}
+
+static int prepare_task(struct ipu_task_entry *t)
+{
+	int ret = 0;
+
+	ret = check_task(t);
+	if (ret > IPU_CHECK_ERR_MIN)
+		return -EINVAL;
+
+	dump_task_info(t);
+
+	return ret;
+}
+
+/* should call from a process context */
+static int queue_task(struct ipu_task_entry *t)
+{
+	int ret = 0;
+	struct ipu_soc *ipu;
+	struct list_head *task_list = NULL;
+	struct mutex *task_lock = NULL;
+	wait_queue_head_t *waitq = NULL;
+
+	ipu = most_free_ipu_task(t);
+	t->dev = ipu->dev;
+
+	dev_dbg(t->dev, "[0x%p]Queue task: id %d\n", (void *)t, t->task_id);
+
+	init_completion(&t->comp);
+
+	t->set.task = 0;
+	switch (t->task_id) {
+	case IPU_TASK_ID_VF:
+		task_list = &ipu->task_list[0];
+		task_lock = &ipu->task_lock[0];
+		waitq = &ipu->waitq[0];
+		if (t->set.mode & IC_MODE)
+			t->set.task |= IC_VF;
+		else if (t->set.mode & VDI_MODE)
+			t->set.task |= VDI_VF;
+		if (t->set.mode & ROT_MODE)
+			t->set.task |= ROT_VF;
+		break;
+	case IPU_TASK_ID_PP:
+		task_list = &ipu->task_list[1];
+		task_lock = &ipu->task_lock[1];
+		waitq = &ipu->waitq[1];
+		if (t->set.mode & IC_MODE)
+			t->set.task |= IC_PP;
+		if (t->set.mode & ROT_MODE)
+			t->set.task |= ROT_PP;
+		break;
+	default:
+		dev_err(t->dev, "[0x%p]should never come here\n", (void *)t);
+	}
+
+	dev_dbg(t->dev, "[0x%p]choose task_id[%d] mode[0x%x]\n",
+			(void *)t, t->task_id, t->set.task);
+	dev_dbg(t->dev, "[0x%p]\tIPU_TASK_ID_VF = %d\n",
+				(void *)t, IPU_TASK_ID_VF);
+	dev_dbg(t->dev, "[0x%p]\tIPU_TASK_ID_PP = %d\n",
+				(void *)t, IPU_TASK_ID_PP);
+	dev_dbg(t->dev, "[0x%p]\tIC_VF = 0x%x\n", (void *)t, IC_VF);
+	dev_dbg(t->dev, "[0x%p]\tIC_PP = 0x%x\n", (void *)t, IC_PP);
+	dev_dbg(t->dev, "[0x%p]\tROT_VF = 0x%x\n", (void *)t, ROT_VF);
+	dev_dbg(t->dev, "[0x%p]\tROT_PP = 0x%x\n", (void *)t, ROT_PP);
+	dev_dbg(t->dev, "[0x%p]\tVDI_VF = 0x%x\n", (void *)t, VDI_VF);
+
+	/* add and wait task */
+	mutex_lock(task_lock);
+	list_add_tail(&t->node, task_list);
+	mutex_unlock(task_lock);
+
+	wake_up_interruptible(waitq);
+
+	wait_for_completion(&t->comp);
+
+	dev_dbg(t->dev, "[0x%p]Queue task finished\n", (void *)t);
+
+	if (t->state != STATE_OK) {
+		dev_err(t->dev, "[0x%p]state %d: %s\n",
+			(void *)t, t->state, state_msg[t->state].msg);
+		ret = -ECANCELED;
+	}
+
+	return ret;
+}
+
+static bool need_split(struct ipu_task_entry *t)
+{
+	return (t->set.split_mode != NO_SPLIT);
+}
+
+static int split_task_thread(void *data)
+{
+	struct ipu_split_task *t = data;
+
+	t->ret = ipu_queue_sp_task(t);
+
+	t->could_finish = true;
+
+	wake_up_interruptible(&t->waitq);
+
+	do_exit(0);
+}
+
+static int create_split_task(
+		int stripe,
+		struct ipu_split_task *sp_task)
+{
+	struct ipu_task *task = &(sp_task->task);
+	struct ipu_task_entry *t = sp_task->parent_task;
+
+	sp_task->task_no |= stripe;
+
+	task->input = t->input;
+	task->output = t->output;
+	task->overlay_en = t->overlay_en;
+	if (task->overlay_en)
+		task->overlay = t->overlay;
+	task->priority = t->priority;
+	task->task_id = t->task_id;
+	task->timeout = t->timeout;
+
+	task->input.crop.w = t->set.sp_setting.iw;
+	task->input.crop.h = t->set.sp_setting.ih;
+	if (task->overlay_en) {
+		task->overlay.crop.w = t->set.sp_setting.ow;
+		task->overlay.crop.h = t->set.sp_setting.oh;
+	}
+	if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
+		task->output.crop.w = t->set.sp_setting.oh;
+		task->output.crop.h = t->set.sp_setting.ow;
+		t->set.sp_setting.rl_split_line = t->set.sp_setting.o_bottom_pos;
+		t->set.sp_setting.ud_split_line = t->set.sp_setting.o_right_pos;
+
+	} else {
+		task->output.crop.w = t->set.sp_setting.ow;
+		task->output.crop.h = t->set.sp_setting.oh;
+		t->set.sp_setting.rl_split_line = t->set.sp_setting.o_right_pos;
+		t->set.sp_setting.ud_split_line = t->set.sp_setting.o_bottom_pos;
+	}
+
+	if (stripe & LEFT_STRIPE)
+		task->input.crop.pos.x += t->set.sp_setting.i_left_pos;
+	else if (stripe & RIGHT_STRIPE)
+		task->input.crop.pos.x += t->set.sp_setting.i_right_pos;
+	if (stripe & UP_STRIPE)
+		task->input.crop.pos.y += t->set.sp_setting.i_top_pos;
+	else if (stripe & DOWN_STRIPE)
+		task->input.crop.pos.y += t->set.sp_setting.i_bottom_pos;
+
+	if (task->overlay_en) {
+		if (stripe & LEFT_STRIPE)
+			task->overlay.crop.pos.x += t->set.sp_setting.o_left_pos;
+		else if (stripe & RIGHT_STRIPE)
+			task->overlay.crop.pos.x += t->set.sp_setting.o_right_pos;
+		if (stripe & UP_STRIPE)
+			task->overlay.crop.pos.y += t->set.sp_setting.o_top_pos;
+		else if (stripe & DOWN_STRIPE)
+			task->overlay.crop.pos.y += t->set.sp_setting.o_bottom_pos;
+	}
+
+	switch (t->output.rotate) {
+	case IPU_ROTATE_NONE:
+		if (stripe & LEFT_STRIPE)
+			task->output.crop.pos.x += t->set.sp_setting.o_left_pos;
+		else if (stripe & RIGHT_STRIPE)
+			task->output.crop.pos.x += t->set.sp_setting.o_right_pos;
+		if (stripe & UP_STRIPE)
+			task->output.crop.pos.y += t->set.sp_setting.o_top_pos;
+		else if (stripe & DOWN_STRIPE)
+			task->output.crop.pos.y += t->set.sp_setting.o_bottom_pos;
+		break;
+	case IPU_ROTATE_VERT_FLIP:
+		if (stripe & LEFT_STRIPE)
+			task->output.crop.pos.x += t->set.sp_setting.o_left_pos;
+		else if (stripe & RIGHT_STRIPE)
+			task->output.crop.pos.x += t->set.sp_setting.o_right_pos;
+		if (stripe & UP_STRIPE)
+			task->output.crop.pos.y =
+					t->output.crop.pos.y + t->output.crop.h
+					- t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
+		else if (stripe & DOWN_STRIPE)
+			task->output.crop.pos.y =
+					t->output.crop.pos.y + t->output.crop.h
+					- t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
+		break;
+	case IPU_ROTATE_HORIZ_FLIP:
+		if (stripe & LEFT_STRIPE)
+			task->output.crop.pos.x =
+					t->output.crop.pos.x + t->output.crop.w
+					- t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
+		else if (stripe & RIGHT_STRIPE)
+			task->output.crop.pos.x =
+					t->output.crop.pos.x + t->output.crop.w
+					- t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
+		if (stripe & UP_STRIPE)
+			task->output.crop.pos.y += t->set.sp_setting.o_top_pos;
+		else if (stripe & DOWN_STRIPE)
+			task->output.crop.pos.y += t->set.sp_setting.o_bottom_pos;
+		break;
+	case IPU_ROTATE_180:
+		if (stripe & LEFT_STRIPE)
+			task->output.crop.pos.x =
+					t->output.crop.pos.x + t->output.crop.w
+					- t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
+		else if (stripe & RIGHT_STRIPE)
+			task->output.crop.pos.x =
+					t->output.crop.pos.x + t->output.crop.w
+					- t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
+		if (stripe & UP_STRIPE)
+			task->output.crop.pos.y =
+					t->output.crop.pos.y + t->output.crop.h
+					- t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
+		else if (stripe & DOWN_STRIPE)
+			task->output.crop.pos.y =
+					t->output.crop.pos.y + t->output.crop.h
+					- t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
+		break;
+	case IPU_ROTATE_90_RIGHT:
+		if (stripe & UP_STRIPE)
+			task->output.crop.pos.x =
+					t->output.crop.pos.x + t->output.crop.w
+					- t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
+		else if (stripe & DOWN_STRIPE)
+			task->output.crop.pos.x =
+					t->output.crop.pos.x + t->output.crop.w
+					- t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
+		if (stripe & LEFT_STRIPE)
+			task->output.crop.pos.y += t->set.sp_setting.o_left_pos;
+		else if (stripe & RIGHT_STRIPE)
+			task->output.crop.pos.y += t->set.sp_setting.o_right_pos;
+		break;
+	case IPU_ROTATE_90_RIGHT_HFLIP:
+		if (stripe & UP_STRIPE)
+			task->output.crop.pos.x += t->set.sp_setting.o_top_pos;
+		else if (stripe & DOWN_STRIPE)
+			task->output.crop.pos.x += t->set.sp_setting.o_bottom_pos;
+		if (stripe & LEFT_STRIPE)
+			task->output.crop.pos.y += t->set.sp_setting.o_left_pos;
+		else if (stripe & RIGHT_STRIPE)
+			task->output.crop.pos.y += t->set.sp_setting.o_right_pos;
+		break;
+	case IPU_ROTATE_90_RIGHT_VFLIP:
+		if (stripe & UP_STRIPE)
+			task->output.crop.pos.x =
+					t->output.crop.pos.x + t->output.crop.w
+					- t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
+		else if (stripe & DOWN_STRIPE)
+			task->output.crop.pos.x =
+					t->output.crop.pos.x + t->output.crop.w
+					- t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
+		if (stripe & LEFT_STRIPE)
+			task->output.crop.pos.y =
+					t->output.crop.pos.y + t->output.crop.h
+					- t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
+		else if (stripe & RIGHT_STRIPE)
+			task->output.crop.pos.y =
+					t->output.crop.pos.y + t->output.crop.h
+					- t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
+		break;
+	case IPU_ROTATE_90_LEFT:
+		if (stripe & UP_STRIPE)
+			task->output.crop.pos.x += t->set.sp_setting.o_top_pos;
+		else if (stripe & DOWN_STRIPE)
+			task->output.crop.pos.x += t->set.sp_setting.o_bottom_pos;
+		if (stripe & LEFT_STRIPE)
+			task->output.crop.pos.y =
+					t->output.crop.pos.y + t->output.crop.h
+					- t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
+		else if (stripe & RIGHT_STRIPE)
+			task->output.crop.pos.y =
+					t->output.crop.pos.y + t->output.crop.h
+					- t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
+		break;
+	default:
+		dev_err(t->dev, "should not be here\n");
+		break;
+	}
+
+	/*check split task deinterlace enable*/
+	if (t->input.deinterlace.enable) {
+		sp_task->ret = ipu_queue_sp_task(sp_task);
+	} else {
+		sp_task->thread = kthread_run(split_task_thread, sp_task,
+					"ipu_split_task");
+		if (IS_ERR(sp_task->thread)) {
+			dev_err(t->dev, "split thread can not create\n");
+			return PTR_ERR(sp_task->thread);
+		}
+	}
+
+	return 0;
+}
+
+static int queue_split_task(struct ipu_task_entry *t)
+{
+	struct ipu_split_task sp_task[4];
+	int i, ret = 0, size;
+
+	dev_dbg(t->dev, "Split task 0x%p\n", (void *)t);
+
+	if ((t->set.split_mode == RL_SPLIT) || (t->set.split_mode == UD_SPLIT))
+		size = 2;
+	else
+		size = 4;
+
+	for (i = 0; i < size; i++) {
+		memset(&sp_task[i], 0, sizeof(struct ipu_split_task));
+		init_waitqueue_head(&(sp_task[i].waitq));
+		sp_task[i].could_finish = false;
+		sp_task[i].parent_task = t;
+		sp_task[i].task_no = t->task_no;
+	}
+
+	if (t->set.split_mode == RL_SPLIT) {
+		create_split_task(LEFT_STRIPE, &sp_task[0]);
+		create_split_task(RIGHT_STRIPE, &sp_task[1]);
+	} else if (t->set.split_mode == UD_SPLIT) {
+		create_split_task(UP_STRIPE, &sp_task[0]);
+		create_split_task(DOWN_STRIPE, &sp_task[1]);
+	} else {
+		create_split_task(LEFT_STRIPE | UP_STRIPE, &sp_task[0]);
+		create_split_task(LEFT_STRIPE | DOWN_STRIPE, &sp_task[1]);
+		create_split_task(RIGHT_STRIPE | UP_STRIPE, &sp_task[2]);
+		create_split_task(RIGHT_STRIPE | DOWN_STRIPE, &sp_task[3]);
+	}
+
+	/*check split task deinterlace enable*/
+	if (t->input.deinterlace.enable) {
+		return ret;
+	} else {
+		for (i = 0; i < size; i++) {
+			wait_event_interruptible(sp_task[i].waitq, sp_task[i].could_finish);
+			if (sp_task[i].ret < 0) {
+				ret = sp_task[i].ret;
+				dev_err(t->dev,
+					"split task %d fail with ret %d\n",
+					i, ret);
+			}
+		}
+		return ret;
+	}
+}
+
+static struct ipu_task_entry *create_task_entry(struct ipu_task *task)
+{
+	struct ipu_task_entry *tsk;
+
+	tsk = kzalloc(sizeof(struct ipu_task_entry), GFP_KERNEL);
+	if (!tsk)
+		return ERR_PTR(-ENOMEM);
+
+	tsk->dev = ipu_dev;
+	tsk->input = task->input;
+	tsk->output = task->output;
+	tsk->overlay_en = task->overlay_en;
+	if (tsk->overlay_en)
+		tsk->overlay = task->overlay;
+	tsk->priority = task->priority;
+	tsk->task_id = task->task_id;
+	if (task->timeout && (task->timeout > DEF_TIMEOUT_MS))
+		tsk->timeout = task->timeout;
+	else
+		tsk->timeout = DEF_TIMEOUT_MS;
+
+	return tsk;
+}
+
+int ipu_check_task(struct ipu_task *task)
+{
+	struct ipu_task_entry *tsk;
+	int ret = 0;
+
+	tsk = create_task_entry(task);
+	if (IS_ERR(tsk))
+		return PTR_ERR(tsk);
+
+	ret = check_task(tsk);
+
+	task->input = tsk->input;
+	task->output = tsk->output;
+	task->overlay = tsk->overlay;
+
+	dump_task_info(tsk);
+
+	kfree(tsk);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(ipu_check_task);
+
+int ipu_queue_sp_task(struct ipu_split_task *sp_task)
+{
+	struct ipu_task_entry *tsk;
+	int ret;
+
+	tsk = create_task_entry(&sp_task->task);
+	if (IS_ERR(tsk))
+		return PTR_ERR(tsk);
+
+	tsk->task_no = sp_task->task_no;
+
+	ret = prepare_task(tsk);
+	if (ret < 0)
+		goto done;
+
+	tsk->set.sp_setting = sp_task->parent_task->set.sp_setting;
+
+	ret = queue_task(tsk);
+done:
+	kfree(tsk);
+	return ret;
+}
+
+int ipu_queue_task(struct ipu_task *task)
+{
+	struct ipu_task_entry *tsk;
+	int ret;
+	u32 tmp_task_no;
+
+	tsk = create_task_entry(task);
+	if (IS_ERR(tsk))
+		return PTR_ERR(tsk);
+
+	ret = prepare_task(tsk);
+	if (ret < 0)
+		goto done;
+
+	/* task_no last for bits for split task type*/
+	tmp_task_no = frame_no++ % 1024;
+	tsk->task_no = tmp_task_no << 4;
+
+	if (need_split(tsk))
+		ret = queue_split_task(tsk);
+	else
+		ret = queue_task(tsk);
+done:
+	kfree(tsk);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(ipu_queue_task);
+
+static bool only_ic(u8 mode)
+{
+	return ((mode == IC_MODE) || (mode == VDI_MODE));
+}
+
+static bool only_rot(u8 mode)
+{
+	return (mode == ROT_MODE);
+}
+
+static bool ic_and_rot(u8 mode)
+{
+	return ((mode == (IC_MODE | ROT_MODE)) ||
+		 (mode == (VDI_MODE | ROT_MODE)));
+}
+
+static int init_ic(struct ipu_soc *ipu, struct ipu_task_entry *t)
+{
+	int ret = 0;
+	ipu_channel_params_t params;
+	dma_addr_t inbuf = 0, ovbuf = 0, ov_alp_buf = 0;
+	dma_addr_t inbuf_p = 0, inbuf_n = 0;
+	dma_addr_t outbuf = 0;
+	int out_uoff = 0, out_voff = 0, out_rot;
+	int out_w = 0, out_h = 0, out_stride;
+	int out_fmt;
+
+	memset(&params, 0, sizeof(params));
+
+	/* is it need link a rot channel */
+	if (ic_and_rot(t->set.mode)) {
+		outbuf = t->set.r_paddr;
+		out_w = t->set.r_width;
+		out_h = t->set.r_height;
+		out_stride = t->set.r_stride;
+		out_fmt = t->set.r_fmt;
+		out_uoff = 0;
+		out_voff = 0;
+		out_rot = IPU_ROTATE_NONE;
+	} else {
+		outbuf = t->output.paddr + t->set.o_off;
+		out_w = t->output.crop.w;
+		out_h = t->output.crop.h;
+		out_stride = t->set.ostride;
+		out_fmt = t->output.format;
+		out_uoff = t->set.o_uoff;
+		out_voff = t->set.o_voff;
+		out_rot = t->output.rotate;
+	}
+
+	/* settings */
+	params.mem_prp_vf_mem.in_width = t->input.crop.w;
+	params.mem_prp_vf_mem.out_width = out_w;
+	params.mem_prp_vf_mem.in_height = t->input.crop.h;
+	params.mem_prp_vf_mem.out_height = out_h;
+	params.mem_prp_vf_mem.in_pixel_fmt = t->input.format;
+	params.mem_prp_vf_mem.out_pixel_fmt = out_fmt;
+	params.mem_prp_vf_mem.motion_sel = t->input.deinterlace.motion;
+
+	params.mem_prp_vf_mem.outh_resize_ratio =
+			t->set.sp_setting.outh_resize_ratio;
+	params.mem_prp_vf_mem.outv_resize_ratio =
+			t->set.sp_setting.outv_resize_ratio;
+
+	if (t->overlay_en) {
+		params.mem_prp_vf_mem.in_g_pixel_fmt = t->overlay.format;
+		params.mem_prp_vf_mem.graphics_combine_en = 1;
+		if (t->overlay.alpha.mode == IPU_ALPHA_MODE_GLOBAL)
+			params.mem_prp_vf_mem.global_alpha_en = 1;
+		else
+			params.mem_prp_vf_mem.alpha_chan_en = 1;
+		params.mem_prp_vf_mem.alpha = t->overlay.alpha.gvalue;
+		if (t->overlay.colorkey.enable) {
+			params.mem_prp_vf_mem.key_color_en = 1;
+			params.mem_prp_vf_mem.key_color = t->overlay.colorkey.value;
+		}
+	}
+
+	/* init channels */
+	ret = ipu_init_channel(ipu, t->set.ic_chan, &params);
+	if (ret < 0) {
+		t->state = STATE_INIT_CHAN_FAIL;
+		goto done;
+	}
+
+	if (deinterlace_3_field(t)) {
+		ret = ipu_init_channel(ipu, t->set.vdi_ic_p_chan, &params);
+		if (ret < 0) {
+			t->state = STATE_INIT_CHAN_FAIL;
+			goto done;
+		}
+		ret = ipu_init_channel(ipu, t->set.vdi_ic_n_chan, &params);
+		if (ret < 0) {
+			t->state = STATE_INIT_CHAN_FAIL;
+			goto done;
+		}
+	}
+
+	/* init channel bufs */
+	if (deinterlace_3_field(t)) {
+		inbuf_p = t->input.paddr + t->set.istride + t->set.i_off;
+		inbuf = t->input.paddr_n + t->set.i_off;
+		inbuf_n = t->input.paddr_n + t->set.istride + t->set.i_off;
+	} else
+		inbuf = t->input.paddr + t->set.i_off;
+
+	if (t->overlay_en) {
+		ovbuf = t->overlay.paddr + t->set.ov_off;
+		if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL)
+			ov_alp_buf = t->overlay.alpha.loc_alp_paddr
+				+ t->set.ov_alpha_off;
+	}
+
+	ret = ipu_init_channel_buffer(ipu,
+			t->set.ic_chan,
+			IPU_INPUT_BUFFER,
+			t->input.format,
+			t->input.crop.w,
+			t->input.crop.h,
+			t->set.istride,
+			IPU_ROTATE_NONE,
+			inbuf,
+			0,
+			0,
+			t->set.i_uoff,
+			t->set.i_voff);
+	if (ret < 0) {
+		t->state = STATE_INIT_CHAN_BUF_FAIL;
+		goto done;
+	}
+
+	if (deinterlace_3_field(t)) {
+		ret = ipu_init_channel_buffer(ipu,
+				t->set.vdi_ic_p_chan,
+				IPU_INPUT_BUFFER,
+				t->input.format,
+				t->input.crop.w,
+				t->input.crop.h,
+				t->set.istride,
+				IPU_ROTATE_NONE,
+				inbuf_p,
+				0,
+				0,
+				t->set.i_uoff,
+				t->set.i_voff);
+		if (ret < 0) {
+			t->state = STATE_INIT_CHAN_BUF_FAIL;
+			goto done;
+		}
+
+		ret = ipu_init_channel_buffer(ipu,
+				t->set.vdi_ic_n_chan,
+				IPU_INPUT_BUFFER,
+				t->input.format,
+				t->input.crop.w,
+				t->input.crop.h,
+				t->set.istride,
+				IPU_ROTATE_NONE,
+				inbuf_n,
+				0,
+				0,
+				t->set.i_uoff,
+				t->set.i_voff);
+		if (ret < 0) {
+			t->state = STATE_INIT_CHAN_BUF_FAIL;
+			goto done;
+		}
+	}
+
+	if (t->overlay_en) {
+		ret = ipu_init_channel_buffer(ipu,
+				t->set.ic_chan,
+				IPU_GRAPH_IN_BUFFER,
+				t->overlay.format,
+				t->overlay.crop.w,
+				t->overlay.crop.h,
+				t->set.ovstride,
+				IPU_ROTATE_NONE,
+				ovbuf,
+				0,
+				0,
+				t->set.ov_uoff,
+				t->set.ov_voff);
+		if (ret < 0) {
+			t->state = STATE_INIT_CHAN_BUF_FAIL;
+			goto done;
+		}
+
+		if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
+			ret = ipu_init_channel_buffer(ipu,
+					t->set.ic_chan,
+					IPU_ALPHA_IN_BUFFER,
+					IPU_PIX_FMT_GENERIC,
+					t->overlay.crop.w,
+					t->overlay.crop.h,
+					t->set.ov_alpha_stride,
+					IPU_ROTATE_NONE,
+					ov_alp_buf,
+					0,
+					0,
+					0, 0);
+			if (ret < 0) {
+				t->state = STATE_INIT_CHAN_BUF_FAIL;
+				goto done;
+			}
+		}
+	}
+
+	ret = ipu_init_channel_buffer(ipu,
+			t->set.ic_chan,
+			IPU_OUTPUT_BUFFER,
+			out_fmt,
+			out_w,
+			out_h,
+			out_stride,
+			out_rot,
+			outbuf,
+			0,
+			0,
+			out_uoff,
+			out_voff);
+	if (ret < 0) {
+		t->state = STATE_INIT_CHAN_BUF_FAIL;
+		goto done;
+	}
+
+done:
+	return ret;
+}
+
+static void uninit_ic(struct ipu_soc *ipu, struct ipu_task_entry *t)
+{
+	ipu_uninit_channel(ipu, t->set.ic_chan);
+	if (deinterlace_3_field(t)) {
+		ipu_uninit_channel(ipu, t->set.vdi_ic_p_chan);
+		ipu_uninit_channel(ipu, t->set.vdi_ic_n_chan);
+	}
+}
+
+static int init_rot(struct ipu_soc *ipu, struct ipu_task_entry *t)
+{
+	int ret = 0;
+	dma_addr_t inbuf = 0, outbuf = 0;
+	int in_uoff = 0, in_voff = 0;
+	int in_fmt, in_width, in_height, in_stride;
+
+	/* init channel */
+	ret = ipu_init_channel(ipu, t->set.rot_chan, NULL);
+	if (ret < 0) {
+		t->state = STATE_INIT_CHAN_FAIL;
+		goto done;
+	}
+
+	/* init channel buf */
+	/* is it need link to a ic channel */
+	if (ic_and_rot(t->set.mode)) {
+		in_fmt = t->set.r_fmt;
+		in_width = t->set.r_width;
+		in_height = t->set.r_height;
+		in_stride = t->set.r_stride;
+		inbuf = t->set.r_paddr;
+		in_uoff = 0;
+		in_voff = 0;
+	} else {
+		in_fmt = t->input.format;
+		in_width = t->input.crop.w;
+		in_height = t->input.crop.h;
+		in_stride = t->set.istride;
+		inbuf = t->input.paddr + t->set.i_off;
+		in_uoff = t->set.i_uoff;
+		in_voff = t->set.i_voff;
+	}
+	outbuf = t->output.paddr + t->set.o_off;
+
+	ret = ipu_init_channel_buffer(ipu,
+			t->set.rot_chan,
+			IPU_INPUT_BUFFER,
+			in_fmt,
+			in_width,
+			in_height,
+			in_stride,
+			t->output.rotate,
+			inbuf,
+			0,
+			0,
+			in_uoff,
+			in_voff);
+	if (ret < 0) {
+		t->state = STATE_INIT_CHAN_BUF_FAIL;
+		goto done;
+	}
+
+	ret = ipu_init_channel_buffer(ipu,
+			t->set.rot_chan,
+			IPU_OUTPUT_BUFFER,
+			t->output.format,
+			t->output.crop.w,
+			t->output.crop.h,
+			t->set.ostride,
+			IPU_ROTATE_NONE,
+			outbuf,
+			0,
+			0,
+			t->set.o_uoff,
+			t->set.o_voff);
+	if (ret < 0) {
+		t->state = STATE_INIT_CHAN_BUF_FAIL;
+		goto done;
+	}
+
+done:
+	return ret;
+}
+
+static void uninit_rot(struct ipu_soc *ipu, struct ipu_task_entry *t)
+{
+	ipu_uninit_channel(ipu, t->set.rot_chan);
+}
+
+static int get_irq(struct ipu_task_entry *t)
+{
+	int irq;
+	ipu_channel_t chan;
+
+	if (only_ic(t->set.mode))
+		chan = t->set.ic_chan;
+	else
+		chan = t->set.rot_chan;
+
+	switch (chan) {
+	case MEM_ROT_VF_MEM:
+		irq = IPU_IRQ_PRP_VF_ROT_OUT_EOF;
+		break;
+	case MEM_ROT_PP_MEM:
+		irq = IPU_IRQ_PP_ROT_OUT_EOF;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+	case MEM_PRP_VF_MEM:
+		irq = IPU_IRQ_PRP_VF_OUT_EOF;
+		break;
+	case MEM_PP_MEM:
+		irq = IPU_IRQ_PP_OUT_EOF;
+		break;
+	default:
+		irq = -EINVAL;
+	}
+
+	return irq;
+}
+
+static irqreturn_t task_irq_handler(int irq, void *dev_id)
+{
+	struct completion *comp = dev_id;
+	complete(comp);
+	return IRQ_HANDLED;
+}
+
+/* Fix deinterlace up&down split mode medium line */
+static void vdi_split_process(struct ipu_soc *ipu, struct ipu_task_entry *t)
+{
+	u32 vdi_size;
+	u32 vdi_save_lines;
+	u32 stripe_mode;
+	u32 task_no;
+	u32 i, offset_addr;
+	unsigned char  *base_off;
+
+	stripe_mode = t->task_no & 0xf;
+	task_no = t->task_no >> 4;
+
+	base_off = (char *) __va(t->output.paddr);
+	if (base_off == NULL) {
+		dev_err(t->dev, "[0x%p]Falied get vitual address\n", (void *)t);
+		return;
+	}
+
+	vdi_save_lines = (t->output.crop.h - t->set.sp_setting.ud_split_line)/2 ;
+	vdi_size = vdi_save_lines * t->output.crop.w * 2;
+
+	if (vdi_save_lines <= 0) {
+		dev_err(t->dev, "[0x%p] vdi_save_line error\n", (void *)t);
+		return;
+	}
+
+	/*check vditmpbuf buffer have alloced or buffer size is changed */
+	if ((vdi_save_lines != old_save_lines) || (vdi_size != old_size)) {
+		if (vditmpbuf[0] != NULL)
+			kfree(vditmpbuf[0]);
+		if (vditmpbuf[1] != NULL)
+			kfree(vditmpbuf[1]);
+
+		vditmpbuf[0] = (char *)kmalloc(vdi_size, GFP_KERNEL);
+		if (vditmpbuf[0] == NULL) {
+			dev_err(t->dev,
+					"[0x%p]Falied Alloc vditmpbuf[0]\n", (void *)t);
+			return;
+		}
+		memset(vditmpbuf[0], 0, vdi_size);
+
+		vditmpbuf[1] = (char *)kmalloc(vdi_size, GFP_KERNEL);
+		if (vditmpbuf[1] == NULL) {
+			dev_err(t->dev,
+					"[0x%p]Falied Alloc vditmpbuf[1]\n", (void *)t);
+			return;
+		}
+		memset(vditmpbuf[1], 0, vdi_size);
+
+		old_save_lines = vdi_save_lines;
+		old_size = vdi_size;
+	}
+
+	/* UP stripe or UP&LEFT stripe */
+	if ((stripe_mode == UP_STRIPE) ||
+			(stripe_mode == (UP_STRIPE | LEFT_STRIPE))) {
+		if (!buf0filled) {
+
+			offset_addr = t->set.o_off +
+				t->set.sp_setting.ud_split_line*t->set.ostride;
+			dmac_flush_range(base_off + offset_addr,
+					base_off + offset_addr + vdi_size);
+			outer_flush_range(t->output.paddr + offset_addr,
+					t->output.paddr + offset_addr + vdi_size);
+
+			for (i = 0; i < vdi_save_lines; i++)
+				memcpy(vditmpbuf[0] + i*t->output.crop.w*2,
+						base_off + offset_addr + i*t->set.ostride,
+						t->output.crop.w*2);
+			buf0filled = true;
+		} else {
+			offset_addr = t->set.o_off +
+					(t->output.crop.h - vdi_save_lines)*t->set.ostride;
+			for (i = 0; i < vdi_save_lines; i++)
+				memcpy(base_off + offset_addr + i*t->set.ostride,
+						vditmpbuf[0] + i*t->output.crop.w*2,
+						t->output.crop.w*2);
+
+			dmac_flush_range(base_off + offset_addr,
+					base_off + offset_addr + i*t->set.ostride);
+			outer_flush_range(t->output.paddr + offset_addr,
+					t->output.paddr + offset_addr + i*t->set.ostride);
+			buf0filled = false;
+		}
+	}
+	/*Down stripe or Down&Left stripe*/
+	else if ((stripe_mode == DOWN_STRIPE) ||
+			(stripe_mode == (DOWN_STRIPE | LEFT_STRIPE))) {
+		if (!buf0filled) {
+			offset_addr = t->set.o_off + vdi_save_lines*t->set.ostride;
+			dmac_flush_range(base_off + offset_addr,
+					base_off + offset_addr + vdi_size);
+			outer_flush_range(t->output.paddr + offset_addr,
+					t->output.paddr + offset_addr + vdi_size);
+
+			for (i = 0; i < vdi_save_lines; i++)
+				memcpy(vditmpbuf[0] + i*t->output.crop.w*2,
+						base_off + offset_addr + i*t->set.ostride,
+						t->output.crop.w*2);
+			buf0filled = true;
+		} else {
+			offset_addr = t->set.o_off;
+			for (i = 0; i < vdi_save_lines; i++)
+				memcpy(base_off + offset_addr + i*t->set.ostride,
+						vditmpbuf[0] + i*t->output.crop.w*2,
+						t->output.crop.w*2);
+
+			dmac_flush_range(base_off + offset_addr,
+					base_off + offset_addr + i*t->set.ostride);
+			outer_flush_range(t->output.paddr + offset_addr,
+					t->output.paddr + offset_addr + i*t->set.ostride);
+			buf0filled = false;
+		}
+	}
+	/*Up&Right stripe*/
+	else if (stripe_mode == (UP_STRIPE | RIGHT_STRIPE)) {
+		if (!buf1filled) {
+			offset_addr = t->set.o_off +
+				t->set.sp_setting.ud_split_line*t->set.ostride;
+			dmac_flush_range(base_off + offset_addr,
+					base_off + offset_addr + vdi_size);
+			outer_flush_range(t->output.paddr + offset_addr,
+					t->output.paddr + offset_addr + vdi_size);
+
+			for (i = 0; i < vdi_save_lines; i++)
+				memcpy(vditmpbuf[1] + i*t->output.crop.w*2,
+						base_off + offset_addr + i*t->set.ostride,
+						t->output.crop.w*2);
+			buf1filled = true;
+		} else {
+			offset_addr = t->set.o_off +
+				(t->output.crop.h - vdi_save_lines)*t->set.ostride;
+			for (i = 0; i < vdi_save_lines; i++)
+				memcpy(base_off + offset_addr + i*t->set.ostride,
+						vditmpbuf[1] + i*t->output.crop.w*2,
+						t->output.crop.w*2);
+
+			dmac_flush_range(base_off + offset_addr,
+					base_off + offset_addr + i*t->set.ostride);
+			outer_flush_range(t->output.paddr + offset_addr,
+					t->output.paddr + offset_addr + i*t->set.ostride);
+			buf1filled = false;
+		}
+	}
+	/*Down stripe or Down&Right stript*/
+	else if (stripe_mode == (DOWN_STRIPE | RIGHT_STRIPE)) {
+		if (!buf1filled) {
+			offset_addr = t->set.o_off + vdi_save_lines*t->set.ostride;
+			dmac_flush_range(base_off + offset_addr,
+					base_off + offset_addr + vdi_save_lines*t->set.ostride);
+			outer_flush_range(t->output.paddr + offset_addr,
+					t->output.paddr + offset_addr + vdi_save_lines*t->set.ostride);
+
+			for (i = 0; i < vdi_save_lines; i++)
+				memcpy(vditmpbuf[1] + i*t->output.crop.w*2,
+						base_off + offset_addr + i*t->set.ostride,
+						t->output.crop.w*2);
+			buf1filled = true;
+		} else {
+			offset_addr = t->set.o_off;
+			for (i = 0; i < vdi_save_lines; i++)
+				memcpy(base_off + offset_addr + i*t->set.ostride,
+						vditmpbuf[1] + i*t->output.crop.w*2,
+						t->output.crop.w*2);
+
+			dmac_flush_range(base_off + offset_addr,
+					base_off + offset_addr + vdi_save_lines*t->set.ostride);
+			outer_flush_range(t->output.paddr + offset_addr,
+					t->output.paddr + offset_addr + vdi_save_lines*t->set.ostride);
+			buf1filled = false;
+		}
+	}
+}
+
+static void do_task(struct ipu_soc *ipu, struct ipu_task_entry *t)
+{
+	struct completion comp;
+	int r_size;
+	int irq;
+	int ret;
+
+	if (!ipu) {
+		t->state = STATE_NO_IPU;
+		return;
+	}
+
+	dev_dbg(ipu->dev, "[0x%p]Do task: id %d\n", (void *)t, t->task_id);
+	dump_task_info(t);
+
+	if (t->set.task & IC_PP) {
+		t->set.ic_chan = MEM_PP_MEM;
+		dev_dbg(ipu->dev, "[0x%p]ic channel MEM_PP_MEM\n", (void *)t);
+	} else if (t->set.task & IC_VF) {
+		t->set.ic_chan = MEM_PRP_VF_MEM;
+		dev_dbg(ipu->dev, "[0x%p]ic channel MEM_PRP_VF_MEM\n", (void *)t);
+	} else if (t->set.task & VDI_VF) {
+		t->set.ic_chan = MEM_VDI_PRP_VF_MEM;
+		if (deinterlace_3_field(t)) {
+			t->set.vdi_ic_p_chan = MEM_VDI_PRP_VF_MEM_P;
+			t->set.vdi_ic_n_chan = MEM_VDI_PRP_VF_MEM_N;
+		}
+		dev_dbg(ipu->dev, "[0x%p]ic channel MEM_VDI_PRP_VF_MEM\n", (void *)t);
+	}
+
+	if (t->set.task & ROT_PP) {
+		t->set.rot_chan = MEM_ROT_PP_MEM;
+		dev_dbg(ipu->dev, "[0x%p]rot channel MEM_ROT_PP_MEM\n", (void *)t);
+	} else if (t->set.task & ROT_VF) {
+		t->set.rot_chan = MEM_ROT_VF_MEM;
+		dev_dbg(ipu->dev, "[0x%p]rot channel MEM_ROT_VF_MEM\n", (void *)t);
+	}
+
+	/* channel setup */
+	if (only_ic(t->set.mode)) {
+		dev_dbg(t->dev, "[0x%p]only ic mode\n", (void *)t);
+		ret = init_ic(ipu, t);
+		if (ret < 0)
+			goto chan_done;
+	} else if (only_rot(t->set.mode)) {
+		dev_dbg(t->dev, "[0x%p]only rot mode\n", (void *)t);
+		ret = init_rot(ipu, t);
+		if (ret < 0)
+			goto chan_done;
+	} else if (ic_and_rot(t->set.mode)) {
+		int rot_idx = (t->task_id == IPU_TASK_ID_VF) ? 0 : 1;
+
+		dev_dbg(t->dev, "[0x%p]ic + rot mode\n", (void *)t);
+		t->set.r_fmt = t->output.format;
+		if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
+			t->set.r_width = t->output.crop.h;
+			t->set.r_height = t->output.crop.w;
+		} else {
+			t->set.r_width = t->output.crop.w;
+			t->set.r_height = t->output.crop.h;
+		}
+		t->set.r_stride = t->set.r_width *
+			bytes_per_pixel(t->set.r_fmt);
+		r_size = PAGE_ALIGN(t->set.r_width * t->set.r_height
+			* fmt_to_bpp(t->set.r_fmt)/8);
+
+		if (r_size > ipu->rot_dma[rot_idx].size) {
+			dev_dbg(t->dev, "[0x%p]realloc rot buffer\n", (void *)t);
+
+			if (ipu->rot_dma[rot_idx].vaddr)
+				dma_free_coherent(t->dev,
+					ipu->rot_dma[rot_idx].size,
+					ipu->rot_dma[rot_idx].vaddr,
+					ipu->rot_dma[rot_idx].paddr);
+
+			ipu->rot_dma[rot_idx].size = r_size;
+			ipu->rot_dma[rot_idx].vaddr = dma_alloc_coherent(t->dev,
+						r_size,
+						&ipu->rot_dma[rot_idx].paddr,
+						GFP_DMA | GFP_KERNEL);
+			if (ipu->rot_dma[rot_idx].vaddr == NULL) {
+				ret = -ENOMEM;
+				goto chan_done;
+			}
+		}
+		t->set.r_paddr = ipu->rot_dma[rot_idx].paddr;
+
+		dev_dbg(t->dev, "[0x%p]rotation:\n", (void *)t);
+		dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->set.r_fmt);
+		dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->set.r_width);
+		dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->set.r_height);
+		dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->set.r_paddr);
+		dev_dbg(t->dev, "[0x%p]\trstride = %d\n", (void *)t, t->set.r_stride);
+
+		ret = init_ic(ipu, t);
+		if (ret < 0)
+			goto chan_done;
+		ret = init_rot(ipu, t);
+		if (ret < 0)
+			goto chan_done;
+		ret = ipu_link_channels(ipu, t->set.ic_chan,
+				t->set.rot_chan);
+		if (ret < 0) {
+			t->state = STATE_LINK_CHAN_FAIL;
+			goto chan_done;
+		}
+	} else {
+		dev_err(t->dev, "[0x%p]do_task: should not be here\n", (void *)t);
+		return;
+	}
+
+	/* channel setup */
+	/* irq setup */
+	irq = get_irq(t);
+	if (irq < 0) {
+		t->state = STATE_NO_IRQ;
+		goto chan_done;
+	}
+
+	dev_dbg(t->dev, "[0x%p]task irq is %d\n", (void *)t, irq);
+
+	init_completion(&comp);
+	ret = ipu_request_irq(ipu, irq, task_irq_handler, 0, NULL, &comp);
+	if (ret < 0) {
+		t->state = STATE_IRQ_FAIL;
+		goto chan_done;
+	}
+
+	/* enable/start channel */
+	if (only_ic(t->set.mode)) {
+		ipu_enable_channel(ipu, t->set.ic_chan);
+		if (deinterlace_3_field(t)) {
+			ipu_enable_channel(ipu, t->set.vdi_ic_p_chan);
+			ipu_enable_channel(ipu, t->set.vdi_ic_n_chan);
+		}
+
+		ipu_select_buffer(ipu, t->set.ic_chan, IPU_OUTPUT_BUFFER, 0);
+		if (t->overlay_en) {
+			ipu_select_buffer(ipu, t->set.ic_chan, IPU_GRAPH_IN_BUFFER, 0);
+			if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL)
+				ipu_select_buffer(ipu, t->set.ic_chan, IPU_ALPHA_IN_BUFFER, 0);
+		}
+		if (deinterlace_3_field(t))
+			ipu_select_multi_vdi_buffer(ipu, 0);
+		else
+			ipu_select_buffer(ipu, t->set.ic_chan, IPU_INPUT_BUFFER, 0);
+	} else if (only_rot(t->set.mode)) {
+		ipu_enable_channel(ipu, t->set.rot_chan);
+		ipu_select_buffer(ipu, t->set.rot_chan, IPU_OUTPUT_BUFFER, 0);
+		ipu_select_buffer(ipu, t->set.rot_chan, IPU_INPUT_BUFFER, 0);
+	} else if (ic_and_rot(t->set.mode)) {
+		ipu_enable_channel(ipu, t->set.rot_chan);
+		ipu_enable_channel(ipu, t->set.ic_chan);
+		if (deinterlace_3_field(t)) {
+			ipu_enable_channel(ipu, t->set.vdi_ic_p_chan);
+			ipu_enable_channel(ipu, t->set.vdi_ic_n_chan);
+		}
+
+		ipu_select_buffer(ipu, t->set.rot_chan, IPU_OUTPUT_BUFFER, 0);
+		if (t->overlay_en) {
+			ipu_select_buffer(ipu, t->set.ic_chan, IPU_GRAPH_IN_BUFFER, 0);
+			if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL)
+				ipu_select_buffer(ipu, t->set.ic_chan, IPU_ALPHA_IN_BUFFER, 0);
+		}
+		ipu_select_buffer(ipu, t->set.ic_chan, IPU_OUTPUT_BUFFER, 0);
+		if (deinterlace_3_field(t))
+			ipu_select_multi_vdi_buffer(ipu, 0);
+		else
+			ipu_select_buffer(ipu, t->set.ic_chan, IPU_INPUT_BUFFER, 0);
+	}
+
+	ret = wait_for_completion_timeout(&comp, msecs_to_jiffies(t->timeout));
+	if (ret == 0)
+		t->state = STATE_IRQ_TIMEOUT;
+
+	/* split mode and VDI mode */
+	if (t->input.deinterlace.enable &&
+			(t->task_no & (UP_STRIPE | DOWN_STRIPE)))
+		vdi_split_process(ipu, t);
+
+	ipu_free_irq(ipu, irq, &comp);
+
+	if (only_ic(t->set.mode)) {
+		ipu_disable_channel(ipu, t->set.ic_chan, true);
+		if (deinterlace_3_field(t)) {
+			ipu_disable_channel(ipu, t->set.vdi_ic_p_chan, true);
+			ipu_disable_channel(ipu, t->set.vdi_ic_n_chan, true);
+		}
+	} else if (only_rot(t->set.mode))
+		ipu_disable_channel(ipu, t->set.rot_chan, true);
+	else if (ic_and_rot(t->set.mode)) {
+		ipu_unlink_channels(ipu, t->set.ic_chan, t->set.rot_chan);
+		ipu_disable_channel(ipu, t->set.rot_chan, true);
+		ipu_disable_channel(ipu, t->set.ic_chan, true);
+		if (deinterlace_3_field(t)) {
+			ipu_disable_channel(ipu, t->set.vdi_ic_p_chan, true);
+			ipu_disable_channel(ipu, t->set.vdi_ic_n_chan, true);
+		}
+	}
+
+chan_done:
+	if (only_ic(t->set.mode))
+		uninit_ic(ipu, t);
+	else if (only_rot(t->set.mode))
+		uninit_rot(ipu, t);
+	else if (ic_and_rot(t->set.mode)) {
+		uninit_ic(ipu, t);
+		uninit_rot(ipu, t);
+	}
+	return;
+}
+
+static int thread_loop(struct ipu_soc *ipu, int id)
+{
+	struct ipu_task_entry *tsk;
+	struct list_head *task_list = &ipu->task_list[id];
+	struct mutex *task_lock = &ipu->task_lock[id];
+	int ret;
+
+	while (!kthread_should_stop()) {
+		int found = 0;
+
+		ret = wait_event_interruptible(ipu->waitq[id], !list_empty(task_list));
+		if (0 != ret)
+			continue;
+
+		mutex_lock(task_lock);
+
+		list_for_each_entry(tsk, task_list, node) {
+			if (tsk->priority == IPU_TASK_PRIORITY_HIGH) {
+				found = 1;
+				break;
+			}
+		}
+
+		if (!found)
+			tsk = list_first_entry(task_list, struct ipu_task_entry, node);
+
+		mutex_unlock(task_lock);
+
+		do_task(ipu, tsk);
+
+		mutex_lock(task_lock);
+		list_del(&tsk->node);
+		mutex_unlock(task_lock);
+
+		complete(&tsk->comp);
+	}
+
+	return 0;
+}
+
+static int task_vf_thread(void *data)
+{
+	struct ipu_soc *ipu = data;
+
+	thread_loop(ipu, 0);
+
+	return 0;
+}
+
+static int task_pp_thread(void *data)
+{
+	struct ipu_soc *ipu = data;
+
+	thread_loop(ipu, 1);
+
+	return 0;
+}
+
+static int mxc_ipu_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static long mxc_ipu_ioctl(struct file *file,
+		unsigned int cmd, unsigned long arg)
+{
+	int __user *argp = (void __user *)arg;
+	int ret = 0;
+
+	switch (cmd) {
+	case IPU_CHECK_TASK:
+		{
+			struct ipu_task task;
+
+			if (copy_from_user
+					(&task, (struct ipu_task *) arg,
+					 sizeof(struct ipu_task)))
+				return -EFAULT;
+			ret = ipu_check_task(&task);
+			if (copy_to_user((struct ipu_task *) arg,
+				&task, sizeof(struct ipu_task)))
+				return -EFAULT;
+			break;
+		}
+	case IPU_QUEUE_TASK:
+		{
+			struct ipu_task task;
+
+			if (copy_from_user
+					(&task, (struct ipu_task *) arg,
+					 sizeof(struct ipu_task)))
+				return -EFAULT;
+			ret = ipu_queue_task(&task);
+			break;
+		}
+	case IPU_ALLOC:
+		{
+			int size;
+			struct ipu_alloc_list *mem;
+
+			mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+			if (mem == NULL)
+				return -ENOMEM;
+
+			if (get_user(size, argp))
+				return -EFAULT;
+
+			mem->size = PAGE_ALIGN(size);
+
+			mem->cpu_addr = dma_alloc_coherent(ipu_dev, size,
+							   &mem->phy_addr,
+							   GFP_DMA);
+			if (mem->cpu_addr == NULL) {
+				kfree(mem);
+				return -ENOMEM;
+			}
+
+			list_add(&mem->list, &ipu_alloc_list);
+
+			dev_dbg(ipu_dev, "allocated %d bytes @ 0x%08X\n",
+				mem->size, mem->phy_addr);
+
+			if (put_user(mem->phy_addr, argp))
+				return -EFAULT;
+
+			break;
+		}
+	case IPU_FREE:
+		{
+			unsigned long offset;
+			struct ipu_alloc_list *mem;
+
+			if (get_user(offset, argp))
+				return -EFAULT;
+
+			ret = -EINVAL;
+			list_for_each_entry(mem, &ipu_alloc_list, list) {
+				if (mem->phy_addr == offset) {
+					list_del(&mem->list);
+					dma_free_coherent(ipu_dev,
+							  mem->size,
+							  mem->cpu_addr,
+							  mem->phy_addr);
+					kfree(mem);
+					ret = 0;
+					break;
+				}
+			}
+
+			break;
+		}
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	bool found = false;
+	u32 len;
+	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+	struct ipu_alloc_list *mem;
+
+	list_for_each_entry(mem, &ipu_alloc_list, list) {
+		if (offset == mem->phy_addr) {
+			found = true;
+			len = mem->size;
+			break;
+		}
+	}
+	if (!found)
+		return -EINVAL;
+
+	if (vma->vm_end - vma->vm_start > len)
+		return -EINVAL;
+
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+				vma->vm_end - vma->vm_start,
+				vma->vm_page_prot)) {
+		printk(KERN_ERR
+				"mmap failed!\n");
+		return -ENOBUFS;
+	}
+	return 0;
+}
+
+static int mxc_ipu_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static struct file_operations mxc_ipu_fops = {
+	.owner = THIS_MODULE,
+	.open = mxc_ipu_open,
+	.mmap = mxc_ipu_mmap,
+	.release = mxc_ipu_release,
+	.unlocked_ioctl = mxc_ipu_ioctl,
+};
+
+int register_ipu_device(struct ipu_soc *ipu, int id)
+{
+	int i, ret = 0;
+
+	if (!major) {
+		major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops);
+		if (major < 0) {
+			printk(KERN_ERR "Unable to register mxc_ipu as a char device\n");
+			ret = major;
+			goto register_cdev_fail;
+		}
+
+		ipu_class = class_create(THIS_MODULE, "mxc_ipu");
+		if (IS_ERR(ipu_class)) {
+			ret = PTR_ERR(ipu_class);
+			goto ipu_class_fail;
+		}
+
+		ipu_dev = device_create(ipu_class, NULL, MKDEV(major, 0),
+				NULL, "mxc_ipu");
+		if (IS_ERR(ipu_dev)) {
+			ret = PTR_ERR(ipu_dev);
+			goto dev_create_fail;
+		}
+		ipu_dev->dma_mask = kmalloc(sizeof(*ipu_dev->dma_mask), GFP_KERNEL);
+		*ipu_dev->dma_mask = DMA_BIT_MASK(32);
+		ipu_dev->coherent_dma_mask = DMA_BIT_MASK(32);
+	}
+
+	for (i = 0; i < 2; i++) {
+		INIT_LIST_HEAD(&ipu->task_list[i]);
+		init_waitqueue_head(&ipu->waitq[i]);
+		mutex_init(&ipu->task_lock[i]);
+
+		ipu->rot_dma[i].size = 0;
+	}
+
+	ipu->thread[0] = kthread_run(task_vf_thread, ipu,
+					"ipu%d_process-vf", id);
+	if (IS_ERR(ipu->thread[0])) {
+		ret = PTR_ERR(ipu->thread[0]);
+		goto kthread0_fail;
+	}
+
+	ipu->thread[1] = kthread_run(task_pp_thread, ipu,
+				"ipu%d_process-pp", id);
+	if (IS_ERR(ipu->thread[1])) {
+		ret = PTR_ERR(ipu->thread[1]);
+		goto kthread1_fail;
+	}
+
+	return ret;
+
+kthread1_fail:
+	kthread_stop(ipu->thread[0]);
+kthread0_fail:
+	if (id == 0)
+		device_destroy(ipu_class, MKDEV(major, 0));
+dev_create_fail:
+	if (id == 0) {
+		class_destroy(ipu_class);
+		unregister_chrdev(major, "mxc_ipu");
+	}
+ipu_class_fail:
+	if (id == 0)
+		unregister_chrdev(major, "mxc_ipu");
+register_cdev_fail:
+	return ret;
+}
+
+void unregister_ipu_device(struct ipu_soc *ipu, int id)
+{
+	int i;
+
+	kthread_stop(ipu->thread[0]);
+	kthread_stop(ipu->thread[1]);
+
+	for (i = 0; i < 2; i++) {
+		if (ipu->rot_dma[i].vaddr)
+			dma_free_coherent(ipu_dev,
+				ipu->rot_dma[i].size,
+				ipu->rot_dma[i].vaddr,
+				ipu->rot_dma[i].paddr);
+	}
+
+	if (major) {
+		device_destroy(ipu_class, MKDEV(major, 0));
+		class_destroy(ipu_class);
+		unregister_chrdev(major, "mxc_ipu");
+		major = 0;
+	}
+}
diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
new file mode 100644
index 00000000000..9e85bfcb8a2
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_disp.c
@@ -0,0 +1,2076 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file ipu_disp.c
+ *
+ * @brief IPU display submodule API functions
+ *
+ * @ingroup IPU
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm/atomic.h>
+#include <mach/clock.h>
+#include <mach/ipu-v3.h>
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+struct dp_csc_param_t {
+	int mode;
+	void *coeff;
+};
+
+#define SYNC_WAVE 0
+#define ASYNC_SER_WAVE 6
+
+/* DC display ID assignments */
+#define DC_DISP_ID_SYNC(di)	(di)
+#define DC_DISP_ID_SERIAL	2
+#define DC_DISP_ID_ASYNC	3
+
+static inline struct ipu_soc *pixelclk2ipu(struct clk *clk)
+{
+	struct ipu_soc *ipu;
+	struct clk *base = clk - clk->id;
+
+	ipu = container_of(base, struct ipu_soc, pixel_clk[0]);
+
+	return ipu;
+}
+
+static unsigned long _ipu_pixel_clk_get_rate(struct clk *clk)
+{
+	struct ipu_soc *ipu = pixelclk2ipu(clk);
+	u32 div;
+
+	_ipu_get(ipu);
+	div = ipu_di_read(ipu, clk->id, DI_BS_CLKGEN0);
+	_ipu_put(ipu);
+
+	if (div == 0)
+		return 0;
+	return  (clk_get_rate(clk->parent) * 16) / div;
+}
+
+static unsigned long _ipu_pixel_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	u32 div;
+	u32 parent_rate = clk_get_rate(clk->parent) * 16;
+	/*
+	 * Calculate divider
+	 * Fractional part is 4 bits,
+	 * so simply multiply by 2^4 to get fractional part.
+	 */
+	div = parent_rate / rate;
+
+	if (div < 0x10)            /* Min DI disp clock divider is 1 */
+		div = 0x10;
+	if (div & ~0xFEF)
+		div &= 0xFF8;
+	else {
+		/* Round up divider if it gets us closer to desired pix clk */
+		if ((div & 0xC) == 0xC) {
+			div += 0x10;
+			div &= ~0xF;
+		}
+	}
+	return parent_rate / div;
+}
+
+static int _ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct ipu_soc *ipu = pixelclk2ipu(clk);
+	u32 div = (clk_get_rate(clk->parent) * 16) / rate;
+
+	/* Round up divider if it gets us closer to desired pix clk */
+	if ((div & 0xC) == 0xC) {
+		div += 0x10;
+		div &= ~0xF;
+	}
+
+	ipu_di_write(ipu, clk->id, div, DI_BS_CLKGEN0);
+
+	/* Setup pixel clock timing */
+	/* FIXME: needs to be more flexible */
+	/* Down time is half of period */
+	ipu_di_write(ipu, clk->id, (div / 16) << 16, DI_BS_CLKGEN1);
+
+	return 0;
+}
+
+static int _ipu_pixel_clk_enable(struct clk *clk)
+{
+	struct ipu_soc *ipu = pixelclk2ipu(clk);
+	u32 disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
+	disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
+	ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
+
+	return 0;
+}
+
+static void _ipu_pixel_clk_disable(struct clk *clk)
+{
+	struct ipu_soc *ipu = pixelclk2ipu(clk);
+
+	u32 disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
+	disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
+	ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
+}
+
+static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct ipu_soc *ipu = pixelclk2ipu(clk);
+	u32 di_gen;
+
+	di_gen = ipu_di_read(ipu, clk->id, DI_GENERAL);
+	if (parent == ipu->ipu_clk)
+		di_gen &= ~DI_GEN_DI_CLK_EXT;
+	else if (!IS_ERR(ipu->di_clk[clk->id]) && parent == ipu->di_clk[clk->id])
+		di_gen |= DI_GEN_DI_CLK_EXT;
+	else {
+		return -EINVAL;
+	}
+
+	ipu_di_write(ipu, clk->id, di_gen, DI_GENERAL);
+	return 0;
+}
+
+#ifdef CONFIG_CLK_DEBUG
+#define __INIT_CLK_DEBUG(n)    .name = #n,
+#else
+#define __INIT_CLK_DEBUG(n)
+#endif
+struct clk ipu_pixel_clk[] = {
+	{
+		__INIT_CLK_DEBUG(pixel_clk_0)
+			.id = 0,
+		.get_rate = _ipu_pixel_clk_get_rate,
+		.set_rate = _ipu_pixel_clk_set_rate,
+		.round_rate = _ipu_pixel_clk_round_rate,
+		.set_parent = _ipu_pixel_clk_set_parent,
+		.enable = _ipu_pixel_clk_enable,
+		.disable = _ipu_pixel_clk_disable,
+	},
+	{
+		__INIT_CLK_DEBUG(pixel_clk_1)
+			.id = 1,
+		.get_rate = _ipu_pixel_clk_get_rate,
+		.set_rate = _ipu_pixel_clk_set_rate,
+		.round_rate = _ipu_pixel_clk_round_rate,
+		.set_parent = _ipu_pixel_clk_set_parent,
+		.enable = _ipu_pixel_clk_enable,
+		.disable = _ipu_pixel_clk_disable,
+	},
+};
+
+struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][2] = {
+	{
+		{
+			.con_id = "pixel_clk_0",
+		},
+		{
+			.con_id = "pixel_clk_1",
+		},
+	},
+	{
+		{
+			.con_id = "pixel_clk_0",
+		},
+		{
+			.con_id = "pixel_clk_1",
+		},
+	},
+};
+
+int dmfc_type_setup;
+
+void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first)
+{
+	u32 dmfc_wr_chan, dmfc_dp_chan;
+
+	if (first) {
+		if (dmfc_type_setup > dmfc_type)
+			dmfc_type = dmfc_type_setup;
+		else
+			dmfc_type_setup = dmfc_type;
+
+		/* disable DMFC-IC channel*/
+		ipu_dmfc_write(ipu, 0x2, DMFC_IC_CTRL);
+	} else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
+		dev_dbg(ipu->dev, "DMFC high resolution has set, will not change\n");
+		return;
+	} else
+		dmfc_type_setup = dmfc_type;
+
+	if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
+		/* 1 - segment 0~3;
+		 * 5B - segement 4, 5;
+		 * 5F - segement 6, 7;
+		 * 1C, 2C and 6B, 6F unused;
+		 */
+		dev_info(ipu->dev, "IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)\n");
+		dmfc_wr_chan = 0x00000088;
+		dmfc_dp_chan = 0x00009694;
+		ipu->dmfc_size_28 = 256*4;
+		ipu->dmfc_size_29 = 0;
+		ipu->dmfc_size_24 = 0;
+		ipu->dmfc_size_27 = 128*4;
+		ipu->dmfc_size_23 = 128*4;
+	} else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
+		/* 1 - segment 0, 1;
+		 * 5B - segement 2~5;
+		 * 5F - segement 6,7;
+		 * 1C, 2C and 6B, 6F unused;
+		 */
+		dev_info(ipu->dev, "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)\n");
+		dmfc_wr_chan = 0x00000090;
+		dmfc_dp_chan = 0x0000968a;
+		ipu->dmfc_size_28 = 128*4;
+		ipu->dmfc_size_29 = 0;
+		ipu->dmfc_size_24 = 0;
+		ipu->dmfc_size_27 = 128*4;
+		ipu->dmfc_size_23 = 256*4;
+	} else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
+		/* 5B - segement 0~3;
+		 * 5F - segement 4~7;
+		 * 1, 1C, 2C and 6B, 6F unused;
+		 */
+		dev_info(ipu->dev, "IPU DMFC ONLY-DP HIGH RESOLUTION: 5B(0~3), 5F(4~7)\n");
+		dmfc_wr_chan = 0x00000000;
+		dmfc_dp_chan = 0x00008c88;
+		ipu->dmfc_size_28 = 0;
+		ipu->dmfc_size_29 = 0;
+		ipu->dmfc_size_24 = 0;
+		ipu->dmfc_size_27 = 256*4;
+		ipu->dmfc_size_23 = 256*4;
+	} else {
+		/* 1 - segment 0, 1;
+		 * 5B - segement 4, 5;
+		 * 5F - segement 6, 7;
+		 * 1C, 2C and 6B, 6F unused;
+		 */
+		dev_info(ipu->dev, "IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
+		dmfc_wr_chan = 0x00000090;
+		dmfc_dp_chan = 0x00009694;
+		ipu->dmfc_size_28 = 128*4;
+		ipu->dmfc_size_29 = 0;
+		ipu->dmfc_size_24 = 0;
+		ipu->dmfc_size_27 = 128*4;
+		ipu->dmfc_size_23 = 128*4;
+	}
+	ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
+	ipu_dmfc_write(ipu, 0x202020F6, DMFC_WR_CHAN_DEF);
+	ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
+	/* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
+	ipu_dmfc_write(ipu, 0x2020F6F6, DMFC_DP_CHAN_DEF);
+}
+
+static int __init dmfc_setup(char *options)
+{
+	get_option(&options, &dmfc_type_setup);
+	if (dmfc_type_setup > DMFC_HIGH_RESOLUTION_ONLY_DP)
+		dmfc_type_setup = DMFC_HIGH_RESOLUTION_ONLY_DP;
+	return 1;
+}
+__setup("dmfc=", dmfc_setup);
+
+void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width)
+{
+	u32 dmfc_gen1 = ipu_dmfc_read(ipu, DMFC_GENERAL1);
+
+	if (width >= HIGH_RESOLUTION_WIDTH) {
+		if (dma_chan == 23)
+			_ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DP, 0);
+		else if (dma_chan == 28)
+			_ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DC, 0);
+	}
+
+	if (dma_chan == 23) { /*5B*/
+		if (ipu->dmfc_size_23/width > 3)
+			dmfc_gen1 |= 1UL << 20;
+		else
+			dmfc_gen1 &= ~(1UL << 20);
+	} else if (dma_chan == 24) { /*6B*/
+		if (ipu->dmfc_size_24/width > 1)
+			dmfc_gen1 |= 1UL << 22;
+		else
+			dmfc_gen1 &= ~(1UL << 22);
+	} else if (dma_chan == 27) { /*5F*/
+		if (ipu->dmfc_size_27/width > 2)
+			dmfc_gen1 |= 1UL << 21;
+		else
+			dmfc_gen1 &= ~(1UL << 21);
+	} else if (dma_chan == 28) { /*1*/
+		if (ipu->dmfc_size_28/width > 2)
+			dmfc_gen1 |= 1UL << 16;
+		else
+			dmfc_gen1 &= ~(1UL << 16);
+	} else if (dma_chan == 29) { /*6F*/
+		if (ipu->dmfc_size_29/width > 1)
+			dmfc_gen1 |= 1UL << 23;
+		else
+			dmfc_gen1 &= ~(1UL << 23);
+	}
+
+	ipu_dmfc_write(ipu, dmfc_gen1, DMFC_GENERAL1);
+}
+
+void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size)
+{
+	u32 dmfc_wr_chan = ipu_dmfc_read(ipu, DMFC_WR_CHAN);
+	u32 dmfc_dp_chan = ipu_dmfc_read(ipu, DMFC_DP_CHAN);
+	int dmfc_bs = 0;
+
+	switch (burst_size) {
+	case 64:
+		dmfc_bs = 0x40;
+		break;
+	case 32:
+	case 20:
+		dmfc_bs = 0x80;
+		break;
+	case 16:
+		dmfc_bs = 0xc0;
+		break;
+	default:
+		dev_err(ipu->dev, "Unsupported burst size %d\n",
+			burst_size);
+		return;
+	}
+
+	if (dma_chan == 23) { /*5B*/
+		dmfc_dp_chan &= ~(0xc0);
+		dmfc_dp_chan |= dmfc_bs;
+	} else if (dma_chan == 27) { /*5F*/
+		dmfc_dp_chan &= ~(0xc000);
+		dmfc_dp_chan |= (dmfc_bs << 8);
+	} else if (dma_chan == 28) { /*1*/
+		dmfc_wr_chan &= ~(0xc0);
+		dmfc_wr_chan |= dmfc_bs;
+	}
+
+	ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
+	ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
+}
+
+static void _ipu_di_data_wave_config(struct ipu_soc *ipu,
+				int di, int wave_gen,
+				int access_size, int component_size)
+{
+	u32 reg;
+	reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
+	    (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
+	ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
+}
+
+static void _ipu_di_data_pin_config(struct ipu_soc *ipu,
+			int di, int wave_gen, int di_pin, int set,
+			int up, int down)
+{
+	u32 reg;
+
+	reg = ipu_di_read(ipu, di, DI_DW_GEN(wave_gen));
+	reg &= ~(0x3 << (di_pin * 2));
+	reg |= set << (di_pin * 2);
+	ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
+
+	ipu_di_write(ipu, di, (down << 16) | up, DI_DW_SET(wave_gen, set));
+}
+
+static void _ipu_di_sync_config(struct ipu_soc *ipu,
+				int di, int wave_gen,
+				int run_count, int run_src,
+				int offset_count, int offset_src,
+				int repeat_count, int cnt_clr_src,
+				int cnt_polarity_gen_en,
+				int cnt_polarity_clr_src,
+				int cnt_polarity_trigger_src,
+				int cnt_up, int cnt_down)
+{
+	u32 reg;
+
+	if ((run_count >= 0x1000) || (offset_count >= 0x1000) || (repeat_count >= 0x1000) ||
+		(cnt_up >= 0x400) || (cnt_down >= 0x400)) {
+		dev_err(ipu->dev, "DI%d counters out of range.\n", di);
+		return;
+	}
+
+	reg = (run_count << 19) | (++run_src << 16) |
+	    (offset_count << 3) | ++offset_src;
+	ipu_di_write(ipu, di, reg, DI_SW_GEN0(wave_gen));
+	reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
+	    (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
+	reg |= (cnt_down << 16) | cnt_up;
+	if (repeat_count == 0) {
+		/* Enable auto reload */
+		reg |= 0x10000000;
+	}
+	ipu_di_write(ipu, di, reg, DI_SW_GEN1(wave_gen));
+	reg = ipu_di_read(ipu, di, DI_STP_REP(wave_gen));
+	reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
+	reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
+	ipu_di_write(ipu, di, reg, DI_STP_REP(wave_gen));
+}
+
+static void _ipu_dc_map_link(struct ipu_soc *ipu,
+		int current_map,
+		int base_map_0, int buf_num_0,
+		int base_map_1, int buf_num_1,
+		int base_map_2, int buf_num_2)
+{
+	int ptr_0 = base_map_0 * 3 + buf_num_0;
+	int ptr_1 = base_map_1 * 3 + buf_num_1;
+	int ptr_2 = base_map_2 * 3 + buf_num_2;
+	int ptr;
+	u32 reg;
+	ptr = (ptr_2 << 10) +  (ptr_1 << 5) + ptr_0;
+
+	reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(current_map));
+	reg &= ~(0x1F << ((16 * (current_map & 0x1))));
+	reg |= ptr << ((16 * (current_map & 0x1)));
+	ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(current_map));
+}
+
+static void _ipu_dc_map_config(struct ipu_soc *ipu,
+		int map, int byte_num, int offset, int mask)
+{
+	int ptr = map * 3 + byte_num;
+	u32 reg;
+
+	reg = ipu_dc_read(ipu, DC_MAP_CONF_VAL(ptr));
+	reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
+	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
+	ipu_dc_write(ipu, reg, DC_MAP_CONF_VAL(ptr));
+
+	reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
+	reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
+	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
+	ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(map));
+}
+
+static void _ipu_dc_map_clear(struct ipu_soc *ipu, int map)
+{
+	u32 reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
+	ipu_dc_write(ipu, reg & ~(0xFFFF << (16 * (map & 0x1))),
+		     DC_MAP_CONF_PTR(map));
+}
+
+static void _ipu_dc_write_tmpl(struct ipu_soc *ipu,
+			int word, u32 opcode, u32 operand, int map,
+			int wave, int glue, int sync, int stop)
+{
+	u32 reg;
+
+	if (opcode == WRG) {
+		reg = sync;
+		reg |= (glue << 4);
+		reg |= (++wave << 11);
+		reg |= ((operand & 0x1FFFF) << 15);
+		ipu_dc_tmpl_write(ipu, reg, word * 2);
+
+		reg = (operand >> 17);
+		reg |= opcode << 7;
+		reg |= (stop << 9);
+		ipu_dc_tmpl_write(ipu, reg, word * 2 + 1);
+	} else {
+		reg = sync;
+		reg |= (glue << 4);
+		reg |= (++wave << 11);
+		reg |= (++map << 15);
+		reg |= (operand << 20) & 0xFFF00000;
+		ipu_dc_tmpl_write(ipu, reg, word * 2);
+
+		reg = (operand >> 12);
+		reg |= opcode << 4;
+		reg |= (stop << 9);
+		ipu_dc_tmpl_write(ipu, reg, word * 2 + 1);
+	}
+}
+
+static void _ipu_dc_link_event(struct ipu_soc *ipu,
+		int chan, int event, int addr, int priority)
+{
+	u32 reg;
+	u32 address_shift;
+	if (event < DC_EVEN_UGDE0) {
+		reg = ipu_dc_read(ipu, DC_RL_CH(chan, event));
+		reg &= ~(0xFFFF << (16 * (event & 0x1)));
+		reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
+		ipu_dc_write(ipu, reg, DC_RL_CH(chan, event));
+	} else {
+		reg = ipu_dc_read(ipu, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
+		if ((event - DC_EVEN_UGDE0) & 0x1) {
+			reg &= ~(0x2FF << 16);
+			reg |= (addr << 16);
+			reg |= priority ? (2 << 24) : 0x0;
+		} else {
+			reg &= ~0xFC00FFFF;
+			if (priority)
+				chan = (chan >> 1) +
+					((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3));
+			else
+				chan = 0x7;
+			address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8;
+			reg |= (addr << address_shift) | (priority << 3) | chan;
+		}
+		ipu_dc_write(ipu, reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
+	}
+}
+
+/*     Y = R *  1.200 + G *  2.343 + B *  .453 + 0.250;
+       U = R * -.672 + G * -1.328 + B *  2.000 + 512.250.;
+       V = R *  2.000 + G * -1.672 + B * -.328 + 512.250.;*/
+static const int rgb2ycbcr_coeff[5][3] = {
+	{0x4D, 0x96, 0x1D},
+	{-0x2B, -0x55, 0x80},
+	{0x80, -0x6B, -0x15},
+	{0x0000, 0x0200, 0x0200},	/* B0, B1, B2 */
+	{0x2, 0x2, 0x2},	/* S0, S1, S2 */
+};
+
+/*     R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
+       G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
+       B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
+static const int ycbcr2rgb_coeff[5][3] = {
+	{0x095, 0x000, 0x0CC},
+	{0x095, 0x3CE, 0x398},
+	{0x095, 0x0FF, 0x000},
+	{0x3E42, 0x010A, 0x3DD6},	/*B0,B1,B2 */
+	{0x1, 0x1, 0x1},	/*S0,S1,S2 */
+};
+
+#define mask_a(a) ((u32)(a) & 0x3FF)
+#define mask_b(b) ((u32)(b) & 0x3FFF)
+
+/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
+static int _rgb_to_yuv(int n, int red, int green, int blue)
+{
+	int c;
+	c = red * rgb2ycbcr_coeff[n][0];
+	c += green * rgb2ycbcr_coeff[n][1];
+	c += blue * rgb2ycbcr_coeff[n][2];
+	c /= 16;
+	c += rgb2ycbcr_coeff[3][n] * 4;
+	c += 8;
+	c /= 16;
+	if (c < 0)
+		c = 0;
+	if (c > 255)
+		c = 255;
+	return c;
+}
+
+/*
+ * Row is for BG: 	RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
+ * Column is for FG:	RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
+ */
+static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
+{{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} },
+{{0, 0}, {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} },
+{{0, 0}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} },
+{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
+{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} }
+};
+
+void __ipu_dp_csc_setup(struct ipu_soc *ipu,
+		int dp, struct dp_csc_param_t dp_csc_param,
+		bool srm_mode_update)
+{
+	u32 reg;
+	const int (*coeff)[5][3];
+
+	if (dp_csc_param.mode >= 0) {
+		reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
+		reg &= ~DP_COM_CONF_CSC_DEF_MASK;
+		reg |= dp_csc_param.mode;
+		ipu_dp_write(ipu, reg, DP_COM_CONF(dp));
+	}
+
+	coeff = dp_csc_param.coeff;
+
+	if (coeff) {
+		ipu_dp_write(ipu, mask_a((*coeff)[0][0]) |
+				(mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
+		ipu_dp_write(ipu, mask_a((*coeff)[0][2]) |
+				(mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
+		ipu_dp_write(ipu, mask_a((*coeff)[1][1]) |
+				(mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
+		ipu_dp_write(ipu, mask_a((*coeff)[2][0]) |
+				(mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
+		ipu_dp_write(ipu, mask_a((*coeff)[2][2]) |
+				(mask_b((*coeff)[3][0]) << 16) |
+				((*coeff)[4][0] << 30), DP_CSC_0(dp));
+		ipu_dp_write(ipu, mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
+				(mask_b((*coeff)[3][2]) << 16) |
+				((*coeff)[4][2] << 30), DP_CSC_1(dp));
+	}
+
+	if (srm_mode_update) {
+		reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
+		ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+	}
+}
+
+int _ipu_dp_init(struct ipu_soc *ipu,
+		ipu_channel_t channel, uint32_t in_pixel_fmt,
+		uint32_t out_pixel_fmt)
+{
+	int in_fmt, out_fmt;
+	int dp;
+	int partial = false;
+	uint32_t reg;
+
+	if (channel == MEM_FG_SYNC) {
+		dp = DP_SYNC;
+		partial = true;
+	} else if (channel == MEM_BG_SYNC) {
+		dp = DP_SYNC;
+		partial = false;
+	} else if (channel == MEM_BG_ASYNC0) {
+		dp = DP_ASYNC0;
+		partial = false;
+	} else {
+		return -EINVAL;
+	}
+
+	in_fmt = format_to_colorspace(in_pixel_fmt);
+	out_fmt = format_to_colorspace(out_pixel_fmt);
+
+	if (partial) {
+		if (in_fmt == RGB) {
+			if (out_fmt == RGB)
+				ipu->fg_csc_type = RGB2RGB;
+			else
+				ipu->fg_csc_type = RGB2YUV;
+		} else {
+			if (out_fmt == RGB)
+				ipu->fg_csc_type = YUV2RGB;
+			else
+				ipu->fg_csc_type = YUV2YUV;
+		}
+	} else {
+		if (in_fmt == RGB) {
+			if (out_fmt == RGB)
+				ipu->bg_csc_type = RGB2RGB;
+			else
+				ipu->bg_csc_type = RGB2YUV;
+		} else {
+			if (out_fmt == RGB)
+				ipu->bg_csc_type = YUV2RGB;
+			else
+				ipu->bg_csc_type = YUV2YUV;
+		}
+	}
+
+	/* Transform color key from rgb to yuv if CSC is enabled */
+	reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
+	if (ipu->color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
+			(((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
+			 ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
+			 ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
+			 ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB)))) {
+		int red, green, blue;
+		int y, u, v;
+		uint32_t color_key = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFFFFFFL;
+
+		dev_dbg(ipu->dev, "_ipu_dp_init color key 0x%x need change to yuv fmt!\n", color_key);
+
+		red = (color_key >> 16) & 0xFF;
+		green = (color_key >> 8) & 0xFF;
+		blue = color_key & 0xFF;
+
+		y = _rgb_to_yuv(0, red, green, blue);
+		u = _rgb_to_yuv(1, red, green, blue);
+		v = _rgb_to_yuv(2, red, green, blue);
+		color_key = (y << 16) | (u << 8) | v;
+
+		reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
+		ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(dp));
+		ipu->color_key_4rgb = false;
+
+		dev_dbg(ipu->dev, "_ipu_dp_init color key change to yuv fmt 0x%x!\n", color_key);
+	}
+
+	__ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], true);
+
+	return 0;
+}
+
+void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel)
+{
+	int dp;
+	int partial = false;
+
+	if (channel == MEM_FG_SYNC) {
+		dp = DP_SYNC;
+		partial = true;
+	} else if (channel == MEM_BG_SYNC) {
+		dp = DP_SYNC;
+		partial = false;
+	} else if (channel == MEM_BG_ASYNC0) {
+		dp = DP_ASYNC0;
+		partial = false;
+	} else {
+		return;
+	}
+
+	if (partial)
+		ipu->fg_csc_type = CSC_NONE;
+	else
+		ipu->bg_csc_type = CSC_NONE;
+
+	__ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], false);
+}
+
+void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
+{
+	u32 reg = 0;
+
+	if ((dc_chan == 1) || (dc_chan == 5)) {
+		if (interlaced) {
+			_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 3);
+			_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 2);
+			_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 1);
+		} else {
+			if (di) {
+				_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 2, 3);
+				_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 3, 2);
+				_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 4, 1);
+				if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+					_ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 9, 5);
+					_ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 8, 5);
+				}
+			} else {
+				_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 5, 3);
+				_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 6, 2);
+				_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 7, 1);
+				if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+					_ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 10, 5);
+					_ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 11, 5);
+				}
+			}
+		}
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
+
+		reg = 0x2;
+		reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
+		reg |= di << 2;
+		if (interlaced)
+			reg |= DC_WR_CH_CONF_FIELD_MODE;
+	} else if ((dc_chan == 8) || (dc_chan == 9)) {
+		/* async channels */
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
+
+		reg = 0x3;
+		reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
+	}
+	ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
+
+	ipu_dc_write(ipu, 0x00000000, DC_WR_CH_ADDR(dc_chan));
+
+	ipu_dc_write(ipu, 0x00000084, DC_GEN);
+}
+
+void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan)
+{
+	if ((dc_chan == 1) || (dc_chan == 5)) {
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 0, 0);
+	} else if ((dc_chan == 8) || (dc_chan == 9)) {
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
+		_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
+	}
+}
+
+int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel)
+{
+	if (channel == MEM_DC_SYNC)
+		return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_1) &
+			  DC_WR_CH_CONF_FIELD_MODE);
+	else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
+		return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_5) &
+			  DC_WR_CH_CONF_FIELD_MODE);
+	return 0;
+}
+
+void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel)
+{
+	int di;
+	uint32_t reg;
+	uint32_t dc_chan;
+	int irq = 0;
+
+	if (channel == MEM_FG_SYNC)
+		irq = IPU_IRQ_DP_SF_END;
+	else if (channel == MEM_DC_SYNC)
+		dc_chan = 1;
+	else if (channel == MEM_BG_SYNC)
+		dc_chan = 5;
+	else
+		return;
+
+	if (channel == MEM_FG_SYNC) {
+		/* Enable FG channel */
+		reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
+		ipu_dp_write(ipu, reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
+
+		reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
+		ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+		return;
+	}
+
+	di = ipu->dc_di_assignment[dc_chan];
+
+	/* Make sure other DC sync channel is not assigned same DI */
+	reg = ipu_dc_read(ipu, DC_WR_CH_CONF(6 - dc_chan));
+	if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
+		reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
+		reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
+		ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
+	}
+
+	reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
+	reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
+	ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
+
+	clk_enable(&ipu->pixel_clk[di]);
+}
+
+static irqreturn_t dc_irq_handler(int irq, void *dev_id)
+{
+	struct ipu_soc *ipu = dev_id;
+	struct completion *comp = &ipu->dc_comp;
+	uint32_t reg;
+	uint32_t dc_chan;
+
+	if (irq == IPU_IRQ_DC_FC_1)
+		dc_chan = 1;
+	else
+		dc_chan = 5;
+
+	if (!ipu->dc_swap) {
+		reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
+		reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
+		ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
+
+		reg = ipu_cm_read(ipu, IPU_DISP_GEN);
+		if (ipu->dc_di_assignment[dc_chan])
+			reg &= ~DI1_COUNTER_RELEASE;
+		else
+			reg &= ~DI0_COUNTER_RELEASE;
+		ipu_cm_write(ipu, reg, IPU_DISP_GEN);
+	}
+
+	complete(comp);
+	return IRQ_HANDLED;
+}
+
+void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap)
+{
+	int ret;
+	uint32_t reg;
+	uint32_t csc;
+	uint32_t dc_chan;
+	int irq = 0;
+	int timeout = 50;
+
+	ipu->dc_swap = swap;
+
+	if (channel == MEM_DC_SYNC) {
+		dc_chan = 1;
+		irq = IPU_IRQ_DC_FC_1;
+	} else if (channel == MEM_BG_SYNC) {
+		dc_chan = 5;
+		irq = IPU_IRQ_DP_SF_END;
+	} else if (channel == MEM_FG_SYNC) {
+		/* Disable FG channel */
+		dc_chan = 5;
+
+		reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
+		csc = reg & DP_COM_CONF_CSC_DEF_MASK;
+		if (csc == DP_COM_CONF_CSC_DEF_FG)
+			reg &= ~DP_COM_CONF_CSC_DEF_MASK;
+
+		reg &= ~DP_COM_CONF_FG_EN;
+		ipu_dp_write(ipu, reg, DP_COM_CONF(DP_SYNC));
+
+		reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
+		ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+
+		if (ipu_is_channel_busy(ipu, MEM_BG_SYNC)) {
+			ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
+					IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END));
+			while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) &
+						IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
+				msleep(2);
+				timeout -= 2;
+				if (timeout <= 0)
+					break;
+			}
+		}
+		return;
+	} else {
+		return;
+	}
+
+	init_completion(&ipu->dc_comp);
+	ret = ipu_request_irq(ipu, irq, dc_irq_handler, 0, NULL, ipu);
+	if (ret < 0) {
+		dev_err(ipu->dev, "DC irq %d in use\n", irq);
+		return;
+	}
+	ret = wait_for_completion_timeout(&ipu->dc_comp, msecs_to_jiffies(50));
+	ipu_free_irq(ipu, irq, ipu);
+	dev_dbg(ipu->dev, "DC stop timeout - %d * 10ms\n", 5 - ret);
+
+	if (ipu->dc_swap) {
+		/* Swap DC channel 1 and 5 settings, and disable old dc chan */
+		reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
+		ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
+		reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
+		reg ^= DC_WR_CH_CONF_PROG_DI_ID;
+		ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
+	} else
+		/* Clock is already off because it must be done quickly, but
+		   we need to fix the ref count */
+		clk_disable(&ipu->pixel_clk[ipu->dc_di_assignment[dc_chan]]);
+}
+
+void _ipu_init_dc_mappings(struct ipu_soc *ipu)
+{
+	/* IPU_PIX_FMT_RGB24 */
+	_ipu_dc_map_clear(ipu, 0);
+	_ipu_dc_map_config(ipu, 0, 0, 7, 0xFF);
+	_ipu_dc_map_config(ipu, 0, 1, 15, 0xFF);
+	_ipu_dc_map_config(ipu, 0, 2, 23, 0xFF);
+
+	/* IPU_PIX_FMT_RGB666 */
+	_ipu_dc_map_clear(ipu, 1);
+	_ipu_dc_map_config(ipu, 1, 0, 5, 0xFC);
+	_ipu_dc_map_config(ipu, 1, 1, 11, 0xFC);
+	_ipu_dc_map_config(ipu, 1, 2, 17, 0xFC);
+
+	/* IPU_PIX_FMT_YUV444 */
+	_ipu_dc_map_clear(ipu, 2);
+	_ipu_dc_map_config(ipu, 2, 0, 15, 0xFF);
+	_ipu_dc_map_config(ipu, 2, 1, 23, 0xFF);
+	_ipu_dc_map_config(ipu, 2, 2, 7, 0xFF);
+
+	/* IPU_PIX_FMT_RGB565 */
+	_ipu_dc_map_clear(ipu, 3);
+	_ipu_dc_map_config(ipu, 3, 0, 4, 0xF8);
+	_ipu_dc_map_config(ipu, 3, 1, 10, 0xFC);
+	_ipu_dc_map_config(ipu, 3, 2, 15, 0xF8);
+
+	/* IPU_PIX_FMT_LVDS666 */
+	_ipu_dc_map_clear(ipu, 4);
+	_ipu_dc_map_config(ipu, 4, 0, 5, 0xFC);
+	_ipu_dc_map_config(ipu, 4, 1, 13, 0xFC);
+	_ipu_dc_map_config(ipu, 4, 2, 21, 0xFC);
+
+	/* IPU_PIX_FMT_VYUY 16bit width */
+	_ipu_dc_map_clear(ipu, 5);
+	_ipu_dc_map_config(ipu, 5, 0, 7, 0xFF);
+	_ipu_dc_map_config(ipu, 5, 1, 0, 0x0);
+	_ipu_dc_map_config(ipu, 5, 2, 15, 0xFF);
+	_ipu_dc_map_clear(ipu, 6);
+	_ipu_dc_map_config(ipu, 6, 0, 0, 0x0);
+	_ipu_dc_map_config(ipu, 6, 1, 7, 0xFF);
+	_ipu_dc_map_config(ipu, 6, 2, 15, 0xFF);
+
+	/* IPU_PIX_FMT_UYUV 16bit width */
+	_ipu_dc_map_clear(ipu, 7);
+	_ipu_dc_map_link(ipu, 7, 6, 0, 6, 1, 6, 2);
+	_ipu_dc_map_clear(ipu, 8);
+	_ipu_dc_map_link(ipu, 8, 5, 0, 5, 1, 5, 2);
+
+	/* IPU_PIX_FMT_YUYV 16bit width */
+	_ipu_dc_map_clear(ipu, 9);
+	_ipu_dc_map_link(ipu, 9, 5, 2, 5, 1, 5, 0);
+	_ipu_dc_map_clear(ipu, 10);
+	_ipu_dc_map_link(ipu, 10, 5, 1, 5, 2, 5, 0);
+
+	/* IPU_PIX_FMT_YVYU 16bit width */
+	_ipu_dc_map_clear(ipu, 11);
+	_ipu_dc_map_link(ipu, 11, 5, 1, 5, 2, 5, 0);
+	_ipu_dc_map_clear(ipu, 12);
+	_ipu_dc_map_link(ipu, 12, 5, 2, 5, 1, 5, 0);
+
+	/* IPU_PIX_FMT_GBR24 */
+	/* IPU_PIX_FMT_VYU444 */
+	_ipu_dc_map_clear(ipu, 13);
+	_ipu_dc_map_link(ipu, 13, 0, 2, 0, 0, 0, 1);
+
+	/* IPU_PIX_FMT_BGR24 */
+	_ipu_dc_map_clear(ipu, 14);
+	_ipu_dc_map_link(ipu, 14, 0, 2, 0, 1, 0, 0);
+}
+
+int _ipu_pixfmt_to_map(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_GENERIC:
+	case IPU_PIX_FMT_RGB24:
+		return 0;
+	case IPU_PIX_FMT_RGB666:
+		return 1;
+	case IPU_PIX_FMT_YUV444:
+		return 2;
+	case IPU_PIX_FMT_RGB565:
+		return 3;
+	case IPU_PIX_FMT_LVDS666:
+		return 4;
+	case IPU_PIX_FMT_VYUY:
+		return 6;
+	case IPU_PIX_FMT_UYVY:
+		return 8;
+	case IPU_PIX_FMT_YUYV:
+		return 10;
+	case IPU_PIX_FMT_YVYU:
+		return 12;
+	case IPU_PIX_FMT_GBR24:
+	case IPU_PIX_FMT_VYU444:
+		return 13;
+	case IPU_PIX_FMT_BGR24:
+		return 14;
+	}
+
+	return -1;
+}
+
+/*!
+ * This function sets the colorspace for of dp.
+ * modes.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       param         	If it's not NULL, update the csc table
+ *                              with this parameter.
+ *
+ * @return      N/A
+ */
+void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
+{
+	int dp;
+	struct dp_csc_param_t dp_csc_param;
+
+	if (channel == MEM_FG_SYNC)
+		dp = DP_SYNC;
+	else if (channel == MEM_BG_SYNC)
+		dp = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0)
+		dp = DP_ASYNC0;
+	else
+		return;
+
+	dp_csc_param.mode = -1;
+	dp_csc_param.coeff = param;
+	__ipu_dp_csc_setup(ipu, dp, dp_csc_param, true);
+}
+
+void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
+{
+	_ipu_dp_set_csc_coefficients(ipu, channel, param);
+}
+EXPORT_SYMBOL(ipu_set_csc_coefficients);
+
+/*!
+ * This function is called to adapt synchronous LCD panel to IPU restriction.
+ *
+ */
+void adapt_panel_to_ipu_restricitions(struct ipu_soc *ipu, uint16_t *v_start_width,
+					uint16_t *v_sync_width,
+					uint16_t *v_end_width)
+{
+	if (*v_end_width < 2) {
+		uint16_t diff = 2 - *v_end_width;
+		if (*v_start_width >= diff) {
+			*v_end_width = 2;
+			*v_start_width = *v_start_width - diff;
+		} else if (*v_sync_width > diff) {
+			*v_end_width = 2;
+			*v_sync_width = *v_sync_width - diff;
+		} else
+			dev_err(ipu->dev, "WARNING: try to adapt timming, but failed\n");
+		dev_err(ipu->dev, "WARNING: adapt panel end blank lines\n");
+	}
+}
+
+/*!
+ * This function is called to initialize a synchronous LCD panel.
+ *
+ * @param	ipu		ipu handler
+ * @param       disp            The DI the panel is attached to.
+ *
+ * @param       pixel_clk       Desired pixel clock frequency in Hz.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer.
+ *                              Pixel format is a FOURCC ASCII code.
+ *
+ * @param       width           The width of panel in pixels.
+ *
+ * @param       height          The height of panel in pixels.
+ *
+ * @param       hStartWidth     The number of pixel clocks between the HSYNC
+ *                              signal pulse and the start of valid data.
+ *
+ * @param       hSyncWidth      The width of the HSYNC signal in units of pixel
+ *                              clocks.
+ *
+ * @param       hEndWidth       The number of pixel clocks between the end of
+ *                              valid data and the HSYNC signal for next line.
+ *
+ * @param       vStartWidth     The number of lines between the VSYNC
+ *                              signal pulse and the start of valid data.
+ *
+ * @param       vSyncWidth      The width of the VSYNC signal in units of lines
+ *
+ * @param       vEndWidth       The number of lines between the end of valid
+ *                              data and the VSYNC signal for next frame.
+ *
+ * @param       sig             Bitfield of signal polarities for LCD interface.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
+			    uint16_t width, uint16_t height,
+			    uint32_t pixel_fmt,
+			    uint16_t h_start_width, uint16_t h_sync_width,
+			    uint16_t h_end_width, uint16_t v_start_width,
+			    uint16_t v_sync_width, uint16_t v_end_width,
+			    uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
+{
+	uint32_t field0_offset = 0;
+	uint32_t field1_offset;
+	uint32_t reg;
+	uint32_t di_gen, vsync_cnt;
+	uint32_t div, rounded_pixel_clk, rounded_parent_clk;
+	uint32_t h_total, v_total;
+	int map;
+	struct clk *di_parent;
+
+	dev_dbg(ipu->dev, "panel size = %d x %d\n", width, height);
+
+	if ((v_sync_width == 0) || (h_sync_width == 0))
+		return EINVAL;
+
+	adapt_panel_to_ipu_restricitions(ipu, &v_start_width, &v_sync_width, &v_end_width);
+	h_total = width + h_sync_width + h_start_width + h_end_width;
+	v_total = height + v_sync_width + v_start_width + v_end_width;
+
+	/* Init clocking */
+	dev_dbg(ipu->dev, "pixel clk = %d\n", pixel_clk);
+
+	di_parent = clk_get_parent(ipu->di_clk[disp]);
+	if (clk_get(NULL, "tve_clk") == di_parent ||
+		clk_get(NULL, "ldb_di0_clk") == di_parent ||
+		clk_get(NULL, "ldb_di1_clk") == di_parent) {
+		/* if di clk parent is tve/ldb, then keep it;*/
+		dev_dbg(ipu->dev, "use special clk parent\n");
+		clk_set_parent(&ipu->pixel_clk[disp], ipu->di_clk[disp]);
+	} else {
+		/* try ipu clk first*/
+		dev_dbg(ipu->dev, "try ipu internal clk\n");
+		clk_set_parent(&ipu->pixel_clk[disp], ipu->ipu_clk);
+		rounded_pixel_clk = clk_round_rate(&ipu->pixel_clk[disp], pixel_clk);
+		/*
+		 * we will only use 1/2 fraction for ipu clk,
+		 * so if the clk rate is not fit, try ext clk.
+		 */
+		if (!sig.int_clk &&
+			((rounded_pixel_clk >= pixel_clk + pixel_clk/200) ||
+			(rounded_pixel_clk <= pixel_clk - pixel_clk/200))) {
+			dev_dbg(ipu->dev, "try ipu ext di clk\n");
+			if (clk_get_usecount(di_parent))
+				dev_warn(ipu->dev,
+					"ext di clk already in use, go back to internal clk\n");
+			else {
+				rounded_pixel_clk = pixel_clk * 2;
+				rounded_parent_clk = clk_round_rate(di_parent,
+							rounded_pixel_clk);
+				while (rounded_pixel_clk < rounded_parent_clk) {
+					/* the max divider from parent to di is 8 */
+					if (rounded_parent_clk / pixel_clk < 8)
+						rounded_pixel_clk += pixel_clk * 2;
+					else
+						rounded_pixel_clk *= 2;
+				}
+				clk_set_rate(di_parent, rounded_pixel_clk);
+				rounded_pixel_clk =
+					clk_round_rate(ipu->di_clk[disp], pixel_clk);
+				clk_set_rate(ipu->di_clk[disp], rounded_pixel_clk);
+				clk_set_parent(&ipu->pixel_clk[disp], ipu->di_clk[disp]);
+			}
+		}
+	}
+	rounded_pixel_clk = clk_round_rate(&ipu->pixel_clk[disp], pixel_clk);
+	clk_set_rate(&ipu->pixel_clk[disp], rounded_pixel_clk);
+	msleep(5);
+	/* Get integer portion of divider */
+	div = clk_get_rate(clk_get_parent(&ipu->pixel_clk[disp])) / rounded_pixel_clk;
+
+	_ipu_lock(ipu);
+
+	_ipu_di_data_wave_config(ipu, disp, SYNC_WAVE, div - 1, div - 1);
+	_ipu_di_data_pin_config(ipu, disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
+
+	map = _ipu_pixfmt_to_map(pixel_fmt);
+	if (map < 0) {
+		dev_dbg(ipu->dev, "IPU_DISP: No MAP\n");
+		_ipu_unlock(ipu);
+		return -EINVAL;
+	}
+
+	/*clear DI*/
+	di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
+	ipu_di_write(ipu, disp,
+		di_gen & (0x3 << 20), DI_GENERAL);
+
+	if (sig.interlaced) {
+		if (g_ipu_hw_rev >= 2) {
+			/* Setup internal HSYNC waveform */
+			_ipu_di_sync_config(ipu,
+					disp, 		/* display */
+					1, 		/* counter */
+					h_total/2 - 1, 	/* run count */
+					DI_SYNC_CLK,	/* run_resolution */
+					0, 		/* offset */
+					DI_SYNC_NONE, 	/* offset resolution */
+					0, 		/* repeat count */
+					DI_SYNC_NONE, 	/* CNT_CLR_SEL */
+					0, 		/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 		/* COUNT UP */
+					0		/* COUNT DOWN */
+					);
+
+			/* Field 1 VSYNC waveform */
+			_ipu_di_sync_config(ipu,
+					disp, 		/* display */
+					2, 		/* counter */
+					h_total - 1, 	/* run count */
+					DI_SYNC_CLK,	/* run_resolution */
+					0, 		/* offset */
+					DI_SYNC_NONE, 	/* offset resolution */
+					0, 		/* repeat count */
+					DI_SYNC_NONE, 	/* CNT_CLR_SEL */
+					0, 		/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 		/* COUNT UP */
+					2*div		/* COUNT DOWN */
+					);
+
+			/* Setup internal HSYNC waveform */
+			_ipu_di_sync_config(ipu,
+					disp, 		/* display */
+					3, 		/* counter */
+					v_total*2 - 1, 	/* run count */
+					DI_SYNC_INT_HSYNC,	/* run_resolution */
+					1, 			/* offset */
+					DI_SYNC_INT_HSYNC, 	/* offset resolution */
+					0, 		/* repeat count */
+					DI_SYNC_NONE, 	/* CNT_CLR_SEL */
+					0, 		/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 		/* COUNT UP */
+					2*div		/* COUNT DOWN */
+					);
+
+			/* Active Field ? */
+			_ipu_di_sync_config(ipu,
+					disp, 		/* display */
+					4, 		/* counter */
+					v_total/2 - 1, 	/* run count */
+					DI_SYNC_HSYNC,	/* run_resolution */
+					v_start_width, 	/*  offset */
+					DI_SYNC_HSYNC, 	/* offset resolution */
+					2, 		/* repeat count */
+					DI_SYNC_VSYNC, 	/* CNT_CLR_SEL */
+					0, 		/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 		/* COUNT UP */
+					0		/* COUNT DOWN */
+					);
+
+			/* Active Line */
+			_ipu_di_sync_config(ipu,
+					disp, 		/* display */
+					5, 		/* counter */
+					0, 		/* run count */
+					DI_SYNC_HSYNC,	/* run_resolution */
+					0, 		/*  offset */
+					DI_SYNC_NONE, 	/* offset resolution */
+					height/2, 	/* repeat count */
+					4, 		/* CNT_CLR_SEL */
+					0, 		/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 		/* COUNT UP */
+					0		/* COUNT DOWN */
+					);
+
+			/* Field 0 VSYNC waveform */
+			_ipu_di_sync_config(ipu,
+					disp, 		/* display */
+					6, 		/* counter */
+					v_total - 1, 	/* run count */
+					DI_SYNC_HSYNC,	/* run_resolution */
+					0, 		/* offset */
+					DI_SYNC_NONE, 	/* offset resolution */
+					0, 		/* repeat count */
+					DI_SYNC_NONE, 	/* CNT_CLR_SEL  */
+					0, 		/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 		/* COUNT UP */
+					0		/* COUNT DOWN */
+					);
+
+			/* DC VSYNC waveform */
+			vsync_cnt = 7;
+			_ipu_di_sync_config(ipu,
+					disp, 		/* display */
+					7, 		/* counter */
+					v_total/2 - 1, 	/* run count */
+					DI_SYNC_HSYNC,	/* run_resolution  */
+					9, 		/* offset  */
+					DI_SYNC_HSYNC, 	/* offset resolution */
+					2, 		/* repeat count */
+					DI_SYNC_VSYNC, 	/* CNT_CLR_SEL */
+					0, 		/* CNT_POLARITY_GEN_EN */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 		/* COUNT UP */
+					0		/* COUNT DOWN */
+					);
+
+			/* active pixel waveform */
+			_ipu_di_sync_config(ipu,
+					disp, 		/* display */
+					8, 		/* counter */
+					0, 		/* run count  */
+					DI_SYNC_CLK,	/* run_resolution */
+					h_start_width, 	/* offset  */
+					DI_SYNC_CLK, 	/* offset resolution */
+					width, 		/* repeat count  */
+					5, 		/* CNT_CLR_SEL  */
+					0, 		/* CNT_POLARITY_GEN_EN  */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL  */
+					0, 		/* COUNT UP  */
+					0		/* COUNT DOWN */
+					);
+
+			/* Second VSYNC */
+			_ipu_di_sync_config(ipu,
+					disp, 		/* display */
+					9, 		/* counter */
+					v_total - 1, 	/* run count */
+					DI_SYNC_INT_HSYNC,	/* run_resolution */
+					v_total/2, 		/* offset  */
+					DI_SYNC_INT_HSYNC, 	/* offset resolution  */
+					0, 		/* repeat count */
+					DI_SYNC_HSYNC, 	/* CNT_CLR_SEL */
+					0, 		/* CNT_POLARITY_GEN_EN  */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_CLR_SEL  */
+					DI_SYNC_NONE, 	/* CNT_POLARITY_TRIGGER_SEL */
+					0, 		/* COUNT UP */
+					2*div		/* COUNT DOWN */
+					);
+
+			/* set gentime select and tag sel */
+			reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
+			reg &= 0x1FFFFFFF;
+			reg |= (3-1)<<29 | 0x00008000;
+			ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
+
+			ipu_di_write(ipu, disp, v_total / 2 - 1, DI_SCR_CONF);
+
+			/* set y_sel = 1 */
+			di_gen |= 0x10000000;
+			di_gen |= DI_GEN_POLARITY_5;
+			di_gen |= DI_GEN_POLARITY_8;
+		} else {
+			/* Setup internal HSYNC waveform */
+			_ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,
+					0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+			field1_offset = v_sync_width + v_start_width + height / 2 +
+				v_end_width;
+			if (sig.odd_field_first) {
+				field0_offset = field1_offset - 1;
+				field1_offset = 0;
+			}
+			v_total += v_start_width + v_end_width;
+
+			/* Field 1 VSYNC waveform */
+			_ipu_di_sync_config(ipu, disp, 2, v_total - 1, 1,
+					field0_offset,
+					field0_offset ? 1 : DI_SYNC_NONE,
+					0, DI_SYNC_NONE, 0,
+					DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
+
+			/* Setup internal HSYNC waveform */
+			_ipu_di_sync_config(ipu, disp, 3, h_total - 1, DI_SYNC_CLK,
+					0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0,
+					DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
+
+			/* Active Field ? */
+			_ipu_di_sync_config(ipu, disp, 4,
+					field0_offset ?
+					field0_offset : field1_offset - 2,
+					1, v_start_width + v_sync_width, 1, 2, 2,
+					0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
+
+			/* Active Line */
+			_ipu_di_sync_config(ipu, disp, 5, 0, 1,
+					0, DI_SYNC_NONE,
+					height / 2, 4, 0, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+			/* Field 0 VSYNC waveform */
+			_ipu_di_sync_config(ipu, disp, 6, v_total - 1, 1,
+					0, DI_SYNC_NONE,
+					0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+			/* DC VSYNC waveform */
+			vsync_cnt = 7;
+			_ipu_di_sync_config(ipu, disp, 7, 0, 1,
+					field1_offset,
+					field1_offset ? 1 : DI_SYNC_NONE,
+					1, 2, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
+
+			/* active pixel waveform */
+			_ipu_di_sync_config(ipu, disp, 8, 0, DI_SYNC_CLK,
+					h_sync_width + h_start_width, DI_SYNC_CLK,
+					width, 5, 0, DI_SYNC_NONE, DI_SYNC_NONE,
+					0, 0);
+
+			/* ??? */
+			_ipu_di_sync_config(ipu, disp, 9, v_total - 1, 2,
+					0, DI_SYNC_NONE,
+					0, DI_SYNC_NONE, 6, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+			reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
+			reg |= 0x8000;
+			ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
+
+			ipu_di_write(ipu, disp, v_sync_width + v_start_width +
+					v_end_width + height / 2 - 1, DI_SCR_CONF);
+		}
+
+		/* Init template microcode */
+		_ipu_dc_write_tmpl(ipu, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
+
+		if (sig.Hsync_pol)
+			di_gen |= DI_GEN_POLARITY_3;
+		if (sig.Vsync_pol)
+			di_gen |= DI_GEN_POLARITY_2;
+	} else {
+		/* Setup internal HSYNC waveform */
+		_ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,
+					0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
+					DI_SYNC_NONE, 0, 0);
+
+		/* Setup external (delayed) HSYNC waveform */
+		_ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1,
+				    DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
+				    0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
+				    DI_SYNC_CLK, 0, h_sync_width * 2);
+		/* Setup VSYNC waveform */
+		vsync_cnt = DI_SYNC_VSYNC;
+		_ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1,
+				    DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
+				    DI_SYNC_NONE, 1, DI_SYNC_NONE,
+				    DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
+		ipu_di_write(ipu, disp, v_total - 1, DI_SCR_CONF);
+
+		/* Setup active data waveform to sync with DC */
+		_ipu_di_sync_config(ipu, disp, 4, 0, DI_SYNC_HSYNC,
+				    v_sync_width + v_start_width, DI_SYNC_HSYNC, height,
+				    DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
+				    DI_SYNC_NONE, 0, 0);
+		_ipu_di_sync_config(ipu, disp, 5, 0, DI_SYNC_CLK,
+				    h_sync_width + h_start_width, DI_SYNC_CLK,
+				    width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
+				    0);
+
+		/* set VGA delayed hsync/vsync no matter VGA enabled */
+		if (disp) {
+			/* couter 7 for VGA delay HSYNC */
+			_ipu_di_sync_config(ipu, disp, 7,
+					h_total - 1, DI_SYNC_CLK,
+					18, DI_SYNC_CLK,
+					0, DI_SYNC_NONE,
+					1, DI_SYNC_NONE, DI_SYNC_CLK,
+					0, h_sync_width * 2);
+
+			/* couter 8 for VGA delay VSYNC */
+			_ipu_di_sync_config(ipu, disp, 8,
+					v_total - 1, DI_SYNC_INT_HSYNC,
+					1, DI_SYNC_INT_HSYNC,
+					0, DI_SYNC_NONE,
+					1, DI_SYNC_NONE, DI_SYNC_INT_HSYNC,
+					0, v_sync_width * 2);
+		}
+
+		/* reset all unused counters */
+		ipu_di_write(ipu, disp, 0, DI_SW_GEN0(6));
+		ipu_di_write(ipu, disp, 0, DI_SW_GEN1(6));
+		if (!disp) {
+			ipu_di_write(ipu, disp, 0, DI_SW_GEN0(7));
+			ipu_di_write(ipu, disp, 0, DI_SW_GEN1(7));
+			ipu_di_write(ipu, disp, 0, DI_STP_REP(7));
+			ipu_di_write(ipu, disp, 0, DI_SW_GEN0(8));
+			ipu_di_write(ipu, disp, 0, DI_SW_GEN1(8));
+			ipu_di_write(ipu, disp, 0, DI_STP_REP(8));
+		}
+		ipu_di_write(ipu, disp, 0, DI_SW_GEN0(9));
+		ipu_di_write(ipu, disp, 0, DI_SW_GEN1(9));
+		ipu_di_write(ipu, disp, 0, DI_STP_REP(9));
+
+		reg = ipu_di_read(ipu, disp, DI_STP_REP(6));
+		reg &= 0x0000FFFF;
+		ipu_di_write(ipu, disp, reg, DI_STP_REP(6));
+
+		/* Init template microcode */
+		if (disp) {
+			if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+				_ipu_dc_write_tmpl(ipu, 8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);
+				_ipu_dc_write_tmpl(ipu, 9, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
+				/* configure user events according to DISP NUM */
+				ipu_dc_write(ipu, (width - 1), DC_UGDE_3(disp));
+			}
+			_ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
+			_ipu_dc_write_tmpl(ipu, 3, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
+			_ipu_dc_write_tmpl(ipu, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
+		} else {
+			if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+				(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+				(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+				(pixel_fmt == IPU_PIX_FMT_VYUY)) {
+				_ipu_dc_write_tmpl(ipu, 10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);
+				_ipu_dc_write_tmpl(ipu, 11, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
+				/* configure user events according to DISP NUM */
+				ipu_dc_write(ipu, width - 1, DC_UGDE_3(disp));
+			}
+		   _ipu_dc_write_tmpl(ipu, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
+		   _ipu_dc_write_tmpl(ipu, 6, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
+		   _ipu_dc_write_tmpl(ipu, 7, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
+		}
+
+		if (sig.Hsync_pol) {
+			di_gen |= DI_GEN_POLARITY_2;
+			if (disp)
+				di_gen |= DI_GEN_POLARITY_7;
+		}
+		if (sig.Vsync_pol) {
+			di_gen |= DI_GEN_POLARITY_3;
+			if (disp)
+				di_gen |= DI_GEN_POLARITY_8;
+		}
+	}
+	/* changinc DISP_CLK polarity: it can be wrong for some applications */
+	if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
+		(pixel_fmt == IPU_PIX_FMT_UYVY) ||
+		(pixel_fmt == IPU_PIX_FMT_YVYU) ||
+		(pixel_fmt == IPU_PIX_FMT_VYUY))
+			di_gen |= 0x00020000;
+
+	if (!sig.clk_pol)
+		di_gen |= DI_GEN_POLARITY_DISP_CLK;
+
+	ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
+
+	ipu_di_write(ipu, disp, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
+			0x00000002, DI_SYNC_AS_GEN);
+	reg = ipu_di_read(ipu, disp, DI_POL);
+	reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
+	if (sig.enable_pol)
+		reg |= DI_POL_DRDY_POLARITY_15;
+	if (sig.data_pol)
+		reg |= DI_POL_DRDY_DATA_POLARITY;
+	ipu_di_write(ipu, disp, reg, DI_POL);
+
+	ipu_dc_write(ipu, width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
+
+	_ipu_unlock(ipu);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_init_sync_panel);
+
+void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp)
+{
+	uint32_t reg;
+	uint32_t di_gen;
+
+	if ((disp != 0) || (disp != 1))
+		return;
+
+	_ipu_lock(ipu);
+
+	di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
+	di_gen |= 0x3ff | DI_GEN_POLARITY_DISP_CLK;
+	ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
+
+	reg = ipu_di_read(ipu, disp, DI_POL);
+	reg |= 0x3ffffff;
+	ipu_di_write(ipu, disp, reg, DI_POL);
+
+	_ipu_unlock(ipu);
+}
+EXPORT_SYMBOL(ipu_uninit_sync_panel);
+
+int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
+			 uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig)
+{
+	int map;
+	u32 ser_conf = 0;
+	u32 div;
+	u32 di_clk = clk_get_rate(ipu->ipu_clk);
+
+	/* round up cycle_time, then calcalate the divider using scaled math */
+	cycle_time += (1000000000UL / di_clk) - 1;
+	div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL);
+
+	map = _ipu_pixfmt_to_map(pixel_fmt);
+	if (map < 0)
+		return -EINVAL;
+
+	_ipu_lock(ipu);
+
+	if (type == IPU_PANEL_SERIAL) {
+		ipu_di_write(ipu, disp, (div << 24) | ((sig.ifc_width - 1) << 4),
+			     DI_DW_GEN(ASYNC_SER_WAVE));
+
+		_ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_CS,
+					0, 0, (div * 2) + 1);
+		_ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_CLK,
+					1, div, div * 2);
+		_ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_RS,
+					2, 0, 0);
+
+		_ipu_dc_write_tmpl(ipu, 0x64, WROD(0), 0, map, ASYNC_SER_WAVE, 0, 0, 1);
+
+		/* Configure DC for serial panel */
+		ipu_dc_write(ipu, 0x14, DC_DISP_CONF1(DC_DISP_ID_SERIAL));
+
+		if (sig.clk_pol)
+			ser_conf |= DI_SER_CONF_SERIAL_CLK_POL;
+		if (sig.data_pol)
+			ser_conf |= DI_SER_CONF_SERIAL_DATA_POL;
+		if (sig.rs_pol)
+			ser_conf |= DI_SER_CONF_SERIAL_RS_POL;
+		if (sig.cs_pol)
+			ser_conf |= DI_SER_CONF_SERIAL_CS_POL;
+		ipu_di_write(ipu, disp, ser_conf, DI_SER_CONF);
+	}
+
+	_ipu_unlock(ipu);
+	return 0;
+}
+EXPORT_SYMBOL(ipu_init_async_panel);
+
+/*!
+ * This function sets the foreground and background plane global alpha blending
+ * modes. This function also sets the DP graphic plane according to the
+ * parameter of IPUv3 DP channel.
+ *
+ * @param	ipu		ipu handler
+ * @param	channel		IPUv3 DP channel
+ *
+ * @param       enable          Boolean to enable or disable global alpha
+ *                              blending. If disabled, local blending is used.
+ *
+ * @param       alpha           Global alpha value.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel,
+				bool enable, uint8_t alpha)
+{
+	uint32_t reg;
+	uint32_t flow;
+	bool bg_chan;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
+	    channel == MEM_BG_ASYNC1)
+		bg_chan = true;
+	else
+		bg_chan = false;
+
+	_ipu_get(ipu);
+
+	_ipu_lock(ipu);
+
+	if (bg_chan) {
+		reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+		ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+	} else {
+		reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+		ipu_dp_write(ipu, reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+	}
+
+	if (enable) {
+		reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
+		ipu_dp_write(ipu, reg | ((uint32_t) alpha << 24),
+			     DP_GRAPH_WIND_CTRL(flow));
+
+		reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+		ipu_dp_write(ipu, reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+	} else {
+		reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+		ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+	}
+
+	reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
+	ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+
+	_ipu_unlock(ipu);
+
+	_ipu_put(ipu);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disp_set_global_alpha);
+
+/*!
+ * This function sets the transparent color key for SDC graphic plane.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       enable          Boolean to enable or disable color key
+ *
+ * @param       colorKey        24-bit RGB color for transparent color key.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel,
+				bool enable, uint32_t color_key)
+{
+	uint32_t reg, flow;
+	int y, u, v;
+	int red, green, blue;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	_ipu_get(ipu);
+
+	_ipu_lock(ipu);
+
+	ipu->color_key_4rgb = true;
+	/* Transform color key from rgb to yuv if CSC is enabled */
+	if (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
+			((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
+			((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
+			((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB))) {
+
+		dev_dbg(ipu->dev, "color key 0x%x need change to yuv fmt\n", color_key);
+
+		red = (color_key >> 16) & 0xFF;
+		green = (color_key >> 8) & 0xFF;
+		blue = color_key & 0xFF;
+
+		y = _rgb_to_yuv(0, red, green, blue);
+		u = _rgb_to_yuv(1, red, green, blue);
+		v = _rgb_to_yuv(2, red, green, blue);
+		color_key = (y << 16) | (u << 8) | v;
+
+		ipu->color_key_4rgb = false;
+
+		dev_dbg(ipu->dev, "color key change to yuv fmt 0x%x\n", color_key);
+	}
+
+	if (enable) {
+		reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
+		ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(flow));
+
+		reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+		ipu_dp_write(ipu, reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+	} else {
+		reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+		ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+	}
+
+	reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
+	ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+
+	_ipu_unlock(ipu);
+
+	_ipu_put(ipu);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disp_set_color_key);
+
+/*!
+ * This function sets the gamma correction for DP output.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       enable          Boolean to enable or disable gamma correction.
+ *
+ * @param       constk        	Gamma piecewise linear approximation constk coeff.
+ *
+ * @param       slopek        	Gamma piecewise linear approximation slopek coeff.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, int constk[], int slopek[])
+{
+	uint32_t reg, flow, i;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	_ipu_get(ipu);
+
+	_ipu_lock(ipu);
+
+	for (i = 0; i < 8; i++)
+		ipu_dp_write(ipu, (constk[2*i] & 0x1ff) | ((constk[2*i+1] & 0x1ff) << 16), DP_GAMMA_C(flow, i));
+	for (i = 0; i < 4; i++)
+		ipu_dp_write(ipu, (slopek[4*i] & 0xff) | ((slopek[4*i+1] & 0xff) << 8) |
+			((slopek[4*i+2] & 0xff) << 16) | ((slopek[4*i+3] & 0xff) << 24), DP_GAMMA_S(flow, i));
+
+	reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
+	if (enable) {
+		if ((ipu->bg_csc_type == RGB2YUV) || (ipu->bg_csc_type == YUV2YUV))
+			reg |= DP_COM_CONF_GAMMA_YUV_EN;
+		else
+			reg &= ~DP_COM_CONF_GAMMA_YUV_EN;
+		ipu_dp_write(ipu, reg | DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
+	} else
+		ipu_dp_write(ipu, reg & ~DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
+
+	reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
+	ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+
+	_ipu_unlock(ipu);
+
+	_ipu_put(ipu);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_disp_set_gamma_correction);
+
+/*!
+ * This function sets the window position of the foreground or background plane.
+ * modes.
+ *
+ * @param	ipu		ipu handler
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       x_pos           The X coordinate position to place window at.
+ *                              The position is relative to the top left corner.
+ *
+ * @param       y_pos           The Y coordinate position to place window at.
+ *                              The position is relative to the top left corner.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
+				int16_t x_pos, int16_t y_pos)
+{
+	u32 reg;
+	uint32_t flow = 0;
+	uint32_t dp_srm_shift;
+
+	if ((channel == MEM_FG_SYNC) || (channel == MEM_BG_SYNC)) {
+		flow = DP_SYNC;
+		dp_srm_shift = 3;
+	} else if (channel == MEM_FG_ASYNC0) {
+		flow = DP_ASYNC0;
+		dp_srm_shift = 5;
+	} else if (channel == MEM_FG_ASYNC1) {
+		flow = DP_ASYNC1;
+		dp_srm_shift = 7;
+	} else
+		return -EINVAL;
+
+	ipu_dp_write(ipu, (x_pos << 16) | y_pos, DP_FG_POS(flow));
+
+	if (ipu_is_channel_busy(ipu, channel)) {
+		/* controled by FSU if channel enabled */
+		reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
+		reg |= (0x1 << dp_srm_shift);
+		ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+	} else {
+		/* disable auto swap, controled by MCU if channel disabled */
+		reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
+		ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
+	}
+
+	return 0;
+}
+
+int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
+				int16_t x_pos, int16_t y_pos)
+{
+	int ret;
+
+	_ipu_get(ipu);
+	_ipu_lock(ipu);
+	ret = _ipu_disp_set_window_pos(ipu, channel, x_pos, y_pos);
+	_ipu_unlock(ipu);
+	_ipu_put(ipu);
+	return ret;
+}
+EXPORT_SYMBOL(ipu_disp_set_window_pos);
+
+int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
+				int16_t *x_pos, int16_t *y_pos)
+{
+	u32 reg;
+	uint32_t flow = 0;
+
+	if (channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	reg = ipu_dp_read(ipu, DP_FG_POS(flow));
+
+	*x_pos = (reg >> 16) & 0x7FF;
+	*y_pos = reg & 0x7FF;
+
+	return 0;
+}
+int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
+				int16_t *x_pos, int16_t *y_pos)
+{
+	int ret;
+
+	_ipu_get(ipu);
+	_ipu_lock(ipu);
+	ret = _ipu_disp_get_window_pos(ipu, channel, x_pos, y_pos);
+	_ipu_unlock(ipu);
+	_ipu_put(ipu);
+	return ret;
+}
+EXPORT_SYMBOL(ipu_disp_get_window_pos);
+
+void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset)
+{
+	if (channel == DIRECT_ASYNC0)
+		writel(value, ipu->disp_base[0] + offset);
+	else if (channel == DIRECT_ASYNC1)
+		writel(value, ipu->disp_base[1] + offset);
+}
+EXPORT_SYMBOL(ipu_disp_direct_write);
+
+void ipu_reset_disp_panel(struct ipu_soc *ipu)
+{
+	uint32_t tmp;
+
+	tmp = ipu_di_read(ipu, 1, DI_GENERAL);
+	ipu_di_write(ipu, 1, tmp | 0x08, DI_GENERAL);
+	msleep(10); /* tRES >= 100us */
+	tmp = ipu_di_read(ipu, 1, DI_GENERAL);
+	ipu_di_write(ipu, 1, tmp & ~0x08, DI_GENERAL);
+	msleep(60);
+
+	return;
+}
+EXPORT_SYMBOL(ipu_reset_disp_panel);
+
+void __devinit ipu_disp_init(struct ipu_soc *ipu)
+{
+	ipu->fg_csc_type = ipu->bg_csc_type = CSC_NONE;
+	ipu->color_key_4rgb = true;
+	_ipu_init_dc_mappings(ipu);
+	_ipu_dmfc_init(ipu, DMFC_NORMAL, 1);
+}
diff --git a/drivers/mxc/ipu3/ipu_ic.c b/drivers/mxc/ipu3/ipu_ic.c
new file mode 100644
index 00000000000..7387e518deb
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_ic.c
@@ -0,0 +1,840 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_ic.c
+ *
+ * @brief IPU IC functions
+ *
+ * @ingroup IPU
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/videodev2.h>
+#include <linux/io.h>
+#include <mach/ipu-v3.h>
+
+#include "ipu_prv.h"
+#include "ipu_regs.h"
+#include "ipu_param_mem.h"
+
+enum {
+	IC_TASK_VIEWFINDER,
+	IC_TASK_ENCODER,
+	IC_TASK_POST_PROCESSOR
+};
+
+static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
+		      ipu_color_space_t out_format, int csc_index);
+static bool _calc_resize_coeffs(struct ipu_soc *ipu,
+				uint32_t inSize, uint32_t outSize,
+				uint32_t *resizeCoeff,
+				uint32_t *downsizeCoeff);
+
+void _ipu_vdi_set_top_field_man(struct ipu_soc *ipu, bool top_field_0)
+{
+	uint32_t reg;
+
+	reg = ipu_vdi_read(ipu, VDI_C);
+	if (top_field_0)
+		reg &= ~VDI_C_TOP_FIELD_MAN_1;
+	else
+		reg |= VDI_C_TOP_FIELD_MAN_1;
+	ipu_vdi_write(ipu, reg, VDI_C);
+}
+
+void _ipu_vdi_set_motion(struct ipu_soc *ipu, ipu_motion_sel motion_sel)
+{
+	uint32_t reg;
+
+	reg = ipu_vdi_read(ipu, VDI_C);
+	reg &= ~(VDI_C_MOT_SEL_FULL | VDI_C_MOT_SEL_MED | VDI_C_MOT_SEL_LOW);
+	if (motion_sel == HIGH_MOTION)
+		reg |= VDI_C_MOT_SEL_FULL;
+	else if (motion_sel == MED_MOTION)
+		reg |= VDI_C_MOT_SEL_MED;
+	else
+		reg |= VDI_C_MOT_SEL_LOW;
+
+	ipu_vdi_write(ipu, reg, VDI_C);
+}
+
+void ic_dump_register(struct ipu_soc *ipu)
+{
+	printk(KERN_DEBUG "IC_CONF = \t0x%08X\n", ipu_ic_read(ipu, IC_CONF));
+	printk(KERN_DEBUG "IC_PRP_ENC_RSC = \t0x%08X\n",
+	       ipu_ic_read(ipu, IC_PRP_ENC_RSC));
+	printk(KERN_DEBUG "IC_PRP_VF_RSC = \t0x%08X\n",
+	       ipu_ic_read(ipu, IC_PRP_VF_RSC));
+	printk(KERN_DEBUG "IC_PP_RSC = \t0x%08X\n", ipu_ic_read(ipu, IC_PP_RSC));
+	printk(KERN_DEBUG "IC_IDMAC_1 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_1));
+	printk(KERN_DEBUG "IC_IDMAC_2 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_2));
+	printk(KERN_DEBUG "IC_IDMAC_3 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_3));
+}
+
+void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel)
+{
+	uint32_t ic_conf;
+
+	ic_conf = ipu_ic_read(ipu, IC_CONF);
+	switch (channel) {
+	case CSI_PRP_VF_MEM:
+	case MEM_PRP_VF_MEM:
+		ic_conf |= IC_CONF_PRPVF_EN;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		ic_conf |= IC_CONF_PRPVF_EN;
+		break;
+	case MEM_ROT_VF_MEM:
+		ic_conf |= IC_CONF_PRPVF_ROT_EN;
+		break;
+	case CSI_PRP_ENC_MEM:
+	case MEM_PRP_ENC_MEM:
+		ic_conf |= IC_CONF_PRPENC_EN;
+		break;
+	case MEM_ROT_ENC_MEM:
+		ic_conf |= IC_CONF_PRPENC_ROT_EN;
+		break;
+	case MEM_PP_MEM:
+		ic_conf |= IC_CONF_PP_EN;
+		break;
+	case MEM_ROT_PP_MEM:
+		ic_conf |= IC_CONF_PP_ROT_EN;
+		break;
+	default:
+		break;
+	}
+	ipu_ic_write(ipu, ic_conf, IC_CONF);
+}
+
+void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel)
+{
+	uint32_t ic_conf;
+
+	ic_conf = ipu_ic_read(ipu, IC_CONF);
+	switch (channel) {
+	case CSI_PRP_VF_MEM:
+	case MEM_PRP_VF_MEM:
+		ic_conf &= ~IC_CONF_PRPVF_EN;
+		break;
+	case MEM_VDI_PRP_VF_MEM:
+		ic_conf &= ~IC_CONF_PRPVF_EN;
+		break;
+	case MEM_ROT_VF_MEM:
+		ic_conf &= ~IC_CONF_PRPVF_ROT_EN;
+		break;
+	case CSI_PRP_ENC_MEM:
+	case MEM_PRP_ENC_MEM:
+		ic_conf &= ~IC_CONF_PRPENC_EN;
+		break;
+	case MEM_ROT_ENC_MEM:
+		ic_conf &= ~IC_CONF_PRPENC_ROT_EN;
+		break;
+	case MEM_PP_MEM:
+		ic_conf &= ~IC_CONF_PP_EN;
+		break;
+	case MEM_ROT_PP_MEM:
+		ic_conf &= ~IC_CONF_PP_ROT_EN;
+		break;
+	default:
+		break;
+	}
+	ipu_ic_write(ipu, ic_conf, IC_CONF);
+}
+
+void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
+{
+	uint32_t reg;
+	uint32_t pixel_fmt;
+
+	reg = ((params->mem_prp_vf_mem.in_height-1) << 16) |
+	  (params->mem_prp_vf_mem.in_width-1);
+	ipu_vdi_write(ipu, reg, VDI_FSIZE);
+
+	/* Full motion, only vertical filter is used
+	   Burst size is 4 accesses */
+	if (params->mem_prp_vf_mem.in_pixel_fmt ==
+	     IPU_PIX_FMT_UYVY ||
+	     params->mem_prp_vf_mem.in_pixel_fmt ==
+	     IPU_PIX_FMT_YUYV)
+		pixel_fmt = VDI_C_CH_422;
+	else
+		pixel_fmt = VDI_C_CH_420;
+
+	reg = ipu_vdi_read(ipu, VDI_C);
+	reg |= pixel_fmt;
+	switch (channel) {
+	case MEM_VDI_PRP_VF_MEM:
+		reg |= VDI_C_BURST_SIZE2_4;
+		break;
+	case MEM_VDI_PRP_VF_MEM_P:
+		reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_SET_1 | VDI_C_VWM1_CLR_2;
+		break;
+	case MEM_VDI_PRP_VF_MEM_N:
+		reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_SET_1 | VDI_C_VWM3_CLR_2;
+		break;
+	default:
+		break;
+	}
+	ipu_vdi_write(ipu, reg, VDI_C);
+
+	if (params->mem_prp_vf_mem.field_fmt == V4L2_FIELD_INTERLACED_TB)
+		_ipu_vdi_set_top_field_man(ipu, false);
+	else if (params->mem_prp_vf_mem.field_fmt == V4L2_FIELD_INTERLACED_BT)
+		_ipu_vdi_set_top_field_man(ipu, true);
+
+	_ipu_vdi_set_motion(ipu, params->mem_prp_vf_mem.motion_sel);
+
+	reg = ipu_ic_read(ipu, IC_CONF);
+	reg &= ~IC_CONF_RWS_EN;
+	ipu_ic_write(ipu, reg, IC_CONF);
+}
+
+void _ipu_vdi_uninit(struct ipu_soc *ipu)
+{
+	ipu_vdi_write(ipu, 0, VDI_FSIZE);
+	ipu_vdi_write(ipu, 0, VDI_C);
+}
+
+void _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params, bool src_is_csi)
+{
+	uint32_t reg, ic_conf;
+	uint32_t downsizeCoeff, resizeCoeff;
+	ipu_color_space_t in_fmt, out_fmt;
+
+	/* Setup vertical resizing */
+	if (!(params->mem_prp_vf_mem.outv_resize_ratio)) {
+		_calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_height,
+				params->mem_prp_vf_mem.out_height,
+				&resizeCoeff, &downsizeCoeff);
+		reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+	} else
+		reg = (params->mem_prp_vf_mem.outv_resize_ratio) << 16;
+
+	/* Setup horizontal resizing */
+	/* Upadeted for IC split case */
+	if (!(params->mem_prp_vf_mem.outh_resize_ratio)) {
+		_calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_width,
+				params->mem_prp_vf_mem.out_width,
+				&resizeCoeff, &downsizeCoeff);
+		reg |= (downsizeCoeff << 14) | resizeCoeff;
+	} else
+		reg |= params->mem_prp_vf_mem.outh_resize_ratio;
+
+	ipu_ic_write(ipu, reg, IC_PRP_VF_RSC);
+
+	ic_conf = ipu_ic_read(ipu, IC_CONF);
+
+	/* Setup color space conversion */
+	in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt);
+	out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
+	if (in_fmt == RGB) {
+		if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+			/* Enable RGB->YCBCR CSC1 */
+			_init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 1);
+			ic_conf |= IC_CONF_PRPVF_CSC1;
+		}
+	}
+	if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+		if (out_fmt == RGB) {
+			/* Enable YCBCR->RGB CSC1 */
+			_init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 1);
+			ic_conf |= IC_CONF_PRPVF_CSC1;
+		} else {
+			/* TODO: Support YUV<->YCbCr conversion? */
+		}
+	}
+
+	if (params->mem_prp_vf_mem.graphics_combine_en) {
+		ic_conf |= IC_CONF_PRPVF_CMB;
+
+		if (!(ic_conf & IC_CONF_PRPVF_CSC1)) {
+			/* need transparent CSC1 conversion */
+			_init_csc(ipu, IC_TASK_VIEWFINDER, RGB, RGB, 1);
+			ic_conf |= IC_CONF_PRPVF_CSC1;  /* Enable RGB->RGB CSC */
+		}
+		in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_g_pixel_fmt);
+		out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
+		if (in_fmt == RGB) {
+			if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+				/* Enable RGB->YCBCR CSC2 */
+				_init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 2);
+				ic_conf |= IC_CONF_PRPVF_CSC2;
+			}
+		}
+		if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+			if (out_fmt == RGB) {
+				/* Enable YCBCR->RGB CSC2 */
+				_init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 2);
+				ic_conf |= IC_CONF_PRPVF_CSC2;
+			} else {
+				/* TODO: Support YUV<->YCbCr conversion? */
+			}
+		}
+
+		if (params->mem_prp_vf_mem.global_alpha_en) {
+			ic_conf |= IC_CONF_IC_GLB_LOC_A;
+			reg = ipu_ic_read(ipu, IC_CMBP_1);
+			reg &= ~(0xff);
+			reg |= params->mem_prp_vf_mem.alpha;
+			ipu_ic_write(ipu, reg, IC_CMBP_1);
+		} else
+			ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
+
+		if (params->mem_prp_vf_mem.key_color_en) {
+			ic_conf |= IC_CONF_KEY_COLOR_EN;
+			ipu_ic_write(ipu, params->mem_prp_vf_mem.key_color,
+					IC_CMBP_2);
+		} else
+			ic_conf &= ~IC_CONF_KEY_COLOR_EN;
+	} else {
+		ic_conf &= ~IC_CONF_PRPVF_CMB;
+	}
+
+	if (src_is_csi)
+		ic_conf &= ~IC_CONF_RWS_EN;
+	else
+		ic_conf |= IC_CONF_RWS_EN;
+
+	ipu_ic_write(ipu, ic_conf, IC_CONF);
+}
+
+void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu)
+{
+	uint32_t reg;
+
+	reg = ipu_ic_read(ipu, IC_CONF);
+	reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB |
+		 IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1);
+	ipu_ic_write(ipu, reg, IC_CONF);
+}
+
+void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params)
+{
+}
+
+void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu)
+{
+	uint32_t reg;
+	reg = ipu_ic_read(ipu, IC_CONF);
+	reg &= ~IC_CONF_PRPVF_ROT_EN;
+	ipu_ic_write(ipu, reg, IC_CONF);
+}
+
+void _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params, bool src_is_csi)
+{
+	uint32_t reg, ic_conf;
+	uint32_t downsizeCoeff, resizeCoeff;
+	ipu_color_space_t in_fmt, out_fmt;
+
+	/* Setup vertical resizing */
+	if (!(params->mem_prp_enc_mem.outv_resize_ratio)) {
+		_calc_resize_coeffs(ipu, params->mem_prp_enc_mem.in_height,
+				params->mem_prp_enc_mem.out_height,
+				&resizeCoeff, &downsizeCoeff);
+		reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+	} else
+		reg = (params->mem_prp_enc_mem.outv_resize_ratio) << 16;
+
+	/* Setup horizontal resizing */
+	/* Upadeted for IC split case */
+	if (!(params->mem_prp_enc_mem.outh_resize_ratio)) {
+		_calc_resize_coeffs(ipu, params->mem_prp_enc_mem.in_width,
+				params->mem_prp_enc_mem.out_width,
+				&resizeCoeff, &downsizeCoeff);
+		reg |= (downsizeCoeff << 14) | resizeCoeff;
+	} else
+		reg |= params->mem_prp_enc_mem.outh_resize_ratio;
+
+	ipu_ic_write(ipu, reg, IC_PRP_ENC_RSC);
+
+	ic_conf = ipu_ic_read(ipu, IC_CONF);
+
+	/* Setup color space conversion */
+	in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt);
+	out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt);
+	if (in_fmt == RGB) {
+		if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+			/* Enable RGB->YCBCR CSC1 */
+			_init_csc(ipu, IC_TASK_ENCODER, RGB, out_fmt, 1);
+			ic_conf |= IC_CONF_PRPENC_CSC1;
+		}
+	}
+	if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+		if (out_fmt == RGB) {
+			/* Enable YCBCR->RGB CSC1 */
+			_init_csc(ipu, IC_TASK_ENCODER, YCbCr, RGB, 1);
+			ic_conf |= IC_CONF_PRPENC_CSC1;
+		} else {
+			/* TODO: Support YUV<->YCbCr conversion? */
+		}
+	}
+
+	if (src_is_csi)
+		ic_conf &= ~IC_CONF_RWS_EN;
+	else
+		ic_conf |= IC_CONF_RWS_EN;
+
+	ipu_ic_write(ipu, ic_conf, IC_CONF);
+}
+
+void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu)
+{
+	uint32_t reg;
+
+	reg = ipu_ic_read(ipu, IC_CONF);
+	reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1);
+	ipu_ic_write(ipu, reg, IC_CONF);
+}
+
+void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params)
+{
+}
+
+void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu)
+{
+	uint32_t reg;
+
+	reg = ipu_ic_read(ipu, IC_CONF);
+	reg &= ~(IC_CONF_PRPENC_ROT_EN);
+	ipu_ic_write(ipu, reg, IC_CONF);
+}
+
+void _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
+{
+	uint32_t reg, ic_conf;
+	uint32_t downsizeCoeff, resizeCoeff;
+	ipu_color_space_t in_fmt, out_fmt;
+
+	/* Setup vertical resizing */
+	if (!(params->mem_pp_mem.outv_resize_ratio)) {
+		_calc_resize_coeffs(ipu, params->mem_pp_mem.in_height,
+			    params->mem_pp_mem.out_height,
+			    &resizeCoeff, &downsizeCoeff);
+		reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
+	} else {
+		reg = (params->mem_pp_mem.outv_resize_ratio) << 16;
+	}
+
+	/* Setup horizontal resizing */
+	/* Upadeted for IC split case */
+	if (!(params->mem_pp_mem.outh_resize_ratio)) {
+		_calc_resize_coeffs(ipu, params->mem_pp_mem.in_width,
+							params->mem_pp_mem.out_width,
+							&resizeCoeff, &downsizeCoeff);
+		reg |= (downsizeCoeff << 14) | resizeCoeff;
+	} else {
+		reg |= params->mem_pp_mem.outh_resize_ratio;
+	}
+
+	ipu_ic_write(ipu, reg, IC_PP_RSC);
+
+	ic_conf = ipu_ic_read(ipu, IC_CONF);
+
+	/* Setup color space conversion */
+	in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt);
+	out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
+	if (in_fmt == RGB) {
+		if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+			/* Enable RGB->YCBCR CSC1 */
+			_init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 1);
+			ic_conf |= IC_CONF_PP_CSC1;
+		}
+	}
+	if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+		if (out_fmt == RGB) {
+			/* Enable YCBCR->RGB CSC1 */
+			_init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 1);
+			ic_conf |= IC_CONF_PP_CSC1;
+		} else {
+			/* TODO: Support YUV<->YCbCr conversion? */
+		}
+	}
+
+	if (params->mem_pp_mem.graphics_combine_en) {
+		ic_conf |= IC_CONF_PP_CMB;
+
+		if (!(ic_conf & IC_CONF_PP_CSC1)) {
+			/* need transparent CSC1 conversion */
+			_init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, RGB, 1);
+			ic_conf |= IC_CONF_PP_CSC1;  /* Enable RGB->RGB CSC */
+		}
+
+		in_fmt = format_to_colorspace(params->mem_pp_mem.in_g_pixel_fmt);
+		out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
+		if (in_fmt == RGB) {
+			if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
+				/* Enable RGB->YCBCR CSC2 */
+				_init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 2);
+				ic_conf |= IC_CONF_PP_CSC2;
+			}
+		}
+		if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
+			if (out_fmt == RGB) {
+				/* Enable YCBCR->RGB CSC2 */
+				_init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 2);
+				ic_conf |= IC_CONF_PP_CSC2;
+			} else {
+				/* TODO: Support YUV<->YCbCr conversion? */
+			}
+		}
+
+		if (params->mem_pp_mem.global_alpha_en) {
+			ic_conf |= IC_CONF_IC_GLB_LOC_A;
+			reg = ipu_ic_read(ipu, IC_CMBP_1);
+			reg &= ~(0xff00);
+			reg |= (params->mem_pp_mem.alpha << 8);
+			ipu_ic_write(ipu, reg, IC_CMBP_1);
+		} else
+			ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
+
+		if (params->mem_pp_mem.key_color_en) {
+			ic_conf |= IC_CONF_KEY_COLOR_EN;
+			ipu_ic_write(ipu, params->mem_pp_mem.key_color,
+					IC_CMBP_2);
+		} else
+			ic_conf &= ~IC_CONF_KEY_COLOR_EN;
+	} else {
+		ic_conf &= ~IC_CONF_PP_CMB;
+	}
+
+	ipu_ic_write(ipu, ic_conf, IC_CONF);
+}
+
+void _ipu_ic_uninit_pp(struct ipu_soc *ipu)
+{
+	uint32_t reg;
+
+	reg = ipu_ic_read(ipu, IC_CONF);
+	reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 |
+		 IC_CONF_PP_CMB);
+	ipu_ic_write(ipu, reg, IC_CONF);
+}
+
+void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
+{
+}
+
+void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu)
+{
+	uint32_t reg;
+	reg = ipu_ic_read(ipu, IC_CONF);
+	reg &= ~IC_CONF_PP_ROT_EN;
+	ipu_ic_write(ipu, reg, IC_CONF);
+}
+
+int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan,
+		uint16_t width, uint16_t height,
+		int burst_size, ipu_rotate_mode_t rot)
+{
+	u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
+	u32 temp_rot = bitrev8(rot) >> 5;
+	bool need_hor_flip = false;
+
+	if ((burst_size != 8) && (burst_size != 16)) {
+		dev_dbg(ipu->dev, "Illegal burst length for IC\n");
+		return -EINVAL;
+	}
+
+	width--;
+	height--;
+
+	if (temp_rot & 0x2)	/* Need horizontal flip */
+		need_hor_flip = true;
+
+	ic_idmac_1 = ipu_ic_read(ipu, IC_IDMAC_1);
+	ic_idmac_2 = ipu_ic_read(ipu, IC_IDMAC_2);
+	ic_idmac_3 = ipu_ic_read(ipu, IC_IDMAC_3);
+	if (dma_chan == 22) {	/* PP output - CB2 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
+
+		if (need_hor_flip)
+			ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
+
+		ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
+		ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
+
+		ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
+		ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
+	} else if (dma_chan == 11) {	/* PP Input - CB5 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
+	} else if (dma_chan == 47) {	/* PP Rot input */
+		ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
+		ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
+	}
+
+	if (dma_chan == 12) {	/* PRP Input - CB6 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
+	}
+
+	if (dma_chan == 20) {	/* PRP ENC output - CB0 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
+
+		if (need_hor_flip)
+			ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
+
+		ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
+		ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
+
+		ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
+		ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
+
+	} else if (dma_chan == 45) {	/* PRP ENC Rot input */
+		ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
+		ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
+	}
+
+	if (dma_chan == 21) {	/* PRP VF output - CB1 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
+
+		if (need_hor_flip)
+			ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
+
+		ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
+		ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
+
+		ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
+		ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
+
+	} else if (dma_chan == 46) {	/* PRP VF Rot input */
+		ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
+		ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
+	}
+
+	if (dma_chan == 14) {	/* PRP VF graphics combining input - CB3 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
+	} else if (dma_chan == 15) {	/* PP graphics combining input - CB4 */
+		if (burst_size == 16)
+			ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
+		else
+			ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
+	}
+
+	ipu_ic_write(ipu, ic_idmac_1, IC_IDMAC_1);
+	ipu_ic_write(ipu, ic_idmac_2, IC_IDMAC_2);
+	ipu_ic_write(ipu, ic_idmac_3, IC_IDMAC_3);
+
+	return 0;
+}
+
+static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
+		      ipu_color_space_t out_format, int csc_index)
+{
+
+/*     Y = R *  .299 + G *  .587 + B *  .114;
+       U = R * -.169 + G * -.332 + B *  .500 + 128.;
+       V = R *  .500 + G * -.419 + B * -.0813 + 128.;*/
+	static const uint32_t rgb2ycbcr_coeff[4][3] = {
+		{0x004D, 0x0096, 0x001D},
+		{0x01D5, 0x01AB, 0x0080},
+		{0x0080, 0x0195, 0x01EB},
+		{0x0000, 0x0200, 0x0200},	/* A0, A1, A2 */
+	};
+
+	/* transparent RGB->RGB matrix for combining
+	 */
+	static const uint32_t rgb2rgb_coeff[4][3] = {
+		{0x0080, 0x0000, 0x0000},
+		{0x0000, 0x0080, 0x0000},
+		{0x0000, 0x0000, 0x0080},
+		{0x0000, 0x0000, 0x0000},	/* A0, A1, A2 */
+	};
+
+/*     R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
+       G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
+       B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
+	static const uint32_t ycbcr2rgb_coeff[4][3] = {
+		{149, 0, 204},
+		{149, 462, 408},
+		{149, 255, 0},
+		{8192 - 446, 266, 8192 - 554},	/* A0, A1, A2 */
+	};
+
+	uint32_t param;
+	uint32_t *base = NULL;
+
+	if (ic_task == IC_TASK_ENCODER) {
+		base = ipu->tpmem_base + 0x2008 / 4;
+	} else if (ic_task == IC_TASK_VIEWFINDER) {
+		if (csc_index == 1)
+			base = ipu->tpmem_base + 0x4028 / 4;
+		else
+			base = ipu->tpmem_base + 0x4040 / 4;
+	} else if (ic_task == IC_TASK_POST_PROCESSOR) {
+		if (csc_index == 1)
+			base = ipu->tpmem_base + 0x6060 / 4;
+		else
+			base = ipu->tpmem_base + 0x6078 / 4;
+	} else {
+		BUG();
+	}
+
+	if ((in_format == YCbCr) && (out_format == RGB)) {
+		/* Init CSC (YCbCr->RGB) */
+		param = (ycbcr2rgb_coeff[3][0] << 27) |
+			(ycbcr2rgb_coeff[0][0] << 18) |
+			(ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2];
+		writel(param, base++);
+		/* scale = 2, sat = 0 */
+		param = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32));
+		writel(param, base++);
+
+		param = (ycbcr2rgb_coeff[3][1] << 27) |
+			(ycbcr2rgb_coeff[0][1] << 18) |
+			(ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0];
+		writel(param, base++);
+		param = (ycbcr2rgb_coeff[3][1] >> 5);
+		writel(param, base++);
+
+		param = (ycbcr2rgb_coeff[3][2] << 27) |
+			(ycbcr2rgb_coeff[0][2] << 18) |
+			(ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1];
+		writel(param, base++);
+		param = (ycbcr2rgb_coeff[3][2] >> 5);
+		writel(param, base++);
+	} else if ((in_format == RGB) && (out_format == YCbCr)) {
+		/* Init CSC (RGB->YCbCr) */
+		param = (rgb2ycbcr_coeff[3][0] << 27) |
+			(rgb2ycbcr_coeff[0][0] << 18) |
+			(rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2];
+		writel(param, base++);
+		/* scale = 1, sat = 0 */
+		param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8);
+		writel(param, base++);
+
+		param = (rgb2ycbcr_coeff[3][1] << 27) |
+			(rgb2ycbcr_coeff[0][1] << 18) |
+			(rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0];
+		writel(param, base++);
+		param = (rgb2ycbcr_coeff[3][1] >> 5);
+		writel(param, base++);
+
+		param = (rgb2ycbcr_coeff[3][2] << 27) |
+			(rgb2ycbcr_coeff[0][2] << 18) |
+			(rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1];
+		writel(param, base++);
+		param = (rgb2ycbcr_coeff[3][2] >> 5);
+		writel(param, base++);
+	} else if ((in_format == RGB) && (out_format == RGB)) {
+		/* Init CSC */
+		param =
+		    (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) |
+		    (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2];
+		writel(param, base++);
+		/* scale = 2, sat = 0 */
+		param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8);
+		writel(param, base++);
+
+		param =
+		    (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) |
+		    (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0];
+		writel(param, base++);
+		param = (rgb2rgb_coeff[3][1] >> 5);
+		writel(param, base++);
+
+		param =
+		    (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) |
+		    (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1];
+		writel(param, base++);
+		param = (rgb2rgb_coeff[3][2] >> 5);
+		writel(param, base++);
+	} else {
+		dev_err(ipu->dev, "Unsupported color space conversion\n");
+	}
+}
+
+static bool _calc_resize_coeffs(struct ipu_soc *ipu,
+				uint32_t inSize, uint32_t outSize,
+				uint32_t *resizeCoeff,
+				uint32_t *downsizeCoeff)
+{
+	uint32_t tempSize;
+	uint32_t tempDownsize;
+
+	/* Input size cannot be more than 4096 */
+	/* Output size cannot be more than 1024 */
+	if ((inSize > 4096) || (outSize > 1024))
+		return false;
+
+	/* Cannot downsize more than 8:1 */
+	if ((outSize << 3) < inSize)
+		return false;
+
+	/* Compute downsizing coefficient */
+	/* Output of downsizing unit cannot be more than 1024 */
+	tempDownsize = 0;
+	tempSize = inSize;
+	while (((tempSize > 1024) || (tempSize >= outSize * 2)) &&
+	       (tempDownsize < 2)) {
+		tempSize >>= 1;
+		tempDownsize++;
+	}
+	*downsizeCoeff = tempDownsize;
+
+	/* compute resizing coefficient using the following equation:
+	   resizeCoeff = M*(SI -1)/(SO - 1)
+	   where M = 2^13, SI - input size, SO - output size    */
+	*resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
+	if (*resizeCoeff >= 16384L) {
+		dev_err(ipu->dev, "Warning! Overflow on resize coeff.\n");
+		*resizeCoeff = 0x3FFF;
+	}
+
+	dev_dbg(ipu->dev, "resizing from %u -> %u pixels, "
+		"downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
+		*downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
+		((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
+
+	return true;
+}
+
+void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu)
+{
+	uint32_t reg;
+	uint32_t mask_reg;
+
+	reg = ipu_vdi_read(ipu, VDI_C);
+	mask_reg = reg & VDI_C_TOP_FIELD_MAN_1;
+	if (mask_reg == VDI_C_TOP_FIELD_MAN_1)
+		reg &= ~VDI_C_TOP_FIELD_MAN_1;
+	else
+		reg |= VDI_C_TOP_FIELD_MAN_1;
+
+	ipu_vdi_write(ipu, reg, VDI_C);
+}
diff --git a/drivers/mxc/ipu3/ipu_param_mem.h b/drivers/mxc/ipu3/ipu_param_mem.h
new file mode 100644
index 00000000000..223a1cdf5fa
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_param_mem.h
@@ -0,0 +1,822 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __INCLUDE_IPU_PARAM_MEM_H__
+#define __INCLUDE_IPU_PARAM_MEM_H__
+
+#include <linux/types.h>
+#include <linux/bitrev.h>
+
+extern u32 *ipu_cpmem_base;
+
+struct ipu_ch_param_word {
+	uint32_t data[5];
+	uint32_t res[3];
+};
+
+struct ipu_ch_param {
+	struct ipu_ch_param_word word[2];
+};
+
+#define ipu_ch_param_addr(ipu, ch) (((struct ipu_ch_param *)ipu->cpmem_base) + (ch))
+
+#define _param_word(base, w) \
+	(((struct ipu_ch_param *)(base))->word[(w)].data)
+
+#define ipu_ch_param_set_field(base, w, bit, size, v) { \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	_param_word(base, w)[i] |= (v) << off; \
+	if (((bit)+(size)-1)/32 > i) { \
+		_param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
+	} \
+}
+
+#define ipu_ch_param_set_field_io(base, w, bit, size, v) { \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	unsigned reg_offset; \
+	u32 temp; \
+	reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
+	reg_offset += i; \
+	temp = readl((u32 *)base + reg_offset); \
+	temp |= (v) << off; \
+	writel(temp, (u32 *)base + reg_offset); \
+	if (((bit)+(size)-1)/32 > i) { \
+		reg_offset++; \
+		temp = readl((u32 *)base + reg_offset); \
+		temp |= (v) >> (off ? (32 - off) : 0); \
+		writel(temp, (u32 *)base + reg_offset); \
+	} \
+}
+
+#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	u32 mask = (1UL << size) - 1; \
+	u32 temp = _param_word(base, w)[i]; \
+	temp &= ~(mask << off); \
+	_param_word(base, w)[i] = temp | (v) << off; \
+	if (((bit)+(size)-1)/32 > i) { \
+		temp = _param_word(base, w)[i + 1]; \
+		temp &= ~(mask >> (32 - off)); \
+		_param_word(base, w)[i + 1] = \
+			temp | ((v) >> (off ? (32 - off) : 0)); \
+	} \
+}
+
+#define ipu_ch_param_mod_field_io(base, w, bit, size, v) { \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	u32 mask = (1UL << size) - 1; \
+	unsigned reg_offset; \
+	u32 temp; \
+	reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
+	reg_offset += i; \
+	temp = readl((u32 *)base + reg_offset); \
+	temp &= ~(mask << off); \
+	temp |= (v) << off; \
+	writel(temp, (u32 *)base + reg_offset); \
+	if (((bit)+(size)-1)/32 > i) { \
+		reg_offset++; \
+		temp = readl((u32 *)base + reg_offset); \
+		temp &= ~(mask >> (32 - off)); \
+		temp |= ((v) >> (off ? (32 - off) : 0)); \
+		writel(temp, (u32 *)base + reg_offset); \
+	} \
+}
+
+#define ipu_ch_param_read_field(base, w, bit, size) ({ \
+	u32 temp2; \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	u32 mask = (1UL << size) - 1; \
+	u32 temp1 = _param_word(base, w)[i]; \
+	temp1 = mask & (temp1 >> off); \
+	if (((bit)+(size)-1)/32 > i) { \
+		temp2 = _param_word(base, w)[i + 1]; \
+		temp2 &= mask >> (off ? (32 - off) : 0); \
+		temp1 |= temp2 << (off ? (32 - off) : 0); \
+	} \
+	temp1; \
+})
+
+#define ipu_ch_param_read_field_io(base, w, bit, size) ({ \
+	u32 temp1, temp2; \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	u32 mask = (1UL << size) - 1; \
+	unsigned reg_offset; \
+	reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
+	reg_offset += i; \
+	temp1 = readl((u32 *)base + reg_offset); \
+	temp1 = mask & (temp1 >> off); \
+	if (((bit)+(size)-1)/32 > i) { \
+		reg_offset++; \
+		temp2 = readl((u32 *)base + reg_offset); \
+		temp2 &= mask >> (off ? (32 - off) : 0); \
+		temp1 |= temp2 << (off ? (32 - off) : 0); \
+	} \
+	temp1; \
+})
+
+static inline int __ipu_ch_get_third_buf_cpmem_num(int ch)
+{
+	switch (ch) {
+	case 8:
+		return 64;
+	case 9:
+		return 65;
+	case 10:
+		return 66;
+	case 13:
+		return 67;
+	case 21:
+		return 68;
+	case 23:
+		return 69;
+	case 27:
+		return 70;
+	case 28:
+		return 71;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static inline void _ipu_ch_params_set_packing(struct ipu_ch_param *p,
+					      int red_width, int red_offset,
+					      int green_width, int green_offset,
+					      int blue_width, int blue_offset,
+					      int alpha_width, int alpha_offset)
+{
+	/* Setup red width and offset */
+	ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
+	ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
+	/* Setup green width and offset */
+	ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
+	ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
+	/* Setup blue width and offset */
+	ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
+	ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
+	/* Setup alpha width and offset */
+	ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
+	ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
+}
+
+static inline void _ipu_ch_param_dump(struct ipu_soc *ipu, int ch)
+{
+	struct ipu_ch_param *p = ipu_ch_param_addr(ipu, ch);
+	dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
+		 p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
+		 p->word[0].data[3], p->word[0].data[4]);
+	dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
+		 p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
+		 p->word[1].data[3], p->word[1].data[4]);
+	dev_dbg(ipu->dev, "PFS 0x%x, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 85, 4));
+	dev_dbg(ipu->dev, "BPP 0x%x, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 107, 3));
+	dev_dbg(ipu->dev, "NPB 0x%x\n",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7));
+
+	dev_dbg(ipu->dev, "FW %d, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 125, 13));
+	dev_dbg(ipu->dev, "FH %d, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 138, 12));
+	dev_dbg(ipu->dev, "Stride %d\n",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14));
+
+	dev_dbg(ipu->dev, "Width0 %d+1, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 116, 3));
+	dev_dbg(ipu->dev, "Width1 %d+1, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 119, 3));
+	dev_dbg(ipu->dev, "Width2 %d+1, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 122, 3));
+	dev_dbg(ipu->dev, "Width3 %d+1, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 125, 3));
+	dev_dbg(ipu->dev, "Offset0 %d, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 128, 5));
+	dev_dbg(ipu->dev, "Offset1 %d, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 133, 5));
+	dev_dbg(ipu->dev, "Offset2 %d, ",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 138, 5));
+	dev_dbg(ipu->dev, "Offset3 %d\n",
+		 ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 143, 5));
+}
+
+static inline void fill_cpmem(struct ipu_soc *ipu, int ch, struct ipu_ch_param *params)
+{
+	int i, w;
+	void *addr = ipu_ch_param_addr(ipu, ch);
+
+	/* 2 words, 5 valid data */
+	for (w = 0; w < 2; w++) {
+		for (i = 0; i < 5; i++) {
+			writel(params->word[w].data[i], addr);
+			addr += 4;
+		}
+		addr += 12;
+	}
+}
+
+static inline void _ipu_ch_param_init(struct ipu_soc *ipu, int ch,
+				      uint32_t pixel_fmt, uint32_t width,
+				      uint32_t height, uint32_t stride,
+				      uint32_t u, uint32_t v,
+				      uint32_t uv_stride, dma_addr_t addr0,
+				      dma_addr_t addr1, dma_addr_t addr2)
+{
+	uint32_t u_offset = 0;
+	uint32_t v_offset = 0;
+	int32_t sub_ch = 0;
+	struct ipu_ch_param params;
+
+	memset(&params, 0, sizeof(params));
+
+	ipu_ch_param_set_field(&params, 0, 125, 13, width - 1);
+
+	if ((ch == 8) || (ch == 9) || (ch == 10)) {
+		ipu_ch_param_set_field(&params, 0, 138, 12, (height / 2) - 1);
+		ipu_ch_param_set_field(&params, 1, 102, 14, (stride * 2) - 1);
+	} else {
+		ipu_ch_param_set_field(&params, 0, 138, 12, height - 1);
+		ipu_ch_param_set_field(&params, 1, 102, 14, stride - 1);
+	}
+
+	/* EBA is 8-byte aligned */
+	ipu_ch_param_set_field(&params, 1, 0, 29, addr0 >> 3);
+	ipu_ch_param_set_field(&params, 1, 29, 29, addr1 >> 3);
+	if (addr0%8)
+		dev_warn(ipu->dev,
+			 "IDMAC%d's EBA0 is not 8-byte aligned\n", ch);
+	if (addr1%8)
+		dev_warn(ipu->dev,
+			 "IDMAC%d's EBA1 is not 8-byte aligned\n", ch);
+
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_GENERIC:
+		/*Represents 8-bit Generic data */
+		ipu_ch_param_set_field(&params, 0, 107, 3, 5);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 6);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 63);	/* burst size */
+
+		break;
+	case IPU_PIX_FMT_GENERIC_32:
+		/*Represents 32-bit Generic data */
+		break;
+	case IPU_PIX_FMT_RGB565:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 5, 0, 6, 5, 5, 11, 8, 16);
+		break;
+	case IPU_PIX_FMT_BGR24:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 1);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 19);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
+		break;
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_YUV444:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 1);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 19);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 16, 8, 8, 8, 0, 8, 24);
+		break;
+	case IPU_PIX_FMT_VYU444:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 1);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 19);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 8, 8, 0, 8, 16, 8, 24);
+		break;
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_BGR32:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 8, 8, 16, 8, 24, 8, 0);
+		break;
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_RGB32:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 24, 8, 16, 8, 8, 8, 0);
+		break;
+	case IPU_PIX_FMT_ABGR32:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		_ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
+		break;
+	case IPU_PIX_FMT_UYVY:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 0xA);	/* pix format */
+		if ((ch == 8) || (ch == 9) || (ch == 10)) {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
+		} else {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+		}
+		break;
+	case IPU_PIX_FMT_YUYV:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 0x8);	/* pix format */
+		if ((ch == 8) || (ch == 9) || (ch == 10)) {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
+		} else {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+		}
+		break;
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+		ipu_ch_param_set_field(&params, 1, 85, 4, 2);	/* pix format */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = stride * height;
+		v_offset = u_offset + (uv_stride * height / 2);
+		if ((ch == 8) || (ch == 9) || (ch == 10)) {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
+			uv_stride = uv_stride*2;
+		} else {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 31);  /* burst size */
+		}
+		break;
+	case IPU_PIX_FMT_YVU420P:
+		ipu_ch_param_set_field(&params, 1, 85, 4, 2);	/* pix format */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		v_offset = stride * height;
+		u_offset = v_offset + (uv_stride * height / 2);
+		if ((ch == 8) || (ch == 9) || (ch == 10)) {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
+			uv_stride = uv_stride*2;
+		} else {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 31);  /* burst size */
+		}
+		break;
+	case IPU_PIX_FMT_YVU422P:
+		/* BPP & pixel format */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 1);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		v_offset = (v == 0) ? stride * height : v;
+		u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
+		break;
+	case IPU_PIX_FMT_YUV422P:
+		/* BPP & pixel format */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 1);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = (u == 0) ? stride * height : u;
+		v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
+		break;
+	case IPU_PIX_FMT_NV12:
+		/* BPP & pixel format */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 4);	/* pix format */
+		uv_stride = stride;
+		u_offset = (u == 0) ? stride * height : u;
+		if ((ch == 8) || (ch == 9) || (ch == 10)) {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
+			uv_stride = uv_stride*2;
+		} else {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+		}
+		break;
+	default:
+		dev_err(ipu->dev, "mxc ipu: unimplemented pixel format\n");
+		break;
+	}
+	/*set burst size to 16*/
+
+
+	if (uv_stride)
+		ipu_ch_param_set_field(&params, 1, 128, 14, uv_stride - 1);
+
+	/* Get the uv offset from user when need cropping */
+	if (u || v) {
+		u_offset = u;
+		v_offset = v;
+	}
+
+	/* UBO and VBO are 22-bit and 8-byte aligned */
+	if (u_offset/8 > 0x3fffff)
+		dev_warn(ipu->dev,
+			 "IDMAC%d's U offset exceeds IPU limitation\n", ch);
+	if (v_offset/8 > 0x3fffff)
+		dev_warn(ipu->dev,
+			 "IDMAC%d's V offset exceeds IPU limitation\n", ch);
+	if (u_offset%8)
+		dev_warn(ipu->dev,
+			 "IDMAC%d's U offset is not 8-byte aligned\n", ch);
+	if (v_offset%8)
+		dev_warn(ipu->dev,
+			 "IDMAC%d's V offset is not 8-byte aligned\n", ch);
+
+	ipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);
+	ipu_ch_param_set_field(&params, 0, 68, 22, v_offset / 8);
+
+	dev_dbg(ipu->dev, "initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ipu, ch));
+	fill_cpmem(ipu, ch, &params);
+	if (addr2) {
+		ipu_ch_param_set_field(&params, 1, 0, 29, addr2 >> 3);
+		ipu_ch_param_set_field(&params, 1, 29, 29, 0);
+
+		sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+		if (sub_ch <= 0)
+			return;
+
+		dev_dbg(ipu->dev, "initializing idma ch %d @ %p sub cpmem\n", ch,
+					ipu_ch_param_addr(ipu, sub_ch));
+		fill_cpmem(ipu, sub_ch, &params);
+	}
+};
+
+static inline void _ipu_ch_param_set_burst_size(struct ipu_soc *ipu,
+						uint32_t ch,
+						uint16_t burst_pixels)
+{
+	int32_t sub_ch = 0;
+
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7,
+			       burst_pixels - 1);
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+	if (sub_ch <= 0)
+		return;
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 78, 7,
+			       burst_pixels - 1);
+};
+
+static inline int _ipu_ch_param_get_burst_size(struct ipu_soc *ipu, uint32_t ch)
+{
+	return ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7) + 1;
+};
+
+static inline int _ipu_ch_param_get_bpp(struct ipu_soc *ipu, uint32_t ch)
+{
+	return ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 107, 3);
+};
+
+static inline void _ipu_ch_param_set_buffer(struct ipu_soc *ipu, uint32_t ch,
+					int bufNum, dma_addr_t phyaddr)
+{
+	if (bufNum == 2) {
+		ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+		if (ch <= 0)
+			return;
+		bufNum = 0;
+	}
+
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 29 * bufNum, 29,
+			       phyaddr / 8);
+};
+
+static inline void _ipu_ch_param_set_rotation(struct ipu_soc *ipu, uint32_t ch,
+					      ipu_rotate_mode_t rot)
+{
+	u32 temp_rot = bitrev8(rot) >> 5;
+	int32_t sub_ch = 0;
+
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 119, 3, temp_rot);
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+	if (sub_ch <= 0)
+		return;
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 119, 3, temp_rot);
+};
+
+static inline void _ipu_ch_param_set_block_mode(struct ipu_soc *ipu, uint32_t ch)
+{
+	int32_t sub_ch = 0;
+
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 117, 2, 1);
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+	if (sub_ch <= 0)
+		return;
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 117, 2, 1);
+};
+
+static inline void _ipu_ch_param_set_alpha_use_separate_channel(struct ipu_soc *ipu,
+								uint32_t ch,
+								bool option)
+{
+	int32_t sub_ch = 0;
+
+	if (option) {
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 89, 1, 1);
+	} else {
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 89, 1, 0);
+	}
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+	if (sub_ch <= 0)
+		return;
+
+	if (option) {
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 89, 1, 1);
+	} else {
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 89, 1, 0);
+	}
+};
+
+static inline void _ipu_ch_param_set_alpha_condition_read(struct ipu_soc *ipu, uint32_t ch)
+{
+	int32_t sub_ch = 0;
+
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 149, 1, 1);
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+	if (sub_ch <= 0)
+		return;
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 149, 1, 1);
+};
+
+static inline void _ipu_ch_param_set_alpha_buffer_memory(struct ipu_soc *ipu, uint32_t ch)
+{
+	int alp_mem_idx;
+	int32_t sub_ch = 0;
+
+	switch (ch) {
+	case 14: /* PRP graphic */
+		alp_mem_idx = 0;
+		break;
+	case 15: /* PP graphic */
+		alp_mem_idx = 1;
+		break;
+	case 23: /* DP BG SYNC graphic */
+		alp_mem_idx = 4;
+		break;
+	case 27: /* DP FG SYNC graphic */
+		alp_mem_idx = 2;
+		break;
+	default:
+		dev_err(ipu->dev, "unsupported correlative channel of local "
+			"alpha channel\n");
+		return;
+	}
+
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 90, 3, alp_mem_idx);
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+	if (sub_ch <= 0)
+		return;
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 90, 3, alp_mem_idx);
+};
+
+static inline void _ipu_ch_param_set_interlaced_scan(struct ipu_soc *ipu, uint32_t ch)
+{
+	u32 stride;
+	int32_t sub_ch = 0;
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+
+	ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch), 0, 113, 1, 1);
+	if (sub_ch > 0)
+		ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 113, 1, 1);
+	stride = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14) + 1;
+	/* ILO is 20-bit and 8-byte aligned */
+	if (stride/8 > 0xfffff)
+		dev_warn(ipu->dev,
+			 "IDMAC%d's ILO exceeds IPU limitation\n", ch);
+	if (stride%8)
+		dev_warn(ipu->dev,
+			 "IDMAC%d's ILO is not 8-byte aligned\n", ch);
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 58, 20, stride / 8);
+	if (sub_ch > 0)
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 58, 20,
+				       stride / 8);
+	stride *= 2;
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14, stride - 1);
+	if (sub_ch > 0)
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 102, 14,
+				       stride - 1);
+};
+
+static inline void _ipu_ch_param_set_axi_id(struct ipu_soc *ipu, uint32_t ch, uint32_t id)
+{
+	int32_t sub_ch = 0;
+
+	id %= 4;
+
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 93, 2, id);
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+	if (sub_ch <= 0)
+		return;
+	ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 93, 2, id);
+};
+
+/* IDMAC U/V offset changing support */
+/* U and V input is not affected, */
+/* the update is done by new calculation according to */
+/* vertical_offset and horizontal_offset */
+static inline void _ipu_ch_offset_update(struct ipu_soc *ipu,
+					int ch,
+					uint32_t pixel_fmt,
+					uint32_t width,
+					uint32_t height,
+					uint32_t stride,
+					uint32_t u,
+					uint32_t v,
+					uint32_t uv_stride,
+					uint32_t vertical_offset,
+					uint32_t horizontal_offset)
+{
+	uint32_t u_offset = 0;
+	uint32_t v_offset = 0;
+	uint32_t old_offset = 0;
+	uint32_t u_fix = 0;
+	uint32_t v_fix = 0;
+	int32_t sub_ch = 0;
+
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_GENERIC:
+	case IPU_PIX_FMT_GENERIC_32:
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_YUV444:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_ABGR32:
+	case IPU_PIX_FMT_UYVY:
+	case IPU_PIX_FMT_YUYV:
+		break;
+
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = stride * (height - vertical_offset - 1) +
+					(stride - horizontal_offset) +
+					(uv_stride * vertical_offset / 2) +
+					horizontal_offset / 2;
+		v_offset = u_offset + (uv_stride * height / 2);
+		u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
+					(horizontal_offset / 2) -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					u_offset;
+		v_fix = v ? (v + (uv_stride * vertical_offset / 2) +
+					(horizontal_offset / 2) -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					v_offset;
+
+		break;
+	case IPU_PIX_FMT_YVU420P:
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		v_offset = stride * (height - vertical_offset - 1) +
+					(stride - horizontal_offset) +
+					(uv_stride * vertical_offset / 2) +
+					horizontal_offset / 2;
+		u_offset = v_offset + (uv_stride * height / 2);
+		u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
+					(horizontal_offset / 2) -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					u_offset;
+		v_fix = v ? (v + (uv_stride * vertical_offset / 2) +
+					(horizontal_offset / 2) -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					v_offset;
+
+		break;
+	case IPU_PIX_FMT_YVU422P:
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		v_offset = stride * (height - vertical_offset - 1) +
+					(stride - horizontal_offset) +
+					(uv_stride * vertical_offset) +
+					horizontal_offset / 2;
+		u_offset = v_offset + uv_stride * height;
+		u_fix = u ? (u + (uv_stride * vertical_offset) +
+					horizontal_offset / 2 -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					u_offset;
+		v_fix = v ? (v + (uv_stride * vertical_offset) +
+					horizontal_offset / 2 -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					v_offset;
+		break;
+	case IPU_PIX_FMT_YUV422P:
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = stride * (height - vertical_offset - 1) +
+					(stride - horizontal_offset) +
+					(uv_stride * vertical_offset) +
+					horizontal_offset / 2;
+		v_offset = u_offset + uv_stride * height;
+		u_fix = u ? (u + (uv_stride * vertical_offset) +
+					horizontal_offset / 2 -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					u_offset;
+		v_fix = v ? (v + (uv_stride * vertical_offset) +
+					horizontal_offset / 2 -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					v_offset;
+		break;
+
+	case IPU_PIX_FMT_NV12:
+		uv_stride = stride;
+		u_offset = stride * (height - vertical_offset - 1) +
+					(stride - horizontal_offset) +
+					(uv_stride * vertical_offset / 2) +
+					horizontal_offset;
+		u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
+					horizontal_offset -
+					(stride * vertical_offset) - (horizontal_offset)) :
+					u_offset;
+
+		break;
+	default:
+		dev_err(ipu->dev, "mxc ipu: unimplemented pixel format\n");
+		break;
+	}
+
+
+
+	if (u_fix > u_offset)
+		u_offset = u_fix;
+
+	if (v_fix > v_offset)
+		v_offset = v_fix;
+
+	/* UBO and VBO are 22-bit and 8-byte aligned */
+	if (u_offset/8 > 0x3fffff)
+		dev_warn(ipu->dev,
+			"IDMAC%d's U offset exceeds IPU limitation\n", ch);
+	if (v_offset/8 > 0x3fffff)
+		dev_warn(ipu->dev,
+			"IDMAC%d's V offset exceeds IPU limitation\n", ch);
+	if (u_offset%8)
+		dev_warn(ipu->dev,
+			"IDMAC%d's U offset is not 8-byte aligned\n", ch);
+	if (v_offset%8)
+		dev_warn(ipu->dev,
+			"IDMAC%d's V offset is not 8-byte aligned\n", ch);
+
+	old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22);
+	if (old_offset != u_offset / 8)
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22, u_offset / 8);
+	old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22);
+	if (old_offset != v_offset / 8)
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22, v_offset / 8);
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+	if (sub_ch <= 0)
+		return;
+	old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 46, 22);
+	if (old_offset != u_offset / 8)
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 46, 22, u_offset / 8);
+	old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 68, 22);
+	if (old_offset != v_offset / 8)
+		ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 68, 22, v_offset / 8);
+};
+
+static inline void _ipu_ch_params_set_alpha_width(struct ipu_soc *ipu, uint32_t ch, int alpha_width)
+{
+	int32_t sub_ch = 0;
+
+	ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch), 1, 125, 3, alpha_width - 1);
+
+	sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
+	if (sub_ch <= 0)
+		return;
+	ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 125, 3, alpha_width - 1);
+};
+
+#endif
diff --git a/drivers/mxc/ipu3/ipu_prv.h b/drivers/mxc/ipu3/ipu_prv.h
new file mode 100644
index 00000000000..7c803a1693d
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_prv.h
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __INCLUDE_IPU_PRV_H__
+#define __INCLUDE_IPU_PRV_H__
+
+#include <linux/types.h>
+#include <linux/device.h>
+#include <mach/clock.h>
+#include <linux/clkdev.h>
+#include <linux/interrupt.h>
+#include <linux/fsl_devices.h>
+
+#ifdef CONFIG_MXC_IPU_V3H
+#define MXC_IPU_MAX_NUM	2
+#else
+#define MXC_IPU_MAX_NUM	1
+#endif
+
+/* Globals */
+extern int dmfc_type_setup;
+extern struct clk ipu_pixel_clk[];
+extern struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][2];
+
+#define IDMA_CHAN_INVALID	0xFF
+#define HIGH_RESOLUTION_WIDTH	1024
+
+struct ipu_irq_node {
+	irqreturn_t(*handler) (int, void *);	/*!< the ISR */
+	const char *name;	/*!< device associated with the interrupt */
+	void *dev_id;		/*!< some unique information for the ISR */
+	__u32 flags;		/*!< not used */
+};
+
+enum csc_type_t {
+	RGB2YUV = 0,
+	YUV2RGB,
+	RGB2RGB,
+	YUV2YUV,
+	CSC_NONE,
+	CSC_NUM
+};
+
+struct ipu_soc {
+	bool online;
+
+	/*clk*/
+	struct clk *ipu_clk;
+	struct clk *di_clk[2];
+	struct clk *csi_clk[2];
+	struct clk pixel_clk[2];
+
+	/*irq*/
+	int irq_sync;
+	int irq_err;
+	struct ipu_irq_node irq_list[IPU_IRQ_COUNT];
+
+	/*reg*/
+	u32 *cm_reg;
+	u32 *idmac_reg;
+	u32 *dp_reg;
+	u32 *ic_reg;
+	u32 *dc_reg;
+	u32 *dc_tmpl_reg;
+	u32 *dmfc_reg;
+	u32 *di_reg[2];
+	u32 *smfc_reg;
+	u32 *csi_reg[2];
+	u32 *cpmem_base;
+	u32 *tpmem_base;
+	u32 *disp_base[2];
+	u32 *vdi_reg;
+
+	struct device *dev;
+
+	ipu_channel_t csi_channel[2];
+	ipu_channel_t using_ic_dirct_ch;
+	unsigned char dc_di_assignment[10];
+	bool sec_chan_en[24];
+	bool thrd_chan_en[24];
+	bool chan_is_interlaced[52];
+	uint32_t channel_init_mask;
+	uint32_t channel_enable_mask;
+
+	/*use count*/
+	atomic_t ipu_use_count;
+	int dc_use_count;
+	int dp_use_count;
+	int dmfc_use_count;
+	int smfc_use_count;
+	int ic_use_count;
+	int rot_use_count;
+	int vdi_use_count;
+	int di_use_count[2];
+	int csi_use_count[2];
+
+	struct mutex mutex_lock;
+	spinlock_t spin_lock;
+
+	int dmfc_size_28;
+	int dmfc_size_29;
+	int dmfc_size_24;
+	int dmfc_size_27;
+	int dmfc_size_23;
+
+	enum csc_type_t fg_csc_type;
+	enum csc_type_t bg_csc_type;
+	bool color_key_4rgb;
+	bool dc_swap;
+	struct completion dc_comp;
+
+	/* for power gating */
+	u32 ipu_conf_reg;
+	u32 ic_conf_reg;
+	u32 cha_db_mode_reg[4];
+	u32 cha_trb_mode_reg[2];
+	u32 idma_sub_addr_reg[5];
+	u32 idma_enable_reg[2];
+	u32 buf_ready_reg[10];
+
+	/*ipu processing driver*/
+	struct list_head task_list[2];
+	struct mutex task_lock[2];
+	wait_queue_head_t waitq[2];
+	struct task_struct *thread[2];
+	struct rot_mem {
+		void *vaddr;
+		dma_addr_t paddr;
+		int size;
+	} rot_dma[2];
+};
+
+struct ipu_channel {
+	u8 video_in_dma;
+	u8 alpha_in_dma;
+	u8 graph_in_dma;
+	u8 out_dma;
+};
+
+enum ipu_dmfc_type {
+	DMFC_NORMAL = 0,
+	DMFC_HIGH_RESOLUTION_DC,
+	DMFC_HIGH_RESOLUTION_DP,
+	DMFC_HIGH_RESOLUTION_ONLY_DP,
+};
+
+static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
+{
+	return readl(ipu->cm_reg + offset);
+}
+
+static inline void ipu_cm_write(struct ipu_soc *ipu,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->cm_reg + offset);
+}
+
+static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
+{
+	return readl(ipu->idmac_reg + offset);
+}
+
+static inline void ipu_idmac_write(struct ipu_soc *ipu,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->idmac_reg + offset);
+}
+
+static inline u32 ipu_dc_read(struct ipu_soc *ipu, unsigned offset)
+{
+	return readl(ipu->dc_reg + offset);
+}
+
+static inline void ipu_dc_write(struct ipu_soc *ipu,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->dc_reg + offset);
+}
+
+static inline u32 ipu_dc_tmpl_read(struct ipu_soc *ipu, unsigned offset)
+{
+	return readl(ipu->dc_tmpl_reg + offset);
+}
+
+static inline void ipu_dc_tmpl_write(struct ipu_soc *ipu,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->dc_tmpl_reg + offset);
+}
+
+static inline u32 ipu_dmfc_read(struct ipu_soc *ipu, unsigned offset)
+{
+	return readl(ipu->dmfc_reg + offset);
+}
+
+static inline void ipu_dmfc_write(struct ipu_soc *ipu,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->dmfc_reg + offset);
+}
+
+static inline u32 ipu_dp_read(struct ipu_soc *ipu, unsigned offset)
+{
+	return readl(ipu->dp_reg + offset);
+}
+
+static inline void ipu_dp_write(struct ipu_soc *ipu,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->dp_reg + offset);
+}
+
+static inline u32 ipu_di_read(struct ipu_soc *ipu, int di, unsigned offset)
+{
+	return readl(ipu->di_reg[di] + offset);
+}
+
+static inline void ipu_di_write(struct ipu_soc *ipu, int di,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->di_reg[di] + offset);
+}
+
+static inline u32 ipu_csi_read(struct ipu_soc *ipu, int csi, unsigned offset)
+{
+	return readl(ipu->csi_reg[csi] + offset);
+}
+
+static inline void ipu_csi_write(struct ipu_soc *ipu, int csi,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->csi_reg[csi] + offset);
+}
+
+static inline u32 ipu_smfc_read(struct ipu_soc *ipu, unsigned offset)
+{
+	return readl(ipu->smfc_reg + offset);
+}
+
+static inline void ipu_smfc_write(struct ipu_soc *ipu,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->smfc_reg + offset);
+}
+
+static inline u32 ipu_vdi_read(struct ipu_soc *ipu, unsigned offset)
+{
+	return readl(ipu->vdi_reg + offset);
+}
+
+static inline void ipu_vdi_write(struct ipu_soc *ipu,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->vdi_reg + offset);
+}
+
+static inline u32 ipu_ic_read(struct ipu_soc *ipu, unsigned offset)
+{
+	return readl(ipu->ic_reg + offset);
+}
+
+static inline void ipu_ic_write(struct ipu_soc *ipu,
+		u32 value, unsigned offset)
+{
+	writel(value, ipu->ic_reg + offset);
+}
+
+int register_ipu_device(struct ipu_soc *ipu, int id);
+void unregister_ipu_device(struct ipu_soc *ipu, int id);
+ipu_color_space_t format_to_colorspace(uint32_t fmt);
+bool ipu_pixel_format_has_alpha(uint32_t fmt);
+
+void ipu_dump_registers(struct ipu_soc *ipu);
+
+uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel);
+
+void ipu_disp_init(struct ipu_soc *ipu);
+void _ipu_init_dc_mappings(struct ipu_soc *ipu);
+int _ipu_dp_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t in_pixel_fmt,
+		 uint32_t out_pixel_fmt);
+void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel);
+void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt);
+void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan);
+void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel);
+void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap);
+void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first);
+void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width);
+void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size);
+int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel);
+
+void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel);
+void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel);
+void _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params, bool src_is_csi);
+void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
+void _ipu_vdi_uninit(struct ipu_soc *ipu);
+void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu);
+void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params);
+void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu);
+void _ipu_ic_init_csi(struct ipu_soc *ipu, ipu_channel_params_t *params);
+void _ipu_ic_uninit_csi(struct ipu_soc *ipu);
+void _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params, bool src_is_csi);
+void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu);
+void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params);
+void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu);
+void _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
+void _ipu_ic_uninit_pp(struct ipu_soc *ipu);
+void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
+void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu);
+int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan, uint16_t width, uint16_t height,
+		      int burst_size, ipu_rotate_mode_t rot);
+void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu);
+int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi);
+void ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
+		uint32_t g_value, uint32_t b_value,
+		uint32_t pix_clk, uint32_t csi);
+void _ipu_csi_ccir_err_detection_enable(struct ipu_soc *ipu, uint32_t csi);
+void _ipu_csi_ccir_err_detection_disable(struct ipu_soc *ipu, uint32_t csi);
+void _ipu_smfc_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t mipi_id, uint32_t csi);
+void _ipu_smfc_set_burst_size(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t bs);
+void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
+int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
+		int16_t x_pos, int16_t y_pos);
+int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
+		int16_t *x_pos, int16_t *y_pos);
+void _ipu_get(struct ipu_soc *ipu);
+void _ipu_put(struct ipu_soc *ipu);
+void _ipu_lock(struct ipu_soc *ipu);
+void _ipu_unlock(struct ipu_soc *ipu);
+#endif				/* __INCLUDE_IPU_PRV_H__ */
diff --git a/drivers/mxc/ipu3/ipu_regs.h b/drivers/mxc/ipu3/ipu_regs.h
new file mode 100644
index 00000000000..c63c9323113
--- /dev/null
+++ b/drivers/mxc/ipu3/ipu_regs.h
@@ -0,0 +1,697 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * @file ipu_regs.h
+ *
+ * @brief IPU Register definitions
+ *
+ * @ingroup IPU
+ */
+#ifndef __IPU_REGS_INCLUDED__
+#define __IPU_REGS_INCLUDED__
+
+/*
+ * hw_rev 2: IPUV3DEX
+ * hw_rev 3: IPUV3M
+ * hw_rev 4: IPUV3H
+ */
+extern int g_ipu_hw_rev;
+
+#define IPU_DISP0_BASE		0x00000000
+#define IPU_MCU_T_DEFAULT	8
+#define IPU_DISP1_BASE		({g_ipu_hw_rev < 4 ? \
+				(IPU_MCU_T_DEFAULT << 25) : \
+				(0x00000000); })
+#define IPUV3DEX_REG_BASE	0x1E000000
+#define IPUV3M_REG_BASE		0x06000000
+#define IPUV3H_REG_BASE		0x00200000
+
+#define IPU_CM_REG_BASE		0x00000000
+#define IPU_IDMAC_REG_BASE	0x00008000
+#define IPU_ISP_REG_BASE	0x00010000
+#define IPU_DP_REG_BASE		0x00018000
+#define IPU_IC_REG_BASE		0x00020000
+#define IPU_IRT_REG_BASE	0x00028000
+#define IPU_CSI0_REG_BASE	0x00030000
+#define IPU_CSI1_REG_BASE	0x00038000
+#define IPU_DI0_REG_BASE	0x00040000
+#define IPU_DI1_REG_BASE	0x00048000
+#define IPU_SMFC_REG_BASE	0x00050000
+#define IPU_DC_REG_BASE		0x00058000
+#define IPU_DMFC_REG_BASE	0x00060000
+#define IPU_VDI_REG_BASE	0x00068000
+#define IPU_CPMEM_REG_BASE 	({g_ipu_hw_rev >= 4 ? \
+				   (0x00100000) : \
+				   (0x01000000); })
+#define IPU_LUT_REG_BASE	0x01020000
+#define IPU_SRM_REG_BASE 	({g_ipu_hw_rev >= 4 ? \
+				   (0x00140000) : \
+				   (0x01040000); })
+#define IPU_TPM_REG_BASE 	({g_ipu_hw_rev >= 4 ? \
+				   (0x00160000) : \
+				   (0x01060000); })
+#define IPU_DC_TMPL_REG_BASE 	({g_ipu_hw_rev >= 4 ? \
+				   (0x00180000) : \
+				   (0x01080000); })
+#define IPU_ISP_TBPR_REG_BASE	0x010C0000
+
+/* Register addresses */
+/* IPU Common registers */
+#define IPU_CONF		(0)
+
+#define IPU_SRM_PRI1		(0x00A0/4)
+#define IPU_SRM_PRI2		(0x00A4/4)
+#define IPU_FS_PROC_FLOW1	(0x00A8/4)
+#define IPU_FS_PROC_FLOW2	(0x00AC/4)
+#define IPU_FS_PROC_FLOW3	(0x00B0/4)
+#define IPU_FS_DISP_FLOW1	(0x00B4/4)
+#define IPU_FS_DISP_FLOW2	(0x00B8/4)
+#define IPU_SKIP		(0x00BC/4)
+#define IPU_DISP_ALT_CONF	(0x00C0/4)
+#define IPU_DISP_GEN		(0x00C4/4)
+#define IPU_DISP_ALT1		(0x00C8/4)
+#define IPU_DISP_ALT2		(0x00CC/4)
+#define IPU_DISP_ALT3		(0x00D0/4)
+#define IPU_DISP_ALT4		(0x00D4/4)
+#define IPU_SNOOP		(0x00D8/4)
+#define IPU_MEM_RST		(0x00DC/4)
+#define IPU_PM			(0x00E0/4)
+#define IPU_GPR			(0x00E4/4)
+#define IPU_CHA_DB_MODE_SEL(ch)	(0x0150/4 + (ch / 32))
+#define IPU_ALT_CHA_DB_MODE_SEL(ch) (0x0168/4 + (ch / 32))
+/*
+ * IPUv3D doesn't support triple buffer, so point
+ * IPU_CHA_TRB_MODE_SEL, IPU_CHA_TRIPLE_CUR_BUF and
+ * IPU_CHA_BUF2_RDY to readonly
+ * IPU_ALT_CUR_BUF0 for IPUv3D.
+ */
+#define IPU_CHA_TRB_MODE_SEL(ch) ({g_ipu_hw_rev >= 2 ? \
+				   (0x0178/4 + (ch / 32)) : \
+				   (0x012C/4); })
+#define IPU_CHA_TRIPLE_CUR_BUF(ch) ({g_ipu_hw_rev >= 2 ? \
+				     (0x0258/4 + ((ch*2) / 32)) : \
+				     (0x012C/4); })
+#define IPU_CHA_BUF2_RDY(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (0x0288/4 + (ch / 32)) : \
+				  (0x012C/4); })
+#define IPU_CHA_CUR_BUF(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (0x023C/4 + (ch / 32)) : \
+				  (0x0124/4 + (ch / 32)); })
+#define IPU_ALT_CUR_BUF0	({g_ipu_hw_rev >= 2 ? \
+				  (0x0244/4) : \
+				  (0x012C/4); })
+#define IPU_ALT_CUR_BUF1	({g_ipu_hw_rev >= 2 ? \
+				  (0x0248/4) : \
+				  (0x0130/4); })
+#define IPU_SRM_STAT		({g_ipu_hw_rev >= 2 ? \
+				  (0x024C/4) : \
+				  (0x0134/4); })
+#define IPU_PROC_TASK_STAT	({g_ipu_hw_rev >= 2 ? \
+				  (0x0250/4) : \
+				  (0x0138/4); })
+#define IPU_DISP_TASK_STAT	({g_ipu_hw_rev >= 2 ? \
+				  (0x0254/4) : \
+				  (0x013C/4); })
+#define IPU_CHA_BUF0_RDY(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (0x0268/4 + (ch / 32)) : \
+				  (0x0140/4 + (ch / 32)); })
+#define IPU_CHA_BUF1_RDY(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (0x0270/4 + (ch / 32)) : \
+				  (0x0148/4 + (ch / 32)); })
+#define IPU_ALT_CHA_BUF0_RDY(ch) ({g_ipu_hw_rev >= 2 ? \
+				   (0x0278/4 + (ch / 32)) : \
+				   (0x0158/4 + (ch / 32)); })
+#define IPU_ALT_CHA_BUF1_RDY(ch) ({g_ipu_hw_rev >= 2 ? \
+				   (0x0280/4 + (ch / 32)) : \
+				   (0x0160/4 + (ch / 32)); })
+
+#define IPU_INT_CTRL(n)		(0x003C/4 + ((n) - 1))
+#define IPU_INT_CTRL_IRQ(irq)	IPU_INT_CTRL(((irq) / 32))
+#define IPU_INT_STAT_IRQ(irq)	IPU_INT_STAT(((irq) / 32))
+#define IPU_INT_STAT(n)		({g_ipu_hw_rev >= 2 ? \
+				  (0x0200/4 + ((n) - 1)) : \
+				  (0x00E8/4 + ((n) - 1)); })
+
+#define IPUIRQ_2_STATREG(irq)	(IPU_INT_STAT(1) + ((irq) / 32))
+#define IPUIRQ_2_CTRLREG(irq)	(IPU_INT_CTRL(1) + ((irq) / 32))
+#define IPUIRQ_2_MASK(irq)	(1UL << ((irq) & 0x1F))
+
+#define VDI_FSIZE (0)
+#define VDI_C (0x0004/4)
+
+/* CMOS Sensor Interface Registers */
+#define CSI_SENS_CONF		(0)
+#define CSI_SENS_FRM_SIZE	(0x0004/4)
+#define CSI_ACT_FRM_SIZE	(0x0008/4)
+#define CSI_OUT_FRM_CTRL	(0x000C/4)
+#define CSI_TST_CTRL		(0x0010/4)
+#define CSI_CCIR_CODE_1		(0x0014/4)
+#define CSI_CCIR_CODE_2		(0x0018/4)
+#define CSI_CCIR_CODE_3		(0x001C/4)
+#define CSI_MIPI_DI		(0x0020/4)
+#define CSI_SKIP		(0x0024/4)
+#define CSI_CPD_CTRL		(0x0028/4)
+#define CSI_CPD_RC(n)		(0x002C/4 + n)
+#define CSI_CPD_RS(n)		(0x004C/4 + n)
+#define CSI_CPD_GRC(n)		(0x005C/4 + n)
+#define CSI_CPD_GRS(n)		(0x007C/4 + n)
+#define CSI_CPD_GBC(n)		(0x008C/4 + n)
+#define CSI_CPD_GBS(n)		(0x00AC/4 + n)
+#define CSI_CPD_BC(n)		(0x00BC/4 + n)
+#define CSI_CPD_BS(n)		(0x00DC/4 + n)
+#define CSI_CPD_OFFSET1		(0x00EC/4)
+#define CSI_CPD_OFFSET2		(0x00F0/4)
+
+/*SMFC Registers */
+#define SMFC_MAP	(0)
+#define SMFC_WMC	(0x0004/4)
+#define SMFC_BS		(0x0008/4)
+
+/* Image Converter Registers */
+#define IC_CONF			0
+#define IC_PRP_ENC_RSC		(0x0004/4)
+#define IC_PRP_VF_RSC		(0x0008/4)
+#define IC_PP_RSC		(0x000C/4)
+#define IC_CMBP_1		(0x0010/4)
+#define IC_CMBP_2		(0x0014/4)
+#define IC_IDMAC_1		(0x0018/4)
+#define IC_IDMAC_2		(0x001C/4)
+#define IC_IDMAC_3		(0x0020/4)
+#define IC_IDMAC_4		(0x0024/4)
+
+#define IDMAC_CONF		(0x0000)
+#define IDMAC_CHA_EN(ch)	(0x0004/4 + (ch/32))
+#define IDMAC_SEP_ALPHA		(0x000C/4)
+#define IDMAC_ALT_SEP_ALPHA	(0x0010/4)
+#define IDMAC_CHA_PRI(ch)	(0x0014/4 + (ch/32))
+#define IDMAC_WM_EN(ch)		(0x001C/4 + (ch/32))
+#define IDMAC_CH_LOCK_EN_1	({g_ipu_hw_rev >= 2 ? \
+				  (0x0024/4) : 0; })
+#define IDMAC_CH_LOCK_EN_2	({g_ipu_hw_rev >= 2 ? \
+				  (0x0028/4) : \
+				  (0x0024/4); })
+#define IDMAC_SUB_ADDR_0	({g_ipu_hw_rev >= 2 ? \
+				  (0x002C/4) : \
+				  (0x0028/4); })
+#define IDMAC_SUB_ADDR_1	({g_ipu_hw_rev >= 2 ? \
+				  (0x0030/4) : \
+				  (0x002C/4); })
+#define IDMAC_SUB_ADDR_2	({g_ipu_hw_rev >= 2 ? \
+				  (0x0034/4) : \
+				  (0x0030/4); })
+/*
+ * IPUv3D doesn't support IDMAC_SUB_ADDR_3 and IDMAC_SUB_ADDR_4,
+ * so point them to readonly IDMAC_CHA_BUSY1 for IPUv3D.
+ */
+#define IDMAC_SUB_ADDR_3	({g_ipu_hw_rev >= 2 ? \
+				  (0x0038/4) : \
+				  (0x0040/4); })
+#define IDMAC_SUB_ADDR_4	({g_ipu_hw_rev >= 2 ? \
+				  (0x003c/4) : \
+				  (0x0040/4); })
+#define IDMAC_BAND_EN(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (0x0040/4 + (ch/32)) : \
+				  (0x0034/4 + (ch/32)); })
+#define IDMAC_CHA_BUSY(ch)	({g_ipu_hw_rev >= 2 ? \
+				  (0x0100/4 + (ch/32)) : \
+				  (0x0040/4 + (ch/32)); })
+
+#define DI_GENERAL		(0)
+#define DI_BS_CLKGEN0		(0x0004/4)
+#define DI_BS_CLKGEN1		(0x0008/4)
+
+#define DI_SW_GEN0(gen)		(0x000C/4 + (gen - 1))
+#define DI_SW_GEN1(gen)		(0x0030/4 + (gen - 1))
+#define DI_STP_REP(gen)		(0x0148/4 + (gen - 1)/2)
+#define DI_SYNC_AS_GEN		(0x0054/4)
+#define DI_DW_GEN(gen)		(0x0058/4 + gen)
+#define DI_DW_SET(gen, set)	(0x0088/4 + gen + 0xC*set)
+#define DI_SER_CONF		(0x015C/4)
+#define DI_SSC			(0x0160/4)
+#define DI_POL			(0x0164/4)
+#define DI_AW0			(0x0168/4)
+#define DI_AW1			(0x016C/4)
+#define DI_SCR_CONF		(0x0170/4)
+#define DI_STAT			(0x0174/4)
+
+#define DMFC_RD_CHAN		(0)
+#define DMFC_WR_CHAN		(0x0004/4)
+#define DMFC_WR_CHAN_DEF	(0x0008/4)
+#define DMFC_DP_CHAN		(0x000C/4)
+#define DMFC_DP_CHAN_DEF	(0x0010/4)
+#define DMFC_GENERAL1		(0x0014/4)
+#define DMFC_GENERAL2		(0x0018/4)
+#define DMFC_IC_CTRL		(0x001C/4)
+#define DMFC_STAT		(0x0020/4)
+
+#define DC_MAP_CONF_PTR(n)	(0x0108/4 + n/2)
+#define DC_MAP_CONF_VAL(n)	(0x0144/4 + n/2)
+
+#define _RL_CH_2_OFFSET(ch)	((ch == 0) ? 8 : ( \
+				 (ch == 1) ? 0x24 : ( \
+				 (ch == 2) ? 0x40 : ( \
+				 (ch == 5) ? 0x64 : ( \
+				 (ch == 6) ? 0x80 : ( \
+				 (ch == 8) ? 0x9C : ( \
+				 (ch == 9) ? 0xBC : (-1))))))))
+#define DC_RL_CH(ch, evt)	(_RL_CH_2_OFFSET(ch)/4 + evt/2)
+
+#define DC_EVT_NF		0
+#define DC_EVT_NL		1
+#define DC_EVT_EOF		2
+#define DC_EVT_NFIELD		3
+#define DC_EVT_EOL		4
+#define DC_EVT_EOFIELD		5
+#define DC_EVT_NEW_ADDR		6
+#define DC_EVT_NEW_CHAN		7
+#define DC_EVT_NEW_DATA		8
+
+#define DC_EVT_NEW_ADDR_W_0	0
+#define DC_EVT_NEW_ADDR_W_1	1
+#define DC_EVT_NEW_CHAN_W_0	2
+#define DC_EVT_NEW_CHAN_W_1	3
+#define DC_EVT_NEW_DATA_W_0	4
+#define DC_EVT_NEW_DATA_W_1	5
+#define DC_EVT_NEW_ADDR_R_0	6
+#define DC_EVT_NEW_ADDR_R_1	7
+#define DC_EVT_NEW_CHAN_R_0	8
+#define DC_EVT_NEW_CHAN_R_1	9
+#define DC_EVT_NEW_DATA_R_0	10
+#define DC_EVT_NEW_DATA_R_1	11
+#define DC_EVEN_UGDE0 		12
+#define DC_ODD_UGDE0 		13
+#define DC_EVEN_UGDE1 		14
+#define DC_ODD_UGDE1 		15
+#define DC_EVEN_UGDE2 		16
+#define DC_ODD_UGDE2 		17
+#define DC_EVEN_UGDE3 		18
+#define DC_ODD_UGDE3 		19
+
+#define dc_ch_offset(ch) \
+({ \
+	const u8 _offset[] = { \
+		0, 0x1C, 0x38, 0x54, 0x58, 0x5C, 0x78, 0, 0x94, 0xB4}; \
+	_offset[ch]; \
+})
+#define DC_WR_CH_CONF(ch)	(dc_ch_offset(ch)/4)
+#define DC_WR_CH_ADDR(ch)	(dc_ch_offset(ch)/4 + 4/4)
+
+#define DC_WR_CH_CONF_1		(0x001C/4)
+#define DC_WR_CH_ADDR_1		(0x0020/4)
+#define DC_WR_CH_CONF_5		(0x005C/4)
+#define DC_WR_CH_ADDR_5		(0x0060/4)
+#define DC_GEN			(0x00D4/4)
+#define DC_DISP_CONF1(disp)	(0x00D8/4 + disp)
+#define DC_DISP_CONF2(disp)	(0x00E8/4 + disp)
+#define DC_STAT			(0x01C8/4)
+#define DC_UGDE_0(evt)		(0x0174/4 + evt*4)
+#define DC_UGDE_1(evt)		(0x0178/4 + evt*4)
+#define DC_UGDE_2(evt)		(0x017C/4 + evt*4)
+#define DC_UGDE_3(evt)		(0x0180/4 + evt*4)
+
+#define DP_SYNC 0
+#define DP_ASYNC0 0x60
+#define DP_ASYNC1 0xBC
+#define DP_COM_CONF(flow)	(flow/4)
+#define DP_GRAPH_WIND_CTRL(flow) (0x0004/4 + flow/4)
+#define DP_FG_POS(flow)		(0x0008/4 + flow/4)
+#define DP_GAMMA_C(flow, i)	(0x0014/4 + flow/4 + i)
+#define DP_GAMMA_S(flow, i)	(0x0034/4 + flow/4 + i)
+#define DP_CSC_A_0(flow)	(0x0044/4 + flow/4)
+#define DP_CSC_A_1(flow)	(0x0048/4 + flow/4)
+#define DP_CSC_A_2(flow)	(0x004C/4 + flow/4)
+#define DP_CSC_A_3(flow)	(0x0050/4 + flow/4)
+#define DP_CSC_0(flow)		(0x0054/4 + flow/4)
+#define DP_CSC_1(flow)		(0x0058/4 + flow/4)
+
+enum {
+	IPU_CONF_CSI0_EN = 0x00000001,
+	IPU_CONF_CSI1_EN = 0x00000002,
+	IPU_CONF_IC_EN = 0x00000004,
+	IPU_CONF_ROT_EN = 0x00000008,
+	IPU_CONF_ISP_EN = 0x00000010,
+	IPU_CONF_DP_EN = 0x00000020,
+	IPU_CONF_DI0_EN = 0x00000040,
+	IPU_CONF_DI1_EN = 0x00000080,
+	IPU_CONF_DMFC_EN = 0x00000400,
+	IPU_CONF_SMFC_EN = 0x00000100,
+	IPU_CONF_DC_EN = 0x00000200,
+	IPU_CONF_VDI_EN = 0x00001000,
+	IPU_CONF_IDMAC_DIS = 0x00400000,
+	IPU_CONF_IC_DMFC_SEL = 0x02000000,
+	IPU_CONF_IC_DMFC_SYNC = 0x04000000,
+	IPU_CONF_VDI_DMFC_SYNC = 0x08000000,
+	IPU_CONF_CSI0_DATA_SOURCE = 0x10000000,
+	IPU_CONF_CSI0_DATA_SOURCE_OFFSET = 28,
+	IPU_CONF_CSI1_DATA_SOURCE = 0x20000000,
+	IPU_CONF_IC_INPUT = 0x40000000,
+	IPU_CONF_CSI_SEL = 0x80000000,
+
+	DI0_COUNTER_RELEASE = 0x01000000,
+	DI1_COUNTER_RELEASE = 0x02000000,
+
+	FS_PRPVF_ROT_SRC_SEL_MASK = 0x00000F00,
+	FS_PRPVF_ROT_SRC_SEL_OFFSET = 8,
+	FS_PRPENC_ROT_SRC_SEL_MASK = 0x0000000F,
+	FS_PRPENC_ROT_SRC_SEL_OFFSET = 0,
+	FS_PP_ROT_SRC_SEL_MASK = 0x000F0000,
+	FS_PP_ROT_SRC_SEL_OFFSET = 16,
+	FS_PP_SRC_SEL_MASK = 0x0000F000,
+	FS_PP_SRC_SEL_OFFSET = 12,
+	FS_PRP_SRC_SEL_MASK = 0x0F000000,
+	FS_PRP_SRC_SEL_OFFSET = 24,
+	FS_VF_IN_VALID = 0x80000000,
+	FS_ENC_IN_VALID = 0x40000000,
+	FS_VDI_SRC_SEL_MASK = 0x30000000,
+	FS_VDI_SRC_SEL_OFFSET = 28,
+
+
+	FS_PRPENC_DEST_SEL_MASK = 0x0000000F,
+	FS_PRPENC_DEST_SEL_OFFSET = 0,
+	FS_PRPVF_DEST_SEL_MASK = 0x000000F0,
+	FS_PRPVF_DEST_SEL_OFFSET = 4,
+	FS_PRPVF_ROT_DEST_SEL_MASK = 0x00000F00,
+	FS_PRPVF_ROT_DEST_SEL_OFFSET = 8,
+	FS_PP_DEST_SEL_MASK = 0x0000F000,
+	FS_PP_DEST_SEL_OFFSET = 12,
+	FS_PP_ROT_DEST_SEL_MASK = 0x000F0000,
+	FS_PP_ROT_DEST_SEL_OFFSET = 16,
+	FS_PRPENC_ROT_DEST_SEL_MASK = 0x00F00000,
+	FS_PRPENC_ROT_DEST_SEL_OFFSET = 20,
+
+	FS_SMFC0_DEST_SEL_MASK = 0x0000000F,
+	FS_SMFC0_DEST_SEL_OFFSET = 0,
+	FS_SMFC1_DEST_SEL_MASK = 0x00000070,
+	FS_SMFC1_DEST_SEL_OFFSET = 4,
+	FS_SMFC2_DEST_SEL_MASK = 0x00000780,
+	FS_SMFC2_DEST_SEL_OFFSET = 7,
+	FS_SMFC3_DEST_SEL_MASK = 0x00003800,
+	FS_SMFC3_DEST_SEL_OFFSET = 11,
+
+	FS_DC1_SRC_SEL_MASK = 0x00F00000,
+	FS_DC1_SRC_SEL_OFFSET = 20,
+	FS_DC2_SRC_SEL_MASK = 0x000F0000,
+	FS_DC2_SRC_SEL_OFFSET = 16,
+	FS_DP_SYNC0_SRC_SEL_MASK = 0x0000000F,
+	FS_DP_SYNC0_SRC_SEL_OFFSET = 0,
+	FS_DP_SYNC1_SRC_SEL_MASK = 0x000000F0,
+	FS_DP_SYNC1_SRC_SEL_OFFSET = 4,
+	FS_DP_ASYNC0_SRC_SEL_MASK = 0x00000F00,
+	FS_DP_ASYNC0_SRC_SEL_OFFSET = 8,
+	FS_DP_ASYNC1_SRC_SEL_MASK = 0x0000F000,
+	FS_DP_ASYNC1_SRC_SEL_OFFSET = 12,
+
+	FS_AUTO_REF_PER_MASK = 0,
+	FS_AUTO_REF_PER_OFFSET = 16,
+
+	TSTAT_VF_MASK = 0x0000000C,
+	TSTAT_VF_OFFSET = 2,
+	TSTAT_VF_ROT_MASK = 0x00000300,
+	TSTAT_VF_ROT_OFFSET = 8,
+	TSTAT_ENC_MASK = 0x00000003,
+	TSTAT_ENC_OFFSET = 0,
+	TSTAT_ENC_ROT_MASK = 0x000000C0,
+	TSTAT_ENC_ROT_OFFSET = 6,
+	TSTAT_PP_MASK = 0x00000030,
+	TSTAT_PP_OFFSET = 4,
+	TSTAT_PP_ROT_MASK = 0x00000C00,
+	TSTAT_PP_ROT_OFFSET = 10,
+
+	TASK_STAT_IDLE = 0,
+	TASK_STAT_ACTIVE = 1,
+	TASK_STAT_WAIT4READY = 2,
+
+	/* Image Converter Register bits */
+	IC_CONF_PRPENC_EN = 0x00000001,
+	IC_CONF_PRPENC_CSC1 = 0x00000002,
+	IC_CONF_PRPENC_ROT_EN = 0x00000004,
+	IC_CONF_PRPVF_EN = 0x00000100,
+	IC_CONF_PRPVF_CSC1 = 0x00000200,
+	IC_CONF_PRPVF_CSC2 = 0x00000400,
+	IC_CONF_PRPVF_CMB = 0x00000800,
+	IC_CONF_PRPVF_ROT_EN = 0x00001000,
+	IC_CONF_PP_EN = 0x00010000,
+	IC_CONF_PP_CSC1 = 0x00020000,
+	IC_CONF_PP_CSC2 = 0x00040000,
+	IC_CONF_PP_CMB = 0x00080000,
+	IC_CONF_PP_ROT_EN = 0x00100000,
+	IC_CONF_IC_GLB_LOC_A = 0x10000000,
+	IC_CONF_KEY_COLOR_EN = 0x20000000,
+	IC_CONF_RWS_EN = 0x40000000,
+	IC_CONF_CSI_MEM_WR_EN = 0x80000000,
+
+	IC_IDMAC_1_CB0_BURST_16 = 0x00000001,
+	IC_IDMAC_1_CB1_BURST_16 = 0x00000002,
+	IC_IDMAC_1_CB2_BURST_16 = 0x00000004,
+	IC_IDMAC_1_CB3_BURST_16 = 0x00000008,
+	IC_IDMAC_1_CB4_BURST_16 = 0x00000010,
+	IC_IDMAC_1_CB5_BURST_16 = 0x00000020,
+	IC_IDMAC_1_CB6_BURST_16 = 0x00000040,
+	IC_IDMAC_1_CB7_BURST_16 = 0x00000080,
+	IC_IDMAC_1_PRPENC_ROT_MASK = 0x00003800,
+	IC_IDMAC_1_PRPENC_ROT_OFFSET = 11,
+	IC_IDMAC_1_PRPVF_ROT_MASK = 0x0001C000,
+	IC_IDMAC_1_PRPVF_ROT_OFFSET = 14,
+	IC_IDMAC_1_PP_ROT_MASK = 0x000E0000,
+	IC_IDMAC_1_PP_ROT_OFFSET = 17,
+	IC_IDMAC_1_PP_FLIP_RS = 0x00400000,
+	IC_IDMAC_1_PRPVF_FLIP_RS = 0x00200000,
+	IC_IDMAC_1_PRPENC_FLIP_RS = 0x00100000,
+
+	IC_IDMAC_2_PRPENC_HEIGHT_MASK = 0x000003FF,
+	IC_IDMAC_2_PRPENC_HEIGHT_OFFSET = 0,
+	IC_IDMAC_2_PRPVF_HEIGHT_MASK = 0x000FFC00,
+	IC_IDMAC_2_PRPVF_HEIGHT_OFFSET = 10,
+	IC_IDMAC_2_PP_HEIGHT_MASK = 0x3FF00000,
+	IC_IDMAC_2_PP_HEIGHT_OFFSET = 20,
+
+	IC_IDMAC_3_PRPENC_WIDTH_MASK = 0x000003FF,
+	IC_IDMAC_3_PRPENC_WIDTH_OFFSET = 0,
+	IC_IDMAC_3_PRPVF_WIDTH_MASK = 0x000FFC00,
+	IC_IDMAC_3_PRPVF_WIDTH_OFFSET = 10,
+	IC_IDMAC_3_PP_WIDTH_MASK = 0x3FF00000,
+	IC_IDMAC_3_PP_WIDTH_OFFSET = 20,
+
+	CSI_SENS_CONF_DATA_FMT_SHIFT = 8,
+	CSI_SENS_CONF_DATA_FMT_MASK = 0x00000700,
+	CSI_SENS_CONF_DATA_FMT_RGB_YUV444 = 0L,
+	CSI_SENS_CONF_DATA_FMT_YUV422_YUYV = 1L,
+	CSI_SENS_CONF_DATA_FMT_YUV422_UYVY = 2L,
+	CSI_SENS_CONF_DATA_FMT_BAYER = 3L,
+	CSI_SENS_CONF_DATA_FMT_RGB565 = 4L,
+	CSI_SENS_CONF_DATA_FMT_RGB555 = 5L,
+	CSI_SENS_CONF_DATA_FMT_RGB444 = 6L,
+	CSI_SENS_CONF_DATA_FMT_JPEG = 7L,
+
+	CSI_SENS_CONF_VSYNC_POL_SHIFT = 0,
+	CSI_SENS_CONF_HSYNC_POL_SHIFT = 1,
+	CSI_SENS_CONF_DATA_POL_SHIFT = 2,
+	CSI_SENS_CONF_PIX_CLK_POL_SHIFT = 3,
+	CSI_SENS_CONF_SENS_PRTCL_MASK = 0x00000070L,
+	CSI_SENS_CONF_SENS_PRTCL_SHIFT = 4,
+	CSI_SENS_CONF_PACK_TIGHT_SHIFT = 7,
+	CSI_SENS_CONF_DATA_WIDTH_SHIFT = 11,
+	CSI_SENS_CONF_EXT_VSYNC_SHIFT = 15,
+	CSI_SENS_CONF_DIVRATIO_SHIFT = 16,
+
+	CSI_SENS_CONF_DIVRATIO_MASK = 0x00FF0000L,
+	CSI_SENS_CONF_DATA_DEST_SHIFT = 24,
+	CSI_SENS_CONF_DATA_DEST_MASK = 0x07000000L,
+	CSI_SENS_CONF_JPEG8_EN_SHIFT = 27,
+	CSI_SENS_CONF_JPEG_EN_SHIFT = 28,
+	CSI_SENS_CONF_FORCE_EOF_SHIFT = 29,
+	CSI_SENS_CONF_DATA_EN_POL_SHIFT = 31,
+
+	CSI_DATA_DEST_ISP = 1L,
+	CSI_DATA_DEST_IC = 2L,
+	CSI_DATA_DEST_IDMAC = 4L,
+
+	CSI_CCIR_ERR_DET_EN = 0x01000000L,
+	CSI_HORI_DOWNSIZE_EN = 0x80000000L,
+	CSI_VERT_DOWNSIZE_EN = 0x40000000L,
+	CSI_TEST_GEN_MODE_EN = 0x01000000L,
+
+	CSI_HSC_MASK = 0x1FFF0000,
+	CSI_HSC_SHIFT = 16,
+	CSI_VSC_MASK = 0x00000FFF,
+	CSI_VSC_SHIFT = 0,
+
+	CSI_TEST_GEN_R_MASK = 0x000000FFL,
+	CSI_TEST_GEN_R_SHIFT = 0,
+	CSI_TEST_GEN_G_MASK = 0x0000FF00L,
+	CSI_TEST_GEN_G_SHIFT = 8,
+	CSI_TEST_GEN_B_MASK = 0x00FF0000L,
+	CSI_TEST_GEN_B_SHIFT = 16,
+
+	CSI_MIPI_DI0_MASK = 0x000000FFL,
+	CSI_MIPI_DI0_SHIFT = 0,
+	CSI_MIPI_DI1_MASK = 0x0000FF00L,
+	CSI_MIPI_DI1_SHIFT = 8,
+	CSI_MIPI_DI2_MASK = 0x00FF0000L,
+	CSI_MIPI_DI2_SHIFT = 16,
+	CSI_MIPI_DI3_MASK = 0xFF000000L,
+	CSI_MIPI_DI3_SHIFT = 24,
+
+	CSI_MAX_RATIO_SKIP_ISP_MASK = 0x00070000L,
+	CSI_MAX_RATIO_SKIP_ISP_SHIFT = 16,
+	CSI_SKIP_ISP_MASK = 0x00F80000L,
+	CSI_SKIP_ISP_SHIFT = 19,
+	CSI_MAX_RATIO_SKIP_SMFC_MASK = 0x00000007L,
+	CSI_MAX_RATIO_SKIP_SMFC_SHIFT = 0,
+	CSI_SKIP_SMFC_MASK = 0x000000F8L,
+	CSI_SKIP_SMFC_SHIFT = 3,
+	CSI_ID_2_SKIP_MASK = 0x00000300L,
+	CSI_ID_2_SKIP_SHIFT = 8,
+
+	CSI_COLOR_FIRST_ROW_MASK = 0x00000002L,
+	CSI_COLOR_FIRST_COMP_MASK = 0x00000001L,
+
+	SMFC_MAP_CH0_MASK = 0x00000007L,
+	SMFC_MAP_CH0_SHIFT = 0,
+	SMFC_MAP_CH1_MASK = 0x00000038L,
+	SMFC_MAP_CH1_SHIFT = 3,
+	SMFC_MAP_CH2_MASK = 0x000001C0L,
+	SMFC_MAP_CH2_SHIFT = 6,
+	SMFC_MAP_CH3_MASK = 0x00000E00L,
+	SMFC_MAP_CH3_SHIFT = 9,
+
+	SMFC_WM0_SET_MASK = 0x00000007L,
+	SMFC_WM0_SET_SHIFT = 0,
+	SMFC_WM1_SET_MASK = 0x000001C0L,
+	SMFC_WM1_SET_SHIFT = 6,
+	SMFC_WM2_SET_MASK = 0x00070000L,
+	SMFC_WM2_SET_SHIFT = 16,
+	SMFC_WM3_SET_MASK = 0x01C00000L,
+	SMFC_WM3_SET_SHIFT = 22,
+
+	SMFC_WM0_CLR_MASK = 0x00000038L,
+	SMFC_WM0_CLR_SHIFT = 3,
+	SMFC_WM1_CLR_MASK = 0x00000E00L,
+	SMFC_WM1_CLR_SHIFT = 9,
+	SMFC_WM2_CLR_MASK = 0x00380000L,
+	SMFC_WM2_CLR_SHIFT = 19,
+	SMFC_WM3_CLR_MASK = 0x0E000000L,
+	SMFC_WM3_CLR_SHIFT = 25,
+
+	SMFC_BS0_MASK = 0x0000000FL,
+	SMFC_BS0_SHIFT = 0,
+	SMFC_BS1_MASK = 0x000000F0L,
+	SMFC_BS1_SHIFT = 4,
+	SMFC_BS2_MASK = 0x00000F00L,
+	SMFC_BS2_SHIFT = 8,
+	SMFC_BS3_MASK = 0x0000F000L,
+	SMFC_BS3_SHIFT = 12,
+
+	PF_CONF_TYPE_MASK = 0x00000007,
+	PF_CONF_TYPE_SHIFT = 0,
+	PF_CONF_PAUSE_EN = 0x00000010,
+	PF_CONF_RESET = 0x00008000,
+	PF_CONF_PAUSE_ROW_MASK = 0x00FF0000,
+	PF_CONF_PAUSE_ROW_SHIFT = 16,
+
+	DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
+	DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
+
+	DI_GEN_DI_CLK_EXT = 0x100000,
+	DI_GEN_POLARITY_DISP_CLK = 0x00020000,
+	DI_GEN_POLARITY_1 = 0x00000001,
+	DI_GEN_POLARITY_2 = 0x00000002,
+	DI_GEN_POLARITY_3 = 0x00000004,
+	DI_GEN_POLARITY_4 = 0x00000008,
+	DI_GEN_POLARITY_5 = 0x00000010,
+	DI_GEN_POLARITY_6 = 0x00000020,
+	DI_GEN_POLARITY_7 = 0x00000040,
+	DI_GEN_POLARITY_8 = 0x00000080,
+
+	DI_POL_DRDY_DATA_POLARITY = 0x00000080,
+	DI_POL_DRDY_POLARITY_15 = 0x00000010,
+
+	DI_VSYNC_SEL_OFFSET = 13,
+
+	DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
+	DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
+	DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
+	DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
+	DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
+	DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
+
+	DC_UGDE_0_ODD_EN = 0x02000000,
+	DC_UGDE_0_ID_CODED_MASK = 0x00000007,
+	DC_UGDE_0_ID_CODED_OFFSET = 0,
+	DC_UGDE_0_EV_PRIORITY_MASK = 0x00000078,
+	DC_UGDE_0_EV_PRIORITY_OFFSET = 3,
+
+	DP_COM_CONF_FG_EN = 0x00000001,
+	DP_COM_CONF_GWSEL = 0x00000002,
+	DP_COM_CONF_GWAM = 0x00000004,
+	DP_COM_CONF_GWCKE = 0x00000008,
+	DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
+	DP_COM_CONF_CSC_DEF_OFFSET = 8,
+	DP_COM_CONF_CSC_DEF_FG = 0x00000300,
+	DP_COM_CONF_CSC_DEF_BG = 0x00000200,
+	DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
+	DP_COM_CONF_GAMMA_EN = 0x00001000,
+	DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
+
+	DI_SER_CONF_LLA_SER_ACCESS = 0x00000020,
+	DI_SER_CONF_SERIAL_CLK_POL = 0x00000010,
+	DI_SER_CONF_SERIAL_DATA_POL = 0x00000008,
+	DI_SER_CONF_SERIAL_RS_POL = 0x00000004,
+	DI_SER_CONF_SERIAL_CS_POL = 0x00000002,
+	DI_SER_CONF_WAIT4SERIAL = 0x00000001,
+
+	VDI_C_CH_420 = 0x00000000,
+	VDI_C_CH_422 = 0x00000002,
+	VDI_C_MOT_SEL_FULL = 0x00000008,
+	VDI_C_MOT_SEL_LOW = 0x00000004,
+	VDI_C_MOT_SEL_MED = 0x00000000,
+	VDI_C_BURST_SIZE1_4 = 0x00000030,
+	VDI_C_BURST_SIZE2_4 = 0x00000300,
+	VDI_C_BURST_SIZE3_4 = 0x00003000,
+	VDI_C_VWM1_SET_1 = 0x00000000,
+	VDI_C_VWM1_CLR_2 = 0x00080000,
+	VDI_C_VWM3_SET_1 = 0x00000000,
+	VDI_C_VWM3_CLR_2 = 0x02000000,
+	VDI_C_TOP_FIELD_MAN_1 = 0x40000000,
+	VDI_C_TOP_FIELD_AUTO_1 = 0x80000000,
+};
+
+enum di_pins {
+	DI_PIN11 = 0,
+	DI_PIN12 = 1,
+	DI_PIN13 = 2,
+	DI_PIN14 = 3,
+	DI_PIN15 = 4,
+	DI_PIN16 = 5,
+	DI_PIN17 = 6,
+	DI_PIN_CS = 7,
+
+	DI_PIN_SER_CLK = 0,
+	DI_PIN_SER_RS = 1,
+};
+
+enum di_sync_wave {
+	DI_SYNC_NONE = -1,
+	DI_SYNC_CLK = 0,
+	DI_SYNC_INT_HSYNC = 1,
+	DI_SYNC_HSYNC = 2,
+	DI_SYNC_VSYNC = 3,
+	DI_SYNC_DE = 5,
+};
+
+/* DC template opcodes */
+#define WROD(lf)		(0x18 | (lf << 1))
+#define WRG	        	(0x01)
+
+#endif
diff --git a/drivers/mxc/vpu/Kconfig b/drivers/mxc/vpu/Kconfig
new file mode 100644
index 00000000000..dada2040e2a
--- /dev/null
+++ b/drivers/mxc/vpu/Kconfig
@@ -0,0 +1,22 @@
+#
+# Codec configuration
+#
+
+menu "MXC VPU(Video Processing Unit) support"
+
+config MXC_VPU
+	  tristate "Support for MXC VPU(Video Processing Unit)"
+	  depends on (ARCH_MX3 || ARCH_MX27 || ARCH_MX37 || ARCH_MX5 || ARCH_MX6)
+	  default y
+	---help---
+	  The VPU codec device provides codec function for H.264/MPEG4/H.263,
+	  as well as MPEG2/VC-1/DivX on some platforms.
+
+config MXC_VPU_DEBUG
+	bool "MXC VPU debugging"
+	depends on MXC_VPU != n
+	help
+	  This is an option for the developers; most people should
+	  say N here.  This enables MXC VPU driver debugging.
+
+endmenu
diff --git a/drivers/mxc/vpu/Makefile b/drivers/mxc/vpu/Makefile
new file mode 100644
index 00000000000..1a821f4921c
--- /dev/null
+++ b/drivers/mxc/vpu/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the VPU drivers.
+#
+
+obj-$(CONFIG_MXC_VPU)                  += mxc_vpu.o
+
+ifeq ($(CONFIG_MXC_VPU_DEBUG),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/mxc/vpu/mxc_vpu.c b/drivers/mxc/vpu/mxc_vpu.c
new file mode 100644
index 00000000000..7bfe9bc8d37
--- /dev/null
+++ b/drivers/mxc/vpu/mxc_vpu.c
@@ -0,0 +1,895 @@
+/*
+ * Copyright 2006-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_vpu.c
+ *
+ * @brief VPU system initialization and file operation implementation
+ *
+ * @ingroup VPU
+ */
+
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/stat.h>
+#include <linux/platform_device.h>
+#include <linux/kdev_t.h>
+#include <linux/dma-mapping.h>
+#include <linux/wait.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/fsl_devices.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/sched.h>
+#include <linux/vmalloc.h>
+#include <asm/sizes.h>
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/iram.h>
+
+#include <mach/mxc_vpu.h>
+
+struct vpu_priv {
+	struct fasync_struct *async_queue;
+	struct work_struct work;
+	struct workqueue_struct *workqueue;
+};
+
+/* To track the allocated memory buffer */
+typedef struct memalloc_record {
+	struct list_head list;
+	struct vpu_mem_desc mem;
+} memalloc_record;
+
+struct iram_setting {
+	u32 start;
+	u32 end;
+};
+
+static DEFINE_SPINLOCK(vpu_lock);
+static LIST_HEAD(head);
+
+static int vpu_major;
+static int vpu_clk_usercount;
+static struct class *vpu_class;
+static struct vpu_priv vpu_data;
+static u8 open_count;
+static struct clk *vpu_clk;
+static struct vpu_mem_desc bitwork_mem = { 0 };
+static struct vpu_mem_desc pic_para_mem = { 0 };
+static struct vpu_mem_desc user_data_mem = { 0 };
+static struct vpu_mem_desc share_mem = { 0 };
+static struct vpu_mem_desc vshare_mem = { 0 };
+
+static void __iomem *vpu_base;
+static int vpu_ipi_irq;
+static u32 phy_vpu_base_addr;
+static struct mxc_vpu_platform_data *vpu_plat;
+
+/* IRAM setting */
+static struct iram_setting iram;
+
+/* implement the blocking ioctl */
+static int codec_done;
+static wait_queue_head_t vpu_queue;
+
+static u32 workctrl_regsave[6];
+static u32 rd_ptr_regsave[4];
+static u32 wr_ptr_regsave[4];
+static u32 dis_flag_regsave[4];
+
+#ifdef CONFIG_SOC_IMX6Q
+#define MXC_VPU_HAS_JPU
+#endif
+
+#ifdef MXC_VPU_HAS_JPU
+static int vpu_jpu_irq;
+#endif
+
+#define	READ_REG(x)		__raw_readl(vpu_base + x)
+#define	WRITE_REG(val, x)	__raw_writel(val, vpu_base + x)
+#define	SAVE_WORK_REGS	do {					\
+	int i;							\
+	for (i = 0; i < ARRAY_SIZE(workctrl_regsave)/2; i++)	\
+		workctrl_regsave[i] = READ_REG(BIT_WORK_CTRL_BUF_REG(i));\
+} while (0)
+#define	RESTORE_WORK_REGS	do {				\
+	int i;							\
+	for (i = 0; i < ARRAY_SIZE(workctrl_regsave)/2; i++)	\
+		WRITE_REG(workctrl_regsave[i], BIT_WORK_CTRL_BUF_REG(i));\
+} while (0)
+#define	SAVE_CTRL_REGS	do {					\
+	int i;							\
+	for (i = ARRAY_SIZE(workctrl_regsave)/2;		\
+			i < ARRAY_SIZE(workctrl_regsave); i++)		\
+		workctrl_regsave[i] = READ_REG(BIT_WORK_CTRL_BUF_REG(i));\
+} while (0)
+#define	RESTORE_CTRL_REGS	do {				\
+	int i;							\
+	for (i = ARRAY_SIZE(workctrl_regsave)/2;		\
+			i < ARRAY_SIZE(workctrl_regsave); i++)		\
+		WRITE_REG(workctrl_regsave[i], BIT_WORK_CTRL_BUF_REG(i));\
+} while (0)
+#define	SAVE_RDWR_PTR_REGS	do {					\
+	int i;								\
+	for (i = 0; i < ARRAY_SIZE(rd_ptr_regsave); i++)		\
+		rd_ptr_regsave[i] = READ_REG(BIT_RD_PTR_REG(i));	\
+	for (i = 0; i < ARRAY_SIZE(wr_ptr_regsave); i++)		\
+		wr_ptr_regsave[i] = READ_REG(BIT_WR_PTR_REG(i));	\
+} while (0)
+#define	RESTORE_RDWR_PTR_REGS	do {					\
+	int i;								\
+	for (i = 0; i < ARRAY_SIZE(rd_ptr_regsave); i++)		\
+		WRITE_REG(rd_ptr_regsave[i], BIT_RD_PTR_REG(i));	\
+	for (i = 0; i < ARRAY_SIZE(wr_ptr_regsave); i++)		\
+		WRITE_REG(wr_ptr_regsave[i], BIT_WR_PTR_REG(i));	\
+} while (0)
+#define	SAVE_DIS_FLAG_REGS	do {					\
+	int i;								\
+	for (i = 0; i < ARRAY_SIZE(dis_flag_regsave); i++)		\
+		dis_flag_regsave[i] = READ_REG(BIT_FRM_DIS_FLG_REG(i));	\
+} while (0)
+#define	RESTORE_DIS_FLAG_REGS	do {					\
+	int i;								\
+	for (i = 0; i < ARRAY_SIZE(dis_flag_regsave); i++)		\
+		WRITE_REG(dis_flag_regsave[i], BIT_FRM_DIS_FLG_REG(i));	\
+} while (0)
+
+/*!
+ * Private function to alloc dma buffer
+ * @return status  0 success.
+ */
+static int vpu_alloc_dma_buffer(struct vpu_mem_desc *mem)
+{
+	mem->cpu_addr = (unsigned long)
+	    dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size),
+			       (dma_addr_t *) (&mem->phy_addr),
+			       GFP_DMA | GFP_KERNEL);
+	pr_debug("[ALLOC] mem alloc cpu_addr = 0x%x\n", mem->cpu_addr);
+	if ((void *)(mem->cpu_addr) == NULL) {
+		printk(KERN_ERR "Physical memory allocation error!\n");
+		return -1;
+	}
+	return 0;
+}
+
+/*!
+ * Private function to free dma buffer
+ */
+static void vpu_free_dma_buffer(struct vpu_mem_desc *mem)
+{
+	if (mem->cpu_addr != 0) {
+		dma_free_coherent(0, PAGE_ALIGN(mem->size),
+				  (void *)mem->cpu_addr, mem->phy_addr);
+	}
+}
+
+/*!
+ * Private function to free buffers
+ * @return status  0 success.
+ */
+static int vpu_free_buffers(void)
+{
+	struct memalloc_record *rec, *n;
+	struct vpu_mem_desc mem;
+
+	list_for_each_entry_safe(rec, n, &head, list) {
+		mem = rec->mem;
+		if (mem.cpu_addr != 0) {
+			vpu_free_dma_buffer(&mem);
+			pr_debug("[FREE] freed paddr=0x%08X\n", mem.phy_addr);
+			/* delete from list */
+			list_del(&rec->list);
+			kfree(rec);
+		}
+	}
+
+	return 0;
+}
+
+static inline void vpu_worker_callback(struct work_struct *w)
+{
+	struct vpu_priv *dev = container_of(w, struct vpu_priv,
+				work);
+
+	if (dev->async_queue)
+		kill_fasync(&dev->async_queue, SIGIO, POLL_IN);
+
+	codec_done = 1;
+	wake_up_interruptible(&vpu_queue);
+
+	/*
+	 * Clock is gated on when dec/enc started, gate it off when
+	 * interrupt is received.
+	 */
+	clk_disable(vpu_clk);
+}
+
+/*!
+ * @brief vpu interrupt handler
+ */
+static irqreturn_t vpu_ipi_irq_handler(int irq, void *dev_id)
+{
+	struct vpu_priv *dev = dev_id;
+
+	READ_REG(BIT_INT_STATUS);
+	WRITE_REG(0x1, BIT_INT_CLEAR);
+
+	queue_work(dev->workqueue, &dev->work);
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * @brief vpu jpu interrupt handler
+ */
+#ifdef MXC_VPU_HAS_JPU
+static irqreturn_t vpu_jpu_irq_handler(int irq, void *dev_id)
+{
+	struct vpu_priv *dev = dev_id;
+
+	WRITE_REG(0, MJPEG_PIC_STATUS_REG);
+
+	queue_work(dev->workqueue, &dev->work);
+
+	return IRQ_HANDLED;
+}
+#endif
+
+/*!
+ * @brief open function for vpu file operation
+ *
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_open(struct inode *inode, struct file *filp)
+{
+	spin_lock(&vpu_lock);
+	open_count++;
+	filp->private_data = (void *)(&vpu_data);
+	spin_unlock(&vpu_lock);
+	return 0;
+}
+
+/*!
+ * @brief IO ctrl function for vpu file operation
+ * @param cmd IO ctrl command
+ * @return  0 on success or negative error code on error
+ */
+static long vpu_ioctl(struct file *filp, u_int cmd,
+		     u_long arg)
+{
+	int ret = 0;
+
+	switch (cmd) {
+	case VPU_IOC_PHYMEM_ALLOC:
+		{
+			struct memalloc_record *rec;
+
+			rec = kzalloc(sizeof(*rec), GFP_KERNEL);
+			if (!rec)
+				return -ENOMEM;
+
+			ret = copy_from_user(&(rec->mem),
+					     (struct vpu_mem_desc *)arg,
+					     sizeof(struct vpu_mem_desc));
+			if (ret) {
+				kfree(rec);
+				return -EFAULT;
+			}
+
+			pr_debug("[ALLOC] mem alloc size = 0x%x\n",
+				 rec->mem.size);
+
+			ret = vpu_alloc_dma_buffer(&(rec->mem));
+			if (ret == -1) {
+				kfree(rec);
+				printk(KERN_ERR
+				       "Physical memory allocation error!\n");
+				break;
+			}
+			ret = copy_to_user((void __user *)arg, &(rec->mem),
+					   sizeof(struct vpu_mem_desc));
+			if (ret) {
+				kfree(rec);
+				ret = -EFAULT;
+				break;
+			}
+
+			spin_lock(&vpu_lock);
+			list_add(&rec->list, &head);
+			spin_unlock(&vpu_lock);
+
+			break;
+		}
+	case VPU_IOC_PHYMEM_FREE:
+		{
+			struct memalloc_record *rec, *n;
+			struct vpu_mem_desc vpu_mem;
+
+			ret = copy_from_user(&vpu_mem,
+					     (struct vpu_mem_desc *)arg,
+					     sizeof(struct vpu_mem_desc));
+			if (ret)
+				return -EACCES;
+
+			pr_debug("[FREE] mem freed cpu_addr = 0x%x\n",
+				 vpu_mem.cpu_addr);
+			if ((void *)vpu_mem.cpu_addr != NULL) {
+				vpu_free_dma_buffer(&vpu_mem);
+			}
+
+			spin_lock(&vpu_lock);
+			list_for_each_entry_safe(rec, n, &head, list) {
+				if (rec->mem.cpu_addr == vpu_mem.cpu_addr) {
+					/* delete from list */
+					list_del(&rec->list);
+					kfree(rec);
+					break;
+				}
+			}
+			spin_unlock(&vpu_lock);
+
+			break;
+		}
+	case VPU_IOC_WAIT4INT:
+		{
+			u_long timeout = (u_long) arg;
+			if (!wait_event_interruptible_timeout
+			    (vpu_queue, codec_done != 0,
+			     msecs_to_jiffies(timeout))) {
+				printk(KERN_WARNING "VPU blocking: timeout.\n");
+				ret = -ETIME;
+			} else if (signal_pending(current)) {
+				printk(KERN_WARNING
+				       "VPU interrupt received.\n");
+				ret = -ERESTARTSYS;
+			} else
+				codec_done = 0;
+			break;
+		}
+	case VPU_IOC_IRAM_SETTING:
+		{
+			ret = copy_to_user((void __user *)arg, &iram,
+					   sizeof(struct iram_setting));
+			if (ret)
+				ret = -EFAULT;
+
+			break;
+		}
+	case VPU_IOC_CLKGATE_SETTING:
+		{
+			u32 clkgate_en;
+
+			if (get_user(clkgate_en, (u32 __user *) arg))
+				return -EFAULT;
+
+			if (clkgate_en) {
+				clk_enable(vpu_clk);
+			} else {
+				clk_disable(vpu_clk);
+			}
+
+			break;
+		}
+	case VPU_IOC_GET_SHARE_MEM:
+		{
+			spin_lock(&vpu_lock);
+			if (share_mem.cpu_addr != 0) {
+				ret = copy_to_user((void __user *)arg,
+						   &share_mem,
+						   sizeof(struct vpu_mem_desc));
+				spin_unlock(&vpu_lock);
+				break;
+			} else {
+				if (copy_from_user(&share_mem,
+						   (struct vpu_mem_desc *)arg,
+						 sizeof(struct vpu_mem_desc))) {
+					spin_unlock(&vpu_lock);
+					return -EFAULT;
+				}
+				if (vpu_alloc_dma_buffer(&share_mem) == -1)
+					ret = -EFAULT;
+				else {
+					if (copy_to_user((void __user *)arg,
+							 &share_mem,
+							 sizeof(struct
+								vpu_mem_desc)))
+						ret = -EFAULT;
+				}
+			}
+			spin_unlock(&vpu_lock);
+			break;
+		}
+	case VPU_IOC_REQ_VSHARE_MEM:
+		{
+			spin_lock(&vpu_lock);
+			if (vshare_mem.cpu_addr != 0) {
+				ret = copy_to_user((void __user *)arg,
+						   &vshare_mem,
+						   sizeof(struct vpu_mem_desc));
+				spin_unlock(&vpu_lock);
+				break;
+			} else {
+				if (copy_from_user(&vshare_mem,
+						   (struct vpu_mem_desc *)arg,
+						   sizeof(struct
+							  vpu_mem_desc))) {
+					spin_unlock(&vpu_lock);
+					return -EFAULT;
+				}
+				/* vmalloc shared memory if not allocated */
+				if (!vshare_mem.cpu_addr)
+					vshare_mem.cpu_addr =
+					    (unsigned long)
+					    vmalloc_user(vshare_mem.size);
+				if (copy_to_user
+				     ((void __user *)arg, &vshare_mem,
+				     sizeof(struct vpu_mem_desc)))
+					ret = -EFAULT;
+			}
+			spin_unlock(&vpu_lock);
+			break;
+		}
+	case VPU_IOC_GET_WORK_ADDR:
+		{
+			if (bitwork_mem.cpu_addr != 0) {
+				ret =
+				    copy_to_user((void __user *)arg,
+						 &bitwork_mem,
+						 sizeof(struct vpu_mem_desc));
+				break;
+			} else {
+				if (copy_from_user(&bitwork_mem,
+						   (struct vpu_mem_desc *)arg,
+						   sizeof(struct vpu_mem_desc)))
+					return -EFAULT;
+
+				if (vpu_alloc_dma_buffer(&bitwork_mem) == -1)
+					ret = -EFAULT;
+				else if (copy_to_user((void __user *)arg,
+						      &bitwork_mem,
+						      sizeof(struct
+							     vpu_mem_desc)))
+					ret = -EFAULT;
+			}
+			break;
+		}
+	case VPU_IOC_SYS_SW_RESET:
+		{
+			if (vpu_plat->reset)
+				vpu_plat->reset();
+
+			break;
+		}
+	case VPU_IOC_REG_DUMP:
+		break;
+	case VPU_IOC_PHYMEM_DUMP:
+		break;
+	default:
+		{
+			printk(KERN_ERR "No such IOCTL, cmd is %d\n", cmd);
+			break;
+		}
+	}
+	return ret;
+}
+
+/*!
+ * @brief Release function for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_release(struct inode *inode, struct file *filp)
+{
+	spin_lock(&vpu_lock);
+	if (open_count > 0 && !(--open_count)) {
+		vpu_free_buffers();
+
+		/* Free shared memory when vpu device is idle */
+		vpu_free_dma_buffer(&share_mem);
+		share_mem.cpu_addr = 0;
+		vfree((void *)vshare_mem.cpu_addr);
+		vshare_mem.cpu_addr = 0;
+	}
+	spin_unlock(&vpu_lock);
+
+	return 0;
+}
+
+/*!
+ * @brief fasync function for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_fasync(int fd, struct file *filp, int mode)
+{
+	struct vpu_priv *dev = (struct vpu_priv *)filp->private_data;
+	return fasync_helper(fd, filp, mode, &dev->async_queue);
+}
+
+/*!
+ * @brief memory map function of harware registers for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_map_hwregs(struct file *fp, struct vm_area_struct *vm)
+{
+	unsigned long pfn;
+
+	vm->vm_flags |= VM_IO | VM_RESERVED;
+	vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
+	pfn = phy_vpu_base_addr >> PAGE_SHIFT;
+	pr_debug("size=0x%x,  page no.=0x%x\n",
+		 (int)(vm->vm_end - vm->vm_start), (int)pfn);
+	return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end - vm->vm_start,
+			       vm->vm_page_prot) ? -EAGAIN : 0;
+}
+
+/*!
+ * @brief memory map function of memory for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_map_dma_mem(struct file *fp, struct vm_area_struct *vm)
+{
+	int request_size;
+	request_size = vm->vm_end - vm->vm_start;
+
+	pr_debug(" start=0x%x, pgoff=0x%x, size=0x%x\n",
+		 (unsigned int)(vm->vm_start), (unsigned int)(vm->vm_pgoff),
+		 request_size);
+
+	vm->vm_flags |= VM_IO | VM_RESERVED;
+	vm->vm_page_prot = pgprot_writecombine(vm->vm_page_prot);
+
+	return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff,
+			       request_size, vm->vm_page_prot) ? -EAGAIN : 0;
+
+}
+
+/* !
+ * @brief memory map function of vmalloced share memory
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_map_vshare_mem(struct file *fp, struct vm_area_struct *vm)
+{
+	int ret = -EINVAL;
+
+	spin_lock(&vpu_lock);
+	ret = remap_vmalloc_range(vm, (void *)(vm->vm_pgoff << PAGE_SHIFT), 0);
+	vm->vm_flags |= VM_IO;
+	spin_unlock(&vpu_lock);
+
+	return ret;
+}
+/*!
+ * @brief memory map interface for vpu file operation
+ * @return  0 on success or negative error code on error
+ */
+static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
+{
+	unsigned long offset;
+
+	offset = vshare_mem.cpu_addr >> PAGE_SHIFT;
+
+	if (vm->vm_pgoff && (vm->vm_pgoff == offset))
+		return vpu_map_vshare_mem(fp, vm);
+	else if (vm->vm_pgoff)
+		return vpu_map_dma_mem(fp, vm);
+	else
+		return vpu_map_hwregs(fp, vm);
+}
+
+struct file_operations vpu_fops = {
+	.owner = THIS_MODULE,
+	.open = vpu_open,
+	.unlocked_ioctl = vpu_ioctl,
+	.release = vpu_release,
+	.fasync = vpu_fasync,
+	.mmap = vpu_mmap,
+};
+
+/*!
+ * This function is called by the driver framework to initialize the vpu device.
+ * @param   dev The device structure for the vpu passed in by the framework.
+ * @return   0 on success or negative error code on error
+ */
+static int vpu_dev_probe(struct platform_device *pdev)
+{
+	int err = 0;
+	struct device *temp_class;
+	struct resource *res;
+	unsigned long addr = 0;
+
+	vpu_plat = pdev->dev.platform_data;
+
+	if (vpu_plat && vpu_plat->iram_enable && vpu_plat->iram_size)
+		iram_alloc(vpu_plat->iram_size, &addr);
+	if (addr == 0)
+		iram.start = iram.end = 0;
+	else {
+		iram.start = addr;
+		iram.end = addr +  vpu_plat->iram_size - 1;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		printk(KERN_ERR "vpu: unable to get vpu base addr\n");
+		return -ENODEV;
+	}
+	phy_vpu_base_addr = res->start;
+	vpu_base = ioremap(res->start, res->end - res->start);
+
+	vpu_major = register_chrdev(vpu_major, "mxc_vpu", &vpu_fops);
+	if (vpu_major < 0) {
+		printk(KERN_ERR "vpu: unable to get a major for VPU\n");
+		err = -EBUSY;
+		goto error;
+	}
+
+	vpu_class = class_create(THIS_MODULE, "mxc_vpu");
+	if (IS_ERR(vpu_class)) {
+		err = PTR_ERR(vpu_class);
+		goto err_out_chrdev;
+	}
+
+	temp_class = device_create(vpu_class, NULL, MKDEV(vpu_major, 0),
+				   NULL, "mxc_vpu");
+	if (IS_ERR(temp_class)) {
+		err = PTR_ERR(temp_class);
+		goto err_out_class;
+	}
+
+	vpu_clk = clk_get(&pdev->dev, "vpu_clk");
+	if (IS_ERR(vpu_clk)) {
+		err = -ENOENT;
+		goto err_out_class;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		printk(KERN_ERR "vpu: unable to get vpu interrupt\n");
+		err = -ENXIO;
+		goto err_out_class;
+	}
+	vpu_ipi_irq = res->start;
+
+	err = request_irq(vpu_ipi_irq, vpu_ipi_irq_handler, 0, "VPU_CODEC_IRQ",
+			  (void *)(&vpu_data));
+	if (err)
+		goto err_out_class;
+
+#ifdef MXC_VPU_HAS_JPU
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+	if (!res) {
+		printk(KERN_ERR "vpu: unable to get vpu jpu interrupt\n");
+		err = -ENXIO;
+		free_irq(vpu_ipi_irq, &vpu_data);
+		goto err_out_class;
+	}
+	vpu_jpu_irq = res->start;
+	err = request_irq(vpu_jpu_irq, vpu_jpu_irq_handler, 0, "VPU_JPG_IRQ",
+			  (void *)(&vpu_data));
+	if (err) {
+		free_irq(vpu_ipi_irq, &vpu_data);
+		goto err_out_class;
+	}
+#endif
+
+	vpu_data.workqueue = create_workqueue("vpu_wq");
+	INIT_WORK(&vpu_data.work, vpu_worker_callback);
+	printk(KERN_INFO "VPU initialized\n");
+	goto out;
+
+      err_out_class:
+	device_destroy(vpu_class, MKDEV(vpu_major, 0));
+	class_destroy(vpu_class);
+      err_out_chrdev:
+	unregister_chrdev(vpu_major, "mxc_vpu");
+      error:
+	iounmap(vpu_base);
+      out:
+	return err;
+}
+
+static int vpu_dev_remove(struct platform_device *pdev)
+{
+	free_irq(vpu_ipi_irq, &vpu_data);
+#ifdef MXC_VPU_HAS_JPU
+	free_irq(vpu_jpu_irq, &vpu_data);
+#endif
+	cancel_work_sync(&vpu_data.work);
+	flush_workqueue(vpu_data.workqueue);
+	destroy_workqueue(vpu_data.workqueue);
+
+	iounmap(vpu_base);
+	if (vpu_plat && vpu_plat->iram_enable && vpu_plat->iram_size)
+		iram_free(iram.start,  vpu_plat->iram_size);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	int i;
+	unsigned long timeout;
+
+	/* Wait for vpu go to idle state, suspect vpu cannot be changed
+	   to idle state after about 1 sec */
+	if (open_count > 0) {
+		timeout = jiffies + HZ;
+		clk_enable(vpu_clk);
+		while (READ_REG(BIT_BUSY_FLAG)) {
+			msleep(1);
+			if (time_after(jiffies, timeout))
+				goto out;
+		}
+		clk_disable(vpu_clk);
+	}
+
+	/* Make sure clock is disabled before suspend */
+	vpu_clk_usercount = clk_get_usecount(vpu_clk);
+	for (i = 0; i < vpu_clk_usercount; i++)
+		clk_disable(vpu_clk);
+
+	if (cpu_is_mx51()) {
+		clk_enable(vpu_clk);
+		if (bitwork_mem.cpu_addr != 0) {
+			SAVE_WORK_REGS;
+			SAVE_CTRL_REGS;
+			SAVE_RDWR_PTR_REGS;
+			SAVE_DIS_FLAG_REGS;
+
+			WRITE_REG(0x1, BIT_BUSY_FLAG);
+			WRITE_REG(VPU_SLEEP_REG_VALUE, BIT_RUN_COMMAND);
+			while (READ_REG(BIT_BUSY_FLAG))
+				;
+		}
+		clk_disable(vpu_clk);
+	}
+
+	if (cpu_is_mx51() && vpu_plat->pg)
+		vpu_plat->pg(1);
+
+	return 0;
+
+out:
+	clk_disable(vpu_clk);
+	return -EAGAIN;
+
+}
+
+static int vpu_resume(struct platform_device *pdev)
+{
+	int i;
+
+	if (!cpu_is_mx51())
+		goto recover_clk;
+
+	if (vpu_plat->pg)
+		vpu_plat->pg(0);
+
+	clk_enable(vpu_clk);
+	if (bitwork_mem.cpu_addr != 0) {
+		u32 *p = (u32 *) bitwork_mem.cpu_addr;
+		u32 data;
+		u16 data_hi;
+		u16 data_lo;
+
+		RESTORE_WORK_REGS;
+
+		WRITE_REG(0x0, BIT_RESET_CTRL);
+		WRITE_REG(0x0, BIT_CODE_RUN);
+
+		/*
+		 * Re-load boot code, from the codebuffer in external RAM.
+		 * Thankfully, we only need 4096 bytes, same for all platforms.
+		 */
+		for (i = 0; i < 2048; i += 4) {
+			data = p[(i / 2) + 1];
+			data_hi = (data >> 16) & 0xFFFF;
+			data_lo = data & 0xFFFF;
+			WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN);
+			WRITE_REG(((i + 1) << 16) | data_lo,
+				  BIT_CODE_DOWN);
+
+			data = p[i / 2];
+			data_hi = (data >> 16) & 0xFFFF;
+			data_lo = data & 0xFFFF;
+			WRITE_REG(((i + 2) << 16) | data_hi,
+				  BIT_CODE_DOWN);
+			WRITE_REG(((i + 3) << 16) | data_lo,
+				  BIT_CODE_DOWN);
+		}
+
+		RESTORE_CTRL_REGS;
+
+		WRITE_REG(BITVAL_PIC_RUN, BIT_INT_ENABLE);
+
+		WRITE_REG(0x1, BIT_BUSY_FLAG);
+		WRITE_REG(0x1, BIT_CODE_RUN);
+		while (READ_REG(BIT_BUSY_FLAG))
+			;
+
+		RESTORE_RDWR_PTR_REGS;
+		RESTORE_DIS_FLAG_REGS;
+
+		WRITE_REG(0x1, BIT_BUSY_FLAG);
+		WRITE_REG(VPU_WAKE_REG_VALUE, BIT_RUN_COMMAND);
+		while (READ_REG(BIT_BUSY_FLAG))
+			;
+	}
+	clk_disable(vpu_clk);
+
+recover_clk:
+	/* Recover vpu clock */
+	for (i = 0; i < vpu_clk_usercount; i++)
+		clk_enable(vpu_clk);
+
+	return 0;
+}
+#else
+#define	vpu_suspend	NULL
+#define	vpu_resume	NULL
+#endif				/* !CONFIG_PM */
+
+/*! Driver definition
+ *
+ */
+static struct platform_driver mxcvpu_driver = {
+	.driver = {
+		   .name = "mxc_vpu",
+		   },
+	.probe = vpu_dev_probe,
+	.remove = vpu_dev_remove,
+	.suspend = vpu_suspend,
+	.resume = vpu_resume,
+};
+
+static int __init vpu_init(void)
+{
+	int ret = platform_driver_register(&mxcvpu_driver);
+
+	init_waitqueue_head(&vpu_queue);
+
+	return ret;
+}
+
+static void __exit vpu_exit(void)
+{
+	if (vpu_major > 0) {
+		device_destroy(vpu_class, MKDEV(vpu_major, 0));
+		class_destroy(vpu_class);
+		unregister_chrdev(vpu_major, "mxc_vpu");
+		vpu_major = 0;
+	}
+
+	vpu_free_dma_buffer(&bitwork_mem);
+	vpu_free_dma_buffer(&pic_para_mem);
+	vpu_free_dma_buffer(&user_data_mem);
+
+	clk_put(vpu_clk);
+
+	platform_driver_unregister(&mxcvpu_driver);
+	return;
+}
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Linux VPU driver for Freescale i.MX/MXC");
+MODULE_LICENSE("GPL");
+
+module_init(vpu_init);
+module_exit(vpu_exit);
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index c136230d50b..9a54af1ed52 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -255,7 +255,7 @@ struct fec_enet_private {
 #define FEC_MMFR_TA		(2 << 16)
 #define FEC_MMFR_DATA(v)	(v & 0xffff)
 
-#define FEC_MII_TIMEOUT		1000 /* us */
+#define FEC_MII_TIMEOUT		50000 /* us */
 
 /* Transmitter timeout */
 #define TX_TIMEOUT (2 * HZ)
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 9f88641e67f..6b69ef75822 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -250,4 +250,11 @@ config CHARGER_MAX8998
 	  Say Y to enable support for the battery charger control sysfs and
 	  platform data of MAX8998/LP3974 PMICs.
 
+config BATTERY_DA9052
+	tristate "Dialog DA9052 Battery"
+	depends on PMIC_DIALOG
+	help
+	  Say Y here to enable support for batteries charger integrated into
+	  DA9052 PMIC.
+
 endif # POWER_SUPPLY
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index b4af13dd8b6..91ecaae0299 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_CHARGER_TWL4030)	+= twl4030_charger.o
 obj-$(CONFIG_CHARGER_GPIO)	+= gpio-charger.o
 obj-$(CONFIG_CHARGER_MAX8997)	+= max8997_charger.o
 obj-$(CONFIG_CHARGER_MAX8998)	+= max8998_charger.o
+obj-$(CONFIG_BATTERY_DA9052)	+= da9052-battery.o
diff --git a/drivers/power/da9052-battery.c b/drivers/power/da9052-battery.c
new file mode 100644
index 00000000000..210e8edade4
--- /dev/null
+++ b/drivers/power/da9052-battery.c
@@ -0,0 +1,847 @@
+/*
+ * da9052-battery.c  --  Batttery Driver for Dialog DA9052
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * Author: Dialog Semiconductor Ltd <dchen@diasemi.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/uaccess.h>
+#include <linux/jiffies.h>
+#include <linux/power_supply.h>
+#include <linux/platform_device.h>
+#include <linux/freezer.h>
+
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/bat.h>
+#include <linux/mfd/da9052/adc.h>
+
+#define DA9052_BAT_DEVICE_NAME			"da9052-bat"
+
+static const char  __initdata banner[] = KERN_INFO \
+	"DA9052 BAT, (c) 2009 Dialog semiconductor Ltd.\n";
+
+static struct da9052_bat_hysteresis bat_hysteresis;
+static struct da9052_bat_event_registration event_status;
+
+
+static u16 array_hys_batvoltage[2];
+static u16 bat_volt_arr[3];
+static u8 hys_flag = FALSE;
+
+static int da9052_read(struct da9052 *da9052, u8 reg_address, u8 *reg_data)
+{
+	struct da9052_ssc_msg msg;
+	int ret;
+
+	msg.addr = reg_address;
+	msg.data = 0;
+
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret)
+		goto ssc_comm_err;
+	da9052_unlock(da9052);
+
+	*reg_data = msg.data;
+	return 0;
+ssc_comm_err:
+	da9052_unlock(da9052);
+	return ret;
+}
+
+static s32 da9052_adc_read_ich(struct da9052 *da9052, u16 *data)
+{
+	struct da9052_ssc_msg msg;
+	da9052_lock(da9052);
+	/* Read charging conversion register */
+	msg.addr = DA9052_ICHGAV_REG;
+	msg.data = 0;
+	if (da9052->read(da9052, &msg)) {
+		da9052_unlock(da9052);
+		return DA9052_SSC_FAIL;
+	}
+	da9052_unlock(da9052);
+
+	*data = (u16)msg.data;
+	DA9052_DEBUG("In function: %s, ICHGAV_REG value read (1)= 0x%X\n",
+		__func__, msg.data);
+	return SUCCESS;
+}
+
+
+static s32 da9052_adc_read_tbat(struct da9052 *da9052, u16 *data)
+{
+	s32 ret;
+	u8 reg_data;
+
+	ret = da9052_read(da9052, DA9052_TBATRES_REG, &reg_data);
+	if (ret)
+		return ret;
+	*data = (u16)reg_data;
+
+	DA9052_DEBUG("In function: %s, TBATRES_REG value read (1)= 0x%X\n",
+		__func__, msg.data);
+	return SUCCESS;
+}
+
+s32 da9052_adc_read_vbat(struct da9052 *da9052, u16 *data)
+{
+	s32 ret;
+
+	ret = da9052_manual_read(da9052, DA9052_ADC_VBAT);
+	DA9052_DEBUG("In function: %s, VBAT value read (1)= 0x%X\n",
+		__func__, temp);
+	if (ret == -EIO) {
+		*data = 0;
+		return ret;
+	} else {
+		*data = ret;
+		return 0;
+	}
+	return 0;
+}
+
+
+static u16 filter_sample(u16 *buffer)
+{
+	u8 count;
+	u16 tempvalue = 0;
+	u16 ret;
+
+	if (buffer == NULL)
+		return -EINVAL;
+
+	for (count = 0; count < DA9052_FILTER_SIZE; count++)
+		tempvalue = tempvalue + *(buffer + count);
+
+	ret = tempvalue/DA9052_FILTER_SIZE;
+	return ret;
+}
+
+static s32  da9052_bat_get_battery_temperature(struct da9052_charger_device
+	*chg_device, u16 *buffer)
+{
+
+	u8 count;
+	u16 filterqueue[DA9052_FILTER_SIZE];
+
+	/* Measure the battery temperature using ADC function.
+		Number of read equal to average filter size*/
+
+	for (count = 0; count < DA9052_FILTER_SIZE; count++)
+		if (da9052_adc_read_tbat(chg_device->da9052,
+					 &filterqueue[count]))
+			return -EIO;
+
+	/* Apply Average filter */
+	filterqueue[0] = filter_sample(filterqueue);
+
+	chg_device->bat_temp = filterqueue[0];
+	*buffer = chg_device->bat_temp;
+
+	return SUCCESS;
+}
+
+static s32  da9052_bat_get_chg_current(struct da9052_charger_device
+	*chg_device, u16 *buffer)
+{
+	if (chg_device->status == POWER_SUPPLY_STATUS_DISCHARGING)
+		return -EIO;
+
+		/* Measure the Charger current using ADC function */
+	if (da9052_adc_read_ich(chg_device->da9052, buffer))
+		return -EIO;
+
+	/* Convert the raw value in terms of mA */
+	chg_device->chg_current = ichg_reg_to_mA(*buffer);
+	*buffer = chg_device->chg_current;
+
+	return 0;
+}
+
+
+s32 da9052_bat_get_battery_voltage(struct da9052_charger_device *chg_device,
+				   u16 *buffer)
+{
+	u8 count;
+	u16 filterqueue[DA9052_FILTER_SIZE];
+
+	/* Measure the battery voltage using ADC function.
+		Number of read equal to average filter size*/
+	for (count = 0; count < DA9052_FILTER_SIZE; count++)
+		if (da9052_adc_read_vbat(chg_device->da9052,
+					 &filterqueue[count]))
+			return -EIO;
+
+	/* Apply average filter */
+	filterqueue[0] = filter_sample(filterqueue);
+
+	/* Convert battery voltage raw value in terms of mV */
+	chg_device->bat_voltage = volt_reg_to_mV(filterqueue[0]);
+	*buffer = chg_device->bat_voltage;
+	return 0;
+}
+
+static void da9052_bat_status_update(struct da9052_charger_device
+	*chg_device)
+{
+	struct da9052_ssc_msg msg;
+	u16 current_value = 0;
+	u16 buffer = 0;
+	u8 regvalue = 0;
+	u8 old_status = chg_device->status;
+
+	DA9052_DEBUG("FUNCTION = %s\n", __func__);
+
+	/* Read Status A register */
+	msg.addr = DA9052_STATUSA_REG;
+	msg.data = 0;
+	da9052_lock(chg_device->da9052);
+
+	if (chg_device->da9052->read(chg_device->da9052, &msg)) {
+		DA9052_DEBUG("%s : failed\n", __func__);
+		da9052_unlock(chg_device->da9052);
+		return;
+	}
+	regvalue = msg.data;
+
+	/* Read Status B register */
+	msg.addr = DA9052_STATUSB_REG;
+	msg.data = 0;
+	if (chg_device->da9052->read(chg_device->da9052, &msg)) {
+		DA9052_DEBUG("%s : failed\n", __func__);
+		da9052_unlock(chg_device->da9052);
+		return;
+	}
+	da9052_unlock(chg_device->da9052);
+
+	/* If DCINDET and DCINSEL are set then connected charger is
+	   WALL Charger unit */
+	if ((regvalue & DA9052_STATUSA_DCINSEL)
+				&& (regvalue & DA9052_STATUSA_DCINDET)) {
+
+		chg_device->charger_type = DA9052_WALL_CHARGER;
+	} else if ((regvalue & DA9052_STATUSA_VBUSSEL)
+				&& (regvalue & DA9052_STATUSA_VBUSDET)) {
+		/* If VBUS_DET and VBUSEL are set then connected charger is
+		   USB Type */
+		if (regvalue & DA9052_STATUSA_VDATDET) {
+			chg_device->charger_type = DA9052_USB_CHARGER;
+		} else {
+			/* Else it has to be USB Host charger */
+			chg_device->charger_type = DA9052_USB_HUB;
+		}
+	} else {
+	/* Battery is discharging since charging device is not present */
+		chg_device->charger_type = DA9052_NOCHARGER;
+		/* Eqv to DISCHARGING_WITHOUT_CHARGER state */
+		chg_device->status = POWER_SUPPLY_STATUS_DISCHARGING;
+	}
+
+
+	if (chg_device->charger_type != DA9052_NOCHARGER) {
+		/* if Charging end flag is set and Charging current is greater
+			than charging end limit then battery is charging */
+		if ((msg.data & DA9052_STATUSB_CHGEND) != 0)  {
+			if (da9052_bat_get_chg_current(chg_device,
+						       &current_value)) {
+				return;
+			}
+			if (current_value >= chg_device->chg_end_current) {
+				chg_device->status =
+					POWER_SUPPLY_STATUS_CHARGING;
+			} else {
+				/* Eqv to DISCHARGING_WITH_CHARGER state*/
+				chg_device->status =
+					POWER_SUPPLY_STATUS_NOT_CHARGING;
+			}
+		} else {
+		/* if Charging end flag is cleared then battery is charging */
+			chg_device->status = POWER_SUPPLY_STATUS_CHARGING;
+		}
+
+		if (POWER_SUPPLY_STATUS_CHARGING == chg_device->status) {
+			if (msg.data != DA9052_STATUSB_CHGPRE) {
+				/* Measure battery voltage. if battery
+				   voltage is greater than
+				   (VCHG_BAT - VCHG_DROP) then battery is in
+				   the termintation mode. */
+				if (da9052_bat_get_battery_voltage(
+					    chg_device, &buffer)) {
+					DA9052_DEBUG("%s : failed\n"
+						     , __func__);
+					return ;
+				}
+				if (buffer > (chg_device->bat_target_voltage -
+					chg_device->charger_voltage_drop) &&
+					(chg_device->cal_capacity >= 99)) {
+					chg_device->status =
+						POWER_SUPPLY_STATUS_FULL;
+				}
+			}
+		}
+	}
+
+	if (chg_device->illegal)
+		chg_device->health = POWER_SUPPLY_HEALTH_UNKNOWN;
+	else if (chg_device->cal_capacity < chg_device->bat_capacity_limit_low)
+		chg_device->health = POWER_SUPPLY_HEALTH_DEAD;
+	else
+		chg_device->health = POWER_SUPPLY_HEALTH_GOOD;
+
+	if (chg_device->status != old_status)
+		power_supply_changed(&chg_device->psy);
+
+	return;
+}
+
+static s32 da9052_bat_suspend_charging(struct da9052_charger_device *chg_device)
+{
+	struct da9052_ssc_msg msg;
+
+	if ((chg_device->status == POWER_SUPPLY_STATUS_DISCHARGING) ||
+		(chg_device->status == POWER_SUPPLY_STATUS_NOT_CHARGING))
+		return 0;
+
+	msg.addr = DA9052_INPUTCONT_REG;
+	msg.data = 0;
+	da9052_lock(chg_device->da9052);
+	/* Read Input condition register */
+	if (chg_device->da9052->read(chg_device->da9052, &msg)) {
+		da9052_unlock(chg_device->da9052);
+		return DA9052_SSC_FAIL;
+	}
+
+	/* set both Wall charger and USB charger suspend bit */
+	msg.data = set_bits(msg.data, DA9052_INPUTCONT_DCINSUSP);
+	msg.data = set_bits(msg.data, DA9052_INPUTCONT_VBUSSUSP);
+
+	/* Write to Input control register */
+	if (chg_device->da9052->write(chg_device->da9052, &msg)) {
+		da9052_unlock(chg_device->da9052);
+		DA9052_DEBUG("%s : failed\n", __func__);
+		return DA9052_SSC_FAIL;
+	}
+	da9052_unlock(chg_device->da9052);
+
+	DA9052_DEBUG("%s : Sucess\n", __func__);
+	return 0;
+}
+
+u32 interpolated(u32 vbat_lower, u32  vbat_upper, u32  level_lower,
+	u32  level_upper, u32 bat_voltage)
+{
+	s32 temp;
+	/*apply formula y= yk + (x - xk) * (yk+1 -yk)/(xk+1 -xk) */
+	temp = ((level_upper - level_lower) * 1000)/(vbat_upper - vbat_lower);
+	temp = level_lower + (((bat_voltage - vbat_lower) * temp)/1000);
+
+	return temp;
+}
+
+s32 capture_first_correct_vbat_sample(struct da9052_charger_device *chg_device,
+u16 *battery_voltage)
+{
+	static u8 count;
+	s32 ret = 0;
+	u32 temp_data = 0;
+
+	ret = da9052_bat_get_battery_voltage(chg_device,
+		&bat_volt_arr[count]);
+	if (ret)
+		return ret;
+	count++;
+
+	if (count < chg_device->vbat_first_valid_detect_iteration)
+		return FAILURE;
+	for (count = 0; count <
+		(chg_device->vbat_first_valid_detect_iteration - 1);
+		count++) {
+			temp_data = (bat_volt_arr[count] *
+			(chg_device->hysteresis_window_size))/100;
+		bat_hysteresis.upper_limit = bat_volt_arr[count] + temp_data;
+		bat_hysteresis.lower_limit = bat_volt_arr[count] - temp_data;
+
+		if ((bat_volt_arr[count + 1] < bat_hysteresis.upper_limit) &&
+			(bat_volt_arr[count + 1] >
+			bat_hysteresis.lower_limit)) {
+				*battery_voltage = (bat_volt_arr[count] +
+				bat_volt_arr[count+1]) / 2;
+				hys_flag = TRUE;
+			return 0;
+		}
+	}
+
+	for (count = 0; count <
+		(chg_device->vbat_first_valid_detect_iteration - 1);
+			count++)
+		bat_volt_arr[count] = bat_volt_arr[count + 1];
+
+	return FAILURE;
+}
+
+
+s32 check_hystersis(struct da9052_charger_device *chg_device, u16 *bat_voltage)
+{
+	u8 ret = 0;
+	u32 offset = 0;
+
+	/* Measure battery voltage using BAT internal function*/
+	if (hys_flag == FALSE) {
+		ret = capture_first_correct_vbat_sample
+			(chg_device, &array_hys_batvoltage[0]);
+		if (ret)
+			return ret;
+	}
+
+	ret = da9052_bat_get_battery_voltage
+		(chg_device, &array_hys_batvoltage[1]);
+	if (ret)
+		return ret;
+	*bat_voltage = array_hys_batvoltage[1];
+
+#if DA9052_BAT_FILTER_HYS
+	printk(KERN_CRIT "\nBAT_LOG: Previous Battery Voltage = %d mV\n",
+				array_hys_batvoltage[0]);
+	printk(KERN_CRIT "\nBAT_LOG:Battery Voltage Before Filter = %d mV\n",
+				array_hys_batvoltage[1]);
+#endif
+	/* Check if measured battery voltage value is within the hysteresis
+		window limit using measured battey votlage value */
+	if ((bat_hysteresis.upper_limit < *bat_voltage) ||
+			(bat_hysteresis.lower_limit > *bat_voltage)) {
+
+		bat_hysteresis.index++;
+		if (bat_hysteresis.index ==
+			chg_device->hysteresis_no_of_reading) {
+			/* Hysteresis Window is set to +- of
+			HYSTERESIS_WINDOW_SIZE percentage of current VBAT */
+			bat_hysteresis.index = 0;
+			offset = ((*bat_voltage) *
+				chg_device->hysteresis_window_size)/
+				100;
+			bat_hysteresis.upper_limit = (*bat_voltage) + offset;
+			bat_hysteresis.lower_limit = (*bat_voltage) - offset;
+		} else {
+#if DA9052_BAT_FILTER_HYS
+			printk(KERN_CRIT "CheckHystersis: Failed\n");
+#endif
+			return -EIO;
+		}
+	} else {
+		bat_hysteresis.index = 0;
+		offset = ((*bat_voltage) *
+			chg_device->hysteresis_window_size)/100;
+		bat_hysteresis.upper_limit = (*bat_voltage) + offset;
+		bat_hysteresis.lower_limit = (*bat_voltage) - offset;
+	}
+
+	/* Digital C Filter, formula Yn = k Yn-1 + (1-k) Xn */
+	*bat_voltage = ((chg_device->chg_hysteresis_const *
+		array_hys_batvoltage[0])/100) +
+		(((100 - chg_device->chg_hysteresis_const) *
+		array_hys_batvoltage[1])/100);
+
+	if ((chg_device->status == POWER_SUPPLY_STATUS_DISCHARGING) &&
+		(*bat_voltage > array_hys_batvoltage[0])) {
+			*bat_voltage = array_hys_batvoltage[0];
+	}
+
+	array_hys_batvoltage[0] = *bat_voltage;
+
+#if DA9052_BAT_FILTER_HYS
+	printk(KERN_CRIT "\nBAT_LOG:Battery Voltage After Filter = %d mV\n",\
+		*bat_voltage);
+
+#endif
+	return 0;
+}
+
+u8 select_temperature(u8 temp_index, u16 bat_temperature)
+{
+	u16 temp_temperature = 0;
+	temp_temperature = (temperature_lookup_ref[temp_index] +
+				temperature_lookup_ref[temp_index+1]) / 2;
+
+	if (bat_temperature >= temp_temperature) {
+		temp_index += 1;
+		return temp_index;
+	} else
+		return temp_index;
+}
+
+s32 da9052_bat_level_update(struct da9052_charger_device *chg_device)
+{
+	u16 bat_temperature;
+	u16 bat_voltage;
+	u32 vbat_lower, vbat_upper, level_upper, level_lower, level;
+	u8 access_index = 0;
+	u8 index = 0, ret;
+	u8 flag = FALSE;
+
+	ret = 0;
+	vbat_lower = 0;
+	vbat_upper = 0;
+	level_upper = 0;
+	level_lower = 0;
+
+	ret = check_hystersis(chg_device, &bat_voltage);
+	if (ret)
+		return ret;
+
+	ret = da9052_bat_get_battery_temperature(chg_device,
+		&bat_temperature);
+	if (ret)
+		return ret;
+
+	for (index = 0; index < (DA9052_NO_OF_LOOKUP_TABLE-1); index++) {
+		if (bat_temperature <= temperature_lookup_ref[0]) {
+			access_index = 0;
+			break;
+		} else if (bat_temperature >
+			temperature_lookup_ref[DA9052_NO_OF_LOOKUP_TABLE]){
+				access_index = DA9052_NO_OF_LOOKUP_TABLE - 1;
+			break;
+		} else if ((bat_temperature >= temperature_lookup_ref[index]) &&
+			(bat_temperature >= temperature_lookup_ref[index+1])) {
+			access_index = select_temperature(index,
+				bat_temperature);
+			break;
+		}
+	}
+	if (bat_voltage >= vbat_vs_capacity_look_up[access_index][0][0]) {
+		chg_device->cal_capacity = 100;
+		return 0;
+	}
+	if (bat_voltage <= vbat_vs_capacity_look_up[access_index]
+		[DA9052_LOOK_UP_TABLE_SIZE-1][0]){
+			chg_device->cal_capacity = 0;
+			return 0;
+	}
+	flag = FALSE;
+
+	for (index = 0; index < (DA9052_LOOK_UP_TABLE_SIZE-1); index++) {
+		if ((bat_voltage <=
+		vbat_vs_capacity_look_up[access_index][index][0]) &&
+		(bat_voltage >=
+		vbat_vs_capacity_look_up[access_index][index+1][0])) {
+			vbat_upper =
+			vbat_vs_capacity_look_up[access_index][index][0];
+			vbat_lower =
+			vbat_vs_capacity_look_up[access_index][index+1][0];
+			level_upper =
+			vbat_vs_capacity_look_up[access_index][index][1];
+			level_lower =
+			vbat_vs_capacity_look_up[access_index][index+1][1];
+			flag = TRUE;
+			break;
+		}
+	}
+	if (!flag)
+		return -EIO;
+
+	level = interpolated(vbat_lower, vbat_upper, level_lower,
+		level_upper, bat_voltage);
+	chg_device->cal_capacity = level;
+	DA9052_DEBUG(" TOTAl_BAT_CAPACITY : %d\n", chg_device->cal_capacity);
+	return 0;
+}
+
+void da9052_bat_tbat_handler(struct da9052_eh_nb *eh_data, unsigned int event)
+{
+	struct da9052_charger_device *chg_device =
+	container_of(eh_data, struct da9052_charger_device, tbat_eh_data);
+
+	chg_device->health = POWER_SUPPLY_HEALTH_OVERHEAT;
+
+}
+
+static s32 da9052_bat_register_event(struct da9052_charger_device *chg_device)
+{
+	s32 ret;
+
+	if (event_status.da9052_event_tbat == FALSE) {
+		chg_device->tbat_eh_data.eve_type = TBAT_EVE;
+		chg_device->tbat_eh_data.call_back = da9052_bat_tbat_handler;
+		DA9052_DEBUG("events = %d\n", TBAT_EVE);
+		ret = chg_device->da9052->register_event_notifier
+			(chg_device->da9052, &chg_device->tbat_eh_data);
+		if (ret)
+			return -EIO;
+		event_status.da9052_event_tbat = TRUE;
+	}
+
+	return 0;
+}
+
+static s32 da9052_bat_unregister_event(struct da9052_charger_device *chg_device)
+{
+	s32 ret;
+
+	if (event_status.da9052_event_tbat) {
+		ret =
+			chg_device->da9052->unregister_event_notifier
+				(chg_device->da9052, &chg_device->tbat_eh_data);
+		if (ret)
+			return -EIO;
+		event_status.da9052_event_tbat = FALSE;
+	}
+
+	return 0;
+}
+
+static int da9052_bat_get_property(struct power_supply *psy,
+				enum power_supply_property psp,
+				union power_supply_propval *val)
+{
+	struct da9052_charger_device *chg_device =
+	container_of(psy, struct da9052_charger_device, psy);
+
+	/* Validate battery presence */
+	if (chg_device->illegal &&  psp != POWER_SUPPLY_PROP_PRESENT)
+		return -ENODEV;
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_STATUS:
+		val->intval = chg_device->status;
+		break;
+	case POWER_SUPPLY_PROP_ONLINE:
+		val->intval = (chg_device->charger_type == DA9052_NOCHARGER)
+			? 0 : 1;
+		break;
+	case POWER_SUPPLY_PROP_PRESENT:
+		val->intval = chg_device->illegal;
+		break;
+	case POWER_SUPPLY_PROP_HEALTH:
+		val->intval = chg_device->health;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+		val->intval = chg_device->bat_target_voltage * 1000;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+		val->intval = chg_device->bat_volt_cutoff * 1000;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_AVG:
+		val->intval = chg_device->bat_voltage * 1000;
+		break;
+	case POWER_SUPPLY_PROP_CURRENT_AVG:
+		val->intval = chg_device->chg_current * 1000;
+		break;
+	case POWER_SUPPLY_PROP_CAPACITY:
+		val->intval = chg_device->cal_capacity;
+		break;
+	case POWER_SUPPLY_PROP_TEMP:
+		val->intval = bat_temp_reg_to_C(chg_device->bat_temp);
+		break;
+	case POWER_SUPPLY_PROP_TECHNOLOGY:
+		val->intval = chg_device->technology;
+		break;
+	default:
+		return -EINVAL;
+	break;
+	}
+	return 0;
+}
+
+
+static u8 detect_illegal_battery(struct da9052_charger_device *chg_device)
+{
+	u16 buffer = 0;
+	s32  ret = 0;
+
+	/* Measure battery temeperature */
+	ret = da9052_bat_get_battery_temperature(chg_device, &buffer);
+	if (ret) {
+		DA9052_DEBUG("%s: Battery temperature measurement failed\n",
+		__func__);
+		return ret;
+	}
+
+	if (buffer > chg_device->bat_with_no_resistor)
+		chg_device->illegal = TRUE;
+	else
+		chg_device->illegal = FALSE;
+
+
+	/* suspend charging of battery if illegal battey is detected */
+	if (chg_device->illegal)
+		da9052_bat_suspend_charging(chg_device);
+
+	return chg_device->illegal;
+}
+
+void da9052_update_bat_properties(struct da9052_charger_device *chg_device)
+{
+	/* Get Bat status and type */
+	da9052_bat_status_update(chg_device);
+	da9052_bat_level_update(chg_device);
+}
+
+static void da9052_bat_external_power_changed(struct power_supply *psy)
+{
+	struct da9052_charger_device *chg_device =
+	container_of(psy, struct da9052_charger_device, psy);
+
+	cancel_delayed_work(&chg_device->monitor_work);
+	queue_delayed_work(chg_device->monitor_wqueue,
+			   &chg_device->monitor_work, HZ/10);
+}
+
+
+static void da9052_bat_work(struct work_struct *work)
+{
+	struct da9052_charger_device *chg_device = container_of(work,
+		struct da9052_charger_device, monitor_work.work);
+
+	da9052_update_bat_properties(chg_device);
+	queue_delayed_work(chg_device->monitor_wqueue,
+			   &chg_device->monitor_work, HZ * 8);
+}
+
+static enum power_supply_property da9052_bat_props[] = {
+	POWER_SUPPLY_PROP_STATUS,
+	POWER_SUPPLY_PROP_ONLINE,
+	POWER_SUPPLY_PROP_PRESENT,
+	POWER_SUPPLY_PROP_HEALTH,
+	POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+	POWER_SUPPLY_PROP_VOLTAGE_AVG,
+	POWER_SUPPLY_PROP_CURRENT_AVG,
+	POWER_SUPPLY_PROP_CAPACITY,
+	POWER_SUPPLY_PROP_TEMP,
+	POWER_SUPPLY_PROP_TECHNOLOGY,
+
+};
+
+static s32 __devinit da9052_bat_probe(struct platform_device *pdev)
+{
+	struct da9052_charger_device *chg_device;
+	u8 reg_data;
+	int ret;
+
+	chg_device = kzalloc(sizeof(*chg_device), GFP_KERNEL);
+	if (!chg_device)
+		return -ENOMEM;
+
+	chg_device->da9052 = dev_get_drvdata(pdev->dev.parent);
+	platform_set_drvdata(pdev, chg_device);
+
+	chg_device->psy.name			= DA9052_BAT_DEVICE_NAME;
+	chg_device->psy.type			= POWER_SUPPLY_TYPE_BATTERY;
+	chg_device->psy.properties		= da9052_bat_props;
+	chg_device->psy.num_properties		= ARRAY_SIZE(da9052_bat_props);
+	chg_device->psy.get_property		= da9052_bat_get_property;
+	chg_device->psy.external_power_changed	=
+		da9052_bat_external_power_changed;
+	chg_device->psy.use_for_apm		= 1;
+	chg_device->charger_type		= DA9052_NOCHARGER;
+	chg_device->status			= POWER_SUPPLY_STATUS_UNKNOWN;
+	chg_device->health			= POWER_SUPPLY_HEALTH_UNKNOWN;
+	chg_device->technology			= POWER_SUPPLY_TECHNOLOGY_LION;
+	chg_device->bat_with_no_resistor	= 62;
+	chg_device->bat_capacity_limit_low	= 4;
+	chg_device->bat_capacity_limit_high	= 70;
+	chg_device->bat_capacity_full		= 100;
+	chg_device->bat_volt_cutoff		= 2800;
+	chg_device->vbat_first_valid_detect_iteration = 3;
+	chg_device->hysteresis_window_size	= 1;
+	chg_device->chg_hysteresis_const	= 89;
+	chg_device->hysteresis_reading_interval	= 1000;
+	chg_device->hysteresis_no_of_reading	= 10;
+
+	ret = da9052_read(chg_device->da9052, DA9052_CHGCONT_REG, &reg_data);
+	if (ret)
+		goto err_charger_init;
+	chg_device->charger_voltage_drop = bat_drop_reg_to_mV(reg_data &&
+							DA9052_CHGCONT_TCTR);
+	chg_device->bat_target_voltage =
+			bat_reg_to_mV(reg_data && DA9052_CHGCONT_VCHGBAT);
+
+	ret = da9052_read(chg_device->da9052, DA9052_ICHGEND_REG, &reg_data);
+	if (ret)
+		goto err_charger_init;
+	chg_device->chg_end_current = ichg_reg_to_mA(reg_data);
+
+	bat_hysteresis.upper_limit	= 0;
+	bat_hysteresis.lower_limit	= 0;
+	bat_hysteresis.hys_flag		= 0;
+
+	chg_device->illegal		= FALSE;
+	detect_illegal_battery(chg_device);
+
+	da9052_bat_register_event(chg_device);
+	if (ret)
+		goto err_charger_init;
+
+	ret = power_supply_register(&pdev->dev, &chg_device->psy);
+	 if (ret)
+		goto err_charger_init;
+
+	INIT_DELAYED_WORK(&chg_device->monitor_work, da9052_bat_work);
+	chg_device->monitor_wqueue = create_singlethread_workqueue(
+		pdev->dev.bus_id);
+	if (!chg_device->monitor_wqueue)
+		goto err_charger_init;
+	queue_delayed_work(chg_device->monitor_wqueue,
+			   &chg_device->monitor_work, HZ * 1);
+
+	return 0;
+
+err_charger_init:
+	platform_set_drvdata(pdev, NULL);
+	kfree(chg_device);
+	return ret;
+}
+static int __devexit da9052_bat_remove(struct platform_device *dev)
+{
+	struct da9052_charger_device *chg_device = platform_get_drvdata(dev);
+
+	/* unregister the events.*/
+	da9052_bat_unregister_event(chg_device);
+
+	cancel_rearming_delayed_workqueue(chg_device->monitor_wqueue,
+					  &chg_device->monitor_work);
+	destroy_workqueue(chg_device->monitor_wqueue);
+
+	power_supply_unregister(&chg_device->psy);
+
+	return 0;
+}
+
+static struct platform_driver da9052_bat_driver = {
+	.probe		= da9052_bat_probe,
+	.remove		= __devexit_p(da9052_bat_remove),
+	.driver.name	= DA9052_BAT_DEVICE_NAME,
+	.driver.owner	= THIS_MODULE,
+};
+
+static int __init da9052_bat_init(void)
+{
+	printk(banner);
+	return platform_driver_register(&da9052_bat_driver);
+}
+
+static void __exit da9052_bat_exit(void)
+{
+	/* To remove printk("DA9052: Unregistering BAT device.\n");*/
+	platform_driver_unregister(&da9052_bat_driver);
+}
+
+module_init(da9052_bat_init);
+module_exit(da9052_bat_exit);
+
+MODULE_AUTHOR("Dialog Semiconductor Ltd");
+MODULE_DESCRIPTION("DA9052 BAT Device Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 9713b1b860c..996f0100238 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -327,5 +327,12 @@ config REGULATOR_AAT2870
 	  If you have a AnalogicTech AAT2870 say Y to enable the
 	  regulator driver.
 
+config REGULATOR_DA9052
+	tristate "Dialog DA9052 regulators"
+	depends on PMIC_DIALOG
+	help
+	  Say y here to support the BUCKs and LDOs regulators found on
+	  Dialog Semiconductor DA9052 PMIC.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 93a6318f532..55d1b5dc3ae 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
 obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
 obj-$(CONFIG_REGULATOR_TPS6586X) += tps6586x-regulator.o
 obj-$(CONFIG_REGULATOR_DA903X)	+= da903x.o
+obj-$(CONFIG_REGULATOR_DA9052)  += da9052-regulator.o
 obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
 obj-$(CONFIG_REGULATOR_PCAP) += pcap-regulator.o
 obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
@@ -46,5 +47,6 @@ obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
 obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
 obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
+obj-$(CONFIG_REGULATOR_DA9052)  += da9052-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/da9052-regulator.c b/drivers/regulator/da9052-regulator.c
new file mode 100644
index 00000000000..612fe60173c
--- /dev/null
+++ b/drivers/regulator/da9052-regulator.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * da9052-regulator.c: Regulator driver for DA9052
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/pm.h>
+
+static struct regulator_ops da9052_ldo_buck_ops;
+
+
+struct regulator {
+	struct device *dev;
+	struct list_head list;
+	int uA_load;
+	int min_uV;
+	int max_uV;
+	int enabled; /* client has called enabled */
+	char *supply_name;
+	struct device_attribute dev_attr;
+	struct regulator_dev *rdev;
+};
+
+
+
+
+#define DA9052_LDO(_id, max, min, step_v, reg, mbits, cbits) \
+{\
+		.reg_desc	= {\
+		.name		= #_id,\
+		.ops		= &da9052_ldo_buck_ops,\
+		.type		= REGULATOR_VOLTAGE,\
+		.id			= _id,\
+		.owner		= THIS_MODULE,\
+	},\
+	.reg_const = {\
+		.max_uV		= (max) * 1000,\
+		.min_uV		= (min) * 1000,\
+		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE\
+		| REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE,\
+		.valid_modes_mask = REGULATOR_MODE_NORMAL,\
+	},\
+		.step_uV		= (step_v) * 1000,\
+		.reg_add		= (reg),\
+		.mask_bits		= (mbits),\
+		.en_bit_mask	= (cbits),\
+}
+
+struct regulator_info {
+	struct regulator_desc reg_desc;
+	struct regulation_constraints reg_const;
+	int step_uV;
+	unsigned char reg_add;
+	unsigned char mask_bits;
+	unsigned char en_bit_mask;
+};
+
+struct da9052_regulator_priv {
+	struct da9052 *da9052;
+	struct regulator_dev *regulators[];
+};
+
+struct regulator_info da9052_regulators[] = {
+	/* LD01 - LDO10*/
+	DA9052_LDO(DA9052_LDO1, DA9052_LDO1_VOLT_UPPER, DA9052_LDO1_VOLT_LOWER,
+			DA9052_LDO1_VOLT_STEP, DA9052_LDO1_REG,
+			DA9052_LDO1_VLDO1, DA9052_LDO1_LDO1EN),
+
+	DA9052_LDO(DA9052_LDO2,
+			DA9052_LDO2_VOLT_UPPER, DA9052_LDO2_VOLT_LOWER,
+			DA9052_LDO2_VOLT_STEP, DA9052_LDO2_REG,
+			DA9052_LDO2_VLDO2,
+			DA9052_LDO2_LDO2EN),
+
+	DA9052_LDO(DA9052_LDO3, DA9052_LDO34_VOLT_UPPER,
+			DA9052_LDO34_VOLT_LOWER,
+			DA9052_LDO34_VOLT_STEP, DA9052_LDO3_REG,
+			DA9052_LDO3_VLDO3, DA9052_LDO3_LDO3EN),
+
+	DA9052_LDO(DA9052_LDO4, DA9052_LDO34_VOLT_UPPER,
+			DA9052_LDO34_VOLT_LOWER,
+			DA9052_LDO34_VOLT_STEP, DA9052_LDO4_REG,
+			DA9052_LDO4_VLDO4, DA9052_LDO4_LDO4EN),
+
+	DA9052_LDO(DA9052_LDO5, DA9052_LDO567810_VOLT_UPPER,
+			DA9052_LDO567810_VOLT_LOWER,
+			DA9052_LDO567810_VOLT_STEP, DA9052_LDO5_REG,
+			DA9052_LDO5_VLDO5, DA9052_LDO5_LDO5EN),
+
+	DA9052_LDO(DA9052_LDO6, DA9052_LDO567810_VOLT_UPPER,
+			DA9052_LDO567810_VOLT_LOWER,
+			DA9052_LDO567810_VOLT_STEP, DA9052_LDO6_REG,
+			DA9052_LDO6_VLDO6, DA9052_LDO6_LDO6EN),
+
+	DA9052_LDO(DA9052_LDO7, DA9052_LDO567810_VOLT_UPPER,
+			DA9052_LDO567810_VOLT_LOWER,
+			DA9052_LDO567810_VOLT_STEP, DA9052_LDO7_REG,
+			DA9052_LDO7_VLDO7, DA9052_LDO7_LDO7EN),
+
+	DA9052_LDO(DA9052_LDO8, DA9052_LDO567810_VOLT_UPPER,
+			DA9052_LDO567810_VOLT_LOWER,
+			DA9052_LDO567810_VOLT_STEP, DA9052_LDO8_REG,
+			DA9052_LDO8_VLDO8, DA9052_LDO8_LDO8EN),
+
+	DA9052_LDO(DA9052_LDO9, DA9052_LDO9_VOLT_UPPER,
+			DA9052_LDO9_VOLT_LOWER,
+			DA9052_LDO9_VOLT_STEP,
+			DA9052_LDO9_REG, DA9052_LDO9_VLDO9,
+			DA9052_LDO9_LDO9EN),
+
+	DA9052_LDO(DA9052_LDO10, DA9052_LDO567810_VOLT_UPPER,
+			DA9052_LDO567810_VOLT_LOWER,
+			DA9052_LDO567810_VOLT_STEP, DA9052_LDO10_REG,
+			DA9052_LDO10_VLDO10, DA9052_LDO10_LDO10EN),
+
+	/* BUCKS */
+	DA9052_LDO(DA9052_BUCK_CORE, DA9052_BUCK_CORE_PRO_VOLT_UPPER,
+			DA9052_BUCK_CORE_PRO_VOLT_LOWER,
+			DA9052_BUCK_CORE_PRO_STEP, DA9052_BUCKCORE_REG,
+			DA9052_BUCKCORE_VBCORE, DA9052_BUCKCORE_BCOREEN),
+
+	DA9052_LDO(DA9052_BUCK_PRO, DA9052_BUCK_CORE_PRO_VOLT_UPPER,
+			DA9052_BUCK_CORE_PRO_VOLT_LOWER,
+			DA9052_BUCK_CORE_PRO_STEP, DA9052_BUCKPRO_REG,
+			DA9052_BUCKPRO_VBPRO, DA9052_BUCKPRO_BPROEN),
+
+	DA9052_LDO(DA9052_BUCK_MEM, DA9052_BUCK_MEM_VOLT_UPPER,
+			DA9052_BUCK_MEM_VOLT_LOWER,
+			DA9052_BUCK_MEM_STEP, DA9052_BUCKMEM_REG,
+			DA9052_BUCKMEM_VBMEM, DA9052_BUCKMEM_BMEMEN),
+#if defined(CONFIG_PMIC_DA9052)
+	DA9052_LDO(DA9052_BUCK_PERI, DA9052_BUCK_PERI_VOLT_UPPER,
+			DA9052_BUCK_PERI_VOLT_LOWER,
+			DA9052_BUCK_PERI_STEP_BELOW_3000, DA9052_BUCKPERI_REG,
+			DA9052_BUCKPERI_VBPERI, DA9052_BUCKPERI_BPERIEN),
+#elif defined(CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx)
+	DA9052_LDO(DA9052_BUCK_PERI, DA9052_BUCK_PERI_VOLT_UPPER,
+			DA9052_BUCK_PERI_VOLT_LOWER,
+			DA9052_BUCK_PERI_STEP, DA9052_BUCKPERI_REG,
+			DA9052_BUCKPERI_VBPERI, DA9052_BUCKPERI_BPERIEN),
+#endif
+};
+
+int da9052_ldo_buck_enable(struct regulator_dev *rdev)
+{
+	struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev);
+	int id = rdev_get_id(rdev);
+	int ret = 0;
+	struct da9052_ssc_msg ssc_msg;
+
+	ssc_msg.addr = da9052_regulators[id].reg_add;
+	ssc_msg.data = 0;
+
+	da9052_lock(priv->da9052);
+	ret = priv->da9052->read(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+
+	ssc_msg.data = (ssc_msg.data | da9052_regulators[id].en_bit_mask);
+
+	ret = priv->da9052->write(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+	da9052_unlock(priv->da9052);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(da9052_ldo_buck_enable);
+/* Code added to support additional attribure in sysfs - changestate */
+
+
+
+int da9052_ldo_buck_disable(struct regulator_dev *rdev)
+{
+	struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev);
+	int id = rdev_get_id(rdev);
+	int ret;
+	struct da9052_ssc_msg ssc_msg;
+
+	ssc_msg.addr = da9052_regulators[id].reg_add;
+	ssc_msg.data = 0;
+
+	da9052_lock(priv->da9052);
+	ret = priv->da9052->read(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+
+	ssc_msg.data = (ssc_msg.data & ~(da9052_regulators[id].en_bit_mask));
+
+	ret = priv->da9052->write(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+	da9052_unlock(priv->da9052);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(da9052_ldo_buck_disable);
+/* Code added to support additional attribure in sysfs - changestate */
+
+static int da9052_ldo_buck_is_enabled(struct regulator_dev *rdev)
+{
+	struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev);
+	int id = rdev_get_id(rdev);
+	int ret;
+	struct da9052_ssc_msg ssc_msg;
+	ssc_msg.addr = da9052_regulators[id].reg_add;
+	ssc_msg.data = 0;
+
+	da9052_lock(priv->da9052);
+	ret = priv->da9052->read(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+	da9052_unlock(priv->da9052);
+	return (ssc_msg.data & da9052_regulators[id].en_bit_mask) != 0;
+}
+
+int da9052_ldo_buck_set_voltage(struct regulator_dev *rdev,
+					int min_uV, int max_uV,
+					unsigned *selector)
+{
+	struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev);
+	struct da9052_ssc_msg ssc_msg;
+	int id = rdev_get_id(rdev);
+	int ret;
+	int ldo_volt = 0;
+	selector;
+
+	/* Below if condition is there for added setvoltage attribute
+	in sysfs */
+	if (0 == max_uV)
+		max_uV = da9052_regulators[id].reg_const.max_uV;
+
+	/* Compare voltage range */
+	if (min_uV > max_uV)
+		return -EINVAL;
+
+	/* Check Minimum/ Maximum voltage range */
+	if (min_uV < da9052_regulators[id].reg_const.min_uV ||
+		min_uV > da9052_regulators[id].reg_const.max_uV)
+		return -EINVAL;
+	if (max_uV < da9052_regulators[id].reg_const.min_uV ||
+		max_uV > da9052_regulators[id].reg_const.max_uV)
+		return -EINVAL;
+#if defined(CONFIG_PMIC_DA9052)
+	/* Get the ldo register value */
+	/* Varying step size for BUCK PERI */
+	if ((da9052_regulators[id].reg_desc.id == DA9052_BUCK_PERI) &&
+			(min_uV >= DA9052_BUCK_PERI_VALUES_3000)) {
+		ldo_volt = (DA9052_BUCK_PERI_VALUES_3000 -
+			da9052_regulators[id].reg_const.min_uV)/
+			(da9052_regulators[id].step_uV);
+		ldo_volt += (min_uV - DA9052_BUCK_PERI_VALUES_3000)/
+			(DA9052_BUCK_PERI_STEP_ABOVE_3000);
+	} else{
+		ldo_volt = (min_uV - da9052_regulators[id].reg_const.min_uV)/
+			(da9052_regulators[id].step_uV);
+		/* Check for maximum value */
+		if ((ldo_volt * da9052_regulators[id].step_uV) +
+			da9052_regulators[id].reg_const.min_uV > max_uV)
+			return -EINVAL;
+	}
+#elif defined(CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx)
+	ldo_volt = (min_uV - da9052_regulators[id].reg_const.min_uV)/
+		(da9052_regulators[id].step_uV);
+	/* Check for maximum value */
+	if ((ldo_volt * da9052_regulators[id].step_uV) +
+		da9052_regulators[id].reg_const.min_uV > max_uV)
+		return -EINVAL;
+#endif
+	/* Configure LDO Voltage, CONF bits */
+	ssc_msg.addr = da9052_regulators[id].reg_add;
+	ssc_msg.data = 0;
+
+	/* Read register */
+	da9052_lock(priv->da9052);
+	ret = priv->da9052->read(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+
+	ssc_msg.data = (ssc_msg.data & ~(da9052_regulators[id].mask_bits));
+	ssc_msg.data |= ldo_volt;
+
+	ret = priv->da9052->write(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+
+	/* Set the GO LDO/BUCk bits so that the voltage changes */
+	ssc_msg.addr = DA9052_SUPPLY_REG;
+	ssc_msg.data = 0;
+
+	ret = priv->da9052->read(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+
+	switch (id) {
+	case DA9052_LDO2:
+		ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VLDO2GO);
+	break;
+	case DA9052_LDO3:
+		ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VLDO3GO);
+	break;
+	case DA9052_BUCK_CORE:
+		ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VBCOREGO);
+	break;
+	case DA9052_BUCK_PRO:
+		ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VBPROGO);
+	break;
+	case DA9052_BUCK_MEM:
+		ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VBMEMGO);
+	break;
+	default:
+		da9052_unlock(priv->da9052);
+		return -EINVAL;
+	}
+
+	ret = priv->da9052->write(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+
+	da9052_unlock(priv->da9052);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(da9052_ldo_buck_set_voltage);
+/* Code added to support additional attributes in sysfs - setvoltage */
+
+
+int da9052_ldo_buck_get_voltage(struct regulator_dev *rdev)
+{
+	struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev);
+	struct da9052_ssc_msg ssc_msg;
+	int id = rdev_get_id(rdev);
+	int ldo_volt = 0;
+	int ldo_volt_uV = 0;
+	int ret;
+
+	ssc_msg.addr = da9052_regulators[id].reg_add;
+	ssc_msg.data = 0;
+	/* Read register */
+	da9052_lock(priv->da9052);
+	ret = priv->da9052->read(priv->da9052, &ssc_msg);
+	if (ret) {
+		da9052_unlock(priv->da9052);
+		return -EIO;
+	}
+	da9052_unlock(priv->da9052);
+
+	ldo_volt = ssc_msg.data & da9052_regulators[id].mask_bits;
+#if defined(CONFIG_PMIC_DA9052)
+	if (da9052_regulators[id].reg_desc.id == DA9052_BUCK_PERI) {
+		if (ldo_volt >= DA9052_BUCK_PERI_VALUES_UPTO_3000) {
+			ldo_volt_uV = ((DA9052_BUCK_PERI_VALUES_UPTO_3000 *
+				da9052_regulators[id].step_uV)
+				+ da9052_regulators[id].reg_const.min_uV);
+			ldo_volt_uV = (ldo_volt_uV +
+				(ldo_volt - DA9052_BUCK_PERI_VALUES_UPTO_3000)
+				* (DA9052_BUCK_PERI_STEP_ABOVE_3000));
+		} else {
+			ldo_volt_uV =
+				(ldo_volt * da9052_regulators[id].step_uV)
+				+ da9052_regulators[id].reg_const.min_uV;
+		}
+	} else {
+		ldo_volt_uV = (ldo_volt * da9052_regulators[id].step_uV) +
+				da9052_regulators[id].reg_const.min_uV;
+	}
+#elif defined(CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx)
+	ldo_volt_uV = (ldo_volt * da9052_regulators[id].step_uV) +
+			da9052_regulators[id].reg_const.min_uV;
+#endif
+	return ldo_volt_uV;
+}
+EXPORT_SYMBOL_GPL(da9052_ldo_buck_get_voltage);
+/* Code added to support additional attributes in sysfs - setvoltage */
+
+
+static struct regulator_ops da9052_ldo_buck_ops = {
+	.is_enabled = da9052_ldo_buck_is_enabled,
+	.enable = da9052_ldo_buck_enable,
+	.disable = da9052_ldo_buck_disable,
+	.get_voltage = da9052_ldo_buck_get_voltage,
+	.set_voltage = da9052_ldo_buck_set_voltage,
+};
+
+static int __devinit da9052_regulator_probe(struct platform_device *pdev)
+{
+	struct da9052_regulator_priv *priv;
+	struct da9052_regulator_platform_data *pdata =
+				(pdev->dev.platform_data);
+	struct da9052 *da9052 = dev_get_drvdata(pdev->dev.parent);
+	struct regulator_init_data  *init_data;
+	int i, ret = 0;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (priv == NULL)
+		return -ENOMEM;
+
+	priv->da9052 = da9052;
+	for (i = 0; i < 14; i++) {
+
+		init_data = &pdata->regulators[i];
+		init_data->driver_data = da9052;
+		pdev->dev.platform_data = init_data;
+		priv->regulators[i] = regulator_register(
+				&da9052_regulators[i].reg_desc,
+				&pdev->dev, init_data,
+				priv);
+		if (IS_ERR(priv->regulators[i])) {
+			ret = PTR_ERR(priv->regulators[i]);
+			goto err;
+		}
+	}
+	platform_set_drvdata(pdev, priv);
+	return 0;
+err:
+	while (--i >= 0)
+		regulator_unregister(priv->regulators[i]);
+	kfree(priv);
+	return ret;
+}
+
+static int __devexit da9052_regulator_remove(struct platform_device *pdev)
+{
+	struct da9052_regulator_priv *priv = platform_get_drvdata(pdev);
+	struct da9052_platform_data *pdata = pdev->dev.platform_data;
+	int i;
+
+	for (i = 0; i < pdata->num_regulators; i++)
+		regulator_unregister(priv->regulators[i]);
+
+	return 0;
+}
+
+static struct platform_driver da9052_regulator_driver = {
+	.probe		= da9052_regulator_probe,
+	.remove		= __devexit_p(da9052_regulator_remove),
+	.driver		= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init da9052_regulator_init(void)
+{
+	return platform_driver_register(&da9052_regulator_driver);
+}
+subsys_initcall(da9052_regulator_init);
+
+static void __exit da9052_regulator_exit(void)
+{
+	platform_driver_unregister(&da9052_regulator_driver);
+}
+module_exit(da9052_regulator_exit);
+
+MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
+MODULE_DESCRIPTION("Power Regulator driver for Dialog DA9052 PMIC");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 53eb4e55b28..8e05f3bb3a4 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -634,6 +634,13 @@ config RTC_MXC
 	   This driver can also be built as a module, if so, the module
 	   will be called "rtc-mxc".
 
+config RTC_DRV_MXC_V2
+	tristate "Freescale MXC Secure Real Time Clock"
+	depends on ARCH_MXC
+	depends on RTC_CLASS
+	help
+	   Support for Freescale SRTC MXC
+
 config RTC_DRV_BQ4802
 	tristate "TI BQ4802"
 	help
@@ -1070,4 +1077,11 @@ config RTC_DRV_PUV3
 	  This drive can also be built as a module. If so, the module
 	  will be called rtc-puv3.
 
+config RTC_DRV_DA9052
+	tristate "Dialog DA9052 RTC"
+	depends on PMIC_DIALOG
+	help
+	  Say y here to support the RTC found on
+	  Dialog Semiconductor DA9052 PMIC.
+
 endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 6e6982335c1..73a7cde370e 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -109,3 +109,5 @@ obj-$(CONFIG_RTC_DRV_VT8500)	+= rtc-vt8500.o
 obj-$(CONFIG_RTC_DRV_WM831X)	+= rtc-wm831x.o
 obj-$(CONFIG_RTC_DRV_WM8350)	+= rtc-wm8350.o
 obj-$(CONFIG_RTC_DRV_X1205)	+= rtc-x1205.o
+obj-$(CONFIG_RTC_DRV_DA9052)	+= rtc-da9052.o
+obj-$(CONFIG_RTC_DRV_MXC_V2)    += rtc-mxc_v2.o
diff --git a/drivers/rtc/rtc-da9052.c b/drivers/rtc/rtc-da9052.c
new file mode 100644
index 00000000000..17ca1777c1c
--- /dev/null
+++ b/drivers/rtc/rtc-da9052.c
@@ -0,0 +1,694 @@
+/*
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * rtc-da9052.c: RTC driver for DA9052
+ */
+
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/rtc.h>
+
+#define DRIVER_NAME "da9052-rtc"
+#define ENABLE		1
+#define DISABLE		0
+
+struct da9052_rtc {
+	struct rtc_device *rtc;
+	struct da9052 *da9052;
+	struct da9052_eh_nb eh_data;
+	unsigned char is_min_alarm;
+	unsigned char enable_tick_alarm;
+	unsigned char enable_clk_buffer;
+	unsigned char set_osc_trim_freq;
+};
+
+static int da9052_rtc_enable_alarm(struct da9052 *da9052, unsigned char flag);
+
+void da9052_rtc_notifier(struct da9052_eh_nb *eh_data, unsigned int event)
+{
+	struct da9052_rtc *rtc =
+		container_of(eh_data, struct da9052_rtc, eh_data);
+	struct da9052_ssc_msg msg;
+	unsigned int ret;
+
+	/* Check the alarm type - TIMER or TICK */
+	msg.addr = DA9052_ALARMMI_REG;
+
+	da9052_lock(rtc->da9052);
+	ret = rtc->da9052->read(rtc->da9052, &msg);
+	if (ret != 0) {
+		da9052_unlock(rtc->da9052);
+		return;
+	}
+
+	da9052_unlock(rtc->da9052);
+
+
+	if (msg.data & DA9052_ALARMMI_ALARMTYPE) {
+		da9052_rtc_enable_alarm(rtc->da9052, 0);
+		printk(KERN_INFO "RTC: TIMER ALARM\n");
+	} else {
+		kobject_uevent(&rtc->rtc->dev.kobj, KOBJ_CHANGE);
+		printk(KERN_INFO "RTC: TICK ALARM\n");
+	}
+}
+
+static int da9052_rtc_validate_parameters(struct rtc_time *rtc_tm)
+{
+
+	if (rtc_tm->tm_sec > DA9052_RTC_SECONDS_LIMIT)
+		return DA9052_RTC_INVALID_SECONDS;
+
+	if (rtc_tm->tm_min > DA9052_RTC_MINUTES_LIMIT)
+		return DA9052_RTC_INVALID_MINUTES;
+
+	if (rtc_tm->tm_hour > DA9052_RTC_HOURS_LIMIT)
+		return DA9052_RTC_INVALID_HOURS;
+
+	if (rtc_tm->tm_mday == 0)
+		return DA9052_RTC_INVALID_DAYS;
+
+	if ((rtc_tm->tm_mon > DA9052_RTC_MONTHS_LIMIT) ||
+	(rtc_tm->tm_mon == 0))
+		return DA9052_RTC_INVALID_MONTHS;
+
+	if (rtc_tm->tm_year > DA9052_RTC_YEARS_LIMIT)
+		return DA9052_RTC_INVALID_YEARS;
+
+	if ((rtc_tm->tm_mon == FEBRUARY)) {
+		if (((rtc_tm->tm_year % 4 == 0) &&
+			(rtc_tm->tm_year % 100 != 0)) ||
+			(rtc_tm->tm_year % 400 == 0)) {
+			if (rtc_tm->tm_mday > 29)
+				return DA9052_RTC_INVALID_DAYS;
+		} else if (rtc_tm->tm_mday > 28) {
+			return DA9052_RTC_INVALID_DAYS;
+		}
+	}
+
+	if (((rtc_tm->tm_mon == APRIL) || (rtc_tm->tm_mon == JUNE) ||
+		(rtc_tm->tm_mon == SEPTEMBER) || (rtc_tm->tm_mon == NOVEMBER))
+		&& (rtc_tm->tm_mday == 31)) {
+		return DA9052_RTC_INVALID_DAYS;
+	}
+
+
+	return 0;
+}
+
+static int da9052_rtc_settime(struct da9052 *da9052, struct rtc_time *rtc_tm)
+{
+
+	struct da9052_ssc_msg msg_arr[6];
+	int validate_param = 0;
+	unsigned char loop_index = 0;
+	int ret = 0;
+
+
+	/* System compatability */
+	rtc_tm->tm_year -= 100;
+	rtc_tm->tm_mon += 1;
+
+	validate_param = da9052_rtc_validate_parameters(rtc_tm);
+	if (validate_param)
+		return validate_param;
+
+	msg_arr[loop_index].addr = DA9052_COUNTS_REG;
+	msg_arr[loop_index++].data = DA9052_COUNTS_MONITOR | rtc_tm->tm_sec;
+
+	msg_arr[loop_index].addr = DA9052_COUNTMI_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = rtc_tm->tm_min;
+
+	msg_arr[loop_index].addr = DA9052_COUNTH_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = rtc_tm->tm_hour;
+
+	msg_arr[loop_index].addr = DA9052_COUNTD_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = rtc_tm->tm_mday;
+
+	msg_arr[loop_index].addr = DA9052_COUNTMO_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = rtc_tm->tm_mon;
+
+	msg_arr[loop_index].addr = DA9052_COUNTY_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = rtc_tm->tm_year;
+
+	da9052_lock(da9052);
+	ret = da9052->write_many(da9052, msg_arr, loop_index);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+
+	da9052_unlock(da9052);
+	return 0;
+}
+
+static int da9052_rtc_gettime(struct da9052 *da9052, struct rtc_time *rtc_tm)
+{
+
+	struct da9052_ssc_msg msg[6];
+	unsigned char loop_index = 0;
+	int validate_param = 0;
+	int ret = 0;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_COUNTS_REG;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_COUNTMI_REG;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_COUNTH_REG;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_COUNTD_REG;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_COUNTMO_REG;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_COUNTY_REG;
+
+	da9052_lock(da9052);
+	ret = da9052->read_many(da9052, msg, loop_index);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+	da9052_unlock(da9052);
+
+	rtc_tm->tm_year = msg[--loop_index].data & DA9052_COUNTY_COUNTYEAR;
+	rtc_tm->tm_mon = msg[--loop_index].data & DA9052_COUNTMO_COUNTMONTH;
+	rtc_tm->tm_mday = msg[--loop_index].data & DA9052_COUNTD_COUNTDAY;
+	rtc_tm->tm_hour = msg[--loop_index].data & DA9052_COUNTH_COUNTHOUR;
+	rtc_tm->tm_min = msg[--loop_index].data & DA9052_COUNTMI_COUNTMIN;
+	rtc_tm->tm_sec = msg[--loop_index].data & DA9052_COUNTS_COUNTSEC;
+
+	validate_param = da9052_rtc_validate_parameters(rtc_tm);
+	if (validate_param)
+		return validate_param;
+
+	/* System compatability */
+	rtc_tm->tm_year += 100;
+	rtc_tm->tm_mon -= 1;
+	return 0;
+}
+
+static int da9052_alarm_gettime(struct da9052 *da9052, struct rtc_time *rtc_tm)
+{
+	struct da9052_ssc_msg msg[5];
+	unsigned char loop_index = 0;
+	int validate_param = 0;
+	int ret = 0;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_ALARMMI_REG;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_ALARMH_REG;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_ALARMD_REG;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_ALARMMO_REG;
+
+	msg[loop_index].data = 0;
+	msg[loop_index++].addr = DA9052_ALARMY_REG;
+
+	da9052_lock(da9052);
+	ret = da9052->read_many(da9052, msg, loop_index);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+	da9052_unlock(da9052);
+
+	rtc_tm->tm_year = msg[--loop_index].data & DA9052_ALARMY_ALARMYEAR;
+	rtc_tm->tm_mon = msg[--loop_index].data & DA9052_ALARMMO_ALARMMONTH;
+	rtc_tm->tm_mday = msg[--loop_index].data & DA9052_ALARMD_ALARMDAY;
+	rtc_tm->tm_hour = msg[--loop_index].data & DA9052_ALARMH_ALARMHOUR;
+	rtc_tm->tm_min = msg[--loop_index].data & DA9052_ALARMMI_ALARMMIN;
+
+	validate_param = da9052_rtc_validate_parameters(rtc_tm);
+	if (validate_param)
+		return validate_param;
+
+	/* System compatability */
+	rtc_tm->tm_year += 100;
+	rtc_tm->tm_mon -= 1;
+
+	return 0;
+}
+
+static int da9052_alarm_settime(struct da9052 *da9052, struct rtc_time *rtc_tm)
+{
+
+	struct da9052_ssc_msg msg_arr[5];
+	struct da9052_ssc_msg msg;
+	int validate_param = 0;
+	unsigned char loop_index = 0;
+	int ret = 0;
+
+	rtc_tm->tm_sec = 0;
+
+	/* System compatability */
+	rtc_tm->tm_year -= 100;
+	rtc_tm->tm_mon += 1;
+
+	validate_param = da9052_rtc_validate_parameters(rtc_tm);
+	if (validate_param)
+		return validate_param;
+
+	msg.addr = DA9052_ALARMMI_REG;
+	msg.data = 0;
+
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+
+	msg.data = msg.data & ~(DA9052_ALARMMI_ALARMMIN);
+	msg.data |= rtc_tm->tm_min;
+
+	msg_arr[loop_index].addr = DA9052_ALARMMI_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = msg.data;
+
+	msg_arr[loop_index].addr = DA9052_ALARMH_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = rtc_tm->tm_hour;
+
+	msg_arr[loop_index].addr = DA9052_ALARMD_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = rtc_tm->tm_mday;
+
+	msg_arr[loop_index].addr = DA9052_ALARMMO_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = rtc_tm->tm_mon;
+
+	msg.addr = DA9052_ALARMY_REG;
+	msg.data = 0;
+	ret = da9052->read(da9052, &msg);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+
+	msg.data = msg.data & ~(DA9052_ALARMY_ALARMYEAR);
+
+
+	msg.data |= rtc_tm->tm_year;
+	msg_arr[loop_index].addr = DA9052_ALARMY_REG;
+	msg_arr[loop_index].data = 0;
+	msg_arr[loop_index++].data = msg.data;
+
+	ret = da9052->write_many(da9052, msg_arr, loop_index);
+	if (ret) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+
+	da9052_unlock(da9052);
+	return 0;
+}
+
+static int da9052_rtc_get_alarm_status(struct da9052 *da9052)
+{
+	struct da9052_ssc_msg msg;
+	int ret = 0;
+
+	msg.addr = DA9052_ALARMY_REG;
+	msg.data = 0;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret != 0) {
+			da9052_unlock(da9052);
+	return ret;
+	}
+
+	da9052_unlock(da9052);
+	msg.data &= DA9052_ALARMY_ALARMON;
+
+	return (msg.data > 0) ? 1 : 0;
+}
+
+
+static int da9052_rtc_enable_alarm(struct da9052 *da9052, unsigned char flag)
+{
+	struct da9052_ssc_msg msg;
+	int ret = 0;
+
+	msg.addr = DA9052_ALARMY_REG;
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &msg);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+
+	if (flag)
+		msg.data = msg.data | DA9052_ALARMY_ALARMON;
+	else
+		msg.data = msg.data & ~(DA9052_ALARMY_ALARMON);
+
+	ret = da9052->write(da9052, &msg);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+	da9052_unlock(da9052);
+
+	return 0;
+}
+
+
+static ssize_t da9052_rtc_mask_irq(struct da9052 *da9052)
+{
+	unsigned char data = 0;
+	ssize_t ret = 0;
+	struct da9052_ssc_msg ssc_msg;
+
+	ssc_msg.addr = DA9052_IRQMASKA_REG;
+	ssc_msg.data = 0;
+
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+
+	data = ret;
+	ssc_msg.data = data |= DA9052_IRQMASKA_MALRAM;
+
+	ret = da9052->write(da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+
+	da9052_unlock(da9052);
+	return 0;
+}
+
+
+static ssize_t da9052_rtc_unmask_irq(struct da9052 *da9052)
+{
+	unsigned char data = 0;
+	ssize_t ret = 0;
+	struct da9052_ssc_msg ssc_msg;
+
+	ssc_msg.addr =  DA9052_IRQMASKA_REG;
+	ssc_msg.data =  0;
+
+	da9052_lock(da9052);
+	ret = da9052->read(da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+
+	data = ret;
+	ssc_msg.data = data &= ~DA9052_IRQMASKA_MALRAM;
+
+	ret = da9052->write(da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(da9052);
+		return ret;
+	}
+
+	da9052_unlock(da9052);
+	return 0;
+
+}
+
+static int da9052_rtc_class_ops_gettime
+			(struct device *dev, struct rtc_time *rtc_tm)
+{
+	int ret;
+	struct da9052 *da9052 = dev_get_drvdata(dev->parent);
+	ret = da9052_rtc_gettime(da9052, rtc_tm);
+	if (ret)
+		return ret;
+	return 0;
+}
+
+
+static int da9052_rtc_class_ops_settime(struct device *dev, struct rtc_time *tm)
+{
+	int ret;
+	struct da9052 *da9052 = dev_get_drvdata(dev->parent);
+	ret = da9052_rtc_settime(da9052, tm);
+
+	return ret;
+}
+
+static int da9052_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	int ret;
+	struct rtc_time *tm = &alrm->time;
+	struct da9052 *da9052 = dev_get_drvdata(dev->parent);
+	ret = da9052_alarm_gettime(da9052, tm);
+
+	if (ret)
+		return ret;
+
+	alrm->enabled = da9052_rtc_get_alarm_status(da9052);
+
+	return 0;
+
+}
+
+static int da9052_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	int ret = 0;
+	struct rtc_time *tm = &alrm->time;
+	struct da9052 *da9052 = dev_get_drvdata(dev->parent);
+
+	ret = da9052_alarm_settime(da9052, tm);
+
+	if (ret)
+		return ret;
+
+	ret = da9052_rtc_enable_alarm(da9052, 1);
+
+	return ret;
+}
+
+static int da9052_rtc_update_irq_enable(struct device *dev,
+		unsigned int enabled)
+{
+	struct da9052_rtc *priv = dev_get_drvdata(dev);
+	int ret = -ENODATA;
+
+	da9052_lock(priv->da9052);
+
+	ret = (enabled ? da9052_rtc_unmask_irq : da9052_rtc_mask_irq)
+						(priv->da9052);
+
+	da9052_unlock(priv->da9052);
+
+	return ret;
+}
+
+static int da9052_rtc_alarm_irq_enable(struct device *dev,
+			unsigned int enabled)
+{
+	struct da9052_rtc *priv = dev_get_drvdata(dev);
+
+	if (enabled)
+		return da9052_rtc_enable_alarm(priv->da9052, enabled);
+	else
+		return da9052_rtc_enable_alarm(priv->da9052, enabled);
+}
+
+static const struct rtc_class_ops da9052_rtc_ops = {
+	.read_time	= da9052_rtc_class_ops_gettime,
+	.set_time	= da9052_rtc_class_ops_settime,
+	.read_alarm	= da9052_rtc_readalarm,
+	.set_alarm	= da9052_rtc_setalarm,
+#if 0
+	.update_irq_enable = da9052_rtc_update_irq_enable,
+	.alarm_irq_enable = da9052_rtc_alarm_irq_enable,
+#endif
+};
+
+
+static int __devinit da9052_rtc_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct da9052_rtc *priv;
+	struct da9052_ssc_msg ssc_msg;
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->da9052 = dev_get_drvdata(pdev->dev.parent);
+	platform_set_drvdata(pdev, priv);
+
+	/* Added to support sysfs wakealarm attribute */
+	pdev->dev.power.can_wakeup = 1;
+	/* Added to support sysfs wakealarm attribute */
+
+	/* Set the EH structure */
+	priv->eh_data.eve_type = ALARM_EVE;
+	priv->eh_data.call_back = &da9052_rtc_notifier;
+	ret = priv->da9052->register_event_notifier(priv->da9052,
+		&priv->eh_data);
+	if (ret)
+		goto err_register_alarm;
+
+	priv->is_min_alarm = 1;
+	priv->enable_tick_alarm = 1;
+	priv->enable_clk_buffer = 1;
+	priv->set_osc_trim_freq = 5;
+	/* Enable/Disable TICK Alarm */
+	/* Read ALARM YEAR register */
+	ssc_msg.addr = DA9052_ALARMY_REG;
+	ssc_msg.data = 0;
+
+	da9052_lock(priv->da9052);
+	ret = priv->da9052->read(priv->da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(priv->da9052);
+		goto err_ssc_comm;
+	}
+
+	if (priv->enable_tick_alarm)
+		ssc_msg.data = (ssc_msg.data | DA9052_ALARMY_TICKON);
+	else
+		ssc_msg.data =
+		((ssc_msg.data & ~(DA9052_ALARMY_TICKON)));
+
+	ret = priv->da9052->write(priv->da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(priv->da9052);
+		goto err_ssc_comm;
+	}
+
+	/* Set TICK Alarm to 1 minute or 1 sec */
+	/* Read ALARM MINUTES register */
+	ssc_msg.addr = DA9052_ALARMMI_REG;
+	ssc_msg.data = 0;
+
+	ret = priv->da9052->read(priv->da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(priv->da9052);
+		goto err_ssc_comm;
+	}
+
+	if (priv->is_min_alarm)
+		/* Set 1 minute tick type */
+		ssc_msg.data = (ssc_msg.data | DA9052_ALARMMI_TICKTYPE);
+	else
+		/* Set 1 sec tick type */
+		ssc_msg.data = (ssc_msg.data & ~(DA9052_ALARMMI_TICKTYPE));
+
+	ret = priv->da9052->write(priv->da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(priv->da9052);
+		goto err_ssc_comm;
+	}
+
+	/* Enable/Disable Clock buffer in Power Down Mode */
+	ssc_msg.addr = DA9052_PDDIS_REG;
+	ssc_msg.data = 0;
+
+	ret = priv->da9052->read(priv->da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(priv->da9052);
+		goto err_ssc_comm;
+	}
+
+	if (priv->enable_clk_buffer)
+		ssc_msg.data = (ssc_msg.data | DA9052_PDDIS_OUT32KPD);
+	else
+		ssc_msg.data = (ssc_msg.data & ~(DA9052_PDDIS_OUT32KPD));
+
+	ret = priv->da9052->write(priv->da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(priv->da9052);
+		goto err_ssc_comm;
+	}
+
+	/* Set clock trim frequency value */
+	ssc_msg.addr = DA9052_OSCTRIM_REG;
+	ssc_msg.data = priv->set_osc_trim_freq;
+
+	ret = priv->da9052->write(priv->da9052, &ssc_msg);
+	if (ret != 0) {
+		da9052_unlock(priv->da9052);
+		goto err_ssc_comm;
+	}
+	da9052_unlock(priv->da9052);
+
+	priv->rtc = rtc_device_register(pdev->name,
+			&pdev->dev, &da9052_rtc_ops, THIS_MODULE);
+	if (IS_ERR(priv->rtc)) {
+		ret = PTR_ERR(priv->rtc);
+		goto err_ssc_comm;
+	}
+	return 0;
+
+err_ssc_comm:
+		priv->da9052->unregister_event_notifier
+			(priv->da9052, &priv->eh_data);
+err_register_alarm:
+		platform_set_drvdata(pdev, NULL);
+		kfree(priv);
+
+	return ret;
+}
+
+static int __devexit da9052_rtc_remove(struct platform_device *pdev)
+{
+	struct da9052_rtc *priv = platform_get_drvdata(pdev);
+	rtc_device_unregister(priv->rtc);
+	da9052_lock(priv->da9052);
+	priv->da9052->unregister_event_notifier(priv->da9052, &priv->eh_data);
+	da9052_unlock(priv->da9052);
+	platform_set_drvdata(pdev, NULL);
+	kfree(priv);
+	return 0;
+}
+
+static struct platform_driver da9052_rtc_driver = {
+	.probe = da9052_rtc_probe,
+	.remove = __devexit_p(da9052_rtc_remove),
+	.driver = {
+		.name = DRIVER_NAME,
+		.owner = THIS_MODULE,
+	},
+};
+
+
+static int __init da9052_rtc_init(void)
+{
+	return platform_driver_register(&da9052_rtc_driver);
+}
+module_init(da9052_rtc_init);
+
+static void __exit da9052_rtc_exit(void)
+{
+	platform_driver_unregister(&da9052_rtc_driver);
+}
+module_exit(da9052_rtc_exit);
+
+MODULE_AUTHOR("Dialog Semiconductor Ltd <dchen@diasemi.com>");
+MODULE_DESCRIPTION("RTC driver for Dialog DA9052 PMIC");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/rtc/rtc-mxc_v2.c b/drivers/rtc/rtc-mxc_v2.c
new file mode 100644
index 00000000000..eb0e987ef6d
--- /dev/null
+++ b/drivers/rtc/rtc-mxc_v2.c
@@ -0,0 +1,765 @@
+/*
+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * Implementation based on rtc-ds1553.c
+ */
+
+/*!
+ * @defgroup RTC Real Time Clock (RTC) Driver
+ */
+/*!
+ * @file rtc-mxc_v2.c
+ * @brief Real Time Clock interface
+ *
+ * This file contains Real Time Clock interface for Linux.
+ *
+ * @ingroup RTC
+ */
+
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/rtc.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/mxc_srtc.h>
+
+#define SRTC_LPSCLR_LLPSC_LSH	17	 /* start bit for LSB time value */
+
+#define SRTC_LPPDR_INIT       0x41736166	/* init for glitch detect */
+
+#define SRTC_LPCR_SWR_LP      (1 << 0)	/* lp software reset */
+#define SRTC_LPCR_EN_LP       (1 << 3)	/* lp enable */
+#define SRTC_LPCR_WAE         (1 << 4)	/* lp wakeup alarm enable */
+#define SRTC_LPCR_SAE         (1 << 5)	/* lp security alarm enable */
+#define SRTC_LPCR_SI          (1 << 6)	/* lp security interrupt enable */
+#define SRTC_LPCR_ALP         (1 << 7)	/* lp alarm flag */
+#define SRTC_LPCR_LTC         (1 << 8)	/* lp lock time counter */
+#define SRTC_LPCR_LMC         (1 << 9)	/* lp lock monotonic counter */
+#define SRTC_LPCR_SV          (1 << 10)	/* lp security violation */
+#define SRTC_LPCR_NSA         (1 << 11)	/* lp non secure access */
+#define SRTC_LPCR_NVEIE       (1 << 12)	/* lp non valid state exit int en */
+#define SRTC_LPCR_IEIE        (1 << 13)	/* lp init state exit int enable */
+#define SRTC_LPCR_NVE         (1 << 14)	/* lp non valid state exit bit */
+#define SRTC_LPCR_IE          (1 << 15)	/* lp init state exit bit */
+
+#define SRTC_LPCR_ALL_INT_EN (SRTC_LPCR_WAE | SRTC_LPCR_SAE | \
+			      SRTC_LPCR_SI | SRTC_LPCR_ALP | \
+			      SRTC_LPCR_NVEIE | SRTC_LPCR_IEIE)
+
+#define SRTC_LPSR_TRI         (1 << 0)	/* lp time read invalidate */
+#define SRTC_LPSR_PGD         (1 << 1)	/* lp power supply glitc detected */
+#define SRTC_LPSR_CTD         (1 << 2)	/* lp clock tampering detected */
+#define SRTC_LPSR_ALP         (1 << 3)	/* lp alarm flag */
+#define SRTC_LPSR_MR          (1 << 4)	/* lp monotonic counter rollover */
+#define SRTC_LPSR_TR          (1 << 5)	/* lp time rollover */
+#define SRTC_LPSR_EAD         (1 << 6)	/* lp external alarm detected */
+#define SRTC_LPSR_IT0         (1 << 7)	/* lp IIM throttle */
+#define SRTC_LPSR_IT1         (1 << 8)
+#define SRTC_LPSR_IT2         (1 << 9)
+#define SRTC_LPSR_SM0         (1 << 10)	/* lp security mode */
+#define SRTC_LPSR_SM1         (1 << 11)
+#define SRTC_LPSR_STATE_LP0   (1 << 12)	/* lp state */
+#define SRTC_LPSR_STATE_LP1   (1 << 13)
+#define SRTC_LPSR_NVES        (1 << 14)	/* lp non-valid state exit status */
+#define SRTC_LPSR_IES         (1 << 15)	/* lp init state exit status */
+
+#define MAX_PIE_NUM     15
+#define MAX_PIE_FREQ    32768
+#define MIN_PIE_FREQ	1
+
+#define SRTC_PI0         (1 << 0)
+#define SRTC_PI1         (1 << 1)
+#define SRTC_PI2         (1 << 2)
+#define SRTC_PI3         (1 << 3)
+#define SRTC_PI4         (1 << 4)
+#define SRTC_PI5         (1 << 5)
+#define SRTC_PI6         (1 << 6)
+#define SRTC_PI7         (1 << 7)
+#define SRTC_PI8         (1 << 8)
+#define SRTC_PI9         (1 << 9)
+#define SRTC_PI10        (1 << 10)
+#define SRTC_PI11        (1 << 11)
+#define SRTC_PI12        (1 << 12)
+#define SRTC_PI13        (1 << 13)
+#define SRTC_PI14        (1 << 14)
+#define SRTC_PI15        (1 << 15)
+
+#define PIT_ALL_ON      (SRTC_PI1 | SRTC_PI2 | SRTC_PI3 | \
+			SRTC_PI4 | SRTC_PI5 | SRTC_PI6 | SRTC_PI7 | \
+			SRTC_PI8 | SRTC_PI9 | SRTC_PI10 | SRTC_PI11 | \
+			SRTC_PI12 | SRTC_PI13 | SRTC_PI14 | SRTC_PI15)
+
+#define SRTC_SWR_HP      (1 << 0)	/* hp software reset */
+#define SRTC_EN_HP       (1 << 3)	/* hp enable */
+#define SRTC_TS          (1 << 4)	/* time syncronize hp with lp */
+
+#define SRTC_IE_AHP      (1 << 16)	/* Alarm HP Interrupt Enable bit */
+#define SRTC_IE_WDHP     (1 << 18)	/* Write Done HP Interrupt Enable bit */
+#define SRTC_IE_WDLP     (1 << 19)	/* Write Done LP Interrupt Enable bit */
+
+#define SRTC_ISR_AHP     (1 << 16)	/* interrupt status: alarm hp */
+#define SRTC_ISR_WDHP    (1 << 18)	/* interrupt status: write done hp */
+#define SRTC_ISR_WDLP    (1 << 19)	/* interrupt status: write done lp */
+#define SRTC_ISR_WPHP    (1 << 20)	/* interrupt status: write pending hp */
+#define SRTC_ISR_WPLP    (1 << 21)	/* interrupt status: write pending lp */
+
+#define SRTC_LPSCMR	0x00	/* LP Secure Counter MSB Reg */
+#define SRTC_LPSCLR	0x04	/* LP Secure Counter LSB Reg */
+#define SRTC_LPSAR	0x08	/* LP Secure Alarm Reg */
+#define SRTC_LPSMCR	0x0C	/* LP Secure Monotonic Counter Reg */
+#define SRTC_LPCR	0x10	/* LP Control Reg */
+#define SRTC_LPSR	0x14	/* LP Status Reg */
+#define SRTC_LPPDR	0x18	/* LP Power Supply Glitch Detector Reg */
+#define SRTC_LPGR	0x1C	/* LP General Purpose Reg */
+#define SRTC_HPCMR	0x20	/* HP Counter MSB Reg */
+#define SRTC_HPCLR	0x24	/* HP Counter LSB Reg */
+#define SRTC_HPAMR	0x28	/* HP Alarm MSB Reg */
+#define SRTC_HPALR	0x2C	/* HP Alarm LSB Reg */
+#define SRTC_HPCR	0x30	/* HP Control Reg */
+#define SRTC_HPISR	0x34	/* HP Interrupt Status Reg */
+#define SRTC_HPIENR	0x38	/* HP Interrupt Enable Reg */
+
+#define SRTC_SECMODE_MASK	0x3	/* the mask of SRTC security mode */
+#define SRTC_SECMODE_LOW	0x0	/* Low Security */
+#define SRTC_SECMODE_MED	0x1	/* Medium Security */
+#define SRTC_SECMODE_HIGH	0x2	/* High Security */
+#define SRTC_SECMODE_RESERVED	0x3	/* Reserved */
+
+struct rtc_drv_data {
+	struct rtc_device *rtc;
+	void __iomem *ioaddr;
+	unsigned long baseaddr;
+	int irq;
+	struct clk *clk;
+	bool irq_enable;
+};
+
+
+/* completion event for implementing RTC_WAIT_FOR_TIME_SET ioctl */
+DECLARE_COMPLETION(srtc_completion);
+/* global to save difference of 47-bit counter value */
+static int64_t time_diff;
+
+/*!
+ * @defgroup RTC Real Time Clock (RTC) Driver
+ */
+/*!
+ * @file rtc-mxc.c
+ * @brief Real Time Clock interface
+ *
+ * This file contains Real Time Clock interface for Linux.
+ *
+ * @ingroup RTC
+ */
+
+static unsigned long rtc_status;
+
+static DEFINE_SPINLOCK(rtc_lock);
+
+/*!
+ * This function does write synchronization for writes to the lp srtc block.
+ * To take care of the asynchronous CKIL clock, all writes from the IP domain
+ * will be synchronized to the CKIL domain.
+ */
+static inline void rtc_write_sync_lp(void __iomem *ioaddr)
+{
+	unsigned int i, count;
+	/* Wait for 3 CKIL cycles */
+	for (i = 0; i < 3; i++) {
+		count = __raw_readl(ioaddr + SRTC_LPSCLR);
+		while
+			((__raw_readl(ioaddr + SRTC_LPSCLR)) == count);
+	}
+}
+
+/*!
+ * This function updates the RTC alarm registers and then clears all the
+ * interrupt status bits.
+ *
+ * @param  alrm         the new alarm value to be updated in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	struct rtc_time alarm_tm, now_tm;
+	unsigned long now, time;
+	int ret;
+
+	now = __raw_readl(ioaddr + SRTC_LPSCMR);
+	rtc_time_to_tm(now, &now_tm);
+
+	alarm_tm.tm_year = now_tm.tm_year;
+	alarm_tm.tm_mon = now_tm.tm_mon;
+	alarm_tm.tm_mday = now_tm.tm_mday;
+
+	alarm_tm.tm_hour = alrm->tm_hour;
+	alarm_tm.tm_min = alrm->tm_min;
+	alarm_tm.tm_sec = alrm->tm_sec;
+
+	rtc_tm_to_time(&now_tm, &now);
+	rtc_tm_to_time(&alarm_tm, &time);
+
+	if (time < now) {
+		time += 60 * 60 * 24;
+		rtc_time_to_tm(time, &alarm_tm);
+	}
+	ret = rtc_tm_to_time(&alarm_tm, &time);
+
+	__raw_writel(time, ioaddr + SRTC_LPSAR);
+
+	/* clear alarm interrupt status bit */
+	__raw_writel(SRTC_LPSR_ALP, ioaddr + SRTC_LPSR);
+
+	return ret;
+}
+
+/*!
+ * This function is the RTC interrupt service routine.
+ *
+ * @param  irq          RTC IRQ number
+ * @param  dev_id       device ID which is not used
+ *
+ * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file.
+ */
+static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
+{
+	struct platform_device *pdev = dev_id;
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	u32 lp_status, lp_cr;
+	u32 events = 0;
+
+	lp_status = __raw_readl(ioaddr + SRTC_LPSR);
+	lp_cr = __raw_readl(ioaddr + SRTC_LPCR);
+
+	/* update irq data & counter */
+	if (lp_status & SRTC_LPSR_ALP) {
+		if (lp_cr & SRTC_LPCR_ALP)
+			events |= (RTC_AF | RTC_IRQF);
+
+		/* disable further lp alarm interrupts */
+		lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+	}
+
+	/* Update interrupt enables */
+	__raw_writel(lp_cr, ioaddr + SRTC_LPCR);
+
+	/* If no interrupts are enabled, turn off interrupts in kernel */
+	if (((lp_cr & SRTC_LPCR_ALL_INT_EN) == 0) && (pdata->irq_enable)) {
+		disable_irq_nosync(pdata->irq);
+		pdata->irq_enable = false;
+	}
+
+	/* clear interrupt status */
+	__raw_writel(lp_status, ioaddr + SRTC_LPSR);
+
+	rtc_write_sync_lp(ioaddr);
+	rtc_update_irq(pdata->rtc, 1, events);
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function is used to open the RTC driver.
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_open(struct device *dev)
+{
+	if (test_and_set_bit(1, &rtc_status))
+		return -EBUSY;
+	return 0;
+}
+
+/*!
+ * clear all interrupts and release the IRQ
+ */
+static void mxc_rtc_release(struct device *dev)
+{
+	rtc_status = 0;
+}
+
+/*!
+ * This function is used to support some ioctl calls directly.
+ * Other ioctl calls are supported indirectly through the
+ * arm/common/rtctime.c file.
+ *
+ * @param  cmd          ioctl command as defined in include/linux/rtc.h
+ * @param  arg          value for the ioctl command
+ *
+ * @return  0 if successful or negative value otherwise.
+ */
+static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd,
+			 unsigned long arg)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	u64 time_47bit;
+	int retVal;
+
+	switch (cmd) {
+	case RTC_READ_TIME_47BIT:
+		time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 |
+			((u64) __raw_readl(ioaddr + SRTC_LPSCLR)));
+		time_47bit >>= SRTC_LPSCLR_LLPSC_LSH;
+
+		if (arg && copy_to_user((u64 *) arg, &time_47bit, sizeof(u64)))
+			return -EFAULT;
+
+		return 0;
+
+	/* This IOCTL to be used by processes to be notified of time changes */
+	case RTC_WAIT_TIME_SET:
+
+		/* don't block without releasing mutex first */
+		mutex_unlock(&pdata->rtc->ops_lock);
+
+		/* sleep until awakened by SRTC driver when LPSCMR is changed */
+		wait_for_completion(&srtc_completion);
+
+		/* relock mutex because rtc_dev_ioctl will unlock again */
+		retVal = mutex_lock_interruptible(&pdata->rtc->ops_lock);
+
+		/* copy the new time difference = new time - previous time
+		  * to the user param. The difference is a signed value */
+		if (arg && copy_to_user((int64_t *) arg, &time_diff,
+			sizeof(int64_t)))
+			return -EFAULT;
+
+		return retVal;
+
+	}
+
+	return -ENOIOCTLCMD;
+}
+
+/*!
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param  tm           contains the RTC time value upon return
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	rtc_time_to_tm(__raw_readl(ioaddr + SRTC_LPSCMR), tm);
+	return 0;
+}
+
+/*!
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param  tm           the time value to be set in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	unsigned long time;
+	u64 old_time_47bit, new_time_47bit;
+	int ret;
+	ret = rtc_tm_to_time(tm, &time);
+	if (ret != 0)
+		return ret;
+
+	old_time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 |
+			((u64) __raw_readl(ioaddr + SRTC_LPSCLR)));
+	old_time_47bit >>= SRTC_LPSCLR_LLPSC_LSH;
+
+	__raw_writel(time, ioaddr + SRTC_LPSCMR);
+	rtc_write_sync_lp(ioaddr);
+
+	new_time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 |
+			((u64) __raw_readl(ioaddr + SRTC_LPSCLR)));
+	new_time_47bit >>= SRTC_LPSCLR_LLPSC_LSH;
+
+	/* update the difference between previous time and new time */
+	time_diff = new_time_47bit - old_time_47bit;
+
+	/* signal all waiting threads that time changed */
+	complete_all(&srtc_completion);
+
+	/* allow signalled threads to handle the time change notification */
+	schedule();
+
+	/* reinitialize completion variable */
+	INIT_COMPLETION(srtc_completion);
+
+	return 0;
+}
+
+/*!
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param  alrm         contains the RTC alarm value upon return
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	rtc_time_to_tm(__raw_readl(ioaddr + SRTC_LPSAR), &alrm->time);
+	alrm->pending =
+	    ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP) != 0) ? 1 : 0;
+
+	return 0;
+}
+
+/*!
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param  alrm         the alarm value to be set in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	unsigned long lock_flags = 0;
+	u32 lp_cr;
+	int ret;
+
+	if (rtc_valid_tm(&alrm->time)) {
+		if (alrm->time.tm_sec > 59 ||
+		    alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) {
+			return -EINVAL;
+		}
+	}
+
+	spin_lock_irqsave(&rtc_lock, lock_flags);
+	lp_cr = __raw_readl(ioaddr + SRTC_LPCR);
+
+	ret = rtc_update_alarm(dev, &alrm->time);
+	if (ret)
+		goto out;
+
+	if (alrm->enabled)
+		lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+	else
+		lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+
+	if (lp_cr & SRTC_LPCR_ALL_INT_EN) {
+		if (!pdata->irq_enable) {
+			enable_irq(pdata->irq);
+			pdata->irq_enable = true;
+		}
+	} else {
+		if (pdata->irq_enable) {
+			disable_irq(pdata->irq);
+			pdata->irq_enable = false;
+		}
+	}
+
+	__raw_writel(lp_cr, ioaddr + SRTC_LPCR);
+
+out:
+	rtc_write_sync_lp(ioaddr);
+	spin_unlock_irqrestore(&rtc_lock, lock_flags);
+	return ret;
+}
+
+/*!
+ * This function is used to provide the content for the /proc/driver/rtc
+ * file.
+ *
+ * @param  seq  buffer to hold the information that the driver wants to write
+ *
+ * @return  The number of bytes written into the rtc file.
+ */
+static int mxc_rtc_proc(struct device *dev, struct seq_file *seq)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	seq_printf(seq, "alarm_IRQ\t: %s\n",
+		   (((__raw_readl(ioaddr + SRTC_LPCR)) & SRTC_LPCR_ALP) !=
+		    0) ? "yes" : "no");
+
+	return 0;
+}
+
+static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	u32 lp_cr;
+	unsigned long lock_flags = 0;
+
+	spin_lock_irqsave(&rtc_lock, lock_flags);
+
+	if (enable) {
+		if (!pdata->irq_enable) {
+			enable_irq(pdata->irq);
+			pdata->irq_enable = true;
+		}
+		lp_cr = __raw_readl(ioaddr + SRTC_LPCR);
+		lp_cr |= SRTC_LPCR_ALP | SRTC_LPCR_WAE;
+		__raw_writel(lp_cr, ioaddr + SRTC_LPCR);
+	} else {
+		lp_cr = __raw_readl(ioaddr + SRTC_LPCR);
+		lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+		if (((lp_cr & SRTC_LPCR_ALL_INT_EN) == 0)
+		    && (pdata->irq_enable)) {
+			disable_irq(pdata->irq);
+			pdata->irq_enable = false;
+		}
+		__raw_writel(lp_cr, ioaddr + SRTC_LPCR);
+	}
+
+	rtc_write_sync_lp(ioaddr);
+	spin_unlock_irqrestore(&rtc_lock, lock_flags);
+	return 0;
+}
+
+/*!
+ * The RTC driver structure
+ */
+static struct rtc_class_ops mxc_rtc_ops = {
+	.open = mxc_rtc_open,
+	.release = mxc_rtc_release,
+	.ioctl = mxc_rtc_ioctl,
+	.read_time = mxc_rtc_read_time,
+	.set_time = mxc_rtc_set_time,
+	.read_alarm = mxc_rtc_read_alarm,
+	.set_alarm = mxc_rtc_set_alarm,
+	.proc = mxc_rtc_proc,
+	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
+};
+
+/*! MXC RTC Power management control */
+static int mxc_rtc_probe(struct platform_device *pdev)
+{
+	struct clk *clk;
+	struct timespec tv;
+	struct resource *res;
+	struct rtc_device *rtc;
+	struct rtc_drv_data *pdata = NULL;
+	void __iomem *ioaddr;
+	int ret = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	pdata->clk = clk_get(&pdev->dev, "rtc_clk");
+	clk_enable(pdata->clk);
+	pdata->baseaddr = res->start;
+	pdata->ioaddr = ioremap(pdata->baseaddr, 0x40);
+	ioaddr = pdata->ioaddr;
+
+	/* Configure and enable the RTC */
+	pdata->irq = platform_get_irq(pdev, 0);
+	if (pdata->irq >= 0) {
+		if (request_irq(pdata->irq, mxc_rtc_interrupt, IRQF_SHARED,
+				pdev->name, pdev) < 0) {
+			dev_warn(&pdev->dev, "interrupt not available.\n");
+			pdata->irq = -1;
+		} else {
+			disable_irq(pdata->irq);
+			pdata->irq_enable = false;
+		}
+	}
+
+	clk = clk_get(&pdev->dev, "rtc_clk");
+	if (clk_get_rate(clk) != 32768) {
+		printk(KERN_ALERT "rtc clock is not valid");
+		ret = -EINVAL;
+		clk_put(clk);
+		goto err_out;
+	}
+	clk_put(clk);
+
+	/* initialize glitch detect */
+	__raw_writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
+	udelay(100);
+
+	/* clear lp interrupt status */
+	__raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+	udelay(100);
+
+	/* move out of init state */
+	__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NSA),
+		     ioaddr + SRTC_LPCR);
+
+	udelay(100);
+
+	while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_IES) == 0)
+		;
+
+	/* move out of non-valid state */
+	__raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
+		      SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
+
+	udelay(100);
+
+	while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_NVES) == 0)
+		;
+
+	__raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+	udelay(100);
+
+	platform_set_drvdata(pdev, pdata);
+
+	rtc = rtc_device_register(pdev->name, &pdev->dev,
+				  &mxc_rtc_ops, THIS_MODULE);
+	if (IS_ERR(rtc)) {
+		platform_set_drvdata(pdev, NULL);
+		ret = PTR_ERR(rtc);
+		goto err_out;
+	}
+
+	pdata->rtc = rtc;
+
+	tv.tv_nsec = 0;
+	tv.tv_sec = __raw_readl(ioaddr + SRTC_LPSCMR);
+
+	/* By default, devices should wakeup if they can */
+	/* So srtc is set as "should wakeup" as it can */
+	device_init_wakeup(&pdev->dev, 1);
+
+	return ret;
+
+err_out:
+	clk_disable(pdata->clk);
+	iounmap(ioaddr);
+	if (pdata->irq >= 0)
+		free_irq(pdata->irq, pdev);
+	kfree(pdata);
+	return ret;
+}
+
+static int __exit mxc_rtc_remove(struct platform_device *pdev)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+	rtc_device_unregister(pdata->rtc);
+	if (pdata->irq >= 0)
+		free_irq(pdata->irq, pdev);
+
+	clk_disable(pdata->clk);
+	clk_put(pdata->clk);
+	kfree(pdata);
+	return 0;
+}
+
+/*!
+ * This function is called to save the system time delta relative to
+ * the MXC RTC when enterring a low power state. This time delta is
+ * then used on resume to adjust the system time to account for time
+ * loss while suspended.
+ *
+ * @param   pdev  not used
+ * @param   state Power state to enter.
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+	if (device_may_wakeup(&pdev->dev)) {
+		enable_irq_wake(pdata->irq);
+	} else {
+		if (pdata->irq_enable)
+			disable_irq(pdata->irq);
+	}
+
+	return 0;
+}
+
+/*!
+ * This function is called to correct the system time based on the
+ * current MXC RTC time relative to the time delta saved during
+ * suspend.
+ *
+ * @param   pdev  not used
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_rtc_resume(struct platform_device *pdev)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+	if (device_may_wakeup(&pdev->dev)) {
+		disable_irq_wake(pdata->irq);
+	} else {
+		if (pdata->irq_enable)
+			enable_irq(pdata->irq);
+	}
+
+	return 0;
+}
+
+/*!
+ * Contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxc_rtc_driver = {
+	.driver = {
+		   .name = "mxc_rtc",
+		   },
+	.probe = mxc_rtc_probe,
+	.remove = __exit_p(mxc_rtc_remove),
+	.suspend = mxc_rtc_suspend,
+	.resume = mxc_rtc_resume,
+};
+
+/*!
+ * This function creates the /proc/driver/rtc file and registers the device RTC
+ * in the /dev/misc directory. It also reads the RTC value from external source
+ * and setup the internal RTC properly.
+ *
+ * @return  -1 if RTC is failed to initialize; 0 is successful.
+ */
+static int __init mxc_rtc_init(void)
+{
+	return platform_driver_register(&mxc_rtc_driver);
+}
+
+/*!
+ * This function removes the /proc/driver/rtc file and un-registers the
+ * device RTC from the /dev/misc directory.
+ */
+static void __exit mxc_rtc_exit(void)
+{
+	platform_driver_unregister(&mxc_rtc_driver);
+
+}
+
+module_init(mxc_rtc_init);
+module_exit(mxc_rtc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Realtime Clock Driver (RTC)");
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 23a447373c5..fbfed8cbe67 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -452,6 +452,31 @@ config USB_GOKU
 	   dynamically linked module called "goku_udc" and to force all
 	   gadget drivers to also be dynamically linked.
 
+config USB_GADGET_ARC
+	tristate "Freescale USB Device Controller"
+	depends on ARCH_MXC || ARCH_STMP3XXX || ARCH_MXS
+	select USB_GADGET_DUALSPEED
+	select USB_OTG_UTILS
+	help
+	   Some Freescale processors have a USBOTG controller,
+	   which supports device mode.
+
+	   Say "y" to link the driver statically, or "m" to build a
+	   dynamically linked module called "arc_udc" and force all
+	   gadget drivers to also be dynamically linked.
+
+config USB_STATIC_IRAM_PPH
+	bool "Apply static IRAM patch"
+	depends on USB_GADGET_ARC && (ARCH_MX37 || ARCH_MX3 || ARCH_MX25 || ARCH_MX51)
+	help
+	   Apply static IRAM patch to peripheral driver.
+
+config USB_ARC
+	tristate
+	depends on USB_GADGET_ARC
+	default USB_GADGET
+	select USB_GADGET_SELECTED
+
 config USB_LANGWELL
 	tristate "Intel Langwell USB Device Controller"
 	depends on PCI
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index b54ac619089..dc9a7e3aadf 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_USB_PXA_U2O)	+= mv_udc.o
 mv_udc-y			:= mv_udc_core.o
 obj-$(CONFIG_USB_CI13XXX_MSM)	+= ci13xxx_msm.o
 obj-$(CONFIG_USB_FUSB300)	+= fusb300_udc.o
+obj-$(CONFIG_USB_ARC)		+= arcotg_udc.o
 
 #
 # USB gadget drivers
diff --git a/drivers/usb/gadget/arcotg_udc.c b/drivers/usb/gadget/arcotg_udc.c
new file mode 100644
index 00000000000..bf09184e83d
--- /dev/null
+++ b/drivers/usb/gadget/arcotg_udc.c
@@ -0,0 +1,3316 @@
+/*
+ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#undef VERBOSE
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/workqueue.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/mm.h>
+#include <linux/jiffies.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/dmapool.h>
+
+#include <asm/processor.h>
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+#include <asm/dma.h>
+#include <asm/cacheflush.h>
+#include <asm/mach-types.h>
+
+#include "arcotg_udc.h"
+#include <mach/arc_otg.h>
+#include <mach/iram.h>
+
+#define	DRIVER_DESC	"ARC USBOTG Device Controller driver"
+#define	DRIVER_AUTHOR	"Freescale Semiconductor"
+#define	DRIVER_VERSION	"1 August 2005"
+
+#ifdef CONFIG_PPC_MPC512x
+#define BIG_ENDIAN_DESC
+#endif
+
+#ifdef BIG_ENDIAN_DESC
+#define cpu_to_hc32(x)	(x)
+#define hc32_to_cpu(x)	(x)
+#else
+#define cpu_to_hc32(x)	cpu_to_le32((x))
+#define hc32_to_cpu(x)	le32_to_cpu((x))
+#endif
+
+#define	DMA_ADDR_INVALID	(~(dma_addr_t)0)
+DEFINE_MUTEX(udc_resume_mutex);
+extern void usb_debounce_id_vbus(void);
+static const char driver_name[] = "fsl-usb2-udc";
+static const char driver_desc[] = DRIVER_DESC;
+
+volatile static struct usb_dr_device *dr_regs;
+volatile static struct usb_sys_interface *usb_sys_regs;
+
+/* it is initialized in probe()  */
+static struct fsl_udc *udc_controller;
+
+#ifdef POSTPONE_FREE_LAST_DTD
+static struct ep_td_struct *last_free_td;
+#endif
+static const struct usb_endpoint_descriptor
+fsl_ep0_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+	.bEndpointAddress =	0,
+	.bmAttributes =		USB_ENDPOINT_XFER_CONTROL,
+	.wMaxPacketSize =	USB_MAX_CTRL_PAYLOAD,
+};
+static const size_t g_iram_size = IRAM_TD_PPH_SIZE;
+static unsigned long g_iram_base;
+static __iomem void *g_iram_addr;
+
+typedef int (*dev_sus)(struct device *dev, pm_message_t state);
+typedef int (*dev_res) (struct device *dev);
+static int udc_suspend(struct fsl_udc *udc);
+static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state);
+static int fsl_udc_resume(struct platform_device *pdev);
+static void fsl_ep_fifo_flush(struct usb_ep *_ep);
+
+#ifdef CONFIG_USB_OTG
+/* Get platform resource from OTG driver */
+extern struct resource *otg_get_resources(void);
+#endif
+
+extern void fsl_platform_set_test_mode(struct fsl_usb2_platform_data *pdata, enum usb_test_mode mode);
+
+#ifdef CONFIG_WORKAROUND_ARCUSB_REG_RW
+static void safe_writel(u32 val32, volatile u32 *addr)
+{
+	__asm__ ("swp %0, %0, [%1]" : : "r"(val32), "r"(addr));
+}
+#endif
+
+#ifdef CONFIG_PPC32
+#define fsl_readl(addr)		in_le32((addr))
+#define fsl_writel(addr, val32) out_le32((val32), (addr))
+#elif defined (CONFIG_WORKAROUND_ARCUSB_REG_RW)
+#define fsl_readl(addr)		readl((addr))
+#define fsl_writel(val32, addr) safe_writel(val32, addr)
+#else
+#define fsl_readl(addr)		readl((addr))
+#define fsl_writel(addr, val32) writel((addr), (val32))
+#endif
+
+/********************************************************************
+ *	Internal Used Function
+********************************************************************/
+
+#ifdef DUMP_QUEUES
+static void dump_ep_queue(struct fsl_ep *ep)
+{
+	int ep_index;
+	struct fsl_req *req;
+	struct ep_td_struct *dtd;
+
+	if (list_empty(&ep->queue)) {
+		pr_debug("udc: empty\n");
+		return;
+	}
+
+	ep_index = ep_index(ep) * 2 + ep_is_in(ep);
+	pr_debug("udc: ep=0x%p  index=%d\n", ep, ep_index);
+
+	list_for_each_entry(req, &ep->queue, queue) {
+		pr_debug("udc: req=0x%p  dTD count=%d\n", req, req->dtd_count);
+		pr_debug("udc: dTD head=0x%p  tail=0x%p\n", req->head,
+			 req->tail);
+
+		dtd = req->head;
+
+		while (dtd) {
+			if (le32_to_cpu(dtd->next_td_ptr) & DTD_NEXT_TERMINATE)
+				break;	/* end of dTD list */
+
+			dtd = dtd->next_td_virt;
+		}
+	}
+}
+#else
+static inline void dump_ep_queue(struct fsl_ep *ep)
+{
+}
+#endif
+
+#if (defined CONFIG_ARCH_MX35 || defined CONFIG_ARCH_MX25)
+/*
+ * The Phy at MX35 and MX25 have bugs, it must disable, and re-eable phy
+ * if the phy clock is disabled before
+ */
+static void reset_phy(void)
+{
+	u32 phyctrl;
+	phyctrl = fsl_readl(&dr_regs->phyctrl1);
+	phyctrl &= ~PHY_CTRL0_USBEN;
+	fsl_writel(phyctrl, &dr_regs->phyctrl1);
+
+	phyctrl = fsl_readl(&dr_regs->phyctrl1);
+	phyctrl |= PHY_CTRL0_USBEN;
+	fsl_writel(phyctrl, &dr_regs->phyctrl1);
+}
+#else
+static void reset_phy(void){; }
+#endif
+/*-----------------------------------------------------------------
+ * done() - retire a request; caller blocked irqs
+ * @status : request status to be set, only works when
+ *	request is still in progress.
+ *--------------------------------------------------------------*/
+static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
+{
+	struct fsl_udc *udc = NULL;
+	unsigned char stopped = ep->stopped;
+	struct ep_td_struct *curr_td, *next_td;
+	int j;
+
+	udc = (struct fsl_udc *)ep->udc;
+	/* Removed the req from fsl_ep->queue */
+	list_del_init(&req->queue);
+
+	/* req.status should be set as -EINPROGRESS in ep_queue() */
+	if (req->req.status == -EINPROGRESS)
+		req->req.status = status;
+	else
+		status = req->req.status;
+
+	/* Free dtd for the request */
+	next_td = req->head;
+	for (j = 0; j < req->dtd_count; j++) {
+		curr_td = next_td;
+		if (j != req->dtd_count - 1) {
+			next_td = curr_td->next_td_virt;
+#ifdef POSTPONE_FREE_LAST_DTD
+			dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
+		} else {
+			if (last_free_td != NULL)
+				dma_pool_free(udc->td_pool, last_free_td,
+						last_free_td->td_dma);
+			last_free_td = curr_td;
+		}
+#else
+		}
+
+		dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
+#endif
+	}
+
+	if (USE_MSC_WR(req->req.length)) {
+		req->req.dma -= 1;
+		memmove(req->req.buf, req->req.buf + 1, MSC_BULK_CB_WRAP_LEN);
+	}
+
+	if (req->mapped) {
+		dma_unmap_single(ep->udc->gadget.dev.parent,
+			req->req.dma, req->req.length,
+			ep_is_in(ep)
+				? DMA_TO_DEVICE
+				: DMA_FROM_DEVICE);
+		req->req.dma = DMA_ADDR_INVALID;
+		req->mapped = 0;
+	} else
+		dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
+			req->req.dma, req->req.length,
+			ep_is_in(ep)
+				? DMA_TO_DEVICE
+				: DMA_FROM_DEVICE);
+
+	if (status && (status != -ESHUTDOWN))
+		VDBG("complete %s req %p stat %d len %u/%u",
+			ep->ep.name, &req->req, status,
+			req->req.actual, req->req.length);
+
+	ep->stopped = 1;
+
+	spin_unlock(&ep->udc->lock);
+	/* complete() is from gadget layer,
+	 * eg fsg->bulk_in_complete() */
+	if (req->req.complete)
+		req->req.complete(&ep->ep, &req->req);
+
+	spin_lock(&ep->udc->lock);
+	ep->stopped = stopped;
+}
+
+/*-----------------------------------------------------------------
+ * nuke(): delete all requests related to this ep
+ * called with spinlock held
+ *--------------------------------------------------------------*/
+static void nuke(struct fsl_ep *ep, int status)
+{
+	ep->stopped = 1;
+	/*
+	 * At udc stop mode, the clock is already off
+	 * So flush fifo, should be done at clock on mode.
+	 */
+	if (!ep->udc->stopped)
+		fsl_ep_fifo_flush(&ep->ep);
+
+	/* Whether this eq has request linked */
+	while (!list_empty(&ep->queue)) {
+		struct fsl_req *req = NULL;
+
+		req = list_entry(ep->queue.next, struct fsl_req, queue);
+		done(ep, req, status);
+	}
+	dump_ep_queue(ep);
+}
+
+/*------------------------------------------------------------------
+	Internal Hardware related function
+ ------------------------------------------------------------------*/
+static inline void
+dr_wake_up_enable(struct fsl_udc *udc, bool enable)
+{
+	struct fsl_usb2_platform_data *pdata;
+	pdata = udc->pdata;
+
+	if (pdata && pdata->wake_up_enable)
+		pdata->wake_up_enable(pdata, enable);
+}
+
+static inline void dr_clk_gate(bool on)
+{
+	struct fsl_usb2_platform_data *pdata = udc_controller->pdata;
+
+	if (!pdata || !pdata->usb_clock_for_pm)
+		return;
+	pdata->usb_clock_for_pm(on);
+	if (on)
+		reset_phy();
+}
+
+static void dr_phy_low_power_mode(struct fsl_udc *udc, bool enable)
+{
+	struct fsl_usb2_platform_data *pdata = udc->pdata;
+	u32 portsc;
+
+	if (pdata && pdata->phy_lowpower_suspend) {
+		pdata->phy_lowpower_suspend(pdata, enable);
+	} else {
+		if (enable) {
+			portsc = fsl_readl(&dr_regs->portsc1);
+			portsc |= PORTSCX_PHY_LOW_POWER_SPD;
+			fsl_writel(portsc, &dr_regs->portsc1);
+		} else {
+			portsc = fsl_readl(&dr_regs->portsc1);
+			portsc &= ~PORTSCX_PHY_LOW_POWER_SPD;
+			fsl_writel(portsc, &dr_regs->portsc1);
+		}
+	}
+	pdata->lowpower = enable;
+}
+
+
+/* workaroud for some boards, maybe there is a large capacitor between the ground and the Vbus
+ * that will cause the vbus dropping very slowly when device is detached,
+ * may cost 2-3 seconds to below 0.8V */
+static void udc_wait_b_session_low(void)
+{
+	u32 temp;
+	u32 wait = 5000/jiffies_to_msecs(1); /* max wait time is 5000 ms */
+	/* if we are in host mode, don't need to care the B session */
+	if ((fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID) == 0)
+		return;
+	/* if the udc is dettached , there will be a suspend irq */
+	if (udc_controller->usb_state != USB_STATE_SUSPENDED)
+		return;
+	temp = fsl_readl(&dr_regs->otgsc);
+	temp &= ~OTGSC_B_SESSION_VALID_IRQ_EN;
+	fsl_writel(temp, &dr_regs->otgsc);
+
+	do {
+		if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_B_SESSION_VALID))
+			break;
+		msleep(jiffies_to_msecs(1));
+		wait -= 1;
+	} while (wait);
+	if (!wait)
+		printk(KERN_ERR "ERROR!!!!!: the vbus can not be lower \
+				then 0.8V for 5 seconds, Pls Check your HW design\n");
+	temp = fsl_readl(&dr_regs->otgsc);
+	temp |= OTGSC_B_SESSION_VALID_IRQ_EN;
+	fsl_writel(temp, &dr_regs->otgsc);
+}
+
+static int dr_controller_setup(struct fsl_udc *udc)
+{
+	unsigned int tmp = 0, portctrl = 0;
+	unsigned int __attribute((unused)) ctrl = 0;
+	unsigned long timeout;
+	struct fsl_usb2_platform_data *pdata;
+
+#define FSL_UDC_RESET_TIMEOUT 1000
+
+	/* before here, make sure dr_regs has been initialized */
+	if (!udc)
+		return -EINVAL;
+	pdata = udc->pdata;
+
+	/* Stop and reset the usb controller */
+	tmp = fsl_readl(&dr_regs->usbcmd);
+	tmp &= ~USB_CMD_RUN_STOP;
+	fsl_writel(tmp, &dr_regs->usbcmd);
+
+	tmp = fsl_readl(&dr_regs->usbcmd);
+	tmp |= USB_CMD_CTRL_RESET;
+	fsl_writel(tmp, &dr_regs->usbcmd);
+
+	/* Wait for reset to complete */
+	timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
+	while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
+		if (time_after(jiffies, timeout)) {
+			ERR("udc reset timeout! \n");
+			return -ETIMEDOUT;
+		}
+		cpu_relax();
+	}
+
+	/* Set the controller as device mode */
+	tmp = fsl_readl(&dr_regs->usbmode);
+	tmp &= ~USB_MODE_CTRL_MODE_MASK;	/* clear mode bits */
+	tmp |= USB_MODE_CTRL_MODE_DEVICE;
+	/* Disable Setup Lockout */
+	tmp |= USB_MODE_SETUP_LOCK_OFF;
+	if (pdata->es)
+		tmp |= USB_MODE_ES;
+	fsl_writel(tmp, &dr_regs->usbmode);
+
+	fsl_platform_set_device_mode(pdata);
+
+	/* Clear the setup status */
+	fsl_writel(0xffffffff, &dr_regs->usbsts);
+
+	tmp = udc->ep_qh_dma;
+	tmp &= USB_EP_LIST_ADDRESS_MASK;
+	fsl_writel(tmp, &dr_regs->endpointlistaddr);
+
+	VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
+		(int)udc->ep_qh, (int)tmp,
+		fsl_readl(&dr_regs->endpointlistaddr));
+
+	/* Config PHY interface */
+	portctrl = fsl_readl(&dr_regs->portsc1);
+	portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
+	switch (udc->phy_mode) {
+	case FSL_USB2_PHY_ULPI:
+		portctrl |= PORTSCX_PTS_ULPI;
+		break;
+	case FSL_USB2_PHY_UTMI_WIDE:
+		portctrl |= PORTSCX_PTW_16BIT;
+		/* fall through */
+	case FSL_USB2_PHY_UTMI:
+		portctrl |= PORTSCX_PTS_UTMI;
+		break;
+	case FSL_USB2_PHY_SERIAL:
+		portctrl |= PORTSCX_PTS_FSLS;
+		break;
+	default:
+		return -EINVAL;
+	}
+	fsl_writel(portctrl, &dr_regs->portsc1);
+
+	if (pdata->change_ahb_burst) {
+		/* if usb should not work in default INCRx mode */
+		tmp = fsl_readl(&dr_regs->sbuscfg);
+		tmp = (tmp & ~0x07) | pdata->ahb_burst_mode;
+		fsl_writel(tmp, &dr_regs->sbuscfg);
+	}
+
+	if (pdata->have_sysif_regs) {
+		/* Config control enable i/o output, cpu endian register */
+		ctrl = __raw_readl(&usb_sys_regs->control);
+		ctrl |= USB_CTRL_IOENB;
+		__raw_writel(ctrl, &usb_sys_regs->control);
+	}
+
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+	/* Turn on cache snooping hardware, since some PowerPC platforms
+	 * wholly rely on hardware to deal with cache coherent. */
+
+	if (pdata->have_sysif_regs) {
+		/* Setup Snooping for all the 4GB space */
+		tmp = SNOOP_SIZE_2GB;	/* starts from 0x0, size 2G */
+		__raw_writel(tmp, &usb_sys_regs->snoop1);
+		tmp |= 0x80000000;	/* starts from 0x8000000, size 2G */
+		__raw_writel(tmp, &usb_sys_regs->snoop2);
+	}
+#endif
+
+	return 0;
+}
+
+/* Enable DR irq and set controller to run state */
+static void dr_controller_run(struct fsl_udc *udc)
+{
+	u32 temp;
+
+	fsl_platform_pullup_enable(udc->pdata);
+
+	/* Enable DR irq reg */
+	temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
+		| USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
+		| USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
+
+	fsl_writel(temp, &dr_regs->usbintr);
+
+	/* enable BSV irq */
+	temp = fsl_readl(&dr_regs->otgsc);
+	temp |= OTGSC_B_SESSION_VALID_IRQ_EN;
+	fsl_writel(temp, &dr_regs->otgsc);
+
+	/* If vbus not on and used low power mode */
+	if (!(temp & OTGSC_B_SESSION_VALID)) {
+		/* Set stopped before low power mode */
+		udc->stopped = 1;
+		/* enable wake up */
+		dr_wake_up_enable(udc, true);
+		/* enter lower power mode */
+		dr_phy_low_power_mode(udc, true);
+		printk(KERN_DEBUG "%s: udc enter low power mode \n", __func__);
+	} else {
+#ifdef CONFIG_ARCH_MX37
+		/*
+		 add some delay for USB timing issue. USB may be
+		 recognize as FS device
+		 during USB gadget remote wake up function
+		*/
+		mdelay(100);
+#endif
+		/* Clear stopped bit */
+		udc->stopped = 0;
+
+		/* The usb line has already been connected to pc */
+		temp = fsl_readl(&dr_regs->usbcmd);
+		temp |= USB_CMD_RUN_STOP;
+		fsl_writel(temp, &dr_regs->usbcmd);
+		printk(KERN_DEBUG "%s: udc out low power mode\n", __func__);
+	}
+
+	return;
+}
+
+static void dr_controller_stop(struct fsl_udc *udc)
+{
+	unsigned int tmp;
+
+	pr_debug("%s\n", __func__);
+
+	/* if we're in OTG mode, and the Host is currently using the port,
+	 * stop now and don't rip the controller out from under the
+	 * ehci driver
+	 */
+	if (udc->gadget.is_otg) {
+		if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
+			pr_debug("udc: Leaving early\n");
+			return;
+		}
+	}
+
+	/* disable all INTR */
+	fsl_writel(0, &dr_regs->usbintr);
+
+	/* disable wake up */
+	dr_wake_up_enable(udc, false);
+	/* disable BSV irq */
+	tmp = fsl_readl(&dr_regs->otgsc);
+	tmp &= ~OTGSC_B_SESSION_VALID_IRQ_EN;
+	fsl_writel(tmp, &dr_regs->otgsc);
+
+	/* Set stopped bit for isr */
+	udc->stopped = 1;
+
+	/* disable IO output */
+/*	usb_sys_regs->control = 0; */
+
+	fsl_platform_pullup_disable(udc->pdata);
+
+	/* set controller to Stop */
+	tmp = fsl_readl(&dr_regs->usbcmd);
+	tmp &= ~USB_CMD_RUN_STOP;
+	fsl_writel(tmp, &dr_regs->usbcmd);
+
+	return;
+}
+
+void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type)
+{
+	unsigned int tmp_epctrl = 0;
+
+	tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (dir) {
+		if (ep_num)
+			tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
+		tmp_epctrl |= EPCTRL_TX_ENABLE;
+		tmp_epctrl |= ((unsigned int)(ep_type)
+				<< EPCTRL_TX_EP_TYPE_SHIFT);
+	} else {
+		if (ep_num)
+			tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
+		tmp_epctrl |= EPCTRL_RX_ENABLE;
+		tmp_epctrl |= ((unsigned int)(ep_type)
+				<< EPCTRL_RX_EP_TYPE_SHIFT);
+	}
+
+	fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
+}
+
+static void
+dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
+{
+	u32 tmp_epctrl = 0;
+
+	tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+
+	if (value) {
+		/* set the stall bit */
+		if (dir)
+			tmp_epctrl |= EPCTRL_TX_EP_STALL;
+		else
+			tmp_epctrl |= EPCTRL_RX_EP_STALL;
+	} else {
+		/* clear the stall bit and reset data toggle */
+		if (dir) {
+			tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
+			tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
+		} else {
+			tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
+			tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
+		}
+	}
+	fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
+}
+
+/* Get stall status of a specific ep
+   Return: 0: not stalled; 1:stalled */
+static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
+{
+	u32 epctrl;
+
+	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (dir)
+		return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
+	else
+		return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
+}
+
+/********************************************************************
+	Internal Structure Build up functions
+********************************************************************/
+
+/*------------------------------------------------------------------
+* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
+ * @zlt: Zero Length Termination Select (1: disable; 0: enable)
+ * @mult: Mult field
+ ------------------------------------------------------------------*/
+static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
+		unsigned char dir, unsigned char ep_type,
+		unsigned int max_pkt_len,
+		unsigned int zlt, unsigned char mult)
+{
+	struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
+	unsigned int tmp = 0;
+
+	/* set the Endpoint Capabilites in QH */
+	switch (ep_type) {
+	case USB_ENDPOINT_XFER_CONTROL:
+		/* Interrupt On Setup (IOS). for control ep  */
+		tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
+			| EP_QUEUE_HEAD_IOS;
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
+			| (mult << EP_QUEUE_HEAD_MULT_POS);
+		break;
+	case USB_ENDPOINT_XFER_BULK:
+	case USB_ENDPOINT_XFER_INT:
+		tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
+		break;
+	default:
+		VDBG("error ep type is %d", ep_type);
+		return;
+	}
+	if (zlt)
+		tmp |= EP_QUEUE_HEAD_ZLT_SEL;
+	p_QH->max_pkt_length = cpu_to_hc32(tmp);
+
+	return;
+}
+
+/* Setup qh structure and ep register for ep0. */
+static void ep0_setup(struct fsl_udc *udc)
+{
+	/* the intialization of an ep includes: fields in QH, Regs,
+	 * fsl_ep struct */
+	struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
+			USB_MAX_CTRL_PAYLOAD, 0, 0);
+	struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
+			USB_MAX_CTRL_PAYLOAD, 0, 0);
+	dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
+	dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
+
+	return;
+
+}
+
+/***********************************************************************
+		Endpoint Management Functions
+***********************************************************************/
+
+/*-------------------------------------------------------------------------
+ * when configurations are set, or when interface settings change
+ * for example the do_set_interface() in gadget layer,
+ * the driver will enable or disable the relevant endpoints
+ * ep0 doesn't use this routine. It is always enabled.
+-------------------------------------------------------------------------*/
+static int fsl_ep_enable(struct usb_ep *_ep,
+		const struct usb_endpoint_descriptor *desc)
+{
+	struct fsl_udc *udc = NULL;
+	struct fsl_ep *ep = NULL;
+	unsigned short max = 0;
+	unsigned char mult = 0, zlt;
+	int retval = -EINVAL;
+	unsigned long flags = 0;
+
+	ep = container_of(_ep, struct fsl_ep, ep);
+
+	pr_debug("udc: %s ep.name=%s\n", __func__, ep->ep.name);
+	/* catch various bogus parameters */
+	if (!_ep || !desc || ep->desc
+			|| (desc->bDescriptorType != USB_DT_ENDPOINT))
+		return -EINVAL;
+
+	udc = ep->udc;
+
+	if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
+		return -ESHUTDOWN;
+
+	max = le16_to_cpu(desc->wMaxPacketSize);
+
+	/* Disable automatic zlp generation.  Driver is reponsible to indicate
+	 * explicitly through req->req.zero.  This is needed to enable multi-td
+	 * request. */
+	zlt = 1;
+
+	/* Assume the max packet size from gadget is always correct */
+	switch (desc->bmAttributes & 0x03) {
+	case USB_ENDPOINT_XFER_CONTROL:
+	case USB_ENDPOINT_XFER_BULK:
+	case USB_ENDPOINT_XFER_INT:
+		/* mult = 0.  Execute N Transactions as demonstrated by
+		 * the USB variable length packet protocol where N is
+		 * computed using the Maximum Packet Length (dQH) and
+		 * the Total Bytes field (dTD) */
+		mult = 0;
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		/* Calculate transactions needed for high bandwidth iso */
+		mult = (unsigned char)(1 + ((max >> 11) & 0x03));
+		max = max & 0x7ff;	/* bit 0~10 */
+		/* 3 transactions at most */
+		if (mult > 3)
+			goto en_done;
+		break;
+	default:
+		goto en_done;
+	}
+
+	spin_lock_irqsave(&udc->lock, flags);
+	ep->ep.maxpacket = max;
+	ep->desc = desc;
+	ep->stopped = 0;
+
+	/* Controller related setup */
+	/* Init EPx Queue Head (Ep Capabilites field in QH
+	 * according to max, zlt, mult) */
+	struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
+			(unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
+					?  USB_SEND : USB_RECV),
+			(unsigned char) (desc->bmAttributes
+					& USB_ENDPOINT_XFERTYPE_MASK),
+			max, zlt, mult);
+
+	/* Init endpoint ctrl register */
+	dr_ep_setup((unsigned char) ep_index(ep),
+			(unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
+					? USB_SEND : USB_RECV),
+			(unsigned char) (desc->bmAttributes
+					& USB_ENDPOINT_XFERTYPE_MASK));
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+	retval = 0;
+
+	VDBG("enabled %s (ep%d%s) maxpacket %d", ep->ep.name,
+			ep->desc->bEndpointAddress & 0x0f,
+			(desc->bEndpointAddress & USB_DIR_IN)
+				? "in" : "out", max);
+en_done:
+	return retval;
+}
+
+/*---------------------------------------------------------------------
+ * @ep : the ep being unconfigured. May not be ep0
+ * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
+*---------------------------------------------------------------------*/
+static int fsl_ep_disable(struct usb_ep *_ep)
+{
+	struct fsl_udc *udc = NULL;
+	struct fsl_ep *ep = NULL;
+	unsigned long flags = 0;
+	u32 epctrl;
+	int ep_num;
+
+	ep = container_of(_ep, struct fsl_ep, ep);
+	if (!_ep || !ep->desc) {
+		VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
+		return -EINVAL;
+	}
+
+	/* disable ep on controller */
+	ep_num = ep_index(ep);
+	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (ep_is_in(ep))
+		epctrl &= ~EPCTRL_TX_ENABLE;
+	else
+		epctrl &= ~EPCTRL_RX_ENABLE;
+	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+
+	udc = (struct fsl_udc *)ep->udc;
+	spin_lock_irqsave(&udc->lock, flags);
+	/* nuke all pending requests (does flush) */
+	nuke(ep, -ESHUTDOWN);
+
+	ep->desc = 0;
+	ep->stopped = 1;
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	VDBG("disabled %s OK", _ep->name);
+	return 0;
+}
+
+/*---------------------------------------------------------------------
+ * allocate a request object used by this endpoint
+ * the main operation is to insert the req->queue to the eq->queue
+ * Returns the request, or null if one could not be allocated
+*---------------------------------------------------------------------*/
+static struct usb_request *
+fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
+{
+	struct fsl_req *req = NULL;
+
+	req = kzalloc(sizeof *req, gfp_flags);
+	if (!req)
+		return NULL;
+
+	req->req.dma = DMA_ADDR_INVALID;
+	pr_debug("udc: req=0x%p   set req.dma=0x%x\n", req, req->req.dma);
+	INIT_LIST_HEAD(&req->queue);
+
+	return &req->req;
+}
+
+static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct fsl_req *req = NULL;
+
+	req = container_of(_req, struct fsl_req, req);
+
+	if (_req)
+		kfree(req);
+}
+
+static void update_qh(struct fsl_req *req)
+{
+	struct fsl_ep *ep = req->ep;
+	int i = ep_index(ep) * 2 + ep_is_in(ep);
+	u32 temp;
+	struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
+
+	/* Write dQH next pointer and terminate bit to 0 */
+	temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
+	if (NEED_IRAM(req->ep)) {
+		/* set next dtd stop bit,ensure only one dtd in this list */
+		req->cur->next_td_ptr |= cpu_to_hc32(DTD_NEXT_TERMINATE);
+		temp = req->cur->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
+	}
+	dQH->next_dtd_ptr = cpu_to_hc32(temp);
+	/* Clear active and halt bit */
+	temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
+			     | EP_QUEUE_HEAD_STATUS_HALT));
+	dQH->size_ioc_int_sts &= temp;
+
+	/* Prime endpoint by writing 1 to ENDPTPRIME */
+	temp = ep_is_in(ep)
+	    ? (1 << (ep_index(ep) + 16))
+	    : (1 << (ep_index(ep)));
+	fsl_writel(temp, &dr_regs->endpointprime);
+}
+
+/*-------------------------------------------------------------------------*/
+static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
+{
+	u32 temp, bitmask, tmp_stat;
+
+	/* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
+	VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
+
+	bitmask = ep_is_in(ep)
+		? (1 << (ep_index(ep) + 16))
+		: (1 << (ep_index(ep)));
+
+	/* check if the pipe is empty */
+	if (!(list_empty(&ep->queue))) {
+		/* Add td to the end */
+		struct fsl_req *lastreq;
+		lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
+		if (NEED_IRAM(ep)) {
+			/* only one dtd in dqh */
+			lastreq->tail->next_td_ptr =
+			    cpu_to_hc32(req->head->td_dma | DTD_NEXT_TERMINATE);
+			goto out;
+		} else {
+			lastreq->tail->next_td_ptr =
+			    cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
+		}
+		/* Read prime bit, if 1 goto done */
+		if (fsl_readl(&dr_regs->endpointprime) & bitmask)
+			goto out;
+		do {
+			/* Set ATDTW bit in USBCMD */
+			temp = fsl_readl(&dr_regs->usbcmd);
+			fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
+
+			/* Read correct status bit */
+			tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
+
+		} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
+
+		/* Write ATDTW bit to 0 */
+		temp = fsl_readl(&dr_regs->usbcmd);
+		fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
+
+		if (tmp_stat)
+			goto out;
+	}
+	update_qh(req);
+out:
+	return 0;
+}
+
+/* Fill in the dTD structure
+ * @req: request that the transfer belongs to
+ * @length: return actually data length of the dTD
+ * @dma: return dma address of the dTD
+ * @is_last: return flag if it is the last dTD of the request
+ * return: pointer to the built dTD */
+static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
+		dma_addr_t *dma, int *is_last)
+{
+	u32 swap_temp;
+	struct ep_td_struct *dtd;
+
+	/* how big will this transfer be? */
+	*length = min(req->req.length - req->req.actual,
+			(unsigned)EP_MAX_LENGTH_TRANSFER);
+	if (NEED_IRAM(req->ep))
+		*length = min(*length, g_iram_size);
+	dtd = dma_pool_alloc(udc_controller->td_pool, GFP_ATOMIC, dma);
+	if (dtd == NULL)
+		return dtd;
+
+	dtd->td_dma = *dma;
+	/* Clear reserved field */
+	swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
+	swap_temp &= ~DTD_RESERVED_FIELDS;
+	dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
+
+	/* Init all of buffer page pointers */
+	swap_temp = (u32) (req->req.dma + req->req.actual);
+	if (NEED_IRAM(req->ep))
+		swap_temp = (u32) (req->req.dma);
+	dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
+	dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
+	dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
+	dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
+	dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
+
+	req->req.actual += *length;
+
+	/* zlp is needed if req->req.zero is set */
+	if (req->req.zero) {
+		if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
+			*is_last = 1;
+		else
+			*is_last = 0;
+	} else if (req->req.length == req->req.actual)
+		*is_last = 1;
+	else
+		*is_last = 0;
+
+	if ((*is_last) == 0)
+		VDBG("multi-dtd request!\n");
+	/* Fill in the transfer size; set active bit */
+	swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
+
+	/* Enable interrupt for the last dtd of a request */
+	if (*is_last && !req->req.no_interrupt)
+		swap_temp |= DTD_IOC;
+	if (NEED_IRAM(req->ep))
+		swap_temp |= DTD_IOC;
+
+	dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
+
+	mb();
+
+	VDBG("length = %d address= 0x%x", *length, (int)*dma);
+
+	return dtd;
+}
+
+/* Generate dtd chain for a request */
+static int fsl_req_to_dtd(struct fsl_req *req)
+{
+	unsigned	count;
+	int		is_last;
+	int		is_first = 1;
+	struct ep_td_struct	*last_dtd = NULL, *dtd;
+	dma_addr_t dma;
+
+	if (NEED_IRAM(req->ep)) {
+		req->oridma = req->req.dma;
+		/* here, replace user buffer to iram buffer */
+		if (ep_is_in(req->ep)) {
+			req->req.dma = req->ep->udc->iram_buffer[1];
+			if ((list_empty(&req->ep->queue))) {
+				/* copy data only when no bulk in transfer is
+				   running */
+				memcpy((char *)req->ep->udc->iram_buffer_v[1],
+				       req->req.buf, min(req->req.length,
+							 g_iram_size));
+			}
+		} else {
+			req->req.dma = req->ep->udc->iram_buffer[0];
+		}
+	}
+
+	if (USE_MSC_WR(req->req.length))
+		req->req.dma += 1;
+
+	do {
+		dtd = fsl_build_dtd(req, &count, &dma, &is_last);
+		if (dtd == NULL)
+			return -ENOMEM;
+
+		if (is_first) {
+			is_first = 0;
+			req->head = dtd;
+		} else {
+			last_dtd->next_td_ptr = cpu_to_hc32(dma);
+			last_dtd->next_td_virt = dtd;
+		}
+		last_dtd = dtd;
+
+		req->dtd_count++;
+	} while (!is_last);
+
+	dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
+	req->cur = req->head;
+	req->tail = dtd;
+
+	return 0;
+}
+
+/* queues (submits) an I/O request to an endpoint */
+static int
+fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
+{
+	struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
+	struct fsl_req *req = container_of(_req, struct fsl_req, req);
+	struct fsl_udc *udc;
+	unsigned long flags;
+	int is_iso = 0;
+
+
+	if (!_ep || !ep->desc) {
+		VDBG("%s, bad ep\n", __func__);
+		return -EINVAL;
+	}
+
+	udc = ep->udc;
+	spin_lock_irqsave(&udc->lock, flags);
+
+	/* catch various bogus parameters */
+	if (!_req || !req->req.buf || (ep_index(ep)
+				      && !list_empty(&req->queue))) {
+		VDBG("%s, bad params\n", __func__);
+		spin_unlock_irqrestore(&udc->lock, flags);
+		return -EINVAL;
+	}
+	if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+		if (req->req.length > ep->ep.maxpacket) {
+			spin_unlock_irqrestore(&udc->lock, flags);
+			return -EMSGSIZE;
+		}
+		is_iso = 1;
+	}
+
+	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
+		spin_unlock_irqrestore(&udc->lock, flags);
+		return -ESHUTDOWN;
+	}
+	req->ep = ep;
+
+	/* map virtual address to hardware */
+	if (req->req.dma == DMA_ADDR_INVALID) {
+		req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
+					req->req.buf,
+					req->req.length, ep_is_in(ep)
+						? DMA_TO_DEVICE
+						: DMA_FROM_DEVICE);
+		req->mapped = 1;
+	} else {
+		dma_sync_single_for_device(ep->udc->gadget.dev.parent,
+					req->req.dma, req->req.length,
+					ep_is_in(ep)
+						? DMA_TO_DEVICE
+						: DMA_FROM_DEVICE);
+		req->mapped = 0;
+	}
+
+	req->req.status = -EINPROGRESS;
+	req->req.actual = 0;
+	req->dtd_count = 0;
+	if (NEED_IRAM(ep)) {
+		req->last_one = 0;
+		req->buffer_offset = 0;
+	}
+
+	/* build dtds and push them to device queue */
+	if (!fsl_req_to_dtd(req)) {
+		fsl_queue_td(ep, req);
+	} else {
+		spin_unlock_irqrestore(&udc->lock, flags);
+		return -ENOMEM;
+	}
+
+	/* irq handler advances the queue */
+	if (req != NULL)
+		list_add_tail(&req->queue, &ep->queue);
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	return 0;
+}
+
+/* dequeues (cancels, unlinks) an I/O request from an endpoint */
+static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
+	struct fsl_req *req;
+	unsigned long flags;
+	int ep_num, stopped, ret = 0;
+	struct fsl_udc *udc = NULL;
+	u32 epctrl;
+
+	if (!_ep || !_req)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ep->udc->lock, flags);
+	stopped = ep->stopped;
+	udc = ep->udc;
+	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
+		spin_unlock_irqrestore(&ep->udc->lock, flags);
+		return -ESHUTDOWN;
+	}
+
+	/* Stop the ep before we deal with the queue */
+	ep->stopped = 1;
+	ep_num = ep_index(ep);
+	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (ep_is_in(ep))
+		epctrl &= ~EPCTRL_TX_ENABLE;
+	else
+		epctrl &= ~EPCTRL_RX_ENABLE;
+	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+
+	/* make sure it's actually queued on this endpoint */
+	list_for_each_entry(req, &ep->queue, queue) {
+		if (&req->req == _req)
+			break;
+	}
+	if (&req->req != _req) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* The request is in progress, or completed but not dequeued */
+	if (ep->queue.next == &req->queue) {
+		_req->status = -ECONNRESET;
+		fsl_ep_fifo_flush(_ep);	/* flush current transfer */
+
+		/* The request isn't the last request in this ep queue */
+		if (req->queue.next != &ep->queue) {
+			struct ep_queue_head *qh;
+			struct fsl_req *next_req;
+
+			qh = ep->qh;
+			next_req = list_entry(req->queue.next, struct fsl_req,
+					queue);
+
+			/* Point the QH to the first TD of next request */
+			fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
+		}
+
+		/* The request hasn't been processed, patch up the TD chain */
+	} else {
+		struct fsl_req *prev_req;
+
+		prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
+		fsl_writel(fsl_readl(&req->tail->next_td_ptr),
+				&prev_req->tail->next_td_ptr);
+
+	}
+
+	done(ep, req, -ECONNRESET);
+
+	/* Enable EP */
+out:	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+	if (ep_is_in(ep))
+		epctrl |= EPCTRL_TX_ENABLE;
+	else
+		epctrl |= EPCTRL_RX_ENABLE;
+	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+	ep->stopped = stopped;
+
+	spin_unlock_irqrestore(&ep->udc->lock, flags);
+	return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------
+ * modify the endpoint halt feature
+ * @ep: the non-isochronous endpoint being stalled
+ * @value: 1--set halt  0--clear halt
+ * Returns zero, or a negative error code.
+*----------------------------------------------------------------*/
+static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
+{
+	struct fsl_ep *ep = NULL;
+	unsigned long flags = 0;
+	int status = -EOPNOTSUPP;	/* operation not supported */
+	unsigned char ep_dir = 0, ep_num = 0;
+	struct fsl_udc *udc = NULL;
+
+	ep = container_of(_ep, struct fsl_ep, ep);
+	udc = ep->udc;
+	if (!_ep || !ep->desc) {
+		status = -EINVAL;
+		goto out;
+	}
+	if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
+		status = -ESHUTDOWN;
+		goto out;
+	}
+
+	if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+		status = -EOPNOTSUPP;
+		goto out;
+	}
+
+	/* Attempt to halt IN ep will fail if any transfer requests
+	 * are still queue */
+	if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
+		status = -EAGAIN;
+		goto out;
+	}
+
+	status = 0;
+	ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
+	ep_num = (unsigned char)(ep_index(ep));
+	spin_lock_irqsave(&ep->udc->lock, flags);
+	dr_ep_change_stall(ep_num, ep_dir, value);
+	spin_unlock_irqrestore(&ep->udc->lock, flags);
+
+	if (ep_index(ep) == 0) {
+		udc->ep0_dir = 0;
+	}
+out:
+	VDBG(" %s %s halt stat %d", ep->ep.name,
+			value ?  "set" : "clear", status);
+
+	return status;
+}
+
+static int arcotg_fifo_status(struct usb_ep *_ep)
+{
+	struct fsl_ep *ep;
+	struct fsl_udc *udc;
+	int size = 0;
+	u32 bitmask;
+	struct ep_queue_head *d_qh;
+
+	ep = container_of(_ep, struct fsl_ep, ep);
+	if (!_ep || (!ep->desc && ep_index(ep) != 0))
+		return -ENODEV;
+
+	udc = (struct fsl_udc *)ep->udc;
+
+	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
+		return -ESHUTDOWN;
+
+	d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
+
+	bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
+	    (1 << (ep_index(ep)));
+
+	if (fsl_readl(&dr_regs->endptstatus) & bitmask)
+		size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
+		    >> DTD_LENGTH_BIT_POS;
+
+	pr_debug("%s %u\n", __func__, size);
+	return size;
+}
+
+static void fsl_ep_fifo_flush(struct usb_ep *_ep)
+{
+	struct fsl_ep *ep;
+	int ep_num, ep_dir;
+	u32 bits;
+	unsigned long timeout;
+#define FSL_UDC_FLUSH_TIMEOUT 1000
+
+	if (!_ep) {
+		return;
+	} else {
+		ep = container_of(_ep, struct fsl_ep, ep);
+		if (!ep->desc)
+			return;
+	}
+	ep_num = ep_index(ep);
+	ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
+
+	if (ep_num == 0)
+		bits = (1 << 16) | 1;
+	else if (ep_dir == USB_SEND)
+		bits = 1 << (16 + ep_num);
+	else
+		bits = 1 << ep_num;
+
+	timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
+	do {
+		fsl_writel(bits, &dr_regs->endptflush);
+
+		/* Wait until flush complete */
+		while (fsl_readl(&dr_regs->endptflush)) {
+			if (time_after(jiffies, timeout)) {
+				ERR("ep flush timeout\n");
+				return;
+			}
+			cpu_relax();
+		}
+		/* See if we need to flush again */
+	} while (fsl_readl(&dr_regs->endptstatus) & bits);
+}
+
+static struct usb_ep_ops fsl_ep_ops = {
+	.enable = fsl_ep_enable,
+	.disable = fsl_ep_disable,
+
+	.alloc_request = fsl_alloc_request,
+	.free_request = fsl_free_request,
+
+	.queue = fsl_ep_queue,
+	.dequeue = fsl_ep_dequeue,
+
+	.set_halt = fsl_ep_set_halt,
+	.fifo_status = arcotg_fifo_status,
+	.fifo_flush = fsl_ep_fifo_flush,	/* flush fifo */
+};
+
+/*-------------------------------------------------------------------------
+		Gadget Driver Layer Operations
+-------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------
+ * Get the current frame number (from DR frame_index Reg )
+ *----------------------------------------------------------------------*/
+static int fsl_get_frame(struct usb_gadget *gadget)
+{
+	return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
+}
+
+/*-----------------------------------------------------------------------
+ * Tries to wake up the host connected to this gadget
+ -----------------------------------------------------------------------*/
+static int fsl_wakeup(struct usb_gadget *gadget)
+{
+	struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
+	u32 portsc;
+
+	/* Remote wakeup feature not enabled by host */
+	if (!udc->remote_wakeup)
+		return -ENOTSUPP;
+
+	portsc = fsl_readl(&dr_regs->portsc1);
+	/* not suspended? */
+	if (!(portsc & PORTSCX_PORT_SUSPEND))
+		return 0;
+	/* trigger force resume */
+	portsc |= PORTSCX_PORT_FORCE_RESUME;
+	fsl_writel(portsc, &dr_regs->portsc1);
+	return 0;
+}
+
+static int can_pullup(struct fsl_udc *udc)
+{
+	return udc->driver && udc->softconnect && udc->vbus_active;
+}
+
+/* Notify controller that VBUS is powered, Called by whatever
+   detects VBUS sessions */
+static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
+{
+	struct fsl_udc	*udc;
+	unsigned long	flags;
+
+	udc = container_of(gadget, struct fsl_udc, gadget);
+	spin_lock_irqsave(&udc->lock, flags);
+	VDBG("VBUS %s\n", is_active ? "on" : "off");
+	udc->vbus_active = (is_active != 0);
+	if (can_pullup(udc))
+		fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
+				&dr_regs->usbcmd);
+	else
+		fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
+				&dr_regs->usbcmd);
+	spin_unlock_irqrestore(&udc->lock, flags);
+	return 0;
+}
+
+/* constrain controller's VBUS power usage
+ * This call is used by gadget drivers during SET_CONFIGURATION calls,
+ * reporting how much power the device may consume.  For example, this
+ * could affect how quickly batteries are recharged.
+ *
+ * Returns zero on success, else negative errno.
+ */
+static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
+{
+	struct fsl_udc *udc;
+	struct fsl_usb2_platform_data *pdata;
+
+	udc = container_of(gadget, struct fsl_udc, gadget);
+	if (udc->transceiver)
+		return otg_set_power(udc->transceiver, mA);
+	pdata = udc->pdata;
+	if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_draw) {
+		pdata->xcvr_ops->set_vbus_draw(pdata->xcvr_ops, pdata, mA);
+		return 0;
+	}
+	return -ENOTSUPP;
+}
+
+/* Change Data+ pullup status
+ * this func is used by usb_gadget_connect/disconnet
+ */
+static int fsl_pullup(struct usb_gadget *gadget, int is_on)
+{
+	struct fsl_udc *udc;
+
+	udc = container_of(gadget, struct fsl_udc, gadget);
+	udc->softconnect = (is_on != 0);
+	if (can_pullup(udc))
+		fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
+				&dr_regs->usbcmd);
+	else
+		fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
+				&dr_regs->usbcmd);
+
+	return 0;
+}
+
+static int fsl_udc_start(struct usb_gadget_driver *driver,
+			int (*bind)(struct usb_gadget *));
+static int fsl_udc_stop(struct usb_gadget_driver *driver);
+
+
+/* defined in gadget.h */
+static struct usb_gadget_ops fsl_gadget_ops = {
+	.get_frame = fsl_get_frame,
+	.wakeup = fsl_wakeup,
+/*	.set_selfpowered = fsl_set_selfpowered,	*/ /* Always selfpowered */
+	.vbus_session = fsl_vbus_session,
+	.vbus_draw = fsl_vbus_draw,
+	.pullup = fsl_pullup,
+	.start = fsl_udc_start,
+	.stop = fsl_udc_stop,
+};
+
+/* Set protocol stall on ep0, protocol stall will automatically be cleared
+   on new transaction */
+static void ep0stall(struct fsl_udc *udc)
+{
+	u32 tmp;
+
+	/* must set tx and rx to stall at the same time */
+	tmp = fsl_readl(&dr_regs->endptctrl[0]);
+	tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
+	fsl_writel(tmp, &dr_regs->endptctrl[0]);
+	udc->ep0_dir = 0;
+}
+
+/* Prime a status phase for ep0 */
+static int ep0_prime_status(struct fsl_udc *udc, int direction)
+{
+	struct fsl_req *req = udc->status_req;
+	struct fsl_ep *ep;
+	int status = 0;
+
+	if (direction == EP_DIR_IN)
+		udc->ep0_dir = USB_DIR_IN;
+	else
+		udc->ep0_dir = USB_DIR_OUT;
+
+	ep = &udc->eps[0];
+
+	req->ep = ep;
+	req->req.length = 0;
+	req->req.status = -EINPROGRESS;
+
+	status = fsl_ep_queue(&ep->ep, &req->req, GFP_ATOMIC);
+	return status;
+}
+
+static inline int udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
+{
+	struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
+
+	if (!ep->name)
+		return 0;
+
+	nuke(ep, -ESHUTDOWN);
+
+	return 0;
+}
+
+/*
+ * ch9 Set address
+ */
+static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
+{
+	/* Save the new address to device struct */
+	udc->device_address = (u8) value;
+	/* Update usb state */
+	udc->usb_state = USB_STATE_ADDRESS;
+	/* Status phase */
+	if (ep0_prime_status(udc, EP_DIR_IN))
+		ep0stall(udc);
+}
+
+/*
+ * ch9 Get status
+ */
+static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
+		u16 index, u16 length)
+{
+	u16 tmp = 0;		/* Status, cpu endian */
+
+	struct fsl_req *req;
+	struct fsl_ep *ep;
+	int status = 0;
+
+	ep = &udc->eps[0];
+
+	if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
+		/* Get device status */
+		tmp = 1 << USB_DEVICE_SELF_POWERED;
+		tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
+	} else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
+		/* Get interface status */
+		/* We don't have interface information in udc driver */
+		tmp = 0;
+	} else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
+		/* Get endpoint status */
+		struct fsl_ep *target_ep;
+
+		target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
+
+		/* stall if endpoint doesn't exist */
+		if (!target_ep->desc)
+			goto stall;
+		tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
+				<< USB_ENDPOINT_HALT;
+	}
+
+	udc->ep0_dir = USB_DIR_IN;
+	/* Borrow the per device data_req */
+	/* status_req had been used to prime status */
+	req = udc->data_req;
+	/* Fill in the reqest structure */
+	*((u16 *) req->req.buf) = cpu_to_le16(tmp);
+	req->ep = ep;
+	req->req.length = 2;
+
+	status = fsl_ep_queue(&ep->ep, &req->req, GFP_ATOMIC);
+	if (status) {
+		udc_reset_ep_queue(udc, 0);
+		ERR("Can't respond to getstatus request \n");
+		goto stall;
+	}
+	return;
+stall:
+	ep0stall(udc);
+
+}
+
+static void setup_received_irq(struct fsl_udc *udc,
+		struct usb_ctrlrequest *setup)
+{
+	u16 wValue = le16_to_cpu(setup->wValue);
+	u16 wIndex = le16_to_cpu(setup->wIndex);
+	u16 wLength = le16_to_cpu(setup->wLength);
+	struct usb_gadget *gadget = &(udc->gadget);
+	unsigned mA = 500;
+	udc_reset_ep_queue(udc, 0);
+
+	if (wLength) {
+		int dir;
+		dir = EP_DIR_IN;
+		if (setup->bRequestType & USB_DIR_IN) {
+			dir = EP_DIR_OUT;
+		}
+		spin_unlock(&udc->lock);
+		if (ep0_prime_status(udc, dir))
+			ep0stall(udc);
+		spin_lock(&udc->lock);
+	}
+	/* We process some stardard setup requests here */
+	switch (setup->bRequest) {
+	case USB_REQ_GET_STATUS:
+		/* Data+Status phase from udc */
+		if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
+					!= (USB_DIR_IN | USB_TYPE_STANDARD))
+			break;
+		spin_unlock(&udc->lock);
+		ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
+		spin_lock(&udc->lock);
+		return;
+
+	case USB_REQ_SET_ADDRESS:
+		/* Status phase from udc */
+		if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
+						| USB_RECIP_DEVICE))
+			break;
+		spin_unlock(&udc->lock);
+		ch9setaddress(udc, wValue, wIndex, wLength);
+		spin_lock(&udc->lock);
+		return;
+	case USB_REQ_SET_CONFIGURATION:
+		spin_unlock(&udc->lock);
+		fsl_vbus_draw(gadget, mA);
+		spin_lock(&udc->lock);
+	     break;
+	case USB_REQ_CLEAR_FEATURE:
+	case USB_REQ_SET_FEATURE:
+		/* Status phase from udc */
+	{
+		int rc = -EOPNOTSUPP;
+		u16 ptc = 0;
+
+		if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
+				== (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
+			int pipe = get_pipe_by_windex(wIndex);
+			struct fsl_ep *ep;
+
+			if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
+				break;
+			ep = get_ep_by_pipe(udc, pipe);
+
+			spin_unlock(&udc->lock);
+			rc = fsl_ep_set_halt(&ep->ep,
+					(setup->bRequest == USB_REQ_SET_FEATURE)
+						? 1 : 0);
+			spin_lock(&udc->lock);
+
+		} else if ((setup->bRequestType & (USB_RECIP_MASK
+				| USB_TYPE_MASK)) == (USB_RECIP_DEVICE
+				| USB_TYPE_STANDARD)) {
+			/* Note: The driver has not include OTG support yet.
+			 * This will be set when OTG support is added */
+			if (setup->wValue == USB_DEVICE_TEST_MODE)
+				ptc = setup->wIndex >> 8;
+			else if (gadget_is_otg(&udc->gadget)) {
+				if (setup->bRequest ==
+				    USB_DEVICE_B_HNP_ENABLE)
+					udc->gadget.b_hnp_enable = 1;
+				else if (setup->bRequest ==
+					 USB_DEVICE_A_HNP_SUPPORT)
+					udc->gadget.a_hnp_support = 1;
+				else if (setup->bRequest ==
+					 USB_DEVICE_A_ALT_HNP_SUPPORT)
+					udc->gadget.a_alt_hnp_support = 1;
+			}
+			rc = 0;
+		} else
+			break;
+
+		if (rc == 0) {
+			spin_unlock(&udc->lock);
+			if (ep0_prime_status(udc, EP_DIR_IN))
+				ep0stall(udc);
+			spin_lock(&udc->lock);
+		}
+		if (ptc) {
+			u32 tmp;
+
+			mdelay(10);
+			fsl_platform_set_test_mode(udc->pdata, ptc);
+			tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
+			fsl_writel(tmp, &dr_regs->portsc1);
+			printk(KERN_INFO "udc: switch to test mode 0x%x.\n", ptc);
+		}
+
+		return;
+	}
+
+	default:
+		break;
+	}
+
+	/* Requests handled by gadget */
+	if (wLength) {
+		/* Data phase from gadget, status phase from udc */
+		udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
+				?  USB_DIR_IN : USB_DIR_OUT;
+		spin_unlock(&udc->lock);
+		if (udc->driver->setup(&udc->gadget,
+				&udc->local_setup_buff) < 0) {
+			/* cancel status phase */
+			udc_reset_ep_queue(udc, 0);
+			ep0stall(udc);
+		}
+	} else {
+		/* No data phase, IN status from gadget */
+		udc->ep0_dir = USB_DIR_IN;
+		spin_unlock(&udc->lock);
+		if (udc->driver->setup(&udc->gadget,
+				&udc->local_setup_buff) < 0)
+			ep0stall(udc);
+	}
+	spin_lock(&udc->lock);
+}
+
+/* Process request for Data or Status phase of ep0
+ * prime status phase if needed */
+static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
+		struct fsl_req *req)
+{
+	if (udc->usb_state == USB_STATE_ADDRESS) {
+		/* Set the new address */
+		u32 new_address = (u32) udc->device_address;
+		fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
+				&dr_regs->deviceaddr);
+	}
+
+	done(ep0, req, 0);
+}
+
+/* Tripwire mechanism to ensure a setup packet payload is extracted without
+ * being corrupted by another incoming setup packet */
+static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
+{
+	u32 temp;
+	struct ep_queue_head *qh;
+	struct fsl_usb2_platform_data *pdata = udc->pdata;
+
+	qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
+
+	/* Clear bit in ENDPTSETUPSTAT */
+	temp = fsl_readl(&dr_regs->endptsetupstat);
+	fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
+
+	/* while a hazard exists when setup package arrives */
+	do {
+		/* Set Setup Tripwire */
+		temp = fsl_readl(&dr_regs->usbcmd);
+		fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
+
+		/* Copy the setup packet to local buffer */
+		if (pdata->le_setup_buf) {
+			u32 *p = (u32 *)buffer_ptr;
+			u32 *s = (u32 *)qh->setup_buffer;
+
+			/* Convert little endian setup buffer to CPU endian */
+			*p++ = le32_to_cpu(*s++);
+			*p = le32_to_cpu(*s);
+		} else {
+			memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
+		}
+	} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
+
+	/* Clear Setup Tripwire */
+	temp = fsl_readl(&dr_regs->usbcmd);
+	fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
+}
+
+static void iram_process_ep_complete(struct fsl_req *curr_req,
+				     int cur_transfer)
+{
+	char *buf;
+	u32 len;
+	int in = ep_is_in(curr_req->ep);
+
+	if (in)
+		buf = (char *)udc_controller->iram_buffer_v[1];
+	else
+		buf = (char *)udc_controller->iram_buffer_v[0];
+
+	if (curr_req->cur->next_td_ptr == cpu_to_hc32(DTD_NEXT_TERMINATE)
+	    || (cur_transfer < g_iram_size)
+	    || (curr_req->req.length == curr_req->req.actual))
+		curr_req->last_one = 1;
+
+	if (curr_req->last_one) {
+		/* the last transfer */
+		if (!in) {
+			memcpy(curr_req->req.buf + curr_req->buffer_offset, buf,
+			       cur_transfer);
+		}
+		if (curr_req->tail->next_td_ptr !=
+				    cpu_to_hc32(DTD_NEXT_TERMINATE)) {
+			/* have next request,queue it */
+			struct fsl_req *next_req;
+			next_req =
+			    list_entry(curr_req->queue.next,
+				       struct fsl_req, queue);
+			if (in)
+				memcpy(buf, next_req->req.buf,
+				       min(g_iram_size, next_req->req.length));
+			update_qh(next_req);
+		}
+		curr_req->req.dma = curr_req->oridma;
+	} else {
+		/* queue next dtd */
+		/* because had next dtd, so should finish */
+		/* tranferring g_iram_size data */
+		curr_req->buffer_offset += g_iram_size;
+		/* pervious set stop bit,now clear it */
+		curr_req->cur->next_td_ptr &= ~cpu_to_hc32(DTD_NEXT_TERMINATE);
+		curr_req->cur = curr_req->cur->next_td_virt;
+		if (in) {
+			len =
+			    min(curr_req->req.length - curr_req->buffer_offset,
+				g_iram_size);
+			memcpy(buf, curr_req->req.buf + curr_req->buffer_offset,
+			       len);
+		} else {
+			memcpy(curr_req->req.buf + curr_req->buffer_offset -
+			       g_iram_size, buf, g_iram_size);
+		}
+		update_qh(curr_req);
+	}
+}
+
+/* process-ep_req(): free the completed Tds for this req */
+static int process_ep_req(struct fsl_udc *udc, int pipe,
+		struct fsl_req *curr_req)
+{
+	struct ep_td_struct *curr_td;
+	int	td_complete, actual, remaining_length, j, tmp;
+	int	status = 0;
+	int	errors = 0;
+	struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
+	int direction = pipe % 2;
+	int total = 0, real_len;
+
+	curr_td = curr_req->head;
+	td_complete = 0;
+	actual = curr_req->req.length;
+	real_len = curr_req->req.length;
+
+	for (j = 0; j < curr_req->dtd_count; j++) {
+		remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
+					& DTD_PACKET_SIZE)
+				>> DTD_LENGTH_BIT_POS;
+		if (NEED_IRAM(curr_req->ep)) {
+			if (real_len >= g_iram_size) {
+				actual = g_iram_size;
+				real_len -= g_iram_size;
+			} else {	/* the last packet */
+				actual = real_len;
+				curr_req->last_one = 1;
+			}
+		}
+		actual -= remaining_length;
+		total += actual;
+
+		errors = hc32_to_cpu(curr_td->size_ioc_sts) & DTD_ERROR_MASK;
+		if (errors) {
+			if (errors & DTD_STATUS_HALTED) {
+				ERR("dTD error %08x QH=%d\n", errors, pipe);
+				/* Clear the errors and Halt condition */
+				tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
+				tmp &= ~errors;
+				curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
+				status = -EPIPE;
+				/* FIXME: continue with next queued TD? */
+
+				break;
+			}
+			if (errors & DTD_STATUS_DATA_BUFF_ERR) {
+				VDBG("Transfer overflow");
+				status = -EPROTO;
+				break;
+			} else if (errors & DTD_STATUS_TRANSACTION_ERR) {
+				VDBG("ISO error");
+				status = -EILSEQ;
+				break;
+			} else
+				ERR("Unknown error has occured (0x%x)!\r\n",
+					errors);
+
+		} else if (hc32_to_cpu(curr_td->size_ioc_sts)
+				& DTD_STATUS_ACTIVE) {
+			VDBG("Request not complete");
+			status = REQ_UNCOMPLETE;
+			return status;
+		} else if (remaining_length) {
+			if (direction) {
+				VDBG("Transmit dTD remaining length not zero");
+				status = -EPROTO;
+				break;
+			} else {
+				td_complete++;
+				break;
+			}
+		} else {
+			td_complete++;
+			VDBG("dTD transmitted successful ");
+		}
+		if (NEED_IRAM(curr_req->ep))
+			if (curr_td->
+			    next_td_ptr & cpu_to_hc32(DTD_NEXT_TERMINATE))
+				break;
+		if (j != curr_req->dtd_count - 1)
+			curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
+	}
+
+	if (status)
+		return status;
+	curr_req->req.actual = total;
+	if (NEED_IRAM(curr_req->ep))
+		iram_process_ep_complete(curr_req, actual);
+	return 0;
+}
+
+/* Process a DTD completion interrupt */
+static void dtd_complete_irq(struct fsl_udc *udc)
+{
+	u32 bit_pos;
+	int i, ep_num, direction, bit_mask, status;
+	struct fsl_ep *curr_ep;
+	struct fsl_req *curr_req, *temp_req;
+
+	/* Clear the bits in the register */
+	bit_pos = fsl_readl(&dr_regs->endptcomplete);
+	fsl_writel(bit_pos, &dr_regs->endptcomplete);
+
+	if (!bit_pos)
+		return;
+
+	for (i = 0; i < udc->max_ep * 2; i++) {
+		ep_num = i >> 1;
+		direction = i % 2;
+
+		bit_mask = 1 << (ep_num + 16 * direction);
+
+		if (!(bit_pos & bit_mask))
+			continue;
+
+		curr_ep = get_ep_by_pipe(udc, i);
+
+		/* If the ep is configured */
+		if (curr_ep->name == NULL) {
+			INFO("Invalid EP?");
+			continue;
+		}
+
+		/* process the req queue until an uncomplete request */
+		list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
+				queue) {
+			status = process_ep_req(udc, i, curr_req);
+
+			VDBG("status of process_ep_req= %d, ep = %d",
+					status, ep_num);
+			if (status == REQ_UNCOMPLETE)
+				break;
+			/* write back status to req */
+			curr_req->req.status = status;
+
+			if (ep_num == 0) {
+				ep0_req_complete(udc, curr_ep, curr_req);
+				break;
+			} else {
+				if (NEED_IRAM(curr_ep)) {
+					if (curr_req->last_one)
+						done(curr_ep, curr_req, status);
+					/* only check the 1th req */
+					break;
+				} else
+					done(curr_ep, curr_req, status);
+			}
+		}
+		dump_ep_queue(curr_ep);
+	}
+}
+
+static void fsl_udc_speed_update(struct fsl_udc *udc)
+{
+	u32 speed = 0;
+	u32 loop = 0;
+
+	/* Wait for port reset finished */
+	while ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)
+		&& (loop++ < 1000))
+		;
+
+	speed = (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SPEED_MASK);
+	switch (speed) {
+	case PORTSCX_PORT_SPEED_HIGH:
+		udc->gadget.speed = USB_SPEED_HIGH;
+		break;
+	case PORTSCX_PORT_SPEED_FULL:
+		udc->gadget.speed = USB_SPEED_FULL;
+		break;
+	case PORTSCX_PORT_SPEED_LOW:
+		udc->gadget.speed = USB_SPEED_LOW;
+		break;
+	default:
+		udc->gadget.speed = USB_SPEED_UNKNOWN;
+		break;
+	}
+}
+
+/* Process a port change interrupt */
+static void port_change_irq(struct fsl_udc *udc)
+{
+	if (udc->bus_reset)
+		udc->bus_reset = 0;
+
+	/* Update port speed */
+	fsl_udc_speed_update(udc);
+
+	/* Update USB state */
+	if (!udc->resume_state)
+		udc->usb_state = USB_STATE_DEFAULT;
+}
+
+/* Process suspend interrupt */
+static void suspend_irq(struct fsl_udc *udc)
+{
+	u32 otgsc = 0;
+
+	pr_debug("%s\n", __func__);
+
+	udc->resume_state = udc->usb_state;
+	udc->usb_state = USB_STATE_SUSPENDED;
+
+	/* Set discharge vbus */
+	otgsc = fsl_readl(&dr_regs->otgsc);
+	otgsc &= ~(OTGSC_INTSTS_MASK);
+	otgsc |= OTGSC_CTRL_VBUS_DISCHARGE;
+	fsl_writel(otgsc, &dr_regs->otgsc);
+
+	/* discharge in work queue */
+	cancel_delayed_work(&udc->gadget_delay_work);
+	schedule_delayed_work(&udc->gadget_delay_work, msecs_to_jiffies(20));
+
+	/* report suspend to the driver, serial.c does not support this */
+	if (udc->driver->suspend)
+		udc->driver->suspend(&udc->gadget);
+}
+
+static void bus_resume(struct fsl_udc *udc)
+{
+	udc->usb_state = udc->resume_state;
+	udc->resume_state = 0;
+
+	/* report resume to the driver, serial.c does not support this */
+	if (udc->driver->resume)
+		udc->driver->resume(&udc->gadget);
+}
+
+/* Clear up all ep queues */
+static int reset_queues(struct fsl_udc *udc)
+{
+	u8 pipe;
+
+	for (pipe = 0; pipe < udc->max_pipes; pipe++)
+		udc_reset_ep_queue(udc, pipe);
+
+	/* report disconnect; the driver is already quiesced */
+	udc->driver->disconnect(&udc->gadget);
+
+	return 0;
+}
+
+/* Process reset interrupt */
+static void reset_irq(struct fsl_udc *udc)
+{
+	u32 temp;
+
+	/* Clear the device address */
+	temp = fsl_readl(&dr_regs->deviceaddr);
+	fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
+
+	udc->device_address = 0;
+
+	/* Clear usb state */
+	udc->resume_state = 0;
+	udc->ep0_dir = 0;
+	udc->remote_wakeup = 0;	/* default to 0 on reset */
+	udc->gadget.b_hnp_enable = 0;
+	udc->gadget.a_hnp_support = 0;
+	udc->gadget.a_alt_hnp_support = 0;
+
+	/* Clear all the setup token semaphores */
+	temp = fsl_readl(&dr_regs->endptsetupstat);
+	fsl_writel(temp, &dr_regs->endptsetupstat);
+
+	/* Clear all the endpoint complete status bits */
+	temp = fsl_readl(&dr_regs->endptcomplete);
+	fsl_writel(temp, &dr_regs->endptcomplete);
+
+	/* Write 1s to the flush register */
+	fsl_writel(0xffffffff, &dr_regs->endptflush);
+
+	/* Bus is reseting */
+	udc->bus_reset = 1;
+	/* Reset all the queues, include XD, dTD, EP queue
+	 * head and TR Queue */
+	reset_queues(udc);
+	udc->usb_state = USB_STATE_DEFAULT;
+}
+
+static void fsl_gadget_event(struct work_struct *work)
+{
+	struct fsl_udc *udc = udc_controller;
+	unsigned long flags;
+
+	spin_lock_irqsave(&udc->lock, flags);
+	/* update port status */
+	fsl_udc_speed_update(udc);
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	/* close dr controller clock */
+	dr_clk_gate(false);
+}
+
+static void fsl_gadget_delay_event(struct work_struct *work)
+{
+	u32 otgsc = 0;
+
+	dr_clk_gate(true);
+	otgsc = fsl_readl(&dr_regs->otgsc);
+	/* clear vbus discharge */
+	if (otgsc & OTGSC_CTRL_VBUS_DISCHARGE) {
+		otgsc &= ~(OTGSC_INTSTS_MASK | OTGSC_CTRL_VBUS_DISCHARGE);
+		fsl_writel(otgsc, &dr_regs->otgsc);
+	}
+	dr_clk_gate(false);
+}
+
+/* if wakup udc, return true; else return false*/
+bool try_wake_up_udc(struct fsl_udc *udc)
+{
+	struct fsl_usb2_platform_data *pdata;
+	u32 irq_src;
+
+	pdata = udc->pdata;
+
+	/* check if Vbus change irq */
+	irq_src = fsl_readl(&dr_regs->otgsc) & (~OTGSC_ID_CHANGE_IRQ_STS);
+	if (irq_src & OTGSC_B_SESSION_VALID_IRQ_STS) {
+		u32 tmp;
+		fsl_writel(irq_src, &dr_regs->otgsc);
+		/* only handle device interrupt event */
+		if (!machine_is_mx53_loco()) {
+			if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID))
+				return false;
+		}
+
+		tmp = fsl_readl(&dr_regs->usbcmd);
+		/* check BSV bit to see if fall or rise */
+		if (irq_src & OTGSC_B_SESSION_VALID) {
+			if (udc->suspended) /*let the system pm resume the udc */
+				return true;
+			udc->stopped = 0;
+			fsl_writel(tmp | USB_CMD_RUN_STOP, &dr_regs->usbcmd);
+			printk(KERN_DEBUG "%s: udc out low power mode\n", __func__);
+		} else {
+			if (udc->driver)
+				udc->driver->disconnect(&udc->gadget);
+			fsl_writel(tmp & ~USB_CMD_RUN_STOP, &dr_regs->usbcmd);
+			udc->stopped = 1;
+			/* enable wake up */
+			dr_wake_up_enable(udc, true);
+			/* close USB PHY clock */
+			dr_phy_low_power_mode(udc, true);
+			schedule_work(&udc->gadget_work);
+			printk(KERN_DEBUG "%s: udc enter low power mode\n", __func__);
+			return false;
+		}
+	}
+
+	return true;
+}
+/*
+ * USB device controller interrupt handler
+ */
+static irqreturn_t fsl_udc_irq(int irq, void *_udc)
+{
+	struct fsl_udc *udc = _udc;
+	u32 irq_src;
+	irqreturn_t status = IRQ_NONE;
+	unsigned long flags;
+	struct fsl_usb2_platform_data *pdata = udc->pdata;
+
+	if (pdata->irq_delay)
+		return status;
+
+	spin_lock_irqsave(&udc->lock, flags);
+
+	if (try_wake_up_udc(udc) == false) {
+		goto irq_end;
+	}
+#ifdef CONFIG_USB_OTG
+	/* if no gadget register in this driver, we need do noting */
+	if (udc->transceiver->gadget == NULL) {
+		goto irq_end;
+	}
+	/* only handle device interrupt event */
+	if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
+		goto irq_end;
+	}
+#endif
+	irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
+	/* Clear notification bits */
+	fsl_writel(irq_src, &dr_regs->usbsts);
+
+	VDBG("0x%x\n", irq_src);
+	/* Need to resume? */
+	if (udc->usb_state == USB_STATE_SUSPENDED)
+		if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
+			bus_resume(udc);
+
+	/* USB Interrupt */
+	if (irq_src & USB_STS_INT) {
+		VDBG("Packet int");
+		/* Setup package, we only support ep0 as control ep */
+		if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
+			tripwire_handler(udc, 0,
+					(u8 *) (&udc->local_setup_buff));
+			setup_received_irq(udc, &udc->local_setup_buff);
+			status = IRQ_HANDLED;
+		}
+
+		/* completion of dtd */
+		if (fsl_readl(&dr_regs->endptcomplete)) {
+			dtd_complete_irq(udc);
+			status = IRQ_HANDLED;
+		}
+	}
+
+	/* SOF (for ISO transfer) */
+	if (irq_src & USB_STS_SOF) {
+		status = IRQ_HANDLED;
+	}
+
+	/* Port Change */
+	if (irq_src & USB_STS_PORT_CHANGE) {
+		port_change_irq(udc);
+		status = IRQ_HANDLED;
+	}
+
+	/* Reset Received */
+	if (irq_src & USB_STS_RESET) {
+		VDBG("reset int");
+		reset_irq(udc);
+		status = IRQ_HANDLED;
+	}
+
+	/* Sleep Enable (Suspend) */
+	if (irq_src & USB_STS_SUSPEND) {
+		VDBG("suspend int");
+		suspend_irq(udc);
+		status = IRQ_HANDLED;
+	}
+
+	if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
+		VDBG("Error IRQ %x ", irq_src);
+	}
+
+irq_end:
+	spin_unlock_irqrestore(&udc->lock, flags);
+	return status;
+}
+
+/*----------------------------------------------------------------*
+ * Hook to gadget drivers
+ * Called by initialization code of gadget drivers
+*----------------------------------------------------------------*/
+static int fsl_udc_start(struct usb_gadget_driver *driver,
+			 int (*bind)(struct usb_gadget *))
+{
+	int retval = -ENODEV;
+	unsigned long flags = 0;
+
+	if (!udc_controller)
+		return -ENODEV;
+
+	if (!bind || !driver || (driver->speed != USB_SPEED_FULL
+			&& driver->speed != USB_SPEED_HIGH)
+			|| !driver->disconnect
+			|| !driver->setup)
+		return -EINVAL;
+
+	if (udc_controller->driver)
+		return -EBUSY;
+
+	/* lock is needed but whether should use this lock or another */
+	spin_lock_irqsave(&udc_controller->lock, flags);
+
+	driver->driver.bus = 0;
+	udc_controller->pdata->port_enables = 1;
+	/* hook up the driver */
+	udc_controller->driver = driver;
+	udc_controller->gadget.dev.driver = &driver->driver;
+	spin_unlock_irqrestore(&udc_controller->lock, flags);
+	dr_clk_gate(true);
+	/* It doesn't need to switch usb from low power mode to normal mode
+	 * at otg mode
+	 */
+	if (!udc_controller->transceiver)
+		dr_phy_low_power_mode(udc_controller, false);
+
+	/* bind udc driver to gadget driver */
+	retval = bind(&udc_controller->gadget);
+	if (retval) {
+		VDBG("bind to %s --> %d", driver->driver.name, retval);
+		udc_controller->gadget.dev.driver = 0;
+		udc_controller->driver = 0;
+		dr_clk_gate(false);
+		goto out;
+	}
+
+	if (udc_controller->transceiver) {
+		/* Suspend the controller until OTG enable it */
+		udc_controller->suspended = 1;/* let the otg resume it */
+		printk(KERN_DEBUG "Suspend udc for OTG auto detect\n");
+		dr_wake_up_enable(udc_controller, true);
+		dr_clk_gate(false);
+		/* export udc suspend/resume call to OTG */
+		udc_controller->gadget.dev.driver->suspend = (dev_sus)fsl_udc_suspend;
+		udc_controller->gadget.dev.driver->resume = (dev_res)fsl_udc_resume;
+
+		/* connect to bus through transceiver */
+		retval = otg_set_peripheral(udc_controller->transceiver,
+					    &udc_controller->gadget);
+		if (retval < 0) {
+			ERR("can't bind to transceiver\n");
+			driver->unbind(&udc_controller->gadget);
+			udc_controller->gadget.dev.driver = 0;
+			udc_controller->driver = 0;
+			return retval;
+		}
+	} else {
+		/* Enable DR IRQ reg and Set usbcmd reg  Run bit */
+		dr_controller_run(udc_controller);
+		if (udc_controller->stopped)
+			dr_clk_gate(false);
+		udc_controller->usb_state = USB_STATE_ATTACHED;
+		udc_controller->ep0_dir = 0;
+	}
+	printk(KERN_INFO "%s: bind to driver %s \n",
+			udc_controller->gadget.name, driver->driver.name);
+
+out:
+	if (retval) {
+		printk(KERN_DEBUG "retval %d \n", retval);
+		udc_controller->pdata->port_enables = 0;
+	}
+	return retval;
+}
+
+/* Disconnect from gadget driver */
+static int fsl_udc_stop(struct usb_gadget_driver *driver)
+{
+	struct fsl_ep *loop_ep;
+	unsigned long flags;
+
+	if (!udc_controller)
+		return -ENODEV;
+
+	if (!driver || driver != udc_controller->driver || !driver->unbind)
+		return -EINVAL;
+
+	if (udc_controller->stopped)
+		dr_clk_gate(true);
+
+	if (udc_controller->transceiver)
+		(void)otg_set_peripheral(udc_controller->transceiver, 0);
+
+	/* stop DR, disable intr */
+	dr_controller_stop(udc_controller);
+
+	udc_controller->pdata->port_enables = 0;
+	/* in fact, no needed */
+	udc_controller->usb_state = USB_STATE_ATTACHED;
+	udc_controller->ep0_dir = 0;
+
+	/* stand operation */
+	spin_lock_irqsave(&udc_controller->lock, flags);
+	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
+	nuke(&udc_controller->eps[0], -ESHUTDOWN);
+	list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
+			ep.ep_list)
+		nuke(loop_ep, -ESHUTDOWN);
+	spin_unlock_irqrestore(&udc_controller->lock, flags);
+
+	/* disconnect gadget before unbinding */
+	driver->disconnect(&udc_controller->gadget);
+
+	/* unbind gadget and unhook driver. */
+	driver->unbind(&udc_controller->gadget);
+	udc_controller->gadget.dev.driver = 0;
+	udc_controller->driver = 0;
+
+	if (udc_controller->gadget.is_otg) {
+		dr_wake_up_enable(udc_controller, true);
+	}
+
+	dr_phy_low_power_mode(udc_controller, true);
+
+	printk(KERN_INFO "unregistered gadget driver '%s'\r\n",
+	       driver->driver.name);
+	return 0;
+}
+
+/*-------------------------------------------------------------------------
+		PROC File System Support
+-------------------------------------------------------------------------*/
+#ifdef CONFIG_USB_GADGET_DEBUG_FILES
+
+#include <linux/seq_file.h>
+
+static const char proc_filename[] = "driver/fsl_usb2_udc";
+
+static int fsl_proc_read(char *page, char **start, off_t off, int count,
+		int *eof, void *_dev)
+{
+	char *buf = page;
+	char *next = buf;
+	unsigned size = count;
+	unsigned long flags;
+	int t, i;
+	u32 tmp_reg;
+	struct fsl_ep *ep = NULL;
+	struct fsl_req *req;
+	struct fsl_usb2_platform_data *pdata;
+
+	struct fsl_udc *udc = udc_controller;
+	pdata = udc->pdata;
+	if (off != 0)
+		return 0;
+
+	dr_clk_gate(true);
+	spin_lock_irqsave(&udc->lock, flags);
+
+	/* ------basic driver infomation ---- */
+	t = scnprintf(next, size,
+			DRIVER_DESC "\n"
+			"%s version: %s\n"
+			"Gadget driver: %s\n\n",
+			driver_name, DRIVER_VERSION,
+			udc->driver ? udc->driver->driver.name : "(none)");
+	size -= t;
+	next += t;
+
+	/* ------ DR Registers ----- */
+	tmp_reg = fsl_readl(&dr_regs->usbcmd);
+	t = scnprintf(next, size,
+			"USBCMD reg:\n"
+			"SetupTW: %d\n"
+			"Run/Stop: %s\n\n",
+			(tmp_reg & USB_CMD_SUTW) ? 1 : 0,
+			(tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->usbsts);
+	t = scnprintf(next, size,
+			"USB Status Reg:\n"
+			"Dr Suspend: %d" "Reset Received: %d" "System Error: %s"
+			"USB Error Interrupt: %s\n\n",
+			(tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
+			(tmp_reg & USB_STS_RESET) ? 1 : 0,
+			(tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
+			(tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->usbintr);
+	t = scnprintf(next, size,
+			"USB Intrrupt Enable Reg:\n"
+			"Sleep Enable: %d" "SOF Received Enable: %d"
+			"Reset Enable: %d\n"
+			"System Error Enable: %d"
+			"Port Change Dectected Enable: %d\n"
+			"USB Error Intr Enable: %d" "USB Intr Enable: %d\n\n",
+			(tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
+			(tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
+			(tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->frindex);
+	t = scnprintf(next, size,
+			"USB Frame Index Reg:" "Frame Number is 0x%x\n\n",
+			(tmp_reg & USB_FRINDEX_MASKS));
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->deviceaddr);
+	t = scnprintf(next, size,
+			"USB Device Address Reg:" "Device Addr is 0x%x\n\n",
+			(tmp_reg & USB_DEVICE_ADDRESS_MASK));
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
+	t = scnprintf(next, size,
+			"USB Endpoint List Address Reg:"
+			"Device Addr is 0x%x\n\n",
+			(tmp_reg & USB_EP_LIST_ADDRESS_MASK));
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->portsc1);
+	t = scnprintf(next, size,
+		"USB Port Status&Control Reg:\n"
+		"Port Transceiver Type : %s" "Port Speed: %s \n"
+		"PHY Low Power Suspend: %s" "Port Reset: %s"
+		"Port Suspend Mode: %s \n" "Over-current Change: %s"
+		"Port Enable/Disable Change: %s\n"
+		"Port Enabled/Disabled: %s"
+		"Current Connect Status: %s\n\n", ({
+			char *s;
+			switch (tmp_reg & PORTSCX_PTS_FSLS) {
+			case PORTSCX_PTS_UTMI:
+				s = "UTMI"; break;
+			case PORTSCX_PTS_ULPI:
+				s = "ULPI "; break;
+			case PORTSCX_PTS_FSLS:
+				s = "FS/LS Serial"; break;
+			default:
+				s = "None"; break;
+			}
+			s; }), ({
+			char *s;
+			switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
+			case PORTSCX_PORT_SPEED_FULL:
+				s = "Full Speed"; break;
+			case PORTSCX_PORT_SPEED_LOW:
+				s = "Low Speed"; break;
+			case PORTSCX_PORT_SPEED_HIGH:
+				s = "High Speed"; break;
+			default:
+				s = "Undefined"; break;
+			}
+			s;
+		}),
+		(tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
+		"Normal PHY mode" : "Low power mode",
+		(tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
+		"Not in Reset",
+		(tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
+		(tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
+		"No",
+		(tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
+		"Not change",
+		(tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
+		"Not correct",
+		(tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
+		"Attached" : "Not-Att");
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->usbmode);
+	t = scnprintf(next, size,
+			"USB Mode Reg:" "Controller Mode is : %s\n\n", ({
+				char *s;
+				switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
+				case USB_MODE_CTRL_MODE_IDLE:
+					s = "Idle"; break;
+				case USB_MODE_CTRL_MODE_DEVICE:
+					s = "Device Controller"; break;
+				case USB_MODE_CTRL_MODE_HOST:
+					s = "Host Controller"; break;
+				default:
+					s = "None"; break;
+				}
+				s;
+			}));
+	size -= t;
+	next += t;
+
+	tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
+	t = scnprintf(next, size,
+			"Endpoint Setup Status Reg:" "SETUP on ep 0x%x\n\n",
+			(tmp_reg & EP_SETUP_STATUS_MASK));
+	size -= t;
+	next += t;
+
+	for (i = 0; i < udc->max_ep / 2; i++) {
+		tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
+		t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
+				i, tmp_reg);
+		size -= t;
+		next += t;
+	}
+	tmp_reg = fsl_readl(&dr_regs->endpointprime);
+	t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n", tmp_reg);
+	size -= t;
+	next += t;
+
+	if (pdata->have_sysif_regs) {
+		tmp_reg = usb_sys_regs->snoop1;
+		t = scnprintf(next, size, "\nSnoop1 Reg = [0x%x]\n\n", tmp_reg);
+		size -= t;
+		next += t;
+
+		tmp_reg = usb_sys_regs->control;
+		t = scnprintf(next, size, "General Control Reg = [0x%x]\n\n",
+				tmp_reg);
+		size -= t;
+		next += t;
+	}
+
+	/* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
+	ep = &udc->eps[0];
+	t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
+			ep->ep.name, ep_maxpacket(ep), ep_index(ep));
+	size -= t;
+	next += t;
+
+	if (list_empty(&ep->queue)) {
+		t = scnprintf(next, size, "its req queue is empty\n\n");
+		size -= t;
+		next += t;
+	} else {
+		list_for_each_entry(req, &ep->queue, queue) {
+			t = scnprintf(next, size,
+				"req %p actual 0x%x length 0x%x  buf %p\n",
+				&req->req, req->req.actual,
+				req->req.length, req->req.buf);
+			size -= t;
+			next += t;
+		}
+	}
+	/* other gadget->eplist ep */
+	list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
+		if (ep->desc) {
+			t = scnprintf(next, size,
+					"\nFor %s Maxpkt is 0x%x "
+					"index is 0x%x\n",
+					ep->ep.name, ep_maxpacket(ep),
+					ep_index(ep));
+			size -= t;
+			next += t;
+
+			if (list_empty(&ep->queue)) {
+				t = scnprintf(next, size,
+						"its req queue is empty\n\n");
+				size -= t;
+				next += t;
+			} else {
+				list_for_each_entry(req, &ep->queue, queue) {
+					t = scnprintf(next, size,
+						"req %p actual 0x%x length"
+						"0x%x  buf %p\n",
+						&req->req, req->req.actual,
+						req->req.length, req->req.buf);
+					size -= t;
+					next += t;
+				} /* end for each_entry of ep req */
+			}	/* end for else */
+		}	/* end for if(ep->queue) */
+	}		/* end (ep->desc) */
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+	dr_clk_gate(false);
+
+	*eof = 1;
+	return count - size;
+}
+
+#define create_proc_file()	create_proc_read_entry(proc_filename, \
+				0, NULL, fsl_proc_read, NULL)
+
+#define remove_proc_file()	remove_proc_entry(proc_filename, NULL)
+
+#else				/* !CONFIG_USB_GADGET_DEBUG_FILES */
+
+#define create_proc_file()	do {} while (0)
+#define remove_proc_file()	do {} while (0)
+
+#endif				/* CONFIG_USB_GADGET_DEBUG_FILES */
+
+/*-------------------------------------------------------------------------*/
+
+/* Release udc structures */
+static void fsl_udc_release(struct device *dev)
+{
+	complete(udc_controller->done);
+	dma_free_coherent(dev, udc_controller->ep_qh_size,
+			udc_controller->ep_qh, udc_controller->ep_qh_dma);
+	kfree(udc_controller);
+}
+
+/******************************************************************
+	Internal structure setup functions
+*******************************************************************/
+/*------------------------------------------------------------------
+ * init resource for globle controller
+ * Return the udc handle on success or NULL on failure
+ ------------------------------------------------------------------*/
+static int __init struct_udc_setup(struct fsl_udc *udc,
+		struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata;
+	size_t size;
+
+	pdata = pdev->dev.platform_data;
+	udc->phy_mode = pdata->phy_mode;
+
+	udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
+	if (!udc->eps) {
+		ERR("malloc fsl_ep failed\n");
+		return -1;
+	}
+
+	/* initialized QHs, take care of alignment */
+	size = udc->max_ep * sizeof(struct ep_queue_head);
+	if (size < QH_ALIGNMENT)
+		size = QH_ALIGNMENT;
+	else if ((size % QH_ALIGNMENT) != 0) {
+		size += QH_ALIGNMENT + 1;
+		size &= ~(QH_ALIGNMENT - 1);
+	}
+	udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
+					&udc->ep_qh_dma, GFP_KERNEL);
+	if (!udc->ep_qh) {
+		ERR("malloc QHs for udc failed\n");
+		kfree(udc->eps);
+		return -1;
+	}
+
+	udc->ep_qh_size = size;
+
+	/* Initialize ep0 status request structure */
+	/* FIXME: fsl_alloc_request() ignores ep argument */
+	udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
+			struct fsl_req, req);
+	/* allocate a small amount of memory to get valid address */
+	udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
+	udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
+	/* Initialize ep0 data request structure */
+	udc->data_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
+			struct fsl_req, req);
+	udc->data_req->req.buf = kmalloc(8, GFP_KERNEL);
+	udc->data_req->req.dma = virt_to_phys(udc->data_req->req.buf);
+
+	udc->resume_state = USB_STATE_NOTATTACHED;
+	udc->usb_state = USB_STATE_POWERED;
+	udc->ep0_dir = 0;
+	udc->remote_wakeup = 0;	/* default to 0 on reset */
+	spin_lock_init(&udc->lock);
+
+	return 0;
+}
+
+/*----------------------------------------------------------------
+ * Setup the fsl_ep struct for eps
+ * Link fsl_ep->ep to gadget->ep_list
+ * ep0out is not used so do nothing here
+ * ep0in should be taken care
+ *--------------------------------------------------------------*/
+static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
+		char *name, int link)
+{
+	struct fsl_ep *ep = &udc->eps[index];
+
+	ep->udc = udc;
+	strcpy(ep->name, name);
+	ep->ep.name = ep->name;
+
+	ep->ep.ops = &fsl_ep_ops;
+	ep->stopped = 0;
+
+	/* for ep0: maxP defined in desc
+	 * for other eps, maxP is set by epautoconfig() called by gadget layer
+	 */
+	ep->ep.maxpacket = (unsigned short) ~0;
+
+	/* the queue lists any req for this ep */
+	INIT_LIST_HEAD(&ep->queue);
+
+	/* gagdet.ep_list used for ep_autoconfig so no ep0 */
+	if (link)
+		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	ep->gadget = &udc->gadget;
+	ep->qh = &udc->ep_qh[index];
+
+	return 0;
+}
+
+/* Driver probe function
+ * all intialization operations implemented here except enabling usb_intr reg
+ * board setup should have been done in the platform code
+ */
+static int __init fsl_udc_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+	int ret = -ENODEV;
+	unsigned int i;
+	u32 dccparams;
+
+	udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
+	if (udc_controller == NULL) {
+		ERR("malloc udc failed\n");
+		return -ENOMEM;
+	}
+	udc_controller->pdata = pdata;
+
+#ifdef CONFIG_USB_OTG
+	/* Memory and interrupt resources will be passed from OTG */
+	udc_controller->transceiver = otg_get_transceiver();
+	if (!udc_controller->transceiver) {
+		printk(KERN_ERR "Can't find OTG driver!\n");
+		ret = -ENODEV;
+		goto err1a;
+	}
+	udc_controller->gadget.is_otg = 1;
+#endif
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ret = -ENXIO;
+		goto err1a;
+	}
+
+#ifndef CONFIG_USB_OTG
+	if (!request_mem_region(res->start, resource_size(res),
+				driver_name)) {
+		ERR("request mem region for %s failed \n", pdev->name);
+		ret = -EBUSY;
+		goto err1a;
+	}
+#endif
+	dr_regs = ioremap(res->start, resource_size(res));
+	if (!dr_regs) {
+		ret = -ENOMEM;
+		goto err1;
+	}
+	pdata->regs = (void *)dr_regs;
+	/*
+	 * do platform specific init: check the clock, grab/config pins, etc.
+	 */
+	if (pdata->init && pdata->init(pdev)) {
+		ret = -ENODEV;
+		goto err2a;
+	}
+
+	/* Due to mx35/mx25's phy's bug */
+	reset_phy();
+
+	if (pdata->have_sysif_regs)
+		usb_sys_regs = (struct usb_sys_interface *)
+				((u32)dr_regs + USB_DR_SYS_OFFSET);
+
+	/* Read Device Controller Capability Parameters register */
+	dccparams = fsl_readl(&dr_regs->dccparams);
+	if (!(dccparams & DCCPARAMS_DC)) {
+		ERR("This SOC doesn't support device role\n");
+		ret = -ENODEV;
+		goto err2;
+	}
+	/* Get max device endpoints */
+	/* DEN is bidirectional ep number, max_ep doubles the number */
+	udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
+
+	udc_controller->irq = platform_get_irq(pdev, 0);
+	if (!udc_controller->irq) {
+		ret = -ENODEV;
+		goto err2;
+	}
+
+	ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
+			driver_name, udc_controller);
+	if (ret != 0) {
+		ERR("cannot request irq %d err %d \n",
+				udc_controller->irq, ret);
+		goto err2;
+	}
+
+	/* Initialize the udc structure including QH member and other member */
+	if (struct_udc_setup(udc_controller, pdev)) {
+		ERR("Can't initialize udc data structure\n");
+		ret = -ENOMEM;
+		goto err3;
+	}
+
+	if (!udc_controller->transceiver) {
+		/* initialize usb hw reg except for regs for EP,
+		 * leave usbintr reg untouched */
+		dr_controller_setup(udc_controller);
+	}
+
+	/* Setup gadget structure */
+	udc_controller->gadget.ops = &fsl_gadget_ops;
+	udc_controller->gadget.is_dualspeed = 1;
+	udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
+	INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
+	udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
+	udc_controller->gadget.name = driver_name;
+
+	/* Setup gadget.dev and register with kernel */
+	dev_set_name(&udc_controller->gadget.dev, "gadget");
+	udc_controller->gadget.dev.release = fsl_udc_release;
+	udc_controller->gadget.dev.parent = &pdev->dev;
+	ret = device_register(&udc_controller->gadget.dev);
+	if (ret < 0)
+		goto err3;
+
+	/* setup QH and epctrl for ep0 */
+	ep0_setup(udc_controller);
+
+	/* setup udc->eps[] for ep0 */
+	struct_ep_setup(udc_controller, 0, "ep0", 0);
+	/* for ep0: the desc defined here;
+	 * for other eps, gadget layer called ep_enable with defined desc
+	 */
+	udc_controller->eps[0].desc = &fsl_ep0_desc;
+	udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
+
+	/* setup the udc->eps[] for non-control endpoints and link
+	 * to gadget.ep_list */
+	for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
+		char name[14];
+
+		sprintf(name, "ep%dout", i);
+		struct_ep_setup(udc_controller, i * 2, name, 1);
+		sprintf(name, "ep%din", i);
+		struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
+	}
+
+	/* use dma_pool for TD management */
+	udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
+			sizeof(struct ep_td_struct),
+			DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
+	if (udc_controller->td_pool == NULL) {
+		ret = -ENOMEM;
+		goto err4;
+	}
+	if (g_iram_size) {
+		g_iram_addr = iram_alloc(USB_IRAM_SIZE, &g_iram_base);
+		for (i = 0; i < IRAM_PPH_NTD; i++) {
+			udc_controller->iram_buffer[i] =
+				g_iram_base + i * g_iram_size;
+			udc_controller->iram_buffer_v[i] =
+				g_iram_addr + i * g_iram_size;
+		}
+	}
+
+	INIT_WORK(&udc_controller->gadget_work, fsl_gadget_event);
+	INIT_DELAYED_WORK(&udc_controller->gadget_delay_work,
+						fsl_gadget_delay_event);
+#ifdef POSTPONE_FREE_LAST_DTD
+	last_free_td = NULL;
+#endif
+
+	/* disable all INTR */
+#ifndef CONFIG_USB_OTG
+	fsl_writel(0, &dr_regs->usbintr);
+	dr_wake_up_enable(udc_controller, false);
+#else
+	dr_wake_up_enable(udc_controller, true);
+#endif
+
+/*
+ * As mx25/mx35 does not implement clk_gate, should not let phy to low
+ * power mode due to IC bug
+ */
+#if !(defined CONFIG_ARCH_MX35 || defined CONFIG_ARCH_MX25)
+{
+	dr_phy_low_power_mode(udc_controller, true);
+}
+#endif
+	udc_controller->stopped = 1;
+
+	/* let the gadget register function open the clk */
+	dr_clk_gate(false);
+
+	create_proc_file();
+
+	ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
+	if (!ret)
+		return ret;
+
+	remove_proc_file();
+err4:
+	device_unregister(&udc_controller->gadget.dev);
+err3:
+	free_irq(udc_controller->irq, udc_controller);
+err2:
+	if (pdata->exit)
+		pdata->exit(pdata->pdev);
+err2a:
+	iounmap((u8 __iomem *)dr_regs);
+err1:
+	if (!udc_controller->transceiver)
+		release_mem_region(res->start, resource_size(res));
+err1a:
+	kfree(udc_controller);
+	udc_controller = NULL;
+	return ret;
+}
+
+/* Driver removal function
+ * Free resources and finish pending transactions
+ */
+static int __exit fsl_udc_remove(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	DECLARE_COMPLETION(done);
+
+	usb_del_gadget_udc(&udc_controller->gadget);
+
+	if (!udc_controller)
+		return -ENODEV;
+	udc_controller->done = &done;
+	/* open USB PHY clock */
+	if (udc_controller->stopped)
+		dr_clk_gate(true);
+
+	/* DR has been stopped in usb_gadget_unregister_driver() */
+	remove_proc_file();
+
+	/* Free allocated memory */
+	if (g_iram_size)
+		iram_free(g_iram_base, IRAM_PPH_NTD * g_iram_size);
+	kfree(udc_controller->status_req->req.buf);
+	kfree(udc_controller->status_req);
+	kfree(udc_controller->data_req->req.buf);
+	kfree(udc_controller->data_req);
+	kfree(udc_controller->eps);
+#ifdef POSTPONE_FREE_LAST_DTD
+	if (last_free_td != NULL)
+		dma_pool_free(udc_controller->td_pool, last_free_td,
+				last_free_td->td_dma);
+#endif
+	dma_pool_destroy(udc_controller->td_pool);
+	free_irq(udc_controller->irq, udc_controller);
+	iounmap((u8 __iomem *)dr_regs);
+
+#ifndef CONFIG_USB_OTG
+{
+	struct resource *res;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, resource_size(res));
+}
+#endif
+
+	device_unregister(&udc_controller->gadget.dev);
+	/* free udc --wait for the release() finished */
+	wait_for_completion(&done);
+
+	/*
+	 * do platform specific un-initialization:
+	 * release iomux pins, etc.
+	 */
+	if (pdata->exit)
+		pdata->exit(pdata->pdev);
+
+	if (udc_controller->stopped)
+		dr_clk_gate(false);
+	return 0;
+}
+
+static bool udc_can_wakeup_system(void)
+{
+	struct fsl_usb2_platform_data *pdata = udc_controller->pdata;
+
+	if (pdata->operating_mode == FSL_USB2_DR_OTG)
+		if (device_may_wakeup(udc_controller->transceiver->dev))
+			return true;
+		else
+			return false;
+	else
+		if (device_may_wakeup(udc_controller->gadget.dev.parent))
+			return true;
+		else
+			return false;
+}
+
+static int udc_suspend(struct fsl_udc *udc)
+{
+	struct fsl_usb2_platform_data *pdata = udc_controller->pdata;
+	u32 mode, usbcmd;
+
+	/*
+	 * When it is the PM suspend routine and the device has no
+	 * abilities to wakeup system, it should not set wakeup enable.
+	 * Otherwise, the system will wakeup even the user only wants to
+	 * charge using usb
+	 */
+	printk(KERN_DEBUG "udc suspend begins\n");
+	if (pdata->pmflags == 0) {
+		if (!udc_can_wakeup_system())
+			dr_wake_up_enable(udc, false);
+		else
+			dr_wake_up_enable(udc, true);
+	}
+
+	mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
+	usbcmd = fsl_readl(&dr_regs->usbcmd);
+
+	/*
+	 * If the controller is already stopped, then this must be a
+	 * PM suspend.  Remember this fact, so that we will leave the
+	 * controller stopped at PM resume time.
+	 */
+	if (udc->suspended) {
+		printk(KERN_DEBUG "gadget already suspended, leaving early\n");
+		goto out;
+	}
+
+	if (mode != USB_MODE_CTRL_MODE_DEVICE) {
+		printk(KERN_DEBUG "gadget not in device mode, leaving early\n");
+		goto out;
+	}
+
+	/* Comment udc_wait_b_session_low, uncomment it at below two
+	 * situations:
+	 * 1. the user wants to debug some problems about vbus
+	 * 2. the vbus discharges very slow at user's board
+	 */
+
+	/* For some buggy hardware designs, see comment of this function for detail */
+	/* udc_wait_b_session_low(); */
+
+	udc->stopped = 1;
+
+	/* stop the controller */
+	usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
+	fsl_writel(usbcmd, &dr_regs->usbcmd);
+
+	dr_phy_low_power_mode(udc, true);
+	printk(KERN_DEBUG "USB Gadget suspend ends\n");
+out:
+	udc->suspended++;
+	if (udc->suspended > 2)
+		printk(KERN_ERR "ERROR: suspended times > 2\n");
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------
+ * Modify Power management attributes
+ * Used by OTG statemachine to disable gadget temporarily
+ -----------------------------------------------------------------*/
+static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	int ret;
+#ifdef CONFIG_USB_OTG
+	if (udc_controller->transceiver->gadget == NULL)
+		return 0;
+#endif
+	if (udc_controller->stopped)
+		dr_clk_gate(true);
+	if (((!(udc_controller->gadget.is_otg)) ||
+		(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) &&
+			(udc_controller->usb_state > USB_STATE_POWERED) &&
+			(udc_controller->usb_state < USB_STATE_SUSPENDED)) {
+		return -EBUSY;/* keep the clk on */
+	} else
+		ret = udc_suspend(udc_controller);
+	dr_clk_gate(false);
+
+	return ret;
+}
+
+/*-----------------------------------------------------------------
+ * Invoked on USB resume. May be called in_interrupt.
+ * Here we start the DR controller and enable the irq
+ *-----------------------------------------------------------------*/
+static int fsl_udc_resume(struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata = udc_controller->pdata;
+	struct fsl_usb2_wakeup_platform_data *wake_up_pdata = pdata->wakeup_pdata;
+	printk(KERN_DEBUG "USB Gadget resume begins\n");
+
+	if (pdata->pmflags == 0) {
+		printk(KERN_DEBUG "%s, Wait for wakeup thread finishes\n", __func__);
+		wait_event_interruptible(wake_up_pdata->wq, !wake_up_pdata->usb_wakeup_is_pending);
+	}
+
+#ifdef CONFIG_USB_OTG
+	if (udc_controller->transceiver->gadget == NULL) {
+		return 0;
+	}
+#endif
+	mutex_lock(&udc_resume_mutex);
+
+	pr_debug("%s(): stopped %d  suspended %d\n", __func__,
+		 udc_controller->stopped, udc_controller->suspended);
+	/* Do noop if the udc is already at resume state */
+	if (udc_controller->suspended == 0) {
+		mutex_unlock(&udc_resume_mutex);
+		return 0;
+	}
+
+	/*
+	 * If the controller was stopped at suspend time, then
+	 * don't resume it now.
+	 */
+
+	if (udc_controller->suspended > 1) {
+		printk(KERN_DEBUG "gadget was already stopped, leaving early\n");
+		if (udc_controller->stopped) {
+			dr_clk_gate(true);
+		}
+		goto end;
+	}
+
+	/* Enable DR irq reg and set controller Run */
+	if (udc_controller->stopped) {
+		/* the clock is already on at usb wakeup routine */
+		if (pdata->lowpower)
+			dr_clk_gate(true);
+		dr_wake_up_enable(udc_controller, false);
+		dr_phy_low_power_mode(udc_controller, false);
+		usb_debounce_id_vbus();
+		/* if in host mode, we need to do nothing */
+		if ((fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID) == 0) {
+			dr_phy_low_power_mode(udc_controller, true);
+			dr_wake_up_enable(udc_controller, true);
+			goto end;
+		}
+		dr_controller_setup(udc_controller);
+		dr_controller_run(udc_controller);
+	}
+	udc_controller->usb_state = USB_STATE_ATTACHED;
+	udc_controller->ep0_dir = 0;
+
+end:
+	/* if udc is resume by otg id change and no device
+	 * connecting to the otg, otg will enter low power mode*/
+	if (udc_controller->stopped) {
+		/*
+		 * If it is PM resume routine, the udc is at low power mode,
+		 * and the udc has no abilities to wakeup system, it should
+		 * set the abilities to wakeup itself. Otherwise, the usb
+		 * subsystem will not leave from low power mode.
+		 */
+		if (!udc_can_wakeup_system() &&
+			(pdata->pmflags == 0)) {
+			dr_wake_up_enable(udc_controller, true);
+		}
+
+		dr_clk_gate(false);
+	}
+	--udc_controller->suspended;
+	mutex_unlock(&udc_resume_mutex);
+	printk(KERN_DEBUG "USB Gadget resume ends\n");
+	return 0;
+}
+
+/*-------------------------------------------------------------------------
+	Register entry point for the peripheral controller driver
+--------------------------------------------------------------------------*/
+
+static struct platform_driver udc_driver = {
+	.remove  = __exit_p(fsl_udc_remove),
+	/* these suspend and resume are not usb suspend and resume */
+	.suspend = fsl_udc_suspend,
+	.resume  = fsl_udc_resume,
+	.probe = fsl_udc_probe,
+	.driver  = {
+		.name = driver_name,
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init udc_init(void)
+{
+	printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
+	return platform_driver_register(&udc_driver);
+}
+#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
+	fs_initcall(udc_init);
+#else
+	module_init(udc_init);
+#endif
+static void __exit udc_exit(void)
+{
+	platform_driver_unregister(&udc_driver);
+	printk(KERN_INFO "%s unregistered \n", driver_desc);
+}
+
+module_exit(udc_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/gadget/arcotg_udc.h b/drivers/usb/gadget/arcotg_udc.h
new file mode 100644
index 00000000000..bc88afb360c
--- /dev/null
+++ b/drivers/usb/gadget/arcotg_udc.h
@@ -0,0 +1,712 @@
+/*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @file arcotg_udc.h
+ * @brief Freescale USB device/endpoint management registers
+ * @ingroup USB
+ */
+
+#ifndef __ARCOTG_UDC_H
+#define __ARCOTG_UDC_H
+
+#define TRUE 1
+#define FALSE 0
+
+#define MSC_BULK_CB_WRAP_LEN 31
+#define USE_MSC_WR(len) false
+
+/* Iram patch */
+#ifdef CONFIG_USB_STATIC_IRAM_PPH
+/* size of 1 qTD's buffer,one is for BULK IN and other is BULK OUT */
+#define USB_IRAM_SIZE		SZ_8K
+#define IRAM_TD_PPH_SIZE	(USB_IRAM_SIZE / 2)
+#define IRAM_PPH_NTD	2	/* number of TDs in IRAM  */
+#else
+#define USB_IRAM_SIZE		0
+#define IRAM_TD_PPH_SIZE	0
+#define IRAM_PPH_NTD	0
+#endif
+
+#define NEED_IRAM(ep) ((g_iram_size) && \
+	((ep)->desc->bmAttributes == USB_ENDPOINT_XFER_BULK))
+
+#ifdef CONFIG_ARCH_MX5
+#define POSTPONE_FREE_LAST_DTD
+#else
+#undef POSTPONE_FREE_LAST_DTD
+#endif
+
+/* ### define USB registers here
+ */
+#define USB_MAX_ENDPOINTS		8
+#define USB_MAX_PIPES			(USB_MAX_ENDPOINTS*2)
+#define USB_MAX_CTRL_PAYLOAD		64
+#define	USB_DR_SYS_OFFSET		0x400
+
+#define	USB_DR_OFFSET	0x3100
+
+struct usb_dr_device {
+	/* Capability register */
+	u32 id;
+	u32 res1[35];
+	u32 sbuscfg;		/* sbuscfg ahb burst */
+	u32 res11[27];
+	u16 caplength;		/* Capability Register Length */
+	u16 hciversion;		/* Host Controller Interface Version */
+	u32 hcsparams;		/* Host Controller Structual Parameters */
+	u32 hccparams;		/* Host Controller Capability Parameters */
+	u32 res2[5];
+	u32 dciversion;		/* Device Controller Interface Version */
+	u32 dccparams;		/* Device Controller Capability Parameters */
+	u32 res3[6];
+	/* Operation register */
+	u32 usbcmd;		/* USB Command Register */
+	u32 usbsts;		/* USB Status Register */
+	u32 usbintr;		/* USB Interrupt Enable Register */
+	u32 frindex;		/* Frame Index Register */
+	u32 res4;
+	u32 deviceaddr;		/* Device Address */
+	u32 endpointlistaddr;	/* Endpoint List Address Register */
+	u32 res5;
+	u32 burstsize;		/* Master Interface Data Burst Size Register */
+	u32 txttfilltuning;	/* Transmit FIFO Tuning Controls Register */
+	u32 res6[6];
+	u32 configflag;		/* Configure Flag Register */
+	u32 portsc1;		/* Port 1 Status and Control Register */
+	u32 res7[7];
+	u32 otgsc;		/* On-The-Go Status and Control */
+	u32 usbmode;		/* USB Mode Register */
+	u32 endptsetupstat;	/* Endpoint Setup Status Register */
+	u32 endpointprime;	/* Endpoint Initialization Register */
+	u32 endptflush;		/* Endpoint Flush Register */
+	u32 endptstatus;	/* Endpoint Status Register */
+	u32 endptcomplete;	/* Endpoint Complete Register */
+	u32 endptctrl[8 * 2];	/* Endpoint Control Registers */
+	u32 res8[256];
+#ifdef CONFIG_ARCH_MX5
+	u32 res9[128];		/* i.MX51 start from 0x800 */
+#endif
+	u32 usbctrl;
+	u32 otgmirror;
+	u32 phyctrl0;
+	u32 phyctrl1;
+	u32 ctrl1;
+	u32 uh2ctrl;
+};
+
+ /* non-EHCI USB system interface registers (Big Endian) */
+struct usb_sys_interface {
+	u32 snoop1;
+	u32 snoop2;
+	u32 age_cnt_thresh;	/* Age Count Threshold Register */
+	u32 pri_ctrl;		/* Priority Control Register */
+	u32 si_ctrl;		/* System Interface Control Register */
+	u8 res[236];
+	u32 control;		/* General Purpose Control Register */
+};
+
+/* ep0 transfer state */
+#define WAIT_FOR_SETUP          0
+#define DATA_STATE_XMIT         1
+#define DATA_STATE_NEED_ZLP     2
+#define WAIT_FOR_OUT_STATUS     3
+#define DATA_STATE_RECV         4
+
+/* Device Controller Capability Parameter register */
+#define DCCPARAMS_DC				0x00000080
+#define DCCPARAMS_DEN_MASK			0x0000001f
+
+/* Frame Index Register Bit Masks */
+#define	USB_FRINDEX_MASKS			(0x3fff)
+/* USB CMD  Register Bit Masks */
+#define  USB_CMD_RUN_STOP                     (0x00000001)
+#define  USB_CMD_CTRL_RESET                   (0x00000002)
+#define  USB_CMD_PERIODIC_SCHEDULE_EN         (0x00000010)
+#define  USB_CMD_ASYNC_SCHEDULE_EN            (0x00000020)
+#define  USB_CMD_INT_AA_DOORBELL              (0x00000040)
+#define  USB_CMD_ASP                          (0x00000300)
+#define  USB_CMD_ASYNC_SCH_PARK_EN            (0x00000800)
+#define  USB_CMD_SUTW                         (0x00002000)
+#define  USB_CMD_ATDTW                        (0x00004000)
+#define  USB_CMD_ITC                          (0x00FF0000)
+
+/* bit 15,3,2 are frame list size */
+#define  USB_CMD_FRAME_SIZE_1024              (0x00000000)
+#define  USB_CMD_FRAME_SIZE_512               (0x00000004)
+#define  USB_CMD_FRAME_SIZE_256               (0x00000008)
+#define  USB_CMD_FRAME_SIZE_128               (0x0000000C)
+#define  USB_CMD_FRAME_SIZE_64                (0x00008000)
+#define  USB_CMD_FRAME_SIZE_32                (0x00008004)
+#define  USB_CMD_FRAME_SIZE_16                (0x00008008)
+#define  USB_CMD_FRAME_SIZE_8                 (0x0000800C)
+
+/* bit 9-8 are async schedule park mode count */
+#define  USB_CMD_ASP_00                       (0x00000000)
+#define  USB_CMD_ASP_01                       (0x00000100)
+#define  USB_CMD_ASP_10                       (0x00000200)
+#define  USB_CMD_ASP_11                       (0x00000300)
+#define  USB_CMD_ASP_BIT_POS                  (8)
+
+/* bit 23-16 are interrupt threshold control */
+#define  USB_CMD_ITC_NO_THRESHOLD             (0x00000000)
+#define  USB_CMD_ITC_1_MICRO_FRM              (0x00010000)
+#define  USB_CMD_ITC_2_MICRO_FRM              (0x00020000)
+#define  USB_CMD_ITC_4_MICRO_FRM              (0x00040000)
+#define  USB_CMD_ITC_8_MICRO_FRM              (0x00080000)
+#define  USB_CMD_ITC_16_MICRO_FRM             (0x00100000)
+#define  USB_CMD_ITC_32_MICRO_FRM             (0x00200000)
+#define  USB_CMD_ITC_64_MICRO_FRM             (0x00400000)
+#define  USB_CMD_ITC_BIT_POS                  (16)
+
+/* USB STS Register Bit Masks */
+#define  USB_STS_INT                          (0x00000001)
+#define  USB_STS_ERR                          (0x00000002)
+#define  USB_STS_PORT_CHANGE                  (0x00000004)
+#define  USB_STS_FRM_LST_ROLL                 (0x00000008)
+#define  USB_STS_SYS_ERR                      (0x00000010)
+#define  USB_STS_IAA                          (0x00000020)
+#define  USB_STS_RESET                        (0x00000040)
+#define  USB_STS_SOF                          (0x00000080)
+#define  USB_STS_SUSPEND                      (0x00000100)
+#define  USB_STS_HC_HALTED                    (0x00001000)
+#define  USB_STS_RCL                          (0x00002000)
+#define  USB_STS_PERIODIC_SCHEDULE            (0x00004000)
+#define  USB_STS_ASYNC_SCHEDULE               (0x00008000)
+
+/* USB INTR Register Bit Masks */
+#define  USB_INTR_INT_EN                      (0x00000001)
+#define  USB_INTR_ERR_INT_EN                  (0x00000002)
+#define  USB_INTR_PTC_DETECT_EN               (0x00000004)
+#define  USB_INTR_FRM_LST_ROLL_EN             (0x00000008)
+#define  USB_INTR_SYS_ERR_EN                  (0x00000010)
+#define  USB_INTR_ASYN_ADV_EN                 (0x00000020)
+#define  USB_INTR_RESET_EN                    (0x00000040)
+#define  USB_INTR_SOF_EN                      (0x00000080)
+#define  USB_INTR_DEVICE_SUSPEND              (0x00000100)
+
+/* Device Address bit masks */
+#define  USB_DEVICE_ADDRESS_MASK              (0xFE000000)
+#define  USB_DEVICE_ADDRESS_BIT_POS           (25)
+
+/* endpoint list address bit masks */
+#define USB_EP_LIST_ADDRESS_MASK              (0xfffff800)
+
+/* PORTSCX  Register Bit Masks */
+#define  PORTSCX_CURRENT_CONNECT_STATUS       (0x00000001)
+#define  PORTSCX_CONNECT_STATUS_CHANGE        (0x00000002)
+#define  PORTSCX_PORT_ENABLE                  (0x00000004)
+#define  PORTSCX_PORT_EN_DIS_CHANGE           (0x00000008)
+#define  PORTSCX_OVER_CURRENT_ACT             (0x00000010)
+#define  PORTSCX_OVER_CURRENT_CHG             (0x00000020)
+#define  PORTSCX_PORT_FORCE_RESUME            (0x00000040)
+#define  PORTSCX_PORT_SUSPEND                 (0x00000080)
+#define  PORTSCX_PORT_RESET                   (0x00000100)
+#define  PORTSCX_LINE_STATUS_BITS             (0x00000C00)
+#define  PORTSCX_PORT_POWER                   (0x00001000)
+#define  PORTSCX_PORT_INDICTOR_CTRL           (0x0000C000)
+#define  PORTSCX_PORT_TEST_CTRL               (0x000F0000)
+#define  PORTSCX_WAKE_ON_CONNECT_EN           (0x00100000)
+#define  PORTSCX_WAKE_ON_CONNECT_DIS          (0x00200000)
+#define  PORTSCX_WAKE_ON_OVER_CURRENT         (0x00400000)
+#define  PORTSCX_PHY_LOW_POWER_SPD            (0x00800000)
+#define  PORTSCX_PORT_FORCE_FULL_SPEED        (0x01000000)
+#define  PORTSCX_PORT_SPEED_MASK              (0x0C000000)
+#define  PORTSCX_PORT_WIDTH                   (0x10000000)
+#define  PORTSCX_PHY_TYPE_SEL                 (0xC0000000)
+
+/* bit 11-10 are line status */
+#define  PORTSCX_LINE_STATUS_SE0              (0x00000000)
+#define  PORTSCX_LINE_STATUS_JSTATE           (0x00000400)
+#define  PORTSCX_LINE_STATUS_KSTATE           (0x00000800)
+#define  PORTSCX_LINE_STATUS_UNDEF            (0x00000C00)
+#define  PORTSCX_LINE_STATUS_BIT_POS          (10)
+
+/* bit 15-14 are port indicator control */
+#define  PORTSCX_PIC_OFF                      (0x00000000)
+#define  PORTSCX_PIC_AMBER                    (0x00004000)
+#define  PORTSCX_PIC_GREEN                    (0x00008000)
+#define  PORTSCX_PIC_UNDEF                    (0x0000C000)
+#define  PORTSCX_PIC_BIT_POS                  (14)
+
+/* bit 19-16 are port test control */
+#define  PORTSCX_PTC_DISABLE                  (0x00000000)
+#define  PORTSCX_PTC_JSTATE                   (0x00010000)
+#define  PORTSCX_PTC_KSTATE                   (0x00020000)
+#define  PORTSCX_PTC_SEQNAK                   (0x00030000)
+#define  PORTSCX_PTC_PACKET                   (0x00040000)
+#define  PORTSCX_PTC_FORCE_EN                 (0x00050000)
+#define  PORTSCX_PTC_BIT_POS                  (16)
+
+/* bit 27-26 are port speed */
+#define  PORTSCX_PORT_SPEED_FULL              (0x00000000)
+#define  PORTSCX_PORT_SPEED_LOW               (0x04000000)
+#define  PORTSCX_PORT_SPEED_HIGH              (0x08000000)
+#define  PORTSCX_PORT_SPEED_UNDEF             (0x0C000000)
+#define  PORTSCX_SPEED_BIT_POS                (26)
+
+/* OTGSC Register Bit Masks */
+#define  OTGSC_ID_CHANGE_IRQ_STS		(1 << 16)
+#define  OTGSC_B_SESSION_VALID_IRQ_EN           (1 << 27)
+#define  OTGSC_B_SESSION_VALID_IRQ_STS          (1 << 19)
+#define  OTGSC_B_SESSION_VALID                  (1 << 11)
+
+/* bit 28 is parallel transceiver width for UTMI interface */
+#define  PORTSCX_PTW                          (0x10000000)
+#define  PORTSCX_PTW_8BIT                     (0x00000000)
+#define  PORTSCX_PTW_16BIT                    (0x10000000)
+
+/* bit 31-30 are port transceiver select */
+#define  PORTSCX_PTS_UTMI                     (0x00000000)
+#define  PORTSCX_PTS_ULPI                     (0x80000000)
+#define  PORTSCX_PTS_FSLS                     (0xC0000000)
+#define  PORTSCX_PTS_BIT_POS                  (30)
+
+/* USB MODE Register Bit Masks */
+#define  USB_MODE_CTRL_MODE_IDLE              (0x00000000)
+#define  USB_MODE_CTRL_MODE_DEVICE            (0x00000002)
+#define  USB_MODE_CTRL_MODE_HOST              (0x00000003)
+#define  USB_MODE_CTRL_MODE_MASK              0x00000003
+#define  USB_MODE_CTRL_MODE_RSV               (0x00000001)
+#define  USB_MODE_ES                          0x00000004 /* (big) Endian Sel */
+#define  USB_MODE_SETUP_LOCK_OFF              (0x00000008)
+#define  USB_MODE_STREAM_DISABLE              (0x00000010)
+/* Endpoint Flush Register */
+#define EPFLUSH_TX_OFFSET		      (0x00010000)
+#define EPFLUSH_RX_OFFSET		      (0x00000000)
+
+/* Endpoint Setup Status bit masks */
+#define  EP_SETUP_STATUS_MASK                 (0x0000003F)
+#define  EP_SETUP_STATUS_EP0		      (0x00000001)
+
+/* ENDPOINTCTRLx  Register Bit Masks */
+#define  EPCTRL_TX_ENABLE                     (0x00800000)
+#define  EPCTRL_TX_DATA_TOGGLE_RST            (0x00400000)	/* Not EP0 */
+#define  EPCTRL_TX_DATA_TOGGLE_INH            (0x00200000)	/* Not EP0 */
+#define  EPCTRL_TX_TYPE                       (0x000C0000)
+#define  EPCTRL_TX_DATA_SOURCE                (0x00020000)	/* Not EP0 */
+#define  EPCTRL_TX_EP_STALL                   (0x00010000)
+#define  EPCTRL_RX_ENABLE                     (0x00000080)
+#define  EPCTRL_RX_DATA_TOGGLE_RST            (0x00000040)	/* Not EP0 */
+#define  EPCTRL_RX_DATA_TOGGLE_INH            (0x00000020)	/* Not EP0 */
+#define  EPCTRL_RX_TYPE                       (0x0000000C)
+#define  EPCTRL_RX_DATA_SINK                  (0x00000002)	/* Not EP0 */
+#define  EPCTRL_RX_EP_STALL                   (0x00000001)
+
+/* bit 19-18 and 3-2 are endpoint type */
+#define  EPCTRL_EP_TYPE_CONTROL               (0)
+#define  EPCTRL_EP_TYPE_ISO                   (1)
+#define  EPCTRL_EP_TYPE_BULK                  (2)
+#define  EPCTRL_EP_TYPE_INTERRUPT             (3)
+#define  EPCTRL_TX_EP_TYPE_SHIFT              (18)
+#define  EPCTRL_RX_EP_TYPE_SHIFT              (2)
+
+/* SNOOPn Register Bit Masks */
+#define  SNOOP_ADDRESS_MASK                   (0xFFFFF000)
+#define  SNOOP_SIZE_ZERO                      (0x00)	/* snooping disable */
+#define  SNOOP_SIZE_4KB                       (0x0B)	/* 4KB snoop size */
+#define  SNOOP_SIZE_8KB                       (0x0C)
+#define  SNOOP_SIZE_16KB                      (0x0D)
+#define  SNOOP_SIZE_32KB                      (0x0E)
+#define  SNOOP_SIZE_64KB                      (0x0F)
+#define  SNOOP_SIZE_128KB                     (0x10)
+#define  SNOOP_SIZE_256KB                     (0x11)
+#define  SNOOP_SIZE_512KB                     (0x12)
+#define  SNOOP_SIZE_1MB                       (0x13)
+#define  SNOOP_SIZE_2MB                       (0x14)
+#define  SNOOP_SIZE_4MB                       (0x15)
+#define  SNOOP_SIZE_8MB                       (0x16)
+#define  SNOOP_SIZE_16MB                      (0x17)
+#define  SNOOP_SIZE_32MB                      (0x18)
+#define  SNOOP_SIZE_64MB                      (0x19)
+#define  SNOOP_SIZE_128MB                     (0x1A)
+#define  SNOOP_SIZE_256MB                     (0x1B)
+#define  SNOOP_SIZE_512MB                     (0x1C)
+#define  SNOOP_SIZE_1GB                       (0x1D)
+#define  SNOOP_SIZE_2GB                       (0x1E)	/* 2GB snoop size */
+
+/* pri_ctrl Register Bit Masks */
+#define  PRI_CTRL_PRI_LVL1                    (0x0000000C)
+#define  PRI_CTRL_PRI_LVL0                    (0x00000003)
+
+/* si_ctrl Register Bit Masks */
+#define  SI_CTRL_ERR_DISABLE                  (0x00000010)
+#define  SI_CTRL_IDRC_DISABLE                 (0x00000008)
+#define  SI_CTRL_RD_SAFE_EN                   (0x00000004)
+#define  SI_CTRL_RD_PREFETCH_DISABLE          (0x00000002)
+#define  SI_CTRL_RD_PREFEFETCH_VAL            (0x00000001)
+
+/* control Register Bit Masks */
+#define  USB_CTRL_IOENB                       (0x00000004)
+#define  USB_CTRL_ULPI_INT0EN                 (0x00000001)
+#define  USB_CTRL_OTG_WUIR                   (0x80000000)
+#define  USB_CTRL_OTG_WUIE                   (0x08000000)
+#define  USB_CTRL_OTG_VWUE			(0x00001000)
+#define  USB_CTRL_OTG_IWUE			(0x00100000)
+
+/* PHY control0 Register Bit Masks */
+#define	PHY_CTRL0_CONF2			(1 << 26)
+#define PHY_CTRL0_USBEN			(1 << 24) /* USB UTMI PHY Enable */
+
+/* USB UH2 CTRL Register Bits */
+#define USB_UH2_OVBWK_EN		(1 << 6) /* OTG VBUS Wakeup Enable */
+#define USB_UH2_OIDWK_EN		(1 << 5) /* OTG ID Wakeup Enable */
+/*!
+ * Endpoint Queue Head data struct
+ * Rem: all the variables of qh are LittleEndian Mode
+ * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr
+ */
+struct ep_queue_head {
+	/*!
+	 * Mult(31-30) , Zlt(29) , Max Pkt len  and IOS(15)
+	 */
+	u32 max_pkt_length;
+
+	/*!
+	 *  Current dTD Pointer(31-5)
+	 */
+	u32 curr_dtd_ptr;
+
+	/*!
+	 *  Next dTD Pointer(31-5), T(0)
+	 */
+	u32 next_dtd_ptr;
+
+	/*!
+	 *  Total bytes (30-16), IOC (15), MultO(11-10), STS (7-0)
+	 */
+	u32 size_ioc_int_sts;
+
+	/*!
+	 * Buffer pointer Page 0 (31-12)
+	 */
+	u32 buff_ptr0;
+
+	/*!
+	 * Buffer pointer Page 1 (31-12)
+	 */
+	u32 buff_ptr1;
+
+	/*!
+	 * Buffer pointer Page 2 (31-12)
+	 */
+	u32 buff_ptr2;
+
+	/*!
+	 * Buffer pointer Page 3 (31-12)
+	 */
+	u32 buff_ptr3;
+
+	/*!
+	 * Buffer pointer Page 4 (31-12)
+	 */
+	u32 buff_ptr4;
+
+	/*!
+	 * reserved field 1
+	 */
+	u32 res1;
+	/*!
+	 * Setup data 8 bytes
+	 */
+	u8 setup_buffer[8];	/* Setup data 8 bytes */
+
+	/*!
+	 * reserved field 2,pad out to 64 bytes
+	 */
+	u32 res2[4];
+};
+
+/* Endpoint Queue Head Bit Masks */
+#define  EP_QUEUE_HEAD_MULT_POS               (30)
+#define  EP_QUEUE_HEAD_ZLT_SEL                (0x20000000)
+#define  EP_QUEUE_HEAD_MAX_PKT_LEN_POS        (16)
+#define  EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info)   (((ep_info)>>16)&0x07ff)
+#define  EP_QUEUE_HEAD_IOS                    (0x00008000)
+#define  EP_QUEUE_HEAD_NEXT_TERMINATE         (0x00000001)
+#define  EP_QUEUE_HEAD_IOC                    (0x00008000)
+#define  EP_QUEUE_HEAD_MULTO                  (0x00000C00)
+#define  EP_QUEUE_HEAD_STATUS_HALT	      (0x00000040)
+#define  EP_QUEUE_HEAD_STATUS_ACTIVE          (0x00000080)
+#define  EP_QUEUE_CURRENT_OFFSET_MASK         (0x00000FFF)
+#define  EP_QUEUE_HEAD_NEXT_POINTER_MASK      0xFFFFFFE0
+#define  EP_QUEUE_FRINDEX_MASK                (0x000007FF)
+#define  EP_MAX_LENGTH_TRANSFER               (0x4000)
+
+/*!
+ * Endpoint Transfer Descriptor data struct
+ *  Rem: all the variables of td are LittleEndian Mode
+ *       must be 32-byte aligned
+ */
+struct ep_td_struct {
+	/*!
+	 *  Next TD pointer(31-5), T(0) set indicate invalid
+	 */
+	u32 next_td_ptr;
+
+	/*!
+	 *  Total bytes (30-16), IOC (15),MultO(11-10), STS (7-0)
+	 */
+	u32 size_ioc_sts;
+
+	/*!
+	 * Buffer pointer Page 0
+	 */
+	u32 buff_ptr0;
+
+	/*!
+	 * Buffer pointer Page 1
+	 */
+	u32 buff_ptr1;
+
+	/*!
+	 * Buffer pointer Page 2
+	 */
+	u32 buff_ptr2;
+
+	/*!
+	 * Buffer pointer Page 3
+	 */
+	u32 buff_ptr3;
+
+	/*!
+	 * Buffer pointer Page 4
+	 */
+	u32 buff_ptr4;
+
+	/*!
+	 * dma address of this td
+	 * */
+	dma_addr_t td_dma;
+
+	/*!
+	 * virtual address of next td
+	 * */
+	struct ep_td_struct *next_td_virt;
+
+	/*!
+	 * make it an even 16 words
+	 * */
+	u32 res[7];
+};
+
+/*!
+ * Endpoint Transfer Descriptor bit Masks
+ */
+#define  DTD_NEXT_TERMINATE                   (0x00000001)
+#define  DTD_IOC                              (0x00008000)
+#define  DTD_STATUS_ACTIVE                    (0x00000080)
+#define  DTD_STATUS_HALTED                    (0x00000040)
+#define  DTD_STATUS_DATA_BUFF_ERR             (0x00000020)
+#define  DTD_STATUS_TRANSACTION_ERR           (0x00000008)
+#define  DTD_RESERVED_FIELDS                  (0x80007300)
+#define  DTD_ADDR_MASK                        0xFFFFFFE0
+#define  DTD_PACKET_SIZE                      (0x7FFF0000)
+#define  DTD_LENGTH_BIT_POS                   (16)
+#define  DTD_ERROR_MASK                       (DTD_STATUS_HALTED | \
+				DTD_STATUS_DATA_BUFF_ERR | \
+				DTD_STATUS_TRANSACTION_ERR)
+/* Alignment requirements; must be a power of two */
+#define DTD_ALIGNMENT				0x20
+#define QH_ALIGNMENT				2048
+
+/* Controller dma boundary */
+#define UDC_DMA_BOUNDARY			0x1000
+
+/* -----------------------------------------------------------------------*/
+/* ##### enum data
+*/
+typedef enum {
+	e_ULPI,
+	e_UTMI_8BIT,
+	e_UTMI_16BIT,
+	e_SERIAL
+} e_PhyInterface;
+
+/*-------------------------------------------------------------------------*/
+
+struct fsl_req {
+	struct usb_request req;
+	struct list_head queue;
+	/* ep_queue() func will add
+	   a request->queue into a udc_ep->queue 'd tail */
+	struct fsl_ep *ep;
+	unsigned mapped;
+
+	struct ep_td_struct *head, *tail;	/* For dTD List
+						   this is a BigEndian Virtual addr */
+	unsigned int dtd_count;
+	/* just for IRAM patch */
+	dma_addr_t oridma;	/* original dma */
+	size_t buffer_offset;	/* offset of user buffer */
+	int last_one;		/* mark if reach to last packet */
+	struct ep_td_struct *cur;	/* current tranfer dtd */
+};
+
+#define REQ_UNCOMPLETE		(1)
+
+struct fsl_ep {
+	struct usb_ep ep;
+	struct list_head queue;
+	struct fsl_udc *udc;
+	struct ep_queue_head *qh;
+	const struct usb_endpoint_descriptor *desc;
+	struct usb_gadget *gadget;
+
+	char name[14];
+	unsigned stopped:1;
+};
+
+#define EP_DIR_IN	1
+#define EP_DIR_OUT	0
+
+struct fsl_udc {
+	struct usb_gadget gadget;
+	struct usb_gadget_driver *driver;
+	struct fsl_usb2_platform_data *pdata;
+	struct fsl_ep *eps;
+	unsigned int max_ep;
+	unsigned int irq;
+
+	struct usb_ctrlrequest local_setup_buff;
+	spinlock_t lock;
+	u32 xcvr_type;
+	struct otg_transceiver *transceiver;
+	unsigned softconnect:1;
+	unsigned vbus_active:1;
+	unsigned remote_wakeup:1;
+	/* we must distinguish the stopped and suspended state,
+	 * stopped means the udc enter lowpower mode, suspended
+	 * means the udc is suspended by system pm or by otg
+	 * switching to host mode.if the udc in suspended state
+	 * it also in the stopped state, while if the udc in
+	 * stopped state,it may not be in the suspended state*/
+	unsigned stopped:1;
+	int suspended;
+
+	struct ep_queue_head *ep_qh;	/* Endpoints Queue-Head */
+	struct fsl_req *status_req;	/* ep0 status request */
+	struct fsl_req *data_req;	/* ep0 data request */
+	struct dma_pool *td_pool;	/* dma pool for DTD */
+	enum fsl_usb2_phy_modes phy_mode;
+
+	size_t ep_qh_size;		/* size after alignment adjustment*/
+	dma_addr_t ep_qh_dma;		/* dma address of QH */
+
+	u32 max_pipes;		/* Device max pipes */
+	u32 max_use_endpts;	/* Max endpointes to be used */
+	u32 bus_reset;		/* Device is bus reseting */
+	u32 resume_state;	/* USB state to resume */
+	u32 usb_state;		/* USB current state */
+	u32 usb_next_state;	/* USB next state */
+	u32 ep0_dir;		/* Endpoint zero direction: can be
+				   USB_DIR_IN or USB_DIR_OUT */
+	u32 usb_sof_count;	/* SOF count */
+	u32 errors;		/* USB ERRORs count */
+	u8 device_address;	/* Device USB address */
+
+	struct completion *done;	/* to make sure release() is done */
+	u32 iram_buffer[IRAM_PPH_NTD];
+	void *iram_buffer_v[IRAM_PPH_NTD];
+	struct work_struct gadget_work;
+	struct delayed_work gadget_delay_work;
+};
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+#define DBG(fmt, args...) 	printk(KERN_DEBUG "[%s]  " fmt "\n", \
+				__func__, ## args)
+#else
+#define DBG(fmt, args...)	do {} while (0)
+#endif
+
+#if 0
+static void dump_msg(const char *label, const u8 * buf, unsigned int length)
+{
+	unsigned int start, num, i;
+	char line[52], *p;
+
+	if (length >= 512)
+		return;
+	pr_debug("udc: %s, length %u:\n", label, length);
+	start = 0;
+	while (length > 0) {
+		num = min(length, 16u);
+		p = line;
+		for (i = 0; i < num; ++i) {
+			if (i == 8)
+				*p++ = ' ';
+			sprintf(p, " %02x", buf[i]);
+			p += 3;
+		}
+		*p = 0;
+		printk(KERN_DEBUG "%6x: %s\n", start, line);
+		buf += num;
+		start += num;
+		length -= num;
+	}
+}
+#endif
+
+#ifdef VERBOSE
+#define VDBG		DBG
+#else
+#define VDBG(stuff...)	do {} while (0)
+#endif
+
+#define ERR(stuff...)		printk(KERN_ERR "udc: " stuff)
+#define INFO(stuff...)		printk(KERN_INFO "udc: " stuff)
+
+/*-------------------------------------------------------------------------*/
+
+/* ### Add board specific defines here
+ */
+
+/*
+ * ### pipe direction macro from device view
+ */
+#define USB_RECV	(0)	/* OUT EP */
+#define USB_SEND	(1)	/* IN EP */
+
+/*
+ * ### internal used help routines.
+ */
+#define ep_index(EP)         ((EP)->desc->bEndpointAddress&0xF)
+#define ep_maxpacket(EP)     ((EP)->ep.maxpacket)
+
+#define ep_is_in(EP)	((ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
+				USB_DIR_IN) : ((EP)->desc->bEndpointAddress \
+				& USB_DIR_IN) == USB_DIR_IN)
+
+#define get_ep_by_pipe(udc, pipe)	((pipe == 1) ? &udc->eps[0] : \
+					&udc->eps[pipe])
+#define get_pipe_by_windex(windex)	((windex & USB_ENDPOINT_NUMBER_MASK) \
+					* 2 + ((windex & USB_DIR_IN) ? 1 : 0))
+
+/* Bulk only class request */
+#define USB_BULK_RESET_REQUEST          0xff
+
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_STMP3XXX) || \
+	defined(CONFIG_ARCH_MXS)
+#include <mach/fsl_usb_gadget.h>
+#elif defined (CONFIG_PPC32)
+#include <asm/fsl_usb_gadget.h>
+#endif
+
+#endif				/* __ARCOTG_UDC_H */
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 060e0e2b1ae..247143e4a1b 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -59,6 +59,36 @@ config USB_EHCI_HCD
 	  To compile this driver as a module, choose M here: the
 	  module will be called ehci-hcd.
 
+config USB_EHCI_ARC
+	bool "Support for Freescale controller"
+	depends on USB_EHCI_HCD && (ARCH_MXC || ARCH_STMP3XXX || ARCH_MXS)
+	select USB_OTG_UTILS
+	---help---
+	   Some Freescale processors have an integrated High Speed
+	   USBOTG controller, which supports EHCI host mode.
+
+	   Say "y" here to add support for this controller
+	   to the EHCI HCD driver.
+
+config USB_EHCI_ARC_OTG
+	bool "Support for DR host port on Freescale controller"
+	depends on USB_EHCI_ARC
+	default y
+	---help---
+	  Enable support for the USB OTG port in HS/FS Host mode.
+
+config USB_STATIC_IRAM
+	bool "Use IRAM for USB"
+	depends on USB_EHCI_ARC
+	---help---
+	  Enable this option to use IRAM instead of DRAM for USB
+	  structures and buffers.  This option will reduce bus
+	  contention on systems with large (VGA+) framebuffer
+	  devices and heavy USB activity.  There are performance
+	  penalties and usage restrictions when using this option.
+
+	  If in doubt, say N.
+
 config USB_EHCI_ROOT_HUB_TT
 	bool "Root Hub Transaction Translators"
 	depends on USB_EHCI_HCD
diff --git a/drivers/usb/host/ehci-arc.c b/drivers/usb/host/ehci-arc.c
new file mode 100644
index 00000000000..8a0a22c3334
--- /dev/null
+++ b/drivers/usb/host/ehci-arc.c
@@ -0,0 +1,736 @@
+/*
+ * Copyright (c) 2005 MontaVista Software
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
+ * by Hunter Wu.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/hcd.h>
+
+#include "../core/usb.h"
+#include "ehci-fsl.h"
+#include <mach/fsl_usb.h>
+
+extern int usb_host_wakeup_irq(struct device *wkup_dev);
+extern void usb_host_set_wakeup(struct device *wkup_dev, bool para);
+static void fsl_usb_lowpower_mode(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+	if (enable) {
+		if (pdata->phy_lowpower_suspend)
+			pdata->phy_lowpower_suspend(pdata, true);
+	} else {
+		if (pdata->phy_lowpower_suspend)
+			pdata->phy_lowpower_suspend(pdata, false);
+	}
+	pdata->lowpower = enable;
+}
+
+static void fsl_usb_clk_gate(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+	if (pdata->usb_clock_for_pm)
+		pdata->usb_clock_for_pm(enable);
+}
+#undef EHCI_PROC_PTC
+#ifdef EHCI_PROC_PTC		/* /proc PORTSC:PTC support */
+/*
+ * write a PORTSC:PTC value to /proc/driver/ehci-ptc
+ * to put the controller into test mode.
+ */
+#include <linux/proc_fs.h>
+#include <asm/uaccess.h>
+#define EFPSL 3			/* ehci fsl proc string length */
+
+static int ehci_fsl_proc_read(char *page, char **start, off_t off, int count,
+			      int *eof, void *data)
+{
+	return 0;
+}
+
+static int ehci_fsl_proc_write(struct file *file, const char __user *buffer,
+			       unsigned long count, void *data)
+{
+	int ptc;
+	u32 portsc;
+	struct ehci_hcd *ehci = (struct ehci_hcd *) data;
+	char str[EFPSL] = {0};
+
+	if (count > EFPSL-1)
+		return -EINVAL;
+
+	if (copy_from_user(str, buffer, count))
+		return -EFAULT;
+
+	str[count] = '\0';
+
+	ptc = simple_strtoul(str, NULL, 0);
+
+	portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
+	portsc &= ~(0xf << 16);
+	portsc |= (ptc << 16);
+	printk(KERN_INFO "PTC %x  portsc %08x\n", ptc, portsc);
+
+	ehci_writel(ehci, portsc, &ehci->regs->port_status[0]);
+
+	return count;
+}
+
+static int ehci_testmode_init(struct ehci_hcd *ehci)
+{
+	struct proc_dir_entry *entry;
+
+	entry = create_proc_read_entry("driver/ehci-ptc", 0644, NULL,
+				       ehci_fsl_proc_read, ehci);
+	if (!entry)
+		return -ENODEV;
+
+	entry->write_proc = ehci_fsl_proc_write;
+	return 0;
+}
+#else
+static int ehci_testmode_init(struct ehci_hcd *ehci)
+{
+	return 0;
+}
+#endif	/* /proc PORTSC:PTC support */
+
+/**
+ * The hcd operation need to be done during the wakeup irq
+ */
+void fsl_usb_recover_hcd(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	u32 cmd = 0;
+
+	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+	/* After receive remote wakeup signaling. Must restore
+	 * CMDRUN bit in 20ms to keep port status.
+	 */
+	cmd = ehci_readl(ehci, &ehci->regs->command);
+	if (!(cmd & CMD_RUN)) {
+		ehci_writel(ehci, ehci->command, &ehci->regs->command);
+		/* Resume root hub here? */
+		usb_hcd_resume_root_hub(hcd);
+	}
+
+	/* disable all interrupt, will re-enable in resume */
+	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
+}
+
+/**
+ * usb_hcd_fsl_probe - initialize FSL-based HCDs
+ * @drvier: Driver to be used for this HCD
+ * @pdev: USB Host Controller being probed
+ * Context: !in_interrupt()
+ *
+ * Allocates basic resources for this USB host controller.
+ *
+ */
+int usb_hcd_fsl_probe(const struct hc_driver *driver,
+		      struct platform_device *pdev)
+{
+	struct fsl_usb2_platform_data *pdata;
+	struct usb_hcd *hcd;
+	struct resource *res;
+	int irq;
+	int retval;
+
+	pr_debug("initializing FSL-SOC USB Controller\n");
+
+	/* Need platform data for setup */
+	pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev,
+			"No platform data for %s.\n", dev_name(&pdev->dev));
+		return -ENODEV;
+	}
+
+	/*
+	 * This is a host mode driver, verify that we're supposed to be
+	 * in host mode.
+	 */
+	if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
+	      (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
+	      (pdata->operating_mode == FSL_USB2_DR_OTG))) {
+		dev_err(&pdev->dev,
+			"Non Host Mode configured for %s. Wrong driver linked.\n",
+			dev_name(&pdev->dev));
+		return -ENODEV;
+	}
+
+	hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
+	if (!hcd) {
+		retval = -ENOMEM;
+		goto err1;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev,
+			"Found HC with no IRQ. Check %s setup!\n",
+			dev_name(&pdev->dev));
+		return -ENODEV;
+	}
+	irq = res->start;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hcd->rsrc_start = res->start;
+	hcd->rsrc_len = resource_size(res);
+
+	if (pdata->operating_mode != FSL_USB2_DR_OTG) {
+		if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+					driver->description)) {
+			dev_dbg(&pdev->dev, "controller already in use\n");
+			retval = -EBUSY;
+			goto err2;
+		}
+	}
+
+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+
+	if (hcd->regs == NULL) {
+		dev_dbg(&pdev->dev, "error mapping memory\n");
+		retval = -EFAULT;
+		goto err3;
+	}
+	pdata->regs = hcd->regs;
+
+	/*
+	 * do platform specific init: check the clock, grab/config pins, etc.
+	 */
+	if (pdata->init && pdata->init(pdev)) {
+		retval = -ENODEV;
+		goto err3;
+	}
+
+	fsl_platform_set_host_mode(hcd);
+	hcd->power_budget = pdata->power_budget;
+
+	retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+	if (retval != 0)
+		goto err4;
+
+	if (pdata->operating_mode == FSL_USB2_DR_OTG) {
+		struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+		dbg("pdev=0x%p  hcd=0x%p  ehci=0x%p\n", pdev, hcd, ehci);
+
+		ehci->transceiver = otg_get_transceiver();
+		dbg("ehci->transceiver=0x%p\n", ehci->transceiver);
+
+		if (!ehci->transceiver) {
+			printk(KERN_ERR "can't find transceiver\n");
+			retval = -ENODEV;
+			goto err5;
+		}
+
+		retval = otg_set_host(ehci->transceiver, &ehci_to_hcd(ehci)->self);
+		if (retval)
+			otg_put_transceiver(ehci->transceiver);
+	} else if ((pdata->operating_mode == FSL_USB2_MPH_HOST) || \
+			(pdata->operating_mode == FSL_USB2_DR_HOST))
+		fsl_platform_set_vbus_power(pdata, 1);
+
+	fsl_platform_set_ahb_burst(hcd);
+	ehci_testmode_init(hcd_to_ehci(hcd));
+	return retval;
+err5:
+	usb_remove_hcd(hcd);
+err4:
+	iounmap(hcd->regs);
+err3:
+	if (pdata->operating_mode != FSL_USB2_DR_OTG)
+		release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err2:
+	usb_put_hcd(hcd);
+err1:
+	dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
+	if (pdata->exit)
+		pdata->exit(pdev);
+	return retval;
+}
+
+/**
+ * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
+ * @dev: USB Host Controller being removed
+ * Context: !in_interrupt()
+ *
+ * Reverses the effect of usb_hcd_fsl_probe().
+ *
+ */
+static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
+			       struct platform_device *pdev)
+{
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+	u32 tmp;
+
+	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		/* Need open clock for register access */
+		if (pdata->usb_clock_for_pm)
+			pdata->usb_clock_for_pm(true);
+
+		tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
+		if (tmp & PORT_PTS_PHCD) {
+			tmp &= ~PORT_PTS_PHCD;
+			ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
+			msleep(100);
+
+			if (pdata->usb_clock_for_pm)
+				pdata->usb_clock_for_pm(false);
+		}
+	}
+
+	/* DDD shouldn't we turn off the power here? */
+	fsl_platform_set_vbus_power(pdata, 0);
+
+	if (ehci->transceiver) {
+		(void)otg_set_host(ehci->transceiver, 0);
+		otg_put_transceiver(ehci->transceiver);
+	} else {
+		release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	}
+
+	usb_remove_hcd(hcd);
+	usb_put_hcd(hcd);
+
+	/*
+	 * do platform specific un-initialization:
+	 * release iomux pins, etc.
+	 */
+	if (pdata->exit)
+		pdata->exit(pdata->pdev);
+
+	iounmap(hcd->regs);
+}
+
+static void fsl_setup_phy(struct ehci_hcd *ehci,
+			  enum fsl_usb2_phy_modes phy_mode, int port_offset)
+{
+	u32 portsc;
+
+	portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
+	portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
+
+	switch (phy_mode) {
+	case FSL_USB2_PHY_ULPI:
+		portsc |= PORT_PTS_ULPI;
+		break;
+	case FSL_USB2_PHY_SERIAL:
+		portsc |= PORT_PTS_SERIAL;
+		break;
+	case FSL_USB2_PHY_UTMI_WIDE:
+		portsc |= PORT_PTS_PTW;
+		/* fall through */
+	case FSL_USB2_PHY_UTMI:
+		portsc |= PORT_PTS_UTMI;
+		break;
+	case FSL_USB2_PHY_NONE:
+		break;
+	}
+	ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
+}
+
+/* called after powerup, by probe or system-pm "wakeup" */
+static int ehci_fsl_reinit(struct ehci_hcd *ehci)
+{
+	fsl_platform_usb_setup(ehci);
+	ehci_port_power(ehci, 0);
+
+	return 0;
+}
+
+static int ehci_fsl_bus_suspend(struct usb_hcd *hcd)
+{
+	int ret = 0;
+	struct fsl_usb2_platform_data *pdata;
+
+	pdata = hcd->self.controller->platform_data;
+	printk(KERN_DEBUG "%s, %s\n", __func__, pdata->name);
+
+	/* the host is already at low power mode */
+	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		return 0;
+	}
+
+	ret = ehci_bus_suspend(hcd);
+	if (ret != 0)
+		return ret;
+
+	if (pdata->platform_suspend)
+		pdata->platform_suspend(pdata);
+
+	usb_host_set_wakeup(hcd->self.controller, true);
+	fsl_usb_lowpower_mode(pdata, true);
+	fsl_usb_clk_gate(hcd->self.controller->platform_data, false);
+	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+	return ret;
+}
+
+static int ehci_fsl_bus_resume(struct usb_hcd *hcd)
+{
+	int ret = 0;
+	struct fsl_usb2_platform_data *pdata;
+
+	pdata = hcd->self.controller->platform_data;
+	printk(KERN_DEBUG "%s, %s\n", __func__, pdata->name);
+
+	/*
+	 * At otg mode, it should not call host resume for usb gadget device
+	 * Otherwise, this usb device can't be recognized as a gadget
+	 */
+	if (hcd->self.is_b_host) {
+		return -ESHUTDOWN;
+	}
+
+	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+		fsl_usb_clk_gate(hcd->self.controller->platform_data, true);
+		usb_host_set_wakeup(hcd->self.controller, false);
+		fsl_usb_lowpower_mode(pdata, false);
+	}
+
+	if (pdata->platform_resume)
+		pdata->platform_resume(pdata);
+
+	ret = ehci_bus_resume(hcd);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+static void ehci_fsl_shutdown(struct usb_hcd *hcd)
+{
+	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+		fsl_usb_clk_gate(hcd->self.controller->platform_data, true);
+	}
+	/* Disable wakeup event first */
+	usb_host_set_wakeup(hcd->self.controller, false);
+
+	ehci_shutdown(hcd);
+	if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+		fsl_usb_clk_gate(hcd->self.controller->platform_data, false);
+	}
+}
+
+/* called during probe() after chip reset completes */
+static int ehci_fsl_setup(struct usb_hcd *hcd)
+{
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	int retval;
+
+	/* EHCI registers start at offset 0x100 */
+	ehci->caps = hcd->regs + 0x100;
+	ehci->regs = hcd->regs + 0x100 +
+	    HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
+	dbg_hcs_params(ehci, "reset");
+	dbg_hcc_params(ehci, "reset");
+
+	/* cache this readonly data; minimize chip reads */
+	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+	retval = ehci_halt(ehci);
+	if (retval)
+		return retval;
+
+	/* data structure init */
+	retval = ehci_init(hcd);
+	if (retval)
+		return retval;
+
+	hcd->has_tt = 1;
+
+	ehci->sbrn = 0x20;
+
+	ehci_reset(ehci);
+
+	retval = ehci_fsl_reinit(ehci);
+	return retval;
+}
+
+static const struct hc_driver ehci_fsl_hc_driver = {
+	.description = hcd_name,
+	.product_desc = "Freescale On-Chip EHCI Host Controller",
+	.hcd_priv_size = sizeof(struct ehci_hcd),
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq = ehci_irq,
+	.flags = HCD_USB2,
+
+	/*
+	 * basic lifecycle operations
+	 */
+	.reset = ehci_fsl_setup,
+	.start = ehci_run,
+	.stop = ehci_stop,
+	.shutdown = ehci_fsl_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue = ehci_urb_enqueue,
+	.urb_dequeue = ehci_urb_dequeue,
+	.endpoint_disable = ehci_endpoint_disable,
+	.endpoint_reset = ehci_endpoint_reset,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number = ehci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data = ehci_hub_status_data,
+	.hub_control = ehci_hub_control,
+	.bus_suspend = ehci_fsl_bus_suspend,
+	.bus_resume = ehci_fsl_bus_resume,
+	.relinquish_port = ehci_relinquish_port,
+	.port_handed_over = ehci_port_handed_over,
+
+	.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+};
+
+static int ehci_fsl_drv_probe(struct platform_device *pdev)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	/* FIXME we only want one one probe() not two */
+	return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
+}
+
+static int ehci_fsl_drv_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+	/* FIXME we only want one one remove() not two */
+	usb_hcd_fsl_remove(hcd, pdev);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+static bool host_can_wakeup_system(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	if (pdata->operating_mode == FSL_USB2_DR_OTG)
+		if (device_may_wakeup(ehci->transceiver->dev))
+			return true;
+		else
+			return false;
+	else
+		if (device_may_wakeup(&(pdev->dev)))
+			return true;
+		else
+			return false;
+}
+
+/* suspend/resume, section 4.3 */
+
+/* These routines rely on the bus (pci, platform, etc)
+ * to handle powerdown and wakeup, and currently also on
+ * transceivers that don't need any software attention to set up
+ * the right sort of wakeup.
+ *
+ * They're also used for turning on/off the port when doing OTG.
+ */
+static int ehci_fsl_drv_suspend(struct platform_device *pdev,
+				pm_message_t message)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	struct usb_device *roothub = hcd->self.root_hub;
+	u32 port_status;
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+	printk(KERN_DEBUG "USB Host suspend begins\n");
+	/* Only handles OTG mode switch event, system suspend event will be done in bus suspend */
+	if (pdata->pmflags == 0) {
+		printk(KERN_DEBUG "%s, pm event \n", __func__);
+		if (!host_can_wakeup_system(pdev)) {
+			int mask;
+			/* Need open clock for register access */
+			if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags))
+				fsl_usb_clk_gate(hcd->self.controller->platform_data, true);
+
+			mask = ehci_readl(ehci, &ehci->regs->intr_enable);
+			mask &= ~STS_PCD;
+			ehci_writel(ehci, mask, &ehci->regs->intr_enable);
+
+			usb_host_set_wakeup(hcd->self.controller, false);
+			fsl_usb_clk_gate(hcd->self.controller->platform_data, false);
+		}
+		return 0;
+	}
+
+	/* only the otg host can go here */
+	/* wait for all usb device on the hcd dettached */
+	usb_lock_device(roothub);
+	if (roothub->children[0] != NULL) {
+		int old = hcd->self.is_b_host;
+		printk(KERN_DEBUG "will resume roothub and its children\n");
+		hcd->self.is_b_host = 0;
+		/* resume the roothub, so that it can test the children is disconnected */
+		if (roothub->state == USB_STATE_SUSPENDED)
+			usb_resume(&roothub->dev, PMSG_USER_SUSPEND);
+		/* we must do unlock here, the hubd thread will hold the same lock
+		 * here release the lock, so that the hubd thread can process the usb
+		 * disconnect event and set the children[0] be NULL, or there will be
+		 * a deadlock */
+		usb_unlock_device(roothub);
+		while (roothub->children[0] != NULL)
+			msleep(1);
+		usb_lock_device(roothub);
+		hcd->self.is_b_host = old;
+	}
+	usb_unlock_device(roothub);
+
+	if (!(hcd->state & HC_STATE_SUSPENDED)) {
+		printk(KERN_DEBUG "will suspend roothub and its children\n");
+		usb_lock_device(roothub);
+		usb_suspend(&roothub->dev, PMSG_USER_SUSPEND);
+		usb_unlock_device(roothub);
+	}
+
+	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		fsl_usb_clk_gate(hcd->self.controller->platform_data, true);
+		set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+	}
+
+	port_status = ehci_readl(ehci, &ehci->regs->port_status[0]);
+	/* save EHCI registers */
+	pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
+	pdata->pm_command &= ~CMD_RUN;
+	pdata->pm_status  = ehci_readl(ehci, &ehci->regs->status);
+	pdata->pm_intr_enable  = ehci_readl(ehci, &ehci->regs->intr_enable);
+	pdata->pm_frame_index  = ehci_readl(ehci, &ehci->regs->frame_index);
+	pdata->pm_segment  = ehci_readl(ehci, &ehci->regs->segment);
+	pdata->pm_frame_list  = ehci_readl(ehci, &ehci->regs->frame_list);
+	pdata->pm_async_next  = ehci_readl(ehci, &ehci->regs->async_next);
+	pdata->pm_configured_flag  =
+		ehci_readl(ehci, &ehci->regs->configured_flag);
+	pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
+
+	/* clear the W1C bits */
+	pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
+
+	/* clear PHCD bit */
+	pdata->pm_portsc &= ~PORT_PTS_PHCD;
+
+	usb_host_set_wakeup(hcd->self.controller, true);
+	fsl_usb_lowpower_mode(pdata, true);
+
+	if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+		fsl_usb_clk_gate(hcd->self.controller->platform_data, false);
+	}
+	pdata->pmflags = 0;
+	printk(KERN_DEBUG "host suspend ends\n");
+	return 0;
+}
+
+static int ehci_fsl_drv_resume(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	struct usb_device *roothub = hcd->self.root_hub;
+	u32 tmp;
+	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+	struct fsl_usb2_wakeup_platform_data *wake_up_pdata = pdata->wakeup_pdata;
+	/* Only handles OTG mode switch event */
+	printk(KERN_DEBUG "ehci fsl drv resume begins: %s\n", pdata->name);
+	if (pdata->pmflags == 0) {
+		printk(KERN_DEBUG "%s,pm event, wait for wakeup irq if needed\n", __func__);
+		wait_event_interruptible(wake_up_pdata->wq, !wake_up_pdata->usb_wakeup_is_pending);
+		if (!host_can_wakeup_system(pdev)) {
+			if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+				fsl_usb_clk_gate(hcd->self.controller->platform_data, true);
+			}
+			usb_host_set_wakeup(hcd->self.controller, true);
+
+			if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+				fsl_usb_clk_gate(hcd->self.controller->platform_data, false);
+			}
+		}
+		return 0;
+	}
+	if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+		set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+		fsl_usb_clk_gate(hcd->self.controller->platform_data, true);
+		usb_host_set_wakeup(hcd->self.controller, false);
+		fsl_usb_lowpower_mode(pdata, false);
+	}
+
+	/* set host mode */
+	fsl_platform_set_host_mode(hcd);
+
+	/* restore EHCI registers */
+	ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
+	ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
+	ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
+	ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
+	ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
+	ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
+	ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
+	ehci_writel(ehci, pdata->pm_configured_flag,
+		    &ehci->regs->configured_flag);
+
+
+	tmp = ehci_readl(ehci, &ehci->regs->command);
+	tmp |= CMD_RUN;
+	ehci_writel(ehci, tmp, &ehci->regs->command);
+
+	if ((hcd->state & HC_STATE_SUSPENDED)) {
+		printk(KERN_DEBUG "will resume roothub and its children\n");
+		usb_lock_device(roothub);
+		usb_resume(&roothub->dev, PMSG_USER_RESUME);
+		usb_unlock_device(roothub);
+	}
+	pdata->pmflags = 0;
+	printk(KERN_DEBUG "ehci fsl drv resume ends: %s\n", pdata->name);
+
+	return 0;
+}
+#endif
+MODULE_ALIAS("platform:fsl-ehci");
+
+static struct platform_driver ehci_fsl_driver = {
+	.probe = ehci_fsl_drv_probe,
+	.remove = ehci_fsl_drv_remove,
+	.shutdown = usb_hcd_platform_shutdown,
+#ifdef CONFIG_PM
+	.suspend = ehci_fsl_drv_suspend,
+	.resume = ehci_fsl_drv_resume,
+#endif
+	.driver = {
+		   .name = "fsl-ehci",
+	},
+};
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 49180622116..89516d12315 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 2005-2010 Freescale Semiconductor, Inc.
+/* Copyright (C) 2005-2011 Freescale Semiconductor, Inc.
  * Copyright (c) 2005 MontaVista Software
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -19,13 +19,17 @@
 #define _EHCI_FSL_H
 
 /* offsets for the non-ehci registers in the FSL SOC USB controller */
-#define FSL_SOC_USB_ULPIVP	0x170
-#define FSL_SOC_USB_PORTSC1	0x184
+#define FSL_SOC_USB_SBUSCFG		0x90
+#define FSL_SOC_USB_BURSTSIZE		0x160
+#define FSL_SOC_USB_TXFILLTUNING	0x164
+#define FSL_SOC_USB_ULPIVP		0x170
+#define FSL_SOC_USB_PORTSC1		0x184
 #define PORT_PTS_MSK		(3<<30)
 #define PORT_PTS_UTMI		(0<<30)
 #define PORT_PTS_ULPI		(2<<30)
 #define	PORT_PTS_SERIAL		(3<<30)
 #define PORT_PTS_PTW		(1<<28)
+#define PORT_PTS_PHCD		(1<<23)
 #define FSL_SOC_USB_PORTSC2	0x188
 #define FSL_SOC_USB_USBMODE	0x1a8
 #define USBMODE_CM_MASK		(3 << 0)	/* controller mode mask */
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 3ff9f82f726..2b97122d6a8 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1234,6 +1234,11 @@ MODULE_LICENSE ("GPL");
 #define        PLATFORM_DRIVER         ehci_hcd_omap_driver
 #endif
 
+#ifdef CONFIG_USB_EHCI_ARC
+#include "ehci-arc.c"
+#define	PLATFORM_DRIVER		ehci_fsl_driver
+#endif
+
 #ifdef CONFIG_PPC_PS3
 #include "ehci-ps3.c"
 #define	PS3_SYSTEM_BUS_DRIVER	ps3_ehci_driver
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d83e967e4e1..de5806bb9ba 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2415,6 +2415,10 @@ source "drivers/video/omap2/Kconfig"
 source "drivers/video/backlight/Kconfig"
 source "drivers/video/display/Kconfig"
 
+if ARCH_MXC
+source "drivers/video/mxc/Kconfig"
+endif
+
 if VT
 	source "drivers/video/console/Kconfig"
 endif
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9b9d8fff773..bc77579e8de 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_FB_KYRO)             += kyro/
 obj-$(CONFIG_FB_SAVAGE)		  += savage/
 obj-$(CONFIG_FB_GEODE)		  += geode/
 obj-$(CONFIG_FB_MBX)		  += mbx/
+obj-$(CONFIG_FB_MXC)              += mxc/
 obj-$(CONFIG_FB_NEOMAGIC)         += neofb.o
 obj-$(CONFIG_FB_3DFX)             += tdfxfb.o
 obj-$(CONFIG_FB_CONTROL)          += controlfb.o
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 278aeaa9250..cc795c014e0 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -342,6 +342,12 @@ config BACKLIGHT_AAT2870
 	  If you have a AnalogicTech AAT2870 say Y to enable the
 	  backlight driver.
 
+config BACKLIGHT_DA9052
+	tristate "Dialog DA9052 WLED"
+	depends on PMIC_DIALOG
+	help
+	  Enable the DA9052 Backlight Driver
+
 endif # BACKLIGHT_CLASS_DEVICE
 
 endif # BACKLIGHT_LCD_SUPPORT
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index fdd1fc4b277..aea6797661d 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -39,4 +39,5 @@ obj-$(CONFIG_BACKLIGHT_ADP8870)	+= adp8870_bl.o
 obj-$(CONFIG_BACKLIGHT_88PM860X) += 88pm860x_bl.o
 obj-$(CONFIG_BACKLIGHT_PCF50633)	+= pcf50633-backlight.o
 obj-$(CONFIG_BACKLIGHT_AAT2870) += aat2870_bl.o
+obj-$(CONFIG_BACKLIGHT_DA9052)	+= da9052_bl.o
 
diff --git a/drivers/video/backlight/da9052_bl.c b/drivers/video/backlight/da9052_bl.c
new file mode 100644
index 00000000000..68fac25d1b1
--- /dev/null
+++ b/drivers/video/backlight/da9052_bl.c
@@ -0,0 +1,464 @@
+/*
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * da9052_bl.c: Backlight driver for DA9052
+ */
+
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+
+#include <linux/delay.h>
+
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/bl.h>
+
+
+#define DRIVER_NAME		"da9052-backlight"
+#define DRIVER_NAME1		"WLED-1"
+#define DRIVER_NAME2		"WLED-2"
+#define DRIVER_NAME3		"WLED-3"
+
+/* These flags define if Backlight LEDs are present */
+/* Set the following macros to 1, if LEDs are present. Otherwise set to 0 */
+#define DA9052_LED1_PRESENT	1
+#define DA9052_LED2_PRESENT	1
+#define DA9052_LED3_PRESENT	1
+
+#define DA9052_MAX_BRIGHTNESS	0xFF
+
+struct da9052_backlight_data {
+	struct device *da9052_dev;
+	int current_brightness;
+	struct da9052 *da9052;
+
+	int is_led1_present;
+	int is_led2_present;
+	int is_led3_present;
+};
+
+enum da9052_led_number {
+	LED1 = 1,
+	LED2,
+	LED3,
+};
+
+static int da9052_backlight_brightness_set(struct da9052_backlight_data *data,
+			int brightness, enum da9052_led_number led)
+{
+	/*
+	 * Mechanism for brightness control:
+	 * For brightness control, current is used.
+	 * PWM feature is not used.
+	 * To use PWM feature, a fixed value of current should be defined.
+	 */
+
+	int ret = 0;
+	unsigned int led_ramp_bit;
+	unsigned int led_current_register;
+	unsigned int led_current_sink_bit;
+	unsigned int led_boost_en_bit;
+	struct da9052_ssc_msg msg;
+
+	switch (led) {
+	case LED1:
+		led_ramp_bit = DA9052_LEDCONT_LED1RAMP;
+		led_current_register = DA9052_LED1CONF_REG;
+		led_current_sink_bit = DA9052_LEDCONT_LED1EN;
+		led_boost_en_bit = DA9052_BOOST_LED1INEN;
+	break;
+	case LED2:
+		led_ramp_bit = DA9052_LEDCONT_LED2RAMP;
+		led_current_register = DA9052_LED2CONF_REG;
+		led_current_sink_bit = DA9052_LEDCONT_LED2EN;
+		led_boost_en_bit = DA9052_BOOST_LED2INEN;
+	break;
+	case LED3:
+		led_ramp_bit = DA9052_LEDCONT_LED3RAMP;
+		led_current_register = DA9052_LED3CONF_REG;
+		led_current_sink_bit = DA9052_LEDCONT_LED3EN;
+		led_boost_en_bit = DA9052_BOOST_LED3INEN;
+	break;
+	default:
+		return -EIO;
+	}
+
+	/*
+		1. Configure the boost register
+		2. Configure the LED _CONT register
+		3. Configure the LEDx_CONF registers to the brightness value.
+	*/
+	msg.addr = DA9052_BOOST_REG;
+	msg.data = 0x3F;
+	if (brightness) {
+		da9052_lock(data->da9052);
+		ret = data->da9052->write(data->da9052, &msg);
+		if (ret) {
+			da9052_unlock(data->da9052);
+			return ret;
+		}
+		da9052_unlock(data->da9052);
+	}
+
+	msg.addr = DA9052_LEDCONT_REG;
+	msg.data = 0xFF;
+	if (brightness) {
+		da9052_lock(data->da9052);
+		ret = data->da9052->write(data->da9052, &msg);
+		if (ret) {
+			da9052_unlock(data->da9052);
+			return ret;
+		}
+		da9052_unlock(data->da9052);
+	}
+
+	msg.addr = led_current_register;
+	msg.data = 0;
+	/* Write to the DA9052 register */
+	da9052_lock(data->da9052);
+	ret = data->da9052->write(data->da9052, &msg);
+	if (ret) {
+		da9052_unlock(data->da9052);
+		return ret;
+	}
+	da9052_unlock(data->da9052);
+	msleep(20);
+	msg.data = brightness;
+	/* Write to the DA9052 register */
+	da9052_lock(data->da9052);
+	ret = data->da9052->write(data->da9052, &msg);
+	if (ret) {
+		da9052_unlock(data->da9052);
+		return ret;
+	}
+	da9052_unlock(data->da9052);
+
+	return 0;
+}
+
+static int da9052_backlight_set(struct backlight_device *bl, int brightness)
+{
+	struct da9052_backlight_data *data = bl_get_data(bl);
+	int ret = 0;
+	/* Check for LED1 */
+	if (1 == data->is_led1_present) {
+		ret = da9052_backlight_brightness_set(data, brightness, LED1);
+		if (ret)
+			return ret;
+	}
+	/* Check for LED2 */
+	if (1 == data->is_led2_present) {
+		ret = da9052_backlight_brightness_set(data, brightness, LED2);
+		if (ret)
+			return ret;
+	}
+	/* Check for LED3 */
+	if (1 == data->is_led3_present) {
+		ret = da9052_backlight_brightness_set(data, brightness, LED3);
+		if (ret)
+			return ret;
+	}
+
+	data->current_brightness = brightness;
+	return 0;
+}
+
+static int da9052_init_WLED(struct da9052_backlight_data *data,
+			enum da9052_led_number led)
+{
+	int ret = 0;
+	unsigned int led_current_register;
+	struct da9052_ssc_msg msg;
+
+	switch (led) {
+	case LED1:
+		led_current_register = DA9052_LED1CONF_REG;
+	break;
+	case LED2:
+		led_current_register = DA9052_LED2CONF_REG;
+	break;
+	case LED3:
+		led_current_register = DA9052_LED3CONF_REG;
+	break;
+	default:
+		return -EIO;
+	}
+
+	msg.addr = DA9052_BOOST_REG;
+	msg.data = 0x00;
+	da9052_lock(data->da9052);
+	ret = data->da9052->write(data->da9052, &msg);
+	if (ret) {
+		da9052_unlock(data->da9052);
+		return ret;
+	}
+	da9052_unlock(data->da9052);
+
+	msg.addr = DA9052_LEDCONT_REG;
+	msg.data = 0x00;
+	da9052_lock(data->da9052);
+	ret = data->da9052->write(data->da9052, &msg);
+	if (ret) {
+		da9052_unlock(data->da9052);
+		return ret;
+	}
+	da9052_unlock(data->da9052);
+
+	msg.addr = led_current_register;
+	msg.data = 0;
+	da9052_lock(data->da9052);
+	ret = data->da9052->write(data->da9052, &msg);
+	da9052_unlock(data->da9052);
+	return ret;
+}
+
+static int da9052_backlight_update_status(struct backlight_device *bl)
+{
+	int brightness = bl->props.brightness;
+
+	if (bl->props.power != FB_BLANK_UNBLANK)
+		brightness = 0;
+
+	if (bl->props.fb_blank != FB_BLANK_UNBLANK)
+		brightness = 0;
+	return da9052_backlight_set(bl, brightness);
+}
+
+static int da9052_backlight_get_brightness(struct backlight_device *bl)
+{
+	struct da9052_backlight_data *data = bl_get_data(bl);
+	return data->current_brightness;
+}
+
+const struct backlight_ops da9052_backlight_ops = {
+	.update_status	= da9052_backlight_update_status,
+	.get_brightness	= da9052_backlight_get_brightness,
+};
+
+static int da9052_backlight_probe1(struct platform_device *pdev)
+{
+	struct da9052_backlight_data *data;
+	struct backlight_device *bl;
+	struct backlight_properties props;
+	int ret = 0;
+	struct da9052 *da9052 = dev_get_drvdata(pdev->dev.parent);
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (data == NULL)
+		return -ENOMEM;
+	data->da9052_dev = pdev->dev.parent;
+	data->da9052	= da9052;
+	data->current_brightness = 0;
+	data->is_led1_present = DA9052_LED1_PRESENT;
+
+	/* Init the WLED-1 bank */
+	ret = da9052_init_WLED(data, LED1);
+	if (ret)
+		return ret;
+
+	memset(&props, 0, sizeof(struct backlight_properties));
+	props.max_brightness = DA9052_MAX_BRIGHTNESS;
+	props.type = BACKLIGHT_RAW;
+	bl = backlight_device_register(pdev->name, data->da9052_dev,
+				       data, &da9052_backlight_ops, &props);
+	if (IS_ERR(bl)) {
+		dev_err(&pdev->dev, "failed to register backlight\n");
+		kfree(data);
+		return PTR_ERR(bl);
+	}
+
+	bl->props.brightness = 0;
+
+	platform_set_drvdata(pdev, bl);
+	backlight_update_status(bl);
+
+	return 0;
+}
+static int da9052_backlight_probe2(struct platform_device *pdev)
+{
+	struct da9052_backlight_data *data;
+	struct backlight_device *bl;
+	struct da9052 *da9052 = dev_get_drvdata(pdev->dev.parent);
+	struct backlight_properties props;
+	int ret = 0;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (data == NULL)
+		return -ENOMEM;
+	data->da9052_dev = pdev->dev.parent;
+	data->da9052	= da9052;
+	data->current_brightness = 0;
+	data->is_led2_present = DA9052_LED2_PRESENT;
+
+	/* Init the WLED-2 bank */
+	ret = da9052_init_WLED(data, LED2);
+	if (ret)
+		return ret;
+
+	memset(&props, 0, sizeof(struct backlight_properties));
+	props.max_brightness = DA9052_MAX_BRIGHTNESS;
+	props.type = BACKLIGHT_RAW;
+	bl = backlight_device_register(pdev->name, data->da9052_dev,
+				       data, &da9052_backlight_ops, &props);
+	if (IS_ERR(bl)) {
+		dev_err(&pdev->dev, "failed to register backlight\n");
+		kfree(data);
+		return PTR_ERR(bl);
+	}
+
+	bl->props.brightness = 0;
+
+	platform_set_drvdata(pdev, bl);
+	backlight_update_status(bl);
+
+	return 0;
+}
+static int da9052_backlight_probe3(struct platform_device *pdev)
+{
+	struct da9052_backlight_data *data;
+	struct backlight_device *bl;
+	struct da9052 *da9052 = dev_get_drvdata(pdev->dev.parent);
+	struct backlight_properties props;
+	int ret = 0;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (data == NULL)
+		return -ENOMEM;
+	data->da9052_dev = pdev->dev.parent;
+	data->da9052	= da9052;
+	data->current_brightness = 0;
+	data->is_led3_present = DA9052_LED3_PRESENT;
+
+	/* Init the WLED-2 bank */
+	ret = da9052_init_WLED(data, LED3);
+	if (ret)
+		return ret;
+
+	memset(&props, 0, sizeof(struct backlight_properties));
+	props.max_brightness = DA9052_MAX_BRIGHTNESS;
+	props.type = BACKLIGHT_RAW;
+	bl = backlight_device_register(pdev->name, data->da9052_dev,
+				       data, &da9052_backlight_ops, &props);
+	if (IS_ERR(bl)) {
+		dev_err(&pdev->dev, "failed to register backlight\n");
+		kfree(data);
+		return PTR_ERR(bl);
+	}
+
+	bl->props.brightness = 0;
+
+	platform_set_drvdata(pdev, bl);
+
+	backlight_update_status(bl);
+	return 0;
+}
+
+static int da9052_backlight_remove1(struct platform_device *pdev)
+{
+	struct backlight_device *bl = platform_get_drvdata(pdev);
+	struct da9052_backlight_data *data = bl_get_data(bl);
+	int ret = 0;
+
+	/* Switch off the WLED-1 */
+	ret = da9052_init_WLED(data, LED1);
+	if (ret)
+		return ret;
+
+	backlight_device_unregister(bl);
+	kfree(data);
+	return 0;
+}
+
+static int da9052_backlight_remove2(struct platform_device *pdev)
+{
+	struct backlight_device *bl = platform_get_drvdata(pdev);
+	struct da9052_backlight_data *data = bl_get_data(bl);
+	int ret = 0;
+
+	/* Switch off the WLED-2 */
+	ret = da9052_init_WLED(data, LED2);
+	if (ret)
+		return ret;
+
+	backlight_device_unregister(bl);
+	kfree(data);
+	return 0;
+}
+static int da9052_backlight_remove3(struct platform_device *pdev)
+{
+	struct backlight_device *bl = platform_get_drvdata(pdev);
+	struct da9052_backlight_data *data = bl_get_data(bl);
+	int ret;
+
+	/* Switch off the WLED-3 */
+	ret = da9052_init_WLED(data, LED3);
+	if (ret)
+		return ret;
+
+	backlight_device_unregister(bl);
+	kfree(data);
+	return 0;
+}
+
+static struct platform_driver da9052_backlight_driver1 = {
+	.driver		= {
+		.name	= DRIVER_NAME1,
+		.owner	= THIS_MODULE,
+	},
+	.probe		= da9052_backlight_probe1,
+	.remove		= da9052_backlight_remove1,
+};
+static struct platform_driver da9052_backlight_driver2 = {
+	.driver		= {
+		.name	= DRIVER_NAME2,
+		.owner	= THIS_MODULE,
+	},
+	.probe		= da9052_backlight_probe2,
+	.remove		= da9052_backlight_remove2,
+};
+static struct platform_driver da9052_backlight_driver3 = {
+	.driver		= {
+		.name	= DRIVER_NAME3,
+		.owner	= THIS_MODULE,
+	},
+	.probe		= da9052_backlight_probe3,
+	.remove		= da9052_backlight_remove3,
+};
+
+static int __init da9052_backlight_init(void)
+{
+	s32 ret;
+	ret = platform_driver_register(&da9052_backlight_driver1);
+	if (ret)
+		return ret;
+	ret = platform_driver_register(&da9052_backlight_driver2);
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&da9052_backlight_driver3);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+module_init(da9052_backlight_init);
+
+static void __exit da9052_backlight_exit(void)
+{
+	platform_driver_unregister(&da9052_backlight_driver1);
+	platform_driver_unregister(&da9052_backlight_driver2);
+	platform_driver_unregister(&da9052_backlight_driver3);
+}
+module_exit(da9052_backlight_exit);
+
+MODULE_AUTHOR("Dialog Semiconductor Ltd <dchen@diasemi.com>");
+MODULE_DESCRIPTION("Backlight driver for Dialog DA9052 PMIC");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
index ad936295d8f..a65f5b57391 100644
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -991,6 +991,17 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var)
 			old_var = info->var;
 			info->var = *var;
 
+			/* call pre-mode change */
+			if (flags & FBINFO_MISC_USEREVENT) {
+				struct fb_event event;
+				int evnt = FB_EVENT_PREMODE_CHANGE;
+
+				info->flags &= ~FBINFO_MISC_USEREVENT;
+				event.info = info;
+				event.data = &mode;
+				fb_notifier_call_chain(evnt, &event);
+			}
+
 			if (info->fbops->fb_set_par) {
 				ret = info->fbops->fb_set_par(info);
 
diff --git a/drivers/video/mxc/Kconfig b/drivers/video/mxc/Kconfig
new file mode 100644
index 00000000000..bb836c3a63f
--- /dev/null
+++ b/drivers/video/mxc/Kconfig
@@ -0,0 +1,34 @@
+config FB_MXC
+	tristate "MXC Framebuffer support"
+	depends on FB && (MXC_IPU || ARCH_MX21 || ARCH_MX27 || ARCH_MX25)
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	select FB_MODE_HELPERS
+	default y
+	help
+	  This is a framebuffer device for the MXC LCD Controller.
+	  See <http://www.linux-fbdev.org/> for information on framebuffer
+	  devices.
+
+	  If you plan to use the LCD display with your MXC system, say
+	  Y here.
+
+config FB_MXC_SYNC_PANEL
+	depends on FB_MXC
+	tristate "Synchronous Panel Framebuffer"
+	default y
+
+config FB_MXC_TVOUT_TVE
+	tristate "MXC TVE TV Out Encoder"
+	depends on FB_MXC_SYNC_PANEL
+	depends on MXC_IPU_V3
+
+config FB_MXC_SII902X
+	depends on FB_MXC_SYNC_PANEL
+	tristate "Si Image SII9022 DVI/HDMI Interface Chip"
+
+config FB_MXC_LDB
+	tristate "MXC LDB"
+	depends on FB_MXC_SYNC_PANEL
+	depends on MXC_IPU_V3
diff --git a/drivers/video/mxc/Makefile b/drivers/video/mxc/Makefile
new file mode 100644
index 00000000000..4c75e1be2d3
--- /dev/null
+++ b/drivers/video/mxc/Makefile
@@ -0,0 +1,5 @@
+obj-$(CONFIG_FB_MXC_TVOUT_TVE)	+= tve.o
+obj-$(CONFIG_FB_MXC_SII902X)	+= mxcfb_sii902x.o
+obj-$(CONFIG_FB_MXC_LDB)	+= ldb.o
+obj-$(CONFIG_FB_MODE_HELPERS)	+= mxc_edid.o
+obj-$(CONFIG_FB_MXC_SYNC_PANEL)	+= mxc_dispdrv.o mxc_lcdif.o mxc_ipuv3_fb.o
diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c
new file mode 100644
index 00000000000..180bf7f6f8d
--- /dev/null
+++ b/drivers/video/mxc/ldb.c
@@ -0,0 +1,646 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @file mxc_ldb.c
+ *
+ * @brief This file contains the LDB driver device interface and fops
+ * functions.
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spinlock.h>
+#include <linux/fsl_devices.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include "mxc_dispdrv.h"
+
+#define DISPDRV_LDB	"ldb"
+
+#define LDB_BGREF_RMODE_MASK		0x00008000
+#define LDB_BGREF_RMODE_INT		0x00008000
+#define LDB_BGREF_RMODE_EXT		0x0
+
+#define LDB_DI1_VS_POL_MASK		0x00000400
+#define LDB_DI1_VS_POL_ACT_LOW		0x00000400
+#define LDB_DI1_VS_POL_ACT_HIGH		0x0
+#define LDB_DI0_VS_POL_MASK		0x00000200
+#define LDB_DI0_VS_POL_ACT_LOW		0x00000200
+#define LDB_DI0_VS_POL_ACT_HIGH		0x0
+
+#define LDB_BIT_MAP_CH1_MASK		0x00000100
+#define LDB_BIT_MAP_CH1_JEIDA		0x00000100
+#define LDB_BIT_MAP_CH1_SPWG		0x0
+#define LDB_BIT_MAP_CH0_MASK		0x00000040
+#define LDB_BIT_MAP_CH0_JEIDA		0x00000040
+#define LDB_BIT_MAP_CH0_SPWG		0x0
+
+#define LDB_DATA_WIDTH_CH1_MASK		0x00000080
+#define LDB_DATA_WIDTH_CH1_24		0x00000080
+#define LDB_DATA_WIDTH_CH1_18		0x0
+#define LDB_DATA_WIDTH_CH0_MASK		0x00000020
+#define LDB_DATA_WIDTH_CH0_24		0x00000020
+#define LDB_DATA_WIDTH_CH0_18		0x0
+
+#define LDB_CH1_MODE_MASK		0x0000000C
+#define LDB_CH1_MODE_EN_TO_DI1		0x0000000C
+#define LDB_CH1_MODE_EN_TO_DI0		0x00000004
+#define LDB_CH1_MODE_DISABLE		0x0
+#define LDB_CH0_MODE_MASK		0x00000003
+#define LDB_CH0_MODE_EN_TO_DI1		0x00000003
+#define LDB_CH0_MODE_EN_TO_DI0		0x00000001
+#define LDB_CH0_MODE_DISABLE		0x0
+
+#define LDB_SPLIT_MODE_EN		0x00000010
+
+struct ldb_data {
+	struct platform_device *pdev;
+	struct mxc_dispdrv_entry *disp_ldb;
+	uint32_t *reg;
+	uint32_t *control_reg;
+	uint32_t *gpr3_reg;
+	struct regulator *lvds_bg_reg;
+	int mode;
+	bool inited;
+	struct clk *di_clk[2];
+	struct clk *ldb_di_clk[2];
+	struct ldb_setting {
+		bool active;
+		bool clk_en;
+		int ipu;
+		int di;
+	} setting[2];
+	struct notifier_block nb;
+};
+
+static int g_ldb_mode;
+
+static struct fb_videomode ldb_modedb[] = {
+	{
+	 "LDB-XGA", 60, 1024, 768, 15385,
+	 220, 40,
+	 21, 7,
+	 60, 10,
+	 0,
+	 FB_VMODE_NONINTERLACED,
+	 FB_MODE_IS_DETAILED,},
+	{
+	 "LDB-1080P60", 60, 1920, 1080, 7692,
+	 100, 40,
+	 30, 3,
+	 10, 2,
+	 0,
+	 FB_VMODE_NONINTERLACED,
+	 FB_MODE_IS_DETAILED,},
+};
+static int ldb_modedb_sz = ARRAY_SIZE(ldb_modedb);
+
+static int bits_per_pixel(int pixel_fmt)
+{
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+		return 24;
+		break;
+	case IPU_PIX_FMT_BGR666:
+	case IPU_PIX_FMT_RGB666:
+	case IPU_PIX_FMT_LVDS666:
+		return 18;
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int valid_mode(int pixel_fmt)
+{
+	return ((pixel_fmt == IPU_PIX_FMT_RGB24) ||
+		(pixel_fmt == IPU_PIX_FMT_BGR24) ||
+		(pixel_fmt == IPU_PIX_FMT_LVDS666) ||
+		(pixel_fmt == IPU_PIX_FMT_RGB666) ||
+		(pixel_fmt == IPU_PIX_FMT_BGR666));
+}
+
+/*
+ *    "ldb=spl0/1"       --      split mode on DI0/1
+ *    "ldb=dul0/1"       --      dual mode on DI0/1
+ *    "ldb=sin0/1"       --      single mode on LVDS0/1
+ *    "ldb=sep0/1" 	 --      separate mode begin from LVDS0/1
+ *
+ *    there are two LVDS channels(LVDS0 and LVDS1) which can transfer video
+ *    datas, there two channels can be used as split/dual/single/separate mode.
+ *
+ *    split mode means display data from DI0 or DI1 will send to both channels
+ *    LVDS0+LVDS1.
+ *    dual mode means display data from DI0 or DI1 will be duplicated on LVDS0
+ *    and LVDS1, it said, LVDS0 and LVDS1 has the same content.
+ *    single mode means only work for DI0/DI1->LVDS0 or DI0/DI1->LVDS1.
+ *    separate mode means you can make DI0/DI1->LVDS0 and DI0/DI1->LVDS1 work
+ *    at the same time.
+ */
+static int __init ldb_setup(char *options)
+{
+	if (!strcmp(options, "spl0"))
+		g_ldb_mode = LDB_SPL_DI0;
+	else if (!strcmp(options, "spl1"))
+		g_ldb_mode = LDB_SPL_DI1;
+	else if (!strcmp(options, "dul0"))
+		g_ldb_mode = LDB_DUL_DI0;
+	else if (!strcmp(options, "dul1"))
+		g_ldb_mode = LDB_DUL_DI1;
+	else if (!strcmp(options, "sin0"))
+		g_ldb_mode = LDB_SIN0;
+	else if (!strcmp(options, "sin1"))
+		g_ldb_mode = LDB_SIN1;
+	else if (!strcmp(options, "sep0"))
+		g_ldb_mode = LDB_SEP0;
+	else if (!strcmp(options, "sep1"))
+		g_ldb_mode = LDB_SEP1;
+
+	return 1;
+}
+__setup("ldb=", ldb_setup);
+
+static int find_ldb_setting(struct ldb_data *ldb, struct fb_info *fbi)
+{
+	char *id_di[] = {
+		 "DISP3 BG",
+		 "DISP3 BG - DI1",
+		};
+	char id[16];
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		if (ldb->setting[i].active) {
+			memset(id, 0, 16);
+			memcpy(id, id_di[ldb->setting[i].di],
+				strlen(id_di[ldb->setting[i].di]));
+			id[4] += ldb->setting[i].ipu;
+			if (!strcmp(id, fbi->fix.id))
+				return i;
+		}
+	}
+	return -EINVAL;
+}
+
+int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct ldb_data *ldb = container_of(nb, struct ldb_data, nb);
+	struct fb_event *event = v;
+	struct fb_info *fbi = event->info;
+	int setting_idx, di;
+
+	setting_idx = find_ldb_setting(ldb, fbi);
+	if (setting_idx < 0)
+		return 0;
+
+	di = ldb->setting[setting_idx].di;
+
+	fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var,
+			&fbi->modelist);
+
+	if (!fbi->mode) {
+		dev_warn(&ldb->pdev->dev,
+				"LDB: can not find mode for xres=%d, yres=%d\n",
+				fbi->var.xres, fbi->var.yres);
+		if (ldb->setting[setting_idx].clk_en) {
+			clk_disable(ldb->ldb_di_clk[di]);
+			ldb->setting[setting_idx].clk_en = false;
+		}
+		return 0;
+	}
+
+	switch (val) {
+	case FB_EVENT_PREMODE_CHANGE:
+	{
+		uint32_t reg;
+		uint32_t pixel_clk, rounded_pixel_clk;
+		struct clk *ldb_clk_parent;
+
+		/* vsync setup */
+		reg = readl(ldb->control_reg);
+		if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) {
+			if (di == 0)
+				reg = (reg & ~LDB_DI0_VS_POL_MASK)
+					| LDB_DI0_VS_POL_ACT_HIGH;
+			else
+				reg = (reg & ~LDB_DI1_VS_POL_MASK)
+					| LDB_DI1_VS_POL_ACT_HIGH;
+		} else {
+			if (di == 0)
+				reg = (reg & ~LDB_DI0_VS_POL_MASK)
+					| LDB_DI0_VS_POL_ACT_LOW;
+			else
+				reg = (reg & ~LDB_DI1_VS_POL_MASK)
+					| LDB_DI1_VS_POL_ACT_LOW;
+		}
+		writel(reg, ldb->control_reg);
+
+		/* clk setup */
+		pixel_clk = (PICOS2KHZ(fbi->var.pixclock)) * 1000UL;
+		ldb_clk_parent = clk_get_parent(ldb->ldb_di_clk[di]);
+		if ((ldb->mode == LDB_SPL_DI0) || (ldb->mode == LDB_SPL_DI1))
+			clk_set_rate(ldb_clk_parent, pixel_clk * 7 / 2);
+		else
+			clk_set_rate(ldb_clk_parent, pixel_clk * 7);
+		rounded_pixel_clk = clk_round_rate(ldb->ldb_di_clk[di],
+				pixel_clk);
+		clk_set_rate(ldb->ldb_di_clk[di], rounded_pixel_clk);
+		clk_enable(ldb->ldb_di_clk[di]);
+		ldb->setting[setting_idx].clk_en = true;
+		break;
+	}
+	case FB_EVENT_BLANK:
+	{
+		if (*((int *)event->data) == FB_BLANK_UNBLANK) {
+			if (!ldb->setting[setting_idx].clk_en) {
+				clk_enable(ldb->ldb_di_clk[di]);
+				ldb->setting[setting_idx].clk_en = true;
+			}
+		} else {
+			if (ldb->setting[setting_idx].clk_en) {
+				clk_disable(ldb->ldb_di_clk[di]);
+				ldb->setting[setting_idx].clk_en = false;
+			}
+		}
+	}
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int ldb_disp_init(struct mxc_dispdrv_entry *disp)
+{
+	int ret = 0, i;
+	struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
+	struct mxc_dispdrv_setting *setting = mxc_dispdrv_getsetting(disp);
+	struct fsl_mxc_ldb_platform_data *plat_data = ldb->pdev->dev.platform_data;
+	struct resource *res;
+	uint32_t base_addr;
+	uint32_t reg, setting_idx;
+
+	/* if input format not valid, make RGB666 as default*/
+	if (!valid_mode(setting->if_fmt)) {
+		dev_warn(&ldb->pdev->dev, "Input pixel format not valid"
+					" use default RGB666\n");
+		setting->if_fmt = IPU_PIX_FMT_RGB666;
+	}
+
+	if (!ldb->inited) {
+		char di_clk[] = "ipu1_di0_clk";
+		char ldb_clk[] = "ldb_di0_clk";
+		int lvds_channel = 0;
+
+		res = platform_get_resource(ldb->pdev, IORESOURCE_MEM, 0);
+		if (IS_ERR(res))
+			return -ENOMEM;
+
+		base_addr = res->start;
+		ldb->reg = ioremap(base_addr, res->end - res->start + 1);
+		ldb->control_reg = ldb->reg + 2;
+		ldb->gpr3_reg = ldb->reg + 3;
+
+		ldb->lvds_bg_reg = regulator_get(&ldb->pdev->dev, plat_data->lvds_bg_reg);
+		if (!IS_ERR(ldb->lvds_bg_reg)) {
+			regulator_set_voltage(ldb->lvds_bg_reg, 2500000, 2500000);
+			regulator_enable(ldb->lvds_bg_reg);
+		}
+
+		/* ipu selected by platform data setting */
+		setting->dev_id = plat_data->ipu_id;
+
+		reg = readl(ldb->control_reg);
+
+		/* refrence resistor select */
+		reg &= ~LDB_BGREF_RMODE_MASK;
+		if (plat_data->ext_ref)
+			reg |= LDB_BGREF_RMODE_EXT;
+		else
+			reg |= LDB_BGREF_RMODE_INT;
+
+		/* TODO: now only use SPWG data mapping for both channel */
+		reg &= ~(LDB_BIT_MAP_CH0_MASK | LDB_BIT_MAP_CH1_MASK);
+		reg |= LDB_BIT_MAP_CH0_SPWG | LDB_BIT_MAP_CH1_SPWG;
+
+		/* channel mode setting */
+		reg &= ~(LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
+		reg &= ~(LDB_DATA_WIDTH_CH0_MASK | LDB_DATA_WIDTH_CH1_MASK);
+
+		if (bits_per_pixel(setting->if_fmt) == 24)
+			reg |= LDB_DATA_WIDTH_CH0_24 | LDB_DATA_WIDTH_CH1_24;
+		else
+			reg |= LDB_DATA_WIDTH_CH0_18 | LDB_DATA_WIDTH_CH1_18;
+
+		if (g_ldb_mode)
+			ldb->mode = g_ldb_mode;
+		else
+			ldb->mode = plat_data->mode;
+
+		if (ldb->mode == LDB_SPL_DI0) {
+			reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI0
+				| LDB_CH1_MODE_EN_TO_DI0;
+			setting->disp_id = 0;
+		} else if (ldb->mode == LDB_SPL_DI1) {
+			reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI1
+				| LDB_CH1_MODE_EN_TO_DI1;
+			setting->disp_id = 1;
+		} else if (ldb->mode == LDB_DUL_DI0) {
+			reg &= ~LDB_SPLIT_MODE_EN;
+			reg |= LDB_CH0_MODE_EN_TO_DI0 | LDB_CH1_MODE_EN_TO_DI0;
+			setting->disp_id = 0;
+		} else if (ldb->mode == LDB_DUL_DI1) {
+			reg &= ~LDB_SPLIT_MODE_EN;
+			reg |= LDB_CH0_MODE_EN_TO_DI1 | LDB_CH1_MODE_EN_TO_DI1;
+			setting->disp_id = 1;
+		} else if (ldb->mode == LDB_SIN0) {
+			reg &= ~LDB_SPLIT_MODE_EN;
+			setting->disp_id = plat_data->disp_id;
+			if (setting->disp_id == 0)
+				reg |= LDB_CH0_MODE_EN_TO_DI0;
+			else
+				reg |= LDB_CH0_MODE_EN_TO_DI1;
+		} else if (ldb->mode == LDB_SIN1) {
+			reg &= ~LDB_SPLIT_MODE_EN;
+			setting->disp_id = plat_data->disp_id;
+			if (setting->disp_id == 0)
+				reg |= LDB_CH1_MODE_EN_TO_DI0;
+			else
+				reg |= LDB_CH1_MODE_EN_TO_DI1;
+		} else { /* separate mode*/
+			setting->disp_id = plat_data->disp_id;
+
+			/* first output is LVDS0 or LVDS1 */
+			if (ldb->mode == LDB_SEP0)
+				lvds_channel = 0;
+			else
+				lvds_channel = 1;
+
+			reg &= ~LDB_SPLIT_MODE_EN;
+
+			if ((lvds_channel == 0) && (setting->disp_id == 0))
+				reg |= LDB_CH0_MODE_EN_TO_DI0;
+			else if ((lvds_channel == 0) && (setting->disp_id == 1))
+				reg |= LDB_CH0_MODE_EN_TO_DI1;
+			else if ((lvds_channel == 1) && (setting->disp_id == 0))
+				reg |= LDB_CH1_MODE_EN_TO_DI0;
+			else
+				reg |= LDB_CH1_MODE_EN_TO_DI1;
+
+			if (bits_per_pixel(setting->if_fmt) == 24) {
+				if (lvds_channel == 0)
+					reg &= ~LDB_DATA_WIDTH_CH1_24;
+				else
+					reg &= ~LDB_DATA_WIDTH_CH0_24;
+			} else {
+				if (lvds_channel == 0)
+					reg &= ~LDB_DATA_WIDTH_CH1_18;
+				else
+					reg &= ~LDB_DATA_WIDTH_CH0_18;
+			}
+		}
+
+		writel(reg, ldb->control_reg);
+
+		/* clock setting */
+		ldb_clk[6] += setting->disp_id;
+		ldb->ldb_di_clk[0] = clk_get(&ldb->pdev->dev, ldb_clk);
+		if (IS_ERR(ldb->ldb_di_clk[0])) {
+			dev_err(&ldb->pdev->dev, "get ldb clk0 failed\n");
+			iounmap(ldb->reg);
+			return PTR_ERR(ldb->ldb_di_clk[0]);
+		}
+		di_clk[3] += setting->dev_id;
+		di_clk[7] += setting->disp_id;
+		ldb->di_clk[0] = clk_get(&ldb->pdev->dev, di_clk);
+		if (IS_ERR(ldb->di_clk[0])) {
+			dev_err(&ldb->pdev->dev, "get di clk0 failed\n");
+			iounmap(ldb->reg);
+			return PTR_ERR(ldb->di_clk[0]);
+		}
+
+		dev_dbg(&ldb->pdev->dev, "ldb_clk to di clk: %s -> %s\n", ldb_clk, di_clk);
+
+		/* fb notifier for clk setting */
+		ldb->nb.notifier_call = ldb_fb_event,
+		ret = fb_register_client(&ldb->nb);
+		if (ret < 0) {
+			iounmap(ldb->reg);
+			return ret;
+		}
+
+		setting_idx = 0;
+		ldb->inited = true;
+	} else { /* second time for separate mode */
+		char di_clk[] = "ipu1_di0_clk";
+		char ldb_clk[] = "ldb_di0_clk";
+		int lvds_channel;
+
+		if ((ldb->mode == LDB_SPL_DI0) ||
+			(ldb->mode == LDB_SPL_DI1) ||
+			(ldb->mode == LDB_DUL_DI0) ||
+			(ldb->mode == LDB_DUL_DI1) ||
+			(ldb->mode == LDB_SIN0) ||
+			(ldb->mode == LDB_SIN1)) {
+			dev_err(&ldb->pdev->dev, "for second ldb disp"
+					"ldb mode should in separate mode\n");
+			return -EINVAL;
+		}
+
+		setting->dev_id = plat_data->ipu_id;
+		setting->disp_id = !plat_data->disp_id;
+
+		/* second output is LVDS0 or LVDS1 */
+		if (ldb->mode == LDB_SEP0)
+			lvds_channel = 1;
+		else
+			lvds_channel = 0;
+
+		reg = readl(ldb->control_reg);
+		if ((lvds_channel == 0) && (setting->disp_id == 0))
+			reg |= LDB_CH0_MODE_EN_TO_DI0;
+		else if ((lvds_channel == 0) && (setting->disp_id == 1))
+			reg |= LDB_CH0_MODE_EN_TO_DI1;
+		else if ((lvds_channel == 1) && (setting->disp_id == 0))
+			reg |= LDB_CH1_MODE_EN_TO_DI0;
+		else
+			reg |= LDB_CH1_MODE_EN_TO_DI1;
+
+		if (bits_per_pixel(setting->if_fmt) == 24) {
+			if (lvds_channel == 0)
+				reg |= LDB_DATA_WIDTH_CH0_24;
+			else
+				reg |= LDB_DATA_WIDTH_CH1_24;
+		} else {
+			if (lvds_channel == 0)
+				reg |= LDB_DATA_WIDTH_CH0_18;
+			else
+				reg |= LDB_DATA_WIDTH_CH1_18;
+		}
+		writel(reg, ldb->control_reg);
+
+		/* clock setting */
+		ldb_clk[6] += setting->disp_id;
+		ldb->ldb_di_clk[1] = clk_get(&ldb->pdev->dev, ldb_clk);
+		if (IS_ERR(ldb->ldb_di_clk[1])) {
+			dev_err(&ldb->pdev->dev, "get ldb clk1 failed\n");
+			return PTR_ERR(ldb->ldb_di_clk[1]);
+		}
+		di_clk[3] += setting->dev_id;
+		di_clk[7] += setting->disp_id;
+		ldb->di_clk[1] = clk_get(&ldb->pdev->dev, di_clk);
+		if (IS_ERR(ldb->di_clk[1])) {
+			dev_err(&ldb->pdev->dev, "get di clk1 failed\n");
+			return PTR_ERR(ldb->di_clk[1]);
+		}
+
+		dev_dbg(&ldb->pdev->dev, "ldb_clk to di clk: %s -> %s\n", ldb_clk, di_clk);
+
+		setting_idx = 1;
+	}
+
+	/*
+	 * ldb_di0_clk -> ipux_di0_clk
+	 * ldb_di1_clk -> ipux_di1_clk
+	 */
+	clk_set_parent(ldb->di_clk[setting_idx],
+			ldb->ldb_di_clk[setting_idx]);
+
+	/* must use spec video mode defined by driver */
+	ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
+				ldb_modedb, ldb_modedb_sz, NULL, setting->default_bpp);
+	if (ret != 1)
+		fb_videomode_to_var(&setting->fbi->var, &ldb_modedb[0]);
+
+	INIT_LIST_HEAD(&setting->fbi->modelist);
+	for (i = 0; i < ldb_modedb_sz; i++) {
+		struct fb_videomode m;
+		fb_var_to_videomode(&m, &setting->fbi->var);
+		if (fb_mode_is_equal(&m, &ldb_modedb[i])) {
+			fb_add_videomode(&ldb_modedb[i],
+					&setting->fbi->modelist);
+			break;
+		}
+	}
+
+	/* save current ldb setting for fb notifier */
+	ldb->setting[setting_idx].active = true;
+	ldb->setting[setting_idx].ipu = setting->dev_id;
+	ldb->setting[setting_idx].di = setting->disp_id;
+
+	return ret;
+}
+
+static void ldb_disp_deinit(struct mxc_dispdrv_entry *disp)
+{
+	struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
+	int i;
+
+	writel(0, ldb->control_reg);
+
+	for (i = 0; i < 2; i++) {
+		clk_disable(ldb->ldb_di_clk[i]);
+		clk_put(ldb->ldb_di_clk[i]);
+	}
+
+	fb_unregister_client(&ldb->nb);
+
+	iounmap(ldb->reg);
+}
+
+static struct mxc_dispdrv_driver ldb_drv = {
+	.name 	= DISPDRV_LDB,
+	.init 	= ldb_disp_init,
+	.deinit	= ldb_disp_deinit,
+};
+
+/*!
+ * This function is called by the driver framework to initialize the LDB
+ * device.
+ *
+ * @param	dev	The device structure for the LDB passed in by the
+ *			driver framework.
+ *
+ * @return      Returns 0 on success or negative error code on error
+ */
+static int ldb_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct ldb_data *ldb;
+
+	ldb = kzalloc(sizeof(struct ldb_data), GFP_KERNEL);
+	if (!ldb) {
+		ret = -ENOMEM;
+		goto alloc_failed;
+	}
+
+	ldb->pdev = pdev;
+	ldb->disp_ldb = mxc_dispdrv_register(&ldb_drv);
+	mxc_dispdrv_setdata(ldb->disp_ldb, ldb);
+
+	dev_set_drvdata(&pdev->dev, ldb);
+
+alloc_failed:
+	return ret;
+}
+
+static int ldb_remove(struct platform_device *pdev)
+{
+	struct ldb_data *ldb = dev_get_drvdata(&pdev->dev);
+
+	mxc_dispdrv_unregister(ldb->disp_ldb);
+	kfree(ldb);
+	return 0;
+}
+
+static struct platform_driver mxcldb_driver = {
+	.driver = {
+		   .name = "mxc_ldb",
+		   },
+	.probe = ldb_probe,
+	.remove = ldb_remove,
+};
+
+static int __init ldb_init(void)
+{
+	return platform_driver_register(&mxcldb_driver);
+}
+
+static void __exit ldb_uninit(void)
+{
+	platform_driver_unregister(&mxcldb_driver);
+}
+
+module_init(ldb_init);
+module_exit(ldb_uninit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC LDB driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxc_dispdrv.c b/drivers/video/mxc/mxc_dispdrv.c
new file mode 100644
index 00000000000..06b7af944f5
--- /dev/null
+++ b/drivers/video/mxc/mxc_dispdrv.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_dispdrv.c
+ * @brief mxc display driver framework.
+ *
+ * A display device driver could call mxc_dispdrv_register(drv) in its dev_probe() function.
+ * Move all dev_probe() things into mxc_dispdrv_driver->init(), init() function should init
+ * and feedback setting;
+ * Move all dev_remove() things into mxc_dispdrv_driver->deinit();
+ * Move all dev_suspend() things into fb_notifier for SUSPEND, if there is;
+ * Move all dev_resume() things into fb_notifier for RESUME, if there is;
+ *
+ * ipuv3 fb driver could call mxc_dispdrv_init(setting) before a fb need be added, with fbi param
+ * passing by setting, after mxc_dispdrv_init() return, FB driver should get the basic setting
+ * about fbi info and ipuv3-hw (ipu_id and disp_id).
+ *
+ * @ingroup Framebuffer
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include "mxc_dispdrv.h"
+
+static LIST_HEAD(dispdrv_list);
+static DEFINE_MUTEX(dispdrv_lock);
+
+struct mxc_dispdrv_entry {
+	const char *name;
+	struct list_head list;
+	int (*init) (struct mxc_dispdrv_entry *);
+	void (*deinit) (struct mxc_dispdrv_entry *);
+	bool active;
+	struct mxc_dispdrv_setting setting;
+	void *priv;
+};
+
+struct mxc_dispdrv_entry *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv)
+{
+	struct mxc_dispdrv_entry *new;
+
+	mutex_lock(&dispdrv_lock);
+
+	new = kzalloc(sizeof(struct mxc_dispdrv_entry), GFP_KERNEL);
+	if (!new) {
+		mutex_unlock(&dispdrv_lock);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	new->name = drv->name;
+	new->init = drv->init;
+	new->deinit = drv->deinit;
+
+	list_add_tail(&new->list, &dispdrv_list);
+	mutex_unlock(&dispdrv_lock);
+
+	return new;
+}
+EXPORT_SYMBOL_GPL(mxc_dispdrv_register);
+
+int mxc_dispdrv_unregister(struct mxc_dispdrv_entry *entry)
+{
+	if (entry) {
+		mutex_lock(&dispdrv_lock);
+		if (entry->active && entry->deinit)
+			entry->deinit(entry);
+		list_del(&entry->list);
+		mutex_unlock(&dispdrv_lock);
+		kfree(entry);
+		return 0;
+	} else
+		return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(mxc_dispdrv_unregister);
+
+int mxc_dispdrv_init(char *name, struct mxc_dispdrv_setting *setting)
+{
+	int ret = 0, found = 0;
+	struct mxc_dispdrv_entry *disp;
+
+	mutex_lock(&dispdrv_lock);
+	list_for_each_entry(disp, &dispdrv_list, list) {
+		if (!strcmp(disp->name, name)) {
+			if (disp->init) {
+				memcpy(&disp->setting, setting,
+						sizeof(struct mxc_dispdrv_setting));
+				ret = disp->init(disp);
+				if (ret >= 0) {
+					disp->active = true;
+					/* setting may need fix-up */
+					memcpy(setting, &disp->setting,
+							sizeof(struct mxc_dispdrv_setting));
+					found = 1;
+					break;
+				}
+			}
+		}
+	}
+
+	if (!found)
+		ret = -EINVAL;
+
+	mutex_unlock(&dispdrv_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mxc_dispdrv_init);
+
+int mxc_dispdrv_setdata(struct mxc_dispdrv_entry *entry, void *data)
+{
+	if (entry) {
+		entry->priv = data;
+		return 0;
+	} else
+		return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(mxc_dispdrv_setdata);
+
+void *mxc_dispdrv_getdata(struct mxc_dispdrv_entry *entry)
+{
+	if (entry) {
+		return entry->priv;
+	} else
+		return ERR_PTR(-EINVAL);
+}
+EXPORT_SYMBOL_GPL(mxc_dispdrv_getdata);
+
+struct mxc_dispdrv_setting
+	*mxc_dispdrv_getsetting(struct mxc_dispdrv_entry *entry)
+{
+	if (entry) {
+		return &entry->setting;
+	} else
+		return ERR_PTR(-EINVAL);
+}
+EXPORT_SYMBOL_GPL(mxc_dispdrv_getsetting);
diff --git a/drivers/video/mxc/mxc_dispdrv.h b/drivers/video/mxc/mxc_dispdrv.h
new file mode 100644
index 00000000000..f5f62a2c3cb
--- /dev/null
+++ b/drivers/video/mxc/mxc_dispdrv.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MXC_DISPDRV_H__
+#define __MXC_DISPDRV_H__
+
+struct mxc_dispdrv_entry;
+
+struct mxc_dispdrv_driver {
+	const char *name;
+	int (*init) (struct mxc_dispdrv_entry *);
+	void (*deinit) (struct mxc_dispdrv_entry *);
+};
+
+struct mxc_dispdrv_setting {
+	/*input-feedback parameter*/
+	struct fb_info *fbi;
+	int if_fmt;
+	int default_bpp;
+	char *dft_mode_str;
+
+	/*feedback parameter*/
+	int dev_id;
+	int disp_id;
+};
+
+struct mxc_dispdrv_entry *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv);
+int mxc_dispdrv_unregister(struct mxc_dispdrv_entry *entry);
+int mxc_dispdrv_init(char *name, struct mxc_dispdrv_setting *setting);
+int mxc_dispdrv_setdata(struct mxc_dispdrv_entry *entry, void *data);
+void *mxc_dispdrv_getdata(struct mxc_dispdrv_entry *entry);
+struct mxc_dispdrv_setting
+	*mxc_dispdrv_getsetting(struct mxc_dispdrv_entry *entry);
+#endif
diff --git a/drivers/video/mxc/mxc_edid.c b/drivers/video/mxc/mxc_edid.c
new file mode 100644
index 00000000000..0fa5cf97602
--- /dev/null
+++ b/drivers/video/mxc/mxc_edid.c
@@ -0,0 +1,451 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxc_edid.c
+ *
+ * @brief MXC EDID driver
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include "mxc_edid.h"
+#include "../edid.h"
+
+#undef DEBUG  /* define this for verbose EDID parsing output */
+
+#ifdef DEBUG
+#define DPRINTK(fmt, args...) printk(fmt, ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+const struct fb_videomode mxc_cea_mode[64] = {
+	/* #1: 640x480p@59.94/60Hz */
+	[1] = {
+		NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+	/* #3: 720x480p@59.94/60Hz */
+	[3] = {
+		NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+	/* #4: 1280x720p@59.94/60Hz */
+	[4] = {
+		NULL, 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+	/* #5: 1920x1080i@59.94/60Hz */
+	[5] = {
+		NULL, 60, 1920, 1080, 13763, 148, 88, 15, 2, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_INTERLACED, 0,
+	},
+	/* #7: 720(1440)x480iH@59.94/60Hz */
+	[7] = {
+		NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0,
+		FB_VMODE_INTERLACED, 0,
+	},
+	/* #9: 720(1440)x240pH@59.94/60Hz */
+	[9] = {
+		NULL, 60, 1440, 240, 18554, 114, 38, 16, 4, 124, 3, 0,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+	/* #16: 1920x1080p@60Hz */
+	[16] = {
+		NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+	/* #18: 720x576pH@50Hz */
+	[18] = {
+		NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+	/* #19: 1280x720p@50Hz */
+	[19] = {
+		NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+	/* #20: 1920x1080i@50Hz */
+	[20] = {
+		NULL, 50, 1920, 1080, 13480, 148, 528, 15, 5, 528, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_INTERLACED, 0,
+	},
+	/* #31: 1920x1080p@50Hz */
+	[31] = {
+		NULL, 50, 1920, 1080, 6734, 148, 528, 36, 4, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+	/* #32: 1920x1080p@23.98/24Hz */
+	[32] = {
+		NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+	/* #35: (2880)x480p4x@59.94/60Hz */
+	[35] = {
+		NULL, 60, 2880, 480, 9250, 240, 64, 30, 9, 248, 6, 0,
+		FB_VMODE_NONINTERLACED, 0,
+	},
+};
+
+static void get_detailed_timing(unsigned char *block,
+				struct fb_videomode *mode)
+{
+	mode->xres = H_ACTIVE;
+	mode->yres = V_ACTIVE;
+	mode->pixclock = PIXEL_CLOCK;
+	mode->pixclock /= 1000;
+	mode->pixclock = KHZ2PICOS(mode->pixclock);
+	mode->right_margin = H_SYNC_OFFSET;
+	mode->left_margin = (H_ACTIVE + H_BLANKING) -
+		(H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
+	mode->upper_margin = V_BLANKING - V_SYNC_OFFSET -
+		V_SYNC_WIDTH;
+	mode->lower_margin = V_SYNC_OFFSET;
+	mode->hsync_len = H_SYNC_WIDTH;
+	mode->vsync_len = V_SYNC_WIDTH;
+	if (HSYNC_POSITIVE)
+		mode->sync |= FB_SYNC_HOR_HIGH_ACT;
+	if (VSYNC_POSITIVE)
+		mode->sync |= FB_SYNC_VERT_HIGH_ACT;
+	mode->refresh = PIXEL_CLOCK/((H_ACTIVE + H_BLANKING) *
+				     (V_ACTIVE + V_BLANKING));
+	if (INTERLACED) {
+		mode->yres *= 2;
+		mode->upper_margin *= 2;
+		mode->lower_margin *= 2;
+		mode->vsync_len *= 2;
+		mode->vmode |= FB_VMODE_INTERLACED;
+	}
+	mode->flag = FB_MODE_IS_DETAILED;
+
+	DPRINTK("      %d MHz ",  PIXEL_CLOCK/1000000);
+	DPRINTK("%d %d %d %d ", H_ACTIVE, H_ACTIVE + H_SYNC_OFFSET,
+	       H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, H_ACTIVE + H_BLANKING);
+	DPRINTK("%d %d %d %d ", V_ACTIVE, V_ACTIVE + V_SYNC_OFFSET,
+	       V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, V_ACTIVE + V_BLANKING);
+	DPRINTK("%sHSync %sVSync\n\n", (HSYNC_POSITIVE) ? "+" : "-",
+	       (VSYNC_POSITIVE) ? "+" : "-");
+}
+
+int mxc_edid_parse_ext_blk(unsigned char *edid,
+		struct mxc_edid_cfg *cfg,
+		struct fb_monspecs *specs)
+{
+	char detail_timing_desc_offset;
+	struct fb_videomode *mode, *m;
+	unsigned char index = 0x0;
+	unsigned char *block;
+	int i, num = 0, revision;
+
+	if (edid[index++] != 0x2) /* only support cea ext block now */
+		return -1;
+	revision = edid[index++];
+	DPRINTK("cea extent revision %d\n", revision);
+	mode = kzalloc(50 * sizeof(struct fb_videomode), GFP_KERNEL);
+	if (mode == NULL)
+		return -1;
+
+	detail_timing_desc_offset = edid[index++];
+
+	if (revision >= 2) {
+		cfg->cea_underscan = (edid[index] >> 7) & 0x1;
+		cfg->cea_basicaudio = (edid[index] >> 6) & 0x1;
+		cfg->cea_ycbcr444 = (edid[index] >> 5) & 0x1;
+		cfg->cea_ycbcr422 = (edid[index] >> 4) & 0x1;
+
+		DPRINTK("CEA underscan %d\n", cfg->cea_underscan);
+		DPRINTK("CEA basicaudio %d\n", cfg->cea_basicaudio);
+		DPRINTK("CEA ycbcr444 %d\n", cfg->cea_ycbcr444);
+		DPRINTK("CEA ycbcr422 %d\n", cfg->cea_ycbcr422);
+	}
+
+	if (revision >= 3) {
+		/* short desc */
+		DPRINTK("CEA Short desc timmings\n");
+		index++;
+		while (index < detail_timing_desc_offset) {
+			unsigned char tagcode, blklen;
+
+			tagcode = (edid[index] >> 5) & 0x7;
+			blklen = (edid[index]) & 0x1f;
+
+			DPRINTK("Tagcode %x Len %d\n", tagcode, blklen);
+
+			switch (tagcode) {
+			case 0x2: /*Video data block*/
+				{
+					int cea_idx;
+					i = 0;
+					while (i < blklen) {
+						index++;
+						cea_idx = edid[index] & 0x7f;
+						if (cea_idx < ARRAY_SIZE(mxc_cea_mode) &&
+								(mxc_cea_mode[cea_idx].xres)) {
+							DPRINTK("Support CEA Format #%d\n", cea_idx);
+							mode[num] = mxc_cea_mode[cea_idx];
+							mode[num].flag |= FB_MODE_IS_STANDARD;
+							num++;
+						}
+						i++;
+					}
+					break;
+				}
+			case 0x3: /*Vendor specific data*/
+				{
+					unsigned char IEEE_reg_iden[3];
+					unsigned char deep_color;
+					IEEE_reg_iden[0] = edid[index+1];
+					IEEE_reg_iden[1] = edid[index+2];
+					IEEE_reg_iden[2] = edid[index+3];
+					deep_color = edid[index+6];
+
+					if ((IEEE_reg_iden[0] == 0x03) &&
+							(IEEE_reg_iden[1] == 0x0c) &&
+							(IEEE_reg_iden[2] == 0x00))
+						cfg->hdmi_cap = 1;
+
+					if (deep_color & 0x40)
+						cfg->vsd_dc_48bit = true;
+					if (deep_color & 0x20)
+						cfg->vsd_dc_36bit = true;
+					if (deep_color & 0x10)
+						cfg->vsd_dc_30bit = true;
+					if (deep_color & 0x08)
+						cfg->vsd_dc_y444 = true;
+					if (deep_color & 0x01)
+						cfg->vsd_dvi_dual = true;
+
+					DPRINTK("VSD hdmi capability %d\n", cfg->hdmi_cap);
+					DPRINTK("VSD support deep color 48bit %d\n", cfg->vsd_dc_48bit);
+					DPRINTK("VSD support deep color 36bit %d\n", cfg->vsd_dc_36bit);
+					DPRINTK("VSD support deep color 30bit %d\n", cfg->vsd_dc_30bit);
+					DPRINTK("VSD support deep color y444 %d\n", cfg->vsd_dc_y444);
+					DPRINTK("VSD support dvi dual %d\n", cfg->vsd_dvi_dual);
+
+					index += blklen;
+					break;
+				}
+			case 0x1: /*Audio data block*/
+			case 0x4: /*Speaker allocation block*/
+			case 0x7: /*User extended block*/
+			default:
+				/* skip */
+				index += blklen;
+				break;
+			}
+
+			index++;
+		}
+	}
+
+	/* long desc */
+	DPRINTK("CEA long desc timmings\n");
+	index = detail_timing_desc_offset;
+	block = edid + index;
+	while (index < (EDID_LENGTH - DETAILED_TIMING_DESCRIPTION_SIZE)) {
+		if (!(block[0] == 0x00 && block[1] == 0x00)) {
+			get_detailed_timing(block, &mode[num]);
+			num++;
+		}
+		block += DETAILED_TIMING_DESCRIPTION_SIZE;
+		index += DETAILED_TIMING_DESCRIPTION_SIZE;
+	}
+
+	if (!num) {
+		kfree(mode);
+		return 0;
+	}
+
+	m = kmalloc((num + specs->modedb_len) *
+			sizeof(struct fb_videomode), GFP_KERNEL);
+	if (!m)
+		return 0;
+
+	if (specs->modedb_len) {
+		memmove(m, specs->modedb,
+			specs->modedb_len * sizeof(struct fb_videomode));
+		kfree(specs->modedb);
+	}
+	memmove(m+specs->modedb_len, mode,
+		num * sizeof(struct fb_videomode));
+	kfree(mode);
+
+	specs->modedb_len += num;
+	specs->modedb = m;
+
+	return 0;
+}
+
+static int mxc_edid_readblk(struct i2c_adapter *adp,
+		unsigned short addr, unsigned char *edid)
+{
+	int ret = 0, extblknum = 0;
+	unsigned char regaddr = 0x0;
+	struct i2c_msg msg[2] = {
+		{
+		.addr	= addr,
+		.flags	= 0,
+		.len	= 1,
+		.buf	= &regaddr,
+		}, {
+		.addr	= addr,
+		.flags	= I2C_M_RD,
+		.len	= EDID_LENGTH,
+		.buf	= edid,
+		},
+	};
+
+	ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
+	if (ret != ARRAY_SIZE(msg)) {
+		DPRINTK("unable to read EDID block\n");
+		return -EIO;
+	}
+
+	if (edid[1] == 0x00)
+		return -ENOENT;
+
+	extblknum = edid[0x7E];
+
+	if (extblknum) {
+		regaddr = 128;
+		msg[1].buf = edid + EDID_LENGTH;
+
+		ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
+		if (ret != ARRAY_SIZE(msg)) {
+			DPRINTK("unable to read EDID ext block\n");
+			return -EIO;
+		}
+	}
+
+	return extblknum;
+}
+
+static int mxc_edid_readsegblk(struct i2c_adapter *adp, unsigned short addr,
+			unsigned char *edid, int seg_num)
+{
+	int ret = 0;
+	unsigned char segment = 0x1, regaddr = 0;
+	struct i2c_msg msg[3] = {
+		{
+		.addr	= 0x30,
+		.flags	= 0,
+		.len	= 1,
+		.buf	= &segment,
+		}, {
+		.addr	= addr,
+		.flags	= 0,
+		.len	= 1,
+		.buf	= &regaddr,
+		}, {
+		.addr	= addr,
+		.flags	= I2C_M_RD,
+		.len	= EDID_LENGTH,
+		.buf	= edid,
+		},
+	};
+
+	ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
+	if (ret != ARRAY_SIZE(msg)) {
+		DPRINTK("unable to read EDID block\n");
+		return -EIO;
+	}
+
+	if (seg_num == 2) {
+		regaddr = 128;
+		msg[2].buf = edid + EDID_LENGTH;
+
+		ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
+		if (ret != ARRAY_SIZE(msg)) {
+			DPRINTK("unable to read EDID block\n");
+			return -EIO;
+		}
+	}
+
+	return ret;
+}
+
+int mxc_edid_var_to_vic(struct fb_var_screeninfo *var)
+{
+	int i;
+	struct fb_videomode m;
+
+	for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
+		fb_var_to_videomode(&m, var);
+		if (fb_mode_is_equal(&m, &mxc_cea_mode[i]))
+			break;
+	}
+
+	if (i == ARRAY_SIZE(mxc_cea_mode))
+		return 0;
+
+	return i;
+}
+EXPORT_SYMBOL(mxc_edid_var_to_vic);
+
+/* make sure edid has 512 bytes*/
+int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
+	unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi)
+{
+	int ret = 0, extblknum;
+	if (!adp || !edid || !cfg || !fbi)
+		return -EINVAL;
+
+	memset(edid, 0, EDID_LENGTH*4);
+	memset(cfg, 0, sizeof(struct mxc_edid_cfg));
+
+	extblknum = mxc_edid_readblk(adp, addr, edid);
+	if (extblknum < 0)
+		return extblknum;
+
+	/* edid first block parsing */
+	memset(&fbi->monspecs, 0, sizeof(fbi->monspecs));
+	fb_edid_to_monspecs(edid, &fbi->monspecs);
+
+	if (extblknum) {
+		int i;
+
+		/* need read segment block? */
+		if (extblknum > 1) {
+			ret = mxc_edid_readsegblk(adp, addr,
+				edid + EDID_LENGTH*2, extblknum - 1);
+			if (ret < 0)
+				return ret;
+		}
+
+		for (i = 1; i <= extblknum; i++)
+			/* edid ext block parsing */
+			mxc_edid_parse_ext_blk(edid + i*EDID_LENGTH,
+					cfg, &fbi->monspecs);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(mxc_edid_read);
diff --git a/drivers/video/mxc/mxc_edid.h b/drivers/video/mxc/mxc_edid.h
new file mode 100644
index 00000000000..ec65a5fa9bd
--- /dev/null
+++ b/drivers/video/mxc/mxc_edid.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxc_edid.h
+ *
+ * @brief MXC EDID tools
+ *
+ * @ingroup Framebuffer
+ */
+
+#ifndef MXC_EDID_H
+#define MXC_EDID_H
+
+struct mxc_edid_cfg {
+	bool cea_underscan;
+	bool cea_basicaudio;
+	bool cea_ycbcr444;
+	bool cea_ycbcr422;
+	bool hdmi_cap;
+
+	/*VSD*/
+	bool vsd_dc_48bit;
+	bool vsd_dc_36bit;
+	bool vsd_dc_30bit;
+	bool vsd_dc_y444;
+	bool vsd_dvi_dual;
+};
+
+int mxc_edid_var_to_vic(struct fb_var_screeninfo *var);
+int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
+	unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi);
+
+#endif
diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c
new file mode 100644
index 00000000000..260b41a3ddf
--- /dev/null
+++ b/drivers/video/mxc/mxc_ipuv3_fb.c
@@ -0,0 +1,2072 @@
+/*
+ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxcfb.c
+ *
+ * @brief MXC Frame buffer driver for SDC
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/io.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <linux/uaccess.h>
+#include <linux/fsl_devices.h>
+#include <asm/mach-types.h>
+#include <mach/ipu-v3.h>
+#include "mxc_dispdrv.h"
+
+/*
+ * Driver name
+ */
+#define MXCFB_NAME      "mxc_sdc_fb"
+
+/* Display port number */
+#define MXCFB_PORT_NUM	2
+/*!
+ * Structure containing the MXC specific framebuffer information.
+ */
+struct mxcfb_info {
+	int default_bpp;
+	int cur_blank;
+	int next_blank;
+	ipu_channel_t ipu_ch;
+	int ipu_id;
+	int ipu_di;
+	u32 ipu_di_pix_fmt;
+	bool ipu_int_clk;
+	bool overlay;
+	bool alpha_chan_en;
+	dma_addr_t alpha_phy_addr0;
+	dma_addr_t alpha_phy_addr1;
+	void *alpha_virt_addr0;
+	void *alpha_virt_addr1;
+	uint32_t alpha_mem_len;
+	uint32_t ipu_ch_irq;
+	uint32_t ipu_alp_ch_irq;
+	uint32_t cur_ipu_buf;
+	uint32_t cur_ipu_alpha_buf;
+
+	u32 pseudo_palette[16];
+
+	bool mode_found;
+	volatile bool wait4vsync;
+	struct semaphore flip_sem;
+	struct semaphore alpha_flip_sem;
+	struct completion vsync_complete;
+
+	void *ipu;
+	struct fb_info *ovfbi;
+};
+
+struct mxcfb_alloc_list {
+	struct list_head list;
+	dma_addr_t phy_addr;
+	void *cpu_addr;
+	u32 size;
+};
+
+enum {
+	BOTH_ON,
+	SRC_ON,
+	TGT_ON,
+	BOTH_OFF
+};
+
+static bool g_dp_in_use[2];
+LIST_HEAD(fb_alloc_list);
+
+static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
+{
+	uint32_t pixfmt = 0;
+
+	if (fbi->var.nonstd)
+		return fbi->var.nonstd;
+
+	switch (fbi->var.bits_per_pixel) {
+	case 24:
+		pixfmt = IPU_PIX_FMT_BGR24;
+		break;
+	case 32:
+		pixfmt = IPU_PIX_FMT_BGR32;
+		break;
+	case 16:
+		pixfmt = IPU_PIX_FMT_RGB565;
+		break;
+	}
+	return pixfmt;
+}
+
+static struct fb_info *found_registered_fb(ipu_channel_t ipu_ch, int ipu_id)
+{
+	int i;
+	struct mxcfb_info *mxc_fbi;
+	struct fb_info *fbi = NULL;
+
+	for (i = 0; i < num_registered_fb; i++) {
+		mxc_fbi =
+			((struct mxcfb_info *)(registered_fb[i]->par));
+
+		if ((mxc_fbi->ipu_ch == ipu_ch) &&
+			(mxc_fbi->ipu_id == ipu_id)) {
+			fbi = registered_fb[i];
+			break;
+		}
+	}
+	return fbi;
+}
+
+static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id);
+static int mxcfb_blank(int blank, struct fb_info *info);
+static int mxcfb_map_video_memory(struct fb_info *fbi);
+static int mxcfb_unmap_video_memory(struct fb_info *fbi);
+
+/*
+ * Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 1;
+	fix->ywrapstep = 1;
+	fix->ypanstep = 1;
+
+	return 0;
+}
+
+static int _setup_disp_channel1(struct fb_info *fbi)
+{
+	ipu_channel_params_t params;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	memset(&params, 0, sizeof(params));
+
+	if (mxc_fbi->ipu_ch == MEM_DC_SYNC) {
+		params.mem_dc_sync.di = mxc_fbi->ipu_di;
+		if (fbi->var.vmode & FB_VMODE_INTERLACED)
+			params.mem_dc_sync.interlaced = true;
+		params.mem_dc_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+		params.mem_dc_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
+	} else {
+		params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
+		if (fbi->var.vmode & FB_VMODE_INTERLACED)
+			params.mem_dp_bg_sync.interlaced = true;
+		params.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+		params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
+		if (mxc_fbi->alpha_chan_en)
+			params.mem_dp_bg_sync.alpha_chan_en = true;
+	}
+	ipu_init_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, &params);
+
+	return 0;
+}
+
+static int _setup_disp_channel2(struct fb_info *fbi)
+{
+	int retval = 0;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+	int fb_stride;
+	unsigned long base;
+
+	switch (bpp_to_pixfmt(fbi)) {
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_NV12:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV420P:
+		fb_stride = fbi->var.xres_virtual;
+		break;
+	default:
+		fb_stride = fbi->fix.line_length;
+	}
+
+	mxc_fbi->cur_ipu_buf = 2;
+	sema_init(&mxc_fbi->flip_sem, 1);
+	if (mxc_fbi->alpha_chan_en) {
+		mxc_fbi->cur_ipu_alpha_buf = 1;
+		sema_init(&mxc_fbi->alpha_flip_sem, 1);
+	}
+	fbi->var.xoffset = 0;
+
+	base = (fbi->var.yoffset * fb_stride + fbi->var.xoffset);
+	base += fbi->fix.smem_start;
+
+	retval = ipu_init_channel_buffer(mxc_fbi->ipu,
+					 mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+					 bpp_to_pixfmt(fbi),
+					 fbi->var.xres, fbi->var.yres,
+					 fb_stride,
+					 fbi->var.rotate,
+					 base,
+					 base,
+					 fbi->var.accel_flags &
+						FB_ACCEL_DOUBLE_FLAG ? 0 : base,
+					 0, 0);
+	if (retval) {
+		dev_err(fbi->device,
+			"ipu_init_channel_buffer error %d\n", retval);
+	}
+
+	if (mxc_fbi->alpha_chan_en) {
+		retval = ipu_init_channel_buffer(mxc_fbi->ipu,
+						 mxc_fbi->ipu_ch,
+						 IPU_ALPHA_IN_BUFFER,
+						 IPU_PIX_FMT_GENERIC,
+						 fbi->var.xres, fbi->var.yres,
+						 fbi->var.xres,
+						 fbi->var.rotate,
+						 mxc_fbi->alpha_phy_addr1,
+						 mxc_fbi->alpha_phy_addr0,
+						 0,
+						 0, 0);
+		if (retval) {
+			dev_err(fbi->device,
+				"ipu_init_channel_buffer error %d\n", retval);
+			return retval;
+		}
+	}
+
+	return retval;
+}
+
+/*
+ * Set framebuffer parameters and change the operating mode.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_par(struct fb_info *fbi)
+{
+	int retval = 0;
+	u32 mem_len, alpha_mem_len;
+	ipu_di_signal_cfg_t sig_cfg;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	dev_dbg(fbi->device, "Reconfiguring framebuffer\n");
+
+	ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+	ipu_disable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+	ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
+	ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
+	mxcfb_set_fix(fbi);
+
+	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
+	if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
+		if (fbi->fix.smem_start)
+			mxcfb_unmap_video_memory(fbi);
+
+		if (mxcfb_map_video_memory(fbi) < 0)
+			return -ENOMEM;
+	}
+
+	if (mxc_fbi->alpha_chan_en) {
+		alpha_mem_len = fbi->var.xres * fbi->var.yres;
+		if ((!mxc_fbi->alpha_phy_addr0 && !mxc_fbi->alpha_phy_addr1) ||
+		    (alpha_mem_len > mxc_fbi->alpha_mem_len)) {
+			if (mxc_fbi->alpha_phy_addr0)
+				dma_free_coherent(fbi->device,
+						  mxc_fbi->alpha_mem_len,
+						  mxc_fbi->alpha_virt_addr0,
+						  mxc_fbi->alpha_phy_addr0);
+			if (mxc_fbi->alpha_phy_addr1)
+				dma_free_coherent(fbi->device,
+						  mxc_fbi->alpha_mem_len,
+						  mxc_fbi->alpha_virt_addr1,
+						  mxc_fbi->alpha_phy_addr1);
+
+			mxc_fbi->alpha_virt_addr0 =
+					dma_alloc_coherent(fbi->device,
+						  alpha_mem_len,
+						  &mxc_fbi->alpha_phy_addr0,
+						  GFP_DMA | GFP_KERNEL);
+
+			mxc_fbi->alpha_virt_addr1 =
+					dma_alloc_coherent(fbi->device,
+						  alpha_mem_len,
+						  &mxc_fbi->alpha_phy_addr1,
+						  GFP_DMA | GFP_KERNEL);
+			if (mxc_fbi->alpha_virt_addr0 == NULL ||
+			    mxc_fbi->alpha_virt_addr1 == NULL) {
+				dev_err(fbi->device, "mxcfb: dma alloc for"
+					" alpha buffer failed.\n");
+				if (mxc_fbi->alpha_virt_addr0)
+					dma_free_coherent(fbi->device,
+						  mxc_fbi->alpha_mem_len,
+						  mxc_fbi->alpha_virt_addr0,
+						  mxc_fbi->alpha_phy_addr0);
+				if (mxc_fbi->alpha_virt_addr1)
+					dma_free_coherent(fbi->device,
+						  mxc_fbi->alpha_mem_len,
+						  mxc_fbi->alpha_virt_addr1,
+						  mxc_fbi->alpha_phy_addr1);
+				return -ENOMEM;
+			}
+			mxc_fbi->alpha_mem_len = alpha_mem_len;
+		}
+	}
+
+	if (mxc_fbi->next_blank != FB_BLANK_UNBLANK)
+		return retval;
+
+	_setup_disp_channel1(fbi);
+
+	if (!mxc_fbi->overlay) {
+		uint32_t out_pixel_fmt;
+
+		memset(&sig_cfg, 0, sizeof(sig_cfg));
+		if (fbi->var.vmode & FB_VMODE_INTERLACED)
+			sig_cfg.interlaced = true;
+		out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+		if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
+			sig_cfg.odd_field_first = true;
+		if (mxc_fbi->ipu_int_clk)
+			sig_cfg.int_clk = true;
+		if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
+			sig_cfg.Hsync_pol = true;
+		if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
+			sig_cfg.Vsync_pol = true;
+		if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
+			sig_cfg.clk_pol = true;
+		if (fbi->var.sync & FB_SYNC_DATA_INVERT)
+			sig_cfg.data_pol = true;
+		if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
+			sig_cfg.enable_pol = true;
+		if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
+			sig_cfg.clkidle_en = true;
+
+		dev_dbg(fbi->device, "pixclock = %ul Hz\n",
+			(u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+
+		if (ipu_init_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di,
+					(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
+					fbi->var.xres, fbi->var.yres,
+					out_pixel_fmt,
+					fbi->var.left_margin,
+					fbi->var.hsync_len,
+					fbi->var.right_margin,
+					fbi->var.upper_margin,
+					fbi->var.vsync_len,
+					fbi->var.lower_margin,
+					0, sig_cfg) != 0) {
+			dev_err(fbi->device,
+				"mxcfb: Error initializing panel.\n");
+			return -EINVAL;
+		}
+
+		fbi->mode =
+		    (struct fb_videomode *)fb_match_mode(&fbi->var,
+							 &fbi->modelist);
+
+		ipu_disp_set_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch, 0, 0);
+	}
+
+	retval = _setup_disp_channel2(fbi);
+	if (retval)
+		return retval;
+
+	ipu_enable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
+
+	return retval;
+}
+
+static int _swap_channels(struct fb_info *fbi_from,
+			  struct fb_info *fbi_to, bool both_on)
+{
+	int retval, tmp;
+	ipu_channel_t old_ch;
+	struct fb_info *ovfbi;
+	struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi_from->par;
+	struct mxcfb_info *mxc_fbi_to = (struct mxcfb_info *)fbi_to->par;
+
+	if (both_on) {
+		ipu_disable_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch, true);
+		ipu_uninit_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch);
+	}
+
+	/* switch the mxc fbi parameters */
+	old_ch = mxc_fbi_from->ipu_ch;
+	mxc_fbi_from->ipu_ch = mxc_fbi_to->ipu_ch;
+	mxc_fbi_to->ipu_ch = old_ch;
+	tmp = mxc_fbi_from->ipu_ch_irq;
+	mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
+	mxc_fbi_to->ipu_ch_irq = tmp;
+	ovfbi = mxc_fbi_from->ovfbi;
+	mxc_fbi_from->ovfbi = mxc_fbi_to->ovfbi;
+	mxc_fbi_to->ovfbi = ovfbi;
+
+	_setup_disp_channel1(fbi_from);
+	retval = _setup_disp_channel2(fbi_from);
+	if (retval)
+		return retval;
+
+	/* switch between dp and dc, disable old idmac, enable new idmac */
+	retval = ipu_swap_channel(mxc_fbi_from->ipu, old_ch, mxc_fbi_from->ipu_ch);
+	ipu_uninit_channel(mxc_fbi_from->ipu, old_ch);
+
+	if (both_on) {
+		_setup_disp_channel1(fbi_to);
+		retval = _setup_disp_channel2(fbi_to);
+		if (retval)
+			return retval;
+		ipu_enable_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch);
+	}
+
+	return retval;
+}
+
+static int swap_channels(struct fb_info *fbi_from)
+{
+	int i;
+	int swap_mode;
+	ipu_channel_t ch_to;
+	struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi_from->par;
+	struct fb_info *fbi_to = NULL;
+	struct mxcfb_info *mxc_fbi_to;
+
+	/* what's the target channel? */
+	if (mxc_fbi_from->ipu_ch == MEM_BG_SYNC)
+		ch_to = MEM_DC_SYNC;
+	else
+		ch_to = MEM_BG_SYNC;
+
+	fbi_to = found_registered_fb(ch_to, mxc_fbi_from->ipu_id);
+	if (!fbi_to)
+		return -1;
+	mxc_fbi_to = (struct mxcfb_info *)fbi_to->par;
+
+	ipu_clear_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq);
+	ipu_clear_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq);
+	ipu_free_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq, fbi_from);
+	ipu_free_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq, fbi_to);
+
+	if (mxc_fbi_from->cur_blank == FB_BLANK_UNBLANK) {
+		if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
+			swap_mode = BOTH_ON;
+		else
+			swap_mode = SRC_ON;
+	} else {
+		if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
+			swap_mode = TGT_ON;
+		else
+			swap_mode = BOTH_OFF;
+	}
+
+	switch (swap_mode) {
+	case BOTH_ON:
+		/* disable target->switch src->enable target */
+		_swap_channels(fbi_from, fbi_to, true);
+		break;
+	case SRC_ON:
+		/* just switch src */
+		_swap_channels(fbi_from, fbi_to, false);
+		break;
+	case TGT_ON:
+		/* just switch target */
+		_swap_channels(fbi_to, fbi_from, false);
+		break;
+	case BOTH_OFF:
+		/* switch directly, no more need to do */
+		mxc_fbi_to->ipu_ch = mxc_fbi_from->ipu_ch;
+		mxc_fbi_from->ipu_ch = ch_to;
+		i = mxc_fbi_from->ipu_ch_irq;
+		mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
+		mxc_fbi_to->ipu_ch_irq = i;
+		break;
+	default:
+		break;
+	}
+
+	if (ipu_request_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq, mxcfb_irq_handler, 0,
+		MXCFB_NAME, fbi_from) != 0) {
+		dev_err(fbi_from->device, "Error registering irq %d\n",
+			mxc_fbi_from->ipu_ch_irq);
+		return -EBUSY;
+	}
+	ipu_disable_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq);
+	if (ipu_request_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq, mxcfb_irq_handler, 0,
+		MXCFB_NAME, fbi_to) != 0) {
+		dev_err(fbi_to->device, "Error registering irq %d\n",
+			mxc_fbi_to->ipu_ch_irq);
+		return -EBUSY;
+	}
+	ipu_disable_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq);
+
+	return 0;
+}
+
+/*
+ * Check framebuffer variable parameters and adjust to valid values.
+ *
+ * @param       var      framebuffer variable parameters
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	u32 vtotal;
+	u32 htotal;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
+
+	/* fg should not bigger than bg */
+	if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
+		struct fb_info *fbi_tmp;
+		int bg_xres = 0, bg_yres = 0;
+		int16_t pos_x, pos_y;
+
+		bg_xres = var->xres;
+		bg_yres = var->yres;
+
+		fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
+		if (fbi_tmp) {
+			bg_xres = fbi_tmp->var.xres;
+			bg_yres = fbi_tmp->var.yres;
+		}
+
+		ipu_disp_get_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch, &pos_x, &pos_y);
+
+		if ((var->xres + pos_x) > bg_xres)
+			var->xres = bg_xres - pos_x;
+		if ((var->yres + pos_y) > bg_yres)
+			var->yres = bg_yres - pos_y;
+	}
+
+	if (var->rotate > IPU_ROTATE_VERT_FLIP)
+		var->rotate = IPU_ROTATE_NONE;
+
+	if (var->xres_virtual < var->xres)
+		var->xres_virtual = var->xres;
+
+	if (var->yres_virtual < var->yres)
+		var->yres_virtual = var->yres * 3;
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 12) &&
+	    (var->bits_per_pixel != 8))
+		var->bits_per_pixel = 16;
+
+	switch (var->bits_per_pixel) {
+	case 8:
+		var->red.length = 3;
+		var->red.offset = 5;
+		var->red.msb_right = 0;
+
+		var->green.length = 3;
+		var->green.offset = 2;
+		var->green.msb_right = 0;
+
+		var->blue.length = 2;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	if (var->pixclock < 1000) {
+		htotal = var->xres + var->right_margin + var->hsync_len +
+		    var->left_margin;
+		vtotal = var->yres + var->lower_margin + var->vsync_len +
+		    var->upper_margin;
+		var->pixclock = (vtotal * htotal * 6UL) / 100UL;
+		var->pixclock = KHZ2PICOS(var->pixclock);
+		dev_dbg(info->device,
+			"pixclock set for 60Hz refresh = %u ps\n",
+			var->pixclock);
+	}
+
+	var->height = -1;
+	var->width = -1;
+	var->grayscale = 0;
+
+	return 0;
+}
+
+static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+	chan &= 0xffff;
+	chan >>= 16 - bf->length;
+	return chan << bf->offset;
+}
+
+static int mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+			   u_int trans, struct fb_info *fbi)
+{
+	unsigned int val;
+	int ret = 1;
+
+	/*
+	 * If greyscale is true, then we convert the RGB value
+	 * to greyscale no matter what visual we are using.
+	 */
+	if (fbi->var.grayscale)
+		red = green = blue = (19595 * red + 38470 * green +
+				      7471 * blue) >> 16;
+	switch (fbi->fix.visual) {
+	case FB_VISUAL_TRUECOLOR:
+		/*
+		 * 16-bit True Colour.  We encode the RGB value
+		 * according to the RGB bitfield information.
+		 */
+		if (regno < 16) {
+			u32 *pal = fbi->pseudo_palette;
+
+			val = _chan_to_field(red, &fbi->var.red);
+			val |= _chan_to_field(green, &fbi->var.green);
+			val |= _chan_to_field(blue, &fbi->var.blue);
+
+			pal[regno] = val;
+			ret = 0;
+		}
+		break;
+
+	case FB_VISUAL_STATIC_PSEUDOCOLOR:
+	case FB_VISUAL_PSEUDOCOLOR:
+		break;
+	}
+
+	return ret;
+}
+
+/*
+ * Function to handle custom ioctls for MXC framebuffer.
+ *
+ * @param       inode   inode struct
+ *
+ * @param       file    file struct
+ *
+ * @param       cmd     Ioctl command to handle
+ *
+ * @param       arg     User pointer to command arguments
+ *
+ * @param       fbi     framebuffer information pointer
+ */
+static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
+{
+	int retval = 0;
+	int __user *argp = (void __user *)arg;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	switch (cmd) {
+	case MXCFB_SET_GBL_ALPHA:
+		{
+			struct mxcfb_gbl_alpha ga;
+
+			if (copy_from_user(&ga, (void *)arg, sizeof(ga))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			if (ipu_disp_set_global_alpha(mxc_fbi->ipu,
+						      mxc_fbi->ipu_ch,
+						      (bool)ga.enable,
+						      ga.alpha)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (ga.enable)
+				mxc_fbi->alpha_chan_en = false;
+
+			if (ga.enable)
+				dev_dbg(fbi->device,
+					"Set global alpha of %s to %d\n",
+					fbi->fix.id, ga.alpha);
+			break;
+		}
+	case MXCFB_SET_LOC_ALPHA:
+		{
+			struct mxcfb_loc_alpha la;
+
+			if (copy_from_user(&la, (void *)arg, sizeof(la))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			if (ipu_disp_set_global_alpha(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+						      !(bool)la.enable, 0)) {
+				retval = -EINVAL;
+				break;
+			}
+
+			if (la.enable && !la.alpha_in_pixel) {
+				struct fb_info *fbi_tmp;
+				ipu_channel_t ipu_ch;
+
+				mxc_fbi->alpha_chan_en = true;
+
+				if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
+					ipu_ch = MEM_BG_SYNC;
+				else if (mxc_fbi->ipu_ch == MEM_BG_SYNC)
+					ipu_ch = MEM_FG_SYNC;
+				else {
+					retval = -EINVAL;
+					break;
+				}
+
+				fbi_tmp = found_registered_fb(ipu_ch, mxc_fbi->ipu_id);
+				if (fbi_tmp)
+					((struct mxcfb_info *)(fbi_tmp->par))->alpha_chan_en = false;
+			} else
+				mxc_fbi->alpha_chan_en = false;
+
+			mxcfb_set_par(fbi);
+
+			la.alpha_phy_addr0 = mxc_fbi->alpha_phy_addr0;
+			la.alpha_phy_addr1 = mxc_fbi->alpha_phy_addr1;
+			if (copy_to_user((void *)arg, &la, sizeof(la))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			if (la.enable)
+				dev_dbg(fbi->device,
+					"Enable DP local alpha for %s\n",
+					fbi->fix.id);
+			break;
+		}
+	case MXCFB_SET_LOC_ALP_BUF:
+		{
+			unsigned long base;
+			uint32_t ipu_alp_ch_irq;
+
+			if (!(((mxc_fbi->ipu_ch == MEM_FG_SYNC) ||
+			     (mxc_fbi->ipu_ch == MEM_BG_SYNC)) &&
+			     (mxc_fbi->alpha_chan_en))) {
+				dev_err(fbi->device,
+					"Should use background or overlay "
+					"framebuffer to set the alpha buffer "
+					"number\n");
+				return -EINVAL;
+			}
+
+			if (get_user(base, argp))
+				return -EFAULT;
+
+			if (base != mxc_fbi->alpha_phy_addr0 &&
+			    base != mxc_fbi->alpha_phy_addr1) {
+				dev_err(fbi->device,
+					"Wrong alpha buffer physical address "
+					"%lu\n", base);
+				return -EINVAL;
+			}
+
+			if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
+				ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF;
+			else
+				ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
+
+			down(&mxc_fbi->alpha_flip_sem);
+
+			mxc_fbi->cur_ipu_alpha_buf =
+						!mxc_fbi->cur_ipu_alpha_buf;
+			if (ipu_update_channel_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+						      IPU_ALPHA_IN_BUFFER,
+						      mxc_fbi->
+							cur_ipu_alpha_buf,
+						      base) == 0) {
+				ipu_select_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+						  IPU_ALPHA_IN_BUFFER,
+						  mxc_fbi->cur_ipu_alpha_buf);
+				ipu_clear_irq(mxc_fbi->ipu, ipu_alp_ch_irq);
+				ipu_enable_irq(mxc_fbi->ipu, ipu_alp_ch_irq);
+			} else {
+				dev_err(fbi->device,
+					"Error updating %s SDC alpha buf %d "
+					"to address=0x%08lX\n",
+					fbi->fix.id,
+					mxc_fbi->cur_ipu_alpha_buf, base);
+			}
+			break;
+		}
+	case MXCFB_SET_CLR_KEY:
+		{
+			struct mxcfb_color_key key;
+			if (copy_from_user(&key, (void *)arg, sizeof(key))) {
+				retval = -EFAULT;
+				break;
+			}
+			retval = ipu_disp_set_color_key(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+							key.enable,
+							key.color_key);
+			dev_dbg(fbi->device, "Set color key to 0x%08X\n",
+				key.color_key);
+			break;
+		}
+	case MXCFB_SET_GAMMA:
+		{
+			struct mxcfb_gamma gamma;
+			if (copy_from_user(&gamma, (void *)arg, sizeof(gamma))) {
+				retval = -EFAULT;
+				break;
+			}
+			retval = ipu_disp_set_gamma_correction(mxc_fbi->ipu,
+							mxc_fbi->ipu_ch,
+							gamma.enable,
+							gamma.constk,
+							gamma.slopek);
+			break;
+		}
+	case MXCFB_WAIT_FOR_VSYNC:
+		{
+			if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
+				/* BG should poweron */
+				struct mxcfb_info *bg_mxcfbi = NULL;
+				struct fb_info *fbi_tmp;
+
+				fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
+				if (fbi_tmp)
+					bg_mxcfbi = ((struct mxcfb_info *)(fbi_tmp->par));
+
+				if (!bg_mxcfbi) {
+					retval = -EINVAL;
+					break;
+				}
+				if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK) {
+					retval = -EINVAL;
+					break;
+				}
+			}
+			if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK) {
+				retval = -EINVAL;
+				break;
+			}
+
+			init_completion(&mxc_fbi->vsync_complete);
+
+			ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+			mxc_fbi->wait4vsync = true;
+			ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+			retval = wait_for_completion_interruptible_timeout(
+				&mxc_fbi->vsync_complete, 1 * HZ);
+			if (retval == 0) {
+				dev_err(fbi->device,
+					"MXCFB_WAIT_FOR_VSYNC: timeout %d\n",
+					retval);
+				mxc_fbi->wait4vsync = false;
+				retval = -ETIME;
+			} else if (retval > 0) {
+				retval = 0;
+			}
+			break;
+		}
+	case FBIO_ALLOC:
+		{
+			int size;
+			struct mxcfb_alloc_list *mem;
+
+			mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+			if (mem == NULL)
+				return -ENOMEM;
+
+			if (get_user(size, argp))
+				return -EFAULT;
+
+			mem->size = PAGE_ALIGN(size);
+
+			mem->cpu_addr = dma_alloc_coherent(fbi->device, size,
+							   &mem->phy_addr,
+							   GFP_DMA);
+			if (mem->cpu_addr == NULL) {
+				kfree(mem);
+				return -ENOMEM;
+			}
+
+			list_add(&mem->list, &fb_alloc_list);
+
+			dev_dbg(fbi->device, "allocated %d bytes @ 0x%08X\n",
+				mem->size, mem->phy_addr);
+
+			if (put_user(mem->phy_addr, argp))
+				return -EFAULT;
+
+			break;
+		}
+	case FBIO_FREE:
+		{
+			unsigned long offset;
+			struct mxcfb_alloc_list *mem;
+
+			if (get_user(offset, argp))
+				return -EFAULT;
+
+			retval = -EINVAL;
+			list_for_each_entry(mem, &fb_alloc_list, list) {
+				if (mem->phy_addr == offset) {
+					list_del(&mem->list);
+					dma_free_coherent(fbi->device,
+							  mem->size,
+							  mem->cpu_addr,
+							  mem->phy_addr);
+					kfree(mem);
+					retval = 0;
+					break;
+				}
+			}
+
+			break;
+		}
+	case MXCFB_SET_OVERLAY_POS:
+		{
+			struct mxcfb_pos pos;
+			struct fb_info *bg_fbi = NULL;
+			struct mxcfb_info *bg_mxcfbi = NULL;
+
+			if (mxc_fbi->ipu_ch != MEM_FG_SYNC) {
+				dev_err(fbi->device, "Should use the overlay "
+					"framebuffer to set the position of "
+					"the overlay window\n");
+				retval = -EINVAL;
+				break;
+			}
+
+			if (copy_from_user(&pos, (void *)arg, sizeof(pos))) {
+				retval = -EFAULT;
+				break;
+			}
+
+			bg_fbi = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
+			if (bg_fbi)
+				bg_mxcfbi = ((struct mxcfb_info *)(bg_fbi->par));
+
+			if (bg_fbi == NULL) {
+				dev_err(fbi->device, "Cannot find the "
+					"background framebuffer\n");
+				retval = -ENOENT;
+				break;
+			}
+
+			/* if fb is unblank, check if the pos fit the display */
+			if (mxc_fbi->cur_blank == FB_BLANK_UNBLANK) {
+				if (fbi->var.xres + pos.x > bg_fbi->var.xres) {
+					if (bg_fbi->var.xres < fbi->var.xres)
+						pos.x = 0;
+					else
+						pos.x = bg_fbi->var.xres - fbi->var.xres;
+				}
+				if (fbi->var.yres + pos.y > bg_fbi->var.yres) {
+					if (bg_fbi->var.yres < fbi->var.yres)
+						pos.y = 0;
+					else
+						pos.y = bg_fbi->var.yres - fbi->var.yres;
+				}
+			}
+
+			retval = ipu_disp_set_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+							 pos.x, pos.y);
+
+			if (copy_to_user((void *)arg, &pos, sizeof(pos))) {
+				retval = -EFAULT;
+				break;
+			}
+			break;
+		}
+	case MXCFB_GET_FB_IPU_CHAN:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_ch, argp))
+				return -EFAULT;
+			break;
+		}
+	case MXCFB_GET_DIFMT:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_di_pix_fmt, argp))
+				return -EFAULT;
+			break;
+		}
+	case MXCFB_GET_FB_IPU_DI:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->ipu_di, argp))
+				return -EFAULT;
+			break;
+		}
+	case MXCFB_GET_FB_BLANK:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (put_user(mxc_fbi->cur_blank, argp))
+				return -EFAULT;
+			break;
+		}
+	case MXCFB_SET_DIFMT:
+		{
+			struct mxcfb_info *mxc_fbi =
+				(struct mxcfb_info *)fbi->par;
+
+			if (get_user(mxc_fbi->ipu_di_pix_fmt, argp))
+				return -EFAULT;
+
+			break;
+		}
+	default:
+		retval = -EINVAL;
+	}
+	return retval;
+}
+
+/*
+ * mxcfb_blank():
+ *      Blank the display.
+ */
+static int mxcfb_blank(int blank, struct fb_info *info)
+{
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
+
+	dev_dbg(info->device, "blank = %d\n", blank);
+
+	if (mxc_fbi->cur_blank == blank)
+		return 0;
+
+	mxc_fbi->next_blank = blank;
+
+	switch (blank) {
+	case FB_BLANK_POWERDOWN:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_NORMAL:
+		ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
+		if (mxc_fbi->ipu_di >= 0)
+			ipu_uninit_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di);
+		ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
+		break;
+	case FB_BLANK_UNBLANK:
+		mxcfb_set_par(info);
+		break;
+	}
+	mxc_fbi->cur_blank = blank;
+	return 0;
+}
+
+/*
+ * Pan or Wrap the Display
+ *
+ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
+ *
+ * @param               var     Variable screen buffer information
+ * @param               info    Framebuffer information pointer
+ */
+static int
+mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par,
+			  *mxc_graphic_fbi = NULL;
+	u_int y_bottom;
+	unsigned long base, active_alpha_phy_addr = 0;
+	bool loc_alpha_en = false;
+	int fb_stride;
+	int i;
+
+	if (info->var.yoffset == var->yoffset)
+		return 0;	/* No change, do nothing */
+
+	/* no pan display during fb blank */
+	if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
+		struct mxcfb_info *bg_mxcfbi = NULL;
+		struct fb_info *fbi_tmp;
+
+		fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
+		if (fbi_tmp)
+			bg_mxcfbi = ((struct mxcfb_info *)(fbi_tmp->par));
+		if (!bg_mxcfbi)
+			return -EINVAL;
+		if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK)
+			return -EINVAL;
+	}
+	if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK)
+		return -EINVAL;
+
+	y_bottom = var->yoffset;
+
+	if (!(var->vmode & FB_VMODE_YWRAP))
+		y_bottom += var->yres;
+
+	if (y_bottom > info->var.yres_virtual)
+		return -EINVAL;
+
+	switch (bpp_to_pixfmt(info)) {
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YVU420P:
+	case IPU_PIX_FMT_NV12:
+	case IPU_PIX_FMT_YUV422P:
+	case IPU_PIX_FMT_YVU422P:
+	case IPU_PIX_FMT_YUV420P:
+		fb_stride = info->var.xres_virtual;
+		break;
+	default:
+		fb_stride = info->fix.line_length;
+	}
+
+	base = (var->yoffset * fb_stride + var->xoffset);
+	base += info->fix.smem_start;
+
+	/* Check if DP local alpha is enabled and find the graphic fb */
+	if (mxc_fbi->ipu_ch == MEM_BG_SYNC || mxc_fbi->ipu_ch == MEM_FG_SYNC) {
+		for (i = 0; i < num_registered_fb; i++) {
+			char *bg_id = "DISP3 BG";
+			char *fg_id = "DISP3 FG";
+			char *idstr = registered_fb[i]->fix.id;
+			bg_id[4] += mxc_fbi->ipu_id;
+			fg_id[4] += mxc_fbi->ipu_id;
+			if ((strcmp(idstr, bg_id) == 0 ||
+			     strcmp(idstr, fg_id) == 0) &&
+			    ((struct mxcfb_info *)
+			      (registered_fb[i]->par))->alpha_chan_en) {
+				loc_alpha_en = true;
+				mxc_graphic_fbi = (struct mxcfb_info *)
+						(registered_fb[i]->par);
+				active_alpha_phy_addr =
+					mxc_fbi->cur_ipu_alpha_buf ?
+					mxc_graphic_fbi->alpha_phy_addr1 :
+					mxc_graphic_fbi->alpha_phy_addr0;
+				dev_dbg(info->device, "Updating SDC alpha "
+					"buf %d address=0x%08lX\n",
+					!mxc_fbi->cur_ipu_alpha_buf,
+					active_alpha_phy_addr);
+				break;
+			}
+		}
+	}
+
+	down(&mxc_fbi->flip_sem);
+
+	mxc_fbi->cur_ipu_buf = (++mxc_fbi->cur_ipu_buf) % 3;
+	mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
+
+	dev_dbg(info->device, "Updating SDC %s buf %d address=0x%08lX\n",
+		info->fix.id, mxc_fbi->cur_ipu_buf, base);
+
+	if (ipu_update_channel_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+				      mxc_fbi->cur_ipu_buf, base) == 0) {
+		/* Update the DP local alpha buffer only for graphic plane */
+		if (loc_alpha_en && mxc_graphic_fbi == mxc_fbi &&
+		    ipu_update_channel_buffer(mxc_graphic_fbi->ipu, mxc_graphic_fbi->ipu_ch,
+					      IPU_ALPHA_IN_BUFFER,
+					      mxc_fbi->cur_ipu_alpha_buf,
+					      active_alpha_phy_addr) == 0) {
+			ipu_select_buffer(mxc_graphic_fbi->ipu, mxc_graphic_fbi->ipu_ch,
+					  IPU_ALPHA_IN_BUFFER,
+					  mxc_fbi->cur_ipu_alpha_buf);
+		}
+
+		/* update u/v offset */
+		ipu_update_channel_offset(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+				IPU_INPUT_BUFFER,
+				bpp_to_pixfmt(info),
+				info->var.xres_virtual,
+				info->var.yres_virtual,
+				info->var.xres_virtual,
+				0, 0,
+				var->yoffset,
+				var->xoffset);
+
+		ipu_select_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+				  mxc_fbi->cur_ipu_buf);
+		ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+		ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+	} else {
+		dev_err(info->device,
+			"Error updating SDC buf %d to address=0x%08lX, "
+			"current buf %d, buf0 ready %d, buf1 ready %d, "
+			"buf2 ready %d\n", mxc_fbi->cur_ipu_buf, base,
+			ipu_get_cur_buffer_idx(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+					       IPU_INPUT_BUFFER),
+			ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+					       IPU_INPUT_BUFFER, 0),
+			ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+					       IPU_INPUT_BUFFER, 1),
+			ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
+					       IPU_INPUT_BUFFER, 2));
+		mxc_fbi->cur_ipu_buf = (++mxc_fbi->cur_ipu_buf) % 3;
+		mxc_fbi->cur_ipu_buf = (++mxc_fbi->cur_ipu_buf) % 3;
+		mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
+		ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+		ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
+		return -EBUSY;
+	}
+
+	dev_dbg(info->device, "Update complete\n");
+
+	info->var.yoffset = var->yoffset;
+
+	return 0;
+}
+
+/*
+ * Function to handle custom mmap for MXC framebuffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @param       vma     Pointer to vm_area_struct
+ */
+static int mxcfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
+{
+	bool found = false;
+	u32 len;
+	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+	struct mxcfb_alloc_list *mem;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	if (offset < fbi->fix.smem_len) {
+		/* mapping framebuffer memory */
+		len = fbi->fix.smem_len - offset;
+		vma->vm_pgoff = (fbi->fix.smem_start + offset) >> PAGE_SHIFT;
+	} else if ((vma->vm_pgoff ==
+			(mxc_fbi->alpha_phy_addr0 >> PAGE_SHIFT)) ||
+		   (vma->vm_pgoff ==
+			(mxc_fbi->alpha_phy_addr1 >> PAGE_SHIFT))) {
+		len = mxc_fbi->alpha_mem_len;
+	} else {
+		list_for_each_entry(mem, &fb_alloc_list, list) {
+			if (offset == mem->phy_addr) {
+				found = true;
+				len = mem->size;
+				break;
+			}
+		}
+		if (!found)
+			return -EINVAL;
+	}
+
+	len = PAGE_ALIGN(len);
+	if (vma->vm_end - vma->vm_start > len)
+		return -EINVAL;
+
+	/* make buffers bufferable */
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+	vma->vm_flags |= VM_IO | VM_RESERVED;
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+			    vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
+		dev_dbg(fbi->device, "mmap remap_pfn_range failed\n");
+		return -ENOBUFS;
+	}
+
+	return 0;
+}
+
+/*!
+ * This structure contains the pointers to the control functions that are
+ * invoked by the core framebuffer driver to perform operations like
+ * blitting, rectangle filling, copy regions and cursor definition.
+ */
+static struct fb_ops mxcfb_ops = {
+	.owner = THIS_MODULE,
+	.fb_set_par = mxcfb_set_par,
+	.fb_check_var = mxcfb_check_var,
+	.fb_setcolreg = mxcfb_setcolreg,
+	.fb_pan_display = mxcfb_pan_display,
+	.fb_ioctl = mxcfb_ioctl,
+	.fb_mmap = mxcfb_mmap,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+	.fb_blank = mxcfb_blank,
+};
+
+static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id)
+{
+	struct fb_info *fbi = dev_id;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	if (mxc_fbi->wait4vsync) {
+		complete(&mxc_fbi->vsync_complete);
+		ipu_disable_irq(mxc_fbi->ipu, irq);
+		mxc_fbi->wait4vsync = false;
+	} else {
+		up(&mxc_fbi->flip_sem);
+		ipu_disable_irq(mxc_fbi->ipu, irq);
+	}
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxcfb_alpha_irq_handler(int irq, void *dev_id)
+{
+	struct fb_info *fbi = dev_id;
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	up(&mxc_fbi->alpha_flip_sem);
+	ipu_disable_irq(mxc_fbi->ipu, irq);
+	return IRQ_HANDLED;
+}
+
+/*
+ * Suspends the framebuffer and blanks the screen. Power management support
+ */
+static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+	int saved_blank;
+#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY
+	void *fbmem;
+#endif
+
+	if (mxc_fbi->ovfbi) {
+		struct mxcfb_info *mxc_fbi_fg =
+			(struct mxcfb_info *)mxc_fbi->ovfbi->par;
+
+		console_lock();
+		fb_set_suspend(mxc_fbi->ovfbi, 1);
+		saved_blank = mxc_fbi_fg->cur_blank;
+		mxcfb_blank(FB_BLANK_POWERDOWN, mxc_fbi->ovfbi);
+		mxc_fbi_fg->next_blank = saved_blank;
+		console_unlock();
+	}
+
+	console_lock();
+	fb_set_suspend(fbi, 1);
+	saved_blank = mxc_fbi->cur_blank;
+	mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
+	mxc_fbi->next_blank = saved_blank;
+	console_unlock();
+
+	return 0;
+}
+
+/*
+ * Resumes the framebuffer and unblanks the screen. Power management support
+ */
+static int mxcfb_resume(struct platform_device *pdev)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	console_lock();
+	mxcfb_blank(mxc_fbi->next_blank, fbi);
+	fb_set_suspend(fbi, 0);
+	console_unlock();
+
+	if (mxc_fbi->ovfbi) {
+		struct mxcfb_info *mxc_fbi_fg =
+			(struct mxcfb_info *)mxc_fbi->ovfbi->par;
+		console_lock();
+		mxcfb_blank(mxc_fbi_fg->next_blank, mxc_fbi->ovfbi);
+		fb_set_suspend(mxc_fbi->ovfbi, 0);
+		console_unlock();
+	}
+
+	return 0;
+}
+
+/*
+ * Main framebuffer functions
+ */
+
+/*!
+ * Allocates the DRAM memory for the frame buffer.      This buffer is remapped
+ * into a non-cached, non-buffered, memory region to allow palette and pixel
+ * writes to occur without flushing the cache.  Once this area is remapped,
+ * all virtual memory access to the video memory should occur at the new region.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxcfb_map_video_memory(struct fb_info *fbi)
+{
+	if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
+		fbi->fix.smem_len = fbi->var.yres_virtual *
+				    fbi->fix.line_length;
+
+	fbi->screen_base = dma_alloc_writecombine(fbi->device,
+				fbi->fix.smem_len,
+				(dma_addr_t *)&fbi->fix.smem_start,
+				GFP_DMA);
+	if (fbi->screen_base == 0) {
+		dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
+		fbi->fix.smem_len = 0;
+		fbi->fix.smem_start = 0;
+		return -EBUSY;
+	}
+
+	dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
+		(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+
+	fbi->screen_size = fbi->fix.smem_len;
+
+	/* Clear the screen */
+	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+
+	return 0;
+}
+
+/*!
+ * De-allocates the DRAM memory for the frame buffer.
+ *
+ * @param       fbi     framebuffer information pointer
+ *
+ * @return      Error code indicating success or failure
+ */
+static int mxcfb_unmap_video_memory(struct fb_info *fbi)
+{
+	dma_free_writecombine(fbi->device, fbi->fix.smem_len,
+			      fbi->screen_base, fbi->fix.smem_start);
+	fbi->screen_base = 0;
+	fbi->fix.smem_start = 0;
+	fbi->fix.smem_len = 0;
+	return 0;
+}
+
+/*!
+ * Initializes the framebuffer information pointer. After allocating
+ * sufficient memory for the framebuffer structure, the fields are
+ * filled with custom information passed in from the configurable
+ * structures.  This includes information such as bits per pixel,
+ * color maps, screen width/height and RGBA offsets.
+ *
+ * @return      Framebuffer structure initialized with our information
+ */
+static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops)
+{
+	struct fb_info *fbi;
+	struct mxcfb_info *mxcfbi;
+
+	/*
+	 * Allocate sufficient memory for the fb structure
+	 */
+	fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev);
+	if (!fbi)
+		return NULL;
+
+	mxcfbi = (struct mxcfb_info *)fbi->par;
+
+	fbi->var.activate = FB_ACTIVATE_NOW;
+
+	fbi->fbops = ops;
+	fbi->flags = FBINFO_FLAG_DEFAULT;
+	fbi->pseudo_palette = mxcfbi->pseudo_palette;
+
+	/*
+	 * Allocate colormap
+	 */
+	fb_alloc_cmap(&fbi->cmap, 16, 0);
+
+	return fbi;
+}
+
+static ssize_t show_disp_chan(struct device *dev,
+			      struct device_attribute *attr, char *buf)
+{
+	struct fb_info *info = dev_get_drvdata(dev);
+	struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
+
+	if (mxcfbi->ipu_ch == MEM_BG_SYNC)
+		return sprintf(buf, "2-layer-fb-bg\n");
+	else if (mxcfbi->ipu_ch == MEM_FG_SYNC)
+		return sprintf(buf, "2-layer-fb-fg\n");
+	else if (mxcfbi->ipu_ch == MEM_DC_SYNC)
+		return sprintf(buf, "1-layer-fb\n");
+	else
+		return sprintf(buf, "err: no display chan\n");
+}
+
+static ssize_t swap_disp_chan(struct device *dev,
+			      struct device_attribute *attr,
+			      const char *buf, size_t count)
+{
+	struct fb_info *info = dev_get_drvdata(dev);
+	struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
+	struct mxcfb_info *fg_mxcfbi = NULL;
+
+	console_lock();
+	/* swap only happen between DP-BG and DC, while DP-FG disable */
+	if (((mxcfbi->ipu_ch == MEM_BG_SYNC) &&
+	     (strstr(buf, "1-layer-fb") != NULL)) ||
+	    ((mxcfbi->ipu_ch == MEM_DC_SYNC) &&
+	     (strstr(buf, "2-layer-fb-bg") != NULL))) {
+		struct fb_info *fbi_fg;
+
+		fbi_fg = found_registered_fb(MEM_FG_SYNC, mxcfbi->ipu_id);
+		if (fbi_fg)
+			fg_mxcfbi = (struct mxcfb_info *)fbi_fg->par;
+
+		if (!fg_mxcfbi ||
+			fg_mxcfbi->cur_blank == FB_BLANK_UNBLANK) {
+			dev_err(dev,
+				"Can not switch while fb2(fb-fg) is on.\n");
+			console_unlock();
+			return count;
+		}
+
+		if (swap_channels(info) < 0)
+			dev_err(dev, "Swap display channel failed.\n");
+	}
+
+	console_unlock();
+	return count;
+}
+DEVICE_ATTR(fsl_disp_property, 644, show_disp_chan, swap_disp_chan);
+
+static int mxcfb_dispdrv_init(struct platform_device *pdev,
+		struct fb_info *fbi)
+{
+	struct ipuv3_fb_platform_data *plat_data = pdev->dev.platform_data;
+	struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
+	struct mxc_dispdrv_setting setting;
+	char disp_dev[32], *default_dev = "lcd";
+	int ret = 0;
+
+	setting.if_fmt = plat_data->interface_pix_fmt;
+	setting.dft_mode_str = plat_data->mode_str;
+	setting.default_bpp = plat_data->default_bpp;
+	if (!setting.default_bpp)
+		setting.default_bpp = 16;
+	setting.fbi = fbi;
+	if (!strlen(plat_data->disp_dev)) {
+		memcpy(disp_dev, default_dev, strlen(default_dev));
+		disp_dev[strlen(default_dev)] = '\0';
+	} else {
+		memcpy(disp_dev, plat_data->disp_dev,
+				strlen(plat_data->disp_dev));
+		disp_dev[strlen(plat_data->disp_dev)] = '\0';
+	}
+
+	dev_info(&pdev->dev, "register mxc display driver %s\n", disp_dev);
+
+	ret = mxc_dispdrv_init(disp_dev, &setting);
+	if (ret < 0) {
+		dev_err(&pdev->dev,
+			"register mxc display driver failed with %d\n", ret);
+	} else {
+		/* fix-up  */
+		mxcfbi->ipu_di_pix_fmt = setting.if_fmt;
+		mxcfbi->default_bpp = setting.default_bpp;
+
+		/* setting */
+		mxcfbi->ipu_id = setting.dev_id;
+		mxcfbi->ipu_di = setting.disp_id;
+	}
+
+	return ret;
+}
+
+/*
+ * Parse user specified options (`video=trident:')
+ * example:
+ * 	video=mxcfb0:dev=lcd,800x480M-16@55,if=RGB565,bpp=16,noaccel
+ */
+static int mxcfb_option_setup(struct platform_device *pdev)
+{
+	struct ipuv3_fb_platform_data *pdata = pdev->dev.platform_data;
+	char *options, *opt, *fb_mode_str = NULL;
+	char name[] = "mxcfb0";
+
+	name[5] += pdev->id;
+	fb_get_options(name, &options);
+
+	if (!options || !*options)
+		return 0;
+
+	while ((opt = strsep(&options, ",")) != NULL) {
+		if (!*opt)
+			continue;
+
+		if (!strncmp(opt, "dev=", 4)) {
+			memcpy(pdata->disp_dev, opt + 4, strlen(opt) - 4);
+			pdata->disp_dev[strlen(opt) - 4] = '\0';
+			continue;
+		}
+		if (!strncmp(opt, "if=", 3)) {
+			if (!strncmp(opt+3, "RGB24", 5)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_RGB24;
+				continue;
+			} else if (!strncmp(opt+6, "BGR24", 5)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_BGR24;
+				continue;
+			}
+			if (!strncmp(opt+3, "GBR24", 5)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_GBR24;
+				continue;
+			}
+			if (!strncmp(opt+3, "RGB565", 6)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_RGB565;
+				continue;
+			}
+			if (!strncmp(opt+3, "RGB666", 6)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_RGB666;
+				continue;
+			}
+			if (!strncmp(opt+3, "YUV444", 6)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_YUV444;
+				continue;
+			}
+			if (!strncmp(opt+3, "LVDS666", 7)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_LVDS666;
+				continue;
+			}
+			if (!strncmp(opt+3, "YUYV16", 6)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_YUYV;
+				continue;
+			}
+			if (!strncmp(opt+3, "UYVY16", 6)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_UYVY;
+				continue;
+			}
+			if (!strncmp(opt+3, "YVYU16", 6)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_YVYU;
+				continue;
+			}
+			if (!strncmp(opt+3, "VYUY16", 6)) {
+				pdata->interface_pix_fmt = IPU_PIX_FMT_VYUY;
+				continue;
+			}
+		}
+		if (!strncmp(opt, "int_clk", 7)) {
+			pdata->int_clk = true;
+			continue;
+		}
+		if (!strncmp(opt, "bpp=", 4))
+			pdata->default_bpp =
+				simple_strtoul(opt + 4, NULL, 0);
+		else
+			fb_mode_str = opt;
+	}
+
+	if (fb_mode_str)
+		pdata->mode_str = fb_mode_str;
+
+	return 0;
+}
+
+static int mxcfb_register(struct fb_info *fbi)
+{
+	struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
+	struct fb_videomode m;
+	int ret = 0;
+	char bg0_id[] = "DISP3 BG";
+	char bg1_id[] = "DISP3 BG - DI1";
+	char fg_id[] = "DISP3 FG";
+
+	if (mxcfbi->ipu_di == 0) {
+		bg0_id[4] += mxcfbi->ipu_id;
+		strcpy(fbi->fix.id, bg0_id);
+	} else if (mxcfbi->ipu_di == 1) {
+		bg1_id[4] += mxcfbi->ipu_id;
+		strcpy(fbi->fix.id, bg1_id);
+	} else { /* Overlay */
+		fg_id[4] += mxcfbi->ipu_id;
+		strcpy(fbi->fix.id, fg_id);
+	}
+
+	if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq, mxcfb_irq_handler, 0,
+				MXCFB_NAME, fbi) != 0) {
+		dev_err(fbi->device, "Error registering BG irq handler.\n");
+		ret = -EBUSY;
+		goto err0;
+	}
+	ipu_disable_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq);
+
+	if (mxcfbi->ipu_alp_ch_irq != -1)
+		if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq,
+					mxcfb_alpha_irq_handler, 0,
+					MXCFB_NAME, fbi) != 0) {
+			dev_err(fbi->device, "Error registering alpha irq "
+					"handler.\n");
+			ret = -EBUSY;
+			goto err1;
+		}
+
+	mxcfb_check_var(&fbi->var, fbi);
+
+	mxcfb_set_fix(fbi);
+
+	/*added first mode to fbi modelist*/
+	if (!fbi->modelist.next || !fbi->modelist.prev)
+		INIT_LIST_HEAD(&fbi->modelist);
+	fb_var_to_videomode(&m, &fbi->var);
+	fb_add_videomode(&m, &fbi->modelist);
+
+	fbi->var.activate |= FB_ACTIVATE_FORCE;
+	console_lock();
+	fbi->flags |= FBINFO_MISC_USEREVENT;
+	ret = fb_set_var(fbi, &fbi->var);
+	fbi->flags &= ~FBINFO_MISC_USEREVENT;
+	console_unlock();
+	if (ret < 0)
+		goto err2;
+
+	if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
+		console_lock();
+		fb_blank(fbi, FB_BLANK_UNBLANK);
+		console_unlock();
+	}
+
+	ret = register_framebuffer(fbi);
+	if (ret < 0)
+		goto err2;
+
+	return ret;
+err2:
+	if (mxcfbi->ipu_alp_ch_irq != -1)
+		ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq, fbi);
+err1:
+	ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq, fbi);
+err0:
+	return ret;
+}
+
+static void mxcfb_unregister(struct fb_info *fbi)
+{
+	struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
+
+	if (mxcfbi->ipu_alp_ch_irq != -1)
+		ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq, fbi);
+	if (mxcfbi->ipu_ch_irq)
+		ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq, fbi);
+
+	unregister_framebuffer(fbi);
+}
+
+static int mxcfb_setup_overlay(struct platform_device *pdev,
+		struct fb_info *fbi_bg)
+{
+	struct fb_info *ovfbi;
+	struct mxcfb_info *mxcfbi_bg = (struct mxcfb_info *)fbi_bg->par;
+	struct mxcfb_info *mxcfbi_fg;
+	int ret = 0;
+
+	ovfbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
+	if (!ovfbi) {
+		ret = -ENOMEM;
+		goto init_ovfbinfo_failed;
+	}
+	mxcfbi_fg = (struct mxcfb_info *)ovfbi->par;
+
+	mxcfbi_fg->ipu = ipu_get_soc(mxcfbi_bg->ipu_id);
+	if (IS_ERR(mxcfbi_fg->ipu)) {
+		ret = -ENODEV;
+		goto get_ipu_failed;
+	}
+	mxcfbi_fg->ipu_id = mxcfbi_bg->ipu_id;
+	mxcfbi_fg->ipu_ch_irq = IPU_IRQ_FG_SYNC_EOF;
+	mxcfbi_fg->ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF;
+	mxcfbi_fg->ipu_ch = MEM_FG_SYNC;
+	mxcfbi_fg->ipu_di = -1;
+	mxcfbi_fg->ipu_di_pix_fmt = mxcfbi_bg->ipu_di_pix_fmt;
+	mxcfbi_fg->overlay = true;
+	mxcfbi_fg->cur_blank = mxcfbi_fg->next_blank = FB_BLANK_POWERDOWN;
+
+	/* Need dummy values until real panel is configured */
+	ovfbi->var.xres = 240;
+	ovfbi->var.yres = 320;
+
+	ret = mxcfb_register(ovfbi);
+	if (ret < 0)
+		goto register_ov_failed;
+
+	mxcfbi_bg->ovfbi = ovfbi;
+
+	return ret;
+
+register_ov_failed:
+get_ipu_failed:
+	fb_dealloc_cmap(&ovfbi->cmap);
+	framebuffer_release(ovfbi);
+init_ovfbinfo_failed:
+	return ret;
+}
+
+static void mxcfb_unsetup_overlay(struct fb_info *fbi_bg)
+{
+	struct mxcfb_info *mxcfbi_bg = (struct mxcfb_info *)fbi_bg->par;
+	struct fb_info *ovfbi = mxcfbi_bg->ovfbi;
+
+	mxcfb_unregister(ovfbi);
+
+	if (&ovfbi->cmap)
+		fb_dealloc_cmap(&ovfbi->cmap);
+	framebuffer_release(ovfbi);
+}
+
+static bool ipu_usage[2][2];
+static int ipu_test_set_usage(int ipu, int di)
+{
+	if (ipu_usage[ipu][di])
+		return -EBUSY;
+	else
+		ipu_usage[ipu][di] = true;
+	return 0;
+}
+
+static void ipu_clear_usage(int ipu, int di)
+{
+	ipu_usage[ipu][di] = false;
+}
+
+/*!
+ * Probe routine for the framebuffer driver. It is called during the
+ * driver binding process.      The following functions are performed in
+ * this routine: Framebuffer initialization, Memory allocation and
+ * mapping, Framebuffer registration, IPU initialization.
+ *
+ * @return      Appropriate error code to the kernel common code
+ */
+static int mxcfb_probe(struct platform_device *pdev)
+{
+	struct ipuv3_fb_platform_data *plat_data = pdev->dev.platform_data;
+	struct fb_info *fbi;
+	struct mxcfb_info *mxcfbi;
+	struct resource *res;
+	int ret = 0;
+
+	/*
+	 * Initialize FB structures
+	 */
+	fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
+	if (!fbi) {
+		ret = -ENOMEM;
+		goto init_fbinfo_failed;
+	}
+
+	mxcfb_option_setup(pdev);
+
+	mxcfbi = (struct mxcfb_info *)fbi->par;
+	mxcfbi->ipu_int_clk = plat_data->int_clk;
+	ret = mxcfb_dispdrv_init(pdev, fbi);
+	if (ret < 0)
+		goto init_dispdrv_failed;
+
+	ret = ipu_test_set_usage(mxcfbi->ipu_id, mxcfbi->ipu_di);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "ipu%d-di%d already in use\n",
+				mxcfbi->ipu_id, mxcfbi->ipu_di);
+		goto ipu_in_busy;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res && res->end) {
+		fbi->fix.smem_len = res->end - res->start + 1;
+		fbi->fix.smem_start = res->start;
+		fbi->screen_base = ioremap(fbi->fix.smem_start, fbi->fix.smem_len);
+	}
+
+	mxcfbi->ipu = ipu_get_soc(mxcfbi->ipu_id);
+	if (IS_ERR(mxcfbi->ipu)) {
+		ret = -ENODEV;
+		goto get_ipu_failed;
+	}
+
+	/* first user uses DP with alpha feature */
+	if (!g_dp_in_use[mxcfbi->ipu_id]) {
+		mxcfbi->ipu_ch_irq = IPU_IRQ_BG_SYNC_EOF;
+		mxcfbi->ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
+		mxcfbi->ipu_ch = MEM_BG_SYNC;
+		mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK;
+
+		ipu_disp_set_global_alpha(mxcfbi->ipu, mxcfbi->ipu_ch, true, 0x80);
+		ipu_disp_set_color_key(mxcfbi->ipu, mxcfbi->ipu_ch, false, 0);
+
+		ret = mxcfb_register(fbi);
+		if (ret < 0)
+			goto mxcfb_register_failed;
+
+		ret = mxcfb_setup_overlay(pdev, fbi);
+		if (ret < 0) {
+			mxcfb_unregister(fbi);
+			goto mxcfb_setupoverlay_failed;
+		}
+
+		g_dp_in_use[mxcfbi->ipu_id] = true;
+	} else {
+		mxcfbi->ipu_ch_irq = IPU_IRQ_DC_SYNC_EOF;
+		mxcfbi->ipu_alp_ch_irq = -1;
+		mxcfbi->ipu_ch = MEM_DC_SYNC;
+		mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
+
+		ret = mxcfb_register(fbi);
+		if (ret < 0)
+			goto mxcfb_register_failed;
+	}
+
+	platform_set_drvdata(pdev, fbi);
+
+	ret = device_create_file(fbi->dev, &dev_attr_fsl_disp_property);
+	if (ret)
+		dev_err(&pdev->dev, "Error %d on creating file\n", ret);
+
+#ifdef CONFIG_LOGO
+	fb_prepare_logo(fbi, 0);
+	fb_show_logo(fbi, 0);
+#endif
+
+	return 0;
+
+mxcfb_setupoverlay_failed:
+mxcfb_register_failed:
+get_ipu_failed:
+	ipu_clear_usage(mxcfbi->ipu_id, mxcfbi->ipu_di);
+ipu_in_busy:
+init_dispdrv_failed:
+	fb_dealloc_cmap(&fbi->cmap);
+	framebuffer_release(fbi);
+init_fbinfo_failed:
+	return ret;
+}
+
+static int mxcfb_remove(struct platform_device *pdev)
+{
+	struct fb_info *fbi = platform_get_drvdata(pdev);
+	struct mxcfb_info *mxc_fbi = fbi->par;
+
+	if (!fbi)
+		return 0;
+
+	mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
+	mxcfb_unregister(fbi);
+	mxcfb_unmap_video_memory(fbi);
+
+	if (mxc_fbi->ovfbi) {
+		mxcfb_blank(FB_BLANK_POWERDOWN, mxc_fbi->ovfbi);
+		mxcfb_unsetup_overlay(fbi);
+		mxcfb_unmap_video_memory(mxc_fbi->ovfbi);
+	}
+
+	ipu_clear_usage(mxc_fbi->ipu_id, mxc_fbi->ipu_di);
+	if (&fbi->cmap)
+		fb_dealloc_cmap(&fbi->cmap);
+	framebuffer_release(fbi);
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcfb_driver = {
+	.driver = {
+		   .name = MXCFB_NAME,
+		   },
+	.probe = mxcfb_probe,
+	.remove = mxcfb_remove,
+	.suspend = mxcfb_suspend,
+	.resume = mxcfb_resume,
+};
+
+/*!
+ * Main entry function for the framebuffer. The function registers the power
+ * management callback functions with the kernel and also registers the MXCFB
+ * callback functions with the core Linux framebuffer driver \b fbmem.c
+ *
+ * @return      Error code indicating success or failure
+ */
+int __init mxcfb_init(void)
+{
+	return platform_driver_register(&mxcfb_driver);
+}
+
+void mxcfb_exit(void)
+{
+	platform_driver_unregister(&mxcfb_driver);
+}
+
+module_init(mxcfb_init);
+module_exit(mxcfb_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC framebuffer driver");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("fb");
diff --git a/drivers/video/mxc/mxc_lcdif.c b/drivers/video/mxc/mxc_lcdif.c
new file mode 100644
index 00000000000..d9d7fa306a8
--- /dev/null
+++ b/drivers/video/mxc/mxc_lcdif.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mxcfb.h>
+#include <linux/fsl_devices.h>
+#include "mxc_dispdrv.h"
+
+struct mxc_lcdif_data {
+	struct platform_device *pdev;
+	struct mxc_dispdrv_entry *disp_lcdif;
+};
+
+#define DISPDRV_LCD	"lcd"
+
+static struct fb_videomode lcdif_modedb[] = {
+	{
+	/* 800x480 @ 57 Hz , pixel clk @ 27MHz */
+	"CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
+	FB_SYNC_CLK_LAT_FALL,
+	FB_VMODE_NONINTERLACED,
+	0,},
+	{
+	/* 800x480 @ 60 Hz , pixel clk @ 32MHz */
+	"SEIKO-WVGA", 60, 800, 480, 29850, 89, 164, 23, 10, 10, 10,
+	FB_SYNC_CLK_LAT_FALL,
+	FB_VMODE_NONINTERLACED,
+	0,},
+};
+static int lcdif_modedb_sz = ARRAY_SIZE(lcdif_modedb);
+
+static int lcdif_init(struct mxc_dispdrv_entry *disp)
+{
+	int ret, i;
+	struct mxc_lcdif_data *lcdif = mxc_dispdrv_getdata(disp);
+	struct mxc_dispdrv_setting *setting = mxc_dispdrv_getsetting(disp);
+	struct fsl_mxc_lcd_platform_data *plat_data
+			= lcdif->pdev->dev.platform_data;
+	struct fb_videomode *modedb = lcdif_modedb;
+	int modedb_sz = lcdif_modedb_sz;
+
+	/* use platform defined ipu/di */
+	setting->dev_id = plat_data->ipu_id;
+	setting->disp_id = plat_data->disp_id;
+
+	ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
+				modedb, modedb_sz, NULL, setting->default_bpp);
+	if (!ret) {
+		fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
+		setting->if_fmt = plat_data->default_ifmt;
+	}
+
+	INIT_LIST_HEAD(&setting->fbi->modelist);
+	for (i = 0; i < modedb_sz; i++) {
+		struct fb_videomode m;
+		fb_var_to_videomode(&m, &setting->fbi->var);
+		if (fb_mode_is_equal(&m, &modedb[i])) {
+			fb_add_videomode(&modedb[i],
+					&setting->fbi->modelist);
+			break;
+		}
+	}
+
+	return ret;
+}
+
+void lcdif_deinit(struct mxc_dispdrv_entry *disp)
+{
+	/*TODO*/
+}
+
+static struct mxc_dispdrv_driver lcdif_drv = {
+	.name 	= DISPDRV_LCD,
+	.init 	= lcdif_init,
+	.deinit	= lcdif_deinit,
+};
+
+static int mxc_lcdif_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct mxc_lcdif_data *lcdif;
+
+	lcdif = kzalloc(sizeof(struct mxc_lcdif_data), GFP_KERNEL);
+	if (!lcdif) {
+		ret = -ENOMEM;
+		goto alloc_failed;
+	}
+
+	lcdif->pdev = pdev;
+	lcdif->disp_lcdif = mxc_dispdrv_register(&lcdif_drv);
+	mxc_dispdrv_setdata(lcdif->disp_lcdif, lcdif);
+
+	dev_set_drvdata(&pdev->dev, lcdif);
+
+alloc_failed:
+	return ret;
+}
+
+static int mxc_lcdif_remove(struct platform_device *pdev)
+{
+	struct mxc_lcdif_data *lcdif = dev_get_drvdata(&pdev->dev);
+
+	mxc_dispdrv_unregister(lcdif->disp_lcdif);
+	kfree(lcdif);
+	return 0;
+}
+
+static struct platform_driver mxc_lcdif_driver = {
+	.driver = {
+		   .name = "mxc_lcdif",
+		   },
+	.probe = mxc_lcdif_probe,
+	.remove = mxc_lcdif_remove,
+};
+
+static int __init mxc_lcdif_init(void)
+{
+	return platform_driver_register(&mxc_lcdif_driver);
+}
+
+static void __exit mxc_lcdif_exit(void)
+{
+	platform_driver_unregister(&mxc_lcdif_driver);
+}
+
+module_init(mxc_lcdif_init);
+module_exit(mxc_lcdif_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX ipuv3 LCD extern port driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxcfb_sii902x.c b/drivers/video/mxc/mxcfb_sii902x.c
new file mode 100644
index 00000000000..17ce8fca68b
--- /dev/null
+++ b/drivers/video/mxc/mxcfb_sii902x.c
@@ -0,0 +1,1307 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxcfb_sii902x.c
+ *
+ * @brief MXC Frame buffer driver for SII902x
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/i2c.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <linux/fsl_devices.h>
+#include <linux/interrupt.h>
+#include <linux/uaccess.h>
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include "mxc_edid.h"
+#include "mxc_dispdrv.h"
+
+#define DISPDRV_SII	"hdmi"
+
+#define TPI_PIX_CLK_LSB                 (0x00)
+#define TPI_PIX_CLK_MSB                 (0x01)
+#define TPI_VERT_FREQ_LSB               (0x02)
+#define TPI_VERT_FREQ_MSB               (0x03)
+#define TPI_TOTAL_PIX_LSB               (0x04)
+#define TPI_TOTAL_PIX_MSB         	(0x05)
+#define TPI_TOTAL_LINES_LSB		(0x06)
+#define TPI_TOTAL_LINES_MSB		(0x07)
+#define TPI_PIX_REPETITION              (0x08)
+#define TPI_INPUT_FORMAT_REG            (0x09)
+#define TPI_OUTPUT_FORMAT_REG           (0x0A)
+
+#define TPI_AVI_BYTE_0                  (0x0C)
+#define TPI_AVI_BYTE_1                  (0x0D)
+#define TPI_AVI_BYTE_2                  (0x0E)
+#define TPI_AVI_BYTE_3                  (0x0F)
+#define TPI_AVI_BYTE_4                  (0x10)
+#define TPI_AVI_BYTE_5                  (0x11)
+
+#define TPI_END_TOP_BAR_LSB             (0x12)
+#define TPI_END_TOP_BAR_MSB             (0x13)
+
+#define TPI_START_BTM_BAR_LSB           (0x14)
+#define TPI_START_BTM_BAR_MSB           (0x15)
+
+#define TPI_END_LEFT_BAR_LSB            (0x16)
+#define TPI_END_LEFT_BAR_MSB            (0x17)
+
+#define TPI_END_RIGHT_BAR_LSB           (0x18)
+#define TPI_END_RIGHT_BAR_MSB           (0x19)
+
+#define TPI_SYSTEM_CONTROL_DATA_REG	(0x1A)
+#define TPI_DEVICE_ID			(0x1B)
+#define TPI_DEVICE_REV_ID		(0x1C)
+#define TPI_RESERVED2			(0x1D)
+#define TPI_DEVICE_POWER_STATE_CTRL_REG	(0x1E)
+
+#define TPI_I2S_EN                      (0x1F)
+#define TPI_I2S_IN_CFG                  (0x20)
+#define TPI_I2S_CHST_0                  (0x21)
+#define TPI_I2S_CHST_1                  (0x22)
+#define TPI_I2S_CHST_2                  (0x23)
+#define TPI_I2S_CHST_3                  (0x24)
+#define TPI_I2S_CHST_4                  (0x25)
+
+#define TPI_AUDIO_HANDLING              (0x25)
+#define TPI_AUDIO_INTERFACE_REG         (0x26)
+#define TPI_AUDIO_SAMPLE_CTRL           (0x27)
+
+#define TPI_INTERRUPT_ENABLE_REG	(0x3C)
+#define TPI_INTERRUPT_STATUS_REG	(0x3D)
+
+#define TPI_INTERNAL_PAGE_REG		0xBC
+#define TPI_INDEXED_OFFSET_REG		0xBD
+#define TPI_INDEXED_VALUE_REG		0xBE
+
+#define MISC_INFO_FRAMES_CTRL           (0xBF)
+#define MISC_INFO_FRAMES_TYPE           (0xC0)
+#define EN_AND_RPT_AUDIO                0xC2
+#define DISABLE_AUDIO                   0x02
+
+#define TPI_ENABLE			(0xC7)
+
+#define INDEXED_PAGE_0		0x01
+#define INDEXED_PAGE_1		0x02
+#define INDEXED_PAGE_2		0x03
+
+#define HOT_PLUG_EVENT          0x01
+#define RX_SENSE_EVENT          0x02
+#define HOT_PLUG_STATE          0x04
+#define RX_SENSE_STATE          0x08
+
+#define OUTPUT_MODE_MASK	(0x01)
+#define OUTPUT_MODE_DVI		(0x00)
+#define OUTPUT_MODE_HDMI	(0x01)
+
+#define LINK_INTEGRITY_MODE_MASK        0x40
+#define LINK_INTEGRITY_STATIC           (0x00)
+#define LINK_INTEGRITY_DYNAMIC          (0x40)
+
+#define TMDS_OUTPUT_CONTROL_MASK	0x10
+#define TMDS_OUTPUT_CONTROL_ACTIVE      (0x00)
+#define TMDS_OUTPUT_CONTROL_POWER_DOWN  (0x10)
+
+#define AV_MUTE_MASK                    0x08
+#define AV_MUTE_NORMAL                  (0x00)
+#define AV_MUTE_MUTED                   (0x08)
+
+#define TX_POWER_STATE_MASK             0x3
+#define TX_POWER_STATE_D0               (0x00)
+#define TX_POWER_STATE_D1               (0x01)
+#define TX_POWER_STATE_D2               (0x02)
+#define TX_POWER_STATE_D3               (0x03)
+
+#define AUDIO_MUTE_MASK                  0x10
+#define AUDIO_MUTE_NORMAL                (0x00)
+#define AUDIO_MUTE_MUTED                 (0x10)
+
+#define AUDIO_SEL_MASK                   0xC0
+#define AUD_IF_SPDIF                     0x40
+#define AUD_IF_I2S                       0x80
+#define AUD_IF_DSD                       0xC0
+#define AUD_IF_HBR                       0x04
+
+#define REFER_TO_STREAM_HDR		0x00
+
+#define AUD_PASS_BASIC      0x00
+#define AUD_PASS_ALL        0x01
+#define AUD_DOWN_SAMPLE     0x02
+#define AUD_DO_NOT_CHECK    0x03
+
+#define BITS_IN_RGB         0x00
+#define BITS_IN_YCBCR444    0x01
+#define BITS_IN_YCBCR422    0x02
+
+#define BITS_IN_AUTO_RANGE  0x00
+#define BITS_IN_FULL_RANGE  0x04
+#define BITS_IN_LTD_RANGE   0x08
+
+#define BIT_EN_DITHER_10_8  0x40
+#define BIT_EXTENDED_MODE   0x80
+
+#define SII_EDID_LEN		512
+#define SIZE_AVI_INFOFRAME	0x0E
+#define SIZE_AUDIO_INFOFRAME    0x0F
+
+#define _4_To_3                 0x10
+#define _16_To_9                0x20
+#define SAME_AS_AR              0x08
+
+struct sii902x_data {
+	struct platform_device *pdev;
+	struct i2c_client *client;
+	struct mxc_dispdrv_entry *disp_hdmi;
+	struct regulator *io_reg;
+	struct regulator *analog_reg;
+	struct delayed_work det_work;
+	struct fb_info *fbi;
+	struct mxc_edid_cfg edid_cfg;
+	bool cable_plugin;
+	bool rx_powerup;
+	bool need_mode_change;
+	u8 edid[SII_EDID_LEN];
+	struct notifier_block nb;
+
+	u8 power_state;
+	u8 tpivmode[3];
+	u8 pixrep;
+
+	/* SII902x video setting:
+	 * 1. hdmi video fmt:
+	 * 	0 = CEA-861 VIC; 1 = HDMI_VIC; 2 = 3D
+	 * 2. vic: video mode index
+	 * 3. aspect ratio:
+	 * 	4x3 or 16x9
+	 * 4. color space:
+	 *	0 = RGB; 1 = YCbCr4:4:4; 2 = YCbCr4:2:2_16bits;
+	 *	3 = YCbCr4:2:2_8bits;4 = xvYCC4:4:4
+	 * 5. color depth:
+	 *	0 = 8bits; 1 = 10bits; 2 = 12bits; 3 = 16bits
+	 * 6. colorimetry:
+	 *	0 = 601; 1 = 709
+	 * 7. syncmode:
+	 * 	0 = external HS/VS/DE; 1 = external HS/VS and internal DE;
+	 *	2 = embedded sync
+	 */
+#define VMD_HDMIFORMAT_CEA_VIC                  0x00
+#define VMD_HDMIFORMAT_HDMI_VIC                 0x01
+#define VMD_HDMIFORMAT_3D                       0x02
+#define VMD_HDMIFORMAT_PC                       0x03
+	u8 hdmi_vid_fmt;
+	u8 vic;
+#define VMD_ASPECT_RATIO_4x3                    0x01
+#define VMD_ASPECT_RATIO_16x9                   0x02
+	u8 aspect_ratio;
+#define RGB			0
+#define YCBCR444		1
+#define YCBCR422_16BITS		2
+#define YCBCR422_8BITS		3
+#define XVYCC444		4
+	u8 icolor_space;
+	u8 ocolor_space;
+#define VMD_COLOR_DEPTH_8BIT                    0x00
+#define VMD_COLOR_DEPTH_10BIT                   0x01
+#define VMD_COLOR_DEPTH_12BIT                   0x02
+#define VMD_COLOR_DEPTH_16BIT                   0x03
+	u8 color_depth;
+#define COLORIMETRY_601		0
+#define COLORIMETRY_709		1
+	u8 colorimetry;
+#define EXTERNAL_HSVSDE		0
+#define INTERNAL_DE             1
+#define EMBEDDED_SYNC           2
+	u8 syncmode;
+	u8 threeDstruct;
+	u8 threeDextdata;
+
+#define AMODE_I2S               0
+#define AMODE_SPDIF             1
+#define AMODE_HBR               2
+#define AMODE_DSD               3
+	u8 audio_mode;
+#define ACHANNEL_2CH            1
+#define ACHANNEL_3CH            2
+#define ACHANNEL_4CH            3
+#define ACHANNEL_5CH            4
+#define ACHANNEL_6CH            5
+#define ACHANNEL_7CH            6
+#define ACHANNEL_8CH            7
+	u8 audio_channels;
+	u8 audiofs;
+	u8 audio_word_len;
+	u8 audio_i2s_fmt;
+};
+
+static __attribute__ ((unused)) void dump_regs(struct sii902x_data *sii902x,
+					u8 reg, int len)
+{
+	u8 buf[50];
+	int i;
+
+	i2c_smbus_read_i2c_block_data(sii902x->client, reg, len, buf);
+	for (i = 0; i < len; i++)
+		dev_dbg(&sii902x->client->dev, "reg[0x%02X]: 0x%02X\n",
+				i+reg, buf[i]);
+}
+
+static ssize_t sii902x_show_name(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct sii902x_data *sii902x = dev_get_drvdata(dev);
+
+	strcpy(buf, sii902x->fbi->fix.id);
+	sprintf(buf+strlen(buf), "\n");
+
+	return strlen(buf);
+}
+
+static DEVICE_ATTR(fb_name, S_IRUGO, sii902x_show_name, NULL);
+
+static ssize_t sii902x_show_state(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct sii902x_data *sii902x = dev_get_drvdata(dev);
+
+	if (sii902x->cable_plugin == false)
+		strcpy(buf, "plugout\n");
+	else
+		strcpy(buf, "plugin\n");
+
+	return strlen(buf);
+}
+
+static DEVICE_ATTR(cable_state, S_IRUGO, sii902x_show_state, NULL);
+
+static ssize_t sii902x_show_edid(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct sii902x_data *sii902x = dev_get_drvdata(dev);
+	int i, j, len = 0;
+
+	for (j = 0; j < SII_EDID_LEN/16; j++) {
+		for (i = 0; i < 16; i++)
+			len += sprintf(buf+len, "0x%02X ",
+					sii902x->edid[j*16 + i]);
+		len += sprintf(buf+len, "\n");
+	}
+
+	return len;
+}
+
+static DEVICE_ATTR(edid, S_IRUGO, sii902x_show_edid, NULL);
+
+/*------------------------------------------------------------------------------
+ * Function Description: Write "0" to all bits in TPI offset "Offset" that are set
+ *                 to "1" in "Pattern"; Leave all other bits in "Offset"
+ *                 unchanged.
+ *-----------------------------------------------------------------------------
+ */
+void read_clr_write_tpi(struct i2c_client *client, u8 offset, u8 mask)
+{
+	u8 tmp;
+
+	tmp = i2c_smbus_read_byte_data(client, offset);
+	tmp &= ~mask;
+	i2c_smbus_write_byte_data(client, offset, tmp);
+}
+
+/*------------------------------------------------------------------------------
+ * Function Description: Write "1" to all bits in TPI offset "Offset" that are set
+ *                 to "1" in "Pattern"; Leave all other bits in "Offset"
+ *                 unchanged.
+ *-----------------------------------------------------------------------------
+ */
+void read_set_write_tpi(struct i2c_client *client, u8 offset, u8 mask)
+{
+	u8 tmp;
+
+	tmp = i2c_smbus_read_byte_data(client, offset);
+	tmp |= mask;
+	i2c_smbus_write_byte_data(client, offset, tmp);
+}
+
+/*------------------------------------------------------------------------------
+ * Function Description: Write "Value" to all bits in TPI offset "Offset" that are set
+ *                 to "1" in "Mask"; Leave all other bits in "Offset"
+ *                 unchanged.
+ *----------------------------------------------------------------------------
+ */
+void read_modify_tpi(struct i2c_client *client, u8 offset, u8 mask, u8 value)
+{
+	u8 tmp;
+
+	tmp = i2c_smbus_read_byte_data(client, offset);
+	tmp &= ~mask;
+	tmp |= (value & mask);
+	i2c_smbus_write_byte_data(client, offset, tmp);
+}
+
+/*------------------------------------------------------------------------------
+ * Function Description: Read an indexed register value
+ *                 Write:
+ *                     1. 0xBC => Internal page num
+ *                     2. 0xBD => Indexed register offset
+ *                 Read:
+ *                     3. 0xBE => Returns the indexed register value
+ *----------------------------------------------------------------------------
+ */
+int read_idx_reg(struct i2c_client *client, u8 page, u8 regoffset)
+{
+	i2c_smbus_write_byte_data(client, TPI_INTERNAL_PAGE_REG, page);
+	i2c_smbus_write_byte_data(client, TPI_INDEXED_OFFSET_REG, regoffset);
+	return i2c_smbus_read_byte_data(client, TPI_INDEXED_VALUE_REG);
+}
+
+/*------------------------------------------------------------------------------
+ * Function Description: Write a value to an indexed register
+ *
+ *                  Write:
+ *                      1. 0xBC => Internal page num
+ *                      2. 0xBD => Indexed register offset
+ *                      3. 0xBE => Set the indexed register value
+ *------------------------------------------------------------------------------
+ */
+void write_idx_reg(struct i2c_client *client, u8 page, u8 regoffset, u8 regval)
+{
+	i2c_smbus_write_byte_data(client, TPI_INTERNAL_PAGE_REG, page);
+	i2c_smbus_write_byte_data(client, TPI_INDEXED_OFFSET_REG, regoffset);
+	i2c_smbus_write_byte_data(client, TPI_INDEXED_VALUE_REG, regval);
+}
+
+/*------------------------------------------------------------------------------
+ * Function Description: Write "Value" to all bits in TPI offset "Offset" that are set
+ *                 to "1" in "Mask"; Leave all other bits in "Offset"
+ *                 unchanged.
+ *----------------------------------------------------------------------------
+ */
+void read_modify_idx_reg(struct i2c_client *client, u8 page, u8 regoffset, u8 mask, u8 value)
+{
+	u8 tmp;
+
+	i2c_smbus_write_byte_data(client, TPI_INTERNAL_PAGE_REG, page);
+	i2c_smbus_write_byte_data(client, TPI_INDEXED_OFFSET_REG, regoffset);
+	tmp = i2c_smbus_read_byte_data(client, TPI_INDEXED_VALUE_REG);
+	tmp &= ~mask;
+	tmp |= (value & mask);
+	i2c_smbus_write_byte_data(client, TPI_INDEXED_VALUE_REG, tmp);
+}
+
+static void sii902x_set_powerstate(struct sii902x_data *sii902x, u8 state)
+{
+	if (sii902x->power_state != state) {
+		read_modify_tpi(sii902x->client, TPI_DEVICE_POWER_STATE_CTRL_REG,
+				TX_POWER_STATE_MASK, state);
+		sii902x->power_state = state;
+	}
+}
+
+static void sii902x_setAVI(struct sii902x_data *sii902x)
+{
+	u8 avi_data[SIZE_AVI_INFOFRAME];
+	u8 tmp;
+	int i;
+
+	dev_dbg(&sii902x->client->dev, "set AVI frame\n");
+
+	memset(avi_data, 0, SIZE_AVI_INFOFRAME);
+
+	if (sii902x->edid_cfg.cea_ycbcr444)
+		tmp = 2;
+	else if (sii902x->edid_cfg.cea_ycbcr422)
+		tmp = 1;
+	else
+		tmp = 0;
+
+	/* AVI byte1: Y1Y0 (output format) */
+	avi_data[1] = (tmp << 5) & 0x60;
+	/* A0 = 1; Active format identification data is present in the AVI InfoFrame.
+	 * S1:S0 = 00;
+	 */
+	avi_data[1] |= 0x10;
+
+	if (sii902x->ocolor_space == XVYCC444) {
+		avi_data[2] = 0xC0;
+		if (sii902x->colorimetry == COLORIMETRY_601)
+			avi_data[3] &= ~0x70;
+		else if (sii902x->colorimetry == COLORIMETRY_709)
+			avi_data[3] = (avi_data[3] & ~0x70) | 0x10;
+	} else if (sii902x->ocolor_space != RGB) {
+		if (sii902x->colorimetry == COLORIMETRY_709)
+			avi_data[2] = 0x80;/* AVI byte2: C1C0*/
+		else if (sii902x->colorimetry == COLORIMETRY_601)
+			avi_data[2] = 0x40;/* AVI byte2: C1C0 */
+	} else {/* Carries no data */
+		/* AVI Byte2: C1C0 */
+		avi_data[2] &= ~0xc0; /* colorimetry = 0 */
+		avi_data[3] &= ~0x70; /* Extended colorimetry = 0 */
+	}
+
+	avi_data[4] = sii902x->vic;
+
+	/*  Set the Aspect Ration info into the Infoframe Byte 2 */
+	if (sii902x->aspect_ratio == VMD_ASPECT_RATIO_16x9)
+		avi_data[2] |= _16_To_9; /* AVI Byte2: M1M0 */
+	else
+		avi_data[2] |= _4_To_3;
+
+       avi_data[2] |= SAME_AS_AR;  /* AVI Byte2: R3..R1 - Set to "Same as Picture Aspect Ratio" */
+       avi_data[5] = sii902x->pixrep; /* AVI Byte5: Pixel Replication - PR3..PR0 */
+
+       /* Calculate AVI InfoFrame ChecKsum */
+       avi_data[0] = 0x82 + 0x02 + 0x0D;
+       for (i = 1; i < SIZE_AVI_INFOFRAME; i++)
+	       avi_data[0] += avi_data[i];
+       avi_data[0] = 0x100 - avi_data[0];
+
+       /* Write the Inforframe data to the TPI Infoframe registers */
+	for (i = 0; i < SIZE_AVI_INFOFRAME; i++)
+		i2c_smbus_write_byte_data(sii902x->client,
+				TPI_AVI_BYTE_0 + i, avi_data[i]);
+
+	dump_regs(sii902x, TPI_AVI_BYTE_0, SIZE_AVI_INFOFRAME);
+}
+
+#define TYPE_AUDIO_INFOFRAMES       0x84
+#define AUDIO_INFOFRAMES_VERSION    0x01
+#define AUDIO_INFOFRAMES_LENGTH     0x0A
+/*------------------------------------------------------------------------------
+* Function Description: Load Audio InfoFrame data into registers and send to sink
+*
+* Accepts: (1) Channel count
+*              (2) speaker configuration per CEA-861D Tables 19, 20
+*              (3) Coding type: 0x09 for DSD Audio. 0 (refer to stream header) for all the rest
+*              (4) Sample Frequency. Non zero for HBR only
+*              (5) Audio Sample Length. Non zero for HBR only.
+*------------------------------------------------------------------------------
+*/
+static void  sii902x_setAIF(struct sii902x_data *sii902x,
+		u8 codingtype, u8 sample_size, u8 sample_freq,
+		u8 speaker_cfg)
+{
+	u8 aif_data[SIZE_AUDIO_INFOFRAME];
+	u8 channel_count = sii902x->audio_channels & 0x07;
+	int i;
+
+	dev_dbg(&sii902x->client->dev, "set AIF frame\n");
+
+	memset(aif_data, 0, SIZE_AUDIO_INFOFRAME);
+
+	/*  Disbale MPEG/Vendor Specific InfoFrames */
+	i2c_smbus_write_byte_data(sii902x->client, MISC_INFO_FRAMES_CTRL, DISABLE_AUDIO);
+
+	aif_data[0] = TYPE_AUDIO_INFOFRAMES;
+	aif_data[1] = AUDIO_INFOFRAMES_VERSION;
+	aif_data[2] = AUDIO_INFOFRAMES_LENGTH;
+	/* Calculate checksum - 0x84 + 0x01 + 0x0A */
+	aif_data[3] = TYPE_AUDIO_INFOFRAMES +
+		AUDIO_INFOFRAMES_VERSION + AUDIO_INFOFRAMES_LENGTH;
+
+	aif_data[4] = channel_count; /* 0 for "Refer to Stream Header" or for 2 Channels. 0x07 for 8 Channels*/
+	aif_data[4] |= (codingtype << 4); /* 0xC7[7:4] == 0b1001 for DSD Audio */
+	aif_data[5] = ((sample_freq & 0x07) << 2) | (sample_size & 0x03);
+	aif_data[7] = speaker_cfg;
+
+	for (i = 4; i < SIZE_AUDIO_INFOFRAME; i++)
+		aif_data[3] += aif_data[i];
+
+	aif_data[3] = 0x100 - aif_data[3];
+
+	/* Re-enable Audio InfoFrame transmission and repeat */
+	i2c_smbus_write_byte_data(sii902x->client, MISC_INFO_FRAMES_CTRL, EN_AND_RPT_AUDIO);
+
+	for (i = 0; i < SIZE_AUDIO_INFOFRAME; i++)
+		i2c_smbus_write_byte_data(sii902x->client,
+				MISC_INFO_FRAMES_TYPE + i, aif_data[i]);
+
+	dump_regs(sii902x, MISC_INFO_FRAMES_TYPE, SIZE_AUDIO_INFOFRAME);
+}
+
+static void sii902x_setaudio(struct sii902x_data *sii902x)
+{
+	dev_dbg(&sii902x->client->dev, "set audio\n");
+
+	/* mute audio */
+	read_modify_tpi(sii902x->client, TPI_AUDIO_INTERFACE_REG,
+			AUDIO_MUTE_MASK, AUDIO_MUTE_MUTED);
+	if (sii902x->audio_mode == AMODE_I2S) {
+		read_modify_tpi(sii902x->client, TPI_AUDIO_INTERFACE_REG,
+				AUDIO_SEL_MASK, AUD_IF_I2S);
+		i2c_smbus_write_byte_data(sii902x->client, TPI_AUDIO_HANDLING,
+				0x08 | AUD_DO_NOT_CHECK);
+	} else {
+		read_modify_tpi(sii902x->client, TPI_AUDIO_INTERFACE_REG,
+				AUDIO_SEL_MASK, AUD_IF_SPDIF);
+		i2c_smbus_write_byte_data(sii902x->client, TPI_AUDIO_HANDLING,
+				AUD_PASS_BASIC);
+	}
+
+	if (sii902x->audio_channels == ACHANNEL_2CH)
+		read_clr_write_tpi(sii902x->client, TPI_AUDIO_INTERFACE_REG, 0x20);
+	else
+		read_set_write_tpi(sii902x->client, TPI_AUDIO_INTERFACE_REG, 0x20);
+
+	if (sii902x->audio_mode == AMODE_I2S) {
+		/* I2S - Map channels */
+		i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_EN, 0x80);
+
+		if (sii902x->audio_channels > ACHANNEL_2CH)
+			i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_EN, 0x91);
+
+		if (sii902x->audio_channels > ACHANNEL_4CH)
+			i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_EN, 0xA2);
+
+		if (sii902x->audio_channels > ACHANNEL_6CH)
+			i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_EN, 0xB3);
+
+		/* I2S - Stream Header Settings */
+		i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_CHST_0, 0x00);
+		i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_CHST_1, 0x00);
+		i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_CHST_2, 0x00);
+		i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_CHST_3, sii902x->audiofs);
+		i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_CHST_4,
+					(sii902x->audiofs << 4) | sii902x->audio_word_len);
+
+		/* added for 16bit auido noise issue */
+		write_idx_reg(sii902x->client, INDEXED_PAGE_1, 0x24, sii902x->audio_word_len);
+
+		/* I2S - Input Configuration */
+		i2c_smbus_write_byte_data(sii902x->client, TPI_I2S_IN_CFG, sii902x->audio_i2s_fmt);
+	}
+
+	i2c_smbus_write_byte_data(sii902x->client, TPI_AUDIO_SAMPLE_CTRL, REFER_TO_STREAM_HDR);
+
+	sii902x_setAIF(sii902x, REFER_TO_STREAM_HDR, REFER_TO_STREAM_HDR, REFER_TO_STREAM_HDR, 0x00);
+
+	/* unmute audio */
+	read_modify_tpi(sii902x->client, TPI_AUDIO_INTERFACE_REG, AUDIO_MUTE_MASK, AUDIO_MUTE_NORMAL);
+}
+
+static void sii902x_setup(struct sii902x_data *sii902x, struct fb_info *fbi)
+{
+	u16 data[4];
+	u32 refresh;
+	u8 *tmp;
+	mm_segment_t old_fs;
+	unsigned int fmt;
+	int i;
+
+	dev_dbg(&sii902x->client->dev, "setup..\n");
+
+	sii902x->vic = mxc_edid_var_to_vic(&fbi->var);
+
+	/* set TPI video mode */
+	data[0] = PICOS2KHZ(fbi->var.pixclock) / 10;
+	data[2] = fbi->var.hsync_len + fbi->var.left_margin +
+		  fbi->var.xres + fbi->var.right_margin;
+	data[3] = fbi->var.vsync_len + fbi->var.upper_margin +
+		  fbi->var.yres + fbi->var.lower_margin;
+	refresh = data[2] * data[3];
+	refresh = (PICOS2KHZ(fbi->var.pixclock) * 1000) / refresh;
+	data[1] = refresh * 100;
+	tmp = (u8 *)data;
+	for (i = 0; i < 8; i++)
+		i2c_smbus_write_byte_data(sii902x->client, i, tmp[i]);
+
+	dump_regs(sii902x, 0, 8);
+
+	if (fbi->fbops->fb_ioctl) {
+		old_fs = get_fs();
+		set_fs(KERNEL_DS);
+		fbi->fbops->fb_ioctl(fbi, MXCFB_GET_DIFMT, (unsigned long)&fmt);
+		set_fs(old_fs);
+		if (fmt == IPU_PIX_FMT_VYU444) {
+			sii902x->icolor_space = YCBCR444;
+			dev_dbg(&sii902x->client->dev, "input color space YUV\n");
+		} else {
+			sii902x->icolor_space = RGB;
+			dev_dbg(&sii902x->client->dev, "input color space RGB\n");
+		}
+	}
+
+	/* reg 0x08: input bus/pixel: full pixel wide (24bit), rising edge */
+	sii902x->tpivmode[0] = 0x70;
+	/* reg 0x09: Set input format */
+	if (sii902x->icolor_space == RGB)
+		sii902x->tpivmode[1] =
+			(((BITS_IN_RGB | BITS_IN_AUTO_RANGE) & ~BIT_EN_DITHER_10_8) & ~BIT_EXTENDED_MODE);
+	else if (sii902x->icolor_space == YCBCR444)
+		sii902x->tpivmode[1] =
+			(((BITS_IN_YCBCR444 | BITS_IN_AUTO_RANGE) & ~BIT_EN_DITHER_10_8) & ~BIT_EXTENDED_MODE);
+	else if ((sii902x->icolor_space == YCBCR422_16BITS) || (sii902x->icolor_space == YCBCR422_8BITS))
+		sii902x->tpivmode[1] =
+			(((BITS_IN_YCBCR422 | BITS_IN_AUTO_RANGE) & ~BIT_EN_DITHER_10_8) & ~BIT_EXTENDED_MODE);
+	/* reg 0x0a: set output format to RGB */
+	sii902x->tpivmode[2] = 0x00;
+
+	if (fbi->var.xres/16 == fbi->var.yres/9)
+		sii902x->aspect_ratio = VMD_ASPECT_RATIO_16x9;
+	else
+		sii902x->aspect_ratio = VMD_ASPECT_RATIO_4x3;
+
+	if ((sii902x->vic == 6) || (sii902x->vic == 7) ||
+		(sii902x->vic == 21) || (sii902x->vic == 22) ||
+		(sii902x->vic == 2) || (sii902x->vic == 3) ||
+		(sii902x->vic == 17) || (sii902x->vic == 18)) {
+		sii902x->tpivmode[2] &= ~0x10; /*BT.601*/
+		sii902x->colorimetry = COLORIMETRY_601;
+		sii902x->aspect_ratio = VMD_ASPECT_RATIO_4x3;
+	} else {
+		sii902x->tpivmode[2] |= 0x10; /*BT.709*/
+		sii902x->colorimetry = COLORIMETRY_709;
+	}
+
+	if ((sii902x->vic == 10) || (sii902x->vic == 11) ||
+		(sii902x->vic == 12) || (sii902x->vic == 13) ||
+		(sii902x->vic == 14) || (sii902x->vic == 15) ||
+		(sii902x->vic == 25) || (sii902x->vic == 26) ||
+		(sii902x->vic == 27) || (sii902x->vic == 28) ||
+		(sii902x->vic == 29) || (sii902x->vic == 30) ||
+		(sii902x->vic == 35) || (sii902x->vic == 36) ||
+		(sii902x->vic == 37) || (sii902x->vic == 38))
+		sii902x->pixrep = 1;
+	else
+		sii902x->pixrep = 0;
+
+	dev_dbg(&sii902x->client->dev, "vic %d\n", sii902x->vic);
+	dev_dbg(&sii902x->client->dev, "pixrep %d\n", sii902x->pixrep);
+	if (sii902x->aspect_ratio == VMD_ASPECT_RATIO_4x3) {
+		dev_dbg(&sii902x->client->dev, "aspect 4:3\n");
+	} else {
+		dev_dbg(&sii902x->client->dev, "aspect 16:9\n");
+	}
+	if (sii902x->colorimetry == COLORIMETRY_601) {
+		dev_dbg(&sii902x->client->dev, "COLORIMETRY_601\n");
+	} else {
+		dev_dbg(&sii902x->client->dev, "COLORIMETRY_709\n");
+	}
+	dev_dbg(&sii902x->client->dev, "hdmi capbility %d\n", sii902x->edid_cfg.hdmi_cap);
+
+	sii902x->ocolor_space = RGB;
+	if (sii902x->edid_cfg.hdmi_cap) {
+		if (sii902x->edid_cfg.cea_ycbcr444) {
+			sii902x->ocolor_space = YCBCR444;
+			sii902x->tpivmode[2] |= 0x1; /*Ycbcr444*/
+		} else if (sii902x->edid_cfg.cea_ycbcr422) {
+			sii902x->ocolor_space = YCBCR422_8BITS;
+			sii902x->tpivmode[2] |= 0x2; /*Ycbcr422*/
+		}
+	}
+
+	dev_dbg(&sii902x->client->dev, "write reg 0x08 0X%2X\n", sii902x->tpivmode[0]);
+	dev_dbg(&sii902x->client->dev, "write reg 0x09 0X%2X\n", sii902x->tpivmode[1]);
+	dev_dbg(&sii902x->client->dev, "write reg 0x0a 0X%2X\n", sii902x->tpivmode[2]);
+
+	i2c_smbus_write_byte_data(sii902x->client, TPI_PIX_REPETITION, sii902x->tpivmode[0]);
+	i2c_smbus_write_byte_data(sii902x->client, TPI_INPUT_FORMAT_REG, sii902x->tpivmode[1]);
+	i2c_smbus_write_byte_data(sii902x->client, TPI_OUTPUT_FORMAT_REG, sii902x->tpivmode[2]);
+
+	/* goto state D0*/
+	sii902x_set_powerstate(sii902x, TX_POWER_STATE_D0);
+
+	if (sii902x->edid_cfg.hdmi_cap) {
+		sii902x_setAVI(sii902x);
+		sii902x_setaudio(sii902x);
+	} else {
+		/* set last byte of TPI AVI InfoFrame for TPI AVI I/O format to take effect ?? */
+		i2c_smbus_write_byte_data(sii902x->client, TPI_END_RIGHT_BAR_MSB, 0x00);
+
+		/* mute audio */
+		read_modify_tpi(sii902x->client, TPI_AUDIO_INTERFACE_REG,
+				AUDIO_MUTE_MASK, AUDIO_MUTE_MUTED);
+	}
+}
+
+#ifdef CONFIG_FB_MODE_HELPERS
+static int sii902x_read_edid(struct sii902x_data *sii902x,
+			struct fb_info *fbi)
+{
+	int old, dat, ret, cnt = 100;
+	unsigned short addr = 0x50;
+	u8 edid_old[SII_EDID_LEN];
+
+	old = i2c_smbus_read_byte_data(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG);
+
+	i2c_smbus_write_byte_data(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG, old | 0x4);
+	do {
+		cnt--;
+		msleep(10);
+		dat = i2c_smbus_read_byte_data(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG);
+	} while ((!(dat & 0x2)) && cnt);
+
+	if (!cnt) {
+		ret = -1;
+		goto done;
+	}
+
+	i2c_smbus_write_byte_data(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG, old | 0x06);
+
+	/* save old edid */
+	memcpy(edid_old, sii902x->edid, SII_EDID_LEN);
+
+	/* edid reading */
+	ret = mxc_edid_read(sii902x->client->adapter, addr,
+				sii902x->edid, &sii902x->edid_cfg, fbi);
+
+	cnt = 100;
+	do {
+		cnt--;
+		i2c_smbus_write_byte_data(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG, old & ~0x6);
+		msleep(10);
+		dat = i2c_smbus_read_byte_data(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG);
+	} while ((dat & 0x6) && cnt);
+
+	if (!cnt)
+		ret = -1;
+
+done:
+	i2c_smbus_write_byte_data(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG, old);
+
+	if (!memcmp(edid_old, sii902x->edid, SII_EDID_LEN))
+		ret = -2;
+	return ret;
+}
+#else
+static int sii902x_read_edid(struct sii902x_data *sii902x,
+			struct fb_info *fbi)
+{
+	return -1;
+}
+#endif
+
+static void sii902x_enable_tmds(struct sii902x_data *sii902x)
+{
+	/* goto state D0*/
+	sii902x_set_powerstate(sii902x, TX_POWER_STATE_D0);
+
+	/* Turn on DVI or HDMI */
+	if (sii902x->edid_cfg.hdmi_cap)
+		read_modify_tpi(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG,
+				OUTPUT_MODE_MASK, OUTPUT_MODE_HDMI);
+	else
+		read_modify_tpi(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG,
+				OUTPUT_MODE_MASK, OUTPUT_MODE_DVI);
+
+	read_modify_tpi(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG,
+		LINK_INTEGRITY_MODE_MASK | TMDS_OUTPUT_CONTROL_MASK | AV_MUTE_MASK,
+		LINK_INTEGRITY_DYNAMIC | TMDS_OUTPUT_CONTROL_ACTIVE | AV_MUTE_NORMAL);
+
+	i2c_smbus_write_byte_data(sii902x->client, TPI_PIX_REPETITION,
+				sii902x->tpivmode[0]);
+}
+
+static void sii902x_disable_tmds(struct sii902x_data *sii902x)
+{
+	read_modify_tpi(sii902x->client, TPI_SYSTEM_CONTROL_DATA_REG,
+		TMDS_OUTPUT_CONTROL_MASK | AV_MUTE_MASK | OUTPUT_MODE_MASK,
+		TMDS_OUTPUT_CONTROL_POWER_DOWN | AV_MUTE_MUTED | OUTPUT_MODE_DVI);
+
+	/* goto state D2*/
+	sii902x_set_powerstate(sii902x, TX_POWER_STATE_D2);
+}
+
+static void sii902x_poweron(struct sii902x_data *sii902x)
+{
+	struct fsl_mxc_lcd_platform_data *plat = sii902x->client->dev.platform_data;
+
+	dev_dbg(&sii902x->client->dev, "power on\n");
+
+	/* Enable pins to HDMI */
+	if (plat->enable_pins)
+		plat->enable_pins();
+
+	if (sii902x->rx_powerup)
+		sii902x_enable_tmds(sii902x);
+}
+
+static void sii902x_poweroff(struct sii902x_data *sii902x)
+{
+	struct fsl_mxc_lcd_platform_data *plat = sii902x->client->dev.platform_data;
+
+	dev_dbg(&sii902x->client->dev, "power off\n");
+
+	/* Disable pins to HDMI */
+	if (plat->disable_pins)
+		plat->disable_pins();
+
+	if (sii902x->rx_powerup)
+		sii902x_disable_tmds(sii902x);
+}
+
+static void sii902x_rx_powerup(struct sii902x_data *sii902x)
+{
+
+	dev_dbg(&sii902x->client->dev, "rx power up\n");
+
+	if (sii902x->need_mode_change) {
+		sii902x->fbi->var.activate |= FB_ACTIVATE_FORCE;
+		console_lock();
+		sii902x->fbi->flags |= FBINFO_MISC_USEREVENT;
+		fb_set_var(sii902x->fbi, &sii902x->fbi->var);
+		sii902x->fbi->flags &= ~FBINFO_MISC_USEREVENT;
+		console_unlock();
+		sii902x->need_mode_change = false;
+	}
+
+	sii902x_enable_tmds(sii902x);
+
+	sii902x->rx_powerup = true;
+}
+
+static void sii902x_rx_powerdown(struct sii902x_data *sii902x)
+{
+	dev_dbg(&sii902x->client->dev, "rx power down\n");
+
+	sii902x_disable_tmds(sii902x);
+
+	sii902x->rx_powerup = false;
+}
+
+static int sii902x_cable_connected(struct sii902x_data *sii902x)
+{
+	int ret;
+
+	dev_dbg(&sii902x->client->dev, "cable connected\n");
+
+	sii902x->cable_plugin = true;
+
+	/* edid read */
+	ret = sii902x_read_edid(sii902x, sii902x->fbi);
+	if (ret == -1)
+		dev_err(&sii902x->client->dev,
+				"read edid fail\n");
+	else if (ret == -2)
+		dev_info(&sii902x->client->dev,
+				"same edid\n");
+	else {
+		if (sii902x->fbi->monspecs.modedb_len > 0) {
+			int i;
+			const struct fb_videomode *mode;
+			struct fb_videomode m;
+
+			fb_destroy_modelist(&sii902x->fbi->modelist);
+
+			for (i = 0; i < sii902x->fbi->monspecs.modedb_len; i++) {
+				/*FIXME now we do not support interlaced mode */
+				if (!(sii902x->fbi->monspecs.modedb[i].vmode & FB_VMODE_INTERLACED))
+					fb_add_videomode(&sii902x->fbi->monspecs.modedb[i],
+							&sii902x->fbi->modelist);
+			}
+
+			fb_var_to_videomode(&m, &sii902x->fbi->var);
+			mode = fb_find_nearest_mode(&m,
+					&sii902x->fbi->modelist);
+
+			fb_videomode_to_var(&sii902x->fbi->var, mode);
+			sii902x->need_mode_change = true;
+		}
+	}
+
+	/* ?? remain it for control back door register */
+	read_modify_idx_reg(sii902x->client, INDEXED_PAGE_0, 0x0a, 0x08, 0x08);
+
+	return 0;
+}
+
+static void sii902x_cable_disconnected(struct sii902x_data *sii902x)
+{
+	dev_dbg(&sii902x->client->dev, "cable disconnected\n");
+	sii902x_rx_powerdown(sii902x);
+	sii902x->cable_plugin = false;
+}
+
+static void det_worker(struct work_struct *work)
+{
+	struct delayed_work *delay_work = to_delayed_work(work);
+	struct sii902x_data *sii902x =
+		container_of(delay_work, struct sii902x_data, det_work);
+	int status;
+	char event_string[16];
+	char *envp[] = { event_string, NULL };
+
+	status = i2c_smbus_read_byte_data(sii902x->client, TPI_INTERRUPT_STATUS_REG);
+
+	/* check cable status */
+	if (status & HOT_PLUG_EVENT) {
+		/* cable connection changes */
+		if ((status & HOT_PLUG_STATE) != sii902x->cable_plugin) {
+			if (status & HOT_PLUG_STATE) {
+				sprintf(event_string, "EVENT=plugin");
+				sii902x_cable_connected(sii902x);
+			} else {
+				sprintf(event_string, "EVENT=plugout");
+				sii902x_cable_disconnected(sii902x);
+			}
+			kobject_uevent_env(&sii902x->pdev->dev.kobj, KOBJ_CHANGE, envp);
+		}
+	}
+
+	/* check rx power */
+	if (((status & RX_SENSE_STATE) >> 3) != sii902x->rx_powerup) {
+		if (sii902x->cable_plugin) {
+			if (status & RX_SENSE_STATE)
+				sii902x_rx_powerup(sii902x);
+			else
+				sii902x_rx_powerdown(sii902x);
+		}
+	}
+
+	/* clear interrupt pending status */
+	i2c_smbus_write_byte_data(sii902x->client, TPI_INTERRUPT_STATUS_REG, status);
+}
+
+static irqreturn_t sii902x_detect_handler(int irq, void *data)
+{
+	struct sii902x_data *sii902x = data;
+
+	schedule_delayed_work(&(sii902x->det_work), msecs_to_jiffies(20));
+
+	return IRQ_HANDLED;
+}
+
+static int sii902x_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct fb_event *event = v;
+	struct fb_info *fbi = event->info;
+	struct sii902x_data *sii902x = container_of(nb, struct sii902x_data, nb);
+
+	if (strcmp(event->info->fix.id, sii902x->fbi->fix.id))
+		return 0;
+
+	switch (val) {
+	case FB_EVENT_MODE_CHANGE:
+		sii902x_setup(sii902x, fbi);
+		break;
+	case FB_EVENT_BLANK:
+		if (*((int *)event->data) == FB_BLANK_UNBLANK)
+			sii902x_poweron(sii902x);
+		else
+			sii902x_poweroff(sii902x);
+		break;
+	}
+	return 0;
+}
+
+static int sii902x_TPI_init(struct i2c_client *client)
+{
+	struct fsl_mxc_lcd_platform_data *plat = client->dev.platform_data;
+	u8 devid = 0;
+	u16 wid = 0;
+
+	if (plat->reset)
+		plat->reset();
+
+	/* sii902x back door register - Set terminations to default */
+	i2c_smbus_write_byte_data(client, 0x82, 0x25);
+	/* sii902x back door register - HW debounce to 64ms (0x14) */
+	i2c_smbus_write_byte_data(client, 0x7c, 0x14);
+
+	/* Set 902x in hardware TPI mode on and jump out of D3 state */
+	if (i2c_smbus_write_byte_data(client, TPI_ENABLE, 0x00) < 0) {
+		dev_err(&client->dev,
+			"cound not find device\n");
+		return -ENODEV;
+	}
+
+	msleep(100);
+
+	/* read device ID */
+	devid = read_idx_reg(client, INDEXED_PAGE_0, 0x03);
+	wid = devid;
+	wid <<= 8;
+	devid = read_idx_reg(client, INDEXED_PAGE_0, 0x02);
+	wid |= devid;
+	devid = i2c_smbus_read_byte_data(client, TPI_DEVICE_ID);
+
+	if (devid == 0xB0)
+		dev_info(&client->dev, "found device %04X", wid);
+	else {
+		dev_err(&client->dev, "cound not find device\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int sii902x_disp_init(struct mxc_dispdrv_entry *disp)
+{
+	int ret = 0;
+	struct sii902x_data *sii902x = mxc_dispdrv_getdata(disp);
+	struct mxc_dispdrv_setting *setting = mxc_dispdrv_getsetting(disp);
+	struct fsl_mxc_lcd_platform_data *plat = sii902x->client->dev.platform_data;
+	bool found = false;
+	static bool inited;
+
+	if (inited)
+		return -EBUSY;
+
+	inited = true;
+
+	setting->dev_id = plat->ipu_id;
+	setting->disp_id = plat->disp_id;
+	setting->if_fmt = IPU_PIX_FMT_RGB24;
+
+	sii902x->fbi = setting->fbi;
+	sii902x->power_state = TX_POWER_STATE_D2;
+	sii902x->icolor_space = RGB;
+	sii902x->audio_mode = AMODE_SPDIF;
+	sii902x->audio_channels = ACHANNEL_2CH;
+
+	sii902x->pdev = platform_device_register_simple("sii902x", 0, NULL, 0);
+	if (IS_ERR(sii902x->pdev)) {
+		dev_err(&sii902x->client->dev,
+				"Unable to register Sii902x as a platform device\n");
+		ret = PTR_ERR(sii902x->pdev);
+		goto register_pltdev_failed;
+	}
+
+	if (plat->io_reg) {
+		sii902x->io_reg = regulator_get(&sii902x->client->dev, plat->io_reg);
+		if (!IS_ERR(sii902x->io_reg)) {
+			regulator_set_voltage(sii902x->io_reg, 3300000, 3300000);
+			regulator_enable(sii902x->io_reg);
+		}
+	}
+	if (plat->analog_reg) {
+		sii902x->analog_reg = regulator_get(&sii902x->client->dev, plat->analog_reg);
+		if (!IS_ERR(sii902x->analog_reg)) {
+			regulator_set_voltage(sii902x->analog_reg, 1300000, 1300000);
+			regulator_enable(sii902x->analog_reg);
+		}
+	}
+
+	/* Claim HDMI pins */
+	if (plat->get_pins)
+		if (!plat->get_pins()) {
+			ret = -EACCES;
+			goto get_pins_failed;
+		}
+
+	ret = sii902x_TPI_init(sii902x->client);
+	if (ret < 0)
+		goto init_failed;
+
+	/* try to read edid */
+	ret = sii902x_read_edid(sii902x, sii902x->fbi);
+	if (ret < 0)
+		dev_warn(&sii902x->client->dev, "Can not read edid\n");
+	else {
+		INIT_LIST_HEAD(&sii902x->fbi->modelist);
+		if (sii902x->fbi->monspecs.modedb_len > 0) {
+			int i;
+			const struct fb_videomode *mode;
+			struct fb_videomode m;
+
+			for (i = 0; i < sii902x->fbi->monspecs.modedb_len; i++) {
+				/*FIXME now we do not support interlaced mode */
+				if (!(sii902x->fbi->monspecs.modedb[i].vmode
+							& FB_VMODE_INTERLACED))
+					fb_add_videomode(
+							&sii902x->fbi->monspecs.modedb[i],
+							&sii902x->fbi->modelist);
+			}
+
+			fb_find_mode(&sii902x->fbi->var, sii902x->fbi, setting->dft_mode_str,
+					NULL, 0, NULL, setting->default_bpp);
+
+			fb_var_to_videomode(&m, &sii902x->fbi->var);
+			mode = fb_find_nearest_mode(&m,
+					&sii902x->fbi->modelist);
+			fb_videomode_to_var(&sii902x->fbi->var, mode);
+			found = true;
+		}
+
+	}
+
+	if (!found) {
+		ret = fb_find_mode(&sii902x->fbi->var, sii902x->fbi, setting->dft_mode_str,
+				NULL, 0, NULL, setting->default_bpp);
+		if (!ret) {
+			ret = -EINVAL;
+			goto find_mode_failed;
+		}
+	}
+
+	if (sii902x->client->irq) {
+		ret = request_irq(sii902x->client->irq, sii902x_detect_handler,
+				IRQF_TRIGGER_FALLING,
+				"SII902x_det", sii902x);
+		if (ret < 0)
+			dev_warn(&sii902x->client->dev,
+				"cound not request det irq %d\n",
+				sii902x->client->irq);
+		else {
+			/*enable cable hot plug irq*/
+			i2c_smbus_write_byte_data(sii902x->client,
+					TPI_INTERRUPT_ENABLE_REG,
+					HOT_PLUG_EVENT | RX_SENSE_EVENT);
+			INIT_DELAYED_WORK(&(sii902x->det_work), det_worker);
+			/*clear hot plug event status*/
+			i2c_smbus_write_byte_data(sii902x->client,
+					TPI_INTERRUPT_STATUS_REG,
+					HOT_PLUG_EVENT | RX_SENSE_EVENT);
+		}
+
+		ret = device_create_file(&sii902x->pdev->dev, &dev_attr_fb_name);
+		if (ret < 0)
+			dev_warn(&sii902x->client->dev,
+				"cound not create sys node for fb name\n");
+		ret = device_create_file(&sii902x->pdev->dev, &dev_attr_cable_state);
+		if (ret < 0)
+			dev_warn(&sii902x->client->dev,
+				"cound not create sys node for cable state\n");
+		ret = device_create_file(&sii902x->pdev->dev, &dev_attr_edid);
+		if (ret < 0)
+			dev_warn(&sii902x->client->dev,
+				"cound not create sys node for edid\n");
+
+		dev_set_drvdata(&sii902x->pdev->dev, sii902x);
+	}
+
+	sii902x->nb.notifier_call = sii902x_fb_event;
+	ret = fb_register_client(&sii902x->nb);
+	if (ret < 0)
+		goto reg_fbclient_failed;
+
+	return ret;
+
+reg_fbclient_failed:
+find_mode_failed:
+init_failed:
+get_pins_failed:
+	platform_device_unregister(sii902x->pdev);
+register_pltdev_failed:
+	return ret;
+}
+
+static void sii902x_disp_deinit(struct mxc_dispdrv_entry *disp)
+{
+	struct sii902x_data *sii902x = mxc_dispdrv_getdata(disp);
+	struct fsl_mxc_lcd_platform_data *plat = sii902x->client->dev.platform_data;
+
+	if (sii902x->client->irq)
+		free_irq(sii902x->client->irq, sii902x);
+
+	fb_unregister_client(&sii902x->nb);
+
+	sii902x_poweroff(sii902x);
+
+	/* Release HDMI pins */
+	if (plat->put_pins)
+		plat->put_pins();
+
+	platform_device_unregister(sii902x->pdev);
+
+	kfree(sii902x);
+}
+
+static struct mxc_dispdrv_driver sii902x_drv = {
+	.name 	= DISPDRV_SII,
+	.init 	= sii902x_disp_init,
+	.deinit	= sii902x_disp_deinit,
+};
+
+static int __devinit sii902x_probe(struct i2c_client *client,
+		const struct i2c_device_id *id)
+{
+	struct sii902x_data *sii902x;
+	int ret = 0;
+
+	if (!i2c_check_functionality(client->adapter,
+				I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
+		return -ENODEV;
+
+	sii902x = kzalloc(sizeof(struct sii902x_data), GFP_KERNEL);
+	if (!sii902x) {
+		ret = -ENOMEM;
+		goto alloc_failed;
+	}
+
+	sii902x->client = client;
+
+	sii902x->disp_hdmi = mxc_dispdrv_register(&sii902x_drv);
+	mxc_dispdrv_setdata(sii902x->disp_hdmi, sii902x);
+
+	i2c_set_clientdata(client, sii902x);
+
+alloc_failed:
+	return ret;
+}
+
+static int __devexit sii902x_remove(struct i2c_client *client)
+{
+	struct sii902x_data *sii902x = i2c_get_clientdata(client);
+
+	mxc_dispdrv_unregister(sii902x->disp_hdmi);
+	kfree(sii902x);
+	return 0;
+}
+
+static const struct i2c_device_id sii902x_id[] = {
+	{ "sii902x", 0 },
+	{},
+};
+MODULE_DEVICE_TABLE(i2c, sii902x_id);
+
+static struct i2c_driver sii902x_i2c_driver = {
+	.driver = {
+		   .name = "sii902x",
+		   },
+	.probe = sii902x_probe,
+	.remove = sii902x_remove,
+	.id_table = sii902x_id,
+};
+
+static int __init sii902x_init(void)
+{
+	return i2c_add_driver(&sii902x_i2c_driver);
+}
+
+static void __exit sii902x_exit(void)
+{
+	i2c_del_driver(&sii902x_i2c_driver);
+}
+
+module_init(sii902x_init);
+module_exit(sii902x_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("SII902x DVI/HDMI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/tve.c b/drivers/video/mxc/tve.c
new file mode 100644
index 00000000000..35b100349fe
--- /dev/null
+++ b/drivers/video/mxc/tve.c
@@ -0,0 +1,1290 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file tve.c
+ * @brief Driver for i.MX TV encoder
+ *
+ * @ingroup Framebuffer
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/clk.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/sysfs.h>
+#include <linux/irq.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <linux/regulator/consumer.h>
+#include <linux/fsl_devices.h>
+#include <linux/uaccess.h>
+#include <asm/atomic.h>
+#include <mach/hardware.h>
+#include <mach/ipu-v3.h>
+#include "mxc_dispdrv.h"
+
+#define TVE_ENABLE			(1UL)
+#define TVE_DAC_FULL_RATE		(0UL<<1)
+#define TVE_DAC_DIV2_RATE		(1UL<<1)
+#define TVE_DAC_DIV4_RATE		(2UL<<1)
+#define TVE_IPU_CLK_ENABLE		(1UL<<3)
+
+#define CD_LM_INT		0x00000001
+#define CD_SM_INT		0x00000002
+#define CD_MON_END_INT		0x00000004
+#define CD_CH_0_LM_ST		0x00000001
+#define CD_CH_0_SM_ST		0x00000010
+#define CD_CH_1_LM_ST		0x00000002
+#define CD_CH_1_SM_ST		0x00000020
+#define CD_CH_2_LM_ST		0x00000004
+#define CD_CH_2_SM_ST		0x00000040
+#define CD_MAN_TRIG		0x00000100
+
+#define TVE_STAND_MASK			(0x0F<<8)
+#define TVE_NTSC_STAND			(0UL<<8)
+#define TVE_PAL_STAND			(3UL<<8)
+#define TVE_HD720P60_STAND		(4UL<<8)
+#define TVE_HD720P50_STAND		(5UL<<8)
+#define TVE_HD720P30_STAND		(6UL<<8)
+#define TVE_HD720P25_STAND		(7UL<<8)
+#define TVE_HD720P24_STAND		(8UL<<8)
+#define TVE_HD1080I60_STAND		(9UL<<8)
+#define TVE_HD1080I50_STAND		(10UL<<8)
+#define TVE_HD1035I60_STAND		(11UL<<8)
+#define TVE_HD1080P30_STAND		(12UL<<8)
+#define TVE_HD1080P25_STAND		(13UL<<8)
+#define TVE_HD1080P24_STAND		(14UL<<8)
+#define TVE_DAC_SAMPRATE_MASK		(0x3<<1)
+#define TVEV2_DATA_SRC_MASK		(0x3<<4)
+
+#define TVEV2_DATA_SRC_BUS_1		(0UL<<4)
+#define TVEV2_DATA_SRC_BUS_2		(1UL<<4)
+#define TVEV2_DATA_SRC_EXT		(2UL<<4)
+
+#define TVEV2_INP_VIDEO_FORM		(1UL<<6)
+#define TVEV2_P2I_CONV_EN		(1UL<<7)
+
+#define TVEV2_DAC_GAIN_MASK		0x3F
+#define TVEV2_DAC_TEST_MODE_MASK	0x7
+
+#define TVOUT_FMT_OFF			0
+#define TVOUT_FMT_NTSC			1
+#define TVOUT_FMT_PAL			2
+#define TVOUT_FMT_720P60		3
+#define TVOUT_FMT_720P30		4
+#define TVOUT_FMT_1080I60		5
+#define TVOUT_FMT_1080I50		6
+#define TVOUT_FMT_1080P30		7
+#define TVOUT_FMT_1080P25		8
+#define TVOUT_FMT_1080P24		9
+#define TVOUT_FMT_VGA_SVGA		10
+#define TVOUT_FMT_VGA_XGA		11
+#define TVOUT_FMT_VGA_SXGA		12
+#define TVOUT_FMT_VGA_WSXGA		13
+
+#define DISPDRV_VGA 	"vga"
+#define DISPDRV_TVE 	"tve"
+
+struct tve_data {
+	struct platform_device *pdev;
+	int revision;
+	int cur_mode;
+	int output_mode;
+	int detect;
+	void *base;
+	spinlock_t tve_lock;
+	bool inited;
+	int enabled;
+	int irq;
+	struct clk *clk;
+	struct clk *di_clk;
+	struct regulator *dac_reg;
+	struct regulator *dig_reg;
+	struct delayed_work cd_work;
+	struct tve_reg_mapping *regs;
+	struct tve_reg_fields_mapping *reg_fields;
+	struct mxc_dispdrv_entry *disp_tve;
+	struct mxc_dispdrv_entry *disp_vga;
+	struct notifier_block nb;
+};
+
+struct tve_reg_mapping {
+	u32 tve_com_conf_reg;
+	u32 tve_cd_cont_reg;
+	u32 tve_int_cont_reg;
+	u32 tve_stat_reg;
+	u32 tve_mv_cont_reg;
+	u32 tve_tvdac_cont_reg;
+	u32 tve_tst_mode_reg;
+};
+
+struct tve_reg_fields_mapping {
+	u32 cd_en;
+	u32 cd_trig_mode;
+	u32 cd_lm_int;
+	u32 cd_sm_int;
+	u32 cd_mon_end_int;
+	u32 cd_man_trig;
+	u32 sync_ch_mask;
+	u32 tvout_mode_mask;
+	u32 sync_ch_offset;
+	u32 tvout_mode_offset;
+	u32 cd_ch_stat_offset;
+};
+
+static struct tve_reg_mapping tve_regs_v1 = {
+	0, 0x14, 0x28, 0x2C, 0x48, 0x08, 0x30
+};
+
+static struct tve_reg_fields_mapping tve_reg_fields_v1 = {
+	1, 2, 1, 2, 4, 0x00010000, 0x7000, 0x70, 12, 4, 8
+};
+
+static struct tve_reg_mapping tve_regs_v2 = {
+	0, 0x34, 0x64, 0x68, 0xDC, 0x28, 0x6c
+};
+
+static struct tve_reg_fields_mapping tve_reg_fields_v2 = {
+	1, 2, 1, 2, 4, 0x01000000, 0x700000, 0x7000, 20, 12, 16
+};
+
+static struct fb_videomode video_modes_tve[] = {
+	{
+	 /* NTSC TV output */
+	 "TV-NTSC", 60, 720, 480, 74074,
+	 122, 15,
+	 18, 26,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_INTERLACED,
+	 FB_MODE_IS_DETAILED,},
+	{
+	 /* PAL TV output */
+	 "TV-PAL", 50, 720, 576, 74074,
+	 132, 11,
+	 22, 26,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
+	 FB_MODE_IS_DETAILED,},
+	{
+	 /* 720p60 TV output */
+	 "TV-720P60", 60, 1280, 720, 13468,
+	 260, 109,
+	 25, 4,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_NONINTERLACED,
+	 FB_MODE_IS_DETAILED,},
+	{
+	 /* 720p30 TV output */
+	 "TV-720P30", 30, 1280, 720, 13468,
+	 260, 1759,
+	 25, 4,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_NONINTERLACED,
+	 FB_MODE_IS_DETAILED,},
+	{
+	 /* 1080i60 TV output */
+	 "TV-1080I60", 60, 1920, 1080, 13468,
+	 192, 87,
+	 20, 24,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
+	 FB_MODE_IS_DETAILED,},
+	{
+	 /* 1080i50 TV output */
+	 "TV-1080I50", 50, 1920, 1080, 13468,
+	 192, 527,
+	 20, 24,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST,
+	 FB_MODE_IS_DETAILED,},
+	{
+	 /* 1080p30 TV output */
+	 "TV-1080P30", 30, 1920, 1080, 13468,
+	 192, 87,
+	 38, 6,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_NONINTERLACED,
+	 FB_MODE_IS_DETAILED,},
+	{
+	 /* 1080p25 TV output */
+	 "TV-1080P25", 25, 1920, 1080, 13468,
+	 192, 527,
+	 38, 6,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_NONINTERLACED,
+	 FB_MODE_IS_DETAILED,},
+	{
+	 /* 1080p24 TV output */
+	 "TV-1080P24", 24, 1920, 1080, 13468,
+	 192, 637,
+	 38, 6,
+	 1, 1,
+	 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	 FB_VMODE_NONINTERLACED,
+	 FB_MODE_IS_DETAILED,},
+};
+static int tve_modedb_sz = ARRAY_SIZE(video_modes_tve);
+
+static struct fb_videomode video_modes_vga[] = {
+	{
+	/* VGA 800x600 40M pixel clk output */
+	 "VGA-SVGA", 60, 800, 600, 25000,
+	 215, 28,
+	 24, 2,
+	 13, 2,
+	 0,
+	 FB_VMODE_NONINTERLACED,
+	 FB_MODE_IS_DETAILED,},
+	{
+	/* VGA 1024x768 65M pixel clk output */
+	 "VGA-XGA", 60, 1024, 768, 15384,
+	 160, 24,
+	 29, 3,
+	 136, 6,
+	 0,
+	 FB_VMODE_NONINTERLACED,
+	 FB_MODE_IS_DETAILED,},
+	{
+	/* VGA 1280x1024 108M pixel clk output */
+	"VGA-SXGA", 60, 1280, 1024, 9259,
+	358, 38,
+	38, 2,
+	12, 2,
+	0,
+	FB_VMODE_NONINTERLACED,
+	FB_MODE_IS_DETAILED,},
+	{
+	/* VGA 1680x1050 294M pixel clk output */
+	"VGA-WSXGA+", 60, 1680, 1050, 6796,
+	288, 104,
+	33, 2,
+	184, 2,
+	0,
+	FB_VMODE_NONINTERLACED,
+	FB_MODE_IS_DETAILED,},
+};
+static int vga_modedb_sz = ARRAY_SIZE(video_modes_vga);
+
+enum tvout_mode {
+	TV_OFF,
+	CVBS0,
+	CVBS2,
+	CVBS02,
+	SVIDEO,
+	SVIDEO_CVBS,
+	YPBPR,
+	TVRGB
+};
+
+static unsigned short tvout_mode_to_channel_map[8] = {
+	0,	/* TV_OFF */
+	1,	/* CVBS0 */
+	4,	/* CVBS2 */
+	5,	/* CVBS02 */
+	1,	/* SVIDEO */
+	5,	/* SVIDEO_CVBS */
+	1,	/* YPBPR */
+	7	/* TVRGB */
+};
+
+static void tve_dump_regs(struct tve_data *tve)
+{
+	dev_dbg(&tve->pdev->dev, "tve_com_conf_reg 0x%x\n",
+			readl(tve->base + tve->regs->tve_com_conf_reg));
+	dev_dbg(&tve->pdev->dev, "tve_cd_cont_reg 0x%x\n",
+			readl(tve->base + tve->regs->tve_cd_cont_reg));
+	dev_dbg(&tve->pdev->dev, "tve_int_cont_reg 0x%x\n",
+			readl(tve->base + tve->regs->tve_int_cont_reg));
+	dev_dbg(&tve->pdev->dev, "tve_tst_mode_reg 0x%x\n",
+			readl(tve->base + tve->regs->tve_tst_mode_reg));
+	dev_dbg(&tve->pdev->dev, "tve_tvdac_cont_reg0 0x%x\n",
+			readl(tve->base + tve->regs->tve_tvdac_cont_reg));
+	dev_dbg(&tve->pdev->dev, "tve_tvdac_cont_reg1 0x%x\n",
+			readl(tve->base + tve->regs->tve_tvdac_cont_reg + 4));
+	dev_dbg(&tve->pdev->dev, "tve_tvdac_cont_reg2 0x%x\n",
+			readl(tve->base + tve->regs->tve_tvdac_cont_reg + 8));
+}
+
+static int is_vga_enabled(struct tve_data *tve)
+{
+	u32 reg;
+
+	if (tve->revision == 2) {
+		reg = readl(tve->base + tve->regs->tve_tst_mode_reg);
+		if (reg & TVEV2_DAC_TEST_MODE_MASK)
+			return 1;
+		else
+			return 0;
+	}
+	return 0;
+}
+
+static inline int is_vga_mode(int mode)
+{
+	return ((mode == TVOUT_FMT_VGA_SVGA)
+		|| (mode == TVOUT_FMT_VGA_XGA)
+		|| (mode == TVOUT_FMT_VGA_SXGA)
+		|| (mode == TVOUT_FMT_VGA_WSXGA));
+}
+
+static inline int valid_mode(int mode)
+{
+	return (is_vga_mode(mode)
+		|| (mode == TVOUT_FMT_NTSC)
+		|| (mode == TVOUT_FMT_PAL)
+		|| (mode == TVOUT_FMT_720P30)
+		|| (mode == TVOUT_FMT_720P60)
+		|| (mode == TVOUT_FMT_1080I50)
+		|| (mode == TVOUT_FMT_1080I60)
+		|| (mode == TVOUT_FMT_1080P24)
+		|| (mode == TVOUT_FMT_1080P25)
+		|| (mode == TVOUT_FMT_1080P30));
+}
+
+static int get_video_mode(struct fb_info *fbi)
+{
+	int mode;
+
+	if (fb_mode_is_equal(fbi->mode, &video_modes_tve[0])) {
+		mode = TVOUT_FMT_NTSC;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_tve[1])) {
+		mode = TVOUT_FMT_PAL;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_tve[2])) {
+		mode = TVOUT_FMT_720P60;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_tve[3])) {
+		mode = TVOUT_FMT_720P30;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_tve[4])) {
+		mode = TVOUT_FMT_1080I60;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_tve[5])) {
+		mode = TVOUT_FMT_1080I50;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_tve[6])) {
+		mode = TVOUT_FMT_1080P30;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_tve[7])) {
+		mode = TVOUT_FMT_1080P25;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_tve[8])) {
+		mode = TVOUT_FMT_1080P24;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_vga[0])) {
+		mode = TVOUT_FMT_VGA_SVGA;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_vga[1])) {
+		mode = TVOUT_FMT_VGA_XGA;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_vga[2])) {
+		mode = TVOUT_FMT_VGA_SXGA;
+	} else if (fb_mode_is_equal(fbi->mode, &video_modes_vga[3])) {
+		mode = TVOUT_FMT_VGA_WSXGA;
+	} else {
+		mode = TVOUT_FMT_OFF;
+	}
+	return mode;
+}
+
+static void tve_disable_vga_mode(struct tve_data *tve)
+{
+	if (tve->revision == 2) {
+		u32 reg;
+		/* disable test mode */
+		reg = readl(tve->base + tve->regs->tve_tst_mode_reg);
+		reg = reg & ~TVEV2_DAC_TEST_MODE_MASK;
+		writel(reg, tve->base + tve->regs->tve_tst_mode_reg);
+	}
+}
+
+static void tve_set_tvout_mode(struct tve_data *tve, int mode)
+{
+	u32 conf_reg;
+
+	/* clear sync_ch and tvout_mode fields */
+	conf_reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+	conf_reg &= ~(tve->reg_fields->sync_ch_mask |
+				tve->reg_fields->tvout_mode_mask);
+
+	conf_reg = conf_reg & ~TVE_DAC_SAMPRATE_MASK;
+	if (tve->revision == 2) {
+		conf_reg = (conf_reg & ~TVEV2_DATA_SRC_MASK) |
+			TVEV2_DATA_SRC_BUS_1;
+		conf_reg = conf_reg & ~TVEV2_INP_VIDEO_FORM;
+		conf_reg = conf_reg & ~TVEV2_P2I_CONV_EN;
+	}
+
+	conf_reg |=
+		mode << tve->reg_fields->
+		tvout_mode_offset | tvout_mode_to_channel_map[mode] <<
+		tve->reg_fields->sync_ch_offset;
+	writel(conf_reg, tve->base + tve->regs->tve_com_conf_reg);
+}
+
+static int _is_tvout_mode_hd_compatible(struct tve_data *tve)
+{
+	u32 conf_reg, mode;
+
+	conf_reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+	mode = (conf_reg >> tve->reg_fields->tvout_mode_offset) & 7;
+	if (mode == YPBPR || mode == TVRGB) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static int tve_setup_vga(struct tve_data *tve)
+{
+	u32 reg;
+
+	if (tve->revision == 2) {
+		/* set gain */
+		reg = readl(tve->base + tve->regs->tve_tvdac_cont_reg);
+		reg = (reg & ~TVEV2_DAC_GAIN_MASK) | 0xa;
+		writel(reg, tve->base + tve->regs->tve_tvdac_cont_reg);
+		reg = readl(tve->base + tve->regs->tve_tvdac_cont_reg + 4);
+		reg = (reg & ~TVEV2_DAC_GAIN_MASK) | 0xa;
+		writel(reg, tve->base + tve->regs->tve_tvdac_cont_reg + 4);
+		reg = readl(tve->base + tve->regs->tve_tvdac_cont_reg + 8);
+		reg = (reg & ~TVEV2_DAC_GAIN_MASK) | 0xa;
+		writel(reg, tve->base + tve->regs->tve_tvdac_cont_reg + 8);
+
+		/* set tve_com_conf_reg  */
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_DAC_SAMPRATE_MASK) | TVE_DAC_DIV2_RATE;
+		reg = (reg & ~TVEV2_DATA_SRC_MASK) | TVEV2_DATA_SRC_BUS_2;
+		reg = reg | TVEV2_INP_VIDEO_FORM;
+		reg = reg & ~TVEV2_P2I_CONV_EN;
+		reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080P30_STAND;
+		reg |= TVRGB << tve->reg_fields->tvout_mode_offset |
+			1 << tve->reg_fields->sync_ch_offset;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+
+		/* set test mode */
+		reg = readl(tve->base + tve->regs->tve_tst_mode_reg);
+		reg = (reg & ~TVEV2_DAC_TEST_MODE_MASK) | 1;
+		writel(reg, tve->base + tve->regs->tve_tst_mode_reg);
+	}
+
+	return 0;
+}
+
+/**
+ * tve_setup
+ * initial the CH7024 chipset by setting register
+ * @param:
+ * 	vos: output video format
+ * @return:
+ * 	0 successful
+ * 	otherwise failed
+ */
+static int tve_setup(struct tve_data *tve, int mode)
+{
+	u32 reg;
+	struct clk *tve_parent_clk;
+	unsigned long parent_clock_rate = 216000000, di1_clock_rate = 27000000;
+	unsigned long tve_clock_rate = 216000000;
+	unsigned long lock_flags;
+
+	if (tve->cur_mode == mode)
+		return 0;
+
+	spin_lock_irqsave(&tve->tve_lock, lock_flags);
+
+	switch (mode) {
+	case TVOUT_FMT_PAL:
+	case TVOUT_FMT_NTSC:
+		parent_clock_rate = 216000000;
+		di1_clock_rate = 27000000;
+		break;
+	case TVOUT_FMT_720P60:
+	case TVOUT_FMT_1080I60:
+	case TVOUT_FMT_1080I50:
+	case TVOUT_FMT_720P30:
+	case TVOUT_FMT_1080P30:
+	case TVOUT_FMT_1080P25:
+	case TVOUT_FMT_1080P24:
+		parent_clock_rate = 297000000;
+		tve_clock_rate = 297000000;
+		di1_clock_rate = 74250000;
+		break;
+	case TVOUT_FMT_VGA_SVGA:
+		parent_clock_rate = 160000000;
+		tve_clock_rate = 80000000;
+		di1_clock_rate = 40000000;
+		break;
+	case TVOUT_FMT_VGA_XGA:
+		parent_clock_rate = 520000000;
+		tve_clock_rate = 130000000;
+		di1_clock_rate = 65000000;
+		break;
+	case TVOUT_FMT_VGA_SXGA:
+		parent_clock_rate = 864000000;
+		tve_clock_rate = 216000000;
+		di1_clock_rate = 108000000;
+		break;
+	case TVOUT_FMT_VGA_WSXGA:
+		parent_clock_rate = 588560000;
+		tve_clock_rate = 294280000;
+		di1_clock_rate = 147140000;
+		break;
+	}
+	if (tve->enabled)
+		clk_disable(tve->clk);
+
+	tve_parent_clk = clk_get_parent(tve->clk);
+
+	clk_set_rate(tve_parent_clk, parent_clock_rate);
+
+	tve_clock_rate = clk_round_rate(tve->clk, tve_clock_rate);
+	clk_set_rate(tve->clk, tve_clock_rate);
+
+	clk_enable(tve->clk);
+	di1_clock_rate = clk_round_rate(tve->di_clk, di1_clock_rate);
+	clk_set_rate(tve->di_clk, di1_clock_rate);
+
+	tve->cur_mode = mode;
+
+	/* select output video format */
+	if (mode == TVOUT_FMT_PAL) {
+		tve_disable_vga_mode(tve);
+		tve_set_tvout_mode(tve, YPBPR);
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_PAL_STAND;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to PAL video\n");
+	} else if (mode == TVOUT_FMT_NTSC) {
+		tve_disable_vga_mode(tve);
+		tve_set_tvout_mode(tve, YPBPR);
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_NTSC_STAND;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to NTSC video\n");
+	} else if (mode == TVOUT_FMT_720P60) {
+		tve_disable_vga_mode(tve);
+		if (!_is_tvout_mode_hd_compatible(tve)) {
+			tve_set_tvout_mode(tve, YPBPR);
+			dev_dbg(&tve->pdev->dev, "The TV out mode is HD incompatible. Setting to YPBPR.");
+		}
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_HD720P60_STAND;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to 720P60 video\n");
+	} else if (mode == TVOUT_FMT_720P30) {
+		tve_disable_vga_mode(tve);
+		if (!_is_tvout_mode_hd_compatible(tve)) {
+			tve_set_tvout_mode(tve, YPBPR);
+			dev_dbg(&tve->pdev->dev, "The TV out mode is HD incompatible. Setting to YPBPR.");
+		}
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_HD720P30_STAND;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to 720P30 video\n");
+	} else if (mode == TVOUT_FMT_1080I60) {
+		tve_disable_vga_mode(tve);
+		if (!_is_tvout_mode_hd_compatible(tve)) {
+			tve_set_tvout_mode(tve, YPBPR);
+			dev_dbg(&tve->pdev->dev, "The TV out mode is HD incompatible. Setting to YPBPR.");
+		}
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080I60_STAND;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to 1080I60 video\n");
+	} else if (mode == TVOUT_FMT_1080I50) {
+		tve_disable_vga_mode(tve);
+		if (!_is_tvout_mode_hd_compatible(tve)) {
+			tve_set_tvout_mode(tve, YPBPR);
+			dev_dbg(&tve->pdev->dev, "The TV out mode is HD incompatible. Setting to YPBPR.");
+		}
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080I50_STAND;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to 1080I50 video\n");
+	} else if (mode == TVOUT_FMT_1080P30) {
+		tve_disable_vga_mode(tve);
+		if (!_is_tvout_mode_hd_compatible(tve)) {
+			tve_set_tvout_mode(tve, YPBPR);
+			dev_dbg(&tve->pdev->dev, "The TV out mode is HD incompatible. Setting to YPBPR.");
+		}
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080P30_STAND;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to 1080P30 video\n");
+	} else if (mode == TVOUT_FMT_1080P25) {
+		tve_disable_vga_mode(tve);
+		if (!_is_tvout_mode_hd_compatible(tve)) {
+			tve_set_tvout_mode(tve, YPBPR);
+			dev_dbg(&tve->pdev->dev, "The TV out mode is HD incompatible. Setting to YPBPR.");
+		}
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080P25_STAND;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to 1080P25 video\n");
+	} else if (mode == TVOUT_FMT_1080P24) {
+		tve_disable_vga_mode(tve);
+		if (!_is_tvout_mode_hd_compatible(tve)) {
+			tve_set_tvout_mode(tve, YPBPR);
+			dev_dbg(&tve->pdev->dev, "The TV out mode is HD incompatible. Setting to YPBPR.");
+		}
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080P24_STAND;
+		writel(reg, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to 1080P24 video\n");
+	} else if (is_vga_mode(mode)) {
+		/* do not need cable detect */
+		tve_setup_vga(tve);
+		dev_dbg(&tve->pdev->dev, "TVE: change to VGA video\n");
+	} else if (mode == TVOUT_FMT_OFF) {
+		writel(0x0, tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE: change to OFF video\n");
+	} else {
+		dev_dbg(&tve->pdev->dev, "TVE: no such video format.\n");
+	}
+
+	if (!tve->enabled)
+		clk_disable(tve->clk);
+
+	spin_unlock_irqrestore(&tve->tve_lock, lock_flags);
+	return 0;
+}
+
+/**
+ * tve_enable
+ * Enable the tve Power to begin TV encoder
+ */
+static void tve_enable(struct tve_data *tve)
+{
+	u32 reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&tve->tve_lock, lock_flags);
+	if (!tve->enabled) {
+		tve->enabled = 1;
+		clk_enable(tve->clk);
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		writel(reg | TVE_IPU_CLK_ENABLE | TVE_ENABLE,
+					tve->base + tve->regs->tve_com_conf_reg);
+		dev_dbg(&tve->pdev->dev, "TVE power on.\n");
+	}
+
+	if (is_vga_enabled(tve)) {
+		/* disable interrupt */
+		dev_dbg(&tve->pdev->dev, "TVE VGA disable cable detect.\n");
+		writel(0xffffffff, tve->base + tve->regs->tve_stat_reg);
+		writel(0, tve->base + tve->regs->tve_int_cont_reg);
+	} else {
+		/* enable interrupt */
+		dev_dbg(&tve->pdev->dev, "TVE TVE enable cable detect.\n");
+		writel(0xffffffff, tve->base + tve->regs->tve_stat_reg);
+		writel(CD_SM_INT | CD_LM_INT | CD_MON_END_INT,
+				tve->base + tve->regs->tve_int_cont_reg);
+	}
+
+	spin_unlock_irqrestore(&tve->tve_lock, lock_flags);
+
+	tve_dump_regs(tve);
+}
+
+/**
+ * tve_disable
+ * Disable the tve Power to stop TV encoder
+ */
+static void tve_disable(struct tve_data *tve)
+{
+	u32 reg;
+	unsigned long lock_flags;
+
+	spin_lock_irqsave(&tve->tve_lock, lock_flags);
+	if (tve->enabled) {
+		tve->enabled = 0;
+		reg = readl(tve->base + tve->regs->tve_com_conf_reg);
+		writel(reg & ~TVE_ENABLE & ~TVE_IPU_CLK_ENABLE,
+				tve->base + tve->regs->tve_com_conf_reg);
+		clk_disable(tve->clk);
+		dev_dbg(&tve->pdev->dev, "TVE power off.\n");
+	}
+	spin_unlock_irqrestore(&tve->tve_lock, lock_flags);
+}
+
+static int tve_update_detect_status(struct tve_data *tve)
+{
+	int old_detect = tve->detect;
+	u32 stat_lm, stat_sm, stat;
+	u32 int_ctl;
+	u32 cd_cont_reg;
+	u32 timeout = 40;
+	unsigned long lock_flags;
+	char event_string[16];
+	char *envp[] = { event_string, NULL };
+
+	spin_lock_irqsave(&tve->tve_lock, lock_flags);
+
+	if (!tve->enabled) {
+		dev_warn(&tve->pdev->dev, "Warning: update tve status while it disabled!\n");
+		tve->detect = 0;
+		goto done;
+	}
+
+	int_ctl = readl(tve->base + tve->regs->tve_int_cont_reg);
+	cd_cont_reg = readl(tve->base + tve->regs->tve_cd_cont_reg);
+
+	if ((cd_cont_reg & 0x1) == 0) {
+		dev_warn(&tve->pdev->dev, "Warning: pls enable TVE CD first!\n");
+		goto done;
+	}
+
+	stat = readl(tve->base + tve->regs->tve_stat_reg);
+	while (((stat & CD_MON_END_INT) == 0) && (timeout > 0)) {
+		spin_unlock_irqrestore(&tve->tve_lock, lock_flags);
+		msleep(2);
+		spin_lock_irqsave(&tve->tve_lock, lock_flags);
+		timeout -= 2;
+		if (!tve->enabled) {
+			dev_warn(&tve->pdev->dev, "Warning: update tve status while it disabled!\n");
+			tve->detect = 0;
+			goto done;
+		} else
+			stat = readl(tve->base + tve->regs->tve_stat_reg);
+	}
+	if (((stat & CD_MON_END_INT) == 0) && (timeout <= 0)) {
+		dev_warn(&tve->pdev->dev, "Warning: get detect result without CD_MON_END_INT!\n");
+		goto done;
+	}
+
+	stat = stat >> tve->reg_fields->cd_ch_stat_offset;
+	stat_lm = stat & (CD_CH_0_LM_ST | CD_CH_1_LM_ST | CD_CH_2_LM_ST);
+	if ((stat_lm == (CD_CH_0_LM_ST | CD_CH_1_LM_ST | CD_CH_2_LM_ST)) &&
+		((stat & (CD_CH_0_SM_ST | CD_CH_1_SM_ST | CD_CH_2_SM_ST)) == 0)
+		) {
+			tve->detect = 3;
+			tve->output_mode = YPBPR;
+	} else if ((stat_lm == (CD_CH_0_LM_ST | CD_CH_1_LM_ST)) &&
+		((stat & (CD_CH_0_SM_ST | CD_CH_1_SM_ST)) == 0)) {
+			tve->detect = 4;
+			tve->output_mode = SVIDEO;
+	} else if (stat_lm == CD_CH_0_LM_ST) {
+		stat_sm = stat & CD_CH_0_SM_ST;
+		if (stat_sm != 0) {
+			/* headset */
+			tve->detect = 2;
+			tve->output_mode = TV_OFF;
+		} else {
+			tve->detect = 1;
+			tve->output_mode = CVBS0;
+		}
+	} else if (stat_lm == CD_CH_2_LM_ST) {
+		stat_sm = stat & CD_CH_2_SM_ST;
+		if (stat_sm != 0) {
+			/* headset */
+			tve->detect = 2;
+			tve->output_mode = TV_OFF;
+		} else {
+			tve->detect = 1;
+			tve->output_mode = CVBS2;
+		}
+	} else {
+		/* none */
+		tve->detect = 0;
+		tve->output_mode = TV_OFF;
+	}
+
+	tve_set_tvout_mode(tve, tve->output_mode);
+
+	/* clear interrupt */
+	writel(CD_MON_END_INT | CD_LM_INT | CD_SM_INT,
+			tve->base + tve->regs->tve_stat_reg);
+
+	writel(int_ctl | CD_SM_INT | CD_LM_INT,
+			tve->base + tve->regs->tve_int_cont_reg);
+
+done:
+	spin_unlock_irqrestore(&tve->tve_lock, lock_flags);
+
+	if (old_detect != tve->detect) {
+		sysfs_notify(&tve->pdev->dev.kobj, NULL, "headphone");
+		if (tve->detect == 1)
+			sprintf(event_string, "EVENT=CVBS0");
+		else if (tve->detect == 3)
+			sprintf(event_string, "EVENT=YPBPR");
+		else if (tve->detect == 4)
+			sprintf(event_string, "EVENT=SVIDEO");
+		else
+			sprintf(event_string, "EVENT=NONE");
+		kobject_uevent_env(&tve->pdev->dev.kobj, KOBJ_CHANGE, envp);
+	}
+
+	dev_dbg(&tve->pdev->dev, "detect = %d mode = %d\n",
+			tve->detect, tve->output_mode);
+	return tve->detect;
+}
+
+static void cd_work_func(struct work_struct *work)
+{
+	struct delayed_work *delay_work = to_delayed_work(work);
+	struct tve_data *tve =
+		container_of(delay_work, struct tve_data, cd_work);
+
+	tve_update_detect_status(tve);
+}
+
+static irqreturn_t tve_detect_handler(int irq, void *data)
+{
+	struct tve_data *tve = data;
+
+	u32 int_ctl = readl(tve->base + tve->regs->tve_int_cont_reg);
+
+	/* disable INT first */
+	int_ctl &= ~(CD_SM_INT | CD_LM_INT | CD_MON_END_INT);
+	writel(int_ctl, tve->base + tve->regs->tve_int_cont_reg);
+
+	writel(CD_MON_END_INT | CD_LM_INT | CD_SM_INT,
+			tve->base + tve->regs->tve_stat_reg);
+
+	schedule_delayed_work(&tve->cd_work, msecs_to_jiffies(1000));
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * FB suspend/resume routing
+ */
+static int tve_suspend(struct tve_data *tve)
+{
+	if (tve->enabled) {
+		writel(0, tve->base + tve->regs->tve_int_cont_reg);
+		writel(0, tve->base + tve->regs->tve_cd_cont_reg);
+		writel(0, tve->base + tve->regs->tve_com_conf_reg);
+		clk_disable(tve->clk);
+	}
+	return 0;
+}
+
+static int tve_resume(struct tve_data *tve, struct fb_info *fbi)
+{
+	int mode;
+
+	if (tve->enabled) {
+		clk_enable(tve->clk);
+
+		/* Setup cable detect */
+		if (tve->revision == 1)
+			writel(0x01067701,
+				tve->base + tve->regs->tve_cd_cont_reg);
+		else
+			writel(0x00770601,
+				tve->base + tve->regs->tve_cd_cont_reg);
+
+		if (valid_mode(tve->cur_mode)) {
+			mode = tve->cur_mode;
+			tve_disable(tve);
+			tve->cur_mode = TVOUT_FMT_OFF;
+			tve_setup(tve, mode);
+		}
+		tve_enable(tve);
+	}
+
+	return 0;
+}
+
+int tve_fb_setup(struct tve_data *tve, struct fb_info *fbi)
+{
+	int mode;
+
+	fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var,
+			&fbi->modelist);
+
+	if (!fbi->mode) {
+		dev_warn(&tve->pdev->dev, "TVE: can not find mode for xres=%d, yres=%d\n",
+				fbi->var.xres, fbi->var.yres);
+		tve_disable(tve);
+		tve->cur_mode = TVOUT_FMT_OFF;
+		return 0;
+	}
+
+	dev_dbg(&tve->pdev->dev, "TVE: fb mode change event: xres=%d, yres=%d\n",
+			fbi->mode->xres, fbi->mode->yres);
+
+	mode = get_video_mode(fbi);
+	if (mode != TVOUT_FMT_OFF) {
+		tve_disable(tve);
+		tve_setup(tve, mode);
+		tve_enable(tve);
+	} else {
+		tve_disable(tve);
+		tve_setup(tve, mode);
+	}
+
+	return 0;
+}
+
+int tve_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct tve_data *tve = container_of(nb, struct tve_data, nb);
+	struct fb_event *event = v;
+	struct fb_info *fbi = event->info;
+
+	/* only work for ipu0 di1*/
+	if (strcmp(fbi->fix.id, "DISP3 BG - DI1"))
+		return 0;
+
+	switch (val) {
+	case FB_EVENT_PREMODE_CHANGE:
+	{
+		tve_fb_setup(tve, fbi);
+		break;
+	}
+	case FB_EVENT_BLANK:
+		if (fbi->mode == NULL)
+			return 0;
+
+		dev_dbg(&tve->pdev->dev, "TVE: fb blank event\n");
+
+		if (*((int *)event->data) == FB_BLANK_UNBLANK) {
+			int mode;
+			mode = get_video_mode(fbi);
+			if (mode != TVOUT_FMT_OFF) {
+				if (tve->cur_mode != mode) {
+					tve_disable(tve);
+					tve_setup(tve, mode);
+				}
+				tve_enable(tve);
+			} else
+				tve_setup(tve, mode);
+		} else
+			tve_disable(tve);
+		break;
+	case FB_EVENT_SUSPEND:
+		tve_suspend(tve);
+		break;
+	case FB_EVENT_RESUME:
+		tve_resume(tve, fbi);
+		break;
+	}
+	return 0;
+}
+
+static ssize_t show_headphone(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct tve_data *tve = dev_get_drvdata(dev);
+	int detect;
+
+	if (!tve->enabled) {
+		strcpy(buf, "tve power off\n");
+		return strlen(buf);
+	}
+
+	detect = tve_update_detect_status(tve);
+
+	if (detect == 0)
+		strcpy(buf, "none\n");
+	else if (detect == 1)
+		strcpy(buf, "cvbs\n");
+	else if (detect == 2)
+		strcpy(buf, "headset\n");
+	else if (detect == 3)
+		strcpy(buf, "component\n");
+	else
+		strcpy(buf, "svideo\n");
+
+	return strlen(buf);
+}
+
+static DEVICE_ATTR(headphone, S_IRUGO | S_IWUSR, show_headphone, NULL);
+
+static int _tve_get_revision(struct tve_data *tve)
+{
+	u32 conf_reg;
+	u32 rev = 0;
+
+	/* find out TVE rev based on the base addr default value
+	 * can be used at the init/probe ONLY */
+	conf_reg = readl(tve->base);
+	switch (conf_reg) {
+	case 0x00842000:
+		rev = 1;
+		break;
+	case 0x00100000:
+		rev = 2;
+		break;
+	}
+	return rev;
+}
+
+static int tve_drv_init(struct mxc_dispdrv_entry *disp, bool vga)
+{
+	int ret;
+	struct tve_data *tve = mxc_dispdrv_getdata(disp);
+	struct mxc_dispdrv_setting *setting = mxc_dispdrv_getsetting(disp);
+	struct fsl_mxc_tve_platform_data *plat_data
+			= tve->pdev->dev.platform_data;
+	struct resource *res;
+	struct fb_videomode *modedb;
+	int modedb_sz;
+	u32 conf_reg;
+
+	if (tve->inited == true)
+		return -ENODEV;
+
+	/*tve&vga only use ipu0 and di1*/
+	setting->dev_id = 0;
+	setting->disp_id = 1;
+
+	res = platform_get_resource(tve->pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		ret = -ENOMEM;
+		goto get_res_failed;
+	}
+
+	tve->irq = platform_get_irq(tve->pdev, 0);
+	if (tve->irq < 0) {
+		ret = tve->irq;
+		goto get_irq_failed;
+	}
+
+	tve->base = ioremap(res->start, res->end - res->start);
+	if (!tve->base) {
+		ret = -ENOMEM;
+		goto ioremap_failed;
+	}
+
+	ret = device_create_file(&tve->pdev->dev, &dev_attr_headphone);
+	if (ret < 0)
+		goto dev_file_create_failed;
+
+	tve->dac_reg = regulator_get(&tve->pdev->dev, plat_data->dac_reg);
+	if (!IS_ERR(tve->dac_reg)) {
+		regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
+		regulator_enable(tve->dac_reg);
+	}
+	tve->dig_reg = regulator_get(&tve->pdev->dev, plat_data->dig_reg);
+	if (!IS_ERR(tve->dig_reg)) {
+		regulator_set_voltage(tve->dig_reg, 1250000, 1250000);
+		regulator_enable(tve->dig_reg);
+	}
+
+	tve->clk = clk_get(&tve->pdev->dev, "tve_clk");
+	if (IS_ERR(tve->clk)) {
+		ret = PTR_ERR(tve->clk);
+		goto get_tveclk_failed;
+	}
+	tve->di_clk = clk_get(NULL, "ipu1_di1_clk");
+	if (IS_ERR(tve->di_clk)) {
+		ret = PTR_ERR(tve->di_clk);
+		goto get_diclk_failed;
+	}
+
+	clk_set_rate(tve->clk, 216000000);
+	clk_set_parent(tve->di_clk, tve->clk);
+	clk_enable(tve->clk);
+
+	tve->revision = _tve_get_revision(tve);
+	if (tve->revision == 1) {
+		tve->regs = &tve_regs_v1;
+		tve->reg_fields = &tve_reg_fields_v1;
+	} else {
+		tve->regs = &tve_regs_v2;
+		tve->reg_fields = &tve_reg_fields_v2;
+	}
+
+	if (vga && cpu_is_mx53()) {
+		setting->if_fmt = IPU_PIX_FMT_GBR24;
+		modedb = video_modes_vga;
+		modedb_sz = vga_modedb_sz;
+	} else {
+		setting->if_fmt = IPU_PIX_FMT_YUV444;
+		if (tve->revision == 1) {
+			modedb = video_modes_tve;
+			modedb_sz = 3;
+		} else {
+			modedb = video_modes_tve;
+			modedb_sz = tve_modedb_sz;
+		}
+	}
+
+	fb_videomode_to_modelist(modedb, modedb_sz, &setting->fbi->modelist);
+
+	/* must use spec video mode defined by driver */
+	ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
+				modedb, modedb_sz, NULL, setting->default_bpp);
+	if (ret != 1)
+		fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
+
+	ret = request_irq(tve->irq, tve_detect_handler, 0, tve->pdev->name, tve);
+	if (ret < 0)
+		goto req_irq_failed;
+
+	/* Setup cable detect, for YPrPb mode, default use channel#-1 for Y */
+	INIT_DELAYED_WORK(&tve->cd_work, cd_work_func);
+	if (tve->revision == 1)
+		writel(0x01067701, tve->base + tve->regs->tve_cd_cont_reg);
+	else
+		writel(0x00770601, tve->base + tve->regs->tve_cd_cont_reg);
+
+	conf_reg = 0;
+	writel(conf_reg, tve->base + tve->regs->tve_com_conf_reg);
+
+	writel(0x00000000, tve->base + tve->regs->tve_mv_cont_reg - 4 * 5);
+	writel(0x00000000, tve->base + tve->regs->tve_mv_cont_reg - 4 * 4);
+	writel(0x00000000, tve->base + tve->regs->tve_mv_cont_reg - 4 * 3);
+	writel(0x00000000, tve->base + tve->regs->tve_mv_cont_reg - 4 * 2);
+	writel(0x00000000, tve->base + tve->regs->tve_mv_cont_reg - 4);
+	writel(0x00000000, tve->base + tve->regs->tve_mv_cont_reg);
+
+	clk_disable(tve->clk);
+
+	tve->nb.notifier_call = tve_fb_event;
+	ret = fb_register_client(&tve->nb);
+	if (ret < 0)
+		goto reg_fbclient_failed;
+
+	dev_set_drvdata(&tve->pdev->dev, tve);
+
+	spin_lock_init(&tve->tve_lock);
+
+	tve->inited = true;
+
+	return 0;
+
+reg_fbclient_failed:
+	free_irq(tve->irq, tve->pdev);
+req_irq_failed:
+get_diclk_failed:
+get_tveclk_failed:
+	device_remove_file(&tve->pdev->dev, &dev_attr_headphone);
+dev_file_create_failed:
+	iounmap(tve->base);
+ioremap_failed:
+get_irq_failed:
+get_res_failed:
+	return ret;
+
+}
+
+static int tvout_init(struct mxc_dispdrv_entry *disp)
+{
+	return tve_drv_init(disp, 0);
+}
+
+static int vga_init(struct mxc_dispdrv_entry *disp)
+{
+	return tve_drv_init(disp, 1);
+}
+
+void tvout_deinit(struct mxc_dispdrv_entry *disp)
+{
+	struct tve_data *tve = mxc_dispdrv_getdata(disp);
+
+	if (tve->enabled)
+		clk_disable(tve->clk);
+
+	fb_unregister_client(&tve->nb);
+	free_irq(tve->irq, tve->pdev);
+	device_remove_file(&tve->pdev->dev, &dev_attr_headphone);
+	iounmap(tve->base);
+}
+
+static struct mxc_dispdrv_driver tve_drv = {
+	.name 	= DISPDRV_TVE,
+	.init  	= tvout_init,
+	.deinit = tvout_deinit,
+};
+
+static struct mxc_dispdrv_driver vga_drv = {
+	.name 	= DISPDRV_VGA,
+	.init 	= vga_init,
+	.deinit	= tvout_deinit,
+};
+
+static int tve_dispdrv_init(struct tve_data *tve)
+{
+	tve->disp_tve = mxc_dispdrv_register(&tve_drv);
+	mxc_dispdrv_setdata(tve->disp_tve, tve);
+	tve->disp_vga = mxc_dispdrv_register(&vga_drv);
+	mxc_dispdrv_setdata(tve->disp_vga, tve);
+	return 0;
+}
+
+static void tve_dispdrv_deinit(struct tve_data *tve)
+{
+	mxc_dispdrv_unregister(tve->disp_tve);
+	mxc_dispdrv_unregister(tve->disp_vga);
+}
+
+static int tve_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct tve_data *tve;
+
+	tve = kzalloc(sizeof(struct tve_data), GFP_KERNEL);
+	if (!tve) {
+		ret = -ENOMEM;
+		goto alloc_failed;
+	}
+
+	tve->pdev = pdev;
+	ret = tve_dispdrv_init(tve);
+	if (ret < 0)
+		goto dispdrv_init_failed;
+
+	dev_set_drvdata(&pdev->dev, tve);
+
+	return 0;
+
+dispdrv_init_failed:
+	kfree(tve);
+alloc_failed:
+	return ret;
+}
+
+static int tve_remove(struct platform_device *pdev)
+{
+	struct tve_data *tve = dev_get_drvdata(&pdev->dev);
+
+	tve_dispdrv_deinit(tve);
+	kfree(tve);
+	return 0;
+}
+
+static struct platform_driver tve_driver = {
+	.driver = {
+		   .name = "mxc_tve",
+		   },
+	.probe = tve_probe,
+	.remove = tve_remove,
+};
+
+static int __init tve_init(void)
+{
+	return platform_driver_register(&tve_driver);
+}
+
+static void __exit tve_exit(void)
+{
+	platform_driver_unregister(&tve_driver);
+}
+
+module_init(tve_init);
+module_exit(tve_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX TV encoder driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 79fd606b7cd..e2a3c0518d0 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1260,6 +1260,11 @@ config WDTPCI
 	  To compile this driver as a module, choose M here: the
 	  module will be called wdt_pci.
 
+config DA9052_WATCHDOG
+	tristate "Dialog DA9052 Watchdog"
+	depends on PMIC_DIALOG
+	help
+	  Support for the watchdog in the DA9052 PMIC.
 #
 # USB-based Watchdog Cards
 #
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index fe893e91935..b21fba58dbf 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -166,3 +166,4 @@ obj-$(CONFIG_WM831X_WATCHDOG) += wm831x_wdt.o
 obj-$(CONFIG_WM8350_WATCHDOG) += wm8350_wdt.o
 obj-$(CONFIG_MAX63XX_WATCHDOG) += max63xx_wdt.o
 obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
+obj-$(CONFIG_DA9052_WATCHDOG) += da9052_wdt.o
diff --git a/drivers/watchdog/da9052_wdt.c b/drivers/watchdog/da9052_wdt.c
new file mode 100644
index 00000000000..cf7f3875df3
--- /dev/null
+++ b/drivers/watchdog/da9052_wdt.c
@@ -0,0 +1,542 @@
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/uaccess.h>
+#include <linux/jiffies.h>
+#include <linux/platform_device.h>
+#include <linux/time.h>
+#include <linux/watchdog.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/wdt.h>
+
+#define DRIVER_NAME "da9052-wdt"
+
+#define	DA9052_STROBING_FILTER_ENABLE		0x0001
+#define	DA9052_STROBING_FILTER_DISABLE		0x0002
+#define	DA9052_SET_STROBING_MODE_MANUAL		0x0004
+#define	DA9052_SET_STROBING_MODE_AUTO		0x0008
+
+#define KERNEL_MODULE				0
+#define ENABLE					1
+#define DISABLE					0
+
+static u8 sm_strobe_filter_flag = DISABLE;
+static u8 sm_strobe_mode_flag = DA9052_STROBE_MANUAL;
+static u32 sm_mon_interval = DA9052_ADC_TWDMIN_TIME;
+static u8 sm_str_req = DISABLE;
+static u8 da9052_sm_scale = DA9052_WDT_DISABLE;
+module_param(sm_strobe_filter_flag,  byte, 0);
+MODULE_PARM_DESC(sm_strobe_filter_flag,
+		"DA9052 SM driver strobe filter flag default = DISABLE");
+
+module_param(sm_strobe_mode_flag, byte, 0);
+MODULE_PARM_DESC(sm_strobe_mode_flag,
+		"DA9052 SM driver watchdog strobing mode default"\
+		"= DA9052_STROBE_MANUAL");
+
+module_param(da9052_sm_scale, byte, 0);
+MODULE_PARM_DESC(da9052_sm_scale,
+		"DA9052 SM driver scaling value used to calculate the"\
+		"time for the strobing  filter default = 0");
+
+module_param(sm_str_req, byte, 0);
+MODULE_PARM_DESC(sm_str_req,
+		"DA9052 SM driver strobe request flag default = DISABLE");
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout,
+		"Watchdog cannot be stopped once started (default="
+		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+static struct timer_list *monitoring_timer;
+
+struct da9052_wdt {
+	struct platform_device *pdev;
+	struct da9052 *da9052;
+};
+static struct miscdevice da9052_wdt_miscdev;
+static unsigned long da9052_wdt_users;
+static int da9052_wdt_expect_close;
+
+static struct da9052_wdt *get_wdt_da9052(void)
+{
+	/*return dev_get_drvdata(da9052_wdt_miscdev.parent);*/
+	return platform_get_drvdata
+			(to_platform_device(da9052_wdt_miscdev.parent));
+}
+
+void start_strobing(struct work_struct *work)
+{
+	struct da9052_ssc_msg msg;
+	int ret;
+	struct da9052_wdt *wdt = get_wdt_da9052();
+
+
+	if (NULL == wdt) {
+		mod_timer(monitoring_timer, jiffies + sm_mon_interval);
+		return;
+	}
+	msg.addr = DA9052_CONTROLD_REG;
+	msg.data = 0;
+	da9052_lock(wdt->da9052);
+	ret = wdt->da9052->read(wdt->da9052, &msg);
+	if (ret) {
+		da9052_unlock(wdt->da9052);
+		return;
+	}
+	da9052_unlock(wdt->da9052);
+
+	msg.data = (msg.data | DA9052_CONTROLD_WATCHDOG);
+	da9052_lock(wdt->da9052);
+	ret = wdt->da9052->write(wdt->da9052, &msg);
+	if (ret) {
+		da9052_unlock(wdt->da9052);
+		return;
+	}
+	da9052_unlock(wdt->da9052);
+
+	sm_str_req = DISABLE;
+
+	mod_timer(monitoring_timer, jiffies + sm_mon_interval);
+	return;
+}
+
+
+void timer_callback(void)
+{
+	if (((sm_strobe_mode_flag) &&
+		(sm_strobe_mode_flag == DA9052_STROBE_MANUAL)) ||
+		(sm_strobe_mode_flag == DA9052_STROBE_AUTO)) {
+		schedule_work(&strobing_action);
+	} else {
+		if (sm_strobe_mode_flag == DA9052_STROBE_MANUAL) {
+			mod_timer(monitoring_timer, jiffies +
+			sm_mon_interval);
+		}
+	}
+}
+
+static int da9052_sm_hw_init(struct da9052_wdt *wdt)
+{
+	/* Create timer structure */
+	monitoring_timer = kzalloc(sizeof(struct timer_list), GFP_KERNEL);
+	if (!monitoring_timer)
+		return -ENOMEM;
+
+	init_timer(monitoring_timer);
+	monitoring_timer->expires = jiffies + sm_mon_interval;
+	monitoring_timer->function = (void *)&timer_callback;
+
+	sm_strobe_filter_flag = DA9052_SM_STROBE_CONF;
+	sm_strobe_mode_flag = DA9052_STROBE_MANUAL;
+
+	return 0;
+}
+
+static int da9052_sm_hw_deinit(struct da9052_wdt *wdt)
+{
+	struct da9052_ssc_msg msg;
+	int ret;
+
+	if (monitoring_timer != NULL)
+		del_timer(monitoring_timer);
+	kfree(monitoring_timer);
+
+	msg.addr = DA9052_CONTROLD_REG;
+	msg.data = 0;
+
+	da9052_lock(wdt->da9052);
+	ret = wdt->da9052->read(wdt->da9052, &msg);
+	if (ret)
+		goto ssc_err;
+	da9052_unlock(wdt->da9052);
+
+	msg.data = (msg.data & ~(DA9052_CONTROLD_TWDSCALE));
+	da9052_lock(wdt->da9052);
+	ret = wdt->da9052->write(wdt->da9052, &msg);
+	if (ret)
+		goto ssc_err;
+	da9052_unlock(wdt->da9052);
+
+	return 0;
+ssc_err:
+	da9052_unlock(wdt->da9052);
+	return -EIO;
+}
+
+s32 da9052_sm_set_strobing_filter(struct da9052_wdt *wdt,
+				u8 strobing_filter_state)
+{
+	struct da9052_ssc_msg msg;
+	int ret = 0;
+
+	msg.addr = DA9052_CONTROLD_REG;
+	msg.data = 0;
+	da9052_lock(wdt->da9052);
+	ret = wdt->da9052->read(wdt->da9052, &msg);
+	if (ret)
+		goto ssc_err;
+	da9052_unlock(wdt->da9052);
+
+	msg.data = (msg.data & DA9052_CONTROLD_TWDSCALE);
+
+	if (strobing_filter_state == ENABLE) {
+		sm_strobe_filter_flag = ENABLE;
+		if (DA9052_WDT_DISABLE == msg.data) {
+			sm_str_req = DISABLE;
+			del_timer(monitoring_timer);
+			return 0;
+		}
+		if (DA9052_SCALE_64X == msg.data)
+			sm_mon_interval = msecs_to_jiffies(DA9052_X64_WINDOW);
+		else if (DA9052_SCALE_32X == msg.data)
+			sm_mon_interval = msecs_to_jiffies(DA9052_X32_WINDOW);
+		else if (DA9052_SCALE_16X == msg.data)
+			sm_mon_interval = msecs_to_jiffies(DA9052_X16_WINDOW);
+		else if (DA9052_SCALE_8X == msg.data)
+			sm_mon_interval = msecs_to_jiffies(DA9052_X8_WINDOW);
+		else if (DA9052_SCALE_4X == msg.data)
+			sm_mon_interval = msecs_to_jiffies(DA9052_X4_WINDOW);
+		else if (DA9052_SCALE_2X == msg.data)
+			sm_mon_interval = msecs_to_jiffies(DA9052_X2_WINDOW);
+		else
+			sm_mon_interval = msecs_to_jiffies(DA9052_X1_WINDOW);
+
+	} else if (strobing_filter_state == DISABLE) {
+		sm_strobe_filter_flag = DISABLE;
+		sm_mon_interval = msecs_to_jiffies(DA9052_ADC_TWDMIN_TIME);
+		if (DA9052_WDT_DISABLE == msg.data) {
+			sm_str_req = DISABLE;
+			del_timer(monitoring_timer);
+			return 0;
+		}
+	} else {
+		return STROBING_FILTER_ERROR;
+	}
+	mod_timer(monitoring_timer, jiffies + sm_mon_interval);
+
+	return 0;
+ssc_err:
+	da9052_unlock(wdt->da9052);
+	return -EIO;
+}
+
+int da9052_sm_set_strobing_mode(u8 strobing_mode_state)
+{
+	if (strobing_mode_state == DA9052_STROBE_AUTO)
+		sm_strobe_mode_flag = DA9052_STROBE_AUTO;
+	else if (strobing_mode_state == DA9052_STROBE_MANUAL)
+		sm_strobe_mode_flag = DA9052_STROBE_MANUAL;
+	else
+		return STROBING_MODE_ERROR;
+
+		return 0;
+}
+
+int da9052_sm_strobe_wdt(void)
+{
+	sm_str_req = ENABLE;
+	return 0;
+}
+
+s32 da9052_sm_set_wdt(struct da9052_wdt *wdt, u8 wdt_scaling)
+{
+	struct da9052_ssc_msg msg;
+	int ret = 0;
+
+
+	if (wdt_scaling > DA9052_SCALE_64X)
+		return INVALID_SCALING_VALUE;
+
+	msg.addr = DA9052_CONTROLD_REG;
+	msg.data = 0;
+	da9052_lock(wdt->da9052);
+	ret = wdt->da9052->read(wdt->da9052, &msg);
+	if (ret)
+		goto ssc_err;
+	da9052_unlock(wdt->da9052);
+
+	if (!((DA9052_WDT_DISABLE == (msg.data & DA9052_CONTROLD_TWDSCALE)) &&
+	    (DA9052_WDT_DISABLE == wdt_scaling))) {
+		msg.data = (msg.data & ~(DA9052_CONTROLD_TWDSCALE));
+		msg.addr = DA9052_CONTROLD_REG;
+
+
+		da9052_lock(wdt->da9052);
+		ret = wdt->da9052->write(wdt->da9052, &msg);
+		if (ret)
+			goto ssc_err;
+		da9052_unlock(wdt->da9052);
+
+		msleep(1);
+		da9052_lock(wdt->da9052);
+		ret = wdt->da9052->read(wdt->da9052, &msg);
+		if (ret)
+			goto ssc_err;
+		da9052_unlock(wdt->da9052);
+
+
+		msg.data |= wdt_scaling;
+
+		da9052_lock(wdt->da9052);
+		ret = wdt->da9052->write(wdt->da9052, &msg);
+		if (ret)
+			goto ssc_err;
+		da9052_unlock(wdt->da9052);
+
+		sm_str_req = DISABLE;
+		if (DA9052_WDT_DISABLE == wdt_scaling) {
+			del_timer(monitoring_timer);
+			return 0;
+		}
+		if (sm_strobe_filter_flag == ENABLE) {
+			if (DA9052_SCALE_64X == wdt_scaling) {
+				sm_mon_interval =
+					msecs_to_jiffies(DA9052_X64_WINDOW);
+			} else if (DA9052_SCALE_32X == wdt_scaling) {
+				sm_mon_interval =
+					msecs_to_jiffies(DA9052_X32_WINDOW);
+			} else if (DA9052_SCALE_16X == wdt_scaling) {
+				sm_mon_interval =
+					msecs_to_jiffies(DA9052_X16_WINDOW);
+			} else if (DA9052_SCALE_8X == wdt_scaling) {
+				sm_mon_interval =
+					msecs_to_jiffies(DA9052_X8_WINDOW);
+			} else if (DA9052_SCALE_4X == wdt_scaling) {
+				sm_mon_interval =
+					msecs_to_jiffies(DA9052_X4_WINDOW);
+			} else if (DA9052_SCALE_2X == wdt_scaling) {
+				sm_mon_interval =
+					msecs_to_jiffies(DA9052_X2_WINDOW);
+			} else {
+				sm_mon_interval =
+					msecs_to_jiffies(DA9052_X1_WINDOW);
+			}
+		} else {
+			sm_mon_interval = msecs_to_jiffies(
+						DA9052_ADC_TWDMIN_TIME);
+		}
+		mod_timer(monitoring_timer, jiffies + sm_mon_interval);
+	}
+
+	return 0;
+ssc_err:
+	da9052_unlock(wdt->da9052);
+	return -EIO;
+}
+
+static int da9052_wdt_open(struct inode *inode, struct file *file)
+{
+	struct da9052_wdt *wdt = get_wdt_da9052();
+	int ret;
+	printk(KERN_INFO"IN WDT OPEN\n");
+
+	if (!wdt) {
+		printk(KERN_INFO"Returning no device\n");
+		return -ENODEV;
+	}
+	printk(KERN_INFO"IN WDT OPEN 1\n");
+
+	if (test_and_set_bit(0, &da9052_wdt_users))
+		return -EBUSY;
+
+	ret = da9052_sm_hw_init(wdt);
+	if (ret != 0) {
+		printk(KERN_ERR "Watchdog hw init failed\n");
+		return ret;
+	}
+
+	return nonseekable_open(inode, file);
+}
+
+static int da9052_wdt_release(struct inode *inode, struct file *file)
+{
+	struct da9052_wdt *wdt = get_wdt_da9052();
+
+	if (da9052_wdt_expect_close == 42)
+		da9052_sm_hw_deinit(wdt);
+	else
+		da9052_sm_strobe_wdt();
+	da9052_wdt_expect_close = 0;
+	clear_bit(0, &da9052_wdt_users);
+	return 0;
+}
+
+static ssize_t da9052_wdt_write(struct file *file,
+				const char __user *data, size_t count,
+				loff_t *ppos)
+{
+	size_t i;
+
+	if (count) {
+		if (!nowayout) {
+			/* In case it was set long ago */
+			da9052_wdt_expect_close = 0;
+			for (i = 0; i != count; i++) {
+				char c;
+				if (get_user(c, data + i))
+					return -EFAULT;
+				if (c == 'V')
+					da9052_wdt_expect_close = 42;
+			}
+		}
+		da9052_sm_strobe_wdt();
+	}
+	return count;
+}
+
+static struct watchdog_info da9052_wdt_info = {
+	.options	= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+	.identity	= "DA9052_SM Watchdog",
+};
+
+static long da9052_wdt_ioctl(struct file *file, unsigned int cmd,
+				unsigned long arg)
+{
+	struct da9052_wdt *wdt = get_wdt_da9052();
+	void __user *argp = (void __user *)arg;
+	int __user *p = argp;
+	unsigned char new_value;
+
+	switch (cmd) {
+
+	case WDIOC_GETSUPPORT:
+		return copy_to_user(argp, &da9052_wdt_info,
+			sizeof(da9052_wdt_info)) ? -EFAULT : 0;
+	case WDIOC_GETSTATUS:
+	case WDIOC_GETBOOTSTATUS:
+		return put_user(0, p);
+	case WDIOC_SETOPTIONS:
+		if (get_user(new_value, p))
+			return -EFAULT;
+		if (new_value & DA9052_STROBING_FILTER_ENABLE)
+			da9052_sm_set_strobing_filter(wdt, ENABLE);
+		if (new_value & DA9052_STROBING_FILTER_DISABLE)
+			da9052_sm_set_strobing_filter(wdt, DISABLE);
+		if (new_value & DA9052_SET_STROBING_MODE_MANUAL)
+			da9052_sm_set_strobing_mode(DA9052_STROBE_MANUAL);
+		if (new_value & DA9052_SET_STROBING_MODE_AUTO)
+			da9052_sm_set_strobing_mode(DA9052_STROBE_AUTO);
+		return 0;
+	case WDIOC_KEEPALIVE:
+		if (da9052_sm_strobe_wdt())
+			return -EFAULT;
+		else
+			return 0;
+	case WDIOC_SETTIMEOUT:
+		if (get_user(new_value, p))
+			return -EFAULT;
+		da9052_sm_scale = new_value;
+		if (da9052_sm_set_wdt(wdt, da9052_sm_scale))
+			return -EFAULT;
+	case WDIOC_GETTIMEOUT:
+		return put_user(sm_mon_interval, p);
+	default:
+		return -ENOTTY;
+	}
+	return 0;
+}
+
+static const struct file_operations da9052_wdt_fops = {
+	.owner          = THIS_MODULE,
+	.llseek		= no_llseek,
+	.unlocked_ioctl	= da9052_wdt_ioctl,
+	.write		= da9052_wdt_write,
+	.open           = da9052_wdt_open,
+	.release        = da9052_wdt_release,
+};
+
+static struct miscdevice da9052_wdt_miscdev = {
+	.minor		= 255,
+	.name		= "da9052-wdt",
+	.fops		= &da9052_wdt_fops,
+};
+
+static int __devinit da9052_sm_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct da9052_wdt *wdt;
+	struct da9052_ssc_msg msg;
+
+	wdt = kzalloc(sizeof(*wdt), GFP_KERNEL);
+	if (!wdt)
+		return -ENOMEM;
+
+	wdt->da9052 = dev_get_drvdata(pdev->dev.parent);
+	platform_set_drvdata(pdev, wdt);
+
+	msg.addr = DA9052_CONTROLD_REG;
+	msg.data = 0;
+
+	da9052_lock(wdt->da9052);
+	ret = wdt->da9052->read(wdt->da9052, &msg);
+	if (ret) {
+		da9052_unlock(wdt->da9052);
+		goto err_ssc_comm;
+	}
+	printk(KERN_INFO"DA9052 SM probe - 0\n");
+
+	msg.data = (msg.data & ~(DA9052_CONTROLD_TWDSCALE));
+	ret = wdt->da9052->write(wdt->da9052, &msg);
+	if (ret) {
+		da9052_unlock(wdt->da9052);
+		goto err_ssc_comm;
+	}
+	da9052_unlock(wdt->da9052);
+
+	da9052_wdt_miscdev.parent = &pdev->dev;
+
+	ret = misc_register(&da9052_wdt_miscdev);
+	if (ret != 0) {
+		platform_set_drvdata(pdev, NULL);
+		kfree(wdt);
+		return -EFAULT;
+	}
+	return 0;
+err_ssc_comm:
+	platform_set_drvdata(pdev, NULL);
+	kfree(wdt);
+	return -EIO;
+}
+
+static int __devexit da9052_sm_remove(struct platform_device *dev)
+{
+	misc_deregister(&da9052_wdt_miscdev);
+
+	return 0;
+}
+
+static struct platform_driver da9052_sm_driver = {
+	.probe		= da9052_sm_probe,
+	.remove		= __devexit_p(da9052_sm_remove),
+	.driver		= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init da9052_sm_init(void)
+{
+	return platform_driver_register(&da9052_sm_driver);
+}
+module_init(da9052_sm_init);
+
+static void __exit da9052_sm_exit(void)
+{
+	platform_driver_unregister(&da9052_sm_driver);
+}
+module_exit(da9052_sm_exit);
+
+MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
+MODULE_DESCRIPTION("DA9052 SM Device Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/firmware/Makefile b/firmware/Makefile
index 5f43bfba3c7..66d0e990285 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -142,6 +142,12 @@ fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
 fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
 fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
 
+ifdef CONFIG_IMX_SDMA
+fw-shipped-$(CONFIG_SOC_IMX50) += imx/sdma/sdma-imx50-to1.bin
+fw-shipped-$(CONFIG_SOC_IMX51) += imx/sdma/sdma-imx51-to3.bin
+fw-shipped-$(CONFIG_SOC_IMX53) += imx/sdma/sdma-imx53-to1.bin
+endif
+
 fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
 
 # Directories which we _might_ need to create, so we have a rule for them.
@@ -166,11 +172,12 @@ quiet_cmd_fwbin = MK_FW   $@
 		  ASM_WORD=$(if $(CONFIG_64BIT),.quad,.long);		     \
 		  ASM_ALIGN=$(if $(CONFIG_64BIT),3,2);			     \
 		  PROGBITS=$(if $(CONFIG_ARM),%,@)progbits;		     \
+		  FWPATH=$(if $(KBUILD_SRC),$(srctree)/)$(2);		     \
 		  echo "/* Generated by firmware/Makefile */"		> $@;\
 		  echo "    .section .rodata"				>>$@;\
 		  echo "    .p2align $${ASM_ALIGN}"			>>$@;\
 		  echo "_fw_$${FWSTR}_bin:"				>>$@;\
-		  echo "    .incbin \"$(2)\""				>>$@;\
+		  echo "    .incbin \"$${FWPATH}\""			>>$@;\
 		  echo "_fw_end:"					>>$@;\
 		  echo "   .section .rodata.str,\"aMS\",$${PROGBITS},1"	>>$@;\
 		  echo "    .p2align $${ASM_ALIGN}"			>>$@;\
diff --git a/firmware/imx/sdma/sdma-imx25-to1.bin b/firmware/imx/sdma/sdma-imx25-to1.bin
new file mode 100644
index 00000000000..7514e09fea7
--- /dev/null
+++ b/firmware/imx/sdma/sdma-imx25-to1.bin
diff --git a/firmware/imx/sdma/sdma-imx31-to1.bin b/firmware/imx/sdma/sdma-imx31-to1.bin
new file mode 100644
index 00000000000..7c3417d07e0
--- /dev/null
+++ b/firmware/imx/sdma/sdma-imx31-to1.bin
diff --git a/firmware/imx/sdma/sdma-imx31-to2.bin b/firmware/imx/sdma/sdma-imx31-to2.bin
new file mode 100644
index 00000000000..7ff9c75f4ca
--- /dev/null
+++ b/firmware/imx/sdma/sdma-imx31-to2.bin
diff --git a/firmware/imx/sdma/sdma-imx35-to1.bin b/firmware/imx/sdma/sdma-imx35-to1.bin
new file mode 100644
index 00000000000..be34cb7faf6
--- /dev/null
+++ b/firmware/imx/sdma/sdma-imx35-to1.bin
diff --git a/firmware/imx/sdma/sdma-imx35-to2.bin b/firmware/imx/sdma/sdma-imx35-to2.bin
new file mode 100644
index 00000000000..cfe72272ae8
--- /dev/null
+++ b/firmware/imx/sdma/sdma-imx35-to2.bin
diff --git a/firmware/imx/sdma/sdma-imx50-to1.bin b/firmware/imx/sdma/sdma-imx50-to1.bin
new file mode 100644
index 00000000000..50be5e828bb
--- /dev/null
+++ b/firmware/imx/sdma/sdma-imx50-to1.bin
diff --git a/firmware/imx/sdma/sdma-imx51-to3.bin b/firmware/imx/sdma/sdma-imx51-to3.bin
new file mode 100644
index 00000000000..c54815a9793
--- /dev/null
+++ b/firmware/imx/sdma/sdma-imx51-to3.bin
diff --git a/firmware/imx/sdma/sdma-imx53-to1.bin b/firmware/imx/sdma/sdma-imx53-to1.bin
new file mode 100644
index 00000000000..68e2c1a5ca1
--- /dev/null
+++ b/firmware/imx/sdma/sdma-imx53-to1.bin
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 1d6836c498d..a67fe1e2b02 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -549,6 +549,8 @@ struct fb_cursor_user {
 #define FB_EVENT_FB_UNBIND              0x0E
 /*      CONSOLE-SPECIFIC: remap all consoles to new fb - for vga switcheroo */
 #define FB_EVENT_REMAP_ALL_CONSOLE      0x0F
+/*	PRE MODE CHANGE added by fsl */
+#define FB_EVENT_PREMODE_CHANGE		0x10
 
 struct fb_event {
 	struct fb_info *info;
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index fffdf00f87b..cb624eaff19 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -50,6 +50,15 @@ enum fsl_usb2_operating_modes {
 	FSL_USB2_DR_OTG,
 };
 
+/* this used for usb port type */
+enum fsl_usb2_modes {
+	FSL_USB_DR_HOST,
+	FSL_USB_DR_DEVICE,
+	FSL_USB_MPH_HOST1,
+	FSL_USB_MPH_HOST2,
+	FSL_USB_UNKNOWN, /* unkonwn status */
+};
+
 enum fsl_usb2_phy_modes {
 	FSL_USB2_PHY_NONE,
 	FSL_USB2_PHY_ULPI,
@@ -58,9 +67,100 @@ enum fsl_usb2_phy_modes {
 	FSL_USB2_PHY_SERIAL,
 };
 
+enum usb_wakeup_event {
+        WAKEUP_EVENT_INVALID,
+        WAKEUP_EVENT_VBUS,
+        WAKEUP_EVENT_ID,
+        WAKEUP_EVENT_DPDM, /* for remote wakeup */
+};
+
 struct clk;
 struct platform_device;
 
+#ifdef CONFIG_USB_EHCI_ARC
+#include <linux/wait.h>
+#include <linux/mutex.h>
+#include <linux/completion.h>
+
+struct fsl_usb2_wakeup_platform_data;
+
+struct fsl_usb2_platform_data {
+	/* board specific information */
+	enum fsl_usb2_operating_modes	operating_mode;
+	enum fsl_usb2_phy_modes		phy_mode;
+	unsigned int			port_enables;
+	unsigned int			workaround;
+
+	int		(*init)(struct platform_device *);
+	void		(*exit)(struct platform_device *);
+	void __iomem	*regs;		/* ioremap'd register base */
+	struct clk	*clk;
+	unsigned	big_endian_mmio:1;
+	unsigned	big_endian_desc:1;
+	unsigned	es:1;		/* need USBMODE:ES */
+	unsigned	le_setup_buf:1;
+	unsigned	have_sysif_regs:1;
+	unsigned	invert_drvvbus:1;
+	unsigned	invert_pwr_fault:1;
+
+	/* Freescale private */
+	char		*name;
+	u32		phy_regs;	/* usb phy register base */
+	u32 		xcvr_type;	/* PORTSC_PTS_* */
+	char 		*transceiver;	/* transceiver name */
+	unsigned 	power_budget;	/* for hcd->power_budget */
+	u32		id_gpio;
+
+	struct fsl_xcvr_ops *xcvr_ops;
+	struct fsl_xcvr_power *xcvr_pwr;
+	int (*gpio_usb_active) (void);
+	void (*gpio_usb_inactive) (void);
+	void (*usb_clock_for_pm) (bool);
+	void (*platform_suspend)(struct fsl_usb2_platform_data *);
+	void (*platform_resume)(struct fsl_usb2_platform_data *);
+	void (*wake_up_enable)(struct fsl_usb2_platform_data *, bool);
+	void (*phy_lowpower_suspend)(struct fsl_usb2_platform_data *, bool);
+	void (*platform_driver_vbus)(bool on); /* for vbus shutdown/open */
+	enum usb_wakeup_event (*is_wakeup_event)(struct fsl_usb2_platform_data *);
+	void (*wakeup_handler)(struct fsl_usb2_platform_data *);
+
+	struct fsl_usb2_wakeup_platform_data *wakeup_pdata;
+	struct platform_device *pdev;
+	unsigned	change_ahb_burst:1;
+	unsigned	ahb_burst_mode:3;
+	unsigned	lowpower:1;
+	unsigned	irq_delay:1;
+	unsigned	wakeup_event:1;
+	u32		pmflags;	/* PM from otg or system */
+
+	/* register save area for suspend/resume */
+	u32		pm_command;
+	u32		pm_status;
+	u32		pm_intr_enable;
+	u32		pm_frame_index;
+	u32		pm_segment;
+	u32		pm_frame_list;
+	u32		pm_async_next;
+	u32		pm_configured_flag;
+	u32		pm_portsc;
+};
+
+struct fsl_usb2_wakeup_platform_data {
+	char *name;
+	void (*usb_clock_for_pm) (bool);
+	void (*usb_wakeup_exhandle) (void);
+	struct fsl_usb2_platform_data *usb_pdata[3];
+	/* This waitqueue is used to wait "usb_wakeup thread" to finish
+	 * during system resume routine. "usb_wakeup theard" should be finished
+	 * prior to usb resume routine.
+	 */
+	wait_queue_head_t wq;
+	/* This flag is used to indicate the "usb_wakeup thread" is finished during
+	 * usb wakeup routine.
+	 */
+	bool usb_wakeup_is_pending;
+};
+#else
 struct fsl_usb2_platform_data {
 	/* board specific information */
 	enum fsl_usb2_operating_modes	operating_mode;
@@ -96,6 +196,12 @@ struct fsl_usb2_platform_data {
 	u32		pm_portsc;
 	u32		pm_usbgenctrl;
 };
+#endif
+
+struct mxc_pm_platform_data {
+        void (*suspend_enter) (void);
+        void (*suspend_exit) (void);
+};
 
 /* Flags in fsl_usb2_mph_platform_data */
 #define FSL_USB2_PORT0_ENABLED	0x00000001
@@ -120,11 +226,67 @@ struct fsl_spi_platform_data {
 	u32	sysclk;
 };
 
+struct mxc_iim_platform_data {
+	const s8        *name;
+	u32     virt_base;
+	u32     reg_base;
+	u32     reg_end;
+	u32     reg_size;
+	u32     bank_start;
+	u32     bank_end;
+	u32     irq;
+	u32     action;
+	struct mutex mutex;
+	struct completion completion;
+	spinlock_t lock;
+	struct clk *clk;
+	struct device *dev;
+	void   (*enable_fuse)(void);
+	void   (*disable_fuse)(void);
+};
+
 struct mpc8xx_pcmcia_ops {
 	void(*hw_ctrl)(int slot, int enable);
 	int(*voltage_set)(int slot, int vcc, int vpp);
 };
 
+/*
+ * This struct is to define the number of SSIs on a platform,
+ * DAM source port config, DAM external port config,
+ * regulator names, and other stuff audio needs.
+ */
+struct mxc_audio_platform_data {
+	int ssi_num;
+	int src_port;
+	int ext_port;
+
+	int intr_id_hp;
+	int ext_ram;
+	struct clk *ssi_clk[2];
+
+	int hp_gpio;
+	int hp_active_low;	/* headphone irq is active loaw */
+
+	int sysclk;
+
+	int (*init) (void);	/* board specific init */
+	int (*amp_enable) (int enable);
+	int (*clock_enable) (int enable);
+	int (*finit) (void);	/* board specific finit */
+	void *priv;		/* used by board specific functions */
+};
+
+struct mxc_spdif_platform_data {
+	int spdif_tx;		/* S/PDIF tx enabled for this board */
+	int spdif_rx;		/* S/PDIF rx enabled for this board */
+	int spdif_clk_44100;	/* tx clk mux in SPDIF_REG_STC; -1 for none */
+	int spdif_clk_48000;	/* tx clk mux in SPDIF_REG_STC; -1 for none */
+	int spdif_clkid;	/* rx clk mux select in SPDIF_REG_SRPC */
+	struct clk *spdif_clk;
+	struct clk *spdif_core_clk;
+	struct clk *spdif_audio_clk;
+};
+
 /* Returns non-zero if the current suspend operation would
  * lead to a deep sleep (i.e. power removed from the core,
  * instead of just the clock).
@@ -135,4 +297,43 @@ int fsl_deep_sleep(void);
 static inline int fsl_deep_sleep(void) { return 0; }
 #endif
 
+struct fsl_mxc_tve_platform_data {
+	char *dac_reg;
+	char *dig_reg;
+};
+
+struct fsl_mxc_lcd_platform_data {
+	char *io_reg;
+	char *core_reg;
+	char *analog_reg;
+	void (*reset) (void);
+	int (*get_pins) (void);
+	void (*put_pins) (void);
+	void (*enable_pins) (void);
+	void (*disable_pins) (void);
+	int default_ifmt;
+	int ipu_id;
+	int disp_id;
+};
+
+struct fsl_mxc_ldb_platform_data {
+	char *lvds_bg_reg;
+	u32 ext_ref;
+#define LDB_SPL_DI0	1
+#define LDB_SPL_DI1	2
+#define LDB_DUL_DI0	3
+#define LDB_DUL_DI1	4
+#define LDB_SIN0	5
+#define LDB_SIN1	6
+#define LDB_SEP0	7
+#define LDB_SEP1	8
+	int mode;
+	int ipu_id;
+	int disp_id;
+
+	/*only work for separate mode*/
+	int sec_ipu_id;
+	int sec_disp_id;
+};
+
 #endif /* _FSL_DEVICE_H_ */
diff --git a/include/linux/ipu.h b/include/linux/ipu.h
new file mode 100644
index 00000000000..05162485455
--- /dev/null
+++ b/include/linux/ipu.h
@@ -0,0 +1,265 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+/*!
+ * @defgroup IPU MXC Image Processing Unit (IPU) Driver
+ */
+/*!
+ * @file arch-mxc/ipu.h
+ *
+ * @brief This file contains the IPU driver API declarations.
+ *
+ * @ingroup IPU
+ */
+
+#ifndef __ASM_ARCH_IPU_H__
+#define __ASM_ARCH_IPU_H__
+
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#ifdef __KERNEL__
+#include <linux/interrupt.h>
+#else
+#ifndef __cplusplus
+typedef unsigned char bool;
+#endif
+#define irqreturn_t int
+#define dma_addr_t int
+#define uint32_t unsigned int
+#define uint16_t unsigned short
+#define uint8_t unsigned char
+#define u32 unsigned int
+#define u8 unsigned char
+#define __u32 u32
+#endif
+
+/*!
+ * Enumeration of IPU rotation modes
+ */
+typedef enum {
+	/* Note the enum values correspond to BAM value */
+	IPU_ROTATE_NONE = 0,
+	IPU_ROTATE_VERT_FLIP = 1,
+	IPU_ROTATE_HORIZ_FLIP = 2,
+	IPU_ROTATE_180 = 3,
+	IPU_ROTATE_90_RIGHT = 4,
+	IPU_ROTATE_90_RIGHT_VFLIP = 5,
+	IPU_ROTATE_90_RIGHT_HFLIP = 6,
+	IPU_ROTATE_90_LEFT = 7,
+} ipu_rotate_mode_t;
+
+/*!
+ * Enumeration of VDI MOTION select
+ */
+typedef enum {
+	MED_MOTION = 0,
+	LOW_MOTION = 1,
+	HIGH_MOTION = 2,
+} ipu_motion_sel;
+
+/*!
+ * Enumeration of DI ports for ADC.
+ */
+typedef enum {
+	DISP0,
+	DISP1,
+	DISP2,
+	DISP3
+} display_port_t;
+
+/*  IPU Pixel format definitions */
+/*  Four-character-code (FOURCC) */
+#define fourcc(a, b, c, d)\
+	 (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*!
+ * @name IPU Pixel Formats
+ *
+ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
+ * the same used by V4L2 API.
+ */
+
+/*! @{ */
+/*! @name Generic or Raw Data Formats */
+/*! @{ */
+#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')	/*!< IPU Generic Data */
+#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')	/*!< IPU Generic Data */
+#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')	/*!< IPU Generic Data */
+#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')	/*!< IPU Generic Data */
+/*! @} */
+/*! @name RGB Formats */
+/*! @{ */
+#define IPU_PIX_FMT_RGB332  fourcc('R', 'G', 'B', '1')	/*!<  8  RGB-3-3-2    */
+#define IPU_PIX_FMT_RGB555  fourcc('R', 'G', 'B', 'O')	/*!< 16  RGB-5-5-5    */
+#define IPU_PIX_FMT_RGB565  fourcc('R', 'G', 'B', 'P')	/*!< 1 6  RGB-5-6-5   */
+#define IPU_PIX_FMT_RGB666  fourcc('R', 'G', 'B', '6')	/*!< 18  RGB-6-6-6    */
+#define IPU_PIX_FMT_BGR666  fourcc('B', 'G', 'R', '6')	/*!< 18  BGR-6-6-6    */
+#define IPU_PIX_FMT_BGR24   fourcc('B', 'G', 'R', '3')	/*!< 24  BGR-8-8-8    */
+#define IPU_PIX_FMT_RGB24   fourcc('R', 'G', 'B', '3')	/*!< 24  RGB-8-8-8    */
+#define IPU_PIX_FMT_GBR24   fourcc('G', 'B', 'R', '3')	/*!< 24  GBR-8-8-8    */
+#define IPU_PIX_FMT_BGR32   fourcc('B', 'G', 'R', '4')	/*!< 32  BGR-8-8-8-8  */
+#define IPU_PIX_FMT_BGRA32  fourcc('B', 'G', 'R', 'A')	/*!< 32  BGR-8-8-8-8  */
+#define IPU_PIX_FMT_RGB32   fourcc('R', 'G', 'B', '4')	/*!< 32  RGB-8-8-8-8  */
+#define IPU_PIX_FMT_RGBA32  fourcc('R', 'G', 'B', 'A')	/*!< 32  RGB-8-8-8-8  */
+#define IPU_PIX_FMT_ABGR32  fourcc('A', 'B', 'G', 'R')	/*!< 32  ABGR-8-8-8-8 */
+/*! @} */
+/*! @name YUV Interleaved Formats */
+/*! @{ */
+#define IPU_PIX_FMT_YUYV    fourcc('Y', 'U', 'Y', 'V')	/*!< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_UYVY    fourcc('U', 'Y', 'V', 'Y')	/*!< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_YVYU    fourcc('Y', 'V', 'Y', 'U')  /*!< 16 YVYU 4:2:2 */
+#define IPU_PIX_FMT_VYUY    fourcc('V', 'Y', 'U', 'Y')  /*!< 16 VYYU 4:2:2 */
+#define IPU_PIX_FMT_Y41P    fourcc('Y', '4', '1', 'P')	/*!< 12 YUV 4:1:1 */
+#define IPU_PIX_FMT_YUV444  fourcc('Y', '4', '4', '4')	/*!< 24 YUV 4:4:4 */
+#define IPU_PIX_FMT_VYU444  fourcc('V', '4', '4', '4')	/*!< 24 VYU 4:4:4 */
+/* two planes -- one Y, one Cb + Cr interleaved  */
+#define IPU_PIX_FMT_NV12    fourcc('N', 'V', '1', '2') /* 12  Y/CbCr 4:2:0  */
+/*! @} */
+/*! @name YUV Planar Formats */
+/*! @{ */
+#define IPU_PIX_FMT_GREY    fourcc('G', 'R', 'E', 'Y')	/*!< 8  Greyscale */
+#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9')	/*!< 9  YVU 4:1:0 */
+#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9')	/*!< 9  YUV 4:1:0 */
+#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2')	/*!< 12 YVU 4:2:0 */
+#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0')	/*!< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2')	/*!< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6')	/*!< 16 YVU 4:2:2 */
+#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')	/*!< 16 YUV 4:2:2 */
+/*! @} */
+
+/* IPU device */
+typedef enum {
+	RGB_CS,
+	YUV_CS,
+	NULL_CS
+} cs_t;
+
+struct ipu_pos {
+	u32 x;
+	u32 y;
+};
+
+struct ipu_crop {
+	struct ipu_pos pos;
+	u32 w;
+	u32 h;
+};
+
+struct ipu_deinterlace {
+	bool	enable;
+	u8	motion; /*see ipu_motion_sel*/
+#define IPU_DEINTERLACE_FIELD_TOP	0
+#define IPU_DEINTERLACE_FIELD_BOTTOM	1
+	u8	field_fmt;
+};
+
+struct ipu_input {
+	u32 width;
+	u32 height;
+	u32 format;
+	struct ipu_crop crop;
+	dma_addr_t paddr;
+
+	struct ipu_deinterlace deinterlace;
+	dma_addr_t paddr_n; /*valid when deinterlace enable*/
+};
+
+struct ipu_alpha {
+#define IPU_ALPHA_MODE_GLOBAL	0
+#define IPU_ALPHA_MODE_LOCAL	1
+	u8 mode;
+	u8 gvalue; /* 0~255 */
+	dma_addr_t loc_alp_paddr;
+};
+
+struct ipu_colorkey {
+	bool enable;
+	u32 value; /* RGB 24bit */
+};
+
+struct ipu_overlay {
+	u32	width;
+	u32	height;
+	u32	format;
+	struct ipu_crop crop;
+	struct ipu_alpha alpha;
+	struct ipu_colorkey colorkey;
+	dma_addr_t paddr;
+};
+
+struct ipu_output {
+	u32	width;
+	u32	height;
+	u32	format;
+	u8	rotate;
+	struct ipu_crop crop;
+	dma_addr_t paddr;
+};
+
+struct ipu_task {
+	struct ipu_input input;
+	struct ipu_output output;
+
+	bool overlay_en;
+	struct ipu_overlay overlay;
+
+#define IPU_TASK_PRIORITY_NORMAL 0
+#define IPU_TASK_PRIORITY_HIGH	1
+	u8	priority;
+
+#define	IPU_TASK_ID_ANY	0
+#define	IPU_TASK_ID_VF	1
+#define	IPU_TASK_ID_PP	2
+#define	IPU_TASK_ID_MAX 3
+	u8	task_id;
+
+	int	timeout;
+};
+
+enum {
+	IPU_CHECK_OK = 0,
+	IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN = 0x1,
+	IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN = 0x2,
+	IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN = 0x4,
+	IPU_CHECK_ERR_MIN,
+	IPU_CHECK_ERR_INPUT_CROP,
+	IPU_CHECK_ERR_OUTPUT_CROP,
+	IPU_CHECK_ERR_OVERLAY_CROP,
+	IPU_CHECK_ERR_INPUT_OVER_LIMIT,
+	IPU_CHECK_ERR_OV_OUT_NO_FIT,
+	IPU_CHECK_ERR_OVERLAY_WITH_VDI,
+	IPU_CHECK_ERR_PROC_NO_NEED,
+	IPU_CHECK_ERR_SPLIT_INPUTW_OVER,
+	IPU_CHECK_ERR_SPLIT_INPUTH_OVER,
+	IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER,
+	IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER,
+	IPU_CHECK_ERR_SPLIT_WITH_ROT,
+};
+
+/* IOCTL commands */
+#define IPU_CHECK_TASK		_IOWR('I', 0x1, struct ipu_task)
+#define IPU_QUEUE_TASK		_IOW('I', 0x2, struct ipu_task)
+#define IPU_ALLOC		_IOWR('I', 0x3, int)
+#define IPU_FREE		_IOW('I', 0x4, int)
+
+/* export functions */
+#ifdef __KERNEL__
+unsigned int fmt_to_bpp(unsigned int pixelformat);
+cs_t colorspaceofpixel(int fmt);
+int need_csc(int ifmt, int ofmt);
+
+int ipu_queue_task(struct ipu_task *task);
+int ipu_check_task(struct ipu_task *task);
+#endif
+
+#endif
diff --git a/include/linux/mfd/da9052/adc.h b/include/linux/mfd/da9052/adc.h
new file mode 100644
index 00000000000..49c7d181d15
--- /dev/null
+++ b/include/linux/mfd/da9052/adc.h
@@ -0,0 +1,66 @@
+/*
+ * da9052 ADC module declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_ADC_H
+#define __LINUX_MFD_DA9052_ADC_H
+
+#include "gpio.h"
+
+#define DA9052_ADC_DEVICE_NAME				"da9052_adc"
+
+/* Channel Definations */
+#define DA9052_ADC_VDDOUT				0
+#define DA9052_ADC_ICH					1
+#define DA9052_ADC_TBAT					2
+#define DA9052_ADC_VBAT					3
+#define DA9052_ADC_ADCIN4				4
+#define DA9052_ADC_ADCIN5				5
+#define DA9052_ADC_ADCIN6				6
+#define DA9052_ADC_TSI					7
+#define DA9052_ADC_TJUNC				8
+#define DA9052_ADC_VBBAT				9
+
+#if (DA9052_GPIO_PIN_0 == DA9052_GPIO_CONFIG_ADC)
+#define DA9052_ADC_CONF_ADC4				1
+#else
+#define DA9052_ADC_CONF_ADC4				0
+#endif
+#if (DA9052_GPIO_PIN_1 == DA9052_GPIO_CONFIG_ADC)
+#define DA9052_ADC_CONF_ADC5				1
+#else
+#define DA9052_ADC_CONF_ADC5				0
+#endif
+#if (DA9052_GPIO_PIN_2 == DA9052_GPIO_CONFIG_ADC)
+#define DA9052_ADC_CONF_ADC6				1
+#else
+#define DA9052_ADC_CONF_ADC6				0
+#endif
+
+/* Maximum retry count to check manual conversion over */
+#define DA9052_ADC_MAX_MANCONV_RETRY_COUNT		8
+
+struct da9052_adc_priv {
+	struct da9052 *da9052;
+	struct device *hwmon_dev;
+	struct mutex manconv_lock;
+};
+
+#endif /* __LINUX_MFD_DA9052_ADC_H */
diff --git a/include/linux/mfd/da9052/bat.h b/include/linux/mfd/da9052/bat.h
new file mode 100644
index 00000000000..4643c457931
--- /dev/null
+++ b/include/linux/mfd/da9052/bat.h
@@ -0,0 +1,264 @@
+/*
+ * da9052 BAT module declarations.
+  *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_BAT_H
+#define __LINUX_MFD_DA9052_BAT_H
+
+#include <linux/power_supply.h>
+
+/* STATIC CONFIGURATION */
+#define DA9052_LOOK_UP_TABLE_SIZE		68
+#define DA9052_NO_OF_LOOKUP_TABLE		3
+#define DA9052_FILTER_SIZE			4
+#define DA9052_NUMBER_OF_STORE_CURENT_READING	4
+#define DA9052_BAT_FILTER_HYS			0
+
+
+static const u16 temperature_lookup_ref
+			[DA9052_NO_OF_LOOKUP_TABLE] = {10, 25, 40};
+static u32 const vbat_vs_capacity_look_up[DA9052_NO_OF_LOOKUP_TABLE]
+					[DA9052_LOOK_UP_TABLE_SIZE][2] = {
+	/* For temperature 10 degree celisus*/
+	{
+	{4082, 100}, {4036, 98},
+	{4020, 96}, {4008, 95},
+	{3997, 93}, {3983, 91},
+	{3964, 90}, {3943, 88},
+	{3926, 87}, {3912, 85},
+	{3900, 84}, {3890, 82},
+	{3881, 80}, {3873, 79},
+	{3865, 77}, {3857, 76},
+	{3848, 74}, {3839, 73},
+	{3829, 71}, {3820, 70},
+	{3811, 68}, {3802, 67},
+	{3794, 65}, {3785, 64},
+	{3778, 62}, {3770, 61},
+	{3763, 59}, {3756, 58},
+	{3750, 56}, {3744, 55},
+	{3738, 53}, {3732, 52},
+	{3727, 50}, {3722, 49},
+	{3717, 47}, {3712, 46},
+	{3708, 44}, {3703, 43},
+	{3700, 41}, {3696, 40},
+	{3693, 38}, {3691, 37},
+	{3688, 35}, {3686, 34},
+	{3683, 32}, {3681, 31},
+	{3678, 29}, {3675, 28},
+	{3672, 26}, {3669, 25},
+	{3665, 23}, {3661, 22},
+	{3656, 21}, {3651, 19},
+	{3645, 18}, {3639, 16},
+	{3631, 15}, {3622, 13},
+	{3611, 12}, {3600, 10},
+	{3587, 9}, {3572, 7},
+	{3548, 6}, {3503, 5},
+	{3420, 3}, {3268, 2},
+	{2992, 1}, {2746, 0}
+	},
+	/* For temperature 25 degree celisus */
+	{
+	{4102, 100}, {4065, 98},
+	{4048, 96}, {4034, 95},
+	{4021, 93}, {4011, 92},
+	{4001, 90}, {3986, 88},
+	{3968, 87}, {3952, 85},
+	{3938, 84}, {3926, 82},
+	{3916, 81}, {3908, 79},
+	{3900, 77}, {3892, 76},
+	{3883, 74}, {3874, 73},
+	{3864, 71}, {3855, 70},
+	{3846, 68}, {3836, 67},
+	{3827, 65}, {3819, 64},
+	{3810, 62}, {3801, 61},
+	{3793, 59}, {3786, 58},
+	{3778, 56}, {3772, 55},
+	{3765, 53}, {3759, 52},
+	{3754, 50}, {3748, 49},
+	{3743, 47}, {3738, 46},
+	{3733, 44}, {3728, 43},
+	{3724, 41}, {3720, 40},
+	{3716, 38}, {3712, 37},
+	{3709, 35}, {3706, 34},
+	{3703, 33}, {3701, 31},
+	{3698, 30}, {3696, 28},
+	{3693, 27}, {3690, 25},
+	{3687, 24}, {3683, 22},
+	{3680, 21}, {3675, 19},
+	{3671, 18}, {3666, 17},
+	{3660, 15}, {3654, 14},
+	{3647, 12}, {3639, 11},
+	{3630, 9}, {3621, 8},
+	{3613, 6}, {3606, 5},
+	{3597, 4}, {3582, 2},
+	{3546, 1}, {2747, 0}
+	},
+	/* For temperature 40 degree celisus*/
+	{
+	{4114, 100}, {4081, 98},
+	{4065, 96}, {4050, 95},
+	{4036, 93}, {4024, 92},
+	{4013, 90}, {4002, 88},
+	{3990, 87}, {3976, 85},
+	{3962, 84}, {3950, 82},
+	{3939, 81}, {3930, 79},
+	{3921, 77}, {3912, 76},
+	{3902, 74}, {3893, 73},
+	{3883, 71}, {3874, 70},
+	{3865, 68}, {3856, 67},
+	{3847, 65}, {3838, 64},
+	{3829, 62}, {3820, 61},
+	{3812, 59}, {3803, 58},
+	{3795, 56}, {3787, 55},
+	{3780, 53}, {3773, 52},
+	{3767, 50}, {3761, 49},
+	{3756, 47}, {3751, 46},
+	{3746, 44}, {3741, 43},
+	{3736, 41}, {3732, 40},
+	{3728, 38}, {3724, 37},
+	{3720, 35}, {3716, 34},
+	{3713, 33}, {3710, 31},
+	{3707, 30}, {3704, 28},
+	{3701, 27}, {3698, 25},
+	{3695, 24}, {3691, 22},
+	{3686, 21}, {3681, 19},
+	{3676, 18}, {3671, 17},
+	{3666, 15}, {3661, 14},
+	{3655, 12}, {3648, 11},
+	{3640, 9}, {3632, 8},
+	{3622, 6}, {3616, 5},
+	{3611, 4}, {3604, 2},
+	{3594, 1}, {2747, 0}
+	}
+};
+
+enum charger_type_enum {
+	DA9052_NOCHARGER = 1,
+	DA9052_USB_HUB,
+	DA9052_USB_CHARGER,
+	DA9052_WALL_CHARGER
+};
+
+struct da9052_bat_event_registration {
+	u8	da9052_event_tbat:1;
+};
+
+struct da9052_bat_hysteresis {
+	u16	bat_volt_arr[3];
+	u16	array_hys_batvoltage[2];
+	u16	upper_limit;
+	u16	lower_limit;
+	u8	index;
+	u8	hys_flag;
+};
+
+struct da9052_charger_device {
+	struct da9052			*da9052;
+	struct workqueue_struct		*monitor_wqueue;
+	struct delayed_work		monitor_work;
+	struct power_supply		psy;
+	struct da9052_eh_nb		tbat_eh_data;
+	u8				cal_capacity;
+	u8				charger_type;
+	u8				health;
+	u8				status;
+	u8				illegal;
+	u16				technology;
+	u16				chg_current;
+	u16				bat_voltage;
+	u16				bat_capacity_limit_low;
+	u16				bat_capacity_full;
+	u16				bat_capacity_limit_high;
+	u16				bat_volt_cutoff;
+	u16				bat_with_no_resistor;
+	u16				bat_temp;
+	u8				hys_flag;
+	u16				charger_voltage_drop;
+	u16				bat_target_voltage;
+	u16				chg_end_current;
+	u16				hysteresis_window_size;
+	u16				chg_hysteresis_const;
+	u16				hysteresis_reading_interval;
+	u16				hysteresis_no_of_reading;
+	u16				vbat_first_valid_detect_iteration;
+};
+
+
+static inline  u8 bat_temp_reg_to_C(u16 value) { return (55 - value); }
+static inline  u8 bat_mV_to_reg(u16 value) { return (((value-4100)/100)<<4); }
+static inline  u8 bat_drop_mV_to_reg(u16 value)
+		{ return (((value-100)/100)<<6); }
+static inline  u16 bat_reg_to_mV(u8 value) { return ((value*100) + 4100); }
+static inline  u16 bat_drop_reg_to_mV(u8 value) { return ((value*100)+100); }
+static inline  u8 vch_thr_mV_to_reg(u16 value) { return ((value-3700)/100); }
+static inline  u8 precharge_mA_to_reg(u8 value) { return ((value/20)<<6); }
+static inline  u8 vddout_mon_mV_to_reg(u16 value)
+		{ return (((value-2500)*128)/1000); }
+static inline  u16 vddout_reg_to_mV(u8 value)
+		{ return ((value*1000)/128)+2500; }
+static inline  u16 volt_reg_to_mV(u16 value)
+		{ return ((value*1000)/512)+2500; }
+static inline  u8 ichg_mA_to_reg(u16 value) { return (value/4); }
+static inline  u16 ichg_reg_to_mA(u8 value) { return ((value*3900)/1000); }
+static inline u8 iset_mA_to_reg(u16 iset_value)
+		{\
+		if ((70 <= iset_value) && (iset_value <= 120)) \
+			return (iset_value-70)/10; \
+		else if ((400 <= iset_value) && (iset_value <= 700)) \
+			return ((iset_value-400)/50)+6; \
+		else if ((900 <= iset_value) && (iset_value <= 1300)) \
+			return ((iset_value-900)/200)+13; else return 0;
+		}
+
+#define DA9052_BAT_DEBUG		0
+
+#define DA9052_BAT_PROFILE		0
+#define SUCCESS				0
+#define FAILURE				1
+
+#define TRUE				1
+#define FALSE				0
+
+#define set_bits(value, mask)		(value | mask)
+#define clear_bits(value, mask)		(value & ~(mask))
+
+#undef DA9052_DEBUG
+#if DA9052_BAT_DEBUG
+#define DA9052_DEBUG(fmt, args...) printk(KERN_CRIT "" fmt, ##args)
+#else
+#define DA9052_DEBUG(fmt, args...)
+#endif
+
+
+/* SSC Read or Write Error */
+#define DA9052_SSC_FAIL			150
+
+/* To enable debug output for your module, set this to 1 */
+#define		DA9052_SSC_DEBUG	0
+
+#undef DA9052_DEBUG
+#if DA9052_SSC_DEBUG
+#define DA9052_DEBUG(fmt, args...) printk(KERN_CRIT "" fmt, ##args)
+#else
+#define DA9052_DEBUG(fmt, args...)
+#endif
+
+
+#endif /* __LINUX_MFD_DA9052_BAT_H */
diff --git a/include/linux/mfd/da9052/bl.h b/include/linux/mfd/da9052/bl.h
new file mode 100644
index 00000000000..9217eb95a77
--- /dev/null
+++ b/include/linux/mfd/da9052/bl.h
@@ -0,0 +1,289 @@
+/*
+ * da9052 Backlight module declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_BL_H
+#define __LINUX_MFD_DA9052_BL_H
+
+/*
+ * enum da9052_bl_current_value - Enum for current values of LED
+ * DA9052_BL_CURRENT_50_0UA: represents 50.0 uA current value
+ */
+enum da9052_bl_current_value {
+/* Current Value for LEDMIN, LED1_CONF, LED2_CONF, LED3_CONF Registers */
+	DA9052_BL_CURRENT_50_0UA = 0,
+	DA9052_BL_CURRENT_51_2UA,
+	DA9052_BL_CURRENT_52_5UA,
+	DA9052_BL_CURRENT_53_7UA,
+	DA9052_BL_CURRENT_55_1UA,
+	DA9052_BL_CURRENT_56_4UA,
+	DA9052_BL_CURRENT_57_8UA,
+	DA9052_BL_CURRENT_59_3UA,
+	DA9052_BL_CURRENT_60_7UA,
+	DA9052_BL_CURRENT_62_2UA,
+	DA9052_BL_CURRENT_63_8UA,
+	DA9052_BL_CURRENT_65_3UA,
+	DA9052_BL_CURRENT_67_0UA,
+	DA9052_BL_CURRENT_68_6UA,
+	DA9052_BL_CURRENT_70_3UA,
+	DA9052_BL_CURRENT_72_0UA,
+	DA9052_BL_CURRENT_73_8UA,
+	DA9052_BL_CURRENT_75_7UA,
+	DA9052_BL_CURRENT_77_5UA,
+	DA9052_BL_CURRENT_79_4UA,
+	DA9052_BL_CURRENT_81_4UA,
+	DA9052_BL_CURRENT_83_4UA,
+	DA9052_BL_CURRENT_85_5UA,
+	DA9052_BL_CURRENT_87_6UA,
+	DA9052_BL_CURRENT_89_8UA,
+	DA9052_BL_CURRENT_92_0UA,
+	DA9052_BL_CURRENT_94_2UA,
+	DA9052_BL_CURRENT_96_6UA,
+	DA9052_BL_CURRENT_99_0UA,
+	DA9052_BL_CURRENT_101_4UA,
+	DA9052_BL_CURRENT_103_9UA,
+	DA9052_BL_CURRENT_106_5UA,
+	DA9052_BL_CURRENT_109_1UA,
+	DA9052_BL_CURRENT_111_8UA,
+	DA9052_BL_CURRENT_114_6UA,
+	DA9052_BL_CURRENT_117_4UA,
+	DA9052_BL_CURRENT_120_6UA,
+	DA9052_BL_CURRENT_123_3UA,
+	DA9052_BL_CURRENT_126_3UA,
+	DA9052_BL_CURRENT_129_4UA,
+	DA9052_BL_CURRENT_132_6UA,
+	DA9052_BL_CURRENT_135_9UA,
+	DA9052_BL_CURRENT_139_3UA,
+	DA9052_BL_CURRENT_142_7UA,
+	DA9052_BL_CURRENT_146_2UA,
+	DA9052_BL_CURRENT_149_9UA,
+	DA9052_BL_CURRENT_153_6UA,
+	DA9052_BL_CURRENT_157_4UA,
+	DA9052_BL_CURRENT_161_2UA,
+	DA9052_BL_CURRENT_165_2UA,
+	DA9052_BL_CURRENT_169_3UA,
+	DA9052_BL_CURRENT_173_5UA,
+	DA9052_BL_CURRENT_177_8UA,
+	DA9052_BL_CURRENT_182_2UA,
+	DA9052_BL_CURRENT_186_7UA,
+	DA9052_BL_CURRENT_191_3UA,
+	DA9052_BL_CURRENT_196_0UA,
+	DA9052_BL_CURRENT_200_9UA,
+	DA9052_BL_CURRENT_205_8UA,
+	DA9052_BL_CURRENT_210_9UA,
+	DA9052_BL_CURRENT_216_1UA,
+	DA9052_BL_CURRENT_221_4UA,
+	DA9052_BL_CURRENT_226_9UA,
+	DA9052_BL_CURRENT_232_5UA,
+	DA9052_BL_CURRENT_238_3UA,
+	DA9052_BL_CURRENT_244_2UA,
+	DA9052_BL_CURRENT_250_2UA,
+	DA9052_BL_CURRENT_256_4UA,
+	DA9052_BL_CURRENT_262_7UA,
+	DA9052_BL_CURRENT_269_2UA,
+	DA9052_BL_CURRENT_275_8UA,
+	DA9052_BL_CURRENT_282_7UA,
+	DA9052_BL_CURRENT_289_6UA,
+	DA9052_BL_CURRENT_296_8UA,
+	DA9052_BL_CURRENT_304_1UA,
+	DA9052_BL_CURRENT_311_6UA,
+	DA9052_BL_CURRENT_319_3UA,
+	DA9052_BL_CURRENT_327_2UA,
+	DA9052_BL_CURRENT_335_3UA,
+	DA9052_BL_CURRENT_343_6UA,
+	DA9052_BL_CURRENT_352_1UA,
+	DA9052_BL_CURRENT_360_8UA,
+	DA9052_BL_CURRENT_369_7UA,
+	DA9052_BL_CURRENT_378_8UA,
+	DA9052_BL_CURRENT_388_2UA,
+	DA9052_BL_CURRENT_397_8UA,
+	DA9052_BL_CURRENT_407_6UA,
+	DA9052_BL_CURRENT_417_7UA,
+	DA9052_BL_CURRENT_428_0UA,
+	DA9052_BL_CURRENT_438_6UA,
+	DA9052_BL_CURRENT_449_4UA,
+	DA9052_BL_CURRENT_460_5UA,
+	DA9052_BL_CURRENT_471_9UA,
+	DA9052_BL_CURRENT_483_5UA,
+	DA9052_BL_CURRENT_495_5UA,
+	DA9052_BL_CURRENT_507_7UA,
+	DA9052_BL_CURRENT_520_3UA,
+	DA9052_BL_CURRENT_533_1UA,
+	DA9052_BL_CURRENT_546_3UA,
+	DA9052_BL_CURRENT_559_8UA,
+	DA9052_BL_CURRENT_573_6UA,
+	DA9052_BL_CURRENT_587_8UA,
+	DA9052_BL_CURRENT_602_3UA,
+	DA9052_BL_CURRENT_617_2UA,
+	DA9052_BL_CURRENT_632_4UA,
+	DA9052_BL_CURRENT_648_0UA,
+	DA9052_BL_CURRENT_664_0UA,
+	DA9052_BL_CURRENT_680_4UA,
+	DA9052_BL_CURRENT_697_2UA,
+	DA9052_BL_CURRENT_714_5UA,
+	DA9052_BL_CURRENT_732_1UA,
+	DA9052_BL_CURRENT_750_2UA,
+	DA9052_BL_CURRENT_768_7UA,
+	DA9052_BL_CURRENT_787_7UA,
+	DA9052_BL_CURRENT_807_2UA,
+	DA9052_BL_CURRENT_827_1UA,
+	DA9052_BL_CURRENT_847_6UA,
+	DA9052_BL_CURRENT_868_5UA,
+	DA9052_BL_CURRENT_889_9UA,
+	DA9052_BL_CURRENT_911_9UA,
+	DA9052_BL_CURRENT_934_4UA,
+	DA9052_BL_CURRENT_957_5UA,
+	DA9052_BL_CURRENT_981_2UA,
+	DA9052_BL_CURRENT_1005_4UA,
+	DA9052_BL_CURRENT_1030_3UA,
+	DA9052_BL_CURRENT_1055_7UA,
+	DA9052_BL_CURRENT_1081_8UA,
+	DA9052_BL_CURRENT_1108_5UA,
+	DA9052_BL_CURRENT_1135_9UA,
+	DA9052_BL_CURRENT_1163_9UA,
+	DA9052_BL_CURRENT_1192_7UA,
+	DA9052_BL_CURRENT_1222_2UA,
+	DA9052_BL_CURRENT_1252_3UA,
+	DA9052_BL_CURRENT_1283_3UA,
+	DA9052_BL_CURRENT_1315_0UA,
+	DA9052_BL_CURRENT_1347_5UA,
+	DA9052_BL_CURRENT_1380_7UA,
+	DA9052_BL_CURRENT_1414_8UA,
+	DA9052_BL_CURRENT_1449_8UA,
+	DA9052_BL_CURRENT_1485_6UA,
+	DA9052_BL_CURRENT_1522_3UA,
+	DA9052_BL_CURRENT_1559_9UA,
+	DA9052_BL_CURRENT_1598_4UA,
+	DA9052_BL_CURRENT_1637_9UA,
+	DA9052_BL_CURRENT_1678_4UA,
+	DA9052_BL_CURRENT_1719_8UA,
+	DA9052_BL_CURRENT_1762_3UA,
+	DA9052_BL_CURRENT_1805_8UA,
+	DA9052_BL_CURRENT_1850_4UA,
+	DA9052_BL_CURRENT_1896_1UA,
+	DA9052_BL_CURRENT_1943_0UA,
+	DA9052_BL_CURRENT_1991_0UA,
+	DA9052_BL_CURRENT_2040_2UA,
+	DA9052_BL_CURRENT_2090_5UA,
+	DA9052_BL_CURRENT_2142_2UA,
+	DA9052_BL_CURRENT_2195_1UA,
+	DA9052_BL_CURRENT_2249_3UA,
+	DA9052_BL_CURRENT_2304_9UA,
+	DA9052_BL_CURRENT_2361_8UA,
+	DA9052_BL_CURRENT_2420_1UA,
+	DA9052_BL_CURRENT_2479_9UA,
+	DA9052_BL_CURRENT_2541_2UA,
+	DA9052_BL_CURRENT_2604_0UA,
+	DA9052_BL_CURRENT_2668_3UA,
+	DA9052_BL_CURRENT_2734_2UA,
+	DA9052_BL_CURRENT_2801_7UA,
+	DA9052_BL_CURRENT_2870_9UA,
+	DA9052_BL_CURRENT_2941_8UA,
+	DA9052_BL_CURRENT_3014_5UA,
+	DA9052_BL_CURRENT_3089_0UA,
+	DA9052_BL_CURRENT_3165_3UA,
+	DA9052_BL_CURRENT_3243_4UA,
+	DA9052_BL_CURRENT_3323_5UA,
+	DA9052_BL_CURRENT_3405_6UA,
+	DA9052_BL_CURRENT_3489_8UA,
+	DA9052_BL_CURRENT_3576_0UA,
+	DA9052_BL_CURRENT_3664_3UA,
+	DA9052_BL_CURRENT_3754_8UA,
+	DA9052_BL_CURRENT_3847_5UA,
+	DA9052_BL_CURRENT_3942_6UA,
+	DA9052_BL_CURRENT_4040_0UA,
+	DA9052_BL_CURRENT_4139_7UA,
+	DA9052_BL_CURRENT_4242_0UA,
+	DA9052_BL_CURRENT_4346_8UA,
+	DA9052_BL_CURRENT_4454_1UA,
+	DA9052_BL_CURRENT_4564_2UA,
+	DA9052_BL_CURRENT_4676_9UA,
+	DA9052_BL_CURRENT_4792_4UA,
+	DA9052_BL_CURRENT_4910_8UA,
+	DA9052_BL_CURRENT_5032_1UA,
+	DA9052_BL_CURRENT_5156_4UA,
+	DA9052_BL_CURRENT_5283_7UA,
+	DA9052_BL_CURRENT_5414_3UA,
+	DA9052_BL_CURRENT_5548_0UA,
+	DA9052_BL_CURRENT_5685_0UA,
+	DA9052_BL_CURRENT_5825_5UA,
+	DA9052_BL_CURRENT_5969_3UA,
+	DA9052_BL_CURRENT_6116_8UA,
+	DA9052_BL_CURRENT_6267_9UA,
+	DA9052_BL_CURRENT_6422_7UA,
+	DA9052_BL_CURRENT_6581_3UA,
+	DA9052_BL_CURRENT_6743_9UA,
+	DA9052_BL_CURRENT_6910_5UA,
+	DA9052_BL_CURRENT_7081_2UA,
+	DA9052_BL_CURRENT_7256_1UA,
+	DA9052_BL_CURRENT_7435_3UA,
+	DA9052_BL_CURRENT_7618_9UA,
+	DA9052_BL_CURRENT_7807_1UA,
+	DA9052_BL_CURRENT_8000_0UA,
+	DA9052_BL_CURRENT_8197_6UA,
+	DA9052_BL_CURRENT_8400_0UA,
+	DA9052_BL_CURRENT_8607_5UA,
+	DA9052_BL_CURRENT_8820_1UA,
+	DA9052_BL_CURRENT_9038_0UA,
+	DA9052_BL_CURRENT_9261_2UA,
+	DA9052_BL_CURRENT_9490_0UA,
+	DA9052_BL_CURRENT_9724_4UA,
+	DA9052_BL_CURRENT_9964_6UA,
+	DA9052_BL_CURRENT_10210_7UA,
+	DA9052_BL_CURRENT_10462_9UA,
+	DA9052_BL_CURRENT_10721_4UA,
+	DA9052_BL_CURRENT_10986_4UA,
+	DA9052_BL_CURRENT_11257_5UA,
+	DA9052_BL_CURRENT_11535_6UA,
+	DA9052_BL_CURRENT_11820_5UA,
+	DA9052_BL_CURRENT_12112_5UA,
+	DA9052_BL_CURRENT_12411_7UA,
+	DA9052_BL_CURRENT_12718_2UA,
+	DA9052_BL_CURRENT_13032_4UA,
+	DA9052_BL_CURRENT_13354_3UA,
+	DA9052_BL_CURRENT_13684_1UA,
+	DA9052_BL_CURRENT_14022_1UA,
+	DA9052_BL_CURRENT_14368_5UA,
+	DA9052_BL_CURRENT_14723_4UA,
+	DA9052_BL_CURRENT_15087_1UA,
+	DA9052_BL_CURRENT_15459_7UA,
+	DA9052_BL_CURRENT_15841_6UA,
+	DA9052_BL_CURRENT_16232_9UA,
+	DA9052_BL_CURRENT_16633_8UA,
+	DA9052_BL_CURRENT_17044_7UA,
+	DA9052_BL_CURRENT_17465_7UA,
+	DA9052_BL_CURRENT_17897_1UA,
+	DA9052_BL_CURRENT_18339_1UA,
+	DA9052_BL_CURRENT_18792_1UA,
+	DA9052_BL_CURRENT_19256_3UA,
+	DA9052_BL_CURRENT_19731_9UA,
+	DA9052_BL_CURRENT_20219_3UA,
+	DA9052_BL_CURRENT_20718_7UA,
+	DA9052_BL_CURRENT_21230_5UA,
+	DA9052_BL_CURRENT_21754_8UA,
+	DA9052_BL_CURRENT_22292_2UA,
+	DA9052_BL_CURRENT_22842_8UA,
+	DA9052_BL_CURRENT_23407_0UA,
+	DA9052_BL_CURRENT_23985_2UA,
+	DA9052_BL_CURRENT_24577_6UA,
+	DA9052_BL_CURRENT_25000_0UA,
+};
+
+#endif /* __LINUX_MFD_DA9052_BL_H */
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
new file mode 100644
index 00000000000..88d34cacbb9
--- /dev/null
+++ b/include/linux/mfd/da9052/da9052.h
@@ -0,0 +1,209 @@
+/*
+ * da9052 declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_DA9052_H
+#define __LINUX_MFD_DA9052_DA9052_H
+
+#include <linux/slab.h>
+#include <linux/mfd/core.h>
+
+#include <linux/mfd/da9052/eh.h>
+#include <linux/mfd/da9052/reg.h>
+#include <linux/mfd/da9052/led.h>
+
+
+#define SPI 1
+#define I2C 2
+
+#define DA9052_SSC_DEVICE_NAME		"da9052_ssc"
+#define DA9052_EH_DEVICE_NAME		"da9052_eh"
+
+#define DA9052_IRQ			S3C_EINT(9)
+
+/* Module specific error codes */
+#define INVALID_REGISTER		2
+#define INVALID_READ			3
+#define INVALID_PAGE			4
+
+/* Defines for Volatile and Non Volatile register types */
+#define VOLATILE			0
+#define NON_VOLATILE			1
+
+/* Defines for cache state */
+#define VALID				0
+#define INVALID				1
+
+/* Total number of registers in DA9057 */
+#define DA9052_REG_CNT			DA9052_PAGE1_REG_END
+
+/* Maximum number of registers that can be read/written by a singe request */
+#define	MAX_READ_WRITE_CNT		16
+
+
+#define DA9052_SSC_SPI_DEVICE_NAME	"da9052_ssc_spi"
+#define PAGE_0_START			1
+#define PAGE_0_END			127
+#define PAGE_1_START			128
+#define PAGE_1_END			255
+#define ACTIVE_PAGE_0			0
+#define ACTIVE_PAGE_1			1
+#define PAGECON_0			0
+#define PAGECON_128			128
+#define RW_POL				1
+
+#define DA9052_SSC_I2C_DEVICE_NAME		"da9052_ssc_i2c"
+#define	DA9052_I2C_ADDR				0x90
+#define	DA9052_SSC_I2C_PAGE_WRITE_MODE		0
+#define DA9052_SSC_I2C_REPEAT_WRITE_MODE	1
+#define DA9052_SSC_I2C_WRITE_MODE		DA9052_SSC_I2C_REPEAT_WRITE_MODE
+
+struct da9052_ssc_msg {
+	unsigned char	data;
+	unsigned char	addr;
+};
+
+struct ssc_cache_entry {
+	 unsigned char	val;
+	 unsigned char	type:4;
+	 unsigned char	status:4;
+};
+
+struct da9052_eh_nb {
+	struct list_head nb_list;
+	unsigned char	eve_type;
+	void (*call_back)(struct da9052_eh_nb *, unsigned int);
+};
+
+struct da9052_regulator_init_data {
+	struct regulator_init_data *init_data;
+	int id;
+
+};
+
+struct da9052_regulator_platform_data {
+	struct regulator_init_data *regulators;
+};
+
+struct da9052_tsi_platform_data {
+	u32	pen_up_interval;
+	u16	tsi_delay_bit_shift;
+	u16	tsi_skip_bit_shift;
+	u16	num_gpio_tsi_register;
+	u16	tsi_supply_voltage;
+	u16	tsi_ref_source;
+	u16	max_tsi_delay;
+	u16	max_tsi_skip_slot;
+};
+
+
+struct da9052 {
+	struct mutex ssc_lock;
+	struct mutex eve_nb_lock;
+	struct mutex manconv_lock;
+	struct work_struct eh_isr_work;
+	struct ssc_cache_entry ssc_cache[DA9052_REG_CNT];
+	int (*read) (struct da9052 *da9052, struct da9052_ssc_msg *sscmsg);
+	int (*write) (struct da9052 *da9052, struct da9052_ssc_msg *sscmsg);
+	int (*read_many) (struct da9052 *da9052,
+		struct da9052_ssc_msg *sscmsg, int cnt);
+	int (*write_many)(struct da9052 *da9052,
+		struct da9052_ssc_msg *sscmsg, int cnt);
+	int (*register_event_notifier)(struct da9052 *da9052,
+		struct da9052_eh_nb *nb);
+	int (*unregister_event_notifier)(struct da9052 *da9052,
+		struct da9052_eh_nb *nb);
+	int num_regulators;
+	int connecting_device;
+	int irq;
+	struct		spi_device *spi_dev;
+	unsigned int	spi_active_page;
+	unsigned char	rw_pol;
+	unsigned char	*spi_rx_buf;
+	unsigned char	*spi_tx_buf;
+
+	struct i2c_client *i2c_client;
+	struct device *dev;
+	struct i2c_adapter *adapter;
+	unsigned char	slave_addr;
+};
+
+
+struct da9052_platform_data {
+	int (*init)(struct da9052 *da9052);
+	int	irq_high;
+	int	irq_base;
+	int	gpio_base;
+	int	num_regulators;
+	struct da9052 *da9052;
+	struct regulator_init_data *regulators;
+	struct da9052_leds_platform_data *led_data;
+	struct da9052_tsi_platform_data *tsi_data;
+};
+
+struct da9052_ssc_ops {
+	int (*write)(struct da9052 *da9052, struct da9052_ssc_msg *msg);
+	int (*read)(struct da9052 *da9052, struct da9052_ssc_msg *msg);
+	int (*write_many)(struct da9052 *da9052,
+	struct da9052_ssc_msg *sscmsg, int msg_no);
+	int (*read_many)(struct da9052 *da9052,
+	struct da9052_ssc_msg *sscmsg, int msg_no);
+	int (*device_register)(struct da9052 *da9052);
+	void (*device_unregister)(void);
+};
+
+int da9052_ssc_write(struct da9052 *da9052,
+		struct da9052_ssc_msg *sscmsg);
+int da9052_ssc_read(struct da9052 *da9052,
+		struct da9052_ssc_msg *sscmsg);
+int da9052_ssc_write_many(struct da9052 *da9052,
+		struct da9052_ssc_msg *sscmsg, int cnt);
+int da9052_ssc_read_many(struct da9052 *da9052,
+		struct da9052_ssc_msg *sscmsg, int cnt);
+
+int da9052_spi_write(struct da9052 *da9052,
+		struct da9052_ssc_msg *msg);
+int da9052_spi_read(struct da9052 *da9052,
+		struct da9052_ssc_msg *msg);
+
+int da9052_spi_write_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg,
+		int msg_no);
+int da9052_spi_read_many(struct da9052 *da9052,
+		struct da9052_ssc_msg *sscmsg,
+		int msg_no);
+
+void da9052_ssc_exit(struct da9052 *da9052);
+int da9052_ssc_init(struct da9052 *da9052);
+
+/* I2C specific Functions */
+int da9052_i2c_write(struct da9052 *da9052, struct da9052_ssc_msg *msg);
+int da9052_i2c_read(struct da9052 *da9052, struct da9052_ssc_msg *msg);
+int da9052_i2c_write_many(struct da9052 *da9052,
+		struct da9052_ssc_msg *sscmsg, int msg_no);
+int da9052_i2c_read_many(struct da9052 *da9052,
+		struct da9052_ssc_msg *sscmsg, int msg_no);
+
+void da9052_lock(struct da9052 *da9052);
+void da9052_unlock(struct da9052 *da9052);
+int eh_register_nb(struct da9052 *da9052, struct da9052_eh_nb *nb);
+int eh_unregister_nb(struct da9052 *da9052, struct da9052_eh_nb *nb);
+int da9052_manual_read(struct da9052 *da9052,
+		unsigned char channel);
+#endif /* __LINUX_MFD_DA9052_DA9052_H */
diff --git a/include/linux/mfd/da9052/eh.h b/include/linux/mfd/da9052/eh.h
new file mode 100644
index 00000000000..c46df5d8962
--- /dev/null
+++ b/include/linux/mfd/da9052/eh.h
@@ -0,0 +1,77 @@
+/*
+ * da9052 Event Handler module declarations.
+  *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_EH_H
+#define __LINUX_MFD_DA9052_EH_H
+
+#define DA9052_EVE_REGISTERS		4
+#define DA9052_EVE_REGISTER_SIZE	8
+
+/* Define for all possible events */
+#define DCIN_DET_EVE			0
+#define VBUS_DET_EVE			1
+#define DCIN_REM_EVE			2
+#define VBUS_REM_EVE			3
+#define VDD_LOW_EVE			4
+#define ALARM_EVE			5
+#define SEQ_RDY_EVE			6
+#define COMP_1V2			7
+#define ONKEY_EVE			8
+#define ID_FLOAT_EVE			9
+#define ID_GND_EVE			10
+#define CHG_END_EVE			11
+#define TBAT_EVE			12
+#define ADC_EOM_EVE			13
+#define PEN_DOWN_EVE			14
+#define TSI_READY_EVE			15
+#define GPI0_EVE			16
+#define GPI1_EVE			17
+#define GPI2_EVE			18
+#define GPI3_EVE			19
+#define GPI4_EVE			20
+#define GPI5_EVE			21
+#define GPI6_EVE			22
+#define GPI7_EVE			23
+#define GPI8_EVE			24
+#define GPI9_EVE			25
+#define GPI10_EVE			26
+#define GPI11_EVE			27
+#define GPI12_EVE			28
+#define GPI13_EVE			29
+#define GPI14_EVE			30
+#define GPI15_EVE			31
+
+/* Total number of events */
+#define EVE_CNT				(GPI15_EVE+1)
+
+/* Error code for register/unregister functions */
+#define INVALID_NB			2
+#define INVALID_EVE			3
+
+/* State for EH thread */
+#define ACTIVE				0
+#define INACTIVE			1
+
+/* Status of nIRQ line */
+#define IRQ_HIGH			0
+#define IRQ_LOW				1
+
+#endif /* __LINUX_MFD_DA9052_EH_H */
diff --git a/include/linux/mfd/da9052/gpio.h b/include/linux/mfd/da9052/gpio.h
new file mode 100644
index 00000000000..68a24ad9d82
--- /dev/null
+++ b/include/linux/mfd/da9052/gpio.h
@@ -0,0 +1,253 @@
+/*
+ * da9052 GPIO module declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_GPIO_H
+#define __LINUX_MFD_DA9052_GPIO_H
+
+#include <linux/gpio.h>
+#define DA9052_GPIO_DEVICE_NAME			"da9052_gpio"
+
+#define DA9052_GPIO_INVALID_TYPE		1
+#define DA9052_GPIO_INVALID_MODE		2
+#define DA9052_GPIO_INVALID_PORTNUMBER		3
+#define DA9052_GPIO_INVALID_FUNCTION		4
+
+#define DA9052_GPIO_CONFIG_ADC			1
+#define DA9052_GPIO_CONFIG_TSI			2
+#define DA9052_GPIO_CONFIG_PM			3
+#define DA9052_GPIO_CONFIG_ACC_ID_DET		4
+#define DA9052_GPIO_CONFIG_GP_FB1		5
+#define DA9052_GPIO_CONFIG_VDD_FAULT		6
+#define DA9052_GPIO_CONFIG_I2C			7
+#define DA9052_GPIO_CONFIG			8
+
+/* Currently used defines for GPIO PINs  */
+#define DA9052_GPIO_PIN_0			DA9052_GPIO_CONFIG_ADC
+#define DA9052_GPIO_PIN_1			DA9052_GPIO_CONFIG_ADC
+#define DA9052_GPIO_PIN_2			DA9052_GPIO_CONFIG_ADC
+
+#define DA9052_GPIO_PIN_3			DA9052_GPIO_CONFIG_TSI
+#define DA9052_GPIO_PIN_4			DA9052_GPIO_CONFIG_TSI
+#define DA9052_GPIO_PIN_5			DA9052_GPIO_CONFIG_TSI
+#define DA9052_GPIO_PIN_6			DA9052_GPIO_CONFIG_TSI
+#define DA9052_GPIO_PIN_7			DA9052_GPIO_CONFIG_TSI
+
+#define DA9052_GPIO_PIN_8			DA9052_GPIO_CONFIG
+#define DA9052_GPIO_PIN_9			DA9052_GPIO_CONFIG
+#define DA9052_GPIO_PIN_10			DA9052_GPIO_CONFIG
+#define DA9052_GPIO_PIN_11			DA9052_GPIO_CONFIG
+
+#define DA9052_GPIO_PIN_12			DA9052_GPIO_CONFIG
+#define DA9052_GPIO_PIN_13			DA9052_GPIO_CONFIG
+
+#define DA9052_GPIO_PIN_14			DA9052_GPIO_CONFIG
+#define DA9052_GPIO_PIN_15			DA9052_GPIO_CONFIG
+
+enum ip_op_type {
+	ALTERNATE_FUNCTIONALITY = 0,
+	INPUT,
+	OUTPUT_OPENDRAIN,
+	OUTPUT_PUSHPULL
+};
+
+enum ip_type {
+	ACTIVE_LOW = 0,
+	ACTIVE_HIGH
+};
+
+enum op_type {
+	SUPPLY_VDD_IO1 = 0,
+	SUPPLY_VDD_IO2
+};
+
+
+enum op_mode {
+	OUTPUT_LOWLEVEL = 0,
+	OUTPUT_HIGHLEVEL
+};
+
+
+enum ip_mode {
+	DEBOUNCING_OFF = 0,
+	DEBOUNCING_ON
+};
+
+/*DEFAULT CONFIG FOR GPIO 0*/
+#if (DA9052_GPIO_PIN_0 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO0_FUNCTION			INPUT
+#define DEFAULT_GPIO0_TYPE			ACTIVE_LOW
+#define DEFAULT_GPIO0_MODE			DEBOUNCING_ON
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 1*/
+#if (DA9052_GPIO_PIN_1 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO1_FUNCTION			INPUT
+#define DEFAULT_GPIO1_TYPE			ACTIVE_LOW
+#define DEFAULT_GPIO1_MODE			DEBOUNCING_ON
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 2*/
+#if (DA9052_GPIO_PIN_2 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO2_FUNCTION			INPUT
+#define DEFAULT_GPIO2_TYPE			ACTIVE_LOW
+#define DEFAULT_GPIO2_MODE			DEBOUNCING_ON
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 3*/
+#if (DA9052_GPIO_PIN_3 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO3_FUNCTION			INPUT
+#define DEFAULT_GPIO3_TYPE			ACTIVE_LOW
+#define DEFAULT_GPIO3_MODE			DEBOUNCING_ON
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 4*/
+#if (DA9052_GPIO_PIN_4 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO4_FUNCTION			OUTPUT_PUSHPULL
+#define DEFAULT_GPIO4_TYPE			SUPPLY_VDD_IO1
+#define DEFAULT_GPIO4_MODE			OUTPUT_LOWLEVEL
+#endif
+/*DEFAULT CONFIG FOR GPIO 5*/
+#if (DA9052_GPIO_PIN_5 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO5_FUNCTION			OUTPUT_PUSHPULL
+#define DEFAULT_GPIO5_TYPE			SUPPLY_VDD_IO1
+#define DEFAULT_GPIO5_MODE			OUTPUT_LOWLEVEL
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 6*/
+#if (DA9052_GPIO_PIN_6 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO6_FUNCTION			OUTPUT_PUSHPULL
+#define DEFAULT_GPIO6_TYPE			SUPPLY_VDD_IO1
+#define DEFAULT_GPIO6_MODE			OUTPUT_LOWLEVEL
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 7*/
+#if (DA9052_GPIO_PIN_7 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO7_FUNCTION			OUTPUT_PUSHPULL
+#define DEFAULT_GPIO7_TYPE			SUPPLY_VDD_IO1
+#define DEFAULT_GPIO7_MODE			OUTPUT_LOWLEVEL
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 8*/
+#if (DA9052_GPIO_PIN_8 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO8_FUNCTION			INPUT
+#define DEFAULT_GPIO8_TYPE			ACTIVE_LOW
+#define DEFAULT_GPIO8_MODE			DEBOUNCING_ON
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 9*/
+#if (DA9052_GPIO_PIN_9 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO9_FUNCTION			INPUT
+#define DEFAULT_GPIO9_TYPE			ACTIVE_LOW
+#define DEFAULT_GPIO9_MODE			DEBOUNCING_ON
+#endif
+
+#if (DA9052_GPIO_PIN_10 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO10_FUNCTION			OUTPUT_PUSHPULL
+#define DEFAULT_GPIO10_TYPE			SUPPLY_VDD_IO2
+#define DEFAULT_GPIO10_MODE			OUTPUT_HIGHLEVEL
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 11 - for RTC blinking LED */
+#if (DA9052_GPIO_PIN_11 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO11_FUNCTION			OUTPUT_PUSHPULL
+#define DEFAULT_GPIO11_TYPE			SUPPLY_VDD_IO2
+#define DEFAULT_GPIO11_MODE			OUTPUT_HIGHLEVEL
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 12*/
+#if (DA9052_GPIO_PIN_12 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO12_FUNCTION			OUTPUT_PUSHPULL
+#define DEFAULT_GPIO12_TYPE			SUPPLY_VDD_IO1
+#define DEFAULT_GPIO12_MODE			OUTPUT_LOWLEVEL
+#endif
+/*DEFAULT CONFIG FOR GPIO 13*/
+#if (DA9052_GPIO_PIN_13 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO13_FUNCTION			OUTPUT_PUSHPULL
+#define DEFAULT_GPIO13_TYPE			SUPPLY_VDD_IO1
+#define DEFAULT_GPIO13_MODE			OUTPUT_LOWLEVEL
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 14 - for LED4 */
+#if (DA9052_GPIO_PIN_14 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO14_FUNCTION			OUTPUT_OPENDRAIN
+#define DEFAULT_GPIO14_TYPE			SUPPLY_VDD_IO1
+#define DEFAULT_GPIO14_MODE			OUTPUT_HIGHLEVEL
+#endif
+
+/*DEFAULT CONFIG FOR GPIO 15 - for LED5 */
+#if (DA9052_GPIO_PIN_15 == DA9052_GPIO_CONFIG)
+#define DEFAULT_GPIO15_FUNCTION			OUTPUT_OPENDRAIN
+#define DEFAULT_GPIO15_TYPE			SUPPLY_VDD_IO1
+#define DEFAULT_GPIO15_MODE			OUTPUT_HIGHLEVEL
+#endif
+
+#define DA9052_GPIO_MAX_PORTNUMBER			16
+#define DA9052_GPIO_MAX_PORTS_PER_REGISTER		8
+#define DA9052_GPIO_SHIFT_COUNT(no)			((no)%8)
+#define DA9052_GPIO_EVEN_PORT_FUNCTIONALITY		0x03
+#define DA9052_GPIO_ODD_PORT_FUNCTIONALITY		0x30
+#define DA9052_GPIO_MASK_UPPER_NIBBLE			0xF0
+#define DA9052_GPIO_MASK_LOWER_NIBBLE			0x0F
+#define DA9052_GPIO_NIBBLE_SHIFT			4
+#define DA9052_GPIO_EVEN_PORT_WRITE_MODE		(1 << 3)
+#define DA9052_GPIO_ODD_PORT_WRITE_MODE			(1 << 7)
+
+
+struct da9052_gpio_read_write {
+	u8 port_number:4;
+	u8 read_write_value:1;
+} ;
+
+struct da9052_gpio_multiple_read {
+	u8 signal_value[16];
+};
+
+struct da9052_gpi_config {
+	enum ip_type type;
+	enum ip_mode mode;
+};
+
+struct da9052_gpo_config {
+	enum op_type type;
+	enum op_mode mode;
+} ;
+
+union da9052_gpio_config {
+	struct da9052_gpi_config input;
+	struct da9052_gpo_config output;
+};
+
+struct da9052_gpio {
+	union da9052_gpio_config gpio_config;
+	enum ip_op_type gpio_function;
+	u8 port_number:4;
+};
+
+struct da9052_gpio_chip {
+	struct da9052_gpio gpio;
+	struct da9052_gpio_read_write read_write;
+	struct da9052 *da9052;
+	/* For testing*/
+	struct da9052_eh_nb eh_data;
+	struct gpio_chip gp;
+};
+
+#endif /* __LINUX_MFD_DA9052_GPIO_H */
diff --git a/include/linux/mfd/da9052/led.h b/include/linux/mfd/da9052/led.h
new file mode 100644
index 00000000000..b4145cd2023
--- /dev/null
+++ b/include/linux/mfd/da9052/led.h
@@ -0,0 +1,39 @@
+/*
+ * da9052 LED module declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_LED_H
+#define __LINUX_MFD_DA9052_LED_H
+
+struct da9052_led_platform_data {
+#define DA9052_LED_4			4
+#define DA9052_LED_5			5
+#define DA9052_LED_MAX			2
+	int id;
+	const char *name;
+	const char *default_trigger;
+};
+
+struct da9052_leds_platform_data {
+	int num_leds;
+	struct da9052_led_platform_data *led;
+};
+
+#endif /* __LINUX_MFD_DA9052_LED_H */
diff --git a/include/linux/mfd/da9052/pm.h b/include/linux/mfd/da9052/pm.h
new file mode 100644
index 00000000000..95487fdb422
--- /dev/null
+++ b/include/linux/mfd/da9052/pm.h
@@ -0,0 +1,81 @@
+/*
+ * da9052 Power Management module declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_PM_H
+#define __LINUX_MFD_DA9052_PM_H
+
+/* PM Device name and static Major number macros */
+#define DRIVER_NAME				"da9052-regulator"
+
+/* PM Device Macros */
+#define DA9052_LDO1				0
+#define DA9052_LDO2				1
+#define DA9052_LDO3				2
+#define DA9052_LDO4				3
+#define DA9052_LDO5				4
+#define DA9052_LDO6				5
+#define DA9052_LDO7				6
+#define DA9052_LDO8				7
+#define DA9052_LDO9				8
+#define DA9052_LDO10				9
+#define DA9052_BUCK_CORE			10
+#define DA9052_BUCK_PRO				11
+#define DA9052_BUCK_MEM				12
+#define DA9052_BUCK_PERI			13
+
+/* PM Device Error Codes */
+
+/* Buck Config Validation Macros */
+#define DA9052_BUCK_CORE_PRO_VOLT_UPPER		2075
+#define DA9052_BUCK_CORE_PRO_VOLT_LOWER		500
+#define DA9052_BUCK_CORE_PRO_STEP		25
+#define DA9052_BUCK_MEM_VOLT_UPPER		2500
+#define DA9052_BUCK_MEM_VOLT_LOWER		925
+#define DA9052_BUCK_MEM_STEP			25
+#if defined(CONFIG_PMIC_DA9052)
+#define DA9052_BUCK_PERI_VOLT_UPPER		3600
+#define DA9052_BUCK_PERI_VOLT_LOWER		1800
+#define DA9052_BUCK_PERI_STEP_BELOW_3000	50
+#define DA9052_BUCK_PERI_STEP_ABOVE_3000	100000
+#define DA9052_BUCK_PERI_VALUES_UPTO_3000	24
+#define DA9052_BUCK_PERI_VALUES_3000		3000000
+#elif defined(CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx)
+#define DA9052_BUCK_PERI_VOLT_UPPER		2500
+#define DA9052_BUCK_PERI_VOLT_LOWER		925
+#define DA9052_BUCK_PERI_STEP			25
+#endif
+#define DA9052_LDO1_VOLT_UPPER			1800
+#define DA9052_LDO1_VOLT_LOWER			600
+#define DA9052_LDO1_VOLT_STEP			50
+#define DA9052_LDO2_VOLT_UPPER			1800
+#define DA9052_LDO2_VOLT_LOWER			600
+#define DA9052_LDO2_VOLT_STEP			25
+#define DA9052_LDO34_VOLT_UPPER			3300
+#define DA9052_LDO34_VOLT_LOWER			1725
+#define DA9052_LDO34_VOLT_STEP			25
+#define DA9052_LDO567810_VOLT_UPPER		3600
+#define DA9052_LDO567810_VOLT_LOWER		1200
+#define DA9052_LDO567810_VOLT_STEP		50
+#define DA9052_LDO9_VOLT_STEP			50
+#define DA9052_LDO9_VOLT_LOWER			1250
+#define DA9052_LDO9_VOLT_UPPER			3650
+
+#endif /* __LINUX_MFD_DA9052_PM_H */
diff --git a/include/linux/mfd/da9052/reg.h b/include/linux/mfd/da9052/reg.h
new file mode 100644
index 00000000000..ba6ad6306a4
--- /dev/null
+++ b/include/linux/mfd/da9052/reg.h
@@ -0,0 +1,929 @@
+/*
+ * da9052 register declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_REG_H
+#define __LINUX_MFD_DA9052_REG_H
+
+#define DA9052_PAGECON0_REG			0
+#define DA9052_STATUSA_REG			1
+#define DA9052_STATUSB_REG			2
+#define DA9052_STATUSC_REG			3
+#define DA9052_STATUSD_REG			4
+#define DA9052_EVENTA_REG			5
+#define DA9052_EVENTB_REG			6
+#define DA9052_EVENTC_REG			7
+#define DA9052_EVENTD_REG			8
+#define DA9052_FAULTLOG_REG			9
+#define DA9052_IRQMASKA_REG			10
+#define DA9052_IRQMASKB_REG			11
+#define DA9052_IRQMASKC_REG			12
+#define DA9052_IRQMASKD_REG			13
+#define DA9052_CONTROLA_REG			14
+#define DA9052_CONTROLB_REG			15
+#define DA9052_CONTROLC_REG			16
+#define DA9052_CONTROLD_REG			17
+#define DA9052_PDDIS_REG			18
+#define DA9052_INTERFACE_REG			19
+#define DA9052_RESET_REG			20
+#define DA9052_GPIO0001_REG			21
+#define DA9052_GPIO0203_REG			22
+#define DA9052_GPIO0405_REG			23
+#define DA9052_GPIO0607_REG			24
+#define DA9052_GPIO0809_REG			25
+#define DA9052_GPIO1011_REG			26
+#define DA9052_GPIO1213_REG			27
+#define DA9052_GPIO1415_REG			28
+#define DA9052_ID01_REG				29
+#define DA9052_ID23_REG				30
+#define DA9052_ID45_REG				31
+#define DA9052_ID67_REG				32
+#define DA9052_ID89_REG				33
+#define DA9052_ID1011_REG			34
+#define DA9052_ID1213_REG			35
+#define DA9052_ID1415_REG			36
+#define DA9052_ID1617_REG			37
+#define DA9052_ID1819_REG			38
+#define DA9052_ID2021_REG			39
+#define DA9052_SEQSTATUS_REG			40
+#define DA9052_SEQA_REG				41
+#define DA9052_SEQB_REG				42
+#define DA9052_SEQTIMER_REG			43
+#define DA9052_BUCKA_REG			44
+#define DA9052_BUCKB_REG			45
+#define DA9052_BUCKCORE_REG			46
+#define DA9052_BUCKPRO_REG			47
+#define DA9052_BUCKMEM_REG			48
+#define DA9052_BUCKPERI_REG			49
+#define DA9052_LDO1_REG				50
+#define DA9052_LDO2_REG				51
+#define DA9052_LDO3_REG				52
+#define DA9052_LDO4_REG				53
+#define DA9052_LDO5_REG				54
+#define DA9052_LDO6_REG				55
+#define DA9052_LDO7_REG				56
+#define DA9052_LDO8_REG				57
+#define DA9052_LDO9_REG				58
+#define DA9052_LDO10_REG			59
+#define DA9052_SUPPLY_REG			60
+#define DA9052_PULLDOWN_REG			61
+#define DA9052_CHGBUCK_REG			62
+#define DA9052_WAITCONT_REG			63
+#define DA9052_ISET_REG				64
+#define DA9052_BATCHG_REG			65
+#define DA9052_CHGCONT_REG			66
+#define DA9052_INPUTCONT_REG			67
+#define DA9052_CHGTIME_REG			68
+#define DA9052_BBATCONT_REG			69
+#define DA9052_BOOST_REG			70
+#define DA9052_LEDCONT_REG			71
+#define DA9052_LEDMIN123_REG			72
+#define DA9052_LED1CONF_REG			73
+#define DA9052_LED2CONF_REG			74
+#define DA9052_LED3CONF_REG			75
+#define DA9052_LED1CONT_REG			76
+#define DA9052_LED2CONT_REG			77
+#define DA9052_LED3CONT_REG			78
+#define DA9052_LED4CONT_REG			79
+#define DA9052_LED5CONT_REG			80
+#define DA9052_ADCMAN_REG			81
+#define DA9052_ADCCONT_REG			82
+#define DA9052_ADCRESL_REG			83
+#define DA9052_ADCRESH_REG			84
+#define DA9052_VDDRES_REG			85
+#define DA9052_VDDMON_REG			86
+#define DA9052_ICHGAV_REG			87
+#define DA9052_ICHGTHD_REG			88
+#define DA9052_ICHGEND_REG			89
+#define DA9052_TBATRES_REG			90
+#define DA9052_TBATHIGHP_REG			91
+#define DA9052_TBATHIGHIN_REG			92
+#define DA9052_TBATLOW_REG			93
+#define DA9052_TOFFSET_REG			94
+#define DA9052_ADCIN4RES_REG			95
+#define DA9052_AUTO4HIGH_REG			96
+#define DA9052_AUTO4LOW_REG			97
+#define DA9052_ADCIN5RES_REG			98
+#define DA9052_AUTO5HIGH_REG			99
+#define DA9052_AUTO5LOW_REG			100
+#define DA9052_ADCIN6RES_REG			101
+#define DA9052_AUTO6HIGH_REG			102
+#define DA9052_AUTO6LOW_REG			103
+#define DA9052_TJUNCRES_REG			104
+#define DA9052_TSICONTA_REG			105
+#define DA9052_TSICONTB_REG			106
+#define DA9052_TSIXMSB_REG			107
+#define DA9052_TSIYMSB_REG			108
+#define DA9052_TSILSB_REG			109
+#define DA9052_TSIZMSB_REG			110
+#define DA9052_COUNTS_REG			111
+#define DA9052_COUNTMI_REG			112
+#define DA9052_COUNTH_REG			113
+#define DA9052_COUNTD_REG			114
+#define DA9052_COUNTMO_REG			115
+#define DA9052_COUNTY_REG			116
+#define DA9052_ALARMMI_REG			117
+#define DA9052_ALARMH_REG			118
+#define DA9052_ALARMD_REG			119
+#define DA9052_ALARMMO_REG			120
+#define DA9052_ALARMY_REG			121
+#define DA9052_SECONDA_REG			122
+#define DA9052_SECONDB_REG			123
+#define DA9052_SECONDC_REG			124
+#define DA9052_SECONDD_REG			125
+#define DA9052_PAGECON128_REG			128
+#define DA9052_CHIPID_REG			129
+#define DA9052_CONFIGID_REG			130
+#define DA9052_OTPCONT_REG			131
+#define DA9052_OSCTRIM_REG			132
+#define DA9052_GPID0_REG			133
+#define DA9052_GPID1_REG			134
+#define DA9052_GPID2_REG			135
+#define DA9052_GPID3_REG			136
+#define DA9052_GPID4_REG			137
+#define DA9052_GPID5_REG			138
+#define DA9052_GPID6_REG			139
+#define DA9052_GPID7_REG			140
+#define DA9052_GPID8_REG			141
+#define DA9052_GPID9_REG			142
+
+#define DA9052_PAGE0_REG_START			(DA9052_STATUSA_REG)
+#define DA9052_PAGE0_REG_END			(DA9052_SECONDD_REG)
+
+#define DA9052_PAGE1_REG_START			(DA9052_CHIPID_REG)
+#define DA9052_PAGE1_REG_END			(DA9052_GPID9_REG)
+
+/* PAGE CONFIGURATION */
+
+/* Reg Page Configuration */
+#define DA9052_PAGECON0_REGPAGE			(1<<7)
+
+/* PAGE CONFIGURATION 128 REGISTER */
+#define DA9052_PAGECON128_REGPAGE		(1<<7)
+
+/* SYSTEM REGISTER */
+
+/* STATUS REGISTER A */
+#define DA9052_STATUSA_VDATDET			(1<<7)
+#define DA9052_STATUSA_VBUSSEL			(1<<6)
+#define DA9052_STATUSA_DCINSEL			(1<<5)
+#define DA9052_STATUSA_VBUSDET			(1<<4)
+#define DA9052_STATUSA_DCINDET			(1<<3)
+#define DA9052_STATUSA_IDGND			(1<<2)
+#define DA9052_STATUSA_IDFLOAT			(1<<1)
+#define DA9052_STATUSA_NONKEY			(1<<0)
+
+
+/* STATUS REGISTER B */
+#define DA9052_STATUSB_COMPDET			(1<<7)
+#define DA9052_STATUSB_SEQUENCING		(1<<6)
+#define DA9052_STATUSB_GPFB2			(1<<5)
+#define DA9052_STATUSB_CHGTO			(1<<4)
+#define DA9052_STATUSB_CHGEND			(1<<3)
+#define DA9052_STATUSB_CHGLIM			(1<<2)
+#define DA9052_STATUSB_CHGPRE			(1<<1)
+#define DA9052_STATUSB_CHGATT			(1<<0)
+
+
+/* STATUS REGISTER C */
+#define DA9052_STATUSC_GPI7			(1<<7)
+#define DA9052_STATUSC_GPI6			(1<<6)
+#define DA9052_STATUSC_GPI5			(1<<5)
+#define DA9052_STATUSC_GPI4			(1<<4)
+#define DA9052_STATUSC_GPI3			(1<<3)
+#define DA9052_STATUSC_GPI2			(1<<2)
+#define DA9052_STATUSC_GPI1			(1<<1)
+#define DA9052_STATUSC_GPI0			(1<<0)
+
+
+/* STATUS REGISTER D */
+#define DA9052_STATUSD_GPI15			(1<<7)
+#define DA9052_STATUSD_GPI14			(1<<6)
+#define DA9052_STATUSD_GPI13			(1<<5)
+#define DA9052_STATUSD_GPI12			(1<<4)
+#define DA9052_STATUSD_GPI11			(1<<3)
+#define DA9052_STATUSD_GPI10			(1<<2)
+#define DA9052_STATUSD_GPI9			(1<<1)
+#define DA9052_STATUSD_GPI8			(1<<0)
+
+
+/* EVENT REGISTER A */
+#define DA9052_EVENTA_ECOMP1V2			(1<<7)
+#define DA9052_EVENTA_ESEQRDY			(1<<6)
+#define DA9052_EVENTA_EALRAM			(1<<5)
+#define DA9052_EVENTA_EVDDLOW			(1<<4)
+#define DA9052_EVENTA_EVBUSREM			(1<<3)
+#define DA9052_EVENTA_EDCINREM			(1<<2)
+#define DA9052_EVENTA_EVBUSDET			(1<<1)
+#define DA9052_EVENTA_EDCINDET			(1<<0)
+
+/* EVENT REGISTER B */
+#define DA9052_EVENTB_ETSIREADY			(1<<7)
+#define DA9052_EVENTB_EPENDOWN			(1<<6)
+#define DA9052_EVENTB_EADCEOM			(1<<5)
+#define DA9052_EVENTB_ETBAT			(1<<4)
+#define DA9052_EVENTB_ECHGEND			(1<<3)
+#define DA9052_EVENTB_EIDGND			(1<<2)
+#define DA9052_EVENTB_EIDFLOAT			(1<<1)
+#define DA9052_EVENTB_ENONKEY			(1<<0)
+
+/* EVENT REGISTER C */
+#define DA9052_EVENTC_EGPI7			(1<<7)
+#define DA9052_EVENTC_EGPI6			(1<<6)
+#define DA9052_EVENTC_EGPI5			(1<<5)
+#define DA9052_EVENTC_EGPI4			(1<<4)
+#define DA9052_EVENTC_EGPI3			(1<<3)
+#define DA9052_EVENTC_EGPI2			(1<<2)
+#define DA9052_EVENTC_EGPI1			(1<<1)
+#define DA9052_EVENTC_EGPI0			(1<<0)
+
+/* EVENT REGISTER D */
+#define DA9052_EVENTC_EGPI15			(1<<7)
+#define DA9052_EVENTC_EGPI14			(1<<6)
+#define DA9052_EVENTC_EGPI13			(1<<5)
+#define DA9052_EVENTC_EGPI12			(1<<4)
+#define DA9052_EVENTC_EGPI11			(1<<3)
+#define DA9052_EVENTC_EGPI10			(1<<2)
+#define DA9052_EVENTC_EGPI9			(1<<1)
+#define DA9052_EVENTC_EGPI8			(1<<0)
+
+
+/* FAULT LOG REGISTER */
+#define DA9052_FAULTLOG_WAITSET			(1<<7)
+#define DA9052_FAULTLOG_NSDSET			(1<<6)
+#define DA9052_FAULTLOG_KEYSHUT			(1<<5)
+#define DA9052_FAULTLOG_TEMPOVER		(1<<3)
+#define DA9052_FAULTLOG_VDDSTART		(1<<2)
+#define DA9052_FAULTLOG_VDDFAULT		(1<<1)
+#define DA9052_FAULTLOG_TWDERROR		(1<<0)
+
+/* IRQ_MASK REGISTER A */
+#define DA9052_IRQMASKA_MCOMP1V2		(1<<7)
+#define DA9052_IRQMASKA_MSEQRDY			(1<<6)
+#define DA9052_IRQMASKA_MALRAM			(1<<5)
+#define DA9052_IRQMASKA_MVDDLOW			(1<<4)
+#define DA9052_IRQMASKA_MVBUSREM		(1<<3)
+#define DA9052_IRQMASKA_MDCINREM		(1<<2)
+#define DA9052_IRQMASKA_MVBUSVLD		(1<<1)
+#define DA9052_IRQMASKA_MDCINVLD		(1<<0)
+
+/* IRQ_MASK REGISTER B */
+#define DA9052_IRQMASKB_MTSIREADY		(1<<7)
+#define DA9052_IRQMASKB_MPENDOWN		(1<<6)
+#define DA9052_IRQMASKB_MADCEOM			(1<<5)
+#define DA9052_IRQMASKB_MTBAT			(1<<4)
+#define DA9052_IRQMASKB_MCHGEND			(1<<3)
+#define DA9052_IRQMASKB_MIDGND			(1<<2)
+#define DA9052_IRQMASKB_MIDFLOAT		(1<<1)
+#define DA9052_IRQMASKB_MNONKEY			(1<<0)
+
+/* IRQ_MASK REGISTER C */
+#define DA9052_IRQMASKC_MGPI7			(1<<7)
+#define DA9052_IRQMASKC_MGPI6			(1<<6)
+#define DA9052_IRQMASKC_MGPI5			(1<<5)
+#define DA9052_IRQMASKC_MGPI4			(1<<4)
+#define DA9052_IRQMASKC_MGPI3			(1<<3)
+#define DA9052_IRQMASKC_MGPI2			(1<<2)
+#define DA9052_IRQMASKC_MGPI1			(1<<1)
+#define DA9052_IRQMASKC_MGPI0			(1<<0)
+
+/* IRQ_MASK REGISTER D */
+#define DA9052_IRQMASKD_MGPI15			(1<<7)
+#define DA9052_IRQMASKD_MGPI14			(1<<6)
+#define DA9052_IRQMASKD_MGPI13			(1<<5)
+#define DA9052_IRQMASKD_MGPI12			(1<<4)
+#define DA9052_IRQMASKD_MGPI11			(1<<3)
+#define DA9052_IRQMASKD_MGPI10			(1<<2)
+#define DA9052_IRQMASKD_MGPI9			(1<<1)
+#define DA9052_IRQMASKD_MGPI8			(1<<0)
+
+/* CONTROL REGISTER A */
+#define DA9052_CONTROLA_GPIV			(1<<7)
+#define DA9052_CONTROLA_PMOTYPE			(1<<5)
+#define DA9052_CONTROLA_PMOV			(1<<4)
+#define DA9052_CONTROLA_PMIV			(1<<3)
+#define DA9052_CONTROLA_PMIFV			(1<<3)
+#define DA9052_CONTROLA_PWR1EN			(1<<2)
+#define DA9052_CONTROLA_PWREN			(1<<1)
+#define DA9052_CONTROLA_SYSEN			(1<<0)
+
+/* CONTROL REGISTER B */
+#define DA9052_CONTROLB_SHUTDOWN		(1<<7)
+#define DA9052_CONTROLB_DEEPSLEEP		(1<<6)
+#define DA9052_CONTROLB_WRITEMODE		(1<<5)
+#define DA9052_CONTROLB_BBATEN			(1<<4)
+#define DA9052_CONTROLB_OTPREADEN		(1<<3)
+#define DA9052_CONTROLB_AUTOBOOT		(1<<2)
+#define DA9052_CONTROLB_ACTDIODE		(1<<1)
+#define DA9052_CONTROLB_BUCKMERGE		(1<<0)
+
+/* CONTROL REGISTER C */
+#define DA9052_CONTROLC_BLINKDUR		(1<<7)
+#define DA9052_CONTROLC_BLINKFRQ		(3<<5)
+#define DA9052_CONTROLC_DEBOUNCING		(7<<2)
+#define DA9052_CONTROLC_PMFB2PIN		(1<<1)
+#define DA9052_CONTROLC_PMFB1PIN		(1<<0)
+
+/* CONTROL REGISTER D */
+#define DA9052_CONTROLD_WATCHDOG		(1<<7)
+#define DA9052_CONTROLD_ACCDETEN		(1<<6)
+#define DA9052_CONTROLD_GPI1415SD		(1<<5)
+#define DA9052_CONTROLD_NONKEYSD		(1<<4)
+#define DA9052_CONTROLD_KEEPACTEN		(1<<3)
+#define DA9052_CONTROLD_TWDSCALE		(7<<0)
+
+/* POWER DOWN DISABLE REGISTER */
+#define DA9052_PDDIS_PMCONTPD			(1<<7)
+#define DA9052_PDDIS_OUT32KPD			(1<<6)
+#define DA9052_PDDIS_CHGBBATPD			(1<<5)
+#define DA9052_PDDIS_CHGPD			(1<<4)
+#define DA9052_PDDIS_HS2WIREPD			(1<<3)
+#define DA9052_PDDIS_PMIFPD			(1<<2)
+#define DA9052_PDDIS_GPADCPD			(1<<1)
+#define DA9052_PDDIS_GPIOPD			(1<<0)
+
+/* CONTROL REGISTER D */
+#define DA9052_INTERFACE_IFBASEADDR		(7<<5)
+#define DA9052_INTERFACE_NCSPOL			(1<<4)
+#define DA9052_INTERFACE_RWPOL			(1<<3)
+#define DA9052_INTERFACE_CPHA			(1<<2)
+#define DA9052_INTERFACE_CPOL			(1<<1)
+#define DA9052_INTERFACE_IFTYPE			(1<<0)
+
+/* CONTROL REGISTER D */
+#define DA9052_RESET_RESETEVENT			(3<<6)
+#define DA9052_RESET_RESETTIMER			(63<<0)
+
+/* GPIO REGISTERS */
+
+/* GPIO control register for PIN 0 and 1 */
+#define DA9052_GPIO0001_GPIO1MODE		(1<<7)
+#define DA9052_GPIO0001_GPIO1TYPE		(1<<6)
+#define DA9052_GPIO0001_GPIO1PIN		(3<<4)
+#define DA9052_GPIO0001_GPIO0MODE		(1<<3)
+#define DA9052_GPIO0001_GPIO0TYPE		(1<<2)
+#define DA9052_GPIO0001_GPIO0PIN		(3<<0)
+
+/* GPIO control register for PIN 2 and 3 */
+#define DA9052_GPIO0203_GPIO3MODE		(1<<7)
+#define DA9052_GPIO0203_GPIO3TYPE		(1<<6)
+#define DA9052_GPIO0203_GPIO3PIN		(3<<4)
+#define DA9052_GPIO0203_GPIO2MODE		(1<<3)
+#define DA9052_GPIO0203_GPIO2TYPE		(1<<2)
+#define DA9052_GPIO0203_GPIO2PIN		(3<<0)
+
+/* GPIO control register for PIN 4 and 5 */
+#define DA9052_GPIO0405_GPIO5MODE		(1<<7)
+#define DA9052_GPIO0405_GPIO5TYPE		(1<<6)
+#define DA9052_GPIO0405_GPIO5PIN		(3<<4)
+#define DA9052_GPIO0405_GPIO4MODE		(1<<3)
+#define DA9052_GPIO0405_GPIO4TYPE		(1<<2)
+#define DA9052_GPIO0405_GPIO4PIN		(3<<0)
+
+/* GPIO control register for PIN 6 and 7 */
+#define DA9052_GPIO0607_GPIO7MODE		(1<<7)
+#define DA9052_GPIO0607_GPIO7TYPE		(1<<6)
+#define DA9052_GPIO0607_GPIO7PIN		(3<<4)
+#define DA9052_GPIO0607_GPIO6MODE		(1<<3)
+#define DA9052_GPIO0607_GPIO6TYPE		(1<<2)
+#define DA9052_GPIO0607_GPIO6PIN		(3<<0)
+
+/* GPIO control register for PIN 8 and 9 */
+#define DA9052_GPIO0809_GPIO9MODE		(1<<7)
+#define DA9052_GPIO0809_GPIO9TYPE		(1<<6)
+#define DA9052_GPIO0809_GPIO9PIN		(3<<4)
+#define DA9052_GPIO0809_GPIO8MODE		(1<<3)
+#define DA9052_GPIO0809_GPIO8TYPE		(1<<2)
+#define DA9052_GPIO0809_GPIO8PIN		(3<<0)
+
+/* GPIO control register for PIN 10 and 11 */
+#define DA9052_GPIO1011_GPIO11MODE		(1<<7)
+#define DA9052_GPIO1011_GPIO11TYPE		(1<<6)
+#define DA9052_GPIO1011_GPIO11PIN		(3<<4)
+#define DA9052_GPIO1011_GPIO10MODE		(1<<3)
+#define DA9052_GPIO1011_GPIO10TYPE		(1<<2)
+#define DA9052_GPIO1011_GPIO10PIN		(3<<0)
+
+/* GPIO control register for PIN 12 and 13 */
+#define DA9052_GPIO1213_GPIO13MODE		(1<<7)
+#define DA9052_GPIO1213_GPIO13TYPE		(1<<6)
+#define DA9052_GPIO1213_GPIO13PIN		(3<<4)
+#define DA9052_GPIO1213_GPIO12MODE		(1<<3)
+#define DA9052_GPIO1213_GPIO12TYPE		(1<<2)
+#define DA9052_GPIO1213_GPIO12PIN		(3<<0)
+
+/* GPIO control register for PIN 14 and 15 */
+#define DA9052_GPIO1415_GPIO15MODE		(1<<7)
+#define DA9052_GPIO1415_GPIO15TYPE		(1<<6)
+#define DA9052_GPIO1415_GPIO15PIN		(3<<4)
+#define DA9052_GPIO1415_GPIO14MODE		(1<<3)
+#define DA9052_GPIO1415_GPIO14TYPE		(1<<2)
+#define DA9052_GPIO1415_GPIO14PIN		(3<<0)
+
+/*POWER SEQUENCER REGISTER*/
+
+/* SEQ control register for ID 0 and 1 */
+#define DA9052_ID01_LDO1STEP			(15<<4)
+#define DA9052_ID01_SYSPRE			(1<<2)
+#define DA9052_ID01_DEFSUPPLY			(1<<1)
+#define DA9052_ID01_nRESMODE			(1<<0)
+
+/* SEQ control register for ID 2 and 3 */
+#define DA9052_ID23_LDO3STEP			(15<<4)
+#define DA9052_ID23_LDO2STEP			(15<<0)
+
+/* SEQ control register for ID 4 and 5 */
+#define DA9052_ID45_LDO5STEP			(15<<4)
+#define DA9052_ID45_LDO4STEP			(15<<0)
+
+/* SEQ control register for ID 6 and 7 */
+#define DA9052_ID67_LDO7STEP			(15<<4)
+#define DA9052_ID67_LDO6STEP			(15<<0)
+
+/* SEQ control register for ID 8 and 9 */
+#define DA9052_ID89_LDO9STEP			(15<<4)
+#define DA9052_ID89_LDO8STEP			(15<<0)
+
+/* SEQ control register for ID 10 and 11 */
+#define DA9052_ID1011_PDDISSTEP			(15<<4)
+#define DA9052_ID1011_LDO10STEP			(15<<0)
+
+/* SEQ control register for ID 12 and 13 */
+#define DA9052_ID1213_VMEMSWSTEP		(15<<4)
+#define DA9052_ID1213_VPERISWSTEP		(15<<0)
+
+/* SEQ control register for ID 14 and 15 */
+#define DA9052_ID1415_BUCKPROSTEP		(15<<4)
+#define DA9052_ID1415_BUCKCORESTEP		(15<<0)
+
+/* SEQ control register for ID 16 and 17 */
+#define DA9052_ID1617_BUCKPERISTEP		(15<<4)
+#define DA9052_ID1617_BUCKMEMSTEP		(15<<0)
+
+/* SEQ control register for ID 18 and 19 */
+#define DA9052_ID1819_GPRISE2STEP		(15<<4)
+#define DA9052_ID1819_GPRISE1STEP		(15<<0)
+
+/* SEQ control register for ID 20 and 21 */
+#define DA9052_ID2021_GPFALL2STEP		(15<<4)
+#define DA9052_ID2021_GPFALL1STEP		(15<<0)
+
+/* Power SEQ Status register */
+#define DA9052_SEQSTATUS_SEQPOINTER		(15<<4)
+#define DA9052_SEQSTATUS_WAITSTEP		(15<<0)
+
+/* Power SEQ A register */
+#define DA9052_SEQA_POWEREND			(15<<4)
+#define DA9052_SEQA_SYSTEMEND			(15<<0)
+
+/* Power SEQ B register */
+#define DA9052_SEQB_PARTDOWN			(15<<4)
+#define DA9052_SEQB_MAXCOUNT			(15<<0)
+
+/* Power SEQ TIMER register */
+#define DA9052_SEQTIMER_SEQDUMMY		(15<<4)
+#define DA9052_SEQTIMER_SEQTIME			(15<<0)
+
+/*POWER SUPPLY CONTROL REGISTER*/
+
+/* BUCK REGISTER A */
+#define DA9052_BUCKA_BPROILIM			(3<<6)
+#define DA9052_BUCKA_BPROMODE			(3<<4)
+#define DA9052_BUCKA_BCOREILIM			(3<<2)
+#define DA9052_BUCKA_BCOREMODE			(3<<0)
+
+/* BUCK REGISTER B */
+#define DA9052_BUCKB_BERIILIM			(3<<6)
+#define DA9052_BUCKB_BPERIMODE			(3<<4)
+#define DA9052_BUCKB_BMEMILIM			(3<<2)
+#define DA9052_BUCKB_BMEMMODE			(3<<0)
+
+/* BUCKCORE REGISTER */
+#define DA9052_BUCKCORE_BCORECONF		(1<<7)
+#define DA9052_BUCKCORE_BCOREEN			(1<<6)
+#define DA9052_BUCKCORE_VBCORE			(63<<0)
+
+/* BUCKPRO REGISTER */
+#define DA9052_BUCKPRO_BPROCONF			(1<<7)
+#define DA9052_BUCKPRO_BPROEN			(1<<6)
+#define DA9052_BUCKPRO_VBPRO			(63<<0)
+
+/* BUCKMEM REGISTER */
+#define DA9052_BUCKMEM_BMEMCONF			(1<<7)
+#define DA9052_BUCKMEM_BMEMEN			(1<<6)
+#define DA9052_BUCKMEM_VBMEM			(63<<0)
+
+/* BUCKPERI REGISTER */
+#define DA9052_BUCKPERI_BPERICONF		(1<<7)
+#define DA9052_BUCKPERI_BPERIEN			(1<<6)
+#if defined(CONFIG_PMIC_DA9052)
+#define DA9052_BUCKPERI_BPERIHS			(1<<5)
+#define DA9052_BUCKPERI_VBPERI			(31<<0)
+#elif defined(CONFIG_PMIC_DA9053AA) || (CONFIG_PMIC_DA9053Bx)
+#define DA9052_BUCKPERI_VBPERI			(63<<0)
+#endif
+
+/* LDO1 REGISTER */
+#define DA9052_LDO1_LDO1CONF			(1<<7)
+#define DA9052_LDO1_LDO1EN			(1<<6)
+#define DA9052_LDO1_VLDO1			(31<<0)
+
+/* LDO2 REGISTER */
+#define DA9052_LDO2_LDO2CONF			(1<<7)
+#define DA9052_LDO2_LDO2EN			(1<<6)
+#define DA9052_LDO2_VLDO2			(63<<0)
+
+/* LDO3 REGISTER */
+#define DA9052_LDO3_LDO3CONF			(1<<7)
+#define DA9052_LDO3_LDO3EN			(1<<6)
+#define DA9052_LDO3_VLDO3			(63<<0)
+
+/* LDO4 REGISTER */
+#define DA9052_LDO4_LDO4CONF			(1<<7)
+#define DA9052_LDO4_LDO4EN			(1<<6)
+#define DA9052_LDO4_VLDO4			(63<<0)
+
+/* LDO5 REGISTER */
+#define DA9052_LDO5_LDO5CONF			(1<<7)
+#define DA9052_LDO5_LDO5EN			(1<<6)
+#define DA9052_LDO5_VLDO5			(63<<0)
+
+/* LDO6 REGISTER */
+#define DA9052_LDO6_LDO6CONF			(1<<7)
+#define DA9052_LDO6_LDO6EN			(1<<6)
+#define DA9052_LDO6_VLDO6			(63<<0)
+
+/* LDO7 REGISTER */
+#define DA9052_LDO7_LDO7CONF			(1<<7)
+#define DA9052_LDO7_LDO7EN			(1<<6)
+#define DA9052_LDO7_VLDO7			(63<<0)
+
+/* LDO8 REGISTER */
+#define DA9052_LDO8_LDO8CONF			(1<<7)
+#define DA9052_LDO8_LDO8EN			(1<<6)
+#define DA9052_LDO8_VLDO8			(63<<0)
+
+/* LDO9 REGISTER */
+#define DA9052_LDO9_LDO9CONF			(1<<7)
+#define DA9052_LDO9_LDO9EN			(1<<6)
+#define DA9052_LDO9_VLDO9			(63<<0)
+
+/* LDO10 REGISTER */
+#define DA9052_LDO10_LDO10CONF			(1<<7)
+#define DA9052_LDO10_LDO10EN			(1<<6)
+#define DA9052_LDO10_VLDO10			(63<<0)
+
+/* SUPPLY REGISTER */
+#define DA9052_SUPPLY_VLOCK			(1<<7)
+#define DA9052_SUPPLY_VMEMSWEN			(1<<6)
+#define DA9052_SUPPLY_VPERISWEN			(1<<5)
+#define DA9052_SUPPLY_VLDO3GO			(1<<4)
+#define DA9052_SUPPLY_VLDO2GO			(1<<3)
+#define DA9052_SUPPLY_VBMEMGO			(1<<2)
+#define DA9052_SUPPLY_VBPROGO			(1<<1)
+#define DA9052_SUPPLY_VBCOREGO			(1<<0)
+
+/* PULLDOWN REGISTER */
+#define DA9052_PULLDOWN_LDO5PDDIS		(1<<5)
+#define DA9052_PULLDOWN_LDO2PDDIS		(1<<4)
+#define DA9052_PULLDOWN_LDO1PDDIS		(1<<3)
+#define DA9052_PULLDOWN_MEMPDDIS		(1<<2)
+#define DA9052_PULLDOWN_PROPDDIS		(1<<1)
+#define DA9052_PULLDOWN_COREPDDIS		(1<<0)
+
+/* BAT CHARGER REGISTER */
+
+/* CHARGER BUCK REGISTER */
+#define DA9052_CHGBUCK_CHGTEMP			(1<<7)
+#define DA9052_CHGBUCK_CHGUSBILIM		(1<<6)
+#define DA9052_CHGBUCK_CHGBUCKLP		(1<<5)
+#define DA9052_CHGBUCK_CHGBUCKEN		(1<<4)
+#define DA9052_CHGBUCK_ISETBUCK			(15<<0)
+
+/* WAIT COUNTER REGISTER */
+#define DA9052_WAITCONT_WAITDIR			(1<<7)
+#define DA9052_WAITCONT_RTCCLOCK		(1<<6)
+#define DA9052_WAITCONT_WAITMODE		(1<<5)
+#define DA9052_WAITCONT_EN32KOUT		(1<<4)
+#define DA9052_WAITCONT_DELAYTIME		(15<<0)
+
+/* ISET CONTROL REGISTER */
+#define DA9052_ISET_ISETDCIN			(15<<4)
+#define DA9052_ISET_ISETVBUS			(15<<0)
+
+/* BATTERY CHARGER CONTROL REGISTER */
+#define DA9052_BATCHG_ICHGPRE			(3<<6)
+#define DA9052_BATCHG_ICHGBAT			(63<<0)
+
+/* CHARGER COUNTER REGISTER */
+#define DA9052_CHGCONT_VCHGBAT			(31<<3)
+#define DA9052_CHGCONT_TCTR			(7<<0)
+
+/* INPUT CONTROL REGISTER */
+#define DA9052_INPUTCONT_TCTRMODE		(1<<7)
+#define DA9052_INPUTCONT_ICHGLOW		(1<<5)
+#define DA9052_INPUTCONT_VBUSSUSP		(1<<4)
+#define DA9052_INPUTCONT_DCINSUSP		(1<<3)
+#define DA9052_INPUTCONT_VCHGTHR		(7<<0)
+
+/* CHARGING TIME REGISTER */
+#define DA9052_CHGTIME_CHGTIME			(255<<0)
+
+/* BACKUP BATTERY CONTROL REGISTER */
+#define DA9052_BBATCONT_BCHARGERISET		(15<<4)
+#define DA9052_BBATCONT_BCHARGERVSET		(15<<0)
+
+/* LED REGISTERS */
+
+/* LED BOOST REGISTER */
+#define DA9052_BOOST_EBFAULT			(1<<7)
+#define DA9052_BOOST_MBFAULT			(1<<6)
+#define DA9052_BOOST_BOOSTFRQ			(1<<5)
+#define DA9052_BOOST_BOOSTILIM			(1<<4)
+#define DA9052_BOOST_LED3INEN			(1<<3)
+#define DA9052_BOOST_LED2INEN			(1<<2)
+#define DA9052_BOOST_LED1INEN			(1<<1)
+#define DA9052_BOOST_BOOSTEN			(1<<0)
+
+/* LED COUNT REGISTER */
+#if defined(CONFIG_PMIC_DA9053Bx)
+#define DA9052_LEDCONT_SELLEDMODE		(1<<7)
+#endif
+#define DA9052_LEDCONT_LED3ICONT		(1<<6)
+#define DA9052_LEDCONT_LED3RAMP			(1<<5)
+#define DA9052_LEDCONT_LED3EN			(1<<4)
+#define DA9052_LEDCONT_LED2RAMP			(1<<3)
+#define DA9052_LEDCONT_LED2EN			(1<<2)
+#define DA9052_LEDCONT_LED1RAMP			(1<<1)
+#define DA9052_LEDCONT_LED1EN			(1<<0)
+
+/* LEDMIN123  REGISTER */
+#define DA9052_LEDMIN123_LEDMINCURRENT		(255<<0)
+
+/* LED1CONF  REGISTER */
+#define DA9052_LED1CONF_LED1CURRENT		(255<<0)
+
+/* LED2CONF  REGISTER */
+#define DA9052_LED2CONF_LED2CURRENT		(255<<0)
+
+/* LED3CONF  REGISTER */
+#define DA9052_LED3CONF_LED3CURRENT		(255<<0)
+
+/* LED1 COUNT  REGISTER */
+#define DA9052_LED1CONT_LED1DIM			(1<<7)
+#define DA9052_LED1CONT_LED1PWM			(127<<0)
+
+/* LED2 COUNT  REGISTER */
+#define DA9052_LED2CONT_LED2DIM			(1<<7)
+#define DA9052_LED2CONT_LED2PWM			(127<<0)
+
+/* LED3 COUNT  REGISTER */
+#define DA9052_LED3CONT_LED3DIM			(1<<7)
+#define DA9052_LED3CONT_LED3PWM			(127<<0)
+
+/* LED4 COUNT  REGISTER */
+#define DA9052_LED4CONT_LED4DIM			(1<<7)
+#define DA9052_LED4CONT_LED4PWM			(127<<0)
+
+/* LED5 COUNT  REGISTER */
+#define DA9052_LED5CONT_LED5DIM			(1<<7)
+#define DA9052_LED5CONT_LED5PWM			(127<<0)
+
+/* ADC REGISTERS */
+
+/* ADC MAN registers */
+#define DA9052_ADCMAN_MANCONV			(1<<4)
+#define DA9052_ADCMAN_MUXSEL			(15<<0)
+
+/* ADC COUNT regsisters */
+#define DA9052_ADCCONT_COMP1V2EN		(1<<7)
+#define DA9052_ADCCONT_ADCMODE			(1<<6)
+#define DA9052_ADCCONT_TBATISRCEN		(1<<5)
+#define DA9052_ADCCONT_AD4ISRCEN		(1<<4)
+#define DA9052_ADCCONT_AUTOAD6EN		(1<<3)
+#define DA9052_ADCCONT_AUTOAD5EN		(1<<2)
+#define DA9052_ADCCONT_AUTOAD4EN		(1<<1)
+#define DA9052_ADCCONT_AUTOVDDEN		(1<<0)
+
+/* ADC 10 BIT MANUAL CONVERSION RESULT LOW register */
+#define DA9052_ADCRESL_ADCRESLSB		(3<<0)
+
+/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH register */
+#define DA9052_ADCRESH_ADCRESMSB		(255<<0)
+
+/* VDD RES regsister*/
+#define DA9052_VDDRES_VDDOUTRES			(255<<0)
+
+/* VDD MON regsister*/
+#define DA9052_VDDMON_VDDOUTMON			(255<<0)
+
+/* ICHG_AV regsister*/
+#define DA9052_ICHGAV_ICHGAV			(255<<0)
+
+/* ICHG_THD regsister*/
+#define DA9052_ICHGTHD_ICHGTHD			(255<<0)
+
+/* ICHG_END regsister*/
+#define DA9052_ICHGEND_ICHGEND			(255<<0)
+
+/* TBAT_RES regsister*/
+#define DA9052_TBATRES_TBATRES			(255<<0)
+
+/* TBAT_HIGHP regsister*/
+#define DA9052_TBATHIGHP_TBATHIGHP		(255<<0)
+
+/* TBAT_HIGHN regsister*/
+#define DA9052_TBATHIGHN_TBATHIGHN		(255<<0)
+
+/* TBAT_LOW regsister*/
+#define DA9052_TBATLOW_TBATLOW			(255<<0)
+
+/* T_OFFSET regsister*/
+#define DA9052_TOFFSET_TOFFSET			(255<<0)
+
+/* ADCIN4_RES regsister*/
+#define DA9052_ADCIN4RES_ADCIN4RES		(255<<0)
+
+/* ADCIN4_HIGH regsister*/
+#define DA9052_AUTO4HIGH_AUTO4HIGH		(255<<0)
+
+/* ADCIN4_LOW regsister*/
+#define DA9052_AUTO4LOW_AUTO4LOW		(255<<0)
+
+/* ADCIN5_RES regsister*/
+#define DA9052_ADCIN5RES_ADCIN5RES		(255<<0)
+
+/* ADCIN5_HIGH regsister*/
+#define DA9052_AUTO5HIGH_AUTOHIGH		(255<<0)
+
+/* ADCIN5_LOW regsister*/
+#define DA9052_AUTO5LOW_AUTO5LOW		(255<<0)
+
+/* ADCIN6_RES regsister*/
+#define DA9052_ADCIN6RES_ADCIN6RES		(255<<0)
+
+/* ADCIN6_HIGH regsister*/
+#define DA9052_AUTO6HIGH_AUTO6HIGH		(255<<0)
+
+/* ADCIN6_LOW regsister*/
+#define DA9052_AUTO6LOW_AUTO6LOW		(255<<0)
+
+/* TJUNC_RES regsister*/
+#define DA9052_TJUNCRES_TJUNCRES		(255<<0)
+
+/* TSI REGISTER */
+
+/* TSI Control Register A */
+#define DA9052_TSICONTA_TSIDELAY		(3<<6)
+#define DA9052_TSICONTA_TSISKIP			(7<<3)
+#define DA9052_TSICONTA_TSIMODE			(1<<2)
+#define DA9052_TSICONTA_PENDETEN		(1<<1)
+#define DA9052_TSICONTA_AUTOTSIEN		(1<<0)
+
+/* TSI Control Register B */
+#define DA9052_TSICONTB_ADCREF			(1<<7)
+#define DA9052_TSICONTB_TSIMAN			(1<<6)
+#define DA9052_TSICONTB_TSIMUX			(3<<4)
+#define DA9052_TSICONTB_TSISEL3			(1<<3)
+#define DA9052_TSICONTB_TSISEL2			(1<<2)
+#define DA9052_TSICONTB_TSISEL1			(1<<1)
+#define DA9052_TSICONTB_TSISEL0			(1<<0)
+
+/* TSI X Co-ordinate MSB Result register */
+#define DA9052_TSIXMSB_TSIXM			(255<<0)
+
+/* TSI Y Co-ordinate MSB Result register */
+#define DA9052_TSIYMSB_TSIYM			(255<<0)
+
+/* TSI Co-ordinate LSB Result register */
+#define DA9052_TSILSB_PENDOWN			(1<<6)
+#define DA9052_TSILSB_TSIZL			(3<<4)
+#define DA9052_TSILSB_TSIYL			(3<<2)
+#define DA9052_TSILSB_TSIXL			(3<<0)
+
+/* TSI Z Measurement MSB Result register */
+#define DA9052_TSIZMSB_TSIZM			(255<<0)
+
+/* RTC REGISTER */
+
+/* RTC TIMER SECONDS REGISTER */
+#define DA9052_COUNTS_MONITOR			(1<<6)
+#define DA9052_COUNTS_COUNTSEC			(63<<0)
+
+/* RTC TIMER MINUTES REGISTER */
+#define DA9052_COUNTMI_COUNTMIN			(63<<0)
+
+/* RTC TIMER HOUR REGISTER */
+#define DA9052_COUNTH_COUNTHOUR			(31<<0)
+
+/* RTC TIMER DAYS REGISTER */
+#define DA9052_COUNTD_COUNTDAY			(31<<0)
+
+/* RTC TIMER MONTHS REGISTER */
+#define DA9052_COUNTMO_COUNTMONTH		(15<<0)
+
+/* RTC TIMER YEARS REGISTER */
+#define DA9052_COUNTY_COUNTYEAR			(63<<0)
+
+/* RTC ALARM MINUTES REGISTER */
+#define DA9052_ALARMMI_TICKTYPE			(1<<7)
+#define DA9052_ALARMMI_ALARMTYPE		(1<<6)
+#define DA9052_ALARMMI_ALARMMIN			(63<<0)
+
+/* RTC ALARM HOURS REGISTER */
+#define DA9052_ALARMH_ALARMHOUR			(31<<0)
+
+/* RTC ALARM DAYS REGISTER */
+#define DA9052_ALARMD_ALARMDAY			(31<<0)
+
+/* RTC ALARM MONTHS REGISTER */
+#define DA9052_ALARMMO_ALARMMONTH		(15<<0)
+
+/* RTC ALARM YEARS REGISTER */
+#define DA9052_ALARMY_TICKON			(1<<7)
+#define DA9052_ALARMY_ALARMON			(1<<6)
+#define DA9052_ALARMY_ALARMYEAR			(63<<0)
+
+/* RTC SECONDS REGISTER  A*/
+#define DA9052_SECONDA_SECONDSA			(255<<0)
+
+/* RTC SECONDS REGISTER  B*/
+#define DA9052_SECONDB_SECONDSB			(255<<0)
+
+/* RTC SECONDS REGISTER  C*/
+#define DA9052_SECONDC_SECONDSC			(255<<0)
+
+/* RTC SECONDS REGISTER  D*/
+#define DA9052_SECONDD_SECONDSD			(255<<0)
+
+/* OTP REGISTER */
+
+/* CHIP IDENTIFICATION REGISTER */
+#define DA9052_CHIPID_MRC			(15<<4)
+#define DA9052_CHIPID_TRC			(15<<0)
+
+/* CONFIGURATION IDENTIFICATION REGISTER */
+#define DA9052_CONFIGID_CUSTOMERID		(31<<3)
+#define DA9052_CONFIGID_CONFID			(7<<0)
+
+/* OTP CONTROL REGISTER */
+#define DA9052_OTPCONT_GPWRITEDIS		(1<<7)
+#define DA9052_OTPCONT_OTPCONFLOCK		(1<<6)
+#define DA9052_OTPCONT_OTPGPLOCK		(1<<5)
+#define DA9052_OTPCONT_OTPCONFG			(1<<3)
+#define DA9052_OTPCONT_OTPGP			(1<<2)
+#define DA9052_OTPCONT_OTPRP			(1<<1)
+#define DA9052_OTPCONT_OTPTRANSFER		(1<<0)
+
+/* RTC OSCILLATOR TRIM REGISTER */
+#define DA9052_OSCTRIM_TRIM32K			(255<<0)
+
+/* GP ID REGISTER 0 */
+#define DA9052_GPID0_GP0			(255<<0)
+
+/* GP ID REGISTER 1 */
+#define DA9052_GPID1_GP1			(255<<0)
+
+/* GP ID REGISTER 2 */
+#define DA9052_GPID2_GP2			(255<<0)
+
+/* GP ID REGISTER 3 */
+#define DA9052_GPID3_GP3			(255<<0)
+
+/* GP ID REGISTER 4 */
+#define DA9052_GPID4_GP4			(255<<0)
+
+/* GP ID REGISTER 5 */
+#define DA9052_GPID5_GP5			(255<<0)
+
+/* GP ID REGISTER 6 */
+#define DA9052_GPID6_GP6			(255<<0)
+
+/* GP ID REGISTER 7 */
+#define DA9052_GPID7_GP7			(255<<0)
+
+/* GP ID REGISTER 8 */
+#define DA9052_GPID8_GP8			(255<<0)
+
+/* GP ID REGISTER 9 */
+#define DA9052_GPID9_GP9			(255<<0)
+
+#endif
+/* __LINUX_MFD_DA9052_REG_H */
diff --git a/include/linux/mfd/da9052/rtc.h b/include/linux/mfd/da9052/rtc.h
new file mode 100644
index 00000000000..2057e9e001d
--- /dev/null
+++ b/include/linux/mfd/da9052/rtc.h
@@ -0,0 +1,322 @@
+/*
+ * da9052 RTC module declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_RTC_H
+#define __LINUX_MFD_DA9052_RTC_H
+
+#define DA9052_RTC_DEVICE_NAME				"da9052_rtc"
+
+/*  Limit values */
+#define DA9052_RTC_SECONDS_LIMIT			59
+#define DA9052_RTC_MINUTES_LIMIT			59
+#define DA9052_RTC_HOURS_LIMIT				23
+#define DA9052_RTC_DAYS_LIMIT				31
+#define DA9052_RTC_MONTHS_LIMIT				12
+#define DA9052_RTC_YEARS_LIMIT				63
+
+/* Months */
+#define FEBRUARY					2
+#define APRIL						4
+#define JUNE						6
+#define	SEPTEMBER					9
+#define NOVEMBER					11
+
+/* BYTE shifts */
+#define DA9052_RTC_FOURTH_BYTE				24
+#define DA9052_RTC_THIRD_BYTE				16
+#define DA9052_RTC_SECOND_BYTE				8
+#define DA9052_RTC_FIRST_BYTE				0
+
+/* Oscillator trim values */
+#define DA9052_RTC_OSC_FRQ_0_0ppm			0
+#define DA9052_RTC_OSC_FRQ_1_9ppm			1
+#define DA9052_RTC_OSC_FRQ_3_8ppm			2
+#define DA9052_RTC_OSC_FRQ_5_7ppm			3
+#define DA9052_RTC_OSC_FRQ_7_6ppm			4
+#define DA9052_RTC_OSC_FRQ_9_5ppm			5
+#define DA9052_RTC_OSC_FRQ_11_4ppm			6
+#define DA9052_RTC_OSC_FRQ_13_3ppm			7
+#define DA9052_RTC_OSC_FRQ_15_2ppm			8
+#define DA9052_RTC_OSC_FRQ_17_1ppm			9
+#define DA9052_RTC_OSC_FRQ_19_0ppm			10
+#define DA9052_RTC_OSC_FRQ_20_9ppm			11
+#define DA9052_RTC_OSC_FRQ_22_8ppm			12
+#define DA9052_RTC_OSC_FRQ_24_7ppm			13
+#define DA9052_RTC_OSC_FRQ_26_7ppm			14
+#define DA9052_RTC_OSC_FRQ_28_6ppm			15
+#define DA9052_RTC_OSC_FRQ_30_5ppm			16
+#define DA9052_RTC_OSC_FRQ_32_4ppm			17
+#define DA9052_RTC_OSC_FRQ_34_3ppm			18
+#define DA9052_RTC_OSC_FRQ_36_2ppm			19
+#define DA9052_RTC_OSC_FRQ_38_1ppm			20
+#define DA9052_RTC_OSC_FRQ_40_0ppm			21
+#define DA9052_RTC_OSC_FRQ_41_9ppm			22
+#define DA9052_RTC_OSC_FRQ_43_8ppm			23
+#define DA9052_RTC_OSC_FRQ_45_7ppm			24
+#define DA9052_RTC_OSC_FRQ_47_6ppm			25
+#define DA9052_RTC_OSC_FRQ_49_5ppm			26
+#define DA9052_RTC_OSC_FRQ_51_4ppm			27
+#define DA9052_RTC_OSC_FRQ_53_4ppm			28
+#define DA9052_RTC_OSC_FRQ_55_3ppm			29
+#define DA9052_RTC_OSC_FRQ_57_2ppm			30
+#define DA9052_RTC_OSC_FRQ_59_1ppm			31
+#define DA9052_RTC_OSC_FRQ_61_0ppm			32
+#define DA9052_RTC_OSC_FRQ_62_9ppm			33
+#define DA9052_RTC_OSC_FRQ_64_8ppm			34
+#define DA9052_RTC_OSC_FRQ_66_7ppm			35
+#define DA9052_RTC_OSC_FRQ_68_6ppm			36
+#define DA9052_RTC_OSC_FRQ_70_5ppm			37
+#define DA9052_RTC_OSC_FRQ_72_4ppm			38
+#define DA9052_RTC_OSC_FRQ_74_3ppm			39
+#define DA9052_RTC_OSC_FRQ_76_2ppm			40
+#define DA9052_RTC_OSC_FRQ_78_2ppm			41
+#define DA9052_RTC_OSC_FRQ_80_1ppm			42
+#define DA9052_RTC_OSC_FRQ_82_0ppm			43
+#define DA9052_RTC_OSC_FRQ_83_9ppm			44
+#define DA9052_RTC_OSC_FRQ_85_8ppm			45
+#define DA9052_RTC_OSC_FRQ_87_7ppm			46
+#define DA9052_RTC_OSC_FRQ_89_6ppm			47
+#define DA9052_RTC_OSC_FRQ_91_5ppm			48
+#define DA9052_RTC_OSC_FRQ_93_4ppm			49
+#define DA9052_RTC_OSC_FRQ_95_3ppm			50
+#define DA9052_RTC_OSC_FRQ_97_2ppm			51
+#define DA9052_RTC_OSC_FRQ_99_1ppm			52
+#define DA9052_RTC_OSC_FRQ_101_0ppm			53
+#define DA9052_RTC_OSC_FRQ_102_9ppm			54
+#define DA9052_RTC_OSC_FRQ_104_9ppm			55
+#define DA9052_RTC_OSC_FRQ_106_8ppm			56
+#define DA9052_RTC_OSC_FRQ_108_7ppm			57
+#define DA9052_RTC_OSC_FRQ_110_6ppm			58
+#define DA9052_RTC_OSC_FRQ_112_5ppm			59
+#define DA9052_RTC_OSC_FRQ_114_4ppm			60
+#define DA9052_RTC_OSC_FRQ_116_3ppm			61
+#define DA9052_RTC_OSC_FRQ_118_2ppm			62
+#define DA9052_RTC_OSC_FRQ_120_1ppm			63
+#define DA9052_RTC_OSC_FRQ_122_0ppm			64
+#define DA9052_RTC_OSC_FRQ_123_9ppm			65
+#define DA9052_RTC_OSC_FRQ_125_8ppm			66
+#define DA9052_RTC_OSC_FRQ_127_7ppm			67
+#define DA9052_RTC_OSC_FRQ_129_6ppm			68
+#define DA9052_RTC_OSC_FRQ_131_6ppm			69
+#define DA9052_RTC_OSC_FRQ_133_5ppm			70
+#define DA9052_RTC_OSC_FRQ_135_4ppm			71
+#define DA9052_RTC_OSC_FRQ_137_3ppm			72
+#define DA9052_RTC_OSC_FRQ_139_2ppm			73
+#define DA9052_RTC_OSC_FRQ_141_1ppm			74
+#define DA9052_RTC_OSC_FRQ_143_0ppm			75
+#define DA9052_RTC_OSC_FRQ_144_9ppm			76
+#define DA9052_RTC_OSC_FRQ_146_8ppm			77
+#define DA9052_RTC_OSC_FRQ_148_7ppm			78
+#define DA9052_RTC_OSC_FRQ_150_6ppm			79
+#define DA9052_RTC_OSC_FRQ_152_5ppm			80
+#define DA9052_RTC_OSC_FRQ_154_4ppm			81
+#define DA9052_RTC_OSC_FRQ_156_4ppm			82
+#define DA9052_RTC_OSC_FRQ_158_3ppm			83
+#define DA9052_RTC_OSC_FRQ_160_2ppm			84
+#define DA9052_RTC_OSC_FRQ_162_1ppm			85
+#define DA9052_RTC_OSC_FRQ_164_0ppm			86
+#define DA9052_RTC_OSC_FRQ_165_9ppm			87
+#define DA9052_RTC_OSC_FRQ_167_8ppm			88
+#define DA9052_RTC_OSC_FRQ_169_7ppm			89
+#define DA9052_RTC_OSC_FRQ_171_6ppm			90
+#define DA9052_RTC_OSC_FRQ_173_5ppm			91
+#define DA9052_RTC_OSC_FRQ_175_4ppm			92
+#define DA9052_RTC_OSC_FRQ_177_3ppm			93
+#define DA9052_RTC_OSC_FRQ_179_2ppm			94
+#define DA9052_RTC_OSC_FRQ_181_1ppm			95
+#define DA9052_RTC_OSC_FRQ_183_1ppm			96
+#define DA9052_RTC_OSC_FRQ_185_0ppm			97
+#define DA9052_RTC_OSC_FRQ_186_9ppm			98
+#define DA9052_RTC_OSC_FRQ_188_8ppm			99
+#define DA9052_RTC_OSC_FRQ_190_7ppm			100
+#define DA9052_RTC_OSC_FRQ_192_6ppm			101
+#define DA9052_RTC_OSC_FRQ_194_5ppm			102
+#define DA9052_RTC_OSC_FRQ_196_4ppm			103
+#define DA9052_RTC_OSC_FRQ_198_3ppm			104
+#define DA9052_RTC_OSC_FRQ_200_2ppm			105
+#define DA9052_RTC_OSC_FRQ_202_1ppm			106
+#define DA9052_RTC_OSC_FRQ_204_0ppm			107
+#define DA9052_RTC_OSC_FRQ_205_9ppm			108
+#define DA9052_RTC_OSC_FRQ_207_9ppm			109
+#define DA9052_RTC_OSC_FRQ_209_8ppm			110
+#define DA9052_RTC_OSC_FRQ_211_7ppm			111
+#define DA9052_RTC_OSC_FRQ_213_6ppm			112
+#define DA9052_RTC_OSC_FRQ_215_5ppm			113
+#define DA9052_RTC_OSC_FRQ_217_4ppm			114
+#define DA9052_RTC_OSC_FRQ_219_3ppm			115
+#define DA9052_RTC_OSC_FRQ_221_2ppm			116
+#define DA9052_RTC_OSC_FRQ_223_1ppm			117
+#define DA9052_RTC_OSC_FRQ_225_0ppm			118
+#define DA9052_RTC_OSC_FRQ_226_9ppm			119
+#define DA9052_RTC_OSC_FRQ_228_8ppm			120
+#define DA9052_RTC_OSC_FRQ_230_7ppm			121
+#define DA9052_RTC_OSC_FRQ_232_6ppm			122
+#define DA9052_RTC_OSC_FRQ_234_6ppm			123
+#define DA9052_RTC_OSC_FRQ_236_5ppm			124
+#define DA9052_RTC_OSC_FRQ_238_4ppm			125
+#define DA9052_RTC_OSC_FRQ_240_3ppm			126
+#define DA9052_RTC_OSC_FRQ_242_2ppm			127
+#define DA9052_RTC_OSC_FRQ_MINUS_244_1ppm		128
+#define DA9052_RTC_OSC_FRQ_MINUS_242_2ppm		129
+#define DA9052_RTC_OSC_FRQ_MINUS_240_3ppm		130
+#define DA9052_RTC_OSC_FRQ_MINUS_238_4ppm		131
+#define DA9052_RTC_OSC_FRQ_MINUS_236_5ppm		132
+#define DA9052_RTC_OSC_FRQ_MINUS_234_6ppm		133
+#define DA9052_RTC_OSC_FRQ_MINUS_232_6ppm		134
+#define DA9052_RTC_OSC_FRQ_MINUS_230_7ppm		135
+#define DA9052_RTC_OSC_FRQ_MINUS_228_8ppm		136
+#define DA9052_RTC_OSC_FRQ_MINUS_226_9ppm		137
+#define DA9052_RTC_OSC_FRQ_MINUS_225_0ppm		138
+#define DA9052_RTC_OSC_FRQ_MINUS_223_1ppm		139
+#define DA9052_RTC_OSC_FRQ_MINUS_221_2ppm		140
+#define DA9052_RTC_OSC_FRQ_MINUS_219_3ppm		141
+#define DA9052_RTC_OSC_FRQ_MINUS_217_4ppm		142
+#define DA9052_RTC_OSC_FRQ_MINUS_215_5ppm		143
+#define DA9052_RTC_OSC_FRQ_MINUS_213_6ppm		144
+#define DA9052_RTC_OSC_FRQ_MINUS_211_7ppm		145
+#define DA9052_RTC_OSC_FRQ_MINUS_209_8ppm		146
+#define DA9052_RTC_OSC_FRQ_MINUS_207_9ppm		147
+#define DA9052_RTC_OSC_FRQ_MINUS_205_9ppm		148
+#define DA9052_RTC_OSC_FRQ_MINUS_204_0ppm		149
+#define DA9052_RTC_OSC_FRQ_MINUS_202_1ppm		150
+#define DA9052_RTC_OSC_FRQ_MINUS_200_2ppm		151
+#define DA9052_RTC_OSC_FRQ_MINUS_198_3ppm		152
+#define DA9052_RTC_OSC_FRQ_MINUS_196_4ppm		153
+#define DA9052_RTC_OSC_FRQ_MINUS_194_5ppm		154
+#define DA9052_RTC_OSC_FRQ_MINUS_192_6ppm		155
+#define DA9052_RTC_OSC_FRQ_MINUS_190_7ppm		156
+#define DA9052_RTC_OSC_FRQ_MINUS_188_8ppm		157
+#define DA9052_RTC_OSC_FRQ_MINUS_186_9ppm		158
+#define DA9052_RTC_OSC_FRQ_MINUS_185_0ppm		159
+#define DA9052_RTC_OSC_FRQ_MINUS_183_1ppm		160
+#define DA9052_RTC_OSC_FRQ_MINUS_181_1ppm		161
+#define DA9052_RTC_OSC_FRQ_MINUS_179_2ppm		162
+#define DA9052_RTC_OSC_FRQ_MINUS_177_3ppm		163
+#define DA9052_RTC_OSC_FRQ_MINUS_175_4ppm		164
+#define DA9052_RTC_OSC_FRQ_MINUS_173_5ppm		165
+#define DA9052_RTC_OSC_FRQ_MINUS_171_6ppm		166
+#define DA9052_RTC_OSC_FRQ_MINUS_169_7ppm		167
+#define DA9052_RTC_OSC_FRQ_MINUS_167_8ppm		168
+#define DA9052_RTC_OSC_FRQ_MINUS_165_9ppm		169
+#define DA9052_RTC_OSC_FRQ_MINUS_164_0ppm		170
+#define DA9052_RTC_OSC_FRQ_MINUS_162_1ppm		171
+#define DA9052_RTC_OSC_FRQ_MINUS_160_2ppm		172
+#define DA9052_RTC_OSC_FRQ_MINUS_158_3ppm		173
+#define DA9052_RTC_OSC_FRQ_MINUS_156_4ppm		174
+#define DA9052_RTC_OSC_FRQ_MINUS_154_4ppm		175
+#define DA9052_RTC_OSC_FRQ_MINUS_152_5ppm		176
+#define DA9052_RTC_OSC_FRQ_MINUS_150_6ppm		177
+#define DA9052_RTC_OSC_FRQ_MINUS_148_7ppm		178
+#define DA9052_RTC_OSC_FRQ_MINUS_146_8ppm		179
+#define DA9052_RTC_OSC_FRQ_MINUS_144_9ppm		180
+#define DA9052_RTC_OSC_FRQ_MINUS_143_0ppm		181
+#define DA9052_RTC_OSC_FRQ_MINUS_141_1ppm		182
+#define DA9052_RTC_OSC_FRQ_MINUS_139_2ppm		183
+#define DA9052_RTC_OSC_FRQ_MINUS_137_3ppm		184
+#define DA9052_RTC_OSC_FRQ_MINUS_135_4ppm		185
+#define DA9052_RTC_OSC_FRQ_MINUS_133_5ppm		186
+#define DA9052_RTC_OSC_FRQ_MINUS_131_6ppm		187
+#define DA9052_RTC_OSC_FRQ_MINUS_129_6ppm		188
+#define DA9052_RTC_OSC_FRQ_MINUS_127_7ppm		189
+#define DA9052_RTC_OSC_FRQ_MINUS_125_8ppm		190
+#define DA9052_RTC_OSC_FRQ_MINUS_123_9ppm		191
+#define DA9052_RTC_OSC_FRQ_MINUS_122_0ppm		192
+#define DA9052_RTC_OSC_FRQ_MINUS_120_1ppm		193
+#define DA9052_RTC_OSC_FRQ_MINUS_118_2ppm		194
+#define DA9052_RTC_OSC_FRQ_MINUS_116_3ppm		195
+#define DA9052_RTC_OSC_FRQ_MINUS_114_4ppm		196
+#define DA9052_RTC_OSC_FRQ_MINUS_112_5ppm		197
+#define DA9052_RTC_OSC_FRQ_MINUS_110_6ppm		198
+#define DA9052_RTC_OSC_FRQ_MINUS_108_7ppm		199
+#define DA9052_RTC_OSC_FRQ_MINUS_106_8ppm		200
+#define DA9052_RTC_OSC_FRQ_MINUS_104_9ppm		201
+#define DA9052_RTC_OSC_FRQ_MINUS_102_9ppm		202
+#define DA9052_RTC_OSC_FRQ_MINUS_101_0ppm		203
+#define DA9052_RTC_OSC_FRQ_MINUS_99_1ppm		204
+#define DA9052_RTC_OSC_FRQ_MINUS_97_2ppm		205
+#define DA9052_RTC_OSC_FRQ_MINUS_95_3ppm		206
+#define DA9052_RTC_OSC_FRQ_MINUS_93_4ppm		207
+#define DA9052_RTC_OSC_FRQ_MINUS_91_5ppm		208
+#define DA9052_RTC_OSC_FRQ_MINUS_89_6ppm		209
+#define DA9052_RTC_OSC_FRQ_MINUS_87_7ppm		210
+#define DA9052_RTC_OSC_FRQ_MINUS_85_8ppm		211
+#define DA9052_RTC_OSC_FRQ_MINUS_83_9ppm		212
+#define DA9052_RTC_OSC_FRQ_MINUS_82_0ppm		213
+#define DA9052_RTC_OSC_FRQ_MINUS_80_1ppm		214
+#define DA9052_RTC_OSC_FRQ_MINUS_78_2ppm		215
+#define DA9052_RTC_OSC_FRQ_MINUS_76_2ppm		216
+#define DA9052_RTC_OSC_FRQ_MINUS_74_3ppm		217
+#define DA9052_RTC_OSC_FRQ_MINUS_72_4ppm		218
+#define DA9052_RTC_OSC_FRQ_MINUS_70_5ppm		219
+#define DA9052_RTC_OSC_FRQ_MINUS_68_6ppm		220
+#define DA9052_RTC_OSC_FRQ_MINUS_66_7ppm		221
+#define DA9052_RTC_OSC_FRQ_MINUS_64_8ppm		222
+#define DA9052_RTC_OSC_FRQ_MINUS_62_9ppm		223
+#define DA9052_RTC_OSC_FRQ_MINUS_61_0ppm		224
+#define DA9052_RTC_OSC_FRQ_MINUS_59_1ppm		225
+#define DA9052_RTC_OSC_FRQ_MINUS_57_2ppm		226
+#define DA9052_RTC_OSC_FRQ_MINUS_55_3ppm		227
+#define DA9052_RTC_OSC_FRQ_MINUS_53_4ppm		228
+#define DA9052_RTC_OSC_FRQ_MINUS_51_4ppm		229
+#define DA9052_RTC_OSC_FRQ_MINUS_49_5ppm		230
+#define DA9052_RTC_OSC_FRQ_MINUS_47_6ppm		231
+#define DA9052_RTC_OSC_FRQ_MINUS_45_7ppm		232
+#define DA9052_RTC_OSC_FRQ_MINUS_43_8ppm		233
+#define DA9052_RTC_OSC_FRQ_MINUS_41_9ppm		234
+#define DA9052_RTC_OSC_FRQ_MINUS_40_0ppm		235
+#define DA9052_RTC_OSC_FRQ_MINUS_38_1ppm		236
+#define DA9052_RTC_OSC_FRQ_MINUS_36_2ppm		237
+#define DA9052_RTC_OSC_FRQ_MINUS_34_3ppm		238
+#define DA9052_RTC_OSC_FRQ_MINUS_32_4ppm		239
+#define DA9052_RTC_OSC_FRQ_MINUS_30_5ppm		240
+#define DA9052_RTC_OSC_FRQ_MINUS_28_6ppm		241
+#define DA9052_RTC_OSC_FRQ_MINUS_26_7ppm		242
+#define DA9052_RTC_OSC_FRQ_MINUS_24_7ppm		243
+#define DA9052_RTC_OSC_FRQ_MINUS_22_8ppm		244
+#define DA9052_RTC_OSC_FRQ_MINUS_20_9ppm		245
+#define DA9052_RTC_OSC_FRQ_MINUS_19_0ppm		246
+#define DA9052_RTC_OSC_FRQ_MINUS_17_1ppm		247
+#define DA9052_RTC_OSC_FRQ_MINUS_15_2ppm		248
+#define DA9052_RTC_OSC_FRQ_MINUS_13_3ppm		249
+#define DA9052_RTC_OSC_FRQ_MINUS_11_4ppm		250
+#define DA9052_RTC_OSC_FRQ_MINUS_9_5ppm			251
+#define DA9052_RTC_OSC_FRQ_MINUS_7_6ppm			252
+#define DA9052_RTC_OSC_FRQ_MINUS_5_7ppm			253
+#define DA9052_RTC_OSC_FRQ_MINUS_3_8ppm			254
+#define DA9052_RTC_OSC_FRQ_MINUS_1_9ppm			255
+
+/* RTC error codes */
+#define DA9052_RTC_INVALID_SECONDS			3
+#define DA9052_RTC_INVALID_MINUTES			4
+#define DA9052_RTC_INVALID_HOURS			5
+#define DA9052_RTC_INVALID_DAYS				6
+#define DA9052_RTC_INVALID_MONTHS			7
+#define DA9052_RTC_INVALID_YEARS			8
+#define DA9052_RTC_INVALID_EVENT			9
+#define DA9052_RTC_INVALID_IOCTL			10
+#define DA9052_RTC_INVALID_SETTING			11
+#define DA9052_RTC_EVENT_ALREADY_REGISTERED		12
+#define DA9052_RTC_EVENT_UNREGISTERED			13
+#define DA9052_RTC_EVENT_REGISTRATION_FAILED		14
+#define DA9052_RTC_EVENT_UNREGISTRATION_FAILED		15
+
+#endif
+/* __LINUX_MFD_DA9052_RTC_H */
diff --git a/include/linux/mfd/da9052/tsi.h b/include/linux/mfd/da9052/tsi.h
new file mode 100644
index 00000000000..a677bbc012a
--- /dev/null
+++ b/include/linux/mfd/da9052/tsi.h
@@ -0,0 +1,427 @@
+/*
+ * da9052 TSI module declarations.
+  *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_TSI_H
+#define __LINUX_MFD_DA9052_TSI_H
+
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/tsi_filter.h>
+#include <linux/mfd/da9052/tsi_calibrate.h>
+#include <linux/mfd/da9052/pm.h>
+
+#define DA9052_TSI_DEVICE_NAME		"da9052-tsi"
+#define DA9052_TSI_INPUT_DEV		DA9052_TSI_DEVICE_NAME
+
+#define TSI_VERSION			0x0101
+#define DA9052_VENDOR_ID		0x15B6
+#define DA9052_PRODUCT_ID		0x9052
+
+#define TSI_INPUT_DEVICE_OFF		0
+#define NUM_INPUT_DEVS			1
+
+#define DA9052_DISPLAY_X_MAX		0x3FF
+#define DA9052_DISPLAY_Y_MAX		0x3FF
+#define DA9052_TOUCH_PRESSURE_MAX	0x3FF
+
+#define DA9052_TCA_AUTO_TSI_ENABLE				(1<<0)
+#define DA9052_TCA_PEN_DET_ENABLE				(1<<1)
+#define DA9052_TCA_TSI_XP_MODE_ENABLE				(1<<2)
+
+#define DA9052_TCA_TSI_DELAY_0SLOTS				(0<<6)
+#define DA9052_TCA_TSI_DELAY_2SLOTS				(2<<6)
+#define DA9052_TCA_TSI_DELAY_4SLOTS				(3<<6)
+
+#define DA9052_TCA_TSI_SEL_XPLUS				(1<<0)
+#define DA9052_TCA_TSI_SEL_XMINUS				(1<<1)
+#define DA9052_TCA_TSI_SEL_YPLUS				(1<<2)
+#define DA9052_TCA_TSI_SEL_YMINUS				(1<<3)
+
+#define DA9052_TCA_TSI_MUX_XPLUS_ROUTED_ADCIN7			(0<<4)
+#define DA9052_TCA_TSI_MUX_YPLUS_ROUTED_ADCIN7			(1<<4)
+#define DA9052_TCA_TSI_MUX_XMINUS_ROUTED_ADCIN7			(2<<4)
+#define DA9052_TCA_TSI_MUX_YMINUS_ROUTED_ADCIN7			(3<<4)
+
+#define DA9052_TCA_TSI_MAN_ENABLE				(1<<6)
+#define DA9052_TCA_TSI_SET_TSIREF				(0<<7)
+#define DA9052_TCA_TSI_SET_XY_REF				(1<<7)
+
+#define DA9052_EVETN_B_E_PEN_DOWN				(1<<6)
+#define DA9052_EVENT_B_E_TSI_READY				(1<<7)
+
+#define DA9052_IRQMASK_B_PENDOWN_MASK				(1<<6)
+#define DA9052_IRQMASK_B_TSI_READY_MASK				(1<<7)
+
+#define X_LSB_SHIFT	(0)
+#define Y_LSB_SHIFT	(2)
+#define Z_LSB_SHIFT	(4)
+#define PEN_DET_SHIFT	(6)
+#define X_MSB_SHIFT	(2)
+#define Y_MSB_SHIFT	(2)
+#define Z_MSB_SHIFT	(2)
+#define X_LSB_MASK	(11 << X_LSB_SHIFT)
+#define Y_LSB_MASK	(11 << Y_LSB_SHIFT)
+#define Z_LSB_MASK	(11 << Z_LSB_SHIFT)
+#define PEN_DET_MASK	(11 << PEN_DET_SHIFT)
+
+#define TSI_FIFO_SIZE		16
+
+#define INVALID_LDO9_VOLT_VALUE			17
+
+#define set_bits(value, mask)		(value | mask)
+#define clear_bits(value, mask)		(value & ~(mask))
+
+#define SUCCESS		0
+#define FAILURE		1
+
+#define SET		1
+#define	RESET		0
+#define	CLEAR		0
+
+#define ENABLE		1
+#define DISABLE		0
+
+#define TRUE		1
+#define FALSE		0
+
+#define incr_with_wrap_reg_fifo(x)			\
+		if (++x >= TSI_REG_DATA_BUF_SIZE)	\
+			x = 0
+
+#define incr_with_wrap(x)	\
+		if (++x >= TSI_FIFO_SIZE)	\
+			x = 0
+
+#undef DA9052_DEBUG
+#if DA9052_TSI_DEBUG
+#define DA9052_DEBUG(fmt, args...) printk(KERN_CRIT "" fmt, ##args)
+#else
+#define DA9052_DEBUG(fmt, args...)
+#endif
+
+enum ADC_MODE {
+
+	ECONOMY_MODE = 0,
+	FAST_MODE = 1
+};
+
+enum TSI_DELAY {
+	TSI_DELAY_0SLOTS = 0,
+	TSI_DELAY_1SLOTS = 1,
+	TSI_DELAY_2SLOTS = 2,
+	TSI_DELAY_4SLOTS = 3
+};
+
+enum TSI_SLOT_SKIP {
+	TSI_SKIP_0SLOTS = 0,
+	TSI_SKIP_2SLOTS = 1,
+	TSI_SKIP_5SLOTS = 2,
+	TSI_SKIP_10SLOTS = 3,
+	TSI_SKIP_30SLOTS = 4,
+	TSI_SKIP_80SLOTS = 5,
+	TSI_SKIP_130SLOTS = 6,
+	TSI_SKIP_330SLOTS = 7
+};
+
+
+enum TSI_MUX_SEL {
+	TSI_MUX_XPLUS	= 0,
+	TSI_MUX_YPLUS	= 1,
+	TSI_MUX_XMINUS	= 2,
+	TSI_MUX_YMINUS	= 3
+};
+
+
+enum TSI_IRQ {
+	TSI_PEN_DWN,
+	TSI_DATA_RDY
+};
+
+
+enum TSI_COORDINATE {
+	X_COORDINATE,
+	Y_COORDINATE,
+	Z_COORDINATE
+};
+
+enum TSI_MEASURE_SEQ {
+	XYZP_MODE,
+	XP_MODE
+};
+
+enum TSI_STATE {
+	TSI_AUTO_MODE,
+	TSI_MANUAL_COORD_X,
+	TSI_MANUAL_COORD_Y,
+	TSI_MANUAL_COORD_Z,
+	TSI_MANUAL_SET,
+	TSI_IDLE
+};
+
+union da9052_tsi_cont_reg {
+	u8 da9052_tsi_cont_a;
+	struct {
+		u8 auto_tsi_en:1;
+		u8 pen_det_en:1;
+		u8 tsi_mode:1;
+		u8 tsi_skip:3;
+		u8 tsi_delay:2;
+	} tsi_cont_a;
+};
+
+union da9052_tsi_man_cont_reg {
+	u8 da9052_tsi_cont_b;
+	struct {
+		u8 tsi_sel_0:1;
+		u8 tsi_sel_1:1;
+		u8 tsi_sel_2:1;
+		u8 tsi_sel_3:1;
+		u8 tsi_mux:2;
+		u8 tsi_man:1;
+		u8 tsi_adc_ref:1;
+	} tsi_cont_b;
+};
+
+struct da9052_tsi_conf {
+	union da9052_tsi_cont_reg	auto_cont;
+	union da9052_tsi_man_cont_reg	man_cont;
+	u8				tsi_adc_sample_intervel:1;
+	enum TSI_STATE			state;
+	u8				ldo9_en:1;
+	u8				ldo9_conf:1;
+	u8				tsi_ready_irq_mask:1;
+	u8				tsi_pendown_irq_mask:1;
+};
+
+
+struct da9052_tsi_reg {
+	u8	x_msb;
+	u8	y_msb;
+	u8	z_msb;
+	u8	lsb;
+};
+
+
+struct da9052_tsi_reg_fifo {
+	struct semaphore	lock;
+	s32			head;
+	s32			tail;
+	struct da9052_tsi_reg	data[TSI_REG_DATA_BUF_SIZE];
+};
+
+struct da9052_tsi_info {
+	struct  da9052_tsi_conf  tsi_conf;
+	struct input_dev	*input_devs[NUM_INPUT_DEVS];
+	struct calib_cfg_t	*tsi_calib;
+	u32			tsi_data_poll_interval;
+	u32			tsi_penup_count;
+	u32			tsi_zero_data_cnt;
+	u8			pen_dwn_event;
+	u8			tsi_rdy_event;
+	u8			pd_reg_status;
+	u8			datardy_reg_status;
+};
+
+struct da9052_tsi {
+	struct da9052_tsi_reg tsi_fifo[TSI_FIFO_SIZE];
+	struct mutex tsi_fifo_lock;
+	u8 tsi_sampling;
+	u8 tsi_state;
+	u32 tsi_fifo_start;
+	u32 tsi_fifo_end;
+};
+
+struct da9052_ts_priv {
+	struct da9052	*da9052;
+	struct da9052_eh_nb pd_nb;
+	struct da9052_eh_nb datardy_nb;
+
+	struct tsi_thread_type	tsi_reg_proc_thread;
+	struct tsi_thread_type tsi_raw_proc_thread;
+
+	struct da9052_tsi_platform_data *tsi_pdata;
+
+	struct da9052_tsi_reg_fifo	tsi_reg_fifo;
+	struct da9052_tsi_raw_fifo	tsi_raw_fifo;
+
+	u32 tsi_reg_data_poll_interval;
+	u32 tsi_raw_data_poll_interval;
+
+	u8 early_data_flag;
+	u8 debounce_over;
+	u8 win_reference_valid;
+
+	int os_data_cnt;
+	int raw_data_cnt;
+};
+
+static inline u8  mask_pendwn_irq(u8 val)
+{
+	return val |= DA9052_IRQMASKB_MPENDOWN;
+}
+
+static inline u8  unmask_pendwn_irq(u8 val)
+{
+	return val &= ~DA9052_IRQMASKB_MPENDOWN;
+}
+
+static inline u8  mask_tsi_rdy_irq(u8 val)
+{
+	return val |= DA9052_IRQMASKB_MTSIREADY;
+}
+
+static inline u8  unmask_tsi_rdy_irq(u8 val)
+{
+	return val &= ~DA9052_IRQMASKB_MTSIREADY;
+}
+
+static inline u8  enable_ldo9(u8 val)
+{
+	return val |= DA9052_LDO9_LDO9EN;
+}
+
+static inline u8  disable_ldo9(u8 val)
+{
+	return val &= ~DA9052_LDO9_LDO9EN;
+}
+
+static inline u8  set_auto_tsi_en(u8 val)
+{
+	return val |= DA9052_TSICONTA_AUTOTSIEN;
+}
+
+static inline u8  reset_auto_tsi_en(u8 val)
+{
+	return val &= ~DA9052_TSICONTA_AUTOTSIEN;
+}
+
+static inline u8  enable_pen_detect(u8 val)
+{
+	return val |= DA9052_TSICONTA_PENDETEN;
+}
+
+static inline u8  disable_pen_detect(u8 val)
+{
+	return val &= ~DA9052_TSICONTA_PENDETEN;
+}
+
+static inline u8  enable_xyzp_mode(u8 val)
+{
+	return val &= ~DA9052_TSICONTA_TSIMODE;
+}
+
+static inline u8  enable_xp_mode(u8 val)
+{
+	return val |= DA9052_TSICONTA_TSIMODE;
+}
+
+static inline u8  enable_tsi_manual_mode(u8 val)
+{
+	return val |= DA9052_TSICONTB_TSIMAN;
+}
+
+static inline u8  disable_tsi_manual_mode(u8 val)
+{
+	return val &= ~DA9052_TSICONTB_TSIMAN;
+}
+
+static inline u8 tsi_sel_xplus_close(u8 val)
+{
+	return val |= DA9052_TSICONTB_TSISEL0;
+}
+
+static inline u8 tsi_sel_xplus_open(u8 val)
+{
+	return val &= ~DA9052_TSICONTB_TSISEL0;
+}
+
+static inline u8 tsi_sel_xminus_close(u8 val)
+{
+	return val |= DA9052_TSICONTB_TSISEL1;
+}
+
+static inline u8 tsi_sel_xminus_open(u8 val)
+{
+	return val &= ~DA9052_TSICONTB_TSISEL1;
+}
+
+static inline u8 tsi_sel_yplus_close(u8 val)
+{
+	return val |= DA9052_TSICONTB_TSISEL2;
+}
+
+static inline u8 tsi_sel_yplus_open(u8 val)
+{
+	return val &= ~DA9052_TSICONTB_TSISEL2;
+}
+
+static inline u8 tsi_sel_yminus_close(u8 val)
+{
+	return val |= DA9052_TSICONTB_TSISEL3;
+}
+
+static inline u8 tsi_sel_yminus_open(u8 val)
+{
+	return val &= ~DA9052_TSICONTB_TSISEL3;
+}
+
+static inline u8 adc_mode_economy_mode(u8 val)
+{
+	return val &= ~DA9052_ADCCONT_ADCMODE ;
+}
+
+static inline u8 adc_mode_fast_mode(u8 val)
+{
+	return val |= DA9052_ADCCONT_ADCMODE;
+}
+int da9052_tsi_get_calib_display_point(struct da9052_tsi_data *display);
+
+struct da9052_ldo_config {
+	u16		ldo_volt;
+	u8		ldo_num;
+	u8		ldo_conf:1;
+	u8		ldo_pd:1;
+};
+
+static inline  u8 ldo9_mV_to_reg(u16 value)
+{
+	return (value - DA9052_LDO9_VOLT_LOWER)/DA9052_LDO9_VOLT_STEP;
+}
+
+static inline  u8 validate_ldo9_mV(u16 value)
+{
+	if ((value >= DA9052_LDO9_VOLT_LOWER) && \
+					(value <= DA9052_LDO9_VOLT_UPPER))
+		return
+			(((value - DA9052_LDO9_VOLT_LOWER)
+			  % DA9052_LDO9_VOLT_STEP > 0) ? -1 : 0);
+	return FAILURE;
+}
+
+s32 da9052_tsi_raw_proc_thread(void *ptr);
+void __init da9052_init_tsi_fifos(struct da9052_ts_priv *priv);
+void clean_tsi_fifos(struct da9052_ts_priv *priv);
+u32 get_reg_data_cnt(struct da9052_ts_priv *priv);
+u32 get_reg_free_space_cnt(struct da9052_ts_priv *priv);
+void da9052_tsi_process_reg_data(struct da9052_ts_priv *priv);
+void da9052_tsi_pen_down_handler(struct da9052_eh_nb *eh_data, u32 event);
+void da9052_tsi_data_ready_handler(struct da9052_eh_nb *eh_data, u32 event);
+
+#endif /* __LINUX_MFD_DA9052_TSI_H */
diff --git a/include/linux/mfd/da9052/tsi_calibrate.h b/include/linux/mfd/da9052/tsi_calibrate.h
new file mode 100644
index 00000000000..a4b42ea079a
--- /dev/null
+++ b/include/linux/mfd/da9052/tsi_calibrate.h
@@ -0,0 +1,47 @@
+/*
+ * da9052 TSI calibration module declarations.
+  *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_TSI_CALIBRATE_H
+#define __LINUX_MFD_DA9052_TSI_CALIBRATE_H
+
+#include <linux/mfd/da9052/tsi_filter.h>
+
+struct Calib_xform_matrix_t {
+	s32	An;
+	s32	Bn;
+	s32	Cn;
+	s32	Dn;
+	s32	En;
+	s32	Fn;
+	s32	Divider;
+} ;
+
+
+struct calib_cfg_t {
+	u8 calibrate_flag;
+} ;
+
+ssize_t da9052_tsi_set_calib_matrix(struct da9052_tsi_data *displayPtr,
+				   struct da9052_tsi_data *screenPtr);
+u8 configure_tsi_calib(struct calib_cfg_t *tsi_calib);
+struct calib_cfg_t *get_calib_config(void);
+#endif /* __LINUX_MFD_DA9052_TSI_CALIBRATE_H */
+
diff --git a/include/linux/mfd/da9052/tsi_cfg.h b/include/linux/mfd/da9052/tsi_cfg.h
new file mode 100644
index 00000000000..21c091b1acc
--- /dev/null
+++ b/include/linux/mfd/da9052/tsi_cfg.h
@@ -0,0 +1,132 @@
+/*
+ * da9052 TSI configuration module declarations.
+  *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_TSI_CFG_H
+#define __LINUX_MFD_DA9052_TSI_CFG_H
+
+#define		DA9052_TSI_DEBUG	0
+
+#define AUTO_MODE			0
+#define IDLE				1
+#define DEFAULT_TSI_STATE		AUTO_MODE
+
+#define TSI_SLOT_SKIP_VALUE		0
+
+#define TSI_DELAY_VALUE			3
+
+#define TSI_MODE_VALUE			0
+
+#define ENABLE_AVERAGE_FILTER		1
+
+#define DEFAULT_AVERAGE_FILTER_SIZE	3
+
+#define ENABLE_WINDOW_FILTER		1
+
+#define TSI_X_WINDOW_SIZE		50
+#define TSI_Y_WINDOW_SIZE		50
+
+#define SAMPLE_CNT_FOR_WIN_REF		3
+
+#define TSI_ECONOMY_MODE		0
+#define TSI_FAST_MODE			1
+#define DEFAULT_TSI_SAMPLING_MODE	TSI_FAST_MODE
+
+#define TSI_USE_CALIBRATION		1
+
+#define DA9052_TSI_CALIB_AN		1
+#define DA9052_TSI_CALIB_BN		0
+#define DA9052_TSI_CALIB_CN		0
+#define DA9052_TSI_CALIB_DN		0
+#define DA9052_TSI_CALIB_EN		1
+#define DA9052_TSI_CALIB_FN		0
+#define DA9052_TSI_CALIB_DIVIDER	1
+
+#define TS_X_MIN	(0)
+#define TS_X_MAX	(1023)
+#define TS_Y_MIN	(0)
+#define TS_Y_MAX	(1023)
+
+#define DISPLAY_X_MIN	(0)
+#define DISPLAY_X_MAX	(1023)
+#define DISPLAY_Y_MIN	(0)
+#define DISPLAY_Y_MAX	(1023)
+
+#define ENABLE_TSI_DEBOUNCE		0
+
+#define TSI_DEBOUNCE_DATA_CNT		3
+
+
+#define RELEASE
+#define DA9052_TSI_RAW_DATA_PROFILING		0
+#define DA9052_TSI_WIN_FLT_DATA_PROFILING	0
+#define DA9052_TSI_AVG_FLT_DATA_PROFILING	0
+#define DA9052_TSI_CALIB_DATA_PROFILING		0
+#define DA9052_TSI_OS_DATA_PROFILING		1
+#define DA9052_TSI_PRINT_DEBOUNCED_DATA		0
+#define DA9052_TSI_PRINT_PREVIOUS_DATA		0
+
+
+#if ENABLE_AVERAGE_FILTER
+#define TSI_AVERAGE_FILTER_SIZE		DEFAULT_AVERAGE_FILTER_SIZE
+#else
+#define TSI_AVERAGE_FILTER_SIZE			1
+#endif
+
+#define TSI_FAST_MODE_SAMPLE_CNT		1000
+#define TSI_ECO_MODE_SAMPLE_CNT			100
+
+#define TSI_POLL_SAMPLE_CNT			10
+
+#define TSI_FAST_MODE_REG_DATA_PROCESSING_INTERVAL	\
+	((1000 / TSI_FAST_MODE_SAMPLE_CNT) * TSI_POLL_SAMPLE_CNT)
+#define TSI_ECO_MODE_REG_DATA_PROCESSING_INTERVAL	\
+	((1000 / TSI_ECO_MODE_SAMPLE_CNT) * TSI_POLL_SAMPLE_CNT)
+
+#if DEFAULT_TSI_SAMPLING_MODE
+#define DEFAULT_REG_DATA_PROCESSING_INTERVAL \
+	TSI_FAST_MODE_REG_DATA_PROCESSING_INTERVAL
+#else
+#define DEFAULT_REG_DATA_PROCESSING_INTERVAL \
+	TSI_ECO_MODE_REG_DATA_PROCESSING_INTERVAL
+#endif
+
+#define TSI_REG_DATA_BUF_SIZE	(2 * TSI_POLL_SAMPLE_CNT)
+
+#define TSI_FAST_MODE_RAW_DATA_PROCESSING_INTERVAL	\
+	((1000 / TSI_FAST_MODE_SAMPLE_CNT) * (TSI_AVERAGE_FILTER_SIZE))
+#define TSI_ECO_MODE_RAW_DATA_PROCESSING_INTERVAL	\
+	((1000 / TSI_ECO_MODE_SAMPLE_CNT) * (TSI_AVERAGE_FILTER_SIZE))
+
+
+#if DEFAULT_TSI_SAMPLING_MODE
+#define DEFAULT_RAW_DATA_PROCESSING_INTERVAL \
+	TSI_FAST_MODE_RAW_DATA_PROCESSING_INTERVAL
+#else
+#define DEFAULT_RAW_DATA_PROCESSING_INTERVAL \
+	TSI_ECO_MODE_RAW_DATA_PROCESSING_INTERVAL
+#endif
+
+
+#define TSI_RAW_DATA_BUF_SIZE  \
+	(TSI_REG_DATA_BUF_SIZE * \
+	((TSI_AVERAGE_FILTER_SIZE / TSI_POLL_SAMPLE_CNT) + 1))
+
+#endif /* __LINUX_MFD_DA9052_TSI_CFG_H */
diff --git a/include/linux/mfd/da9052/tsi_filter.h b/include/linux/mfd/da9052/tsi_filter.h
new file mode 100644
index 00000000000..4bb7003cead
--- /dev/null
+++ b/include/linux/mfd/da9052/tsi_filter.h
@@ -0,0 +1,58 @@
+/*
+ * da9052 TSI filter module declarations.
+  *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_TSI_FILTER_H
+#define __LINUX_MFD_DA9052_TSI_FILTER_H
+
+#include <linux/mfd/da9052/tsi_cfg.h>
+#include <linux/semaphore.h>
+#include <linux/kthread.h>
+
+struct da9052_tsi_data {
+	s16	x;
+	s16	y;
+	s16	z;
+};
+
+struct da9052_tsi_raw_fifo {
+	struct semaphore	lock;
+	s32			head;
+	s32			tail;
+	struct da9052_tsi_data	data[TSI_RAW_DATA_BUF_SIZE];
+};
+
+struct tsi_thread_type {
+	u8			pid;
+	u8			state;
+	struct completion	notifier;
+	struct task_struct	*thread_task;
+} ;
+
+/* State for TSI thread */
+#define	ACTIVE		0
+#define	INACTIVE	1
+
+
+extern u32 da9052_tsi_get_input_dev(u8 off);
+
+ssize_t da9052_tsi_get_calib_display_point(struct da9052_tsi_data *displayPtr);
+
+#endif	/* __LINUX_MFD_DA9052_TSI_FILTER_H */
diff --git a/include/linux/mfd/da9052/wdt.h b/include/linux/mfd/da9052/wdt.h
new file mode 100644
index 00000000000..6a77bfc5fd9
--- /dev/null
+++ b/include/linux/mfd/da9052/wdt.h
@@ -0,0 +1,83 @@
+/*
+ * da9052 SM (watchdog) module declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_DA9052_WDT_H
+#define __LINUX_MFD_DA9052_WDT_H
+
+#include <linux/platform_device.h>
+
+/* To enable debug output for your module, set this to 1 */
+#define	DA9052_SM_DEBUG				0
+
+/* Error codes */
+#define BUS_ERR					2
+#define INIT_FAIL				3
+#define SM_OPEN_FAIL				4
+#define NO_IOCTL_CMD				5
+#define INVALID_SCALING_VALUE			6
+#define STROBING_FILTER_ERROR			7
+#define TIMER_DELETE_ERR			8
+#define STROBING_MODE_ERROR			9
+
+/* IOCTL Switch */
+/* For strobe watchdog function */
+#define DA9052_SM_IOCTL_STROBE_WDT		1
+
+/* For setting watchdog timer time */
+#define DA9052_SM_IOCTL_SET_WDT			2
+
+/* For enabling/disabling strobing filter */
+#define DA9052_SM_IOCTL_SET_STROBING_FILTER	3
+
+/* For enabling/disabling strobing filter */
+#define DA9052_SM_IOCTL_SET_STROBING_MODE	4
+
+/* Watchdog time scaling TWDMAX scaling macros */
+#define DA9052_WDT_DISABLE			0
+#define DA9052_SCALE_1X				1
+#define DA9052_SCALE_2X				2
+#define DA9052_SCALE_4X				3
+#define DA9052_SCALE_8X				4
+#define DA9052_SCALE_16X			5
+#define DA9052_SCALE_32X			6
+#define DA9052_SCALE_64X			7
+
+#define DA9052_STROBE_WIN_FILTER_PER		80
+#define DA9052_X1_WINDOW	((1 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100)
+#define DA9052_X2_WINDOW	((2 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100)
+#define DA9052_X4_WINDOW	((4 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100)
+#define DA9052_X8_WINDOW	((8 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100)
+#define DA9052_X16_WINDOW	((16 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100)
+#define DA9052_X32_WINDOW	((32 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100)
+#define DA9052_X64_WINDOW	((64 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100)
+
+#define DA9052_STROBE_AUTO			1
+#define DA9052_STROBE_MANUAL			0
+
+#define DA9052_SM_STROBE_CONF			DISABLE
+
+#define DA9052_ADC_TWDMIN_TIME			500
+
+void start_strobing(struct work_struct *work);
+/* Create a handler for the scheduling start_strobing function */
+DECLARE_WORK(strobing_action, start_strobing);
+
+#endif /* __LINUX_MFD_DA9052_WDT_H */
diff --git a/include/linux/mxc_srtc.h b/include/linux/mxc_srtc.h
new file mode 100644
index 00000000000..1d3c7b6feef
--- /dev/null
+++ b/include/linux/mxc_srtc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_srtc.h
+ *
+ * @brief SRTC IOCTL definitions
+ *
+ * @ingroup RTC
+ */
+
+
+#define RTC_READ_TIME_47BIT	_IOR('p', 0x20, unsigned long long)
+/* blocks until LPSCMR is set, returns difference */
+#define RTC_WAIT_TIME_SET	_IOR('p', 0x21, int64_t)
diff --git a/include/linux/mxc_v4l2.h b/include/linux/mxc_v4l2.h
new file mode 100644
index 00000000000..95e8d9e64c7
--- /dev/null
+++ b/include/linux/mxc_v4l2.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+/*!
+ * @file arch-mxc/mxc_v4l2.h
+ *
+ * @brief mxc V4L2 private structures
+ *
+ * @ingroup MXC_V4L2_CAPTURE
+ */
+
+#ifndef __ASM_ARCH_MXC_V4L2_H__
+#define __ASM_ARCH_MXC_V4L2_H__
+
+#define V4L2_CID_MXC_MOTION     (V4L2_CID_PRIVATE_BASE + 0)
+
+#endif
diff --git a/include/linux/mxcfb.h b/include/linux/mxcfb.h
new file mode 100644
index 00000000000..817bda95c35
--- /dev/null
+++ b/include/linux/mxcfb.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+/*
+ * @file arch-mxc/   mxcfb.h
+ *
+ * @brief Global header file for the MXC Frame buffer
+ *
+ * @ingroup Framebuffer
+ */
+#ifndef __ASM_ARCH_MXCFB_H__
+#define __ASM_ARCH_MXCFB_H__
+
+#include <linux/fb.h>
+
+#define FB_SYNC_OE_LOW_ACT	0x80000000
+#define FB_SYNC_CLK_LAT_FALL	0x40000000
+#define FB_SYNC_DATA_INVERT	0x20000000
+#define FB_SYNC_CLK_IDLE_EN	0x10000000
+#define FB_SYNC_SHARP_MODE	0x08000000
+#define FB_SYNC_SWAP_RGB	0x04000000
+#define FB_ACCEL_TRIPLE_FLAG	0x00000000
+#define FB_ACCEL_DOUBLE_FLAG	0x00000001
+
+struct mxcfb_gbl_alpha {
+	int enable;
+	int alpha;
+};
+
+struct mxcfb_loc_alpha {
+	int enable;
+	int alpha_in_pixel;
+	unsigned long alpha_phy_addr0;
+	unsigned long alpha_phy_addr1;
+};
+
+struct mxcfb_color_key {
+	int enable;
+	__u32 color_key;
+};
+
+struct mxcfb_pos {
+	__u16 x;
+	__u16 y;
+};
+
+struct mxcfb_gamma {
+	int enable;
+	int constk[16];
+	int slopek[16];
+};
+
+struct mxcfb_rect {
+	__u32 top;
+	__u32 left;
+	__u32 width;
+	__u32 height;
+};
+
+#define GRAYSCALE_8BIT				0x1
+#define GRAYSCALE_8BIT_INVERTED			0x2
+
+#define AUTO_UPDATE_MODE_REGION_MODE		0
+#define AUTO_UPDATE_MODE_AUTOMATIC_MODE		1
+
+#define UPDATE_SCHEME_SNAPSHOT			0
+#define UPDATE_SCHEME_QUEUE			1
+#define UPDATE_SCHEME_QUEUE_AND_MERGE		2
+
+#define UPDATE_MODE_PARTIAL			0x0
+#define UPDATE_MODE_FULL			0x1
+
+#define WAVEFORM_MODE_AUTO			257
+
+#define TEMP_USE_AMBIENT			0x1000
+
+#define EPDC_FLAG_ENABLE_INVERSION		0x01
+#define EPDC_FLAG_FORCE_MONOCHROME		0x02
+#define EPDC_FLAG_USE_ALT_BUFFER		0x100
+
+#define FB_POWERDOWN_DISABLE			-1
+
+struct mxcfb_alt_buffer_data {
+	__u32 phys_addr;
+	__u32 width;	/* width of entire buffer */
+	__u32 height;	/* height of entire buffer */
+	struct mxcfb_rect alt_update_region;	/* region within buffer to update */
+};
+
+struct mxcfb_update_data {
+	struct mxcfb_rect update_region;
+	__u32 waveform_mode;
+	__u32 update_mode;
+	__u32 update_marker;
+	int temp;
+	uint flags;
+	struct mxcfb_alt_buffer_data alt_buffer_data;
+};
+
+/*
+ * Structure used to define waveform modes for driver
+ * Needed for driver to perform auto-waveform selection
+ */
+struct mxcfb_waveform_modes {
+	int mode_init;
+	int mode_du;
+	int mode_gc4;
+	int mode_gc8;
+	int mode_gc16;
+	int mode_gc32;
+};
+
+#define MXCFB_WAIT_FOR_VSYNC	_IOW('F', 0x20, u_int32_t)
+#define MXCFB_SET_GBL_ALPHA     _IOW('F', 0x21, struct mxcfb_gbl_alpha)
+#define MXCFB_SET_CLR_KEY       _IOW('F', 0x22, struct mxcfb_color_key)
+#define MXCFB_SET_OVERLAY_POS   _IOWR('F', 0x24, struct mxcfb_pos)
+#define MXCFB_GET_FB_IPU_CHAN 	_IOR('F', 0x25, u_int32_t)
+#define MXCFB_SET_LOC_ALPHA     _IOWR('F', 0x26, struct mxcfb_loc_alpha)
+#define MXCFB_SET_LOC_ALP_BUF    _IOW('F', 0x27, unsigned long)
+#define MXCFB_SET_GAMMA	       _IOW('F', 0x28, struct mxcfb_gamma)
+#define MXCFB_GET_FB_IPU_DI 	_IOR('F', 0x29, u_int32_t)
+#define MXCFB_GET_DIFMT	       _IOR('F', 0x2A, u_int32_t)
+#define MXCFB_GET_FB_BLANK     _IOR('F', 0x2B, u_int32_t)
+#define MXCFB_SET_DIFMT		_IOW('F', 0x2C, u_int32_t)
+
+/* IOCTLs for E-ink panel updates */
+#define MXCFB_SET_WAVEFORM_MODES	_IOW('F', 0x2B, struct mxcfb_waveform_modes)
+#define MXCFB_SET_TEMPERATURE		_IOW('F', 0x2C, int32_t)
+#define MXCFB_SET_AUTO_UPDATE_MODE	_IOW('F', 0x2D, __u32)
+#define MXCFB_SEND_UPDATE		_IOW('F', 0x2E, struct mxcfb_update_data)
+#define MXCFB_WAIT_FOR_UPDATE_COMPLETE	_IOW('F', 0x2F, __u32)
+#define MXCFB_SET_PWRDOWN_DELAY		_IOW('F', 0x30, int32_t)
+#define MXCFB_GET_PWRDOWN_DELAY		_IOR('F', 0x31, int32_t)
+#define MXCFB_SET_UPDATE_SCHEME		_IOW('F', 0x32, __u32)
+
+#ifdef __KERNEL__
+
+extern struct fb_videomode mxcfb_modedb[];
+extern int mxcfb_modedb_sz;
+
+enum {
+	MXCFB_REFRESH_OFF,
+	MXCFB_REFRESH_AUTO,
+	MXCFB_REFRESH_PARTIAL,
+};
+
+int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode,
+			   struct mxcfb_rect *update_region);
+int mxc_elcdif_frame_addr_setup(dma_addr_t phys);
+#endif				/* __KERNEL__ */
+#endif
diff --git a/include/linux/regulator/da9052-regulator.h b/include/linux/regulator/da9052-regulator.h
new file mode 100644
index 00000000000..d09b69cb542
--- /dev/null
+++ b/include/linux/regulator/da9052-regulator.h
@@ -0,0 +1,15 @@
+/* This file is there to support additional attributes in
+ sysfs - changestate and setvoltage
+*/
+#ifndef _DA9052_REGULATOR_H
+#define _DA9052_REGULATOR_H
+
+int da9052_ldo_buck_enable(struct regulator_dev *rdev);
+int da9052_ldo_buck_disable(struct regulator_dev *rdev);
+
+
+int da9052_ldo_buck_set_voltage(struct regulator_dev *rdev,
+				int min_uV, int max_uV);
+int da9052_ldo_buck_get_voltage(struct regulator_dev *rdev);
+
+#endif
diff --git a/include/linux/usb/fsl_xcvr.h b/include/linux/usb/fsl_xcvr.h
new file mode 100644
index 00000000000..4c57e03ef2d
--- /dev/null
+++ b/include/linux/usb/fsl_xcvr.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License.  You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+#ifndef __LINUX_USB_FSL_XCVR_H
+#define __LINUX_USB_FSL_XCVR_H
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+struct fsl_usb2_platform_data;
+
+enum usb_test_mode{
+	USB_TEST_J = 1,
+	USB_TEST_K = 2,
+};
+
+/**
+ * @name: transceiver name
+ * @xcvr_type: one of PORTSC_PTS_{UTMI,SERIAL,ULPI}
+ * @init: transceiver- and board-specific initialization function
+ * @uninit: transceiver- and board-specific uninitialization function
+ * @set_host:
+ * @set_device:
+ * @pullup: enable or disable D+ pullup
+ *
+ */
+struct fsl_xcvr_ops {
+	char *name;
+	u32 xcvr_type;
+
+	void (*init)(struct fsl_xcvr_ops *ops);
+	void (*uninit)(struct fsl_xcvr_ops *ops);
+	void (*suspend)(struct fsl_xcvr_ops *ops);
+	void (*set_host)(void);
+	void (*set_device)(void);
+	void (*set_vbus_power)(struct fsl_xcvr_ops *ops,
+			       struct fsl_usb2_platform_data *pdata, int on);
+	void (*set_vbus_draw)(struct fsl_xcvr_ops *ops,
+			struct fsl_usb2_platform_data *pdata, unsigned mA);
+	void (*set_remote_wakeup)(u32 *view);
+	void (*pullup)(int on);
+	void(*set_test_mode)(u32 *view, enum usb_test_mode mode);
+};
+
+struct fsl_xcvr_power {
+	struct platform_device *usb_pdev;
+	struct regulator *regu1;
+	struct regulator *regu2;
+};
+#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index fa787d45d74..ffb1cdf7bb3 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -217,6 +217,9 @@ config SND_SOC_MAX98095
 config SND_SOC_MAX9850
 	tristate
 
+config SND_SOC_MXC_SPDIF
+       tristate
+
 config SND_SOC_PCM3008
        tristate
 
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index a2c7842e357..149845c7426 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -28,6 +28,7 @@ snd-soc-max9850-objs := max9850.o
 snd-soc-pcm3008-objs := pcm3008.o
 snd-soc-rt5631-objs := rt5631.o
 snd-soc-sgtl5000-objs := sgtl5000.o
+snd-soc-mxc-spdif-objs := mxc_spdif.o
 snd-soc-alc5623-objs := alc5623.o
 snd-soc-sn95031-objs := sn95031.o
 snd-soc-spdif-objs := spdif_transciever.o
@@ -129,6 +130,7 @@ obj-$(CONFIG_SND_SOC_MAX9850)	+= snd-soc-max9850.o
 obj-$(CONFIG_SND_SOC_PCM3008)	+= snd-soc-pcm3008.o
 obj-$(CONFIG_SND_SOC_RT5631)	+= snd-soc-rt5631.o
 obj-$(CONFIG_SND_SOC_SGTL5000)  += snd-soc-sgtl5000.o
+obj-$(CONFIG_SND_SOC_MXC_SPDIF)	+= snd-soc-mxc-spdif.o
 obj-$(CONFIG_SND_SOC_SN95031)	+=snd-soc-sn95031.o
 obj-$(CONFIG_SND_SOC_SPDIF)	+= snd-soc-spdif.o
 obj-$(CONFIG_SND_SOC_SSM2602)	+= snd-soc-ssm2602.o
diff --git a/sound/soc/codecs/mxc_spdif.c b/sound/soc/codecs/mxc_spdif.c
new file mode 100644
index 00000000000..6c33179de34
--- /dev/null
+++ b/sound/soc/codecs/mxc_spdif.c
@@ -0,0 +1,1242 @@
+/*
+ * MXC SPDIF ALSA Soc Codec Driver
+ *
+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/fsl_devices.h>
+#include <linux/io.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/asoundef.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <mach/hardware.h>
+
+#include "mxc_spdif.h"
+
+#define MXC_SPDIF_DEBUG 0
+
+static unsigned int gainsel_multi[GAINSEL_MULTI_MAX] = {
+	24 * 1024, 16 * 1024, 12 * 1024,
+	8 * 1024, 6 * 1024, 4 * 1024,
+	3 * 1024,
+};
+
+/*
+ * SPDIF control structure
+ * Defines channel status, subcode and Q sub
+ */
+struct spdif_mixer_control {
+	/* spinlock to access control data */
+	spinlock_t ctl_lock;
+	/* IEC958 channel tx status bit */
+	unsigned char ch_status[4];
+	/* User bits */
+	unsigned char subcode[2 * SPDIF_UBITS_SIZE];
+	/* Q subcode part of user bits */
+	unsigned char qsub[2 * SPDIF_QSUB_SIZE];
+	/* buffer ptrs for writer */
+	unsigned int upos;
+	unsigned int qpos;
+	/* ready buffer index of the two buffers */
+	unsigned int ready_buf;
+};
+
+struct mxc_spdif_priv {
+	struct snd_soc_codec codec;
+	struct mxc_spdif_platform_data *plat_data;
+	unsigned long __iomem *reg_base;
+	unsigned long reg_phys_base;
+	struct snd_card *card;	/* ALSA SPDIF sound card handle */
+	struct snd_pcm *pcm;	/* ALSA spdif driver type handle */
+	atomic_t dpll_locked;	/* DPLL locked status */
+};
+
+struct spdif_mixer_control mxc_spdif_control;
+
+static unsigned long spdif_base_addr;
+
+#if MXC_SPDIF_DEBUG
+static void dumpregs(void)
+{
+	unsigned int value, i;
+
+	for (i = 0 ; i <= 0x38 ; i += 4) {
+		value = readl(spdif_base_addr + i) & 0xffffff;
+		pr_debug("reg 0x%02x = 0x%06x\n", i, value);
+	}
+
+	i = 0x44;
+	value = readl(spdif_base_addr + i) & 0xffffff;
+	pr_debug("reg 0x%02x = 0x%06x\n", i, value);
+
+	i = 0x50;
+	value = readl(spdif_base_addr + i) & 0xffffff;
+	pr_debug("reg 0x%02x = 0x%06x\n", i, value);
+}
+#else
+static void dumpregs(void) {}
+#endif
+
+/* define each spdif interrupt handlers */
+typedef void (*spdif_irq_func_t) (unsigned int bit, void *desc);
+
+/* spdif irq functions declare */
+static void spdif_irq_fifo(unsigned int bit, void *devid);
+static void spdif_irq_dpll_lock(unsigned int bit, void *devid);
+static void spdif_irq_uq(unsigned int bit, void *devid);
+static void spdif_irq_bit_error(unsigned int bit, void *devid);
+static void spdif_irq_sym_error(unsigned int bit, void *devid);
+static void spdif_irq_valnogood(unsigned int bit, void *devid);
+static void spdif_irq_cnew(unsigned int bit, void *devid);
+
+/* irq function list */
+static spdif_irq_func_t spdif_irq_handlers[] = {
+	spdif_irq_fifo,
+	spdif_irq_fifo,
+	spdif_irq_dpll_lock,
+	NULL,
+	spdif_irq_fifo,
+	spdif_irq_uq,
+	spdif_irq_uq,
+	spdif_irq_uq,
+	spdif_irq_uq,
+	spdif_irq_uq,
+	spdif_irq_uq,
+	NULL,
+	NULL,
+	NULL,
+	spdif_irq_bit_error,
+	spdif_irq_sym_error,
+	spdif_irq_valnogood,
+	spdif_irq_cnew,
+	NULL,
+	spdif_irq_fifo,
+	spdif_irq_dpll_lock,
+};
+
+static void spdif_intr_enable(unsigned long intr, int enable)
+{
+	unsigned long value;
+
+	value = __raw_readl(spdif_base_addr + SPDIF_REG_SIE) & 0xffffff;
+
+	if (enable)
+		value |= intr;
+	else
+		value &= ~intr;
+
+	__raw_writel(value, spdif_base_addr + SPDIF_REG_SIE);
+}
+
+/*
+ * Get spdif interrupt status and clear the interrupt
+ */
+static int spdif_intr_status(void)
+{
+	unsigned long value;
+
+	value = __raw_readl(SPDIF_REG_SIS + spdif_base_addr) & 0xffffff;
+	value &= __raw_readl(spdif_base_addr + SPDIF_REG_SIE);
+	__raw_writel(value, SPDIF_REG_SIC + spdif_base_addr);
+
+	return value;
+}
+
+static irqreturn_t spdif_isr(int irq, void *dev_id)
+{
+	unsigned long int_stat;
+	int line;
+
+	int_stat = spdif_intr_status();
+
+	while ((line = ffs(int_stat)) != 0) {
+		int_stat &= ~(1UL << (line - 1));
+		if (spdif_irq_handlers[line - 1] != NULL)
+			spdif_irq_handlers[line - 1] (line - 1, dev_id);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Rx FIFO Full, Underrun/Overrun interrupts
+ * Tx FIFO Empty, Underrun/Overrun interrupts
+ */
+static void spdif_irq_fifo(unsigned int bit, void *devid)
+{
+	pr_debug("irq %s\n", __func__);
+}
+
+/*
+ * DPLL locked and lock loss interrupt handler
+ */
+static void spdif_irq_dpll_lock(unsigned int bit, void *devid)
+{
+	struct mxc_spdif_priv *spdif_priv = (struct mxc_spdif_priv *)devid;
+	unsigned int locked = __raw_readl(spdif_base_addr + SPDIF_REG_SRPC);
+
+	if (locked & SRPC_DPLL_LOCKED) {
+		pr_debug("SPDIF Rx dpll locked\n");
+		atomic_set(&spdif_priv->dpll_locked, 1);
+	} else {
+		/* INT_LOSS_LOCK */
+		pr_debug("SPDIF Rx dpll loss lock\n");
+		atomic_set(&spdif_priv->dpll_locked, 0);
+	}
+}
+
+/*
+ * U/Q channel related interrupts handler
+ *
+ * U/QChannel full, overrun interrupts
+ * U/QChannel sync error and frame error interrupts
+ */
+static void spdif_irq_uq(unsigned int bit, void *devid)
+{
+	unsigned long val;
+	int index;
+	struct spdif_mixer_control *ctrl = &mxc_spdif_control;
+
+	bit = 1 << bit;
+	/* get U/Q channel datas */
+	switch (bit) {
+
+	case INT_URX_OV:	/* read U data */
+		pr_debug("User bit receive overrun\n");
+	case INT_URX_FUL:
+		pr_debug("U bit receive full\n");
+
+		if (ctrl->upos >= SPDIF_UBITS_SIZE * 2) {
+			ctrl->upos = 0;
+		} else if (unlikely((ctrl->upos % SPDIF_UBITS_SIZE) + 3
+				    > SPDIF_UBITS_SIZE)) {
+			pr_err("User bit receivce buffer overflow\n");
+			break;
+		}
+		val = __raw_readl(spdif_base_addr + SPDIF_REG_SQU);
+		ctrl->subcode[ctrl->upos++] = val >> 16;
+		ctrl->subcode[ctrl->upos++] = val >> 8;
+		ctrl->subcode[ctrl->upos++] = val;
+
+		break;
+
+	case INT_QRX_OV:	/* read Q data */
+		pr_debug("Q bit receive overrun\n");
+	case INT_QRX_FUL:
+		pr_debug("Q bit receive full\n");
+
+		if (ctrl->qpos >= SPDIF_QSUB_SIZE * 2) {
+			ctrl->qpos = 0;
+		} else if (unlikely((ctrl->qpos % SPDIF_QSUB_SIZE) + 3
+				    > SPDIF_QSUB_SIZE)) {
+			pr_debug("Q bit receivce buffer overflow\n");
+			break;
+		}
+		val = __raw_readl(spdif_base_addr + SPDIF_REG_SRQ);
+		ctrl->qsub[ctrl->qpos++] = val >> 16;
+		ctrl->qsub[ctrl->qpos++] = val >> 8;
+		ctrl->qsub[ctrl->qpos++] = val;
+
+		break;
+
+	case INT_UQ_ERR:	/* read U/Q data and do buffer reset */
+		pr_debug("U/Q bit receive error\n");
+		val = __raw_readl(spdif_base_addr + SPDIF_REG_SQU);
+		val = __raw_readl(spdif_base_addr + SPDIF_REG_SRQ);
+		/* drop this U/Q buffer */
+		ctrl->ready_buf = 0;
+		ctrl->upos = 0;
+		ctrl->qpos = 0;
+		break;
+
+	case INT_UQ_SYNC:	/* U/Q buffer reset */
+		pr_debug("U/Q sync receive\n");
+
+		if (ctrl->qpos == 0)
+			break;
+		index = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE;
+		/* set ready to this buffer */
+		ctrl->ready_buf = index + 1;
+		break;
+	}
+}
+
+/*
+ * SPDIF receiver found parity bit error interrupt handler
+ */
+static void spdif_irq_bit_error(unsigned int bit, void *devid)
+{
+	pr_debug("SPDIF interrupt parity bit error\n");
+}
+
+/*
+ * SPDIF receiver found illegal symbol interrupt handler
+ */
+static void spdif_irq_sym_error(unsigned int bit, void *devid)
+{
+	pr_debug("SPDIF interrupt symbol error\n");
+}
+
+/*
+ * SPDIF validity flag no good interrupt handler
+ */
+static void spdif_irq_valnogood(unsigned int bit, void *devid)
+{
+	pr_debug("SPDIF interrupt validate is not good\n");
+}
+
+/*
+ * SPDIF receive change in value of control channel
+ */
+static void spdif_irq_cnew(unsigned int bit, void *devid)
+{
+	pr_debug("SPDIF interrupt cstatus new\n");
+}
+
+static void spdif_softreset(void)
+{
+	unsigned long value = 1;
+	int cycle = 0;
+
+	__raw_writel(SCR_SOFT_RESET, spdif_base_addr + SPDIF_REG_SCR);
+
+	while (value && (cycle++ < 10))
+		value = __raw_readl(spdif_base_addr + SPDIF_REG_SCR) & 0x1000;
+}
+
+static int spdif_set_clk_accuracy(enum spdif_clk_accuracy level)
+{
+	unsigned long value;
+
+	value = __raw_readl(SPDIF_REG_STCSCL + spdif_base_addr) & 0xffffcf;
+	value |= (level << 4);
+	__raw_writel(value, SPDIF_REG_STCSCL + spdif_base_addr);
+
+	pr_debug("STCSCL: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_STCSCL));
+
+	return 0;
+}
+
+/*
+ * set SPDIF PhaseConfig register for rx clock
+ */
+static int spdif_set_rx_clksrc(enum spdif_clk_src clksrc,
+			       enum spdif_gainsel gainsel, int dpll_locked)
+{
+	unsigned long value;
+
+	if (clksrc > SPDIF_CLK_SRC5 || gainsel > GAINSEL_MULTI_3)
+		return 1;
+
+	if (dpll_locked)
+		value = clksrc;
+	else
+		value = clksrc + SRPC_CLKSRC_SEL_LOCKED;
+
+	value = (value << SRPC_CLKSRC_SEL_OFFSET) |
+		(gainsel << SRPC_GAINSEL_OFFSET);
+
+	__raw_writel(value, spdif_base_addr + SPDIF_REG_SRPC);
+
+	return 0;
+}
+
+/*
+ * Get RX data clock rate given the SPDIF bus_clk
+ */
+static int spdif_get_rxclk_rate(struct clk *bus_clk, enum spdif_gainsel gainsel)
+{
+	unsigned long freqmeas, phaseconf, busclk_freq = 0;
+	u64 tmpval64;
+	enum spdif_clk_src clksrc;
+
+	freqmeas = __raw_readl(spdif_base_addr + SPDIF_REG_SRFM);
+	phaseconf = __raw_readl(spdif_base_addr + SPDIF_REG_SRPC);
+
+	clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0x0F;
+	if (clksrc < 5 && (phaseconf & SRPC_DPLL_LOCKED)) {
+		/* get bus clock from system */
+		busclk_freq = clk_get_rate(bus_clk);
+	}
+
+	/* FreqMeas_CLK = (BUS_CLK*FreqMeas[23:0])/2^10/GAINSEL/128 */
+	tmpval64 = (u64) busclk_freq * freqmeas;
+	do_div(tmpval64, gainsel_multi[gainsel]);
+	do_div(tmpval64, 128 * 1024);
+
+	pr_debug("FreqMeas:    %d\n", (int)freqmeas);
+	pr_debug("busclk_freq: %d\n", (int)busclk_freq);
+	pr_debug("rx rate:     %d\n", (int)tmpval64);
+
+	return (int)tmpval64;
+}
+
+static int spdif_set_sample_rate(int src_44100, int src_48000, int sample_rate)
+{
+	unsigned long cstatus, stc;
+	int ret = 0;
+
+	cstatus = __raw_readl(SPDIF_REG_STCSCL + spdif_base_addr) & 0xfffff0;
+	stc = __raw_readl(SPDIF_REG_STC + spdif_base_addr) & ~0x7FF;
+
+	switch (sample_rate) {
+	case 44100:
+		if (src_44100 < 0) {
+			pr_info("%s: no defined 44100 clk src\n", __func__);
+			ret = -1;
+		} else {
+			__raw_writel(cstatus, SPDIF_REG_STCSCL + spdif_base_addr);
+			stc |= (src_44100 << 8) | 0x07;
+			__raw_writel(stc, SPDIF_REG_STC + spdif_base_addr);
+			pr_debug("set sample rate to 44100\n");
+		}
+		break;
+	case 48000:
+		if (src_48000 < 0) {
+			pr_info("%s: no defined 48000 clk src\n", __func__);
+			ret = -1;
+		} else {
+			cstatus |= 0x04;
+			__raw_writel(cstatus, SPDIF_REG_STCSCL + spdif_base_addr);
+			stc |= (src_48000 << 8) | 0x07;
+			__raw_writel(stc, SPDIF_REG_STC + spdif_base_addr);
+			pr_debug("set sample rate to 48000\n");
+		}
+		break;
+	case 32000:
+		if (src_48000 < 0) {
+			pr_info("%s: no defined 48000 clk src\n", __func__);
+			ret = -1;
+		} else {
+			cstatus |= 0x0c;
+			__raw_writel(cstatus, SPDIF_REG_STCSCL + spdif_base_addr);
+			stc |= (src_48000 << 8) | 0x0b;
+			__raw_writel(stc, SPDIF_REG_STC + spdif_base_addr);
+			pr_debug("set sample rate to 32000\n");
+		}
+		break;
+	}
+
+	pr_debug("STCSCL: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_STCSCL));
+
+	return ret;
+}
+
+static int spdif_set_channel_status(int value, unsigned long reg)
+{
+	__raw_writel(value & 0xffffff, reg + spdif_base_addr);
+
+	return 0;
+}
+
+static unsigned int spdif_playback_rates[] = { 32000, 44100, 48000 };
+
+static unsigned int spdif_capture_rates[] = {
+	16000, 32000, 44100, 48000, 64000, 96000
+};
+
+static struct snd_pcm_hw_constraint_list hw_playback_rates_stereo = {
+	.count = ARRAY_SIZE(spdif_playback_rates),
+	.list = spdif_playback_rates,
+	.mask = 0,
+};
+
+static struct snd_pcm_hw_constraint_list hw_capture_rates_stereo = {
+	.count = ARRAY_SIZE(spdif_capture_rates),
+	.list = spdif_capture_rates,
+	.mask = 0,
+};
+
+static int mxc_spdif_playback_startup(struct snd_pcm_substream *substream,
+					       struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec);
+	struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data;
+	int err;
+
+	if (!plat_data->spdif_tx)
+		return -EINVAL;
+
+	clk_enable(plat_data->spdif_clk);
+	clk_enable(plat_data->spdif_audio_clk);
+
+	err = snd_pcm_hw_constraint_list(runtime, 0,
+					 SNDRV_PCM_HW_PARAM_RATE,
+					 &hw_playback_rates_stereo);
+	if (err < 0)
+		goto failed;
+	err = snd_pcm_hw_constraint_integer(runtime,
+					    SNDRV_PCM_HW_PARAM_PERIODS);
+	if (err < 0)
+		goto failed;
+
+	return 0;
+failed:
+	clk_disable(plat_data->spdif_clk);
+	return err;
+}
+
+static int mxc_spdif_playback_prepare(struct snd_pcm_substream *substream,
+					  struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec);
+	struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	unsigned int ch_status;
+	unsigned long regval;
+	int err;
+
+	if (!plat_data->spdif_tx)
+		return -EINVAL;
+
+	regval = __raw_readl(spdif_base_addr + SPDIF_REG_SCR);
+	regval &= 0xfc33e3;
+	regval &= ~SCR_LOW_POWER;
+	regval |= SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_NORMAL |
+	    SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | (2 << SCR_TXFIFO_ESEL_BIT);
+	__raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr);
+
+	/* Default clock source from EXTAL, divider by 8, generate 44.1kHz
+	   sample rate */
+	__raw_writel(0x07, SPDIF_REG_STC + spdif_base_addr);
+
+	ch_status = ((mxc_spdif_control.ch_status[2] << 16) |
+		     (mxc_spdif_control.ch_status[1] << 8) |
+		     mxc_spdif_control.ch_status[0]);
+	spdif_set_channel_status(ch_status, SPDIF_REG_STCSCH);
+	ch_status = mxc_spdif_control.ch_status[3];
+	spdif_set_channel_status(ch_status, SPDIF_REG_STCSCL);
+	spdif_intr_enable(INT_TXFIFO_RESYNC, 1);
+	err = spdif_set_sample_rate(plat_data->spdif_clk_44100,
+				    plat_data->spdif_clk_48000,
+				    runtime->rate);
+	if (err < 0) {
+		pr_info("%s - err < 0\n", __func__);
+		return err;
+	}
+	spdif_set_clk_accuracy(SPDIF_CLK_ACCURACY_LEV2);
+
+	pr_debug("SCR: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SCR));
+	pr_debug("SIE: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIE));
+	pr_debug("STC: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_STC));
+
+	pr_debug("STCSCH: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_STCSCH));
+	pr_debug("STCSCL: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_STCSCL));
+
+	regval = __raw_readl(SPDIF_REG_SCR + spdif_base_addr);
+	regval |= SCR_DMA_TX_EN;
+	__raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr);
+
+	dumpregs();
+	return 0;
+}
+
+static int mxc_spdif_playback_shutdown(struct snd_pcm_substream *substream,
+						struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec);
+	struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data;
+	unsigned long regval;
+
+	if (!plat_data->spdif_tx)
+		return -EINVAL;
+
+	dumpregs();
+	pr_debug("SIS: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIS));
+
+	spdif_intr_status();
+	spdif_intr_enable(INT_TXFIFO_RESYNC, 0);
+
+	regval = __raw_readl(SPDIF_REG_SCR + spdif_base_addr) & 0xffffe3;
+	regval |= SCR_TXSEL_OFF;
+	__raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr);
+	regval = __raw_readl(SPDIF_REG_STC + spdif_base_addr) & ~0x7FF;
+	regval |= (0x7 << STC_TXCLK_SRC_OFFSET);
+	__raw_writel(regval, SPDIF_REG_STC + spdif_base_addr);
+
+	regval = __raw_readl(SPDIF_REG_SCR + spdif_base_addr);
+	regval &= ~SCR_DMA_TX_EN;
+	regval |= SCR_LOW_POWER;
+	__raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr);
+
+	clk_disable(plat_data->spdif_audio_clk);
+	clk_disable(plat_data->spdif_clk);
+
+	return 0;
+}
+
+static int mxc_spdif_capture_startup(struct snd_pcm_substream *substream,
+					      struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data;
+	int err = 0;
+
+	if (!plat_data->spdif_rx)
+		return -EINVAL;
+
+	/* enable rx bus clock */
+	clk_enable(plat_data->spdif_clk);
+
+	/* set hw param constraints */
+	err = snd_pcm_hw_constraint_list(runtime, 0,
+					 SNDRV_PCM_HW_PARAM_RATE,
+					 &hw_capture_rates_stereo);
+	if (err < 0)
+		goto failed;
+
+	err = snd_pcm_hw_constraint_integer(runtime,
+					    SNDRV_PCM_HW_PARAM_PERIODS);
+	if (err < 0)
+		goto failed;
+
+	/* enable spdif dpll lock interrupt */
+	spdif_intr_enable(INT_DPLL_LOCKED, 1);
+
+	return 0;
+
+failed:
+	clk_disable(plat_data->spdif_clk);
+	return err;
+}
+
+static int mxc_spdif_capture_prepare(struct snd_pcm_substream *substream,
+					 struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec);
+	struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data;
+	unsigned long regval;
+
+	if (!plat_data->spdif_rx)
+		return -EINVAL;
+
+	regval = __raw_readl(spdif_base_addr + SPDIF_REG_SCR);
+	/*
+	 * initial and reset SPDIF configuration:
+	 * RxFIFO off
+	 * RxFIFO sel to 8 sample
+	 * Autosync
+	 * Valid bit set
+	 */
+	regval &= ~(SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO | SCR_LOW_POWER);
+	regval |= (2 << SCR_RXFIFO_FSEL_BIT) | SCR_RXFIFO_AUTOSYNC;
+	__raw_writel(regval, spdif_base_addr + SPDIF_REG_SCR);
+
+	/* enable interrupts, include DPLL lock */
+	spdif_intr_enable(INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |
+			  INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |
+			  INT_UQ_SYNC | INT_UQ_ERR | INT_RX_RESYNC |
+			  INT_LOSS_LOCK, 1);
+
+	/* setup rx clock source */
+	spdif_set_rx_clksrc(plat_data->spdif_clkid, SPDIF_DEFAULT_GAINSEL, 1);
+
+	regval = __raw_readl(SPDIF_REG_SCR + spdif_base_addr);
+	regval |= SCR_DMA_RX_EN;
+	__raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr);
+
+	/* Debug: dump registers */
+	pr_debug("SCR: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SCR));
+	pr_debug("SIE: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIE));
+	pr_debug("SRPC: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SRPC));
+	pr_debug("FreqMeas: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SRFM));
+
+	return 0;
+}
+
+static int mxc_spdif_capture_shutdown(struct snd_pcm_substream *substream,
+					       struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec);
+	struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data;
+	unsigned long regval;
+
+	if (!plat_data->spdif_rx)
+		return -EINVAL;
+
+	pr_debug("SIS: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIS));
+	pr_debug("SRPC: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SRPC));
+	pr_debug("FreqMeas: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SRFM));
+
+	spdif_intr_enable(INT_DPLL_LOCKED | INT_SYM_ERR | INT_BIT_ERR |
+			  INT_URX_FUL | INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |
+			  INT_UQ_SYNC | INT_UQ_ERR | INT_RX_RESYNC |
+			  INT_LOSS_LOCK, 0);
+
+	regval = __raw_readl(SPDIF_REG_SCR + spdif_base_addr);
+	regval &= SCR_DMA_RX_EN;
+	__raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr);
+
+	/* turn off RX fifo, disable dma and autosync */
+	regval = __raw_readl(spdif_base_addr + SPDIF_REG_SCR);
+	regval |= SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO | SCR_LOW_POWER;
+	regval &= ~(SCR_DMA_RX_EN | SCR_RXFIFO_AUTOSYNC);
+	__raw_writel(regval, spdif_base_addr + SPDIF_REG_SCR);
+
+	clk_disable(plat_data->spdif_clk);
+
+	return 0;
+}
+
+/*
+ * MXC SPDIF IEC958 controller(mixer) functions
+ *
+ *	Channel status get/put control
+ *	User bit value get/put control
+ *	Valid bit value get control
+ *	DPLL lock status get control
+ *	User bit sync mode selection control
+ */
+static int mxc_pb_spdif_info(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+	uinfo->count = 1;
+	return 0;
+}
+
+static int mxc_pb_spdif_get(struct snd_kcontrol *kcontrol,
+			    struct snd_ctl_elem_value *uvalue)
+{
+	uvalue->value.iec958.status[0] = mxc_spdif_control.ch_status[0];
+	uvalue->value.iec958.status[1] = mxc_spdif_control.ch_status[1];
+	uvalue->value.iec958.status[2] = mxc_spdif_control.ch_status[2];
+	uvalue->value.iec958.status[3] = mxc_spdif_control.ch_status[3];
+	return 0;
+}
+
+static int mxc_pb_spdif_put(struct snd_kcontrol *kcontrol,
+			    struct snd_ctl_elem_value *uvalue)
+{
+	unsigned int ch_status;
+	mxc_spdif_control.ch_status[0] = uvalue->value.iec958.status[0];
+	mxc_spdif_control.ch_status[1] = uvalue->value.iec958.status[1];
+	mxc_spdif_control.ch_status[2] = uvalue->value.iec958.status[2];
+	mxc_spdif_control.ch_status[3] = uvalue->value.iec958.status[3];
+	ch_status =
+	    ((mxc_spdif_control.ch_status[2] << 16) |
+	     (mxc_spdif_control.ch_status[1] << 8) |
+	     mxc_spdif_control.ch_status[0]);
+	spdif_set_channel_status(ch_status, SPDIF_REG_STCSCH);
+	ch_status = mxc_spdif_control.ch_status[3];
+	spdif_set_channel_status(ch_status, SPDIF_REG_STCSCL);
+
+	pr_debug("STCSCH: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_STCSCH));
+	pr_debug("STCSCL: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_STCSCL));
+
+	return 0;
+}
+
+static int mxc_spdif_info(struct snd_kcontrol *kcontrol,
+			  struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+	uinfo->count = 1;
+	return 0;
+}
+
+/*
+ * Get channel status from SPDIF_RX_CCHAN register
+ */
+static int mxc_spdif_capture_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned int cstatus;
+
+	if (!(__raw_readl(spdif_base_addr + SPDIF_REG_SIS) & INT_CNEW))
+		return -EAGAIN;
+
+	cstatus = __raw_readl(spdif_base_addr + SPDIF_REG_SRCSLH);
+	ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
+	ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
+	ucontrol->value.iec958.status[2] = cstatus & 0xFF;
+	cstatus = __raw_readl(spdif_base_addr + SPDIF_REG_SRCSLL);
+	ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
+	ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
+	ucontrol->value.iec958.status[5] = cstatus & 0xFF;
+
+	/* clear intr */
+	__raw_writel(INT_CNEW, spdif_base_addr + SPDIF_REG_SIC);
+
+	return 0;
+}
+
+/*
+ * Get User bits (subcode) from chip value which readed out
+ * in UChannel register.
+ */
+static int mxc_spdif_subcode_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned long flags;
+	int ret = 0;
+
+	spin_lock_irqsave(&mxc_spdif_control.ctl_lock, flags);
+	if (mxc_spdif_control.ready_buf) {
+		memcpy(&ucontrol->value.iec958.subcode[0],
+		       &mxc_spdif_control.subcode[(mxc_spdif_control.ready_buf -
+						   1) * SPDIF_UBITS_SIZE],
+		       SPDIF_UBITS_SIZE);
+	} else {
+		ret = -EAGAIN;
+	}
+	spin_unlock_irqrestore(&mxc_spdif_control.ctl_lock, flags);
+
+	return ret;
+}
+
+/*
+ * Q-subcode infomation.
+ * the byte size is SPDIF_UBITS_SIZE/8
+ */
+static int mxc_spdif_qinfo(struct snd_kcontrol *kcontrol,
+			   struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
+	uinfo->count = SPDIF_QSUB_SIZE;
+	return 0;
+}
+
+/*
+ * Get Q subcode from chip value which readed out
+ * in QChannel register.
+ */
+static int mxc_spdif_qget(struct snd_kcontrol *kcontrol,
+			  struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned long flags;
+	int ret = 0;
+
+	spin_lock_irqsave(&mxc_spdif_control.ctl_lock, flags);
+	if (mxc_spdif_control.ready_buf) {
+		memcpy(&ucontrol->value.bytes.data[0],
+		       &mxc_spdif_control.qsub[(mxc_spdif_control.ready_buf -
+						1) * SPDIF_QSUB_SIZE],
+		       SPDIF_QSUB_SIZE);
+	} else {
+		ret = -EAGAIN;
+	}
+	spin_unlock_irqrestore(&mxc_spdif_control.ctl_lock, flags);
+
+	return ret;
+}
+
+/*
+ * Valid bit infomation.
+ */
+static int mxc_spdif_vbit_info(struct snd_kcontrol *kcontrol,
+			       struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = 1;
+	return 0;
+}
+
+/*
+ * Get valid good bit from interrupt status register.
+ */
+static int mxc_spdif_vbit_get(struct snd_kcontrol *kcontrol,
+			      struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned int int_val;
+
+	int_val = __raw_readl(spdif_base_addr + SPDIF_REG_SIS);
+	ucontrol->value.integer.value[0] = (int_val & INT_VAL_NOGOOD) != 0;
+	__raw_writel(INT_VAL_NOGOOD, spdif_base_addr + SPDIF_REG_SIC);
+
+	return 0;
+}
+
+/*
+ * DPLL lock infomation.
+ */
+static int mxc_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 16000;
+	uinfo->value.integer.max = 96000;
+	return 0;
+}
+
+/*
+ * Get DPLL lock or not info from stable interrupt status register.
+ * User application must use this control to get locked,
+ * then can do next PCM operation
+ */
+static int mxc_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+	struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec);
+
+	struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data;
+
+	if (atomic_read(&spdif_priv->dpll_locked)) {
+		ucontrol->value.integer.value[0] =
+		    spdif_get_rxclk_rate(plat_data->spdif_clk,
+					 SPDIF_DEFAULT_GAINSEL);
+	} else {
+		ucontrol->value.integer.value[0] = 0;
+	}
+	return 0;
+}
+
+/*
+ * User bit sync mode info
+ */
+static int mxc_spdif_usync_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = 1;
+	return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int mxc_spdif_usync_get(struct snd_kcontrol *kcontrol,
+			       struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned int int_val;
+	int_val = __raw_readl(spdif_base_addr + SPDIF_REG_SRCD);
+	ucontrol->value.integer.value[0] = (int_val & SRCD_CD_USER) != 0;
+	return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int mxc_spdif_usync_put(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned int int_val;
+
+	int_val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
+	__raw_writel(int_val, spdif_base_addr + SPDIF_REG_SRCD);
+	return 0;
+}
+
+/*
+ * MXC SPDIF IEC958 controller defines
+ */
+static struct snd_kcontrol_new mxc_spdif_ctrls[] = {
+	/* status cchanel controller */
+	{
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
+	 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE |
+	 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+	 .info = mxc_pb_spdif_info,
+	 .get = mxc_pb_spdif_get,
+	 .put = mxc_pb_spdif_put,
+	 },
+	{
+	 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+	 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
+	 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+	 .info = mxc_spdif_info,
+	 .get = mxc_spdif_capture_get,
+	 },
+	/* user bits controller */
+	{
+	 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+	 .name = "IEC958 Subcode Capture Default",
+	 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+	 .info = mxc_spdif_info,
+	 .get = mxc_spdif_subcode_get,
+	 },
+	{
+	 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+	 .name = "IEC958 Q-subcode Capture Default",
+	 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+	 .info = mxc_spdif_qinfo,
+	 .get = mxc_spdif_qget,
+	 },
+	/* valid bit error controller */
+	{
+	 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+	 .name = "IEC958 V-Bit Errors",
+	 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+	 .info = mxc_spdif_vbit_info,
+	 .get = mxc_spdif_vbit_get,
+	 },
+	/* DPLL lock info get controller */
+	{
+	 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+	 .name = "RX Sample Rate",
+	 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+	 .info = mxc_spdif_rxrate_info,
+	 .get = mxc_spdif_rxrate_get,
+	 },
+	/* User bit sync mode set/get controller */
+	{
+	 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+	 .name = "IEC958 USyncMode CDText",
+	 .access =
+	 SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE |
+	 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+	 .info = mxc_spdif_usync_info,
+	 .get = mxc_spdif_usync_get,
+	 .put = mxc_spdif_usync_put,
+	 },
+};
+
+static int mxc_spdif_startup(struct snd_pcm_substream *substream,
+			     struct snd_soc_dai *dai)
+{
+	int ret;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		ret = mxc_spdif_playback_startup(substream, dai);
+	else
+		ret = mxc_spdif_capture_startup(substream, dai);
+
+	return ret;
+}
+
+static void mxc_spdif_shutdown(struct snd_pcm_substream *substream,
+			       struct snd_soc_dai *dai)
+{
+	int ret;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		ret = mxc_spdif_playback_shutdown(substream, dai);
+	else
+		ret = mxc_spdif_capture_shutdown(substream, dai);
+}
+
+static int mxc_spdif_prepare(struct snd_pcm_substream *substream,
+			     struct snd_soc_dai *dai)
+{
+	int ret;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		ret = mxc_spdif_playback_prepare(substream, dai);
+	else
+		ret = mxc_spdif_capture_prepare(substream, dai);
+
+	return ret;
+}
+
+struct snd_soc_dai_ops mxc_spdif_codec_dai_ops = {
+	.startup = mxc_spdif_startup,
+	.prepare = mxc_spdif_prepare,
+	.shutdown = mxc_spdif_shutdown,
+};
+
+struct snd_soc_dai_driver mxc_spdif_codec_dai = {
+	.name = "mxc-spdif",
+	.ops = &mxc_spdif_codec_dai_ops,
+};
+
+static int mxc_spdif_soc_probe(struct snd_soc_codec *codec)
+{
+	snd_soc_add_controls(codec, mxc_spdif_ctrls,
+			     ARRAY_SIZE(mxc_spdif_ctrls));
+	return 0;
+}
+
+static int mxc_spdif_soc_remove(struct snd_soc_codec *codec)
+{
+	/* all done in mxc_spdif_remove */
+	return 0;
+}
+
+struct snd_soc_codec_driver soc_codec_dev_spdif = {
+	.probe = mxc_spdif_soc_probe,
+	.remove = mxc_spdif_soc_remove,
+};
+
+static int __devinit mxc_spdif_probe(struct platform_device *pdev)
+{
+	struct mxc_spdif_platform_data *plat_data =
+	    (struct mxc_spdif_platform_data *)pdev->dev.platform_data;
+	struct resource *res;
+	struct mxc_spdif_priv *spdif_priv;
+	int err, irq;
+	int ret = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENOENT;
+
+	dev_info(&pdev->dev, "MXC SPDIF Audio\n");
+
+	spdif_priv = kzalloc(sizeof(struct mxc_spdif_priv), GFP_KERNEL);
+	if (spdif_priv == NULL)
+		return -ENOMEM;
+
+	if (plat_data->spdif_tx) {
+		mxc_spdif_codec_dai.playback.stream_name = "Playback";
+		mxc_spdif_codec_dai.playback.channels_min = 2;
+		mxc_spdif_codec_dai.playback.channels_max = 2;
+
+		if (plat_data->spdif_clk_44100 >= 0)
+			mxc_spdif_codec_dai.playback.rates |= SNDRV_PCM_RATE_44100;
+		if (plat_data->spdif_clk_48000 >= 0)
+			mxc_spdif_codec_dai.playback.rates |= SNDRV_PCM_RATE_32000 |
+							      SNDRV_PCM_RATE_48000;
+
+		mxc_spdif_codec_dai.playback.formats = MXC_SPDIF_FORMATS_PLAYBACK;
+	}
+
+	if (plat_data->spdif_rx) {
+		mxc_spdif_codec_dai.capture.stream_name = "Capture";
+		mxc_spdif_codec_dai.capture.channels_min = 2;
+		mxc_spdif_codec_dai.capture.channels_max = 2;
+
+		/* rx clock is recovered from audio stream, so it is not
+		   dependent on tx clocks available */
+		mxc_spdif_codec_dai.capture.rates = MXC_SPDIF_RATES_CAPTURE;
+
+		mxc_spdif_codec_dai.capture.formats = MXC_SPDIF_FORMATS_CAPTURE;
+	}
+
+	platform_set_drvdata(pdev, spdif_priv);
+
+	spdif_priv->reg_phys_base = res->start;
+	spdif_priv->reg_base = ioremap(res->start, res->end - res->start + 1);
+	spdif_priv->plat_data = plat_data;
+
+	spdif_base_addr = (unsigned long)spdif_priv->reg_base;
+
+	/* initial spinlock for control data */
+	spin_lock_init(&mxc_spdif_control.ctl_lock);
+
+	if (plat_data->spdif_tx) {
+		/* init tx channel status default value */
+		mxc_spdif_control.ch_status[0] =
+		    IEC958_AES0_CON_NOT_COPYRIGHT |
+		    IEC958_AES0_CON_EMPHASIS_5015;
+		mxc_spdif_control.ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
+		mxc_spdif_control.ch_status[2] = 0x00;
+		mxc_spdif_control.ch_status[3] =
+		    IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
+	}
+
+	plat_data->spdif_clk = clk_get(&pdev->dev, NULL);
+
+	atomic_set(&spdif_priv->dpll_locked, 0);
+
+	/* spdif_xtal_clk */
+	clk_enable(plat_data->spdif_core_clk);
+	spdif_softreset();
+
+	/* disable all the interrupts */
+	spdif_intr_enable(0xffffff, 0);
+
+	/* spdif interrupt register and disable */
+	irq = platform_get_irq(pdev, 0);
+	if ((irq <= 0) || request_irq(irq, spdif_isr, 0, "spdif", spdif_priv)) {
+		pr_err("MXC spdif: failed to request irq\n");
+		err = -EBUSY;
+		goto card_err;
+	}
+
+	ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_spdif,
+				     &mxc_spdif_codec_dai, 1);
+
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register codec\n");
+		goto card_err;
+	}
+
+	dumpregs();
+
+	return 0;
+
+card_err:
+	clk_disable(plat_data->spdif_clk);
+	clk_put(plat_data->spdif_clk);
+	clk_disable(plat_data->spdif_core_clk);
+
+	platform_set_drvdata(pdev, NULL);
+	kfree(spdif_priv);
+
+	return ret;
+}
+
+static int __devexit mxc_spdif_remove(struct platform_device *pdev)
+{
+	struct mxc_spdif_priv *spdif_priv = platform_get_drvdata(pdev);
+	struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data;
+
+	snd_soc_unregister_codec(&pdev->dev);
+
+	clk_disable(plat_data->spdif_clk);
+	clk_put(plat_data->spdif_clk);
+	clk_disable(plat_data->spdif_core_clk);
+
+	platform_set_drvdata(pdev, NULL);
+	kfree(spdif_priv);
+
+	return 0;
+}
+
+struct platform_driver mxc_spdif_driver = {
+	.driver = {
+		   .name = "mxc_spdif",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = mxc_spdif_probe,
+	.remove = __devexit_p(mxc_spdif_remove),
+};
+
+static int __init mxc_spdif_init(void)
+{
+	return platform_driver_register(&mxc_spdif_driver);
+}
+
+static void __exit mxc_spdif_exit(void)
+{
+	return platform_driver_unregister(&mxc_spdif_driver);
+}
+
+module_init(mxc_spdif_init);
+module_exit(mxc_spdif_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC SPDIF transmitter");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/mxc_spdif.h b/sound/soc/codecs/mxc_spdif.h
new file mode 100644
index 00000000000..7eb98352d4d
--- /dev/null
+++ b/sound/soc/codecs/mxc_spdif.h
@@ -0,0 +1,164 @@
+/*
+ * ALSA SoC MXC SPDIF codec driver
+ *
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * Based on stmp3xxx_spdif.h by:
+ * Vladimir Barinov <vbarinov@embeddedalley.com>
+ *
+ * Copyright 2008 SigmaTel, Inc
+ * Copyright 2008 Embedded Alley Solutions, Inc
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program  is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef __MXC_SPDIF_CODEC_H
+#define __MXC_SPDIF_CODEC_H
+
+#define SPDIF_REG_SCR		0x00
+#define SPDIF_REG_SRCD		0x04
+#define SPDIF_REG_SRPC		0x08
+#define SPDIF_REG_SIE		0x0C
+#define SPDIF_REG_SIS		0x10
+#define SPDIF_REG_SIC		0x10
+#define SPDIF_REG_SRL		0x14
+#define SPDIF_REG_SRR		0x18
+#define SPDIF_REG_SRCSLH	0x1C
+#define SPDIF_REG_SRCSLL	0x20
+#define SPDIF_REG_SQU		0x24
+#define SPDIF_REG_SRQ		0x28
+#define SPDIF_REG_STL		0x2C
+#define SPDIF_REG_STR		0x30
+#define SPDIF_REG_STCSCH	0x34
+#define SPDIF_REG_STCSCL	0x38
+#define SPDIF_REG_SRFM		0x44
+#define SPDIF_REG_STC		0x50
+
+/* SPDIF Configuration register */
+#define SCR_RXFIFO_CTL_ZERO	(1 << 23)
+#define SCR_RXFIFO_OFF		(1 << 22)
+#define SCR_RXFIFO_RST		(1 << 21)
+#define SCR_RXFIFO_FSEL_BIT	(19)
+#define SCR_RXFIFO_FSEL_MASK	(0x3 << SCR_RXFIFO_FSEL_BIT)
+#define SCR_RXFIFO_AUTOSYNC	(1 << 18)
+#define SCR_TXFIFO_AUTOSYNC	(1 << 17)
+#define SCR_TXFIFO_ESEL_BIT	(15)
+#define SCR_TXFIFO_ESEL_MASK	(0x3 << SCR_TXFIFO_FSEL_BIT)
+#define SCR_LOW_POWER		(1 << 13)
+#define SCR_SOFT_RESET		(1 << 12)
+#define SCR_TXFIFO_ZERO		(0 << 10)
+#define SCR_TXFIFO_NORMAL	(1 << 10)
+#define SCR_TXFIFO_ONESAMPLE	(1 << 11)
+#define SCR_DMA_RX_EN		(1 << 9)
+#define SCR_DMA_TX_EN		(1 << 8)
+#define SCR_VAL_CLEAR		(1 << 5)
+#define SCR_TXSEL_OFF		(0 << 2)
+#define SCR_TXSEL_RX		(1 << 2)
+#define SCR_TXSEL_NORMAL	(0x5 << 2)
+#define SCR_USRC_SEL_NONE	(0x0)
+#define SCR_USRC_SEL_RECV	(0x1)
+#define SCR_USRC_SEL_CHIP	(0x3)
+
+/* SPDIF CDText control */
+#define SRCD_CD_USER_OFFSET	1
+#define SRCD_CD_USER		(1 << SRCD_CD_USER_OFFSET)
+
+/* SPDIF Phase Configuration register */
+#define SRPC_DPLL_LOCKED	(1 << 6)
+#define SRPC_CLKSRC_SEL_OFFSET	7
+#define SRPC_CLKSRC_SEL_LOCKED	5
+/* gain sel */
+#define SRPC_GAINSEL_OFFSET	3
+
+enum spdif_gainsel {
+	GAINSEL_MULTI_24 = 0,
+	GAINSEL_MULTI_16,
+	GAINSEL_MULTI_12,
+	GAINSEL_MULTI_8,
+	GAINSEL_MULTI_6,
+	GAINSEL_MULTI_4,
+	GAINSEL_MULTI_3,
+	GAINSEL_MULTI_MAX,
+};
+
+#define SPDIF_DEFAULT_GAINSEL	GAINSEL_MULTI_8
+
+/* SPDIF interrupt mask define */
+#define INT_DPLL_LOCKED		(1 << 20)
+#define INT_TXFIFO_UNOV		(1 << 19)
+#define INT_TXFIFO_RESYNC	(1 << 18)
+#define INT_CNEW		(1 << 17)
+#define INT_VAL_NOGOOD		(1 << 16)
+#define INT_SYM_ERR		(1 << 15)
+#define INT_BIT_ERR		(1 << 14)
+#define INT_URX_FUL		(1 << 10)
+#define INT_URX_OV		(1 << 9)
+#define INT_QRX_FUL		(1 << 8)
+#define INT_QRX_OV		(1 << 7)
+#define INT_UQ_SYNC		(1 << 6)
+#define INT_UQ_ERR		(1 << 5)
+#define INT_RX_UNOV		(1 << 4)
+#define INT_RX_RESYNC		(1 << 3)
+#define INT_LOSS_LOCK		(1 << 2)
+#define INT_TX_EMPTY		(1 << 1)
+#define INT_RXFIFO_FUL		(1 << 0)
+
+/* SPDIF Clock register */
+#define STC_SYSCLK_DIV_OFFSET	11
+#define STC_TXCLK_SRC_OFFSET	8
+#define STC_TXCLK_DIV_OFFSET	0
+
+#define SPDIF_CSTATUS_BYTE	6
+#define SPDIF_UBITS_SIZE	96
+#define SPDIF_QSUB_SIZE		(SPDIF_UBITS_SIZE/8)
+
+enum spdif_clk_accuracy {
+	SPDIF_CLK_ACCURACY_LEV2 = 0,
+	SPDIF_CLK_ACCURACY_LEV1 = 2,
+	SPDIF_CLK_ACCURACY_LEV3 = 1,
+	SPDIF_CLK_ACCURACY_RESV = 3
+};
+
+/* SPDIF clock source */
+enum spdif_clk_src {
+	SPDIF_CLK_SRC1 = 0,
+	SPDIF_CLK_SRC2,
+	SPDIF_CLK_SRC3,
+	SPDIF_CLK_SRC4,
+	SPDIF_CLK_SRC5,
+};
+
+enum spdif_max_wdl {
+	SPDIF_MAX_WDL_20,
+	SPDIF_MAX_WDL_24
+};
+
+enum spdif_wdl {
+	SPDIF_WDL_DEFAULT = 0,
+	SPDIF_WDL_FIFTH = 4,
+	SPDIF_WDL_FOURTH = 3,
+	SPDIF_WDL_THIRD = 2,
+	SPDIF_WDL_SECOND = 1,
+	SPDIF_WDL_MAX = 5
+};
+
+#define MXC_SPDIF_RATES_PLAYBACK	(SNDRV_PCM_RATE_32000 |	\
+					 SNDRV_PCM_RATE_44100 |	\
+					 SNDRV_PCM_RATE_48000)
+
+#define MXC_SPDIF_RATES_CAPTURE		(SNDRV_PCM_RATE_16000 | \
+					 SNDRV_PCM_RATE_32000 |	\
+					 SNDRV_PCM_RATE_44100 | \
+					 SNDRV_PCM_RATE_48000 |	\
+					 SNDRV_PCM_RATE_64000 | \
+					 SNDRV_PCM_RATE_96000)
+
+#define MXC_SPDIF_FORMATS_PLAYBACK	(SNDRV_PCM_FMTBIT_S16_LE | \
+					 SNDRV_PCM_FMTBIT_S20_3LE | \
+					 SNDRV_PCM_FMTBIT_S24_LE)
+
+#define MXC_SPDIF_FORMATS_CAPTURE	(SNDRV_PCM_FMTBIT_S24_LE)
+
+#endif /* __MXC_SPDIF_CODEC_H */
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index bbcf921166f..cb9818c5830 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -131,13 +131,20 @@ static int mic_bias_event(struct snd_soc_dapm_widget *w,
 	case SND_SOC_DAPM_POST_PMU:
 		/* change mic bias resistor to 4Kohm */
 		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
-				SGTL5000_BIAS_R_MASK,
-				SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
+			SGTL5000_BIAS_R_MASK,
+			SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
+
+		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
+			SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
 		break;
 
 	case SND_SOC_DAPM_PRE_PMD:
 		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
-				SGTL5000_BIAS_R_MASK, 0);
+			SGTL5000_BIAS_R_MASK,
+			SGTL5000_BIAS_R_off << SGTL5000_BIAS_R_SHIFT);
+
+		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
+			SGTL5000_VAG_POWERUP, 0);
 		break;
 	}
 	return 0;
@@ -180,16 +187,16 @@ SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
 static const struct snd_kcontrol_new adc_mux =
 SOC_DAPM_ENUM("Capture Mux", adc_enum);
 
-/* input sources for DAC */
-static const char *dac_mux_text[] = {
+/* input sources for Headphone */
+static const char *hp_mux_text[] = {
 	"DAC", "LINE_IN"
 };
 
-static const struct soc_enum dac_enum =
-SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
+static const struct soc_enum hp_mux_enum =
+SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, hp_mux_text);
 
-static const struct snd_kcontrol_new dac_mux =
-SOC_DAPM_ENUM("Headphone Mux", dac_enum);
+static const struct snd_kcontrol_new hp_mux =
+SOC_DAPM_ENUM("Headphone Mux", hp_mux_enum);
 
 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
 	SND_SOC_DAPM_INPUT("LINE_IN"),
@@ -198,7 +205,7 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
 	SND_SOC_DAPM_OUTPUT("HP_OUT"),
 	SND_SOC_DAPM_OUTPUT("LINE_OUT"),
 
-	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
+	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SND_SOC_NOPM, 0, 0,
 				mic_bias_event,
 				SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 
@@ -210,7 +217,7 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
 			SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
 
 	SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
-	SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
+	SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &hp_mux),
 
 	/* aif for i2s input */
 	SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
@@ -230,7 +237,8 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
 /* routes for sgtl5000 */
 static const struct snd_soc_dapm_route audio_map[] = {
 	{"Capture Mux", "LINE_IN", "LINE_IN"},	/* line_in --> adc_mux */
-	{"Capture Mux", "MIC_IN", "MIC_IN"},	/* mic_in --> adc_mux */
+	{"Mic Bias", NULL, "MIC_IN"},		/* mic_in --> mic bias */
+	{"Capture Mux", "MIC_IN", "Mic Bias"},	/* mic bias --> adc_mux */
 
 	{"ADC", NULL, "Capture Mux"},		/* adc_mux --> adc */
 	{"AIFOUT", NULL, "ADC"},		/* adc --> i2s_out */
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index 738391757f2..7ffeed2d351 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -17,6 +17,9 @@ config SND_MXC_SOC_FIQ
 config SND_MXC_SOC_MX2
 	tristate
 
+config SND_MXC_SOC_SPDIF_DAI
+	tristate
+
 config SND_MXC_SOC_WM1133_EV1
 	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
 	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
@@ -44,6 +47,17 @@ config SND_SOC_PHYCORE_AC97
 	  Say Y if you want to add support for SoC audio on Phytec phyCORE
 	  and phyCARD boards in AC97 mode
 
+config SND_SOC_IMX_SGTL5000
+	tristate "SoC Audio support for i.MX boards with sgtl5000"
+	depends on MACH_MX35_3DS || MACH_MX51_BABBAGE || MACH_MX53_LOCO
+	select SND_SOC_SGTL5000
+	select SND_MXC_SOC_MX2
+	help
+	  Say Y if you want to add support for SoC audio
+	  on an i.MX board with a sgtl5000 codec, Say N
+	  if you don't make sure that the sgtl5000 is
+	  supported or not.
+
 config SND_SOC_EUKREA_TLV320
 	tristate "Eukrea TLV320"
 	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
@@ -57,4 +71,14 @@ config SND_SOC_EUKREA_TLV320
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
 
+config SND_SOC_IMX_SPDIF
+	tristate "SoC Audio support for IMX - S/PDIF"
+	default n
+	select SND_MXC_SOC_SPDIF_DAI
+	select SND_SOC_MXC_SPDIF
+	select SND_MXC_SOC_MX2
+	help
+	  Say Y if you want to add support for SoC audio on a IMX development
+	  board with S/PDIF.
+
 endif	# SND_IMX_SOC
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
index d6d609ba7e2..d5a04757d62 100644
--- a/sound/soc/imx/Makefile
+++ b/sound/soc/imx/Makefile
@@ -2,18 +2,24 @@
 snd-soc-imx-objs := imx-ssi.o
 snd-soc-imx-fiq-objs := imx-pcm-fiq.o
 snd-soc-imx-mx2-objs := imx-pcm-dma-mx2.o
+snd-soc-imx-spdif-dai-objs := imx-spdif-dai.o
 
 obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o
 obj-$(CONFIG_SND_MXC_SOC_FIQ) += snd-soc-imx-fiq.o
 obj-$(CONFIG_SND_MXC_SOC_MX2) += snd-soc-imx-mx2.o
+obj-$(CONFIG_SND_MXC_SOC_SPDIF_DAI) += snd-soc-imx-spdif-dai.o
 
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
 snd-soc-phycore-ac97-objs := phycore-ac97.o
 snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
 snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
+snd-soc-imx-spdif-objs := imx-spdif.o
 
 obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
 obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
 obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
 obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
+obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
+obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/imx/imx-pcm-dma-mx2.c
index 43fdc24f7e8..27d250944a0 100644
--- a/sound/soc/imx/imx-pcm-dma-mx2.c
+++ b/sound/soc/imx/imx-pcm-dma-mx2.c
@@ -83,7 +83,7 @@ static int imx_ssi_dma_alloc(struct snd_pcm_substream *substream,
 
 	dma_params = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
 
-	iprtd->dma_data.peripheral_type = IMX_DMATYPE_SSI;
+	iprtd->dma_data.peripheral_type = dma_params->peripheral_type;
 	iprtd->dma_data.priority = DMA_PRIO_HIGH;
 	iprtd->dma_data.dma_request = dma_params->dma;
 
diff --git a/sound/soc/imx/imx-sgtl5000.c b/sound/soc/imx/imx-sgtl5000.c
new file mode 100644
index 00000000000..0ff8ee00b3c
--- /dev/null
+++ b/sound/soc/imx/imx-sgtl5000.c
@@ -0,0 +1,396 @@
+/*
+ * sound/soc/imx/3ds-sgtl5000.c --  SoC audio for i.MX 3ds boards with
+ *                                  sgtl5000 codec
+ *
+ * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/fsl_devices.h>
+#include <linux/gpio.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include <sound/soc-dapm.h>
+#include <asm/mach-types.h>
+#include <mach/audmux.h>
+
+#include "../codecs/sgtl5000.h"
+#include "imx-ssi.h"
+
+static struct imx_sgtl5000_priv {
+	int sysclk;
+	int hw;
+	struct platform_device *pdev;
+} card_priv;
+
+static struct snd_soc_jack hs_jack;
+static struct snd_soc_card imx_sgtl5000;
+
+/* Headphones jack detection DAPM pins */
+static struct snd_soc_jack_pin hs_jack_pins[] = {
+	{
+		.pin = "Headphone Jack",
+		.mask = SND_JACK_HEADPHONE,
+	},
+};
+
+/* Headphones jack detection gpios */
+static struct snd_soc_jack_gpio hs_jack_gpios[] = {
+	[0] = {
+		/* gpio is set on per-platform basis */
+		.name           = "hp-gpio",
+		.report         = SND_JACK_HEADPHONE,
+		.debounce_time	= 200,
+	},
+};
+
+static int sgtl5000_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	u32 dai_format;
+	int ret;
+	unsigned int channels = params_channels(params);
+
+	snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, card_priv.sysclk, 0);
+
+	snd_soc_dai_set_sysclk(codec_dai, SGTL5000_LRCLK, params_rate(params), 0);
+
+	dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+		SND_SOC_DAIFMT_CBM_CFM;
+
+	/* set codec DAI configuration */
+	ret = snd_soc_dai_set_fmt(codec_dai, dai_format);
+	if (ret < 0)
+		return ret;
+
+
+	/* TODO: The SSI driver should figure this out for us */
+	switch (channels) {
+	case 2:
+		snd_soc_dai_set_tdm_slot(cpu_dai, 0xfffffffc, 0xfffffffc, 2, 0);
+		break;
+	case 1:
+		snd_soc_dai_set_tdm_slot(cpu_dai, 0xfffffffe, 0xfffffffe, 1, 0);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* set cpu DAI configuration */
+	dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |
+		SND_SOC_DAIFMT_CBM_CFM;
+	ret = snd_soc_dai_set_fmt(cpu_dai, dai_format);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static struct snd_soc_ops imx_sgtl5000_hifi_ops = {
+	.hw_params = sgtl5000_params,
+};
+
+static int sgtl5000_jack_func;
+static int sgtl5000_spk_func;
+static int sgtl5000_line_in_func;
+
+static const char *jack_function[] = { "off", "on"};
+
+static const char *spk_function[] = { "off", "on" };
+
+static const char *line_in_function[] = { "off", "on" };
+
+static const struct soc_enum sgtl5000_enum[] = {
+	SOC_ENUM_SINGLE_EXT(2, jack_function),
+	SOC_ENUM_SINGLE_EXT(2, spk_function),
+	SOC_ENUM_SINGLE_EXT(2, line_in_function),
+};
+
+static int sgtl5000_get_jack(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.enumerated.item[0] = sgtl5000_jack_func;
+	return 0;
+}
+
+static int sgtl5000_set_jack(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+	if (sgtl5000_jack_func == ucontrol->value.enumerated.item[0])
+		return 0;
+
+	sgtl5000_jack_func = ucontrol->value.enumerated.item[0];
+	if (sgtl5000_jack_func)
+		snd_soc_dapm_enable_pin(&codec->dapm, "Headphone Jack");
+	else
+		snd_soc_dapm_disable_pin(&codec->dapm, "Headphone Jack");
+
+	snd_soc_dapm_sync(&codec->dapm);
+	return 1;
+}
+
+static int sgtl5000_get_spk(struct snd_kcontrol *kcontrol,
+			    struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.enumerated.item[0] = sgtl5000_spk_func;
+	return 0;
+}
+
+static int sgtl5000_set_spk(struct snd_kcontrol *kcontrol,
+			    struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+	if (sgtl5000_spk_func == ucontrol->value.enumerated.item[0])
+		return 0;
+
+	sgtl5000_spk_func = ucontrol->value.enumerated.item[0];
+	if (sgtl5000_spk_func)
+		snd_soc_dapm_enable_pin(&codec->dapm, "Ext Spk");
+	else
+		snd_soc_dapm_disable_pin(&codec->dapm, "Ext Spk");
+
+	snd_soc_dapm_sync(&codec->dapm);
+	return 1;
+}
+
+static int sgtl5000_get_line_in(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.enumerated.item[0] = sgtl5000_line_in_func;
+	return 0;
+}
+
+static int sgtl5000_set_line_in(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+	if (sgtl5000_line_in_func == ucontrol->value.enumerated.item[0])
+		return 0;
+
+	sgtl5000_line_in_func = ucontrol->value.enumerated.item[0];
+	if (sgtl5000_line_in_func)
+		snd_soc_dapm_enable_pin(&codec->dapm, "Line In Jack");
+	else
+		snd_soc_dapm_disable_pin(&codec->dapm, "Line In Jack");
+
+	snd_soc_dapm_sync(&codec->dapm);
+	return 1;
+}
+
+/* imx_3stack card dapm widgets */
+static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets[] = {
+	SND_SOC_DAPM_MIC("Mic Jack", NULL),
+	SND_SOC_DAPM_LINE("Line In Jack", NULL),
+	SND_SOC_DAPM_SPK("Ext Spk", NULL),
+	SND_SOC_DAPM_HP("Headphone Jack", NULL),
+};
+
+static const struct snd_kcontrol_new sgtl5000_machine_controls[] = {
+	SOC_ENUM_EXT("Jack Function", sgtl5000_enum[0], sgtl5000_get_jack,
+		     sgtl5000_set_jack),
+	SOC_ENUM_EXT("Speaker Function", sgtl5000_enum[1], sgtl5000_get_spk,
+		     sgtl5000_set_spk),
+	SOC_ENUM_EXT("Line In Function", sgtl5000_enum[1], sgtl5000_get_line_in,
+		     sgtl5000_set_line_in),
+};
+
+/* imx_3stack machine connections to the codec pins */
+static const struct snd_soc_dapm_route audio_map[] = {
+
+	/* Mic Jack --> MIC_IN (with automatic bias) */
+	{"MIC_IN", NULL, "Mic Jack"},
+
+	/* Line in Jack --> LINE_IN */
+	{"LINE_IN", NULL, "Line In Jack"},
+
+	/* HP_OUT --> Headphone Jack */
+	{"Headphone Jack", NULL, "HP_OUT"},
+
+	/* LINE_OUT --> Ext Speaker */
+	{"Ext Spk", NULL, "LINE_OUT"},
+};
+
+static int imx_3stack_sgtl5000_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct snd_soc_codec *codec = rtd->codec;
+	int ret;
+
+	ret = snd_soc_add_controls(codec, sgtl5000_machine_controls,
+			ARRAY_SIZE(sgtl5000_machine_controls));
+	if (ret)
+		return ret;
+
+	/* Add imx_3stack specific widgets */
+	snd_soc_dapm_new_controls(&codec->dapm, imx_3stack_dapm_widgets,
+				  ARRAY_SIZE(imx_3stack_dapm_widgets));
+
+	/* Set up imx_3stack specific audio path audio_map */
+	snd_soc_dapm_add_routes(&codec->dapm, audio_map, ARRAY_SIZE(audio_map));
+
+	snd_soc_dapm_disable_pin(&codec->dapm, "Line In Jack");
+	snd_soc_dapm_enable_pin(&codec->dapm, "Headphone Jack");
+	snd_soc_dapm_sync(&codec->dapm);
+
+	/* Jack detection API stuff */
+	ret = snd_soc_jack_new(codec, "Headphone Jack",
+			       SND_JACK_HEADPHONE, &hs_jack);
+	if (ret)
+		return ret;
+
+	ret = snd_soc_jack_add_pins(&hs_jack, ARRAY_SIZE(hs_jack_pins),
+				hs_jack_pins);
+	if (ret) {
+		printk(KERN_ERR "failed to call  snd_soc_jack_add_pins\n");
+		return ret;
+	}
+
+	ret = snd_soc_jack_add_gpios(&hs_jack, ARRAY_SIZE(hs_jack_gpios),
+				hs_jack_gpios);
+	if (ret)
+		printk(KERN_WARNING "failed to call snd_soc_jack_add_gpios\n");
+
+	return 0;
+}
+
+static struct snd_soc_dai_link imx_sgtl5000_dai[] = {
+	{
+		.name		= "HiFi",
+		.stream_name	= "HiFi",
+		.codec_dai_name	= "sgtl5000",
+		.codec_name	= "sgtl5000.1-000a",
+		.cpu_dai_name	= "imx-ssi.1",
+		.platform_name	= "imx-pcm-audio.1",
+		.init		= imx_3stack_sgtl5000_init,
+		.ops		= &imx_sgtl5000_hifi_ops,
+	},
+};
+
+static struct snd_soc_card imx_sgtl5000 = {
+	.name		= "sgtl5000-audio",
+	.dai_link	= imx_sgtl5000_dai,
+	.num_links	= ARRAY_SIZE(imx_sgtl5000_dai),
+};
+
+static struct platform_device *imx_sgtl5000_snd_device;
+
+static int imx_audmux_config(int slave, int master)
+{
+	unsigned int ptcr, pdcr;
+	slave = slave - 1;
+	master = master - 1;
+
+	/* SSI0 mastered by port 5 */
+	ptcr = MXC_AUDMUX_V2_PTCR_SYN |
+		MXC_AUDMUX_V2_PTCR_TFSDIR |
+		MXC_AUDMUX_V2_PTCR_TFSEL(master) |
+		MXC_AUDMUX_V2_PTCR_TCLKDIR |
+		MXC_AUDMUX_V2_PTCR_TCSEL(master);
+	pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);
+	mxc_audmux_v2_configure_port(slave, ptcr, pdcr);
+
+	ptcr = MXC_AUDMUX_V2_PTCR_SYN;
+	pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(slave);
+	mxc_audmux_v2_configure_port(master, ptcr, pdcr);
+
+	return 0;
+}
+
+static int __devinit imx_sgtl5000_probe(struct platform_device *pdev)
+{
+	struct mxc_audio_platform_data *plat = pdev->dev.platform_data;
+
+	int ret = 0;
+
+	card_priv.pdev = pdev;
+
+	imx_audmux_config(plat->src_port, plat->ext_port);
+
+	ret = -EINVAL;
+	if (plat->init && plat->init())
+		return ret;
+
+	card_priv.sysclk = plat->sysclk;
+
+	hs_jack_gpios[0].gpio = plat->hp_gpio;
+	hs_jack_gpios[0].invert = plat->hp_active_low;
+
+	return 0;
+}
+
+static int imx_sgtl5000_remove(struct platform_device *pdev)
+{
+	struct mxc_audio_platform_data *plat = pdev->dev.platform_data;
+
+	if (plat->finit)
+		plat->finit();
+
+	return 0;
+}
+
+static struct platform_driver imx_sgtl5000_audio_driver = {
+	.probe = imx_sgtl5000_probe,
+	.remove = imx_sgtl5000_remove,
+	.driver = {
+		   .name = "imx-sgtl5000",
+		   },
+};
+
+static int __init imx_sgtl5000_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&imx_sgtl5000_audio_driver);
+	if (ret)
+		return -ENOMEM;
+
+	if (machine_is_mx35_3ds())
+		imx_sgtl5000_dai[0].codec_name = "sgtl5000.0-000a";
+	else
+		imx_sgtl5000_dai[0].codec_name = "sgtl5000.1-000a";
+
+	imx_sgtl5000_snd_device = platform_device_alloc("soc-audio", -1);
+	if (!imx_sgtl5000_snd_device)
+		return -ENOMEM;
+
+	platform_set_drvdata(imx_sgtl5000_snd_device, &imx_sgtl5000);
+
+	ret = platform_device_add(imx_sgtl5000_snd_device);
+
+	if (ret) {
+		printk(KERN_ERR "ASoC: Platform device allocation failed\n");
+		platform_device_put(imx_sgtl5000_snd_device);
+	}
+
+	return ret;
+}
+
+static void __exit imx_sgtl5000_exit(void)
+{
+	platform_driver_unregister(&imx_sgtl5000_audio_driver);
+	platform_device_unregister(imx_sgtl5000_snd_device);
+}
+
+module_init(imx_sgtl5000_init);
+module_exit(imx_sgtl5000_exit);
+
+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+MODULE_DESCRIPTION("PhyCORE ALSA SoC driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/imx/imx-spdif-dai.c b/sound/soc/imx/imx-spdif-dai.c
new file mode 100644
index 00000000000..a3b38658c6f
--- /dev/null
+++ b/sound/soc/imx/imx-spdif-dai.c
@@ -0,0 +1,137 @@
+/*
+ * ALSA SoC SPDIF Audio Layer for MXS
+ *
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * Based on stmp3xxx_spdif_dai.c
+ * Vladimir Barinov <vbarinov@embeddedalley.com>
+ * Copyright 2008 SigmaTel, Inc
+ * Copyright 2008 Embedded Alley Solutions, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program  is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <mach/dma.h>
+#include <mach/hardware.h>
+
+#include "../codecs/mxc_spdif.h"
+
+#define MXC_SPDIF_TXFIFO_WML      0x8
+#define MXC_SPDIF_RXFIFO_WML      0x8
+
+struct imx_pcm_dma_params dma_params_tx;
+struct imx_pcm_dma_params dma_params_rx;
+
+static int imx_spdif_hw_params(struct snd_pcm_substream *substream,
+			       struct snd_pcm_hw_params *params,
+			       struct snd_soc_dai *cpu_dai)
+{
+	/* Tx/Rx config */
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		snd_soc_dai_set_dma_data(cpu_dai, substream, &dma_params_tx);
+	else
+		snd_soc_dai_set_dma_data(cpu_dai, substream, &dma_params_rx);
+
+	return 0;
+}
+
+struct snd_soc_dai_ops imx_spdif_dai_ops = {
+	.hw_params      = imx_spdif_hw_params,
+};
+
+struct snd_soc_dai_driver imx_spdif_dai = {
+	.playback = {
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = MXC_SPDIF_RATES_PLAYBACK,
+		.formats = MXC_SPDIF_FORMATS_PLAYBACK,
+	},
+	.capture = {
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = MXC_SPDIF_RATES_CAPTURE,
+		.formats = MXC_SPDIF_FORMATS_CAPTURE,
+	},
+	.ops = &imx_spdif_dai_ops,
+};
+
+static int imx_spdif_dai_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret = 0;
+
+	dma_params_tx.burstsize = MXC_SPDIF_TXFIFO_WML;
+	dma_params_rx.burstsize = MXC_SPDIF_RXFIFO_WML;
+
+	dma_params_tx.peripheral_type = IMX_DMATYPE_SPDIF;
+	dma_params_rx.peripheral_type = IMX_DMATYPE_SPDIF;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
+	if (res)
+		dma_params_tx.dma = res->start;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
+	if (res)
+		dma_params_rx.dma = res->start;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx_reg");
+	if (res)
+		dma_params_tx.dma_addr = res->start;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx_reg");
+	if (res)
+		dma_params_rx.dma_addr = res->start;
+
+	ret = snd_soc_register_dai(&pdev->dev, &imx_spdif_dai);
+	if (ret) {
+		dev_err(&pdev->dev, "register DAI failed\n");
+		goto failed_register;
+	}
+
+	return 0;
+
+failed_register:
+	return ret;
+}
+
+static int __devexit imx_spdif_dai_remove(struct platform_device *pdev)
+{
+	snd_soc_unregister_dai(&pdev->dev);
+	return 0;
+}
+
+static struct platform_driver imx_ssi_driver = {
+	.probe = imx_spdif_dai_probe,
+	.remove = __devexit_p(imx_spdif_dai_remove),
+
+	.driver = {
+		.name = "imx-spdif-dai",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init imx_spdif_dai_init(void)
+{
+	return platform_driver_register(&imx_ssi_driver);
+}
+
+static void __exit imx_spdif_dai_exit(void)
+{
+	platform_driver_unregister(&imx_ssi_driver);
+}
+module_init(imx_spdif_dai_init);
+module_exit(imx_spdif_dai_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("IMX SPDIF DAI");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/imx/imx-spdif.c b/sound/soc/imx/imx-spdif.c
new file mode 100644
index 00000000000..f336545f921
--- /dev/null
+++ b/sound/soc/imx/imx-spdif.c
@@ -0,0 +1,144 @@
+/*
+ * ASoC S/PDIF driver for IMX development boards
+ *
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * based on stmp3780_devb_spdif.c
+ *
+ * Vladimir Barinov <vbarinov@embeddedalley.com>
+ *
+ * Copyright 2008 SigmaTel, Inc
+ * Copyright 2008 Embedded Alley Solutions, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program  is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+#include <asm/mach-types.h>
+#include <asm/dma.h>
+#include <mach/hardware.h>
+
+#include "imx-ssi.h"
+#include "../codecs/mxc_spdif.h"
+
+/* imx digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link imx_spdif_dai_link = {
+	.name = "IMX SPDIF",
+	.stream_name = "IMX SPDIF",
+	.codec_dai_name = "mxc-spdif",
+	.codec_name = "mxc_spdif.0",
+	.cpu_dai_name = "imx-spdif-dai.0",
+	.platform_name = "imx-pcm-audio.2", /* imx-pcm-dma-mx2 */
+};
+
+static struct snd_soc_card snd_soc_card_imx_spdif = {
+	.name = "imx-spdif",
+	.dai_link = &imx_spdif_dai_link,
+	.num_links = 1,
+};
+
+static int __devinit imx_spdif_audio_probe(struct platform_device *pdev)
+{
+	struct imx_ssi *ssi;
+	int ret;
+
+	ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
+	if (!ssi)
+		return -ENOMEM;
+
+	dev_set_drvdata(&pdev->dev, ssi);
+
+	ssi->soc_platform_pdev = platform_device_alloc("imx-pcm-audio", 2);
+	if (!ssi->soc_platform_pdev) {
+		pr_err("%s failed platform_device_alloc\n", __func__);
+		return -ENOMEM;
+	}
+
+	/* It may seem weird to be using struct imx_ssi here because S/PDIF
+	   doesn't use ssi.  We only use soc_platform_pdev in struct imx_ssi.
+	   But we need it because imx-pcm-dma-mx2 initializes other fields. */
+	platform_set_drvdata(ssi->soc_platform_pdev, ssi);
+
+	ret = platform_device_add(ssi->soc_platform_pdev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to add platform device\n");
+		platform_device_put(ssi->soc_platform_pdev);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devexit imx_spdif_audio_remove(struct platform_device *pdev)
+{
+	struct imx_ssi *ssi = platform_get_drvdata(pdev);
+
+	platform_device_unregister(ssi->soc_platform_pdev);
+	snd_soc_unregister_dai(&pdev->dev);
+	kfree(ssi);
+
+	return 0;
+}
+
+static struct platform_driver imx_spdif_audio_driver = {
+	.probe = imx_spdif_audio_probe,
+	.remove = __devexit_p(imx_spdif_audio_remove),
+	.driver = {
+		   .name = "imx-spdif-audio-device",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static struct platform_device *imx_spdif_snd_device;
+
+static int __init imx_spdif_init(void)
+{
+	int ret = 0;
+
+	ret = platform_driver_register(&imx_spdif_audio_driver);
+	if (ret) {
+		pr_err("%s - failed platform_driver_register\n", __func__);
+		return -ENOMEM;
+	}
+
+	imx_spdif_snd_device = platform_device_alloc("soc-audio", 1);
+	if (!imx_spdif_snd_device) {
+		pr_err("%s - failed platform_device_alloc\n", __func__);
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(imx_spdif_snd_device, &snd_soc_card_imx_spdif);
+
+	ret = platform_device_add(imx_spdif_snd_device);
+	if (ret) {
+		pr_err("ASoC S/PDIF: Platform device allocation failed\n");
+		platform_device_put(imx_spdif_snd_device);
+	}
+
+	return ret;
+}
+
+static void __exit imx_spdif_exit(void)
+{
+	platform_driver_unregister(&imx_spdif_audio_driver);
+	platform_device_unregister(imx_spdif_snd_device);
+}
+
+module_init(imx_spdif_init);
+module_exit(imx_spdif_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("IMX EVK development board ASoC driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c
index 4c05e2b8f4d..563d197e37d 100644
--- a/sound/soc/imx/imx-ssi.c
+++ b/sound/soc/imx/imx-ssi.c
@@ -89,14 +89,13 @@ static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
 	u32 strcr = 0, scr;
 
-	scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
+	scr = readl(ssi->base + SSI_SCR) & ~SSI_SCR_SYN;
 
 	/* DAI mode */
 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 	case SND_SOC_DAIFMT_I2S:
 		/* data on rising edge of bclk, frame low 1clk before data */
 		strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
-		scr |= SSI_SCR_NET;
 		if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
 			scr &= ~SSI_I2S_MODE_MASK;
 			scr |= SSI_SCR_I2S_MODE_SLAVE;
@@ -145,8 +144,6 @@ static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 
 	strcr |= SSI_STCR_TFEN0;
 
-	if (ssi->flags & IMX_SSI_NET)
-		scr |= SSI_SCR_NET;
 	if (ssi->flags & IMX_SSI_SYN)
 		scr |= SSI_SCR_SYN;
 
@@ -243,7 +240,8 @@ static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
 {
 	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
 	struct imx_pcm_dma_params *dma_data;
-	u32 reg, sccr;
+	u32 reg, sccr, scr;
+	unsigned int channels = params_channels(params);
 
 	/* Tx/Rx config */
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
@@ -276,6 +274,14 @@ static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
 
 	writel(sccr, ssi->base + reg);
 
+	scr = readl(ssi->base + SSI_SCR);
+
+	if (channels == 1)
+		scr &= ~SSI_SCR_NET;
+	else
+		scr |= SSI_SCR_NET;
+
+	writel(scr, ssi->base + SSI_SCR);
 	return 0;
 }
 
@@ -391,6 +397,9 @@ static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
 int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_card *card = rtd->card->snd_card;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+
 	struct snd_pcm *pcm = rtd->pcm;
 	int ret = 0;
 
@@ -398,14 +407,17 @@ int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
 		card->dev->dma_mask = &imx_pcm_dmamask;
 	if (!card->dev->coherent_dma_mask)
 		card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
-	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
+
+	if (cpu_dai->driver->playback.channels_min &&
+	    codec_dai->driver->playback.channels_min) {
 		ret = imx_pcm_preallocate_dma_buffer(pcm,
 			SNDRV_PCM_STREAM_PLAYBACK);
 		if (ret)
 			goto out;
 	}
 
-	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
+	if (cpu_dai->driver->capture.channels_min &&
+	    codec_dai->driver->capture.channels_min) {
 		ret = imx_pcm_preallocate_dma_buffer(pcm,
 			SNDRV_PCM_STREAM_CAPTURE);
 		if (ret)
@@ -658,6 +670,8 @@ static int imx_ssi_probe(struct platform_device *pdev)
 
 	ssi->dma_params_tx.burstsize = 4;
 	ssi->dma_params_rx.burstsize = 4;
+	ssi->dma_params_tx.peripheral_type = IMX_DMATYPE_SSI_SP;
+	ssi->dma_params_rx.peripheral_type = IMX_DMATYPE_SSI_SP;
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
 	if (res)
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/imx/imx-ssi.h
index 1072dfb53e4..cee624e64b0 100644
--- a/sound/soc/imx/imx-ssi.h
+++ b/sound/soc/imx/imx-ssi.h
@@ -188,12 +188,6 @@
 #include <linux/dmaengine.h>
 #include <mach/dma.h>
 
-struct imx_pcm_dma_params {
-	int dma;
-	unsigned long dma_addr;
-	int burstsize;
-};
-
 struct imx_ssi {
 	struct platform_device *ac97_dev;